From: David Bauer <mail@david-bauer.net>
Date: Thu, 7 Dec 2023 20:50:25 +0000 (+0100)
Subject: pci
X-Git-Url: http://git.openwrt.org/?a=commitdiff_plain;h=a5ef75e6d776a61c48571163f502131389e6a5fc;p=openwrt%2Fstaging%2Fblocktrron.git

pci
---

diff --git a/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch b/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch
index 5e343d01cc..1df9cce51a 100644
--- a/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch
+++ b/target/linux/mediatek/patches-6.1/611-pcie-mediatek-gen3-PERST-for-100ms.patch
@@ -1,17 +1,18 @@
 --- a/drivers/pci/controller/pcie-mediatek-gen3.c
 +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
-@@ -350,7 +350,13 @@ static int mtk_pcie_startup_port(struct
- 	msleep(100);
+@@ -390,9 +390,14 @@ static int mtk_pcie_startup_port(struct
+ 	 * The deassertion of PERST# should be delayed 100ms (TPVPERL)
+ 	 * for the power and clock to become stable.
+ 	 */
+-	msleep(100);
++	msleep(300);
  
  	/* De-assert reset signals */
--	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
 +	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB);
-+	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
++	writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
 +
-+	msleep(100);
++	msleep(300);
 +
-+	/* De-assert PERST# signals */
-+	val &= ~(PCIE_PE_RSTB);
- 	writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);
+ 	val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB);
+ 	writel_relaxed(val, port->base + PCIE_RST_CTRL_REG);
  
- 	/* Check if the link is up or not */