From: Shiji Yang <yangshiji66@qq.com>
Date: Sat, 20 May 2023 12:35:51 +0000 (+0800)
Subject: ath79: improve support for D-Link DIR-8x9 A1 series
X-Git-Url: http://git.openwrt.org/?a=commitdiff_plain;h=e5d8739aa846db621b6368ba83db17c353a35dea;p=openwrt%2Fstaging%2Fxback.git

ath79: improve support for D-Link DIR-8x9 A1 series

1. Remove unnecessary new lines in the dts.
2. Remove duplicate included file "gpio.h" in the device dts.
3. Add missing button labels "reset" and "wps".
4. Unify the format of the reg properties.
5. Add u-boot environment support.
6. Reduce spi clock frequency since the max value suggested by the
   chip datasheet is only 25 MHz.
7. Add seama header fixup for DIR-859 A1. Without this header fixup,
   u-boot checksum for kernel will fail after the first boot.

Signed-off-by: Shiji Yang <yangshiji66@qq.com>
---

diff --git a/package/boot/uboot-envtools/files/ath79 b/package/boot/uboot-envtools/files/ath79
index 47271453f6..38fc663e70 100644
--- a/package/boot/uboot-envtools/files/ath79
+++ b/package/boot/uboot-envtools/files/ath79
@@ -27,6 +27,8 @@ araknis,an-700-ap-i-ac|\
 arduino,yun|\
 buffalo,bhr-4grv2|\
 devolo,magic-2-wifi|\
+dlink,dir-859-a1|\
+dlink,dir-869-a1|\
 engenius,eap1200h|\
 engenius,eap1750h|\
 engenius,eap300-v2|\
diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts b/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts
index a828f86cb1..93bd8e363e 100644
--- a/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-859-a1.dts
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
 #include "qca9563_dlink_dir-8x9-a1.dtsi"
-#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "D-Link DIR-859 A1";
diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-869-a1.dts b/target/linux/ath79/dts/qca9563_dlink_dir-869-a1.dts
index eab713ea66..5afe683613 100644
--- a/target/linux/ath79/dts/qca9563_dlink_dir-869-a1.dts
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-869-a1.dts
@@ -1,7 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
 #include "qca9563_dlink_dir-8x9-a1.dtsi"
-#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "D-Link DIR-869 A1";
@@ -28,4 +27,3 @@
 		};
 	};
 };
-
diff --git a/target/linux/ath79/dts/qca9563_dlink_dir-8x9-a1.dtsi b/target/linux/ath79/dts/qca9563_dlink_dir-8x9-a1.dtsi
index 556ba604a6..754fcd415d 100644
--- a/target/linux/ath79/dts/qca9563_dlink_dir-8x9-a1.dtsi
+++ b/target/linux/ath79/dts/qca9563_dlink_dir-8x9-a1.dtsi
@@ -6,17 +6,18 @@
 #include <dt-bindings/input/input.h>
 
 / {
-
 	keys {
 		compatible = "gpio-keys";
 
 		wps {
+			label = "wps";
 			linux,code = <KEY_WPS_BUTTON>;
 			gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
 			debounce-interval = <60>;
 		};
 
 		reset {
+			label = "reset";
 			linux,code = <KEY_RESTART>;
 			gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
 			debounce-interval = <60>;
@@ -42,7 +43,7 @@
 	flash@0 {
 		compatible = "jedec,spi-nor";
 		reg = <0>;
-		spi-max-frequency = <50000000>;
+		spi-max-frequency = <25000000>;
 
 		partitions {
 			compatible = "fixed-partitions";
@@ -51,19 +52,19 @@
 
 			partition@0 {
 				label = "bootloader";
-				reg = <0x000000 0x40000>;
+				reg = <0x000000 0x040000>;
 				read-only;
 			};
 
 			partition@40000 {
+				compatible = "u-boot,env";
 				label = "bdcfg";
-				reg = <0x040000 0x10000>;
-				read-only;
+				reg = <0x040000 0x010000>;
 			};
 
 			partition@50000 {
 				label = "devdata";
-				reg = <0x050000 0x10000>;
+				reg = <0x050000 0x010000>;
 				read-only;
 
 				compatible = "nvmem-cells";
@@ -81,7 +82,7 @@
 
 			partition@60000 {
 				label = "devconf";
-				reg = <0x060000 0x10000>;
+				reg = <0x060000 0x010000>;
 				read-only;
 			};
 
diff --git a/target/linux/ath79/generic/base-files/etc/uci-defaults/09_fix-checksum b/target/linux/ath79/generic/base-files/etc/uci-defaults/09_fix-checksum
index 7f4d6cf428..ad3db95a0c 100644
--- a/target/linux/ath79/generic/base-files/etc/uci-defaults/09_fix-checksum
+++ b/target/linux/ath79/generic/base-files/etc/uci-defaults/09_fix-checksum
@@ -22,6 +22,7 @@ dlink,dap-3662-a1)
 	fixwrgg
 	;;
 dlink,dir-629-a1|\
+dlink,dir-859-a1|\
 dlink,dir-869-a1|\
 qihoo,c301)
 	fix_seama_header