project/bcm63xx/atf.git
5 years agodoc: Make checkpatch ignore rst files
Paul Beesley [Thu, 7 Mar 2019 16:42:31 +0000 (16:42 +0000)]
doc: Make checkpatch ignore rst files

Previously checkpatch was invoked with options to make it ignore
Markdown (md) files as this was the dominant format for TF-A
documents. Now that rst is being used everywhere this option needs
updating.

Change-Id: I59b5a0bcc45d2386df4f880b8d333baef0bbee77
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agodoc: Format security advisory titles and headings
Paul Beesley [Thu, 7 Mar 2019 16:22:44 +0000 (16:22 +0000)]
doc: Format security advisory titles and headings

Required so that the advisory documents are all valid RST files (with a
header) and that they all integrate into the document tree.

Change-Id: I68ca2b0b9e648e24b460deb772c471a38518da26
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agodoc: Reformat platform port documents
Paul Beesley [Wed, 22 May 2019 10:22:44 +0000 (11:22 +0100)]
doc: Reformat platform port documents

The platform port documents are not very standardised right now and
they don't integrate properly into the document tree so:

1) Make sure each port has a proper name and title (incl. owner)
2) Correct use of headings, subheadings, etc in each port
3) Resolve any naming conflicts between documents

Change-Id: I4c2da6f57172b7f2af3512e766ae9ce3b840b50f
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agodoc: Normalise section numbering and headings
Paul Beesley [Thu, 7 Mar 2019 15:53:44 +0000 (15:53 +0000)]
doc: Normalise section numbering and headings

Required work to make all documents sit at the correct levels within
the document tree and any derived content like the table of contents
and the categories in the sidebar.

Change-Id: I4885fbe30864a87c8822ee67482b71fb46a8fbc6
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agodoc: Reword document titles
Paul Beesley [Thu, 7 Mar 2019 15:47:15 +0000 (15:47 +0000)]
doc: Reword document titles

This patch attempts to standardise the document titles as well as
adding titles to documents that were missing one. The aim is to
remove needless references to "TF-A" or "Trusted Firmware" in the
title of every document and to make sure that the title matches
with the document content.

Change-Id: I9b93ccf43b5d57e8dc793a5311b8ed7c4dd245cc
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agoMerge "rcar_gen3: drivers: qos: update QoS setting" into integration
Sandrine Bailleux [Wed, 22 May 2019 08:01:02 +0000 (08:01 +0000)]
Merge "rcar_gen3: drivers: qos: update QoS setting" into integration

5 years agoMerge changes Icf1ea76c,I9ca3f278 into integration
Sandrine Bailleux [Wed, 22 May 2019 07:06:39 +0000 (07:06 +0000)]
Merge changes Icf1ea76c,I9ca3f278 into integration

* changes:
  imx8: Replace PLAT_IMX8* with automatic PLAT_imx8*
  plat: imx8mq: Implement IMX_SIP_GET_SOC_INFO

5 years agoMerge "Rework smc_unknown return code path in smc_handler" into integration
Sandrine Bailleux [Wed, 22 May 2019 06:22:03 +0000 (06:22 +0000)]
Merge "Rework smc_unknown return code path in smc_handler" into integration

5 years agorcar_gen3: drivers: qos: update QoS setting
Yoshifumi Hosoya [Fri, 12 Apr 2019 08:08:15 +0000 (17:08 +0900)]
rcar_gen3: drivers: qos: update QoS setting

Update M3 Ver.3.0 QoS setting rev.0.03.

Change-Id: I892521d456c606ac3d30f2b2ac6b4e16faa5fc48
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
5 years agoMerge "doc: Move content out of readme and create new index page" into integration
Sandrine Bailleux [Tue, 21 May 2019 14:57:07 +0000 (14:57 +0000)]
Merge "doc: Move content out of readme and create new index page" into integration

5 years agoMerge "doc: Move documents into subdirectories" into integration
Sandrine Bailleux [Tue, 21 May 2019 14:56:08 +0000 (14:56 +0000)]
Merge "doc: Move documents into subdirectories" into integration

5 years agodoc: Move content out of readme and create new index page
Paul Beesley [Thu, 7 Mar 2019 15:25:14 +0000 (15:25 +0000)]
doc: Move content out of readme and create new index page

Previously the readme.rst file served as the entrypoint for the
documentation. With a Sphinx build the top-level document is set
to be index.rst as it contains the primary document index.

This patch moves some content from readme.rst into index.rst and
splits the license information out into license.rst.

Change-Id: I5c50250b81136fe36aa9ceedaae302b44ec11e47
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agodoc: Move documents into subdirectories
Paul Beesley [Mon, 11 Feb 2019 17:54:45 +0000 (17:54 +0000)]
doc: Move documents into subdirectories

This change creates the following directories under docs/
in order to provide a grouping for the content:

- components
- design
- getting_started
- perf
- process

In each of these directories an index.rst file is created
and this serves as an index / landing page for each of the
groups when the pages are compiled. Proper layout of the
top-level table of contents relies on this directory/index
structure.

Without this patch it is possible to build the documents
correctly with Sphinx but the output looks messy because
there is no overall hierarchy.

Change-Id: I3c9f4443ec98571a56a6edf775f2c8d74d7f429f
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agoMerge "doc: Add minimal Sphinx support" into integration
Sandrine Bailleux [Tue, 21 May 2019 13:42:17 +0000 (13:42 +0000)]
Merge "doc: Add minimal Sphinx support" into integration

5 years agoMerge "romlib: Improve compilation flags definition" into integration
Sandrine Bailleux [Tue, 21 May 2019 12:33:18 +0000 (12:33 +0000)]
Merge "romlib: Improve compilation flags definition" into integration

5 years agodoc: Add minimal Sphinx support
Paul Beesley [Wed, 23 Jan 2019 15:39:39 +0000 (15:39 +0000)]
doc: Add minimal Sphinx support

Add the essentials for supporting a Sphinx documentation build:

- A makefile under docs/ to invoke Sphinx with the desired output
  format
- A Sphinx master configuration file (conf.py)
- A single, top-level index page (index.rst)
- The TF.org logo that is integrated in the the sidebar of the
  rendered output

Change-Id: I85e67e939658638337ca7972936a354878083a25
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agoMerge "Fix docs references to header files" into integration
Sandrine Bailleux [Tue, 21 May 2019 08:55:31 +0000 (08:55 +0000)]
Merge "Fix docs references to header files" into integration

5 years agoFix docs references to header files
John Tsichritzis [Mon, 13 May 2019 10:20:05 +0000 (11:20 +0100)]
Fix docs references to header files

Change-Id: I5c06e777d93ac653a853997c2b7c1c9d09b1e49c
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agoRework smc_unknown return code path in smc_handler
Madhukar Pappireddy [Wed, 8 May 2019 20:41:41 +0000 (15:41 -0500)]
Rework smc_unknown return code path in smc_handler

The intention of this patch is to leverage the existing el3_exit() return
routine for smc_unknown return path rather than a custom set of instructions.
In order to leverage el3_exit(), the necessary counteraction (i.e., saving the
system registers apart from GP registers) must be performed. Hence a series of
instructions which save system registers( like SPSR_EL3, SCR_EL3 etc) to stack
are moved to the top of group of instructions which essentially decode the OEN
from the smc function identifier and obtain the specific service handler in
rt_svc_descs_array. This ensures that the control flow for both known and
unknown smc calls will be similar.

Change-Id: I67f94cfcba176bf8aee1a446fb58a4e383905a87
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
5 years agoMerge "Update docs for FVP v11.6" into integration
Sandrine Bailleux [Tue, 21 May 2019 08:17:16 +0000 (08:17 +0000)]
Merge "Update docs for FVP v11.6" into integration

5 years agoromlib: Improve compilation flags definition
Louis Mayencourt [Mon, 29 Apr 2019 15:35:30 +0000 (16:35 +0100)]
romlib: Improve compilation flags definition

* Optimization flags were only provided for debug build.
* Set optimisation level to -O1
* Remove CFLAGS which is never used for romlib
* Remove the ignored -g flag from LDFLAGS

Change-Id: Id4b69026d8a322ed4cb0acf06c350f13d31571ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoUpdate docs for FVP v11.6
John Tsichritzis [Mon, 20 May 2019 12:09:34 +0000 (13:09 +0100)]
Update docs for FVP v11.6

Change-Id: I33c1bf49aa10867e1a2ca4c167112b99bf756dda
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agoimx8: Replace PLAT_IMX8* with automatic PLAT_imx8*
Leonard Crestez [Mon, 20 May 2019 08:28:50 +0000 (11:28 +0300)]
imx8: Replace PLAT_IMX8* with automatic PLAT_imx8*

Platform defines are already provided by the build system so let's not
duplicate them.

Change-Id: Icf1ea76c3c3213e27b447c95e2b22b961fa7693e
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
5 years agoplat: imx8mq: Implement IMX_SIP_GET_SOC_INFO
Leonard Crestez [Fri, 10 May 2019 10:07:41 +0000 (13:07 +0300)]
plat: imx8mq: Implement IMX_SIP_GET_SOC_INFO

The manual documents that 0x3036006c should contains the soc revision
for imx8mq but this always reports A0. Work around this by parsing the
ROM header and checking if OCOTP register 0x40 is stuck at 0xff0055aa.

Determining this inside TF-A makes life easier for OS, see for example
this linux discussion: https://lkml.org/lkml/2019/5/3/465

The soc revision can also be useful inside TF-A itself, for example for
the non-upstream DDR DVFS "busfreq" feature is affected by 8mq erratas.

The clock for OCOTP block can be disabled by OS so only initialize soc
revision once at boot time.

Change-Id: I9ca3f27840229ce8a28b53870e44da29f63c73aa
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
5 years agoMerge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration
Soby Mathew [Thu, 16 May 2019 08:33:56 +0000 (08:33 +0000)]
Merge changes from topic "sami/550_fix_n1sdp_issues_v1" into integration

* changes:
  N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
  N1SDP: Fix DRAM2 start address
  Add option for defining platform DRAM2 base
  Disable speculative loads only if SSBS is supported

5 years agoMerge "plat: imx8mq: Remove duplicated linker symbols" into integration
Soby Mathew [Wed, 15 May 2019 16:00:40 +0000 (16:00 +0000)]
Merge "plat: imx8mq: Remove duplicated linker symbols" into integration

5 years agoMerge "drivers: ufs: Extend the delay after reset to wait for some slower chips"...
Soby Mathew [Wed, 15 May 2019 15:58:17 +0000 (15:58 +0000)]
Merge "drivers: ufs: Extend the delay after reset to wait for some slower chips" into integration

5 years agoMerge "Remove .arch directives from spinlock.S" into integration
Soby Mathew [Wed, 15 May 2019 15:54:32 +0000 (15:54 +0000)]
Merge "Remove .arch directives from spinlock.S" into integration

5 years agoMerge "SMMUv3: Abort DMA transactions" into integration
Soby Mathew [Wed, 15 May 2019 15:54:16 +0000 (15:54 +0000)]
Merge "SMMUv3: Abort DMA transactions" into integration

5 years agoN1SDP: Initialise CNTFRQ in Non Secure CNTBaseN
Sami Mujawar [Fri, 10 May 2019 07:52:07 +0000 (08:52 +0100)]
N1SDP: Initialise CNTFRQ in Non Secure CNTBaseN

N1SDP exhibits the behavior similar to Juno wherein CNTBaseN.CNTFRQ
can be written but does not reflect the value of the CNTFRQ register
in CNTCTLBase frame. This doesn't follow ARM ARM in that the value
updated in CNTCTLBase.CNTFRQ is not reflected in CNTBaseN.CNTFRQ.

Hence enable the workaround (applied to Juno) for N1SDP that updates
the CNTFRQ register in the Non Secure CNTBaseN frame.

Change-Id: Id89ee1bca0f25c9d62f8f794f2c4f4e618cdf092
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
5 years agoN1SDP: Fix DRAM2 start address
Sami Mujawar [Thu, 9 May 2019 12:43:30 +0000 (13:43 +0100)]
N1SDP: Fix DRAM2 start address

The default DRAM2 start address for Arm platforms
is 0x880000000. However, for N1SDP platform this is
0x8080000000.

Fix the DRAM2 start address by initialising
PLAT_ARM_DRAM2_BASE.

Without this fix there is a mismatch of the System
memory region view as seen by the BL31 runtime
firmware (PSCI) versus the view of the OS (which
is based on the description provided by UEFI. In
this case UEFI is correctly describing the DRAM2
start address).

This implicates in secondary cores failing to start
on some Operating Systems if the OS decides to place
the secondary start address in the mismatched region.

Change-Id: I57220e753219353dda429868b4c5e1a69944cc64
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
5 years agoAdd option for defining platform DRAM2 base
Sami Mujawar [Thu, 9 May 2019 12:35:02 +0000 (13:35 +0100)]
Add option for defining platform DRAM2 base

The default DRAM2 base address for Arm platforms
is 0x880000000. However, on some platforms the
firmware may want to move the start address to
a different value.

To support this introduce PLAT_ARM_DRAM2_BASE that
defaults to 0x880000000; but can be overridden by
a platform (e.g. in platform_def.h).

Change-Id: I0d81195e06070bc98f376444b48ada2db1666e28
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
5 years agoDisable speculative loads only if SSBS is supported
Sami Mujawar [Fri, 10 May 2019 13:28:37 +0000 (14:28 +0100)]
Disable speculative loads only if SSBS is supported

Examine the ID_AA64PFR1_EL1 bits 7:4 to see if speculative
loads (SSBS) is implemented, before disabling speculative
loads.

Change-Id: I7607c45ed2889260d22a94f6fd9af804520acf67
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
5 years agodrivers: ufs: Extend the delay after reset to wait for some slower chips
John Stultz [Mon, 13 May 2019 23:56:19 +0000 (16:56 -0700)]
drivers: ufs: Extend the delay after reset to wait for some slower chips

We've seen issues with some THG based UFS chips, where
after reset the LUNs don't always enumerate properly.

After some debugging, we found that extending the mdelay
here seems to resolve the issue by giving the chips enough
time to complete reset.

Change-Id: I848f810b2438ed6ad3d33db614c61d2cef9ac400
Signed-off-by: John Stultz <john.stultz@linaro.org>
5 years agoplat: imx8mq: Remove duplicated linker symbols
Jacky Bai [Tue, 9 Apr 2019 02:55:24 +0000 (10:55 +0800)]
plat: imx8mq: Remove duplicated linker symbols

Remove duplicated linker symbols, resue the symbols
defined in bl_common.h

Change-Id: I10de450eccc78c09b61a8ae7126bf4f4029fa682
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
5 years agoRemove .arch directives from spinlock.S
Alexei Fedorov [Fri, 10 May 2019 15:55:16 +0000 (16:55 +0100)]
Remove .arch directives from spinlock.S

This patch removes .arch "arm8.1-a" and "armv8-a"
directives which overwrite ASFLAGS_aarch64 option based
on ARM_ARCH_MINOR passed to Makefile and cause
translation errors like
"selected processor does not support `bti jc'"
for armv8.5-a targets when BTI support is enabled.

Change-Id: Idca5b66ed1e5d86e2188b0c0f16c3819990957c4
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
5 years agoSMMUv3: Abort DMA transactions
Alexei Fedorov [Thu, 9 May 2019 11:14:40 +0000 (12:14 +0100)]
SMMUv3: Abort DMA transactions

For security DMA should be blocked at the SMMU by default
unless explicitly enabled for a device. SMMU is disabled
after reset with all streams bypassing the SMMU, and
abortion of all incoming transactions implements a default
deny policy on reset.
This patch also moves "bl1_platform_setup()" function from
arm_bl1_setup.c to FVP platforms' fvp_bl1_setup.c and
fvp_ve_bl1_setup.c files.

Change-Id: Ie0ffedc10219b1b884eb8af625bd4b6753749b1a
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
5 years agoMerge "Initialize platform for MediaTek mt8183" into integration
Soby Mathew [Fri, 10 May 2019 10:42:18 +0000 (10:42 +0000)]
Merge "Initialize platform for MediaTek mt8183" into integration

5 years agoMerge "maintainers: Step down as sub-maintainer" into integration
Antonio Niño Díaz [Fri, 10 May 2019 08:57:32 +0000 (08:57 +0000)]
Merge "maintainers: Step down as sub-maintainer" into integration

5 years agoMerge "plat: imx8m: Implement IMX_SIP_BUILDINFO" into integration
Antonio Niño Díaz [Fri, 10 May 2019 08:51:29 +0000 (08:51 +0000)]
Merge "plat: imx8m: Implement IMX_SIP_BUILDINFO" into integration

5 years agoInitialize platform for MediaTek mt8183
kenny liang [Wed, 10 Apr 2019 13:09:26 +0000 (21:09 +0800)]
Initialize platform for MediaTek mt8183

- Add basic platform setup
- Add generic CPU helper functions
- Add delay timer platform implementation
- Use TI 16550 uart driver

Change-Id: I1c29569c68fe9fca5e10e88a22a29690bab7141f
Signed-off-by: kenny liang <kenny.liang@mediatek.com>
5 years agoplat: imx8m: Implement IMX_SIP_BUILDINFO
Leonard Crestez [Wed, 8 May 2019 19:29:21 +0000 (22:29 +0300)]
plat: imx8m: Implement IMX_SIP_BUILDINFO

The IMX_SIP_BUILDINFO call was implemented for imx8qm and imx8qx but
it's also applicable to imx8m.

This fixes U-Boot not printing commit hash on 8m with upstream TF-A.

Change-Id: Idcfd9729eaaccf329c24e241da325f1f6cd3c880
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
5 years agomaintainers: Step down as sub-maintainer
Antonio Nino Diaz [Thu, 9 May 2019 13:26:22 +0000 (14:26 +0100)]
maintainers: Step down as sub-maintainer

I'm giving full maintainership of the Raspberry Pi 3 platform port to
Paul. I'm also leaving the GXBB maintainership to Andre, who is also
happy to pass it on to someone else who is more interested in it.

Change-Id: Ieb2212f5fc11ebde9fc0c857e9e305d691d4ee3f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoMerge "Add Makefile check for PAuth and AArch64" into integration
Antonio Niño Díaz [Thu, 9 May 2019 12:49:37 +0000 (12:49 +0000)]
Merge "Add Makefile check for PAuth and AArch64" into integration

5 years agoAdd Makefile check for PAuth and AArch64
John Tsichritzis [Tue, 7 May 2019 13:09:09 +0000 (14:09 +0100)]
Add Makefile check for PAuth and AArch64

Pointer authentication is supported only in AArch64. A relevant check is
added for that in the Makefile.

Change-Id: I021ba65a9bd5764fd33292bee42617015e04a870
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agoMerge "docs: Update contribution guidelines for binary components" into integration
Soby Mathew [Wed, 8 May 2019 13:41:56 +0000 (13:41 +0000)]
Merge "docs: Update contribution guidelines for binary components" into integration

5 years agoMerge changes I286b925e,I1151c2bc into integration
Antonio Niño Díaz [Wed, 8 May 2019 13:34:04 +0000 (13:34 +0000)]
Merge changes I286b925e,I1151c2bc into integration

* changes:
  plat: imx8mq: Only keep IRQ 32 unmasked
  plat: imx8mq: gpc: Enable all power domain by default

5 years agoMerge "Fix RST rendering and other typos" into integration
Soby Mathew [Wed, 8 May 2019 13:06:19 +0000 (13:06 +0000)]
Merge "Fix RST rendering and other typos" into integration

5 years agoFix RST rendering and other typos
John Tsichritzis [Tue, 7 May 2019 13:13:07 +0000 (14:13 +0100)]
Fix RST rendering and other typos

1) One space was missing from the indentation and, hence, rendering error
was generated in the user guide.
2) Partially reword Pointer Authentication related info.

Change-Id: Id5e65d419ec51dd7764f24d1b96b6c9942d63ba4
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agoplat: imx8mq: Only keep IRQ 32 unmasked
Leonard Crestez [Mon, 6 May 2019 18:43:49 +0000 (21:43 +0300)]
plat: imx8mq: Only keep IRQ 32 unmasked

Only IRQ 32 (SPI 0) needs to be kept unmasked, not everything divisible
by 32.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Change-Id: I286b925eead89218cfeddd82f53a634f3447d212

5 years agoplat: imx8mq: gpc: Enable all power domain by default
Leonard Crestez [Mon, 6 May 2019 19:22:14 +0000 (22:22 +0300)]
plat: imx8mq: gpc: Enable all power domain by default

This is similar to imx8mm and allows uboot to run fastboot over USB otg.

There is a different set of power domains on 8mq but same bits covers
all off them.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Change-Id: I1151c2bc2d32b1e02b4db16285b3d30cabc0d64d

5 years agoMerge changes from topic "sm/fix_a76_errata" into integration
Soby Mathew [Tue, 7 May 2019 14:31:25 +0000 (14:31 +0000)]
Merge changes from topic "sm/fix_a76_errata" into integration

* changes:
  Workaround for cortex-A76 errata 1286807
  Cortex-A76: workarounds for errata 1257314126260612628881275112

5 years agoWorkaround for cortex-A76 errata 1286807
Soby Mathew [Fri, 3 May 2019 12:17:56 +0000 (13:17 +0100)]
Workaround for cortex-A76 errata 1286807

The workaround for Cortex-A76 errata #1286807 is implemented
in this patch.

Change-Id: I6c15af962ac99ce223e009f6d299cefb41043bed
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
5 years agoCortex-A76: workarounds for errata 1257314, 1262606, 1262888, 1275112
Soby Mathew [Wed, 1 May 2019 08:43:18 +0000 (09:43 +0100)]
Cortex-A76: workarounds for errata 1257314126260612628881275112

The workarounds for errata 125731412626061262888 and 1275112 are
added to the Cortex-A76 cpu specific file. The workarounds are disabled
by default and have to be explicitly enabled by the platform integrator.

Change-Id: I70474927374cb67725f829d159ddde9ac4edc343
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
5 years agoMerge "Add compile-time errors for HW_ASSISTED_COHERENCY flag" into integration
Soby Mathew [Fri, 3 May 2019 13:35:38 +0000 (13:35 +0000)]
Merge "Add compile-time errors for HW_ASSISTED_COHERENCY flag" into integration

5 years agoAdd compile-time errors for HW_ASSISTED_COHERENCY flag
John Tsichritzis [Tue, 19 Mar 2019 17:20:52 +0000 (17:20 +0000)]
Add compile-time errors for HW_ASSISTED_COHERENCY flag

This patch fixes this issue:
https://github.com/ARM-software/tf-issues/issues/660

The introduced changes are the following:

1) Some cores implement cache coherency maintenance operation on the
hardware level. For those cores, such as - but not only - the DynamIQ
cores, it is mandatory that TF-A is compiled with the
HW_ASSISTED_COHERENCY flag. If not, the core behaviour at runtime is
unpredictable. To prevent this, compile time checks have been added and
compilation errors are generated, if needed.

2) To enable this change for FVP, a logical separation has been done for
the core libraries. A system cannot contain cores of both groups, i.e.
cores that manage coherency on hardware and cores that don't do it. As
such, depending on the HW_ASSISTED_COHERENCY flag, FVP includes the
libraries only of the relevant cores.

3) The neoverse_e1.S file has been added to the FVP sources.

Change-Id: I787d15819b2add4ec0d238249e04bf0497dc12f3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agoMerge "SMMUv3: refactor the driver code" into integration
Soby Mathew [Fri, 3 May 2019 11:09:02 +0000 (11:09 +0000)]
Merge "SMMUv3: refactor the driver code" into integration

5 years agoSMMUv3: refactor the driver code
Alexei Fedorov [Fri, 26 Apr 2019 11:07:07 +0000 (12:07 +0100)]
SMMUv3: refactor the driver code

This patch is a preparation for the subsequent changes in
SMMUv3 driver. It introduces a new "smmuv3_poll" function
and replaces inline functions for accessing SMMU registers
with mmio read/write operations. Also the infinite loop
for the poll has been replaced with a counter based timeout.

Change-Id: I7a0547beb1509601f253e126b1a7a6ab3b0307e7
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
5 years agoMerge changes from topic "rk3399q7" into integration
Soby Mathew [Thu, 2 May 2019 11:25:26 +0000 (11:25 +0000)]
Merge changes from topic "rk3399q7" into integration

* changes:
  rockchip: Disable binary generation for all SoCs.
  build_macros: Add mechanism to prevent bin generation.

5 years agorockchip: Disable binary generation for all SoCs.
Christoph Müllner [Wed, 24 Apr 2019 07:52:54 +0000 (09:52 +0200)]
rockchip: Disable binary generation for all SoCs.

All supported Rockchip SoCs (RK3288, RK3328, RK3368 and RK3399)
have non-continuous memory areas in the linker script with a huge
gap between them. This results in extremely padded binary images
with a size of about 4 GiB.

E.g. on the RK3399 we have the following memory areas (and base addresses):
RAM (0x1000), SRAM (0xFF8C0000), and PMUSRAM (0xFF3B0000).

Consumers of the TF-A project (e.g. coreboot or U-Boot) therefore
use the ELF image instead, which has a size of a few hundred kBs.

In order to prevent the generation of a huge and useless file,
this patch disables the binary generation for all affected Rockchip
SoCs.

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I4ac65bdf1e598c3e1a59507897d183aee9a36916

5 years agobuild_macros: Add mechanism to prevent bin generation.
Christoph Müllner [Wed, 24 Apr 2019 07:45:30 +0000 (09:45 +0200)]
build_macros: Add mechanism to prevent bin generation.

On certain platforms it does not make sense to generate
TF-A binary images. For example a platform could make use of serveral
memory areas, which are non-continuous and the resulting binary
therefore would suffer from the padding-bytes.
Typically these platforms use the ELF image.

This patch introduces a variable DISABLE_BIN_GENERATION, which
can be set to '1' in the platform makefile to prevent the binary
generation.

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I62948e88bab685bb055fe6167d9660d14e604462

5 years agoMerge changes from topic "rk3399q7" into integration
Antonio Niño Díaz [Thu, 2 May 2019 10:13:08 +0000 (10:13 +0000)]
Merge changes from topic "rk3399q7" into integration

* changes:
  rockchip: Allow console device to be set by DTB.
  rockchip: Add params_setup to RK3328.
  rockchip: Streamline and complete UARTn_BASE macros.

5 years agorockchip: Allow console device to be set by DTB.
Christoph Müllner [Fri, 19 Apr 2019 12:16:27 +0000 (14:16 +0200)]
rockchip: Allow console device to be set by DTB.

Currently the compile-time constant PLAT_RK_UART_BASE defines
which UART is used as console device. E.g. on RK3399 it is set
to UART2. That means, that a single bl31 image can not be used
for two boards, which just differ on the UART console.

This patch addresses this limitation by parsing the "stdout-path"
property from the "chosen" node in the DTB. The expected property
string is expected to have the form "serialN:XXX", with
N being either 0, 1, 2, 3 or 4. When the property is found, it will
be used to override PLAT_RK_UART_BASE.

Tested on RK3399-Q7, with a stdout-path of "serial0:115200n8".

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: Iafe1320e77ab006c121f8d52745d54cef68a48c7

5 years agorockchip: Add params_setup to RK3328.
Christoph Müllner [Wed, 1 May 2019 15:45:10 +0000 (17:45 +0200)]
rockchip: Add params_setup to RK3328.

params_setup.c provides the function params_early_setup, which
takes care of parsing ATF parameters (bl31_plat_param array,
fdt or coreboot table). As params_early_setup is defined as weak
symbol in bl31_plat_setup.c, providing a platform-specific
bl31_plat_setup implementation is optional.

This patch adds the rockchip-common params_setup.c to the sources
for RK3328. This streamlines the parameter handling for all supported
rockchip SoCs.

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I071c03106114364ad2fc408e49cc791fe5b35925

5 years agorockchip: Streamline and complete UARTn_BASE macros.
Christoph Müllner [Tue, 30 Apr 2019 23:37:58 +0000 (01:37 +0200)]
rockchip: Streamline and complete UARTn_BASE macros.

In order to set the UART base during bootup in common code of
plat/rockchip, we need to streamline the way the UART base addresses
are defined and add the missing definitions and mappings.

This patch does so by following the pattern UARTn_BASE, which is
already in use on RK3399 and RK3328. The numbering itself is derived
from the upstream Linux DTS files of the individual SoCs.

Signed-off-by: Christoph Müllner <christophm30@gmail.com>
Change-Id: I341a1996f4ceed5f82a2f6687d4dead9d7cc5c1f

5 years agodocs: Update contribution guidelines for binary components
Julius Werner [Thu, 18 Apr 2019 23:47:46 +0000 (16:47 -0700)]
docs: Update contribution guidelines for binary components

This patch updates the contribution guidelines to refer to the new
binary repository.

Change-Id: I898dc58973be91c3f87be53a755269fca2e93174
Signed-off-by: Julius Werner <jwerner@chromium.org>
5 years agoMerge "ti: k3: common: Remove MSMC port definitions" into integration
Soby Mathew [Tue, 30 Apr 2019 16:17:09 +0000 (16:17 +0000)]
Merge "ti: k3: common: Remove MSMC port definitions" into integration

5 years agoMerge changes from topic "lm/stack_protector" into integration
Soby Mathew [Tue, 30 Apr 2019 15:43:21 +0000 (15:43 +0000)]
Merge changes from topic "lm/stack_protector" into integration

* changes:
  juno: Add security sources for tsp-juno
  Add support for default stack-protector flag

5 years agojuno: Add security sources for tsp-juno
Louis Mayencourt [Wed, 17 Apr 2019 15:35:24 +0000 (16:35 +0100)]
juno: Add security sources for tsp-juno

Security sources are required if stack-protector is enabled.

Change-Id: Ia0071f60cf03d48b200fd1facbe50bd9e2f8f282
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoAdd support for default stack-protector flag
Louis Mayencourt [Tue, 26 Mar 2019 16:59:26 +0000 (16:59 +0000)]
Add support for default stack-protector flag

The current stack-protector support is for none, "strong" or "all".
The default use of the flag enables the stack-protection to all
functions that declare a character array of eight bytes or more in
length on their stack.
This option can be tuned with the --param=ssp-buffer-size=N option.

Change-Id: I11ad9568187d58de1b962b8ae04edd1dc8578fb0
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoti: k3: common: Remove MSMC port definitions
Andrew F. Davis [Wed, 27 Mar 2019 14:37:10 +0000 (09:37 -0500)]
ti: k3: common: Remove MSMC port definitions

The MSMC port defines were added to help in the case when some ports
are not connected and have no cores attached. We can get the same
functionality by defined the number of cores on that port to zero.
This simplifies several code paths, do this here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I3247fe37af7b86c3227e647b4f617fab70c8ee8a

5 years agoMerge "rockchip: only include libfdt in non-coreboot cases" into integration
Soby Mathew [Mon, 29 Apr 2019 15:38:40 +0000 (15:38 +0000)]
Merge "rockchip: only include libfdt in non-coreboot cases" into integration

5 years agoMerge "hikey: Add define for UART2" into integration
Soby Mathew [Mon, 29 Apr 2019 11:29:52 +0000 (11:29 +0000)]
Merge "hikey: Add define for UART2" into integration

5 years agoMerge changes from topic "avenger96" into integration
Soby Mathew [Mon, 29 Apr 2019 11:29:27 +0000 (11:29 +0000)]
Merge changes from topic "avenger96" into integration

* changes:
  fdts: Fix DTC warnings for STM32MP1 platform
  docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
  stm32mp1: Add Avenger96 board support

5 years agoMerge changes from topic "k3-coherency" into integration
Soby Mathew [Mon, 29 Apr 2019 11:28:39 +0000 (11:28 +0000)]
Merge changes from topic "k3-coherency" into integration

* changes:
  ti: k3: common: Mark sections for AM65x coherency workaround
  ti: k3: common: Allow USE_COHERENT_MEM for K3
  ti: k3: common: Fix RO data area size calculation
  ti: k3: common: Remove unused STUB macro

5 years agoMerge "plat: allwinner: common: use r_wdog instead of wdog" into integration
Antonio Niño Díaz [Mon, 29 Apr 2019 09:03:18 +0000 (09:03 +0000)]
Merge "plat: allwinner: common: use r_wdog instead of wdog" into integration

5 years agoMerge changes Ie7766e80,Ia74dbc36 into integration
Antonio Niño Díaz [Mon, 29 Apr 2019 08:51:10 +0000 (08:51 +0000)]
Merge changes Ie7766e80,Ia74dbc36 into integration

* changes:
  plat: marvell: do not rely on argument passed via smc
  plat: marvell: sip: make sure that comphy init will use correct address

5 years agorockchip: only include libfdt in non-coreboot cases
Heiko Stuebner [Wed, 24 Apr 2019 18:26:51 +0000 (20:26 +0200)]
rockchip: only include libfdt in non-coreboot cases

While mainline u-boot always expects to submit the devicetree
as platform param, coreboot always uses the existing parameter
structure. As libfdt is somewhat big, it makes sense to limit
its inclusion to where necessary and thus only to non-coreboot
builds.

libfdt itself will get build in all cases, but only the non-
coreboot build will actually reference and thus include it.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I4c5bc28405a14e6070917e48a526bfe77bab2fb7

5 years agoti: k3: common: Mark sections for AM65x coherency workaround
Andrew F. Davis [Thu, 25 Apr 2019 17:57:02 +0000 (13:57 -0400)]
ti: k3: common: Mark sections for AM65x coherency workaround

These sections of code are only needed for the coherency workaround
used for AM65x, if this workaround is not needed then this code
is not either. Mark it off to keep it separated from the rest of
the PSCI implementation.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I113ca6a2a1f7881814ab0a64e5bac57139bc03ef

5 years agoti: k3: common: Allow USE_COHERENT_MEM for K3
Andrew F. Davis [Thu, 25 Apr 2019 17:54:09 +0000 (13:54 -0400)]
ti: k3: common: Allow USE_COHERENT_MEM for K3

To make the USE_COHERENT_MEM option work we need to add an entry for the
area to our memory map table. Also fixup the alignment here.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I1c05477a97646ac73846a711bc38d3746628d847

5 years agoti: k3: common: Fix RO data area size calculation
Andrew F. Davis [Thu, 25 Apr 2019 17:52:54 +0000 (13:52 -0400)]
ti: k3: common: Fix RO data area size calculation

The size of the RO data area was calculated by subtracting the area end
address from itself and not the base address due to a typo. Fix this
here.

Note, this was noticed at a glance thanks to the new aligned formating
of this table.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: I994022ac9fc95dc5e37a420714da76081c61cce7

5 years agoti: k3: common: Remove unused STUB macro
Andrew F. Davis [Thu, 25 Apr 2019 17:51:12 +0000 (13:51 -0400)]
ti: k3: common: Remove unused STUB macro

This macro was used when many of these functions were stubbed out,
the macro is not used anymore, remove it.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ida33f92fe3810a89e6e51faf6e93c1d2ada1a2ee

5 years agohikey: Add define for UART2
Michalis Pappas [Tue, 23 Apr 2019 11:56:49 +0000 (13:56 +0200)]
hikey: Add define for UART2

Change-Id: I54869151bfc434df66933bd418c70cca9c3d0861
Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
5 years agofdts: Fix DTC warnings for STM32MP1 platform
Manivannan Sadhasivam [Fri, 26 Apr 2019 13:25:59 +0000 (18:55 +0530)]
fdts: Fix DTC warnings for STM32MP1 platform

DTC issues below warnings for STM32MP1 platform for using upper case
in unit address:

fdts/stm32mp15-ddr.dtsi:8.20-151.5: Warning (simple_bus_reg): /soc/ddr@5A003000: simple-bus unit address format error, expected "5a003000"
fdts/stm32mp157c-security.dtsi:9.25-13.5: Warning (simple_bus_reg): /soc/stgen@5C008000: simple-bus unit address format error, expected "5c008000"

Fix this by using the lower case unit address for concerned nodes.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Change-Id: Id3d19ac3b47ec6bcea2bd3382225e2e923dc4a70

5 years agodocs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable
Manivannan Sadhasivam [Fri, 26 Apr 2019 13:16:29 +0000 (18:46 +0530)]
docs: plat: stm32mp1: Document the usage of DTB_FILE_NAME variable

Since STM32MP1 platform supports different boards, it is necessary
to build for a particular board. With the current instructions, the
user has to modify the DTB_FILE_NAME variable in platform.mk for
building for a particular board, but this can be avoided by passing
the appropriate board DTB name via DTB_FILE_NAME make variable.
Hence document the same in platform doc.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Change-Id: I16797e7256c7eb699a7b8846356fe430d0fe0aa1

5 years agostm32mp1: Add Avenger96 board support
Manivannan Sadhasivam [Fri, 26 Apr 2019 13:13:50 +0000 (18:43 +0530)]
stm32mp1: Add Avenger96 board support

Add board support for Avenger96 board from Arrow Electronics. This
board is based on STM32MP157A SoC and is one of the 96Boards Consumer
Edition platform.

More information about this board can be found in 96Boards website:
https://www.96boards.org/product/avenger96/

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Change-Id: Ic905f26c38d03883c6e4ea221b4b275a4b534857

5 years agoMerge "rk3399: m0: Fix compiler warnings." into integration
Soby Mathew [Fri, 26 Apr 2019 12:55:49 +0000 (12:55 +0000)]
Merge "rk3399: m0: Fix compiler warnings." into integration

5 years agoMerge "Cortex-A53: Fix reporting of missing errata when not needed" into integration
Antonio Niño Díaz [Fri, 26 Apr 2019 12:47:08 +0000 (12:47 +0000)]
Merge "Cortex-A53: Fix reporting of missing errata when not needed" into integration

5 years agoMerge changes from topic "rk3288" into integration
Soby Mathew [Fri, 26 Apr 2019 12:42:44 +0000 (12:42 +0000)]
Merge changes from topic "rk3288" into integration

* changes:
  rockchip: document platform
  rockchip: add support for rk3288
  rockchip: add common aarch32 support
  rockchip: rk3328: drop double declaration of entry_point storage
  rockchip: Allow socs with undefined wfe check bits
  rockchip: move pmusram assembler code to a aarch64 subdir
  sp_min: allow inclusion of a platform-specific linker script
  sp_min: make sp_min_warm_entrypoint public
  drivers: ti: uart: add a aarch32 variant

5 years agoMerge "Doc: Update link to TBBR-CLIENT specification" into integration
Soby Mathew [Fri, 26 Apr 2019 12:40:04 +0000 (12:40 +0000)]
Merge "Doc: Update link to TBBR-CLIENT specification" into integration

5 years agoCortex-A53: Fix reporting of missing errata when not needed
Andrew F. Davis [Wed, 24 Apr 2019 20:11:03 +0000 (16:11 -0400)]
Cortex-A53: Fix reporting of missing errata when not needed

Errata 819472, 824069, and 827319 are currently reported in a warning as
missing during boot for platforms that do not need them. Only warn when
the errata is needed for a given revision but not compiled in like other
errata workarounds.

Fixes: bd393704d2b1 ("Cortex-A53: Workarounds for 819472, 824069 and 827319")
Signed-off-by: Andrew F. Davis <afd@ti.com>
Change-Id: Ifd757b3d0e73a9bd465b98dc20648b6c13397d8d

5 years agorockchip: document platform
Heiko Stuebner [Fri, 19 Apr 2019 10:35:47 +0000 (12:35 +0200)]
rockchip: document platform

This adds a rockchip.rst to docs/plat documenting the general
approach to using the Rockchip ATF platforms together with the
supported bootloaders and also adds myself as maintainer after
making sure Tony Xie is ok with that.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Idce53d15eff4ac6de05bbb35d86e57ed50d0cbb9

5 years agorockchip: add support for rk3288
Heiko Stuebner [Thu, 14 Mar 2019 21:12:04 +0000 (22:12 +0100)]
rockchip: add support for rk3288

The rk3288 is a 4-core Cortex-A12 SoC and shares a lot of features
with later SoCs.

Working features are general non-secure mode (the gic needs special
love for that), psci-based smp bringing cpu cores online and also
taking them offline again, psci-based suspend (the simpler variant
also included in the linux kernel, deeper suspend following later)
and I was also already able to test HYP-mode and was able to boot
a virtual kernel using kvm.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ibaaa583b2e78197591a91d254339706fe732476a

5 years agorockchip: add common aarch32 support
Heiko Stuebner [Thu, 14 Mar 2019 21:11:34 +0000 (22:11 +0100)]
rockchip: add common aarch32 support

There are a number or ARMv7 Rockchip SoCs that are very similar in their
bringup routines to the existing arm64 SoCs, so there is quite a high
commonality possible here.

Things like virtualization also need psci and hyp-mode and instead of
trying to cram this into bootloaders like u-boot, barebox or coreboot
(all used in the field), re-use the existing infrastructure in TF-A
for this (both Rockchip plat support and armv7 support in general).

So add core support for aarch32 Rockchip SoCs, with actual soc support
following in a separate patch.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I298453985b5d8434934fc0c742fda719e994ba0b

5 years agorockchip: rk3328: drop double declaration of entry_point storage
Heiko Stuebner [Thu, 25 Apr 2019 10:40:41 +0000 (12:40 +0200)]
rockchip: rk3328: drop double declaration of entry_point storage

The cpuson_entry_point and cpuson_flags are already declared in
plat_private.h so there is no need to have it again declared in
the local pmu.h, especially as it may cause conflicts when the
other type changes.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I80ae0e23d22f67109ed96f8ac059973b6de2ce87

5 years agorockchip: Allow socs with undefined wfe check bits
Heiko Stuebner [Thu, 7 Mar 2019 07:01:37 +0000 (08:01 +0100)]
rockchip: Allow socs with undefined wfe check bits

Some older socs like the rk3288 do not have the necessary registers
to check the wfi/wfe state of the cpu cores. Allow this case an "just"
do an additional delay similar to how the Linux kernel handles smp
right now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I0f67af388b06b8bfb4a9bac411b4900ac266a77a

5 years agorockchip: move pmusram assembler code to a aarch64 subdir
Heiko Stuebner [Tue, 5 Mar 2019 12:46:41 +0000 (13:46 +0100)]
rockchip: move pmusram assembler code to a aarch64 subdir

The current code doing power-management from sram is highly
arm64-specific so should live in a corresponding subdirectory
and not in the common area.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I3b79ac26f70fd189d4d930faa6251439a644c5d9

5 years agosp_min: allow inclusion of a platform-specific linker script
Heiko Stuebner [Thu, 11 Apr 2019 13:26:07 +0000 (15:26 +0200)]
sp_min: allow inclusion of a platform-specific linker script

Similar to bl31 allow sp_min to also include a platform-specific
linker script. This allows for example to place specific code in
other memories of the system, like resume code in sram, while the
main tf-a lives in ddr.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I67642f7bfca036b5d51eb0fa092b479a647a9cc1

5 years agosp_min: make sp_min_warm_entrypoint public
Heiko Stuebner [Sat, 2 Mar 2019 10:59:04 +0000 (11:59 +0100)]
sp_min: make sp_min_warm_entrypoint public

Similar to bl31_warm_entrypoint, sp_min-based platforms may need
that for special resume handling.

Therefore move it from the private header to the sp_min platform header.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I40d9eb3ff77cff88d47c1ff51d53d9b2512cbd3e

5 years agodrivers: ti: uart: add a aarch32 variant
Heiko Stuebner [Thu, 7 Mar 2019 09:26:19 +0000 (10:26 +0100)]
drivers: ti: uart: add a aarch32 variant

Rockchip re-uses the ti uart console driver and for aarch32 needs a
specific variant, so add it.
There are also aarch32 ti socs, so it may be useful for them as well
at some point.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I31ede7cc7b10347b3691cff051db2b985fd59e17