project/bcm63xx/atf.git
5 years agoMerge pull request #1882 from ambroise-arm/av/a15-errata
Soby Mathew [Wed, 13 Mar 2019 15:34:33 +0000 (15:34 +0000)]
Merge pull request #1882 from ambroise-arm/av/a15-errata

Apply workarounds for errata of Cortex-A15

5 years agoMerge pull request #1881 from sandrine-bailleux-arm/sb/doc-fixes
Soby Mathew [Wed, 13 Mar 2019 15:33:36 +0000 (15:33 +0000)]
Merge pull request #1881 from sandrine-bailleux-arm/sb/doc-fixes

Minor doc fixes

5 years agoMerge pull request #1880 from lmayencourt/lm/pie
Soby Mathew [Wed, 13 Mar 2019 15:33:13 +0000 (15:33 +0000)]
Merge pull request #1880 from lmayencourt/lm/pie

PIE: fix linking with pie and binutils > 2.27

5 years agoMerge pull request #1879 from pbeesley-arm/pb/todo-removal
Soby Mathew [Wed, 13 Mar 2019 15:32:15 +0000 (15:32 +0000)]
Merge pull request #1879 from pbeesley-arm/pb/todo-removal

Pb/todo removal

5 years agoMerge pull request #1878 from jts-arm/sctlr
Soby Mathew [Wed, 13 Mar 2019 15:32:00 +0000 (15:32 +0000)]
Merge pull request #1878 from jts-arm/sctlr

Apply stricter speculative load restriction

5 years agoMerge pull request #1874 from hadi-asyrafi/qspi_boot
Soby Mathew [Wed, 13 Mar 2019 15:31:33 +0000 (15:31 +0000)]
Merge pull request #1874 from hadi-asyrafi/qspi_boot

intel: QSPI boot enablement

5 years agoMerge pull request #1873 from hadi-asyrafi/driver_qspi
Soby Mathew [Wed, 13 Mar 2019 15:30:43 +0000 (15:30 +0000)]
Merge pull request #1873 from hadi-asyrafi/driver_qspi

intel: Add driver for QSPI

5 years agoMerge pull request #1843 from DavidPu/xlat_tables_v2_non_recursion
Soby Mathew [Wed, 13 Mar 2019 15:26:51 +0000 (15:26 +0000)]
Merge pull request #1843 from DavidPu/xlat_tables_v2_non_recursion

Remove recursion from xlat_tables_v2 library

5 years agoMerge pull request #1858 from thloh85-intel/dwmmc_fixes
Soby Mathew [Wed, 13 Mar 2019 15:25:54 +0000 (15:25 +0000)]
Merge pull request #1858 from thloh85-intel/dwmmc_fixes

drivers: synopsys: Fix synopsys MMC driver

5 years agoMerge pull request #1856 from masahisak/synquacer-scmi-support
Soby Mathew [Wed, 13 Mar 2019 15:24:11 +0000 (15:24 +0000)]
Merge pull request #1856 from masahisak/synquacer-scmi-support

plat/synquacer: enable SCMI support

5 years agoCortex-A15: Implement workaround for errata 827671
Ambroise Vincent [Tue, 5 Mar 2019 09:54:21 +0000 (09:54 +0000)]
Cortex-A15: Implement workaround for errata 827671

This erratum can only be worked around on revisions >= r3p0 because the
register that needs to be accessed only exists in those revisions[1].

[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438g/CIHEAAAD.html

Change-Id: I5d773547d7a09b5bd01dabcd19ceeaf53c186faa
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A15: Implement workaround for errata 816470
Ambroise Vincent [Mon, 4 Mar 2019 16:56:26 +0000 (16:56 +0000)]
Cortex-A15: Implement workaround for errata 816470

Change-Id: I9755252725be25bfd0147839d7df56888424ff84
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoMerge pull request #1877 from bryanodonoghue/integration+bl2-el3-eret-fix-v2
Dimitris Papastamos [Wed, 13 Mar 2019 13:59:00 +0000 (13:59 +0000)]
Merge pull request #1877 from bryanodonoghue/integration+bl2-el3-eret-fix-v2

bl2-el3: Fix exit to bl32 by ensuring full write to SPSR

5 years agoMerge pull request #1861 from Yann-lms/checkpatch
Dimitris Papastamos [Wed, 13 Mar 2019 13:58:10 +0000 (13:58 +0000)]
Merge pull request #1861 from Yann-lms/checkpatch

Update checkpatch options

5 years agoMerge pull request #1875 from Yann-lms/bsec
Dimitris Papastamos [Wed, 13 Mar 2019 13:57:48 +0000 (13:57 +0000)]
Merge pull request #1875 from Yann-lms/bsec

fdts: stm32mp1: add bsec node

5 years agobl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed
Bryan O'Donoghue [Tue, 12 Mar 2019 12:09:51 +0000 (12:09 +0000)]
bl1-smc-handler: Ensure the lower-order 16 bits of SPSR are programmed

A bug recently fixed in bl2/aarch32/bl2_el3_entrypoint.S relates to
programming the lower-order 16 bits of the SPSR to populate into the CPSR
on eret.

The BL1 smc-handler code is identical and has the same shortfall in
programming the SPSR from the platform defined struct
entry_point_info->spsr.

msr spsr, r1 will only update bits f->[31:24] and c->[7:0] respectively. In
order to ensure the 16 lower-order processor mode bits x->[15:8] and
c->[7:0] this patch changes msr spsr, r1 to msr spsr_xc, r1.

This change ensures we capture the x field, which we are interested in and
not the f field which we are not.

Fixes: f3b4914be3b4 ('AArch32: Add generic changes in BL1')
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
5 years agobl2-el3: Fix exit to bl32 by ensuring a more complete write to SPSR
Bryan O'Donoghue [Mon, 11 Mar 2019 15:36:07 +0000 (15:36 +0000)]
bl2-el3: Fix exit to bl32 by ensuring a more complete write to SPSR

Prior to entry into BL32 we set the SPSR by way of msr spsr, r1.
This unfortunately only writes the bits f->[31:24] and c->[7:0].

This patch updates the bl2 exit path to write the x->[15:8] and c->[7:0]
fields of the SPSR. For the purposes of initial setup of the SPSR the x and
c fields should be sufficient and importantly will capture the necessary
lower-order control bits that f:c alone do not.

This is important to do to ensure the SPSR is set to the mode the platform
intends prior to performing an eret.

Fixes: b1d27b484f41 ("bl2-el3: Add BL2_EL3 image")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
5 years agointel: QSPI boot enablement
Muhammad Hadi Asyrafi Abdul Halim [Fri, 8 Mar 2019 11:02:33 +0000 (19:02 +0800)]
intel: QSPI boot enablement
Manages QSPI initialization, configuration and IO handling as boot device

Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
5 years agointel: Add driver for QSPI
Muhammad Hadi Asyrafi Abdul Halim [Fri, 8 Mar 2019 11:21:04 +0000 (19:21 +0800)]
intel: Add driver for QSPI
To support the enablement of QSPI booting

Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
5 years agoplat/arm: mhu: make mhu driver generic
Masahisa Kojima [Thu, 7 Mar 2019 02:23:42 +0000 (11:23 +0900)]
plat/arm: mhu: make mhu driver generic

MHU doorbell driver requires arm platform specific
macro "PLAT_CSS_MHU_BASE".
Rename it to "PLAT_MHUV2_BASE", so that platforms other than arm
can use generic MHU doorbell driver.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
5 years agoplat/synquacer: enable SCMI support
Masahisa Kojima [Thu, 7 Mar 2019 01:41:54 +0000 (10:41 +0900)]
plat/synquacer: enable SCMI support

Enable the SCMI protocol support in SynQuacer platform.
Aside from power domain, system power and apcore management protocol,
this commit adds the vendor specific protocol(0x80).
This vendor specific protocol is used to get the dram mapping information
from SCP.

Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
5 years agoMakefile: fix linking with pie and binutils > 2.27
Louis Mayencourt [Tue, 5 Mar 2019 17:08:46 +0000 (17:08 +0000)]
Makefile: fix linking with pie and binutils > 2.27

Since binutils 1a9ccd70f9a7[1] TFA will not link when the PIE option is
used:

    aarch64-linux-gnu-ld: build/fvp/debug/bl31/bl31.elf: Not enough room
        for program headers, try linking with -N
    aarch64-linux-gnu-ld: final link failed: Bad value

This issue was also encountered by u-boot[2] and linux powerpc kernel
[3]. The fix is to provide --no-dynamic-linker for the linker. This
tells the linker that PIE does not need loaded program program headers.

Fix https://github.com/ARM-software/tf-issues/issues/675

[1] https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commit;h=1a9ccd70f9a7
[2] http://git.denx.de/?p=u-boot.git;a=commit;h=e391b1e64b0bd65709a28a4764afe4f32d408243
[3] https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?h=next&id=ff45000fcb56b5b0f1a14a865d3541746d838a0a

Change-Id: Ic3c33c795a9b7bdeab0e87c4345153ce2703a524
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoPIE: Correct minor typographical errors
Louis Mayencourt [Fri, 1 Mar 2019 14:36:46 +0000 (14:36 +0000)]
PIE: Correct minor typographical errors

Change-Id: Ie7832b2ebffe15d53ffe3584e4d23a449d4f81ac
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agodoc: Minor formatting enhancement
Sandrine Bailleux [Tue, 12 Mar 2019 14:10:49 +0000 (15:10 +0100)]
doc: Minor formatting enhancement

The security advisories would all appear on a single line. Use bullet
points instead to improve the readability.

Change-Id: Id631985d7d559b3632f43d695cffa6735520b64a
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
5 years agodoc: Fix a broken link in the readme.rst file
Sandrine Bailleux [Tue, 12 Mar 2019 14:07:27 +0000 (15:07 +0100)]
doc: Fix a broken link in the readme.rst file

Change-Id: I53a4649b17614f711957424ddffed1dcccfc7880
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
5 years agodrivers: Remove TODO from io_fip.c
Paul Beesley [Wed, 6 Mar 2019 15:52:16 +0000 (15:52 +0000)]
drivers: Remove TODO from io_fip.c

The comment suggests checking version numbers and
a checksum but there doesn't seem to be any usable
data for either of these.

For example, fip_toc_header_t doesn't contain any
version information and neither does fip_toc_entry_t.

As the function name "is_valid_header" suggests, this
function is not concerned with checksumming any of
the table of contents entries.

Change-Id: I8673ae5dd37793771760169f26b2f55c15fbf587
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agodrivers: Remove TODO from io_storage
Paul Beesley [Wed, 6 Mar 2019 15:42:50 +0000 (15:42 +0000)]
drivers: Remove TODO from io_storage

This TODO was added five years ago so I assume that there is not
going to be a shutdown API added after all.

Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d3
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agotools: Remove TODO from fiptool
Paul Beesley [Wed, 6 Mar 2019 15:28:11 +0000 (15:28 +0000)]
tools: Remove TODO from fiptool

It is quite unlikely that this number will ever change and, if it
does need to change, we should have a good reason to do so. It
seems that this comment is now redundant.

Change-Id: I409c764080748e338e9bc5606bbdcc475213fb6e
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agotools: Remove unused cert_create defines
Paul Beesley [Wed, 6 Mar 2019 15:27:15 +0000 (15:27 +0000)]
tools: Remove unused cert_create defines

Change-Id: Iea72ef9ba16325cbce07eea1a975d2a96eede274
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agoApply stricter speculative load restriction
John Tsichritzis [Mon, 4 Mar 2019 16:42:54 +0000 (16:42 +0000)]
Apply stricter speculative load restriction

The SCTLR.DSSBS bit is zero by default thus disabling speculative loads.
However, we also explicitly set it to zero for BL2 and TSP images when
each image initialises its context. This is done to ensure that the
image environment is initialised in a safe state, regardless of the
reset value of the bit.

Change-Id: If25a8396641edb640f7f298b8d3309d5cba3cd79
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agodrivers: synopsys: Fix synopsys MMC driver
Tien Hock, Loh [Tue, 12 Mar 2019 06:36:19 +0000 (14:36 +0800)]
drivers: synopsys: Fix synopsys MMC driver

There are some issues with synopsys MMC driver:
- CMD8 should not expect data (for SD)
- ACMD51 should expect data (Send SCR for SD)
- dw_prepare should not dictate size to be MMC_BLOCK_SIZE, block size is
now handled in the dw_prepare function
- after the CMD completes, when doing dw_read, we need to invalidate cache
and wait for the data transfer to complete
- Need to set FIFO threshold, otherwise DMA might never get the interrupt
to read or write

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
5 years agoMerge pull request #1872 from Yann-lms/ocr_voltage
Dimitris Papastamos [Mon, 11 Mar 2019 09:20:47 +0000 (09:20 +0000)]
Merge pull request #1872 from Yann-lms/ocr_voltage

mmc: stm32_sdmmc2: fill ocr_voltage

5 years agoRemove some warnings when using checkpatch with --strict option
Yann Gautier [Fri, 8 Mar 2019 14:44:59 +0000 (15:44 +0100)]
Remove some warnings when using checkpatch with --strict option

Some checks are ignored as they do not match TF-A coding rules:
PREFER_KERNEL_TYPES, USLEEP_RANGE
or MISRA:
COMPARISON_TO_NULL, UNNECESSARY_PARENTHESES

Change-Id: I335ede89fc872a6169028552d1ba9312fc61a0ba
Signed-off-by: Yann Gautier <yann.gautier@st.com>
5 years agoAdd the possibility to pass options for checkpatch
Yann Gautier [Fri, 8 Mar 2019 14:44:00 +0000 (15:44 +0100)]
Add the possibility to pass options for checkpatch

It can be handy for example to add --strict option which can detect more
coding issues, even if not mandated by TF-A coding rules.
To use it:
 CHECKPATCH_OPTS="--strict" make checkpatch

Change-Id: I707e4cc2d1250b21f18ff16169b5f1e5ab03a7ed
Signed-off-by: Yann Gautier <yann.gautier@st.com>
5 years ago.checkpatch.conf: ignore BRACES warnings
Yann Gautier [Wed, 6 Mar 2019 09:58:13 +0000 (10:58 +0100)]
.checkpatch.conf: ignore BRACES warnings

MISRA C:2012 Rule 15.6 asks to have braces for the body of an if,
for, or while statement.
This conflicts with checkpatch, and the warning should then be ignored.

Change-Id: I22589b68b03f19a426d3bcbc10a99d4e4c76eced
Signed-off-by: Yann Gautier <yann.gautier@st.com>
5 years agofdts: stm32mp1: add bsec node
Yann Gautier [Mon, 11 Mar 2019 09:04:38 +0000 (10:04 +0100)]
fdts: stm32mp1: add bsec node

This node is added in a new file stm32mp157c-security.dtsi.
This node includes OTPs that should be shadowed and made readable
to non secure world.
Explicitly add status and secure-status, as these OTPs are accessible
by secure and non-secure world.

The stgen node is also moved to this file.

Change-Id: I3c89a01588d2e411fecfc44997e1c5df2fc37cad
Signed-off-by: Yann Gautier <yann.gautier@st.com>
5 years agoallwinner: regulators: pick correct DT subnode
Andre Przywara [Sun, 17 Feb 2019 22:10:11 +0000 (22:10 +0000)]
allwinner: regulators: pick correct DT subnode

So far the DT node describing the AXP803 PMIC used in many Allwinner A64
boards had only one subnode, so our code just entering the first subnode
to find all regulators worked fine.

However recent DT updates in the Linux kernel add more subnodes *before*
that, so we need to make sure to explicitly enter the "regulators"
subnode to find the information we are after.

Improve some DT node parsing error handling on the way.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
5 years agoFixup register handling in aarch32 reset_handler
Heiko Stuebner [Tue, 5 Mar 2019 23:29:13 +0000 (00:29 +0100)]
Fixup register handling in aarch32 reset_handler

The BL handover interface stores the bootloader arguments in
registers r9-r12, so when the reset_handler stores the lr pointer
in r10 it clobers one of the arguments.

Adapt to use r8 and adapt the comment about registers allowed
to clober.

I've checked aarch32 reset_handlers and none seem to use higher
registers as far as I can tell.

Fixes: a6f340fe58b9 ("Introduce the new BL handover interface")
Cc: Soby Mathew <soby.mathew@arm.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
5 years agozynqmp: pm: Add support for setting PMU configuration object
Luca Ceresoli [Thu, 28 Feb 2019 21:15:35 +0000 (22:15 +0100)]
zynqmp: pm: Add support for setting PMU configuration object

Allow EL2 (e.g. U-Boot) to load the configuration object at runtime
into the Xilinx ZynqMP PMU firmware. This allows booting with U-Boot
and U-Boot SPL with PMU FW without hard-coding the configuration
object.

Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net>
5 years agommc: stm32_sdmmc2: fill ocr_voltage
Yann Gautier [Fri, 8 Mar 2019 09:59:00 +0000 (10:59 +0100)]
mmc: stm32_sdmmc2: fill ocr_voltage

STM32MP1 SDMMC device voltage is 3.3V. We should then precise the 2 ranges
3.2 to 3.3V and 3.3 to 3.4V in ocr_voltage field.

Change-Id: I88e479f8f16bfe608a7808eace0df3fdec48deab
Signed-off-by: Yann Gautier <yann.gautier@st.com>
5 years agoMerge pull request #1867 from AlexeiFedorov/af/enable_ptrauth_warm_boot
Dimitris Papastamos [Fri, 8 Mar 2019 09:43:54 +0000 (09:43 +0000)]
Merge pull request #1867 from AlexeiFedorov/af/enable_ptrauth_warm_boot

BL31: Enable pointer authentication support in warm boot path

5 years agoMerge pull request #1870 from thloh85-intel/s10_mmc
Dimitris Papastamos [Fri, 8 Mar 2019 09:42:44 +0000 (09:42 +0000)]
Merge pull request #1870 from thloh85-intel/s10_mmc

plat: intel: Add MMC OCR voltage information for initialization

5 years agoMerge pull request #1863 from thloh85-intel/mmc_fixes
Dimitris Papastamos [Fri, 8 Mar 2019 09:41:22 +0000 (09:41 +0000)]
Merge pull request #1863 from thloh85-intel/mmc_fixes

drivers: mmc: Fix some issues with MMC stack

5 years agoplat: intel: Add MMC OCR voltage information for initialization
Tien Hock, Loh [Fri, 8 Mar 2019 01:26:24 +0000 (09:26 +0800)]
plat: intel: Add MMC OCR voltage information for initialization

MMC stack needs OCR voltage information for the platform to initialize
MMC controller correctly.

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
5 years agoplat: intel: Add MMC OCR voltage information for initialization
Tien Hock, Loh [Fri, 8 Mar 2019 01:26:24 +0000 (09:26 +0800)]
plat: intel: Add MMC OCR voltage information for initialization

MMC stack needs OCR voltage information for the platform to initialize
MMC controller correctly.

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
5 years agoMerge pull request #1864 from hadi-asyrafi/mailbox_fix
Dimitris Papastamos [Thu, 7 Mar 2019 13:58:12 +0000 (13:58 +0000)]
Merge pull request #1864 from hadi-asyrafi/mailbox_fix

intel: Mailbox service un-accessible

5 years agoMerge pull request #1862 from thloh85-intel/s10_bl2
Dimitris Papastamos [Thu, 7 Mar 2019 13:31:41 +0000 (13:31 +0000)]
Merge pull request #1862 from thloh85-intel/s10_bl2

plat: intel: Improve ECC scrubbing performance

5 years agoMerge pull request #1868 from Yann-lms/zeromem_device_info
Dimitris Papastamos [Thu, 7 Mar 2019 13:31:10 +0000 (13:31 +0000)]
Merge pull request #1868 from Yann-lms/zeromem_device_info

stm32mp1: zeromem device_info struct

5 years agoMerge pull request #1869 from pbeesley-arm/pb/wiki-import
Soby Mathew [Thu, 7 Mar 2019 13:19:52 +0000 (13:19 +0000)]
Merge pull request #1869 from pbeesley-arm/pb/wiki-import

Pb/wiki import

5 years agodoc: Add and correct headings for imported files
Paul Beesley [Tue, 5 Mar 2019 17:19:37 +0000 (17:19 +0000)]
doc: Add and correct headings for imported files

Some files imported from the wiki are missing RST section headers and
other files are using inconsistent characters for the same header level.

Change-Id: I318c843f9bc8fb40074ef90827b9acac06463662
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agodoc: Add missing CVE links to advisories
Paul Beesley [Tue, 5 Mar 2019 17:10:07 +0000 (17:10 +0000)]
doc: Add missing CVE links to advisories

Some security advisories did not contain a direct link to the CVE page
on mitre.org.

Change-Id: I80f8f27a25da3a76b564a3e49cafe5e253379f37
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agodoc: Update links within imported wiki content
Joel Hutton [Tue, 26 Feb 2019 16:23:54 +0000 (16:23 +0000)]
doc: Update links within imported wiki content

This patch covers two changes:

- Links that refer to GitHub are updated to point to the
  relevant content on trustedfirmware.org

- Internal links between documents have been updated,
  with the required .rst suffix being added or due
  to a change in the relative locations of the files.

Change-Id: Ibf87da7d2ece726d1c94a9b33a2bbc3129de7779
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agodoc: Migrate a subset of the GitHub wiki content
Joel Hutton [Mon, 25 Feb 2019 15:18:56 +0000 (15:18 +0000)]
doc: Migrate a subset of the GitHub wiki content

With the TF wiki being migrated from GitHub to trustedfirmware.org,
some documents will be moved into the docs/ directory within the
repository rather than remaining as external content. The
appropriate action has been decided on a per-document basis.

Change-Id: Id0f615f3418369256f30d2e34e354a115389d105
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agoBL31: Enable pointer authentication support in warm boot path
Alexei Fedorov [Wed, 6 Mar 2019 11:15:51 +0000 (11:15 +0000)]
BL31: Enable pointer authentication support in warm boot path

In the current Pointer Authentication support added in
commit b86048c40cb7d9ccd7aeac1681945676a6dc36ff
PAuth gets enabled in BL31 cold boot entrypoint only,
(see bl31_entrypoint() in bl31\aarch64\bl31_entrypoint.S)
but not in bl31_warm_entrypoint().
This results in EnIA bit [31] in SCTLR_EL3 not being set
and pointer authentication disabled after CPU wake-up event.

Fixes ARM-software/tf-issues#684

Change-Id: I27a67804764dfba2a6d72ca119ca2bcff4f536d6
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
5 years agoMerge pull request #1860 from pbeesley-arm/pb/todo-cleanup
Dimitris Papastamos [Thu, 7 Mar 2019 09:57:28 +0000 (09:57 +0000)]
Merge pull request #1860 from pbeesley-arm/pb/todo-cleanup

doc: Remove todo from example code

5 years agostm32mp1: zeromem device_info struct
Yann Gautier [Thu, 7 Mar 2019 09:54:34 +0000 (10:54 +0100)]
stm32mp1: zeromem device_info struct

The change of the structure highlighted the fact that all fields are not
correctly initialized with zeroes.

Replace the other memset in the function with zeromem, as it is faster.

Change-Id: I27f45a64e34637f79fa519f486bf5936721ef396
Signed-off-by: Yann Gautier <yann.gautier@st.com>
5 years agointel: Mailbox service un-accessible
Muhammad Hadi Asyrafi Abdul Halim [Thu, 7 Mar 2019 05:17:25 +0000 (13:17 +0800)]
intel: Mailbox service un-accessible
Change map region for device 2 from non-secure to secure

Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
5 years agodrivers: mmc: Fix some issues with MMC stack
Tien Hock, Loh [Thu, 7 Mar 2019 03:34:20 +0000 (11:34 +0800)]
drivers: mmc: Fix some issues with MMC stack

Some bugs in MMC stack needs to be fixed:
- scr cannot be local as this will cause cache issue when invalidating
after the read DMA transfer is completed
- ACMD41 needs to send voltage information in initialization, otherwise the
command is a query, thus will not initialize the controller
- when checking device state, retry until the retries counter goes to zero
before failing

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
5 years agoplat: intel: Improve ECC scrubbing performance
Tien Hock, Loh [Thu, 7 Mar 2019 03:28:05 +0000 (11:28 +0800)]
plat: intel: Improve ECC scrubbing performance

We should be using zeromem to scrub memory instead of memset. This would
improve the performance by 200x

Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
5 years agoRemove todo from example code
Paul Beesley [Fri, 25 Jan 2019 14:35:26 +0000 (14:35 +0000)]
Remove todo from example code

Keeping that in the docs is a bit untidy

Change-Id: Ia95246208cee48df1536b4317a8c896ab2c84fc2
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
5 years agoxlat_tables_v2: print xlat tables without recursion
David Pu [Mon, 25 Feb 2019 18:52:41 +0000 (10:52 -0800)]
xlat_tables_v2: print xlat tables without recursion

This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
order compared to recursive version.

fixes arm-software/tf-issues#664

Signed-off-by: David Pu <dpu@nvidia.com>
5 years agoxlat_tables_v2: unmap region without recursion.
David Pu [Fri, 22 Feb 2019 10:36:20 +0000 (02:36 -0800)]
xlat_tables_v2: unmap region without recursion.

This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
order compared to recursive version.

fixes arm-software/tf-issues#664

Signed-off-by: David Pu <dpu@nvidia.com>
5 years agoxlat_tables_v2: map region without recursion.
David Pu [Fri, 22 Feb 2019 10:31:40 +0000 (02:31 -0800)]
xlat_tables_v2: map region without recursion.

This patch uses an array on stack to save parent xlat table information when
traversing the xlat tables. It keeps exactly same xlat table traversal
order compared to recursive version.

fixes arm-software/tf-issues#664

Signed-off-by: David Pu <dpu@nvidia.com>
5 years agoMerge pull request #1847 from jts-arm/mbedtls
Antonio Niño Díaz [Tue, 5 Mar 2019 10:39:14 +0000 (10:39 +0000)]
Merge pull request #1847 from jts-arm/mbedtls

Remove Mbed TLS dependency from plat_bl_common.c

5 years agoMerge pull request #1855 from dp-arm/dp/ssbs
Antonio Niño Díaz [Tue, 5 Mar 2019 09:52:28 +0000 (09:52 +0000)]
Merge pull request #1855 from dp-arm/dp/ssbs

Ensure proper ID register is checked for feature detection

5 years agoMerge pull request #1853 from vwadekar/dummy_io_storage
Antonio Niño Díaz [Tue, 5 Mar 2019 09:52:14 +0000 (09:52 +0000)]
Merge pull request #1853 from vwadekar/dummy_io_storage

Tegra: dummy support for the io_storage backend

5 years agoMerge pull request #1854 from marex/arm/master/atf-v2.0.1
Antonio Niño Díaz [Tue, 5 Mar 2019 09:51:58 +0000 (09:51 +0000)]
Merge pull request #1854 from marex/arm/master/atf-v2.0.1

Arm/master/atf v2.0.1

5 years agoMerge pull request #1852 from sandrine-bailleux-arm/sb/fix-intmgt-doc
Antonio Niño Díaz [Mon, 4 Mar 2019 17:05:19 +0000 (17:05 +0000)]
Merge pull request #1852 from sandrine-bailleux-arm/sb/fix-intmgt-doc

Minor fixes in the interrupt framework design guide

5 years agoEnsure proper ID register is checked for feature detection
Dimitris Papastamos [Wed, 27 Feb 2019 11:46:48 +0000 (11:46 +0000)]
Ensure proper ID register is checked for feature detection

SSBS support is determined by checking ID_AA64PFR1_EL1 and not
ID_AA64PFR0_EL1.

Fixes ARM-Software/tf-issues#679

Change-Id: I8ecba13b850995ec6a6ede3c2a1e02e69a3a95db
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
5 years agorcar_gen3: drivers: pfc: Configure GP5_09 as input on ULCB
Marek Vasut [Sat, 2 Mar 2019 14:34:36 +0000 (15:34 +0100)]
rcar_gen3: drivers: pfc: Configure GP5_09 as input on ULCB

Configure the GPIO5 09 pin as input on the ULCB board by default,
since the pin is routed on the expansion connector and not connected
to anything by default.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
5 years agorcar_gen3: Add M3-W 3.0 support
Marek Vasut [Mon, 25 Feb 2019 13:57:08 +0000 (14:57 +0100)]
rcar_gen3: Add M3-W 3.0 support

Add support for the M3W 3.0 SoC and synchronize the upstream ATF with
Renesas downstream ATF release v2.0.1.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
5 years agorcar_gen3: Add myself as a maintainer
Marek Vasut [Wed, 20 Feb 2019 12:16:14 +0000 (13:16 +0100)]
rcar_gen3: Add myself as a maintainer

Add myself into the maintainers file to make Jorge's life easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
5 years agoMerge pull request #1844 from chandnich/rename_sgiclark
Antonio Niño Díaz [Mon, 4 Mar 2019 09:52:09 +0000 (09:52 +0000)]
Merge pull request #1844 from chandnich/rename_sgiclark

css/sgi: replace all uses of Clark with new product names

5 years agoMerge pull request #1851 from antonio-nino-diaz-arm/an/pauth
Antonio Niño Díaz [Mon, 4 Mar 2019 09:51:34 +0000 (09:51 +0000)]
Merge pull request #1851 from antonio-nino-diaz-arm/an/pauth

Correctly check for support of Address Authentication

5 years agoMerge pull request #1837 from spencercw/master
Antonio Niño Díaz [Mon, 4 Mar 2019 09:50:59 +0000 (09:50 +0000)]
Merge pull request #1837 from spencercw/master

imx: Configure CAAM job rings master ID for i.MX8MQ

5 years agoTegra: dummy support for the io_storage backend
Varun Wadekar [Fri, 1 Mar 2019 18:18:35 +0000 (10:18 -0800)]
Tegra: dummy support for the io_storage backend

This patch provides dummy macros and platform files to compile
the io_storage driver backend. This patch is necessary to
remove the "--unresolved=el3_panic" linker flag from Tegra's
makefiles and allow us to revert this workaround, previously
suggested by the ARM toolchain team.

The "--unresolved=el3_panic" flag actually was a big hammer that
allowed Tegra platforms to work with armlink previously but it
masks legit errors with the code as well.

Change-Id: I0421d35657823215229f84231896b84167f90548
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
5 years agoDoc: Fix internal links in interrupt framework design guide
Sandrine Bailleux [Mon, 25 Feb 2019 13:02:26 +0000 (14:02 +0100)]
Doc: Fix internal links in interrupt framework design guide

Some of the sections numbers have been incorrect since the document
structure has changed. Using references to sections rather than
hard-coded section numbers fixes the issue while making it more
future-proof to updates.

Change-Id: I80f5ab6a55a0073b1562a02ce2c9ec7d67cddfff
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
5 years agoDoc: Fix a formatting glitch
Sandrine Bailleux [Mon, 25 Feb 2019 09:33:51 +0000 (10:33 +0100)]
Doc: Fix a formatting glitch

While converting the interrupt framework design document from Markdown
to reStructuredText format, see commit 6f6257476754 ("Convert
documentation to reStructuredText"), the structure of the document was
changed and one of the titles got lost. Fix that.

Change-Id: Ib3e6c1f9f01f16108fde3b89ceb624bd54049d2f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
5 years agoMerge pull request #1842 from DavidPu/reduce_cyclomatic_complexity_metric
Antonio Niño Díaz [Fri, 1 Mar 2019 12:43:17 +0000 (12:43 +0000)]
Merge pull request #1842 from DavidPu/reduce_cyclomatic_complexity_metric

Reduce cyclomatic complexity metric

5 years agoMerge pull request #1815 from Anson-Huang/gic
Antonio Niño Díaz [Fri, 1 Mar 2019 12:42:33 +0000 (12:42 +0000)]
Merge pull request #1815 from Anson-Huang/gic

gic: make sure ProcessorSleep bit clear successfully

5 years agoMerge pull request #1751 from vwadekar/tegra-scatter-file-support
Antonio Niño Díaz [Fri, 1 Mar 2019 11:23:58 +0000 (11:23 +0000)]
Merge pull request #1751 from vwadekar/tegra-scatter-file-support

Tegra scatter file support

5 years agoMerge pull request #1849 from loumay-arm/lm/a73_errata
Antonio Niño Díaz [Fri, 1 Mar 2019 11:23:48 +0000 (11:23 +0000)]
Merge pull request #1849 from loumay-arm/lm/a73_errata

Cortex-A73: Implement workaround for errata 852427

5 years agoCorrectly check for support of Address Authentication
Antonio Nino Diaz [Fri, 1 Mar 2019 09:35:26 +0000 (09:35 +0000)]
Correctly check for support of Address Authentication

Check for both IMPLEMENTATION_DEFINED and Architected algorithms of
Address Authentication.

Change-Id: I209dcc6087172cfef7baf8d09e0454628f02cbd0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoMerge pull request #1845 from ambroise-arm/av/errata
Antonio Niño Díaz [Fri, 1 Mar 2019 09:17:27 +0000 (09:17 +0000)]
Merge pull request #1845 from ambroise-arm/av/errata

Apply workarounds for errata of Cortex-A53, A55 and A57

5 years agoMerge pull request #1846 from loumay-arm/lm/mpam
Antonio Niño Díaz [Fri, 1 Mar 2019 09:17:16 +0000 (09:17 +0000)]
Merge pull request #1846 from loumay-arm/lm/mpam

MPAM: enable MPAM EL2 traps

5 years agoMerge pull request #1848 from antonio-nino-diaz-arm/an/docs
Antonio Niño Díaz [Fri, 1 Mar 2019 09:16:58 +0000 (09:16 +0000)]
Merge pull request #1848 from antonio-nino-diaz-arm/an/docs

Minor changes to documentation and comments

5 years agoimx: make sure GIC redistributor is awake before initialization
Anson Huang [Fri, 1 Mar 2019 02:51:38 +0000 (10:51 +0800)]
imx: make sure GIC redistributor is awake before initialization

GICR_WAKER.ProcessorSleep can only be set to zero when:
— GICR_WAKER.Sleep bit[0] == 0.
— GICR_WAKER.Quiescent bit[31] == 0.

On some platforms, when system reboot with GIC in sleep
mode but with power ON, such as on NXP's i.MX8QM, Linux
kernel enters suspend but could be requested to reboot,
and GIC is in sleep mode and it is inside a power domain
which is ON in this scenario, when CPU reset, the GIC
driver trys to set CORE's redistributor interface to awake,
with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31]
both set, the ProcessorSleep bit[1] will never be clear
and cause system hang.

This patch makes sure GICR_WAKER.Sleep bit[0] and
GICR_WAKER.Quiescent bit[31] are both zeor before clearing
ProcessorSleep bit[1].

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
5 years agoxlat_tables_v2: find VA/idx with helper functions.
David Pu [Fri, 22 Feb 2019 10:23:57 +0000 (02:23 -0800)]
xlat_tables_v2: find VA/idx with helper functions.

This patch introduces 2 helper functions 'xlat_tables_find_start_va' and
'xlat_tables_va_to_index' to find the first VA and table index affected by the
specified mmap region. it reduces code duplication and cyclomatic code
complexity in xlat_tables_map/unmap_region functions.

Cyclomatic complexity calculated using 'Coverity'

fixes arm-software/tf-issues#673

Signed-off-by: David Pu <dpu@nvidia.com>
5 years agoxlat_tables_v2: get unmap action type with helper function.
David Pu [Fri, 22 Feb 2019 10:15:57 +0000 (02:15 -0800)]
xlat_tables_v2: get unmap action type with helper function.

This patch introduces helper function 'xlat_tables_unmap_region_action'
to get the required action type from given arguments when unmapping the
specified region.
it reduces cyclomatic code complexity in xlat_tables_unmap_region function.

Cyclomatic complexity calculated using 'Coverity'

fixes arm-software/tf-issues#673

Signed-off-by: David Pu <dpu@nvidia.com>
5 years agoRemove Mbed TLS dependency from plat_bl_common.c
John Tsichritzis [Thu, 28 Feb 2019 11:14:03 +0000 (11:14 +0000)]
Remove Mbed TLS dependency from plat_bl_common.c

Due to the shared Mbed TLS heap optimisation introduced in 6d01a463,
common code files were depending on Mbed TLS specific headers. This
dependency is now removed by moving the default, unoptimised heap
implementation inside the Mbed TLS specific files.

Change-Id: I11ea3eb4474f0d9b6cb79a2afd73a51a4a9b8994
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agoMinor changes to documentation and comments
Antonio Nino Diaz [Thu, 28 Feb 2019 13:35:21 +0000 (13:35 +0000)]
Minor changes to documentation and comments

Fix some typos and clarify some sentences.

Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoCortex-A73: Implement workaround for errata 852427
Louis Mayencourt [Wed, 27 Feb 2019 14:24:16 +0000 (14:24 +0000)]
Cortex-A73: Implement workaround for errata 852427

In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of the Diagnostic Register to prevent this.

Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoMPAM: enable MPAM EL2 traps
Louis Mayencourt [Mon, 11 Feb 2019 11:25:50 +0000 (11:25 +0000)]
MPAM: enable MPAM EL2 traps

Complete the MPAM enablement in TF-A for lower ELs by enabling the EL2
traps in MPAMHCR_EL2 and MPAM2_EL2.This prevents an
MPAM-unaware-hypervisor to be restricted by an MPAM-aware-guest.

Change-Id: I47bf3f833fa22baa590f83d49cc0e3f2974e698d
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoMerge pull request #1839 from loumay-arm/lm/a7x_errata
Antonio Niño Díaz [Thu, 28 Feb 2019 10:19:24 +0000 (10:19 +0000)]
Merge pull request #1839 from loumay-arm/lm/a7x_errata

Cortex-A73/75/76 errata workaround

5 years agojuno: Enable CPU errata workarounds
Ambroise Vincent [Fri, 22 Feb 2019 14:19:16 +0000 (14:19 +0000)]
juno: Enable CPU errata workarounds

Change-Id: I7593f5ed89b9ef13b510e2259c909838c64ec56c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A53: Workarounds for 819472, 824069 and 827319
Ambroise Vincent [Thu, 21 Feb 2019 14:16:24 +0000 (14:16 +0000)]
Cortex-A53: Workarounds for 819472, 824069 and 827319

The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.

Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A57: Implement workaround for erratum 817169
Ambroise Vincent [Thu, 21 Feb 2019 16:35:49 +0000 (16:35 +0000)]
Cortex-A57: Implement workaround for erratum 817169

Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A57: Implement workaround for erratum 814670
Ambroise Vincent [Thu, 21 Feb 2019 16:35:07 +0000 (16:35 +0000)]
Cortex-A57: Implement workaround for erratum 814670

Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A55: Implement workaround for erratum 903758
Ambroise Vincent [Thu, 21 Feb 2019 16:29:50 +0000 (16:29 +0000)]
Cortex-A55: Implement workaround for erratum 903758

Change-Id: I07e69061ba7a918cdfaaa83fa3a42dee910887d7
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A55: Implement workaround for erratum 846532
Ambroise Vincent [Thu, 21 Feb 2019 16:29:16 +0000 (16:29 +0000)]
Cortex-A55: Implement workaround for erratum 846532

Change-Id: Iacb6331c1f6b27340e71279f92f147ebbc71862f
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>