project/bcm63xx/atf.git
5 years agoMerge pull request #1855 from dp-arm/dp/ssbs
Antonio Niño Díaz [Tue, 5 Mar 2019 09:52:28 +0000 (09:52 +0000)]
Merge pull request #1855 from dp-arm/dp/ssbs

Ensure proper ID register is checked for feature detection

5 years agoMerge pull request #1853 from vwadekar/dummy_io_storage
Antonio Niño Díaz [Tue, 5 Mar 2019 09:52:14 +0000 (09:52 +0000)]
Merge pull request #1853 from vwadekar/dummy_io_storage

Tegra: dummy support for the io_storage backend

5 years agoMerge pull request #1854 from marex/arm/master/atf-v2.0.1
Antonio Niño Díaz [Tue, 5 Mar 2019 09:51:58 +0000 (09:51 +0000)]
Merge pull request #1854 from marex/arm/master/atf-v2.0.1

Arm/master/atf v2.0.1

5 years agoMerge pull request #1852 from sandrine-bailleux-arm/sb/fix-intmgt-doc
Antonio Niño Díaz [Mon, 4 Mar 2019 17:05:19 +0000 (17:05 +0000)]
Merge pull request #1852 from sandrine-bailleux-arm/sb/fix-intmgt-doc

Minor fixes in the interrupt framework design guide

5 years agoEnsure proper ID register is checked for feature detection
Dimitris Papastamos [Wed, 27 Feb 2019 11:46:48 +0000 (11:46 +0000)]
Ensure proper ID register is checked for feature detection

SSBS support is determined by checking ID_AA64PFR1_EL1 and not
ID_AA64PFR0_EL1.

Fixes ARM-Software/tf-issues#679

Change-Id: I8ecba13b850995ec6a6ede3c2a1e02e69a3a95db
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
5 years agorcar_gen3: drivers: pfc: Configure GP5_09 as input on ULCB
Marek Vasut [Sat, 2 Mar 2019 14:34:36 +0000 (15:34 +0100)]
rcar_gen3: drivers: pfc: Configure GP5_09 as input on ULCB

Configure the GPIO5 09 pin as input on the ULCB board by default,
since the pin is routed on the expansion connector and not connected
to anything by default.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
5 years agorcar_gen3: Add M3-W 3.0 support
Marek Vasut [Mon, 25 Feb 2019 13:57:08 +0000 (14:57 +0100)]
rcar_gen3: Add M3-W 3.0 support

Add support for the M3W 3.0 SoC and synchronize the upstream ATF with
Renesas downstream ATF release v2.0.1.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
5 years agorcar_gen3: Add myself as a maintainer
Marek Vasut [Wed, 20 Feb 2019 12:16:14 +0000 (13:16 +0100)]
rcar_gen3: Add myself as a maintainer

Add myself into the maintainers file to make Jorge's life easier.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
5 years agoMerge pull request #1844 from chandnich/rename_sgiclark
Antonio Niño Díaz [Mon, 4 Mar 2019 09:52:09 +0000 (09:52 +0000)]
Merge pull request #1844 from chandnich/rename_sgiclark

css/sgi: replace all uses of Clark with new product names

5 years agoMerge pull request #1851 from antonio-nino-diaz-arm/an/pauth
Antonio Niño Díaz [Mon, 4 Mar 2019 09:51:34 +0000 (09:51 +0000)]
Merge pull request #1851 from antonio-nino-diaz-arm/an/pauth

Correctly check for support of Address Authentication

5 years agoMerge pull request #1837 from spencercw/master
Antonio Niño Díaz [Mon, 4 Mar 2019 09:50:59 +0000 (09:50 +0000)]
Merge pull request #1837 from spencercw/master

imx: Configure CAAM job rings master ID for i.MX8MQ

5 years agoTegra: dummy support for the io_storage backend
Varun Wadekar [Fri, 1 Mar 2019 18:18:35 +0000 (10:18 -0800)]
Tegra: dummy support for the io_storage backend

This patch provides dummy macros and platform files to compile
the io_storage driver backend. This patch is necessary to
remove the "--unresolved=el3_panic" linker flag from Tegra's
makefiles and allow us to revert this workaround, previously
suggested by the ARM toolchain team.

The "--unresolved=el3_panic" flag actually was a big hammer that
allowed Tegra platforms to work with armlink previously but it
masks legit errors with the code as well.

Change-Id: I0421d35657823215229f84231896b84167f90548
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
5 years agoDoc: Fix internal links in interrupt framework design guide
Sandrine Bailleux [Mon, 25 Feb 2019 13:02:26 +0000 (14:02 +0100)]
Doc: Fix internal links in interrupt framework design guide

Some of the sections numbers have been incorrect since the document
structure has changed. Using references to sections rather than
hard-coded section numbers fixes the issue while making it more
future-proof to updates.

Change-Id: I80f5ab6a55a0073b1562a02ce2c9ec7d67cddfff
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
5 years agoDoc: Fix a formatting glitch
Sandrine Bailleux [Mon, 25 Feb 2019 09:33:51 +0000 (10:33 +0100)]
Doc: Fix a formatting glitch

While converting the interrupt framework design document from Markdown
to reStructuredText format, see commit 6f6257476754 ("Convert
documentation to reStructuredText"), the structure of the document was
changed and one of the titles got lost. Fix that.

Change-Id: Ib3e6c1f9f01f16108fde3b89ceb624bd54049d2f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
5 years agoMerge pull request #1842 from DavidPu/reduce_cyclomatic_complexity_metric
Antonio Niño Díaz [Fri, 1 Mar 2019 12:43:17 +0000 (12:43 +0000)]
Merge pull request #1842 from DavidPu/reduce_cyclomatic_complexity_metric

Reduce cyclomatic complexity metric

5 years agoMerge pull request #1815 from Anson-Huang/gic
Antonio Niño Díaz [Fri, 1 Mar 2019 12:42:33 +0000 (12:42 +0000)]
Merge pull request #1815 from Anson-Huang/gic

gic: make sure ProcessorSleep bit clear successfully

5 years agoMerge pull request #1751 from vwadekar/tegra-scatter-file-support
Antonio Niño Díaz [Fri, 1 Mar 2019 11:23:58 +0000 (11:23 +0000)]
Merge pull request #1751 from vwadekar/tegra-scatter-file-support

Tegra scatter file support

5 years agoMerge pull request #1849 from loumay-arm/lm/a73_errata
Antonio Niño Díaz [Fri, 1 Mar 2019 11:23:48 +0000 (11:23 +0000)]
Merge pull request #1849 from loumay-arm/lm/a73_errata

Cortex-A73: Implement workaround for errata 852427

5 years agoCorrectly check for support of Address Authentication
Antonio Nino Diaz [Fri, 1 Mar 2019 09:35:26 +0000 (09:35 +0000)]
Correctly check for support of Address Authentication

Check for both IMPLEMENTATION_DEFINED and Architected algorithms of
Address Authentication.

Change-Id: I209dcc6087172cfef7baf8d09e0454628f02cbd0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoMerge pull request #1845 from ambroise-arm/av/errata
Antonio Niño Díaz [Fri, 1 Mar 2019 09:17:27 +0000 (09:17 +0000)]
Merge pull request #1845 from ambroise-arm/av/errata

Apply workarounds for errata of Cortex-A53, A55 and A57

5 years agoMerge pull request #1846 from loumay-arm/lm/mpam
Antonio Niño Díaz [Fri, 1 Mar 2019 09:17:16 +0000 (09:17 +0000)]
Merge pull request #1846 from loumay-arm/lm/mpam

MPAM: enable MPAM EL2 traps

5 years agoMerge pull request #1848 from antonio-nino-diaz-arm/an/docs
Antonio Niño Díaz [Fri, 1 Mar 2019 09:16:58 +0000 (09:16 +0000)]
Merge pull request #1848 from antonio-nino-diaz-arm/an/docs

Minor changes to documentation and comments

5 years agoimx: make sure GIC redistributor is awake before initialization
Anson Huang [Fri, 1 Mar 2019 02:51:38 +0000 (10:51 +0800)]
imx: make sure GIC redistributor is awake before initialization

GICR_WAKER.ProcessorSleep can only be set to zero when:
— GICR_WAKER.Sleep bit[0] == 0.
— GICR_WAKER.Quiescent bit[31] == 0.

On some platforms, when system reboot with GIC in sleep
mode but with power ON, such as on NXP's i.MX8QM, Linux
kernel enters suspend but could be requested to reboot,
and GIC is in sleep mode and it is inside a power domain
which is ON in this scenario, when CPU reset, the GIC
driver trys to set CORE's redistributor interface to awake,
with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31]
both set, the ProcessorSleep bit[1] will never be clear
and cause system hang.

This patch makes sure GICR_WAKER.Sleep bit[0] and
GICR_WAKER.Quiescent bit[31] are both zeor before clearing
ProcessorSleep bit[1].

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
5 years agoxlat_tables_v2: find VA/idx with helper functions.
David Pu [Fri, 22 Feb 2019 10:23:57 +0000 (02:23 -0800)]
xlat_tables_v2: find VA/idx with helper functions.

This patch introduces 2 helper functions 'xlat_tables_find_start_va' and
'xlat_tables_va_to_index' to find the first VA and table index affected by the
specified mmap region. it reduces code duplication and cyclomatic code
complexity in xlat_tables_map/unmap_region functions.

Cyclomatic complexity calculated using 'Coverity'

fixes arm-software/tf-issues#673

Signed-off-by: David Pu <dpu@nvidia.com>
5 years agoxlat_tables_v2: get unmap action type with helper function.
David Pu [Fri, 22 Feb 2019 10:15:57 +0000 (02:15 -0800)]
xlat_tables_v2: get unmap action type with helper function.

This patch introduces helper function 'xlat_tables_unmap_region_action'
to get the required action type from given arguments when unmapping the
specified region.
it reduces cyclomatic code complexity in xlat_tables_unmap_region function.

Cyclomatic complexity calculated using 'Coverity'

fixes arm-software/tf-issues#673

Signed-off-by: David Pu <dpu@nvidia.com>
5 years agoMinor changes to documentation and comments
Antonio Nino Diaz [Thu, 28 Feb 2019 13:35:21 +0000 (13:35 +0000)]
Minor changes to documentation and comments

Fix some typos and clarify some sentences.

Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoCortex-A73: Implement workaround for errata 852427
Louis Mayencourt [Wed, 27 Feb 2019 14:24:16 +0000 (14:24 +0000)]
Cortex-A73: Implement workaround for errata 852427

In AArch32, execution of 2 instructions with opposite condition code
might lead to either a data corruption or a CPU deadlock. Set the bit
12 of the Diagnostic Register to prevent this.

Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoMPAM: enable MPAM EL2 traps
Louis Mayencourt [Mon, 11 Feb 2019 11:25:50 +0000 (11:25 +0000)]
MPAM: enable MPAM EL2 traps

Complete the MPAM enablement in TF-A for lower ELs by enabling the EL2
traps in MPAMHCR_EL2 and MPAM2_EL2.This prevents an
MPAM-unaware-hypervisor to be restricted by an MPAM-aware-guest.

Change-Id: I47bf3f833fa22baa590f83d49cc0e3f2974e698d
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoMerge pull request #1839 from loumay-arm/lm/a7x_errata
Antonio Niño Díaz [Thu, 28 Feb 2019 10:19:24 +0000 (10:19 +0000)]
Merge pull request #1839 from loumay-arm/lm/a7x_errata

Cortex-A73/75/76 errata workaround

5 years agojuno: Enable CPU errata workarounds
Ambroise Vincent [Fri, 22 Feb 2019 14:19:16 +0000 (14:19 +0000)]
juno: Enable CPU errata workarounds

Change-Id: I7593f5ed89b9ef13b510e2259c909838c64ec56c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A53: Workarounds for 819472, 824069 and 827319
Ambroise Vincent [Thu, 21 Feb 2019 14:16:24 +0000 (14:16 +0000)]
Cortex-A53: Workarounds for 819472, 824069 and 827319

The workarounds for these errata are so closely related that it is
better to only have one patch to make it easier to understand.

Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A57: Implement workaround for erratum 817169
Ambroise Vincent [Thu, 21 Feb 2019 16:35:49 +0000 (16:35 +0000)]
Cortex-A57: Implement workaround for erratum 817169

Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A57: Implement workaround for erratum 814670
Ambroise Vincent [Thu, 21 Feb 2019 16:35:07 +0000 (16:35 +0000)]
Cortex-A57: Implement workaround for erratum 814670

Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A55: Implement workaround for erratum 903758
Ambroise Vincent [Thu, 21 Feb 2019 16:29:50 +0000 (16:29 +0000)]
Cortex-A55: Implement workaround for erratum 903758

Change-Id: I07e69061ba7a918cdfaaa83fa3a42dee910887d7
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A55: Implement workaround for erratum 846532
Ambroise Vincent [Thu, 21 Feb 2019 16:29:16 +0000 (16:29 +0000)]
Cortex-A55: Implement workaround for erratum 846532

Change-Id: Iacb6331c1f6b27340e71279f92f147ebbc71862f
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A55: Implement workaround for erratum 798797
Ambroise Vincent [Thu, 21 Feb 2019 16:27:34 +0000 (16:27 +0000)]
Cortex-A55: Implement workaround for erratum 798797

Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A55: Implement workaround for erratum 778703
Ambroise Vincent [Thu, 21 Feb 2019 16:25:37 +0000 (16:25 +0000)]
Cortex-A55: Implement workaround for erratum 778703

Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agoCortex-A55: Implement workaround for erratum 768277
Ambroise Vincent [Thu, 21 Feb 2019 16:20:43 +0000 (16:20 +0000)]
Cortex-A55: Implement workaround for erratum 768277

Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
5 years agocss/sgi: replace all uses of Clark with new product names
Chandni Cherukuri [Wed, 27 Feb 2019 08:29:11 +0000 (13:59 +0530)]
css/sgi: replace all uses of Clark with new product names

Replace all uses of 'SGI_CLARK' with 'RD_N1E1_EDGE' and
'SGI_CLARK_HELIOS' with 'RD_E1_EDGE' as per the updated product
names

Change-Id: Ib8136e421b1a46da1e5df58c6b1432d5c78d279b
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
5 years agoMerge pull request #1841 from antonio-nino-diaz-arm/an/fix-gensmc
Antonio Niño Díaz [Wed, 27 Feb 2019 17:15:13 +0000 (17:15 +0000)]
Merge pull request #1841 from antonio-nino-diaz-arm/an/fix-gensmc

trusty: Include file with GIC definitions

5 years agoTegra: Support for scatterfile for the BL31 image
Varun Wadekar [Fri, 11 Jan 2019 22:47:48 +0000 (14:47 -0800)]
Tegra: Support for scatterfile for the BL31 image

This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.

In order to enable the scatterfile usage the following changes
have been made:

* provide mapping for ld.S symbols in bl_common.h
* include bl_common.h from all the affected files
* update the makefile rules to use the scatterfile and armlink
  to compile BL31
* update pubsub.h to add sections to the scatterfile

NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.

Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
5 years agotrusty: Include file with GIC definitions
Antonio Nino Diaz [Wed, 27 Feb 2019 15:11:18 +0000 (15:11 +0000)]
trusty: Include file with GIC definitions

The GIC definitions used in this file have to be provided by the platform
but platform_def.h wasn't included.

Change-Id: I858cdf7e60c50577c8e798d64ec2cbc4f067f33b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoMerge pull request #1829 from antonio-nino-diaz-arm/an/pauth
Antonio Niño Díaz [Wed, 27 Feb 2019 14:32:35 +0000 (14:32 +0000)]
Merge pull request #1829 from antonio-nino-diaz-arm/an/pauth

Add Pointer Authentication (ARMv8.3-PAuth) support to the TF

5 years agoMerge pull request #1840 from grandpaul/rpi3-sdhost-improve1
Antonio Niño Díaz [Wed, 27 Feb 2019 14:32:21 +0000 (14:32 +0000)]
Merge pull request #1840 from grandpaul/rpi3-sdhost-improve1

RaspberryPi3 sdhost driver improvement.

5 years agoTSP: Enable pointer authentication support
Antonio Nino Diaz [Tue, 26 Feb 2019 11:41:03 +0000 (11:41 +0000)]
TSP: Enable pointer authentication support

The size increase after enabling options related to ARMv8.3-PAuth is:

+----------------------------+-------+-------+-------+--------+
|                            |  text |  bss  |  data | rodata |
+----------------------------+-------+-------+-------+--------+
| CTX_INCLUDE_PAUTH_REGS = 1 |   +40 |   +0  |   +0  |   +0   |
|                            |  0.4% |       |       |        |
+----------------------------+-------+-------+-------+--------+
| ENABLE_PAUTH = 1           |  +352 |    +0 |  +16  |   +0   |
|                            |  3.1% |       | 15.8% |        |
+----------------------------+-------+-------+-------+--------+

Results calculated with the following build configuration:

    make PLAT=fvp SPD=tspd DEBUG=1 \
    SDEI_SUPPORT=1                 \
    EL3_EXCEPTION_HANDLING=1       \
    TSP_NS_INTR_ASYNC_PREEMPT=1    \
    CTX_INCLUDE_PAUTH_REGS=1       \
    ENABLE_PAUTH=1

Change-Id: I6cc1fe0b2345c547dcef66f98758c4eb55fe5ee4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoBL31: Enable pointer authentication support
Antonio Nino Diaz [Thu, 31 Jan 2019 11:01:26 +0000 (11:01 +0000)]
BL31: Enable pointer authentication support

The size increase after enabling options related to ARMv8.3-PAuth is:

+----------------------------+-------+-------+-------+--------+
|                            |  text |  bss  |  data | rodata |
+----------------------------+-------+-------+-------+--------+
| CTX_INCLUDE_PAUTH_REGS = 1 |  +192 | +1536 |   +0  |   +0   |
|                            |  0.3% |  3.1% |       |        |
+----------------------------+-------+-------+-------+--------+
| ENABLE_PAUTH = 1           | +1848 | +1536 |  +16  |   +0   |
|                            |  3.3% |  3.1% |  3.1% |        |
+----------------------------+-------+-------+-------+--------+

Results calculated with the following build configuration:

    make PLAT=fvp SPD=tspd DEBUG=1 \
    SDEI_SUPPORT=1                 \
    EL3_EXCEPTION_HANDLING=1       \
    TSP_NS_INTR_ASYNC_PREEMPT=1    \
    CTX_INCLUDE_PAUTH_REGS=1       \
    ENABLE_PAUTH=1

Change-Id: I43db7e509a4f39da6599ec2faa690d197573ec1b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoBL2_AT_EL3: Enable pointer authentication support
Antonio Nino Diaz [Thu, 31 Jan 2019 17:40:44 +0000 (17:40 +0000)]
BL2_AT_EL3: Enable pointer authentication support

The size increase after enabling options related to ARMv8.3-PAuth is:

+----------------------------+-------+-------+-------+--------+
|                            |  text |  bss  |  data | rodata |
+----------------------------+-------+-------+-------+--------+
| CTX_INCLUDE_PAUTH_REGS = 1 |   +44 |   +0  |   +0  |   +0   |
|                            |  0.2% |       |       |        |
+----------------------------+-------+-------+-------+--------+
| ENABLE_PAUTH = 1           |  +712 |   +0  |  +16  |   +0   |
|                            |  3.1% |       |  0.9% |        |
+----------------------------+-------+-------+-------+--------+

The results are valid for the following build configuration:

    make PLAT=fvp SPD=tspd DEBUG=1 \
    BL2_AT_EL3=1                   \
    CTX_INCLUDE_PAUTH_REGS=1       \
    ENABLE_PAUTH=1

Change-Id: I1c0616e7dea30962a92b4fd113428bc30a018320
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoBL2: Enable pointer authentication support
Antonio Nino Diaz [Thu, 31 Jan 2019 10:48:47 +0000 (10:48 +0000)]
BL2: Enable pointer authentication support

The size increase after enabling options related to ARMv8.3-PAuth is:

+----------------------------+-------+-------+-------+--------+
|                            |  text |  bss  |  data | rodata |
+----------------------------+-------+-------+-------+--------+
| CTX_INCLUDE_PAUTH_REGS = 1 |   +40 |   +0  |   +0  |   +0   |
|                            |  0.2% |       |       |        |
+----------------------------+-------+-------+-------+--------+
| ENABLE_PAUTH = 1           |  +664 |   +0  |  +16  |   +0   |
|                            |  3.1% |       |  0.9% |        |
+----------------------------+-------+-------+-------+--------+

Results calculated with the following build configuration:

    make PLAT=fvp SPD=tspd DEBUG=1 \
    SDEI_SUPPORT=1                 \
    EL3_EXCEPTION_HANDLING=1       \
    TSP_NS_INTR_ASYNC_PREEMPT=1    \
    CTX_INCLUDE_PAUTH_REGS=1       \
    ENABLE_PAUTH=1

The changes for BL2_AT_EL3 aren't done in this commit.

Change-Id: I8c803b40c7160525a06173bc6cdca21c4505837d
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoBL1: Enable pointer authentication support
Antonio Nino Diaz [Wed, 30 Jan 2019 20:29:50 +0000 (20:29 +0000)]
BL1: Enable pointer authentication support

The size increase after enabling options related to ARMv8.3-PAuth is:

+----------------------------+-------+-------+-------+--------+
|                            |  text |  bss  |  data | rodata |
+----------------------------+-------+-------+-------+--------+
| CTX_INCLUDE_PAUTH_REGS = 1 |  +108 |  +192 |   +0  |   +0   |
|                            |  0.5% |  0.8% |       |        |
+----------------------------+-------+-------+-------+--------+
| ENABLE_PAUTH = 1           |  +748 |  +192 |  +16  |   +0   |
|                            |  3.7% |  0.8% |  7.0% |        |
+----------------------------+-------+-------+-------+--------+

Results calculated with the following build configuration:

    make PLAT=fvp SPD=tspd DEBUG=1 \
    SDEI_SUPPORT=1                 \
    EL3_EXCEPTION_HANDLING=1       \
    TSP_NS_INTR_ASYNC_PREEMPT=1    \
    CTX_INCLUDE_PAUTH_REGS=1       \
    ENABLE_PAUTH=1

Change-Id: I3a7d02feb6a6d212be32a01432b0c7c1a261f567
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoplat/arm: Implement ARMv8.3-PAuth interfaces
Antonio Nino Diaz [Thu, 31 Jan 2019 11:01:10 +0000 (11:01 +0000)]
plat/arm: Implement ARMv8.3-PAuth interfaces

This feature is only supported on FVP.

Change-Id: I4e265610211d92a84bd2773c34acfbe02a1a1826
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoAdd support for pointer authentication
Antonio Nino Diaz [Tue, 19 Feb 2019 11:53:51 +0000 (11:53 +0000)]
Add support for pointer authentication

The previous commit added the infrastructure to load and save
ARMv8.3-PAuth registers during Non-secure <-> Secure world switches, but
didn't actually enable pointer authentication in the firmware.

This patch adds the functionality needed for platforms to provide
authentication keys for the firmware, and a new option (ENABLE_PAUTH) to
enable pointer authentication in the firmware itself. This option is
disabled by default, and it requires CTX_INCLUDE_PAUTH_REGS to be
enabled.

Change-Id: I35127ec271e1198d43209044de39fa712ef202a5
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoMerge pull request #1838 from chandnich/rename
Antonio Niño Díaz [Wed, 27 Feb 2019 11:15:12 +0000 (11:15 +0000)]
Merge pull request #1838 from chandnich/rename

Apply official names to SGI-Clark Platforms

5 years agoAdd ARMv8.3-PAuth registers to CPU context
Antonio Nino Diaz [Thu, 31 Jan 2019 11:58:00 +0000 (11:58 +0000)]
Add ARMv8.3-PAuth registers to CPU context

ARMv8.3-PAuth adds functionality that supports address authentication of
the contents of a register before that register is used as the target of
an indirect branch, or as a load.

This feature is supported only in AArch64 state.

This feature is mandatory in ARMv8.3 implementations.

This feature adds several registers to EL1. A new option called
CTX_INCLUDE_PAUTH_REGS has been added to select if the TF needs to save
them during Non-secure <-> Secure world switches. This option must be
enabled if the hardware has the registers or the values will be leaked
during world switches.

To prevent leaks, this patch also disables pointer authentication in the
Secure world if CTX_INCLUDE_PAUTH_REGS is 0. Any attempt to use it will
be trapped in EL3.

Change-Id: I27beba9907b9a86c6df1d0c5bf6180c972830855
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoCleanup context handling library
Antonio Nino Diaz [Wed, 30 Jan 2019 20:41:31 +0000 (20:41 +0000)]
Cleanup context handling library

Minor style cleanup.

Change-Id: Ief19dece41a989e2e8157859a265701549f6c585
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoMerge pull request #1834 from thloh85-intel/s10_bl31
Antonio Niño Díaz [Wed, 27 Feb 2019 10:22:34 +0000 (10:22 +0000)]
Merge pull request #1834 from thloh85-intel/s10_bl31

plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform

5 years agoMerge pull request #1831 from antonio-nino-diaz-arm/an/sccd
Antonio Niño Díaz [Wed, 27 Feb 2019 09:21:42 +0000 (09:21 +0000)]
Merge pull request #1831 from antonio-nino-diaz-arm/an/sccd

Disable processor Cycle Counting in Secure state

5 years agoMerge pull request #1826 from smaeul/allwinner
Antonio Niño Díaz [Wed, 27 Feb 2019 09:21:31 +0000 (09:21 +0000)]
Merge pull request #1826 from smaeul/allwinner

allwinner: A few minor improvements

5 years agoboard/rde1edge: rename sgiclarkh to rde1edge
Chandni Cherukuri [Fri, 22 Feb 2019 11:14:49 +0000 (16:44 +0530)]
board/rde1edge: rename sgiclarkh to rde1edge

Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarkh' with
'rde1edge' as per the updated product names.

Change-Id: I14e9b0332851798531de21d70eb54f1e5557a7bd
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
5 years agoboard/rdn1edge: rename sgiclarka to rdn1edge
Chandni Cherukuri [Fri, 22 Feb 2019 08:11:03 +0000 (13:41 +0530)]
board/rdn1edge: rename sgiclarka to rdn1edge

Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarka' with
'rdn1edge' as per the updated product names.

Change-Id: Idbc157c73477ec32f507ba2d4a4e907d8813374c
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
5 years agorpi3: sdhost: SDHost driver improvement
Ying-Chun Liu (PaulLiu) [Tue, 12 Feb 2019 14:41:06 +0000 (22:41 +0800)]
rpi3: sdhost: SDHost driver improvement

This commit improves the SDHost driver for RPi3 as following:
 * Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on
   block reading.
 * In some low probability that SEND_OP_COND might results CRC7
   error. We can consider that the command runs correctly. We don't
   need to retry this command so removing the code for retry.
 * Using MMC_BUS_WIDTH_1 as MMC default value to improve the stability.
 * Increase the clock to 50Mhz in data mode to speed up the io.
 * Change the pull resistors configuration to gain more stability.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
5 years agoAdd workaround for errata 1073348 for Cortex-A76
Louis Mayencourt [Mon, 25 Feb 2019 15:17:44 +0000 (15:17 +0000)]
Add workaround for errata 1073348 for Cortex-A76

Concurrent instruction TLB miss and mispredicted return instruction
might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to
prevent this.

Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoAdd workaround for errata 1220197 for Cortex-A76
Louis Mayencourt [Mon, 25 Feb 2019 11:37:38 +0000 (11:37 +0000)]
Add workaround for errata 1220197 for Cortex-A76

Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.

Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoAdd workaround for errata 1130799 for Cortex-A76
Louis Mayencourt [Thu, 21 Feb 2019 17:35:07 +0000 (17:35 +0000)]
Add workaround for errata 1130799 for Cortex-A76

TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page
aggregated address translation data in the L2 TLB might cause
corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to
prevent this.

Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoAdd workaround for errata 790748 for Cortex-A75
Louis Mayencourt [Mon, 25 Feb 2019 14:57:57 +0000 (14:57 +0000)]
Add workaround for errata 790748 for Cortex-A75

Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.

Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoAdd workaround for errata 764081 of Cortex-A75
Louis Mayencourt [Wed, 20 Feb 2019 12:11:41 +0000 (12:11 +0000)]
Add workaround for errata 764081 of Cortex-A75

Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.

Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoAdd workaround for errata 855423 of Cortex-A73
Louis Mayencourt [Thu, 21 Feb 2019 16:38:16 +0000 (16:38 +0000)]
Add workaround for errata 855423 of Cortex-A73

Broadcast maintainance operations might not be correctly synchronized
between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this.

Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
5 years agoplat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform
Tien Hock, Loh [Tue, 26 Feb 2019 01:25:14 +0000 (09:25 +0800)]
plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform

This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox calls for FPGA reconfiguration

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
5 years agoMerge pull request #1836 from Yann-lms/docs_and_m4
Antonio Niño Díaz [Fri, 22 Feb 2019 15:23:52 +0000 (15:23 +0000)]
Merge pull request #1836 from Yann-lms/docs_and_m4

Update documentation for STM32MP1 and add Cortex-M4 support

5 years agoimx: Configure CAAM job rings master ID for i.MX8MQ
Chris Spencer [Thu, 21 Feb 2019 08:35:26 +0000 (08:35 +0000)]
imx: Configure CAAM job rings master ID for i.MX8MQ

For i.MX8MQ B0 revision the default configuration of JRaMID is not valid
to allow the kernel to use the CAAM job rings. This patch sets the
master ID of the Cortex A in the JRaMID registers.

Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk>
5 years agoMerge pull request #1835 from jts-arm/rename
Antonio Niño Díaz [Fri, 22 Feb 2019 13:05:37 +0000 (13:05 +0000)]
Merge pull request #1835 from jts-arm/rename

Apply official names to new Arm Neoverse cores

5 years agoMerge pull request #1828 from uarif1/master
Antonio Niño Díaz [Thu, 21 Feb 2019 13:47:08 +0000 (13:47 +0000)]
Merge pull request #1828 from uarif1/master

Introduce Versatile Express FVP platform to arm-trusted-firmware.

5 years agoMerge pull request #1833 from marex/arm/master/pci-v2.0.0
Antonio Niño Díaz [Thu, 21 Feb 2019 13:46:39 +0000 (13:46 +0000)]
Merge pull request #1833 from marex/arm/master/pci-v2.0.0

rcar_gen3: plat: Prevent PCIe hang during L1X config access

5 years agostm32mp1: add minimal support for co-processor Cortex-M4
Yann Gautier [Fri, 15 Feb 2019 16:33:27 +0000 (17:33 +0100)]
stm32mp1: add minimal support for co-processor Cortex-M4

STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minimal security features to allow communications between A7 and M4
are also added.

Change-Id: I60417e244a476f60a2758f4969700b2684056665
Signed-off-by: Yann Gautier <yann.gautier@st.com>
5 years agodocs: stm32mp1: add links to documentation
Yann Gautier [Wed, 20 Feb 2019 16:34:16 +0000 (17:34 +0100)]
docs: stm32mp1: add links to documentation

A link to st.com page describing STM32MP1 is added.
Add the information about Cortex-M4 embedded in STM32MP1.
Correct typo for u-boot command.

Change-Id: Ie900f6ee59461c5e7ad8a8b06854abaf41fca3ce
Signed-off-by: Yann Gautier <yann.gautier@st.com>
5 years agorcar_gen3: plat: Prevent PCIe hang during L1X config access
Marek Vasut [Mon, 11 Feb 2019 23:09:46 +0000 (00:09 +0100)]
rcar_gen3: plat: Prevent PCIe hang during L1X config access

In case the PCIe controller receives a L1_Enter_PM DLLP, it will
disable the internal PLLs. The system software cannot predict it
and can attempt to perform device config space access across the
PCIe link while the controller is in this transitional state. If
such condition happens, the PCIe controller register access will
trigger ARM64 SError exception.

This patch adds checks for which PCIe controller is enabled,
checks whether the PCIe controller is in such a transitional
state and if so, first completes the transition and then restarts
the instruction which caused the SError.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
5 years agoMerge pull request #1832 from jts-arm/docs
Antonio Niño Díaz [Wed, 20 Feb 2019 14:21:34 +0000 (14:21 +0000)]
Merge pull request #1832 from jts-arm/docs

docs: Document romlib design

5 years agoMerge pull request #1830 from antonio-nino-diaz-arm/an/fix-fw-design
Antonio Niño Díaz [Wed, 20 Feb 2019 14:21:25 +0000 (14:21 +0000)]
Merge pull request #1830 from antonio-nino-diaz-arm/an/fix-fw-design

docs: Update documentation about ARMv8.2-TTCNP

5 years agoDocumentation for Versatile Express Fixed Virtual Platforms
Usama Arif [Tue, 5 Feb 2019 15:44:17 +0000 (15:44 +0000)]
Documentation for Versatile Express Fixed Virtual Platforms

This documentation contains information about the boot sequence,
code location and build procedure for fvp_ve platform.

Change-Id: I339903f663cc625cfabc75ed8e4accb8b2c3917c
Signed-off-by: Usama Arif <usama.arif@arm.com>
5 years agoplat/arm: Support for Cortex A5 in FVP Versatile Express platform
Usama Arif [Wed, 12 Dec 2018 17:14:29 +0000 (17:14 +0000)]
plat/arm: Support for Cortex A5 in FVP Versatile Express platform

Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex a5
is also included.

Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678
Signed-off-by: Usama Arif <usama.arif@arm.com>
5 years agoDivision functionality for cores that dont have divide hardware.
Usama Arif [Wed, 12 Dec 2018 17:08:33 +0000 (17:08 +0000)]
Division functionality for cores that dont have divide hardware.

Cortex a5 doesnt support hardware division such as sdiv and udiv commands.
This commit adds a software division function in assembly as well as include
appropriate files for software divison.

The software division algorithm is a modified version obtained from:
http://www.keil.com/support/man/docs/armasm/armasm_dom1359731155623.htm

Change-Id: Ib405a330da5f1cea1e68e07e7b520edeef9e2652
Signed-off-by: Usama Arif <usama.arif@arm.com>
5 years agoARMv7: support non-LPAE mapping (not xlat_v2)
Etienne Carriere [Tue, 24 Oct 2017 20:47:59 +0000 (22:47 +0200)]
ARMv7: support non-LPAE mapping (not xlat_v2)

Support 32bit descriptor MMU table. This is required by ARMv7
architectures that do not support the Large Page Address Extensions.

nonlpae_tables.c source file is dumped from the OP-TEE project:
core_mmu_armv7.c and related header files.

Change-Id: If912d66c374290c49c5a1211ce4c5c27b2d7dc60
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Usama Arif <usama.arif@arm.com>
5 years agoplat/arm: Introduce FVP Versatile Express platform.
Usama Arif [Fri, 30 Nov 2018 15:43:56 +0000 (15:43 +0000)]
plat/arm: Introduce FVP Versatile Express platform.

This patch adds support for Versatile express FVP (Fast models).
Versatile express is a family of platforms that are based on ARM v7.
Currently this port has only been tested on Cortex A7, although it
should work with other ARM V7 cores that support LPAE, generic timers,
VFP and hardware divide. Future patches will support other
cores like Cortex A5 that dont support features like LPAE
and hardware divide. This platform is tested on and only expected to
work on single core models.

Change-Id: I10893af65b8bb64da7b3bd851cab8231718e61dd
Signed-off-by: Usama Arif <usama.arif@arm.com>
5 years agodocs: Document romlib design
Sathees Balya [Wed, 30 Jan 2019 15:56:44 +0000 (15:56 +0000)]
docs: Document romlib design

Change-Id: I2b75be16f452a8ab7c2445ccd519fb057a135812
Co-authored-by: John Tsichritzis <john.tsichritzis@arm.com>
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agodocs: Update documentation about ARMv8.2-TTCNP
Antonio Nino Diaz [Tue, 19 Feb 2019 13:14:06 +0000 (13:14 +0000)]
docs: Update documentation about ARMv8.2-TTCNP

Commit 2559b2c8256f ("xlat v2: Dynamically detect need for CnP bit")
modified the code to convert the compile-time check for ARMv8.2-TTCNP to
a runtime check, but forgot to update the documentation associated to it.

Change-Id: I6d33a4de389d976dbdcce65d8fdf138959530669
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoRename Cortex-Helios to Neoverse E1
John Tsichritzis [Tue, 19 Feb 2019 14:01:55 +0000 (14:01 +0000)]
Rename Cortex-Helios to Neoverse E1

Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agoRename Cortex-Helios filenames to Neoverse E1
John Tsichritzis [Tue, 19 Feb 2019 13:54:21 +0000 (13:54 +0000)]
Rename Cortex-Helios filenames to Neoverse E1

Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agoRename Cortex-Ares to Neoverse N1
John Tsichritzis [Tue, 19 Feb 2019 13:49:06 +0000 (13:49 +0000)]
Rename Cortex-Ares to Neoverse N1

Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agoRename Cortex-Ares filenames to Neoverse N1
John Tsichritzis [Tue, 19 Feb 2019 13:48:44 +0000 (13:48 +0000)]
Rename Cortex-Ares filenames to Neoverse N1

Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
5 years agoMerge pull request #1825 from antonio-nino-diaz-arm/an/csv2
Antonio Niño Díaz [Tue, 19 Feb 2019 10:04:00 +0000 (10:04 +0000)]
Merge pull request #1825 from antonio-nino-diaz-arm/an/csv2

Update macro to check need for CVE-2017-5715 mitigation

5 years agoDisable processor Cycle Counting in Secure state
Antonio Nino Diaz [Mon, 18 Feb 2019 16:55:43 +0000 (16:55 +0000)]
Disable processor Cycle Counting in Secure state

In a system with ARMv8.5-PMU implemented:

- If EL3 is using AArch32, setting MDCR_EL3.SCCD to 1 disables counting
  in Secure state in PMCCNTR.

- If EL3 is using AArch64, setting SDCR.SCCD to 1 disables counting in
  Secure state in PMCCNTR_EL0.

So far this effect has been achieved by setting PMCR_EL0.DP (in AArch64)
or PMCR.DP (in AArch32) to 1 instead, but this isn't considered secure
as any EL can change that value.

Change-Id: I82cbb3e48f2e5a55c44d9c4445683c5881ef1f6f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoRename PLAT_ARM_BL31_RUN_UART* variable
Usama Arif [Mon, 11 Feb 2019 16:35:42 +0000 (16:35 +0000)]
Rename PLAT_ARM_BL31_RUN_UART* variable

The variable is renamed to PLAT_ARM_RUN_UART as
the UART is used outside BL31 as well.

Change-Id: I00e3639dfb2001758b7d24548c11236c6335f64a
Signed-off-by: Usama Arif <usama.arif@arm.com>
5 years agoMerge pull request #1824 from antonio-nino-diaz-arm/an/move-dyn-xlat
Antonio Niño Díaz [Mon, 18 Feb 2019 10:52:23 +0000 (10:52 +0000)]
Merge pull request #1824 from antonio-nino-diaz-arm/an/move-dyn-xlat

fvp: trusty: Move dynamic xlat enable to platform

5 years agoMerge pull request #1823 from antonio-nino-diaz-arm/an/spm-regs
Antonio Niño Díaz [Mon, 18 Feb 2019 10:52:16 +0000 (10:52 +0000)]
Merge pull request #1823 from antonio-nino-diaz-arm/an/spm-regs

SPM: Remove unnecessary register save

5 years agoMerge pull request #1821 from Yann-lms/stm32mp1_2019-02-14
Antonio Niño Díaz [Mon, 18 Feb 2019 10:51:57 +0000 (10:51 +0000)]
Merge pull request #1821 from Yann-lms/stm32mp1_2019-02-14

Series of new patches for STM32MP1

5 years agoallwinner: Clean up CPU ops functions
Samuel Holland [Sun, 17 Feb 2019 21:33:33 +0000 (15:33 -0600)]
allwinner: Clean up CPU ops functions

Convert them to take an mpidr instead of a (cluster, core) pair. This
simplifies all of the call sites, and actually makes the functions a bit
smaller.

Signed-off-by: Samuel Holland <samuel@sholland.org>
5 years agoallwinner: Constify data structures
Samuel Holland [Sun, 17 Feb 2019 21:09:11 +0000 (15:09 -0600)]
allwinner: Constify data structures

This maximizes the amount of data protected by the MMU.

Signed-off-by: Samuel Holland <samuel@sholland.org>
5 years agoMerge pull request #1822 from antonio-nino-diaz-arm/an/plat-arm
Antonio Niño Díaz [Fri, 15 Feb 2019 11:03:06 +0000 (11:03 +0000)]
Merge pull request #1822 from antonio-nino-diaz-arm/an/plat-arm

docs: Update note about plat/arm in Porting Guide

5 years agoSPM: Remove unnecessary register save
Antonio Nino Diaz [Thu, 14 Feb 2019 11:40:19 +0000 (11:40 +0000)]
SPM: Remove unnecessary register save

Since commit 01fc1c24b9a0 ("BL31: Use helper function to save registers
in SMC handler") all the general-purpose registers are saved when
entering EL3. It isn't needed to save them here.

Change-Id: Ic540a5441b89b70888da587ab8fc3b2508cef8cc
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agoUpdate macro to check need for CVE-2017-5715 mitigation
Antonio Nino Diaz [Tue, 12 Feb 2019 11:25:02 +0000 (11:25 +0000)]
Update macro to check need for CVE-2017-5715 mitigation

Armv8.5 introduces the field CSV2 to register ID_AA64PFR0_EL1. It can
have the following 3 values:

- 0: Branch targets trained in one hardware described context may affect
     speculative execution in a different hardware described context. In
     some CPUs it may be needed to apply mitigations.

- 1: Branch targets trained in one hardware described context can only
     affect speculative execution in a different hardware described
     context in a hard-to-determine way. No mitigation required.

- 2: Same as 1, but the device is also aware of SCXTNUM_ELx register
     contexts. The TF doesn't use the registers, so there is no
     difference with 1.

The field CSV2 was originally introduced in the TRM of the Cortex-A76
before the release of the Armv8.5 architecture. That TRM only mentions
the meaning of values 0 and 1. Because of this, the code only checks if
the field has value 1 to know whether to enable or disable the
mitigations.

This patch makes it aware of value 2 as well. Both values 1 and 2
disable the mitigation, and 0 enables it.

Change-Id: I5af33de25a0197c98173f52c6c8c77b51a51429f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
5 years agostm32mp1: introduce STM32MP1 discovery boards
Yann Gautier [Tue, 12 Feb 2019 18:00:29 +0000 (19:00 +0100)]
stm32mp1: introduce STM32MP1 discovery boards

Add the device tree files to support the 2 discovery boards: DK1 & DK2.

Change-Id: I90b4797dc69bd0aab1b643a72c932ead48a03c1f
Signed-off-by: Yann Gautier <yann.gautier@st.com>