From 194ca6127ee18cd3a95da4d03f02e43b5428c0bb Mon Sep 17 00:00:00 2001 From: John Crispin Date: Fri, 14 Nov 2014 16:52:42 +0000 Subject: [PATCH] ralink: improve mt7530 support the SDK does a bit of extra init that we did not do yet when using an external mt7530. Signed-off-by: John Crispin SVN-Revision: 43245 --- .../drivers/net/ethernet/ralink/gsw_mt7620a.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c index 74fe0bb6ff..58c209857e 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620a.c @@ -478,8 +478,22 @@ static void gsw_hw_init_mt7620(struct mt7620_gsw *gsw, struct device_node *np) gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR); if (of_property_read_bool(np, "mediatek,mt7530")) { - gsw_w32(gsw, gsw_r32(gsw, GSW_REG_GPC1) | (0x1f << 24), GSW_REG_GPC1); - pr_info("gsw: truning EPHY off\n"); + u32 val; + + /* turn off ephy and set phy base addr to 12 */ + gsw_w32(gsw, gsw_r32(gsw, GSW_REG_GPC1) | (0x1f << 24) | (0xc << 16), GSW_REG_GPC1); + + /* set MT7530 central align */ + val = mt7530_mdio_r32(gsw, 0x7830); + val &= ~1; + val |= 1<<1; + mt7530_mdio_w32(gsw, 0x7830, val); + + val = mt7530_mdio_r32(gsw, 0x7a40); + val &= ~(1<<30); + mt7530_mdio_w32(gsw, 0x7a40, val); + + mt7530_mdio_w32(gsw, 0x7a78, 0x855); } else { /* EPHY1 fixup - only run if the ephy is enabled */ -- 2.30.2