From 366dab94edc837d137303c79bd4d3c891f7b40e7 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 7 Jul 2011 19:56:02 +0000 Subject: [PATCH] drop ifxmips SVN-Revision: 27544 --- package/ifx-tapi/Config.in | 76 - package/ifx-tapi/Makefile | 69 - .../ifx-tapi/patches/001-portability.patch | 26 - package/ifx-tapi/patches/100-ifxmips.patch | 108 - package/ifx-tapidemo/Config.in | 39 - package/ifx-tapidemo/Makefile | 68 - package/ifx-tapidemo/files/bringup_tapidemo | 89 - .../ifx-tapidemo/patches/100-ifxmips.patch | 78 - .../patches/110-no_echo_cancelation.patch | 12 - package/ifx-vmmc/Config.in | 53 - package/ifx-vmmc/Makefile | 157 - package/ifx-vmmc/files/vmmc.init | 25 - .../ifx-vmmc/patches/001-portability.patch | 26 - package/ifx-vmmc/patches/100-ifxmips.patch | 491 --- package/ifxmips-dsl-api/Config.in | 33 - package/ifxmips-dsl-api/Makefile | 170 - .../patches/100-dsl_compat.patch | 39 - .../patches/200-mei_compat.patch | 94 - .../patches/300-atm_compat.patch | 156 - .../patches/400-debug-output.patch | 286 -- .../patches/500-portability.patch | 184 - package/ifxmips-dsl-api/src/Makefile | 3 - package/ifxmips-dsl-api/src/ifx_atm.h | 172 - package/ifxmips-dsl-api/src/ifxmips_atm.h | 172 - .../ifxmips-dsl-api/src/ifxmips_atm_core.c | 2507 -------------- .../ifxmips-dsl-api/src/ifxmips_atm_core.h | 249 -- .../ifxmips-dsl-api/src/ifxmips_atm_danube.c | 272 -- .../src/ifxmips_atm_fw_danube.h | 429 --- .../src/ifxmips_atm_fw_regs_common.h | 364 -- .../src/ifxmips_atm_fw_regs_danube.h | 30 - .../src/ifxmips_atm_ppe_common.h | 231 -- .../src/ifxmips_atm_ppe_danube.h | 100 - package/ifxmips-dsl-api/src/ifxmips_mei.c | 2998 ----------------- .../src/ifxmips_mei_interface.h | 700 ---- package/ifxmips-dsl-control/Makefile | 88 - .../files/ifx_cpe_control_init.sh | 21 - package/ifxos/Makefile | 49 - package/ifxos/patches/100-portability.patch | 28 - package/uboot-ifxmips/Config.in | 9 - package/uboot-ifxmips/Makefile | 84 - .../files/board/ifx/danube/Makefile | 44 - .../files/board/ifx/danube/README | 55 - .../files/board/ifx/danube/config.mk | 33 - .../files/board/ifx/danube/danube.c | 208 -- .../files/board/ifx/danube/ddr_settings.h | 50 - .../files/board/ifx/danube/ddr_settings_111.h | 50 - .../files/board/ifx/danube/ddr_settings_166.h | 50 - .../ifx/danube/ddr_settings_PROMOSDDR400.h | 50 - .../ifx/danube/ddr_settings_Samsung_166.h | 51 - .../board/ifx/danube/ddr_settings_e111.h | 50 - .../board/ifx/danube/ddr_settings_e166.h | 50 - .../board/ifx/danube/ddr_settings_psc_166.h | 51 - .../board/ifx/danube/ddr_settings_r111.h | 50 - .../board/ifx/danube/ddr_settings_r166.h | 50 - .../files/board/ifx/danube/flash.c | 917 ----- .../files/board/ifx/danube/lowlevel_init.S | 582 ---- .../files/board/ifx/danube/pmuenable.S | 48 - .../board/ifx/danube/u-boot-bootstrap.lds | 69 - .../files/board/ifx/danube/u-boot.lds | 69 - .../files/cpu/mips/danube/Makefile | 46 - .../files/cpu/mips/danube/ifx_asc.c | 257 -- .../files/cpu/mips/danube/ifx_cache.S | 60 - .../files/cpu/mips/danube/ifx_clock.c | 88 - .../files/cpu/mips/danube/ifx_cpu.c | 5 - .../files/cpu/mips/danube/ifx_start.S | 51 - .../files/danube_ref_ddr166.conf | 134 - package/uboot-ifxmips/files/drivers/ifx_sw.c | 459 --- package/uboot-ifxmips/files/gct | 157 - .../uboot-ifxmips/files/include/LzmaDecode.h | 113 - .../uboot-ifxmips/files/include/LzmaTypes.h | 45 - .../uboot-ifxmips/files/include/LzmaWrapper.h | 36 - .../files/include/asm-mips/danube.h | 2033 ----------- .../files/include/asm-mips/ifx_asc.h | 220 -- .../files/include/asm-mips/inca-ip2.h | 634 ---- .../files/include/asm-mips/pinstrap.h | 12 - package/uboot-ifxmips/files/include/boot.h | 86 - .../files/include/configs/danube.h | 273 -- .../files/lib_bootstrap/Makefile | 60 - .../files/lib_generic/LzmaDecode.c | 620 ---- .../files/lib_generic/LzmaWrapper.c | 220 -- package/uboot-ifxmips/files/net/ifx_eth.c | 4 - .../patches/001-portability.patch | 30 - package/uboot-ifxmips/patches/100-ifx.patch | 2102 ------------ .../patches/110-compile_fix.patch | 25 - .../uboot-ifxmips/patches/120-eon_flash.patch | 24 - package/uboot-ifxmips/patches/130-a800.patch | 31 - target/linux/ifxmips/Makefile | 26 - .../ifxmips/base-files/etc/config/network | 26 - .../base-files/etc/hotplug.d/button/00-reset | 3 - target/linux/ifxmips/base-files/etc/inittab | 4 - .../base-files/lib/upgrade/platform.sh | 25 - target/linux/ifxmips/config-2.6.30 | 162 - target/linux/ifxmips/extract.py | 9 - target/linux/ifxmips/extract.sh | 42 - .../ifxmips/files/arch/mips/ifxmips/Kconfig | 28 - .../ifxmips/files/arch/mips/ifxmips/Makefile | 1 - .../ifxmips/files/arch/mips/ifxmips/board.c | 404 --- .../ifxmips/files/arch/mips/ifxmips/clock.c | 204 -- .../files/arch/mips/ifxmips/dma-core.c | 690 ---- .../ifxmips/files/arch/mips/ifxmips/gpio.c | 345 -- .../ifxmips/files/arch/mips/ifxmips/irq.c | 235 -- .../ifxmips/files/arch/mips/ifxmips/pmu.c | 46 - .../ifxmips/files/arch/mips/ifxmips/prom.c | 157 - .../ifxmips/files/arch/mips/ifxmips/reset.c | 59 - .../ifxmips/files/arch/mips/ifxmips/setup.c | 92 - .../ifxmips/files/arch/mips/ifxmips/timer.c | 829 ----- .../mips/include/asm/mach-ifxmips/ifxmips.h | 517 --- .../include/asm/mach-ifxmips/ifxmips_cgu.h | 64 - .../include/asm/mach-ifxmips/ifxmips_dma.h | 195 -- .../include/asm/mach-ifxmips/ifxmips_ebu.h | 23 - .../include/asm/mach-ifxmips/ifxmips_gpio.h | 40 - .../include/asm/mach-ifxmips/ifxmips_gptu.h | 155 - .../include/asm/mach-ifxmips/ifxmips_irq.h | 78 - .../include/asm/mach-ifxmips/ifxmips_led.h | 26 - .../include/asm/mach-ifxmips/ifxmips_pmu.h | 32 - .../include/asm/mach-ifxmips/ifxmips_prom.h | 26 - .../arch/mips/include/asm/mach-ifxmips/irq.h | 28 - .../arch/mips/include/asm/mach-ifxmips/war.h | 24 - .../ifxmips/files/arch/mips/pci/ops-ifxmips.c | 120 - .../ifxmips/files/arch/mips/pci/pci-ifxmips.c | 209 -- target/linux/ifxmips/generic/target.mk | 5 - target/linux/ifxmips/image/Makefile | 39 - .../ifxmips/nfs/base-files/etc/config/network | 7 - .../lib/preinit/01_init_nfs_ifxmips | 12 - target/linux/ifxmips/nfs/config-default | 23 - target/linux/ifxmips/nfs/target.mk | 8 - .../patches-2.6.30/000-mips-bad-intctl.patch | 36 - .../010-mips_clocksource_init_war.patch | 35 - .../ifxmips/patches-2.6.30/100-board.patch | 67 - .../ifxmips/patches-2.6.30/110-pci.patch | 9 - .../ifxmips/patches-2.6.30/120-serial.patch | 588 ---- .../ifxmips/patches-2.6.30/130-ethernet.patch | 524 --- .../ifxmips/patches-2.6.30/140-mtd.patch | 296 -- .../ifxmips/patches-2.6.30/150-wdt.patch | 229 -- .../ifxmips/patches-2.6.30/160-led.patch | 230 -- .../patches-2.6.30/200-genirq_fix.patch | 14 - .../patches-2.6.30/300-cfi0001-swap.patch | 25 - .../patches-2.6.30/310-cfi0002-swap.patch | 15 - .../ifxmips/patches-2.6.30/400-atm_hack.patch | 48 - .../ifxmips/patches-2.6.30/500-arv452.patch | 79 - .../ifxmips/patches-2.6.30/600-ebu-gpio.patch | 196 -- target/linux/ifxmips/profiles/000-None.mk | 17 - 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delete mode 100644 target/linux/ifxmips/patches-2.6.30/310-cfi0002-swap.patch delete mode 100644 target/linux/ifxmips/patches-2.6.30/400-atm_hack.patch delete mode 100644 target/linux/ifxmips/patches-2.6.30/500-arv452.patch delete mode 100644 target/linux/ifxmips/patches-2.6.30/600-ebu-gpio.patch delete mode 100644 target/linux/ifxmips/profiles/000-None.mk delete mode 100644 target/linux/ifxmips/profiles/100-Atheros.mk delete mode 100644 target/linux/ifxmips/profiles/200-Ralink.mk diff --git a/package/ifx-tapi/Config.in b/package/ifx-tapi/Config.in deleted file mode 100644 index e360883fd4..0000000000 --- a/package/ifx-tapi/Config.in +++ /dev/null @@ -1,76 +0,0 @@ -menu "Configuration" - depends on PACKAGE_kmod-ifx-tapi - -config VOICE_CPE_TAPI_FAX - bool "fax relay and modem support" - default n - help - Option to enable fax/modem support in TAPI. - Note: Newer platforms as AR9 and VR9 support a T.38 fax relay stack - in FW while older platforms like Danube or VINETIC-CPE require a - separate SW stack executed as an application. - -config VOICE_CPE_TAPI_CID - bool "CID support" - default y - help - Option to enable Caller ID support. - -config VOICE_CPE_TAPI_LT_GR909 - bool "Linetesting GR-909 support" - default y - help - Option to enable linetesting GR-909. - -config VOICE_CPE_TAPI_DECT - bool "DECT encoding for COSIC modem" - default n - help - Option to enable DECT encoding for COSIC modem. - -config VOICE_CPE_TAPI_KPI - bool "KPI (Kernel Packet Interface)" - default y - help - Option to enable the generic kernel level packet interface - which allows accelerated packet transfer for various purposes. - The most important example is the QOS option, which allows - to redirect RTP packets directly into the IP stack. - Other options relying on KPI are DECT and HDLC. - -config VOICE_CPE_TAPI_QOS - bool "QOS for accelerated RTP packet handling" - default y - help - Option to enable an accelerated RTP packet transfer inside - the LINUX kernel space. This option requires the KPI2UDP - packet, which actually provides the OS specific hooks in - the IP stack. - -config VOICE_CPE_TAPI_STATISTICS - bool "TAPI statistics via /proc fs" - default y - help - Option to enable /proc fs statistics for packet counts etc. - -config VOICE_CPE_TAPI_METERING - bool "Metering (TTX) support" - default n - help - Option to enable metering (TTX) support. - -config VOICE_CPE_TAPI_HDLC - bool "PCM HDLC support, evaluation" - default n - help - Option to enable PCM HDLC framing inside the firmware, e.g. for - ISDN D-Channel access. - -config VOICE_CPE_TAPI_TRACES - bool "enable driver traces" - default y - help - enable driver traces with different trace levels to be - configured dynamically from the application or during insmod - -endmenu diff --git a/package/ifx-tapi/Makefile b/package/ifx-tapi/Makefile deleted file mode 100644 index e4638186e2..0000000000 --- a/package/ifx-tapi/Makefile +++ /dev/null @@ -1,69 +0,0 @@ -# -# Copyright (C) 2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=drv_tapi -PKG_VERSION:=3.11.0 -PKG_RELEASE:=1 - -PKG_SOURCE:=drv_tapi-$(PKG_VERSION).tar.gz -PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources -PKG_MD5SUM:=1ffee83ce69f55915468c309d8ae2138 - -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/ifx-tapi - SUBMENU:=Voice over IP - TITLE:=Lantiq TAPI subsystem - URL:=http://www.lantiq.com/ - MAINTAINER:=Lantiq - DEPENDS:=+kmod-ifxos @BROKEN - FILES:=$(PKG_BUILD_DIR)/src/drv_tapi.$(LINUX_KMOD_SUFFIX) - AUTOLOAD:=$(call AutoLoad,20,drv_tapi) - MENU:=1 -endef - -define KernelPackage/ifx-tapi/description - Voice Subsystem Telephony API High Level Driver -endef - -define KernelPackage/ifx-tapi/config - source "$(SOURCE)/Config.in" -endef - -CONFIGURE_ARGS += \ - ARCH=$(LINUX_KARCH) \ - --enable-linux-26 \ - --enable-kernelbuild="$(LINUX_DIR)" \ - --enable-kernelincl="$(LINUX_DIR)/include" \ - --with-ifxos-incl=$(STAGING_DIR)/usr/include/ifxos \ - $(call autoconf_bool,CONFIG_IFX_DRV_TAPI_EVENT_LOGGER,el-debug) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_FAX,fax t38) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_CID,cid) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_DECT,dect) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_KPI,kpi) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_QOS,qos) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_LT_GR909,lt) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_STATISTICS,statistics) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_METERING,metering) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_HDLC,hdlc) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_TRACES,trace) - -define Build/Configure - (cd $(PKG_BUILD_DIR); aclocal && autoconf && automake) - $(call Build/Configure/Default) -endef - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include/drv_tapi - $(CP) --dereference $(PKG_BUILD_DIR)/include/* $(1)/usr/include/drv_tapi - (cd $(1)/usr/include/drv_tapi && ln -s . include && ln -s ../ifxos/ifx_types.h .) -endef - -$(eval $(call KernelPackage,ifx-tapi)) diff --git a/package/ifx-tapi/patches/001-portability.patch b/package/ifx-tapi/patches/001-portability.patch deleted file mode 100644 index 807a64b125..0000000000 --- a/package/ifx-tapi/patches/001-portability.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/src/Makefile.am -+++ b/src/Makefile.am -@@ -149,7 +149,7 @@ if KERNEL_2_6 - drv_tapi_OBJS = "$(subst .c,.o, $(drv_tapi_SOURCES))" - - drv_tapi.ko: $(drv_tapi_SOURCES) $(EXTRA_DIST) -- @echo -e "Making Linux 2.6.x kernel object" -+ @echo "Making Linux 2.6.x kernel object" - @for f in $(drv_tapi_SOURCES) ; do \ - if test ! -e $(PWD)/$$f; then \ - echo " LN $$f" ; \ -@@ -157,10 +157,10 @@ drv_tapi.ko: $(drv_tapi_SOURCES) $(EXTRA - ln -s @abs_srcdir@/$$f $(PWD)/$$f; \ - fi; \ - done; -- @echo -e "# drv_tapi: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild -- @echo -e "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild -- @echo -e "$(subst .ko,,$@)-y := $(drv_tapi_OBJS)" >> $(PWD)/Kbuild -- @echo -e "EXTRA_CFLAGS := -DHAVE_CONFIG_H $(CFLAGS) $(drv_tapi_CFLAGS) $(INCLUDES)" >> $(PWD)/Kbuild -+ @echo "# drv_tapi: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild -+ @echo "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild -+ @echo "$(subst .ko,,$@)-y := $(drv_tapi_OBJS)" >> $(PWD)/Kbuild -+ @echo "EXTRA_CFLAGS := -DHAVE_CONFIG_H $(CFLAGS) $(drv_tapi_CFLAGS) $(INCLUDES)" >> $(PWD)/Kbuild - $(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules - - clean-generic: diff --git a/package/ifx-tapi/patches/100-ifxmips.patch b/package/ifx-tapi/patches/100-ifxmips.patch deleted file mode 100644 index bce831c080..0000000000 --- a/package/ifx-tapi/patches/100-ifxmips.patch +++ /dev/null @@ -1,108 +0,0 @@ ---- a/src/drv_tapi_linux.c -+++ b/src/drv_tapi_linux.c -@@ -544,7 +544,7 @@ static ssize_t ifx_tapi_write (struct fi - IFX_uint8_t *pData; - IFX_size_t buf_size; - #endif /* TAPI_PACKET */ -- IFX_ssize_t size = 0; -+ ssize_t size = 0; - - #ifdef TAPI_PACKET - if (pTapiDev->bInitialized == IFX_FALSE) -@@ -3600,7 +3600,11 @@ IFX_void_t TAPI_OS_ThreadKill(IFXOS_Thre - flag and released after the down() call. */ - lock_kernel(); - mb(); -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) - kill_proc(pThrCntrl->tid, SIGKILL, 1); -+#else -+ kill_pid(find_vpid(pThrCntrl->tid), SIGKILL, 1); -+#endif - /* release the big kernel lock */ - unlock_kernel(); - wait_for_completion (&pThrCntrl->thrCompletion); ---- a/src/drv_tapi_osmap.h -+++ b/src/drv_tapi_osmap.h -@@ -17,39 +17,6 @@ - */ - - #include "ifx_types.h" /* ifx type definitions */ -- --#ifndef HAVE_IFX_ULONG_T -- #warning please update your ifx_types.h, using local definition of IFX_ulong_t -- /* unsigned long type - valid for 32bit systems only */ -- typedef unsigned long IFX_ulong_t; -- #define HAVE_IFX_ULONG_T --#endif /* HAVE_IFX_ULONG_T */ -- --#ifndef HAVE_IFX_LONG_T -- #warning please update your ifx_types.h, using local definition of IFX_long_t -- /* long type - valid for 32bit systems only */ -- typedef long IFX_long_t; -- #define HAVE_IFX_LONG_T --#endif /* HAVE_IFX_LONG_T */ -- --#ifndef HAVE_IFX_INTPTR_T -- #warning please update your ifx_types.h, using local definition of IFX_intptr_t -- typedef IFX_long_t IFX_intptr_t; -- #define HAVE_IFX_INTPTR_T --#endif /* HAVE_IFX_INTPTR_T */ -- --#ifndef HAVE_IFX_SIZE_T -- #warning please update your ifx_types.h, using local definition of IFX_size_t -- typedef IFX_ulong_t IFX_size_t; -- #define HAVE_IFX_SIZE_T --#endif /* HAVE_IFX_SIZE_T */ -- --#ifndef HAVE_IFX_SSIZE_T -- #warning please update your ifx_types.h, using local definition of IFX_ssize_t -- typedef IFX_long_t IFX_ssize_t; -- #define HAVE_IFX_SSIZE_T --#endif /* HAVE_IFX_SSIZE_T */ -- - #include "ifxos_interrupt.h" - #include "ifxos_memory_alloc.h" - #include "ifxos_copy_user_space.h" ---- a/include/drv_tapi_ll_interface.h -+++ b/include/drv_tapi_ll_interface.h -@@ -40,13 +40,6 @@ - #include "ifxos_select.h" - #endif /* TAPI_PACKET */ - --#ifndef HAVE_IFX_ULONG_T -- #warning please update your ifx_types.h, using local definition of IFX_ulong_t -- /* unsigned long type - valid for 32bit systems only */ -- typedef unsigned long IFX_ulong_t; -- #define HAVE_IFX_ULONG_T --#endif /* HAVE_IFX_ULONG_T */ -- - /* ============================= */ - /* Local Macros Definitions */ - /* ============================= */ ---- a/src/lib/lib_bufferpool/lib_bufferpool.c -+++ b/src/lib/lib_bufferpool/lib_bufferpool.c -@@ -80,24 +80,6 @@ - #include - #endif /* LINUX */ - -- --/* ============================= */ --/* Extra type definitions */ --/* ============================= */ --#ifndef HAVE_IFX_ULONG_T -- #warning please update your ifx_types.h, using local definition of IFX_ulong_t -- /* unsigned long type - valid for 32bit systems only */ -- typedef unsigned long IFX_ulong_t; -- #define HAVE_IFX_ULONG_T --#endif /* HAVE_IFX_ULONG_T */ -- --#ifndef HAVE_IFX_UINTPTR_T -- #warning please update your ifx_types.h, using local definition of IFX_uintptr_t -- typedef IFX_ulong_t IFX_uintptr_t; -- #define HAVE_IFX_UINTPTR_T --#endif /* HAVE_IFX_UINTPTR_T */ -- -- - /* ============================= */ - /* Local Macros & Definitions */ - /* ============================= */ diff --git a/package/ifx-tapidemo/Config.in b/package/ifx-tapidemo/Config.in deleted file mode 100644 index 42ec5fa1c3..0000000000 --- a/package/ifx-tapidemo/Config.in +++ /dev/null @@ -1,39 +0,0 @@ -menu "Configuration" - depends on PACKAGE_ifx-tapidemo -choice - prompt "board selection" - default VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3 if TARGET_ifxmips_platform_danube - default VOICE_CPE_TAPIDEMO_BOARD_EASY508xx if TARGET_ifxmips_platform_ar9 - default VOICE_CPE_TAPIDEMO_BOARD_EASY80910 if TARGET_ifxmips_platform_vr9 - default VOICE_CPE_TAPIDEMO_BOARD_EASY50812 - help - Select the target platform. - - config VOICE_CPE_TAPIDEMO_BOARD_EASY50712 - bool "Danube reference board" - - config VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3 - bool "Danube reference board V3" - - config VOICE_CPE_TAPIDEMO_BOARD_EASY508xx - bool "AR9/GR9 reference board" - - config VOICE_CPE_TAPIDEMO_BOARD_EASY80910 - bool "VR9 reference board" -endchoice - -config VOICE_CPE_TAPIDEMO_QOS - bool "enable QOS support" - default n - help - Option to enable the KPI2UDP RTP packet acceleration path - (highly recommended for VoIP). - -config VOICE_CPE_TAPIDEMO_FAX_T.38_FW - bool "enable T.38 fax relay" - depends on (TARGET_ifxmips_platform_ar9 || TARGET_ifxmips_platform_vr9) - default n - help - enable T.38 fax relay demo. - -endmenu diff --git a/package/ifx-tapidemo/Makefile b/package/ifx-tapidemo/Makefile deleted file mode 100644 index e90ad4d258..0000000000 --- a/package/ifx-tapidemo/Makefile +++ /dev/null @@ -1,68 +0,0 @@ -# -# Copyright (C) 2008-2010 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=tapidemo -PKG_VERSION:=5.0.1.27 -PKG_RELEASE:=1 - -PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz -PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources -PKG_MD5SUM:=a38a7bf3242aad607f50f57b988bc87c - -include $(INCLUDE_DIR)/package.mk - -define Package/ifx-tapidemo - SECTION:=utils - CATEGORY:=Utilities - TITLE:=TAPIdemo application for Lantiq boards - URL:=http://www.lantiq.com/ - MAINTAINER:=Lantiq - DEPENDS:=+kmod-ifx-tapi +kmod-ifx-vmmc @BROKEN - MENU:=1 -endef - -define Package/ifx-tapidemo/description - Voice Access mini-PBX Demo Application -endef - -define Package/ifx-tapidemo/config - source "$(SOURCE)/Config.in" -endef - -CONFIGURE_ARGS += \ - ARCH=$(LINUX_KARCH) \ - --enable-linux-26 \ - --enable-kernelincl="$(LINUX_DIR)/include" \ - --with-drvincl="$(STAGING_DIR)/usr/include" \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_QOS,qos) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPIDEMO_FAX_T,fax-t38) \ - --enable-trace \ - --enable-fs - -ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY50712),y) - CONFIGURE_ARGS += --enable-boardname=EASY50712 -endif -ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY50712_V3),y) - CONFIGURE_ARGS += --enable-boardname=EASY50712_V3 -endif -ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY508xx),y) - CONFIGURE_ARGS += --enable-boardname=EASY508XX -endif -ifeq ($(CONFIG_VOICE_CPE_TAPIDEMO_BOARD_EASY80910),y) - CONFIGURE_ARGS += --enable-boardname=EASY508XX -endif - -define Package/ifx-tapidemo/install - $(INSTALL_DIR) $(1)/usr/sbin $(1)/etc/init.d/ - $(INSTALL_BIN) $(PKG_BUILD_DIR)/src/tapidemo $(1)/usr/sbin - $(INSTALL_BIN) ./files/bringup_tapidemo $(1)/etc/init.d/tapidemo -endef - -$(eval $(call BuildPackage,ifx-tapidemo)) diff --git a/package/ifx-tapidemo/files/bringup_tapidemo b/package/ifx-tapidemo/files/bringup_tapidemo deleted file mode 100644 index 6eb13d25f1..0000000000 --- a/package/ifx-tapidemo/files/bringup_tapidemo +++ /dev/null @@ -1,89 +0,0 @@ -#!/bin/sh /etc/rc.common -# (C) 2008 openwrt.org - -START=96 - -[ ! -f /dev/vmmc10 ] && { - mknod /dev/vmmc10 c 122 10 - mknod /dev/vmmc11 c 122 11 - mknod /dev/vmmc12 c 122 12 - mknod /dev/vmmc13 c 122 13 - mknod /dev/vmmc14 c 122 14 - mknod /dev/vmmc15 c 122 15 - mknod /dev/vmmc16 c 122 16 - mknod /dev/vmmc17 c 122 17 - mknod /dev/vmmc18 c 122 18 -} - -TD_EXTRA_FLAGS_FXO= -TD_EXTRA_FLAGS_KPI2UDP= -TD_DOWNLOAD_PATH=/lib/firmware/ -DEV_NODE_TERIDIAN=ter10 - - # Show help -help() -{ - echo "Usage:" - echo " - $0 WAN-IF-NAME - start TAPIDEMO without FXO support" - echo " - $0 WAN-IF-NAME fxo - start TAPIDEMO with FXO support." - echo " - $0 stop - stop TAPIDEMO" -} - -# Check if device node for Teridian exists -checkFxoSupport() -{ - if [ ! -e /dev/$DEV_NODE_TERIDIAN ];then - echo "FXO support is disabled. Can not find required driver's device node." - else - TD_EXTRA_FLAGS_FXO="-x" - fi -} - -# Check if module drv_kpi2udp is loaded -checkKpi2UdpSupport() -{ - tmp=`cat /proc/modules | grep 'drv_kpi2udp '` - if [ "$tmp" != "" ]; then - TD_EXTRA_FLAGS_KPI2UDP="-q" - fi -} - -start() -{ - TD_WANIF=$1 - - TD_WANIF_IP=`ifconfig $TD_WANIF | grep 'inet addr:' | cut -f2 -d: | cut -f1 -d' '` - if [ "$TD_WANIF_IP" = "" ]; then - echo "Error, getting IP address for network device $TD_WANIF failed." - exit 1 - fi - - if [ "$2" = "" ];then - # FXO support is disabled. - continue - elif [ "$2" = "fxo" ];then - checkFxoSupport - else - echo "Error, unknown second parameter." - help - exit 1 - fi - - checkKpi2UdpSupport - - if [ -r /etc/rc.conf ]; then - . /etc/rc.conf - fi - - TD_DEBUG_LEVEL=$tapiDebugLevel - if [ "$TD_DEBUG_LEVEL" = "" ]; then - TD_DEBUG_LEVEL=3 - fi - - /usr/sbin/tapidemo -d $TD_DEBUG_LEVEL $TD_EXTRA_FLAGS_FXO $TD_EXTRA_FLAGS_KPI2UDP -i $TD_WANIF_IP -l $TD_DOWNLOAD_PATH & -} - -stop() -{ - killall tapidemo > /dev/null 2> /dev/null -} diff --git a/package/ifx-tapidemo/patches/100-ifxmips.patch b/package/ifx-tapidemo/patches/100-ifxmips.patch deleted file mode 100644 index 43fa988ef7..0000000000 --- a/package/ifx-tapidemo/patches/100-ifxmips.patch +++ /dev/null @@ -1,78 +0,0 @@ ---- a/src/board_easy50712.c Mon Mar 15 14:47:53 2010 +0300 -+++ b/src/board_easy50712.c Tue Mar 16 17:25:55 2010 +0300 -@@ -40,7 +40,9 @@ - #endif /* DUSLIC_FXO */ - #endif /* EASY50712_V3 */ - --#include "asm/ifx/ifx_gpio.h" -+#ifdef FXO -+# include "asm/ifx/ifx_gpio.h" -+#endif - - /* ============================= */ - /* Defines */ -@@ -896,6 +898,7 @@ - /* Global function definition */ - /* ============================= */ - -+#ifdef FXO - /** - Set direction of GPIO pin to out which is used for set/clear reset. - -@@ -944,7 +947,7 @@ - return IFX_SUCCESS; - } - break; -- -+ - case GPIO_DUSLIC_EASY50510: - { - TRACE(TAPIDEMO, DBG_LEVEL_LOW, -@@ -982,8 +985,9 @@ - - return IFX_SUCCESS; - }; -+#endif - -- -+#ifdef FXO - /* - Set/Clear reset of device by using GPIO port. - -@@ -1086,7 +1090,9 @@ - /* usleep(100000); karol - workaround, */ - return ret; - } -+#endif - -+#ifdef EASY50510 - /** - Set PCM master mode. - -@@ -1178,15 +1184,16 @@ - - return ret; - } -+#endif - - /** - Register board. - - \param pBoard - pointer to board -- -+ - \return IFX_SUCCESS if successful, otherwise IFX_ERROR. - -- \remarks -+ \remarks - */ - IFX_return_t BOARD_Easy50712_Register(BOARD_t* pBoard) - { -@@ -1204,7 +1211,3 @@ - pBoard->RemoveBoard = BOARD_Easy50712_RemoveBoard; - return IFX_SUCCESS; - } -- -- -- -- diff --git a/package/ifx-tapidemo/patches/110-no_echo_cancelation.patch b/package/ifx-tapidemo/patches/110-no_echo_cancelation.patch deleted file mode 100644 index d424d48470..0000000000 --- a/package/ifx-tapidemo/patches/110-no_echo_cancelation.patch +++ /dev/null @@ -1,12 +0,0 @@ -Index: tapidemo-5.0.1.27/src/device_vmmc.c -=================================================================== ---- tapidemo-5.0.1.27.orig/src/device_vmmc.c 2009-11-09 15:40:31.000000000 +0100 -+++ tapidemo-5.0.1.27/src/device_vmmc.c 2010-03-30 21:32:51.000000000 +0200 -@@ -240,7 +240,6 @@ - TRACE(TAPIDEMO, DBG_LEVEL_HIGH, - ("Error, BBD file %s is not found.\n(File: %s, line: %d)\n", - pCpuDevice->pszBBD_CRAM_File, __FILE__, __LINE__)); -- return IFX_ERROR; - } - - #endif /* USE_FILESYSTEM */ diff --git a/package/ifx-vmmc/Config.in b/package/ifx-vmmc/Config.in deleted file mode 100644 index 2a7894e7f0..0000000000 --- a/package/ifx-vmmc/Config.in +++ /dev/null @@ -1,53 +0,0 @@ -menu "Configuration" - depends on PACKAGE_kmod-ifx-vmmc -choice - prompt "device selection" - default VOICE_CPE_VMMC_WITH_DEVICE_DANUBE_extract - help - Select the target device. - - config VOICE_CPE_VMMC_WITH_DEVICE_DANUBE_extract - bool "Danube, Twinpass, Vinax - extract binaries" - - config VOICE_CPE_VMMC_WITH_DEVICE_DANUBE - bool "Danube, Twinpass, Vinax" - - config VOICE_CPE_VMMC_WITH_DEVICE_AR9 - bool "AR9 family" - - config VOICE_CPE_VMMC_WITH_DEVICE_VR9 - bool "VR9 family" - -endchoice - -config VOICE_CPE_VMMC_PMC - depends on (VOICE_CPE_VMMC_WITH_DEVICE_AR9 || VOICE_CPE_VMMC_WITH_DEVICE_VR9) - bool "Power Management Control support" - default n - help - Option to enable Power Management Control on AR9, VR9. Not supported for Danube. - -config VOICE_CPE_VMMC_DISABLE_DECT_NIBBLE_SWAP - bool "Disable DECT nibble swap" - default n - help - Option to disable DECT nibble swap for COSIC modem (for backward compatibility only). - -config VOICE_CPE_VMMC_EVENT_LOGGER - depends on BROKEN - bool "Event logger support" - default n - help - Option to enable details traces between drv_vmmc and the voice FW - - for debugging only - - requires package ifx-evtlog - -config VOICE_CPE_VMMC_MPS_HISTORY_SIZE - int "MPS history buffer in words (0<=size<=512)" - default "128" - help - MPS history buffer (default=128 words, maximum=512 words, 0=disable) - To opimize the memory footprint in RAM, you might want to set the - buffer size to 0. - -endmenu diff --git a/package/ifx-vmmc/Makefile b/package/ifx-vmmc/Makefile deleted file mode 100644 index fdf169ad6c..0000000000 --- a/package/ifx-vmmc/Makefile +++ /dev/null @@ -1,157 +0,0 @@ -# -# Copyright (C) 2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=drv_vmmc -PKG_VERSION:=1.7.0 -PKG_RELEASE:=1 - -PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz -PKG_MD5SUM:=3f1b44e79408a3320aa9f8b21a260fd0 -PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources - -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/ifx-vmmc - SUBMENU:=Voice over IP - TITLE:=TAPI LL driver for Voice Macro - URL:=http://www.lantiq.com/ - MAINTAINER:=Lantiq - DEPENDS:=+kmod-ifx-tapi @BROKEN - FILES:=$(PKG_BUILD_DIR)/src/drv_vmmc.$(LINUX_KMOD_SUFFIX) - AUTOLOAD:=$(call AutoLoad,25,drv_vmmc) - MENU:=1 -endef - -define KernelPackage/ifx-vmmc/description - Voice Subsystem Low Level Driver for Danube, AR9, VR9 device families -endef - -define KernelPackage/ifx-vmmc/config - source "$(SOURCE)/Config.in" -endef - -CONFIGURE_ARGS += \ - ARCH=$(LINUX_KARCH) \ - --enable-linux-26 \ - --enable-kernelbuild="$(LINUX_DIR)" \ - --enable-kernelincl="$(LINUX_DIR)/include" \ - --enable-tapiincl="$(STAGING_DIR)/usr/include/drv_tapi" \ - --with-ifxos-incl=$(STAGING_DIR)/usr/include/ifxos \ - $(call autoconf_bool,CONFIG_VOICE_CPE_VMMC_EVENT_LOGGER,el-debug) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_VMMC_PMC,pmc) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_VMMC_DISABLE_DECT_NIBBLE_SWAP,dect-nibble-swap) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_FAX,fax t38) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_CID,cid) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_DECT,dect) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_KPI,kpi) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_LT_GR909,lt calibration) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_HDLC,hdlc) \ - $(call autoconf_bool,CONFIG_VOICE_CPE_TAPI_TRACES,trace) - -ifneq ($(CONFIG_VOICE_CPE_VMMC_MPS_HISTORY_SIZE),128) - CONFIGURE_ARGS += --enable-history-buf=$(CONFIG_VOICE_CPE_VMMC_MPS_HISTORY_SIZE) -endif - -#defaults -FW_URL:=http://localhost/ -FW_TARGET:=ifx_firmware.bin -FW_FILE:=fw_voip_ifx.tar.gz -COEF_TARGET:=ifx_bbd_fxs.bin -COEF_FILE:=coef_voip_ifx.tar.gz - -FW_DIR:=lib/firmware -ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_DANUBE_extract),y) - CONFIGURE_ARGS += --with-device=DANUBE - FW_TARGET:=danube_firmware.bin - FW_URL:=http://www.arcor.de/hilfe/files/pdf/ - FW_FILE=arcor_A800_452CPW_FW_1.02.206(20081201).bin - FW_MD5SUM:=19d9af4e369287a0f0abaed415cdac10 - COEF_TARGET:=danube_bbd_fxs.bin - COEF_FILE:=arcor_A800_452CPW_FW_1.02.206(20081201).bin - COEF_MD5SUM:=19d9af4e369287a0f0abaed415cdac10 -endif - -ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_DANUBE),y) - CONFIGURE_ARGS += --with-device=DANUBE - FW_TARGET:=danube_firmware.bin - FW_FILE=fw_voip_danube-12.1.0.1.0.tar.gz - FW_MD5SUM:=51868b88dee9dbc65d3dbba355ded91c - COEF_TARGET:=danube_bbd_fxs.bin - COEF_FILE:=coef_voip_danube-0.9.0.tar.gz - COEF_MD5SUM:=c8ac6592b304b03829a8123560e15710 -endif - -ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_AR9),y) - CONFIGURE_ARGS += --with-device=AR9 - # TODO: add fw/coef -endif - -ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_VR9),y) - CONFIGURE_ARGS += --with-device=VR9 - # TODO: add fw/coef -endif - -ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_DANUBE_extract),y) -define Download/decode - FILE:=ifxmips_fw_decodev2.tar.bz2 - URL:=http://downloads.openwrt.org/sources/ - MD5SUM:=9f4ebfae5cb9d9e8fca46057a653ae27 -endef -$(eval $(call Download,decode)) -endif - -define Download/firmware - FILE:=$(FW_FILE) - URL:=$(FW_URL) - MD5SUM:=$(FW_MD5SUM) -endef -$(eval $(call Download,firmware)) - -define Download/coef - FILE:=$(COEF_FILE) - URL:=$(FW_URL) - MD5SUM:=$(COEF_MD5SUM) -endef -$(eval $(call Download,coef)) - -define Build/Configure - rm -rf \ - $(PKG_BUILD_DIR)/coef \ - $(PKG_BUILD_DIR)/firmware - mkdir -p \ - $(PKG_BUILD_DIR)/coef \ - $(PKG_BUILD_DIR)/firmware -ifeq ($(CONFIG_VOICE_CPE_VMMC_WITH_DEVICE_DANUBE_extract),y) - $(PLATFORM_DIR)/extract.sh $(DL_DIR) '$(FW_FILE)' - $(CP) $(DL_DIR)/voip.bin $(PKG_BUILD_DIR)/firmware/$(FW_TARGET) - $(CP) $(DL_DIR)/voip_coef.bin $(PKG_BUILD_DIR)/coef/$(COEF_TARGET) -else - $(TAR) -C $(PKG_BUILD_DIR)/firmware -xvzf $(DL_DIR)/$(FW_FILE) - $(TAR) -C $(PKG_BUILD_DIR)/coef -xvzf $(DL_DIR)/$(COEF_FILE) -endif - (cd $(PKG_BUILD_DIR); aclocal && autoconf && automake) - $(call Build/Configure/Default) -endef - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include - mkdir -p $(1)/usr/include/drv_vmmc - $(CP) -v --dereference $(PKG_BUILD_DIR)/include/* $(1)/usr/include/drv_vmmc - (cd $(1)/usr/include/drv_vmmc && ln -snf . include) -endef - -define KernelPackage/ifx-vmmc/install - $(INSTALL_DIR) $(1)/etc/init.d $(1)/$(FW_DIR) - $(INSTALL_BIN) ./files/vmmc.init $(1)/etc/init.d/vmmc - $(CP) $(PKG_BUILD_DIR)/firmware/$(FW_TARGET) $(1)/$(FW_DIR)/$(FW_TARGET) - $(CP) $(PKG_BUILD_DIR)/coef/$(COEF_TARGET) $(1)/$(FW_DIR)/$(COEF_TARGET) -endef - -$(eval $(call KernelPackage,ifx-vmmc)) diff --git a/package/ifx-vmmc/files/vmmc.init b/package/ifx-vmmc/files/vmmc.init deleted file mode 100644 index bae7badaf0..0000000000 --- a/package/ifx-vmmc/files/vmmc.init +++ /dev/null @@ -1,25 +0,0 @@ -#!/bin/sh /etc/rc.common -# -# Activate Voice CPE TAPI subsystem LL driver for VMMC - -START=31 - -start() { - # TODO: clean up this mess - [ `cat /proc/cpuinfo | grep system | cut -f 3 -d ' '` = "Twinpass-VE" ] && { - [ ! -e /dev/danube-port ] && mknod /dev/danube-port c 254 0 - return; - } - [ `cat /proc/cpuinfo | grep system | cut -f 3 -d ' '` != "Danube" ] && { - [ ! -e /dev/amazon_s-port ] && mknod /dev/amazon_s-port c 240 1 - echo "INFO configuring HW scheduling 33/66" - echo "t0 0x0" > /proc/mips/mtsched - echo "t1 0x1" > /proc/mips/mtsched - echo "v0 0x0" > /proc/mips/mtsched - } - [ `cat /proc/cpuinfo | grep system | cut -f 3 -d ' '` = "Danube" ] && { - [ ! -e /dev/danube-port ] && mknod /dev/danube-port c 240 1 - # switch life-line relais - echo 1 > /sys/class/leds/fxs_relay/brightness - } -} diff --git a/package/ifx-vmmc/patches/001-portability.patch b/package/ifx-vmmc/patches/001-portability.patch deleted file mode 100644 index fb8ab68ed4..0000000000 --- a/package/ifx-vmmc/patches/001-portability.patch +++ /dev/null @@ -1,26 +0,0 @@ ---- a/src/Makefile.am -+++ b/src/Makefile.am -@@ -227,7 +227,7 @@ drv_vmmc_CFLAGS += -fno-common - drv_vmmc_OBJS = "$(subst .c,.o, $(drv_vmmc_SOURCES) $(nodist_drv_vmmc_SOURCES))" - - drv_vmmc.ko: $(drv_vmmc_SOURCES) $(EXTRA_DIST) -- @echo -e "Making Linux 2.6.x kernel object" -+ @echo "Making Linux 2.6.x kernel object" - @for f in $(drv_vmmc_SOURCES) $(nodist_drv_vmmc_SOURCES) ; do \ - if test ! -e $(PWD)/$$f; then \ - echo " LN $$f" ; \ -@@ -235,10 +235,10 @@ drv_vmmc.ko: $(drv_vmmc_SOURCES) $(EXTRA - ln -s @abs_srcdir@/$$f $(PWD)/$$f; \ - fi; \ - done; -- @echo -e "# drv_vmmc: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild -- @echo -e "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild -- @echo -e "$(subst .ko,,$@)-y := $(drv_vmmc_OBJS)" >> $(PWD)/Kbuild -- @echo -e "EXTRA_CFLAGS := -DHAVE_CONFIG_H $(CFLAGS) $(drv_vmmc_CFLAGS) $(INCLUDES)" >> $(PWD)/Kbuild -+ @echo "# drv_vmmc: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild -+ @echo "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild -+ @echo "$(subst .ko,,$@)-y := $(drv_vmmc_OBJS)" >> $(PWD)/Kbuild -+ @echo "EXTRA_CFLAGS := -DHAVE_CONFIG_H $(CFLAGS) $(drv_vmmc_CFLAGS) $(INCLUDES)" >> $(PWD)/Kbuild - $(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules - - clean-generic: diff --git a/package/ifx-vmmc/patches/100-ifxmips.patch b/package/ifx-vmmc/patches/100-ifxmips.patch deleted file mode 100644 index 6a4cc8d590..0000000000 --- a/package/ifx-vmmc/patches/100-ifxmips.patch +++ /dev/null @@ -1,491 +0,0 @@ ---- a/src/drv_vmmc_access.h -+++ b/src/drv_vmmc_access.h -@@ -24,6 +24,10 @@ - #include "drv_mps_vmmc.h" - #endif - -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)) -+# define IFX_MPS IFXMIPS_MPS_BASE_ADDR -+#endif -+ - /* ============================= */ - /* Global Defines */ - /* ============================= */ ---- a/src/drv_vmmc_bbd.c -+++ b/src/drv_vmmc_bbd.c -@@ -939,7 +939,11 @@ static IFX_int32_t vmmc_BBD_DownloadChCr - IFX_uint8_t padBytes = 0; - #endif - IFX_uint16_t cram_offset, cram_crc, -- pCmd [MAX_CMD_WORD] = {0}; -+ pCmd [MAX_CMD_WORD] -+#if defined (__GNUC__) || defined (__GNUG__) -+ __attribute__ ((aligned(4))) -+#endif -+ = {0}; - - /* read offset */ - cpb2w (&cram_offset, &bbd_cram->pData[0], sizeof (IFX_uint16_t)); ---- a/src/drv_vmmc_danube.h -+++ b/src/drv_vmmc_danube.h -@@ -15,12 +15,59 @@ - */ - - #if defined SYSTEM_DANUBE --#include -+# if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)) -+# include -+ -+# define IFX_GPIO_PIN_NUMBER_PER_PORT 16 -+# define IFX_GPIO_PIN_ID(port, pin) ((port) \ -+ * IFX_GPIO_PIN_NUMBER_PER_PORT \ -+ + (pin)) -+# define IFX_GPIO_PIN_ID_TO_PORT(pin_id) (pin_id >> 4) -+# define IFX_GPIO_PIN_ID_TO_PIN(pin_id) (pin_id & 0x0F) -+ -+# define IFX_GPIO_MODULE_TAPI_VMMC 0 /* not used */ -+ -+# define ifx_gpio_pin_reserve(a,b) 0 /* obsolete */ -+ -+# define ifx_gpio_open_drain_set(a,b) ifxmips_port_set_open_drain( \ -+ IFX_GPIO_PIN_ID_TO_PORT(a), \ -+ IFX_GPIO_PIN_ID_TO_PIN(a)) -+ -+# define ifx_gpio_altsel0_set(a,b) ifxmips_port_set_altsel0( \ -+ IFX_GPIO_PIN_ID_TO_PORT(a), \ -+ IFX_GPIO_PIN_ID_TO_PIN(a)) -+ -+# define ifx_gpio_altsel1_set(a,b) ifxmips_port_set_altsel1( \ -+ IFX_GPIO_PIN_ID_TO_PORT(a), \ -+ IFX_GPIO_PIN_ID_TO_PIN(a)) -+ -+# define ifx_gpio_altsel0_clear(a,b) ifxmips_port_clear_altsel0( \ -+ IFX_GPIO_PIN_ID_TO_PORT(a), \ -+ IFX_GPIO_PIN_ID_TO_PIN(a)) -+ -+# define ifx_gpio_altsel1_clear(a,b) ifxmips_port_clear_altsel1( \ -+ IFX_GPIO_PIN_ID_TO_PORT(a), \ -+ IFX_GPIO_PIN_ID_TO_PIN(a)) -+ -+# define ifx_gpio_dir_in_set(a,b) ifxmips_port_set_dir_in( \ -+ IFX_GPIO_PIN_ID_TO_PORT(a), \ -+ IFX_GPIO_PIN_ID_TO_PIN(a)) -+ -+# define ifx_gpio_dir_out_set(a,b) ifxmips_port_set_dir_out( \ -+ IFX_GPIO_PIN_ID_TO_PORT(a), \ -+ IFX_GPIO_PIN_ID_TO_PIN(a)) -+ -+# define ifx_gpio_pin_free(a,b) ifxmips_port_free_pin( \ -+ IFX_GPIO_PIN_ID_TO_PORT(a), \ -+ IFX_GPIO_PIN_ID_TO_PIN(a)) -+# else -+# include -+# endif - #else - #error no system selected - #endif - --#define VMMC_TAPI_GPIO_MODULE_ID IFX_GPIO_MODULE_TAPI_VMMC -+#define VMMC_TAPI_GPIO_MODULE_ID IFX_GPIO_MODULE_TAPI_VMMC - /** - - */ ---- a/src/drv_vmmc_init.c -+++ b/src/drv_vmmc_init.c -@@ -48,6 +48,14 @@ - #include "drv_vmmc_pmc.h" - #endif /* PMC_SUPPORTED */ - -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)) -+# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR -+# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR -+# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR -+# define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR -+# define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR -+# define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR -+#endif - - /* ============================= */ - /* Local Macros & Definitions */ ---- a/src/drv_vmmc_init_cap.c -+++ b/src/drv_vmmc_init_cap.c -@@ -22,6 +22,11 @@ - #include "drv_mps_vmmc.h" - #include "drv_mps_vmmc_device.h" - -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)) -+# define IFX_MPS_CHIPID_VERSION_GET IFXMIPS_MPS_CHIPID_VERSION_GET -+# define IFX_MPS_CHIPID IFXMIPS_MPS_CHIPID -+#endif -+ - /* ============================= */ - /* Configuration defintions */ - /* ============================= */ ---- a/src/mps/drv_mps_vmmc_common.c -+++ b/src/mps/drv_mps_vmmc_common.c -@@ -35,8 +35,35 @@ - #include "ifxos_interrupt.h" - #include "ifxos_time.h" - --#include --#include -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)) -+# include -+# include -+# include -+ -+# define ifx_gptu_timer_request ifxmips_request_timer -+# define ifx_gptu_timer_start ifxmips_start_timer -+# define ifx_gptu_countvalue_get ifxmips_get_count_value -+# define ifx_gptu_timer_free ifxmips_free_timer -+ -+# define IFX_MPS_SRAM IFXMIPS_MPS_SRAM -+# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR -+# define IFX_MPS_AD1ENR IFXMIPS_MPS_AD1ENR -+# define IFX_MPS_VC0ENR IFXMIPS_MPS_VC0ENR -+# define IFX_MPS_SAD0SR IFXMIPS_MPS_SAD0SR -+# define IFX_MPS_RAD0SR IFXMIPS_MPS_RAD0SR -+# define IFX_MPS_RAD1SR IFXMIPS_MPS_RAD1SR -+# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR -+# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR -+# define IFX_MPS_RVC0SR IFXMIPS_MPS_RVC0SR -+# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR -+ -+# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) -+ -+# define bsp_mask_and_ack_irq ifxmips_mask_and_ack_irq -+#else -+# include -+# include -+#endif - - #include "drv_mps_vmmc.h" - #include "drv_mps_vmmc_dbg.h" -@@ -193,7 +220,8 @@ IFX_boolean_t ifx_mps_ext_bufman () - */ - IFX_void_t *ifx_mps_fastbuf_malloc (IFX_size_t size, IFX_int32_t priority) - { -- IFX_uint32_t ptr, flags; -+ unsigned long flags; -+ IFX_uint32_t ptr; - IFX_int32_t index = fastbuf_index; - - if (fastbuf_initialized == 0) -@@ -219,11 +247,11 @@ IFX_void_t *ifx_mps_fastbuf_malloc (IFX_ - if ((volatile IFX_uint32_t) fastbuf_pool[index] & FASTBUF_USED) - continue; - ptr = fastbuf_pool[index]; -- (volatile IFX_uint32_t) fastbuf_pool[index] |= FASTBUF_USED; -+ fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] | FASTBUF_USED; - if ((priority == FASTBUF_FW_OWNED) || (priority == FASTBUF_CMD_OWNED) || - (priority == FASTBUF_EVENT_OWNED) || - (priority == FASTBUF_WRITE_OWNED)) -- (volatile IFX_uint32_t) fastbuf_pool[index] |= priority; -+ fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] | priority; - fastbuf_index = index; - IFXOS_UNLOCKINT (flags); - return (IFX_void_t *) ptr; -@@ -247,7 +275,7 @@ IFX_void_t *ifx_mps_fastbuf_malloc (IFX_ - */ - IFX_void_t ifx_mps_fastbuf_free (const IFX_void_t * ptr) - { -- IFX_uint32_t flags; -+ unsigned long flags; - IFX_int32_t index = fastbuf_index; - - IFXOS_LOCKINT (flags); -@@ -261,8 +289,9 @@ IFX_void_t ifx_mps_fastbuf_free (const I - FASTBUF_EVENT_OWNED | FASTBUF_WRITE_OWNED)) - == ((IFX_uint32_t) ptr | FASTBUF_USED)) - { -- (volatile IFX_uint32_t) fastbuf_pool[index] &= ~FASTBUF_USED; -- (volatile IFX_uint32_t) fastbuf_pool[index] &= -+ fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] & ~FASTBUF_USED; -+ -+ fastbuf_pool[index] = (volatile IFX_uint32_t) fastbuf_pool[index] & - ~(FASTBUF_FW_OWNED | FASTBUF_CMD_OWNED | FASTBUF_EVENT_OWNED | - FASTBUF_WRITE_OWNED); - IFXOS_UNLOCKINT (flags); -@@ -444,7 +473,7 @@ static mps_buffer_state_e ifx_mps_bufman - */ - static IFX_int32_t ifx_mps_bufman_inc_level (IFX_uint32_t value) - { -- IFX_uint32_t flags; -+ unsigned long flags; - - if (mps_buffer.buf_level + value > MPS_BUFFER_MAX_LEVEL) - { -@@ -471,7 +500,7 @@ static IFX_int32_t ifx_mps_bufman_inc_le - */ - static IFX_int32_t ifx_mps_bufman_dec_level (IFX_uint32_t value) - { -- IFX_uint32_t flags; -+ unsigned long flags; - - if (mps_buffer.buf_level < value) - { -@@ -932,7 +961,7 @@ IFX_int32_t ifx_mps_common_open (mps_com - mps_mbx_dev * pMBDev, IFX_int32_t bcommand, - IFX_boolean_t from_kernel) - { -- IFX_uint32_t flags; -+ unsigned long flags; - - IFXOS_LOCKINT (flags); - -@@ -1048,7 +1077,7 @@ IFX_int32_t ifx_mps_common_close (mps_mb - IFX_void_t ifx_mps_release_structures (mps_comm_dev * pDev) - { - IFX_int32_t count; -- IFX_uint32_t flags; -+ unsigned long flags; - - IFXOS_LOCKINT (flags); - IFXOS_BlockFree (pFW_img_data); -@@ -1544,7 +1573,7 @@ IFX_int32_t ifx_mps_mbx_read_message (mp - IFX_uint32_t * bytes) - { - IFX_int32_t i, ret; -- IFX_uint32_t flags; -+ unsigned long flags; - - IFXOS_LOCKINT (flags); - -@@ -1751,7 +1780,7 @@ IFX_int32_t ifx_mps_mbx_write_message (m - { - mps_fifo *mbx; - IFX_uint32_t i; -- IFX_uint32_t flags; -+ unsigned long flags; - IFX_int32_t retval = -EAGAIN; - IFX_int32_t retries = 0; - IFX_uint32_t word = 0; -@@ -2138,6 +2167,7 @@ IFX_int32_t ifx_mps_mbx_write_cmd (mps_m - TRACE (MPS, DBG_LEVEL_HIGH, - ("%s(): Invalid device ID %d !\n", __FUNCTION__, pMBDev->devID)); - } -+ - return retval; - } - -@@ -2161,7 +2191,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF - mps_mbx_dev *mbx_dev; - MbxMsg_s msg; - IFX_uint32_t bytes_read = 0; -- IFX_uint32_t flags; -+ unsigned long flags; - IFX_int32_t ret; - - /* set pointer to data upstream mailbox, no matter if 0,1,2 or 3 because -@@ -2252,7 +2282,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF - { - ifx_mps_bufman_dec_level (1); - if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) && -- (atomic_read (&pMPSDev->provide_buffer->object.count) == 0)) -+ ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0)) - { - IFXOS_LockRelease (pMPSDev->provide_buffer); - } -@@ -2295,7 +2325,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF - #endif /* CONFIG_PROC_FS */ - ifx_mps_bufman_dec_level (1); - if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) && -- (atomic_read (&pMPSDev->provide_buffer->object.count) == 0)) -+ ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0)) - { - IFXOS_LockRelease (pMPSDev->provide_buffer); - } -@@ -2325,7 +2355,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF - IFX_void_t ifx_mps_mbx_cmd_upstream (IFX_ulong_t dummy) - { - mps_fifo *mbx; -- IFX_uint32_t flags; -+ unsigned long flags; - - /* set pointer to upstream command mailbox */ - mbx = &(pMPSDev->cmd_upstrm_fifo); -@@ -2373,7 +2403,7 @@ IFX_void_t ifx_mps_mbx_event_upstream (I - mps_event_msg msg; - IFX_int32_t length = 0; - IFX_int32_t read_length = 0; -- IFX_uint32_t flags; -+ unsigned long flags; - - /* set pointer to upstream event mailbox */ - mbx = &(pMPSDev->event_upstrm_fifo); -@@ -2616,7 +2646,7 @@ IFX_void_t ifx_mps_disable_mailbox_int ( - */ - IFX_void_t ifx_mps_dd_mbx_int_enable (IFX_void_t) - { -- IFX_uint32_t flags; -+ unsigned long flags; - MPS_Ad0Reg_u Ad0Reg; - - IFXOS_LOCKINT (flags); -@@ -2642,7 +2672,7 @@ IFX_void_t ifx_mps_dd_mbx_int_enable (IF - */ - IFX_void_t ifx_mps_dd_mbx_int_disable (IFX_void_t) - { -- IFX_uint32_t flags; -+ unsigned long flags; - MPS_Ad0Reg_u Ad0Reg; - - IFXOS_LOCKINT (flags); -@@ -2769,6 +2799,7 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t - } - } - -+ - if (MPS_Ad0StatusReg.fld.du_mbx) - { - #ifdef CONFIG_PROC_FS -@@ -3062,7 +3093,8 @@ IFX_int32_t ifx_mps_get_fw_version (IFX_ - */ - IFX_return_t ifx_mps_init_gpt () - { -- IFX_uint32_t flags, timer_flags, timer, loops = 0; -+ unsigned long flags; -+ IFX_uint32_t timer_flags, timer, loops = 0; - IFX_ulong_t count; - #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9) - timer = TIMER1A; ---- a/src/mps/drv_mps_vmmc_danube.c -+++ b/src/mps/drv_mps_vmmc_danube.c -@@ -32,9 +32,22 @@ - #include "ifxos_select.h" - #include "ifxos_interrupt.h" - --#include --#include --#include -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)) -+# include -+# include -+# include -+# include -+ -+# define IFX_RCU_RST_REQ IFXMIPS_RCU_RST -+# define IFX_RCU_RST_REQ_CPU1 IFXMIPS_RCU_RST_CPU1 -+ -+# define ifx_get_cp1_base prom_get_cp1_base -+# define ifx_get_cp1_size prom_get_cp1_size -+#else -+# include -+# include -+# include -+#endif - - #include "drv_mps_vmmc.h" - #include "drv_mps_vmmc_dbg.h" -@@ -119,6 +132,15 @@ IFX_int32_t ifx_mps_download_firmware (m - } - - /* check if FW image fits in available memory space */ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)) -+ if (mem > ifx_get_cp1_size()<<20) -+ { -+ TRACE (MPS, DBG_LEVEL_HIGH, -+ ("[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\n", -+ __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()<<20)); -+ return IFX_ERROR; -+ } -+#else - if (mem > ifx_get_cp1_size()) - { - TRACE (MPS, DBG_LEVEL_HIGH, -@@ -126,6 +148,7 @@ IFX_int32_t ifx_mps_download_firmware (m - __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size())); - return IFX_ERROR; - } -+#endif - - /* reset the driver */ - ifx_mps_reset (); -@@ -337,7 +360,7 @@ IFX_void_t ifx_mps_release (IFX_void_t) - */ - IFX_void_t ifx_mps_wdog_expiry() - { -- IFX_uint32_t flags; -+ unsigned long flags; - - IFXOS_LOCKINT (flags); - /* recalculate and compare the firmware checksum */ ---- a/src/mps/drv_mps_vmmc_device.h -+++ b/src/mps/drv_mps_vmmc_device.h -@@ -16,8 +16,15 @@ - declarations. - *******************************************************************************/ - --#include --#include -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)) -+# include -+# include -+# include -+# include -+#else -+# include -+# include -+#endif - - /* ============================= */ - /* MPS Common defines */ ---- a/src/mps/drv_mps_vmmc_linux.c -+++ b/src/mps/drv_mps_vmmc_linux.c -@@ -40,10 +40,26 @@ - #include - #endif /* */ - -- --#include --#include --#include -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28)) -+# include -+# include -+ -+# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR -+# define IFX_MPS_AD1ENR IFXMIPS_MPS_AD1ENR -+# define IFX_MPS_RAD0SR IFXMIPS_MPS_RAD0SR -+# define IFX_MPS_RAD1SR IFXMIPS_MPS_RAD1SR -+# define IFX_MPS_VC0ENR IFXMIPS_MPS_VC0ENR -+# define IFX_MPS_RVC0SR IFXMIPS_MPS_RVC0SR -+ -+# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) -+# define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18) -+# define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19) -+# define IFX_ICU_IM4_IER IFXMIPS_ICU_IM4_IER -+#else -+# include -+# include -+# include -+#endif - - /* lib_ifxos headers */ - #include "ifx_types.h" -@@ -914,7 +930,7 @@ IFX_int32_t ifx_mps_ioctl (struct inode - #endif /* MPS_FIFO_BLOCKING_WRITE */ - case FIO_MPS_GET_STATUS: - { -- IFX_uint32_t flags; -+ unsigned long flags; - - IFXOS_LOCKINT (flags); - -@@ -949,7 +965,7 @@ IFX_int32_t ifx_mps_ioctl (struct inode - #if CONFIG_MPS_HISTORY_SIZE > 0 - case FIO_MPS_GET_CMD_HISTORY: - { -- IFX_uint32_t flags; -+ unsigned long flags; - - if (from_kernel) - { -@@ -1637,6 +1653,7 @@ IFX_int32_t ifx_mps_get_status_proc (IFX - sprintf (buf + len, " minLv: \t %8d\n", - ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space); - } -+ - return len; - } - diff --git a/package/ifxmips-dsl-api/Config.in b/package/ifxmips-dsl-api/Config.in deleted file mode 100644 index 72942e6fff..0000000000 --- a/package/ifxmips-dsl-api/Config.in +++ /dev/null @@ -1,33 +0,0 @@ -menu "Configuration" - depends on PACKAGE_kmod-ifxmips-dsl-api - -choice - prompt "Firmware" - default IFXMIPS_ANNEX_B - help - This option controls which firmware is loaded - -config IFXMIPS_ANNEX_A - bool "Annex-A" - help - Annex-A - -config IFXMIPS_ANNEX_B - bool "Annex-B" - help - Annex-B - -endchoice - -config IFXMIPS_DSL_FIRMWARE - bool "ifxmips-dsl firmware extractor" - default y - help - Say Y, if you need ifxmips-dsl to auto extract the firmware for you from the a800 firmware image - -config IFXMIPS_DSL_DEBUG - bool "ifxmips-dsl debugging" - help - Say Y, if you need ifxmips-dsl to display debug messages. - -endmenu diff --git a/package/ifxmips-dsl-api/Makefile b/package/ifxmips-dsl-api/Makefile deleted file mode 100644 index de86cf55e9..0000000000 --- a/package/ifxmips-dsl-api/Makefile +++ /dev/null @@ -1,170 +0,0 @@ -# -# Copyright (C) 2009 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -# ralph / blogic - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=ifxmips-dsl-api -PKG_BASE_NAME:=drv_dsl_cpe_api_danube -PKG_VERSION:=3.24.4.4 -PKG_RELEASE:=1 -PKG_SOURCE:=$(PKG_BASE_NAME)-$(PKG_VERSION).tar.gz -PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/drv_dsl_cpe_api-$(PKG_VERSION) -PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/ -PKG_MD5SUM:=c45bc531c1ed2ac80f68fb986b63bb87 - -FW_BASE_NAME:=dsl_danube_firmware_adsl -FW_A_VER:=02.04.04.00.00.01 -FW_B_VER:=02.04.01.07.00.02 -FW_A_FILE_VER:=244001 -FW_B_FILE_VER:=241702 -FW_A_MD5:=f717db3067a0049a26e233ab11238710 -FW_B_MD5:=349de7cd20368f4ac9b7e8322114a512 - -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/ifxmips-dsl-api - SECTION:=sys - CATEGORY:=Kernel modules - SUBMENU:=Network Devices - TITLE:=DSL CPE API driver - URL:=http://www.infineon.com/ - MAINTAINER:=Infineon Technologies AG / Lantiq / blogic@openwrt.org - DEPENDS:=@TARGET_ifxmips @BROKEN - FILES:=$(PKG_BUILD_DIR)/src/mei/ifxmips_mei.$(LINUX_KMOD_SUFFIX) \ - $(PKG_BUILD_DIR)/src/drv_dsl_cpe_api.$(LINUX_KMOD_SUFFIX) \ - $(PKG_BUILD_DIR)/src/mei/ifxmips_atm.$(LINUX_KMOD_SUFFIX) - AUTOLOAD:=$(call AutoLoad,50,ifxmips_mei drv_dsl_cpe_api ifxmips_atm) - MENU:=1 -endef - -define KernelPackage/ifxmips-dsl-api/description - Infineon DSL CPE API for Amazon SE, Danube and Vinax. - - This package contains the DSL CPE API driver for Amazon SE & Danube. - - Supported Devices: - - Amazon SE - - Danube - - This package was kindly contributed to openwrt by Infineon/Lantiq -endef - -define KernelPackage/ifxmips-dsl-api/config - source "$(SOURCE)/Config.in" -endef - -ifeq ($(CONFIG_IFXMIPS_DSL_FIRMWARE),y) -FW_FILE:=arcor_A800_452CPW_FW_1.02.206(20081201).bin -define Download/firmware - URL:=http://www.arcor.de/hilfe/files/pdf/ - FILE=$(FW_FILE) - MD5SUM:=19d9af4e369287a0f0abaed415cdac10 -endef -$(eval $(call Download,firmware)) - -else - -define Download/annex-a - FILE:=$(FW_BASE_NAME)_a-$(FW_A_VER).tar.gz - URL:=http://mirror2.openwrt.org/sources/ - MD5SUM:=$(FW_A_MD5) -endef -$(eval $(call Download,annex-a)) - -define Download/annex-b - FILE:=$(FW_BASE_NAME)_b-$(FW_B_VER).tar.gz - URL:=http://mirror2.openwrt.org/sources/ - MD5SUM:=$(FW_B_MD5) -endef -$(eval $(call Download,annex-b)) -endif - -IFX_DSL_MAX_DEVICE=1 -IFX_DSL_LINES_PER_DEVICE=1 -IFX_DSL_CHANNELS_PER_LINE=1 - -CONFIGURE_ARGS += --enable-kernel-include="$(LINUX_DIR)/include" \ - --with-max-device="$(IFX_DSL_MAX_DEVICE)" \ - --with-lines-per-device="$(IFX_DSL_LINES_PER_DEVICE)" \ - --with-channels-per-line="$(IFX_DSL_CHANNELS_PER_LINE)" \ - --enable-danube \ - --enable-add-drv-cflags="-DMODULE" \ - --disable-dsl-delt-static \ - --disable-adsl-led \ - --enable-dsl-ceoc \ - --enable-dsl-pm \ - --enable-dsl-pm-total \ - --enable-dsl-pm-history \ - --enable-dsl-pm-showtime \ - --enable-dsl-pm-channel-counters \ - --enable-dsl-pm-datapath-counters \ - --enable-dsl-pm-line-counters \ - --enable-dsl-pm-channel-thresholds \ - --enable-dsl-pm-datapath-thresholds \ - --enable-dsl-pm-line-thresholds \ - --enable-dsl-pm-optional-parameters \ - --enable-linux-26 \ - --enable-kernelbuild="$(LINUX_DIR)" \ - ARCH=$(LINUX_KARCH) - -EXTRA_CFLAGS = -fno-pic -mno-abicalls -mlong-calls -G 0 - -ifeq ($(CONFIG_IFXMIPS_DSL_DEBUG),y) -CONFIGURE_ARGS += \ - --enable-debug=yes \ - --enable-debug-prints=yes -EXTRA_CFLAGS += -DDEBUG -endif - -define Build/Prepare - $(PKG_UNPACK) - $(INSTALL_DIR) $(PKG_BUILD_DIR)/src/mei/ - $(CP) ./src/* $(PKG_BUILD_DIR)/src/mei/ - $(Build/Patch) - $(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(FW_BASE_NAME)_a-$(FW_A_VER).tar.gz - $(TAR) -C $(PKG_BUILD_DIR) -xzf $(DL_DIR)/$(FW_BASE_NAME)_b-$(FW_B_VER).tar.gz -endef - -define Build/Configure - (cd $(PKG_BUILD_DIR); aclocal && autoconf && automake) - $(call Build/Configure/Default) -endef - -define Build/Compile - cd $(LINUX_DIR); \ - ARCH=mips CROSS_COMPILE="$(KERNEL_CROSS)" \ - $(MAKE) M=$(PKG_BUILD_DIR)/src/mei/ V=1 modules - $(call Build/Compile/Default) -endef - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/include - $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api.h $(1)/usr/include - $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_ioctl.h $(1)/usr/include - $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_adslmib.h $(1)/usr/include - $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_adslmib_ioctl.h $(1)/usr/include - $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_g997.h $(1)/usr/include - $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_types.h $(1)/usr/include - $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_pm.h $(1)/usr/include - $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_api_error.h $(1)/usr/include - $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_danube_ctx.h $(1)/usr/include - $(CP) $(PKG_BUILD_DIR)/src/include/drv_dsl_cpe_cmv_danube.h $(1)/usr/include -endef - -define KernelPackage/ifxmips-dsl-api/install - $(INSTALL_DIR) $(1)/lib/firmware/ -ifeq ($(CONFIG_IFXMIPS_DSL_FIRMWARE),y) - $(PLATFORM_DIR)/extract.sh $(DL_DIR) '$(FW_FILE)' - $(CP) $(DL_DIR)/dsl_$(if $(CONFIG_IFXMIPS_ANNEX_A),a,b).bin $(1)/lib/firmware/ModemHWE.bin -else - $(CP) $(PKG_BUILD_DIR)/$(FW_BASE_NAME)_$(if $(CONFIG_IFXMIPS_ANNEX_A),a_$(FW_A_FILE_VER),b_$(FW_B_FILE_VER)).bin $(1)/lib/firmware/ModemHWE.bin -endif -endef - -$(eval $(call KernelPackage,ifxmips-dsl-api)) diff --git a/package/ifxmips-dsl-api/patches/100-dsl_compat.patch b/package/ifxmips-dsl-api/patches/100-dsl_compat.patch deleted file mode 100644 index dea82f0304..0000000000 --- a/package/ifxmips-dsl-api/patches/100-dsl_compat.patch +++ /dev/null @@ -1,39 +0,0 @@ ---- a/src/include/drv_dsl_cpe_device_danube.h -+++ b/src/include/drv_dsl_cpe_device_danube.h -@@ -24,7 +24,7 @@ - #include "drv_dsl_cpe_simulator_danube.h" - #else - /* Include for the low level driver interface header file */ --#include "asm/ifx/ifx_mei_bsp.h" -+#include "mei/ifxmips_mei_interface.h" - #endif /* defined(DSL_CPE_SIMULATOR_DRIVER) && defined(WIN32)*/ - - #define DSL_MAX_LINE_NUMBER 1 ---- a/src/common/drv_dsl_cpe_os_linux.c -+++ b/src/common/drv_dsl_cpe_os_linux.c -@@ -11,6 +11,7 @@ - #ifdef __LINUX__ - - #define DSL_INTERN -+#include - - #include "drv_dsl_cpe_api.h" - #include "drv_dsl_cpe_api_ioctl.h" -@@ -1058,6 +1059,7 @@ static void DSL_DRV_DebugInit(void) - /* Entry point of driver */ - int __init DSL_ModuleInit(void) - { -+ struct class *dsl_class; - DSL_int_t i; - - printk(DSL_DRV_CRLF DSL_DRV_CRLF "Infineon CPE API Driver version: %s" DSL_DRV_CRLF, -@@ -1104,7 +1106,8 @@ int __init DSL_ModuleInit(void) - } - - DSL_DRV_DevNodeInit(); -- -+ dsl_class = class_create(THIS_MODULE, "dsl_cpe_api"); -+ device_create(dsl_class, NULL, MKDEV(DRV_DSL_CPE_API_DEV_MAJOR, 0), NULL, "dsl_cpe_api"); - return 0; - } - diff --git a/package/ifxmips-dsl-api/patches/200-mei_compat.patch b/package/ifxmips-dsl-api/patches/200-mei_compat.patch deleted file mode 100644 index 352a974e60..0000000000 --- a/package/ifxmips-dsl-api/patches/200-mei_compat.patch +++ /dev/null @@ -1,94 +0,0 @@ ---- a/src/mei/ifxmips_mei.c -+++ b/src/mei/ifxmips_mei.c -@@ -41,18 +41,20 @@ - #include - #include - #include -+#include -+#include - #include - #include --#include --#include --#include --//#include --#include --#include -+ -+#include -+#include -+#include -+#include -+#include "ifxmips_atm.h" - #define IFX_MEI_BSP - #include "ifxmips_mei_interface.h" - --#define IFXMIPS_RCU_RST IFX_RCU_RST_REQ -+/*#define IFXMIPS_RCU_RST IFX_RCU_RST_REQ - #define IFXMIPS_RCU_RST_REQ_ARC_JTAG IFX_RCU_RST_REQ_ARC_JTAG - #define IFXMIPS_RCU_RST_REQ_DFE IFX_RCU_RST_REQ_DFE - #define IFXMIPS_RCU_RST_REQ_AFE IFX_RCU_RST_REQ_AFE -@@ -76,7 +78,7 @@ - #define ifxmips_r32(reg) __raw_readl(reg) - #define ifxmips_w32(val, reg) __raw_writel(val, reg) - #define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg) -- -+*/ - #define IFX_MEI_EMSG(fmt, args...) printk(KERN_ERR "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args) - #define IFX_MEI_DMSG(fmt, args...) printk(KERN_INFO "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args) - -@@ -173,7 +175,8 @@ static u32 *mei_arc_swap_buff = NULL; // - extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr); - #define MEI_MASK_AND_ACK_IRQ ifxmips_mask_and_ack_irq - --static int dev_major = 105; -+#define MEI_MAJOR 105 -+static int dev_major = MEI_MAJOR; - - static struct file_operations bsp_mei_operations = { - owner:THIS_MODULE, -@@ -2294,10 +2297,10 @@ IFX_MEI_InitDevice (int num) - IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DFEIR]); - return -1; - } -- if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) { -+ /*if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) { - IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DYING_GASP]); - return -1; -- } -+ }*/ - // IFX_MEI_DMSG("Device %d initialized. IER %#x\n", num, bsp_get_irq_ier(pDev->nIrq[IFX_DYING_GASP])); - return 0; - } -@@ -2922,6 +2925,7 @@ int __init - IFX_MEI_ModuleInit (void) - { - int i = 0; -+ static struct class *dsl_class; - - printk ("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision); - -@@ -2935,14 +2939,15 @@ IFX_MEI_ModuleInit (void) - IFX_MEI_InitProcFS (i); - #endif - } -- for (i = 0; i <= DSL_BSP_CB_LAST ; i++) -+ for (i = 0; i <= DSL_BSP_CB_LAST ; i++) - dsl_bsp_event_callback[i].function = NULL; - - #ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK - printk(KERN_INFO "[%s %s %d]: Start loopback test...\n", __FILE__, __func__, __LINE__); - DFE_Loopback_Test (); - #endif -- -+ dsl_class = class_create(THIS_MODULE, "ifx_mei"); -+ device_create(dsl_class, NULL, MKDEV(MEI_MAJOR, 0), NULL, "ifx_mei"); - return 0; - } - -@@ -2996,3 +3001,5 @@ EXPORT_SYMBOL (DSL_BSP_EventCBUnregister - - module_init (IFX_MEI_ModuleInit); - module_exit (IFX_MEI_ModuleExit); -+ -+MODULE_LICENSE("Dual BSD/GPL"); diff --git a/package/ifxmips-dsl-api/patches/300-atm_compat.patch b/package/ifxmips-dsl-api/patches/300-atm_compat.patch deleted file mode 100644 index 27dc163079..0000000000 --- a/package/ifxmips-dsl-api/patches/300-atm_compat.patch +++ /dev/null @@ -1,156 +0,0 @@ ---- a/src/mei/ifxmips_atm_core.c -+++ b/src/mei/ifxmips_atm_core.c -@@ -58,9 +58,8 @@ - /* - * Chip Specific Head File - */ --#include --#include --#include -+#include -+#include - #include "ifxmips_atm_core.h" - - -@@ -1146,7 +1145,7 @@ static INLINE void mailbox_signal(unsign - - static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue) - { -- unsigned int qsb_clk = ifx_get_fpi_hz(); -+ unsigned int qsb_clk = ifxmips_get_fpi_hz(); - unsigned int qsb_qid = queue + FIRST_QSB_QID; - union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}}; - union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}}; -@@ -1318,7 +1317,7 @@ static void set_qsb(struct atm_vcc *vcc, - - static void qsb_global_set(void) - { -- unsigned int qsb_clk = ifx_get_fpi_hz(); -+ unsigned int qsb_clk = ifxmips_get_fpi_hz(); - int i; - unsigned int tmp1, tmp2, tmp3; - -@@ -2505,3 +2504,4 @@ static void __exit ifx_atm_exit(void) - - module_init(ifx_atm_init); - module_exit(ifx_atm_exit); -+MODULE_LICENSE("Dual BSD/GPL"); ---- a/src/mei/ifxmips_atm_ppe_common.h -+++ b/src/mei/ifxmips_atm_ppe_common.h -@@ -1,9 +1,10 @@ - #ifndef IFXMIPS_ATM_PPE_COMMON_H - #define IFXMIPS_ATM_PPE_COMMON_H - -- -- --#if defined(CONFIG_DANUBE) -+#if defined(CONFIG_IFXMIPS) -+ #include "ifxmips_atm_ppe_danube.h" -+ #define CONFIG_DANUBE -+#elif defined(CONFIG_DANUBE) - #include "ifxmips_atm_ppe_danube.h" - #elif defined(CONFIG_AMAZON_SE) - #include "ifxmips_atm_ppe_amazon_se.h" -@@ -16,7 +17,6 @@ - #endif - - -- - /* - * Code/Data Memory (CDM) Interface Configuration Register - */ ---- a/src/mei/ifxmips_atm_core.h -+++ b/src/mei/ifxmips_atm_core.h -@@ -25,8 +25,8 @@ - #define IFXMIPS_ATM_CORE_H - - -- --#include -+#include "ifxmips_compat.h" -+#include "ifx_atm.h" - #include "ifxmips_atm_ppe_common.h" - #include "ifxmips_atm_fw_regs_common.h" - ---- /dev/null -+++ b/src/mei/ifxmips_compat.h -@@ -0,0 +1,43 @@ -+#ifndef _IFXMIPS_COMPAT_H__ -+#define _IFXMIPS_COMPAT_H__ -+ -+#define IFX_SUCCESS 0 -+#define IFX_ERROR (-1) -+ -+#define ATM_VBR_NRT ATM_VBR -+#define ATM_VBR_RT 6 -+#define ATM_UBR_PLUS 7 -+#define ATM_GFR 8 -+ -+#define NUM_ENTITY(x) (sizeof(x) / sizeof(*(x))) -+ -+#define SET_BITS(x, msb, lsb, value) \ -+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) -+ -+ -+#define IFX_PMU_ENABLE 1 -+#define IFX_PMU_DISABLE 0 -+ -+#define IFX_PMU_MODULE_DSL_DFE (1 << 9) -+#define IFX_PMU_MODULE_AHBS (1 << 13) -+#define IFX_PMU_MODULE_PPE_QSB (1 << 18) -+#define IFX_PMU_MODULE_PPE_SLL01 (1 << 19) -+#define IFX_PMU_MODULE_PPE_TC (1 << 21) -+#define IFX_PMU_MODULE_PPE_EMA (1 << 22) -+#define IFX_PMU_MODULE_PPE_TOP (1 << 29) -+ -+#define ifx_pmu_set(a,b) {if(a == IFX_PMU_ENABLE) ifxmips_pmu_enable(b); else ifxmips_pmu_disable(b);} -+ -+#define PPE_TOP_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x)) -+#define PPE_SLL01_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_SLL01, (__x)) -+#define PPE_TC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TC, (__x)) -+#define PPE_EMA_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_EMA, (__x)) -+#define PPE_QSB_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_QSB, (__x)) -+#define PPE_TPE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHBS, (__x)) -+#define DSL_DFE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DSL_DFE, (__x)) -+ -+#define IFX_REG_W32(_v, _r) __raw_writel((_v), (_r)) -+ -+#define CONFIG_IFXMIPS_DSL_CPE_MEI y -+ -+#endif ---- a/src/mei/ifxmips_atm_ppe_danube.h -+++ b/src/mei/ifxmips_atm_ppe_danube.h -@@ -1,7 +1,7 @@ - #ifndef IFXMIPS_ATM_PPE_DANUBE_H - #define IFXMIPS_ATM_PPE_DANUBE_H - -- -+#include - - /* - * FPI Configuration Bus Register and Memory Address Mapping -@@ -93,7 +93,7 @@ - /* - * Mailbox IGU1 Interrupt - */ --#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24 -+#define PPE_MAILBOX_IGU1_INT IFXMIPS_PPE_MBOX_INT - - - ---- a/src/mei/ifxmips_atm_danube.c -+++ b/src/mei/ifxmips_atm_danube.c -@@ -45,10 +45,9 @@ - /* - * Chip Specific Head File - */ --#include --#include --#include --#include -+#include -+#include -+#include "ifxmips_compat.h" - #include "ifxmips_atm_core.h" - #include "ifxmips_atm_fw_danube.h" - diff --git a/package/ifxmips-dsl-api/patches/400-debug-output.patch b/package/ifxmips-dsl-api/patches/400-debug-output.patch deleted file mode 100644 index 59d4b41cc4..0000000000 --- a/package/ifxmips-dsl-api/patches/400-debug-output.patch +++ /dev/null @@ -1,286 +0,0 @@ ---- a/src/mei/ifxmips_mei.c -+++ b/src/mei/ifxmips_mei.c -@@ -79,8 +79,8 @@ - #define ifxmips_w32(val, reg) __raw_writel(val, reg) - #define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg) - */ --#define IFX_MEI_EMSG(fmt, args...) printk(KERN_ERR "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args) --#define IFX_MEI_DMSG(fmt, args...) printk(KERN_INFO "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args) -+#define IFX_MEI_EMSG(fmt, args...) pr_err("[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args) -+#define IFX_MEI_DMSG(fmt, args...) pr_debug("[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args) - - #ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK - //#define DFE_MEM_TEST -@@ -1301,7 +1301,7 @@ IFX_MEI_RunAdslModem (DSL_DEV_Device_t * - IFX_MEI_EMSG (">>> malloc fail for codeswap buff!!! <<<\n"); - return DSL_DEV_MEI_ERR_FAILURE; - } -- printk("allocate %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff); -+ IFX_MEI_DMSG("allocate %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff); - } - - DSL_DEV_PRIVATE(pDev)->img_hdr = -@@ -1476,7 +1476,7 @@ IFX_MEI_DFEMemoryFree (DSL_DEV_Device_t - } - - if(mei_arc_swap_buff != NULL){ -- printk("free %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff); -+ IFX_MEI_DMSG("free %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff); - kfree(mei_arc_swap_buff); - mei_arc_swap_buff=NULL; - } -@@ -1496,7 +1496,7 @@ IFX_MEI_DFEMemoryAlloc (DSL_DEV_Device_t - // DSL_DEV_PRIVATE(pDev)->adsl_mem_info; - int allocate_size = SDRAM_SEGMENT_SIZE; - -- printk(KERN_INFO "[%s %d]: image_size = %ld\n", __func__, __LINE__, size); -+ IFX_MEI_DMSG("image_size = %ld\n", size); - // Alloc Swap Pages - for (idx = 0; size > 0 && idx < MAX_BAR_REGISTERS; idx++) { - // skip bar15 for XDATA usage. -@@ -1596,7 +1596,7 @@ DSL_BSP_FWDownload (DSL_DEV_Device_t * p - ssize_t retval = -ENOMEM; - int idx = 0; - -- printk("\n%s\n", __func__); -+ IFX_MEI_DMSG("\n"); - - if (*loff == 0) { - if (size < sizeof (img_hdr_tmp)) { -@@ -1648,7 +1648,7 @@ DSL_BSP_FWDownload (DSL_DEV_Device_t * p - goto error; - } - adsl_mem_info[XDATA_REGISTER].type = FREE_RELOAD; -- printk(KERN_INFO "[%s %d] -> IFX_MEI_BarUpdate()\n", __func__, __LINE__); -+ IFX_MEI_DMSG("-> IFX_MEI_BarUpdate()\n"); - IFX_MEI_BarUpdate (pDev, (DSL_DEV_PRIVATE(pDev)->nBar)); - } - else if (DSL_DEV_PRIVATE(pDev)-> image_size == 0) { -@@ -1927,7 +1927,7 @@ static void - WriteMbox (u32 * mboxarray, u32 size) - { - IFX_MEI_DebugWrite (&dsl_devices[0], IMBOX_BASE, mboxarray, size); -- printk ("write to %X\n", IMBOX_BASE); -+ IFX_MEI_DMSG("write to %X\n", IMBOX_BASE); - IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV); - } - -@@ -1936,7 +1936,7 @@ static void - ReadMbox (u32 * mboxarray, u32 size) - { - IFX_MEI_DebugRead (&dsl_devices[0], OMBOX_BASE, mboxarray, size); -- printk ("read from %X\n", OMBOX_BASE); -+ IFX_MEI_DMSG("read from %X\n", OMBOX_BASE); - } - - static void -@@ -1966,7 +1966,7 @@ arc_code_page_download (uint32_t arc_cod - { - int count; - -- printk ("try to download pages,size=%d\n", arc_code_length); -+ IFX_MEI_DMSG("try to download pages,size=%d\n", arc_code_length); - IFX_MEI_ControlModeSet (&dsl_devices[0], MEI_MASTER_MODE); - IFX_MEI_HaltArc (&dsl_devices[0]); - IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_AD, 0); -@@ -2005,21 +2005,21 @@ dfe_loopback_irq_handler (DSL_DEV_Device - memset (&rd_mbox[0], 0, 10 * 4); - ReadMbox (&rd_mbox[0], 6); - if (rd_mbox[0] == 0x0) { -- printk ("Get ARC_ACK\n"); -+ FX_MEI_DMSG("Get ARC_ACK\n"); - got_int = 1; - } - else if (rd_mbox[0] == 0x5) { -- printk ("Get ARC_BUSY\n"); -+ IFX_MEI_DMSG("Get ARC_BUSY\n"); - got_int = 2; - } - else if (rd_mbox[0] == 0x3) { -- printk ("Get ARC_EDONE\n"); -+ IFX_MEI_DMSG("Get ARC_EDONE\n"); - if (rd_mbox[1] == 0x0) { - got_int = 3; -- printk ("Get E_MEMTEST\n"); -+ IFX_MEI_DMSG("Get E_MEMTEST\n"); - if (rd_mbox[2] != 0x1) { - got_int = 4; -- printk ("Get Result %X\n", rd_mbox[2]); -+ IFX_MEI_DMSG("Get Result %X\n", rd_mbox[2]); - } - } - } -@@ -2037,21 +2037,21 @@ wait_mem_test_result (void) - uint32_t mbox[5]; - mbox[0] = 0; - -- printk ("Waiting Starting\n"); -+ IFX_MEI_DMSG("Waiting Starting\n"); - while (mbox[0] == 0) { - ReadMbox (&mbox[0], 5); - } -- printk ("Try to get mem test result.\n"); -+ IFX_MEI_DMSG("Try to get mem test result.\n"); - ReadMbox (&mbox[0], 5); - if (mbox[0] == 0xA) { -- printk ("Success.\n"); -+ IFX_MEI_DMSG("Success.\n"); - } - else if (mbox[0] == 0xA) { -- printk ("Fail,address %X,except data %X,receive data %X\n", -+ IFX_MEI_EMSG("Fail,address %X,except data %X,receive data %X\n", - mbox[1], mbox[2], mbox[3]); - } - else { -- printk ("Fail\n"); -+ IFX_MEI_EMSG("Fail\n"); - } - } - -@@ -2067,7 +2067,7 @@ arc_ping_testing (DSL_DEV_Device_t *pDev - rd_mbox[i] = 0; - } - -- printk ("send ping msg\n"); -+ FX_MEI_DMSG("send ping msg\n"); - wr_mbox[0] = MEI_PING; - WriteMbox (&wr_mbox[0], 10); - -@@ -2075,7 +2075,7 @@ arc_ping_testing (DSL_DEV_Device_t *pDev - MEI_WAIT (100); - } - -- printk ("send start event\n"); -+ IFX_MEI_DMSG("send start event\n"); - got_int = 0; - - wr_mbox[0] = 0x4; -@@ -2094,14 +2094,14 @@ arc_ping_testing (DSL_DEV_Device_t *pDev - IFX_MEI_LongWordWriteOffset (&dsl_devices[0], - (u32) ME_ME2ARC_INT, - MEI_TO_ARC_MSGAV); -- printk ("sleeping\n"); -+ IFX_MEI_DMSG("sleeping\n"); - while (1) { - if (got_int > 0) { - - if (got_int > 3) -- printk ("got_int >>>> 3\n"); -+ IFX_MEI_DMSG("got_int >>>> 3\n"); - else -- printk ("got int = %d\n", got_int); -+ IFX_MEI_DMSG("got int = %d\n", got_int); - got_int = 0; - //schedule(); - DSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]); -@@ -2152,7 +2152,7 @@ DFE_Loopback_Test (void) - DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].type = FREE_RELOAD; - IFX_MEI_WRITE_REGISTER_L ((((uint32_t) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address) & 0x0fffffff), - IFXMIPS_MEI_BASE_ADDR + ME_XMEM_BAR_BASE + idx * 4); -- printk ("bar%d(%X)=%X\n", idx, -+ IFX_MEI_DMSG("bar%d(%X)=%X\n", idx, - IFXMIPS_MEI_BASE_ADDR + ME_XMEM_BAR_BASE + - idx * 4, (((uint32_t) - ((ifx_mei_device_private_t *) -@@ -2169,20 +2169,20 @@ DFE_Loopback_Test (void) - return DSL_DEV_MEI_ERR_FAILURE; - } - //WriteARCreg(AUX_IC_CTRL,2); -- printk(KERN_INFO "[%s %s %d]: Setting MEI_MASTER_MODE..\n", __FILE__, __func__, __LINE__); -+ IFX_MEI_DMSG("Setting MEI_MASTER_MODE..\n"); - IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE); - #define AUX_IC_CTRL 0x11 - _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, - AUX_IC_CTRL, 2); -- printk(KERN_INFO "[%s %s %d]: Setting JTAG_MASTER_MODE..\n", __FILE__, __func__, __LINE__); -+ IFX_MEI_DMSG("Setting JTAG_MASTER_MODE..\n"); - IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE); - -- printk(KERN_INFO "[%s %s %d]: Halting ARC...\n", __FILE__, __func__, __LINE__); -+ IFX_MEI_DMSG("Halting ARC...\n"); - IFX_MEI_HaltArc (&dsl_devices[0]); - - #ifdef DFE_PING_TEST - -- printk ("ping test image size=%d\n", sizeof (arc_ahb_access_code)); -+ IFX_MEI_DMSG("ping test image size=%d\n", sizeof (arc_ahb_access_code)); - memcpy ((u8 *) (DSL_DEV_PRIVATE(pDev)-> - adsl_mem_info[0].address + 0x1004), - &arc_ahb_access_code[0], sizeof (arc_ahb_access_code)); -@@ -2190,13 +2190,13 @@ DFE_Loopback_Test (void) - - #endif //DFE_PING_TEST - -- printk ("ARC ping test code download complete\n"); -+ IFX_MEI_DMSG("ARC ping test code download complete\n"); - #endif //defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK) - #ifdef DFE_MEM_TEST - IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_MASK, MSGAV_EN); - - arc_code_page_download (1537, &code_array[0]); -- printk ("ARC mem test code download complete\n"); -+ IFX_MEI_DMSG("ARC mem test code download complete\n"); - #endif //DFE_MEM_TEST - #ifdef DFE_ATM_LOOPBACK - arc_debug_data = 0xf; -@@ -2215,7 +2215,7 @@ DFE_Loopback_Test (void) - IFX_MEI_DebugWrite (&dsl_devices[0], 0x32010, &arc_debug_data, 1); - #endif //DFE_ATM_LOOPBACK - IFX_MEI_IRQEnable (pDev); -- printk(KERN_INFO "[%s %s %d]: run ARC...\n", __FILE__, __func__, __LINE__); -+ IFX_MEI_DMSG("run ARC...\n"); - IFX_MEI_RunArc (&dsl_devices[0]); - - #ifdef DFE_PING_TEST -@@ -2526,7 +2526,7 @@ IFX_MEI_Ioctls (DSL_DEV_Device_t * pDev, - break; - - case DSL_FIO_BSP_DSL_START: -- printk("\n%s: DSL_FIO_BSP_DSL_START\n",__func__); -+ IFX_MEI_DMSG("DSL_FIO_BSP_DSL_START\n"); - if ((meierr = IFX_MEI_RunAdslModem (pDev)) != DSL_DEV_MEI_ERR_SUCCESS) { - IFX_MEI_EMSG ("IFX_MEI_RunAdslModem() error..."); - meierr = DSL_DEV_MEI_ERR_FAILURE; -@@ -2927,11 +2927,11 @@ IFX_MEI_ModuleInit (void) - int i = 0; - static struct class *dsl_class; - -- printk ("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision); -+ pr_info("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision); - - for (i = 0; i < BSP_MAX_DEVICES; i++) { - if (IFX_MEI_InitDevice (i) != 0) { -- printk ("%s: Init device fail!\n", __FUNCTION__); -+ IFX_MEI_EMSG("Init device fail!\n"); - return -EIO; - } - IFX_MEI_InitDevNode (i); -@@ -2943,7 +2943,7 @@ IFX_MEI_ModuleInit (void) - dsl_bsp_event_callback[i].function = NULL; - - #ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK -- printk(KERN_INFO "[%s %s %d]: Start loopback test...\n", __FILE__, __func__, __LINE__); -+ IFX_MEI_DMSG("Start loopback test...\n"); - DFE_Loopback_Test (); - #endif - dsl_class = class_create(THIS_MODULE, "ifx_mei"); ---- a/src/mei/ifxmips_atm_core.c -+++ b/src/mei/ifxmips_atm_core.c -@@ -2335,7 +2335,7 @@ static int atm_showtime_enter(struct por - IFX_REG_W32(0x0F, UTP_CFG); - #endif - -- printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n", g_atm_priv_data.port[0].tx_max_cell_rate, g_atm_priv_data.port[1].tx_max_cell_rate, (unsigned int)g_xdata_addr); -+ pr_debug("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n", g_atm_priv_data.port[0].tx_max_cell_rate, g_atm_priv_data.port[1].tx_max_cell_rate, (unsigned int)g_xdata_addr); - - return IFX_SUCCESS; - } -@@ -2351,7 +2351,7 @@ static int atm_showtime_exit(void) - // TODO: ReTX clean state - g_xdata_addr = NULL; - -- printk("leave showtime\n"); -+ pr_debug("leave showtime\n"); - - return IFX_SUCCESS; - } diff --git a/package/ifxmips-dsl-api/patches/500-portability.patch b/package/ifxmips-dsl-api/patches/500-portability.patch deleted file mode 100644 index cbac514f20..0000000000 --- a/package/ifxmips-dsl-api/patches/500-portability.patch +++ /dev/null @@ -1,184 +0,0 @@ ---- a/configure.in -+++ b/configure.in -@@ -333,12 +333,12 @@ AC_ARG_ENABLE(ifxos-include, - echo Set the lib_ifxos include path $enableval - AC_SUBST([IFXOS_INCLUDE_PATH],[$enableval]) - else -- echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH -+ echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH - AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH]) - fi - ], - [ -- echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH -+ echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH - AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH]) - ] - ) -@@ -1702,73 +1702,73 @@ dnl Set the configure params for dist ch - AC_SUBST([DISTCHECK_CONFIGURE_PARAMS],[$CONFIGURE_OPTIONS]) - - AC_CONFIG_COMMANDS_PRE([ --echo -e "------------------------------------------------------------------------" --echo -e " Configuration for drv_dsl_cpe_api:" --echo -e " Configure model type: $DSL_CONFIG_MODEL_TYPE" --echo -e " Source code location: $srcdir" --echo -e " Compiler: $CC" --echo -e " Compiler c-flags: $CFLAGS" --echo -e " Extra compiler c-flags: $EXTRA_DRV_CFLAGS" --echo -e " Host System Type: $host" --echo -e " Install path: $prefix" --echo -e " Linux kernel include path: $KERNEL_INCL_PATH" --echo -e " Linux kernel build path: $KERNEL_BUILD_PATH" --echo -e " Linux kernel architecture: $KERNEL_ARCH" --echo -e " Include IFXOS: $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT" --echo -e " IFXOS include path: $IFXOS_INCLUDE_PATH" --echo -e " Driver Include Path $DSL_DRIVER_INCL_PATH" --echo -e " DSL device: $DSL_DEVICE_NAME" --echo -e " Max device number: $DSL_DRV_MAX_DEVICE_NUMBER" --echo -e " Channels per line: $DSL_CHANNELS_PER_LINE" --echo -e " Build lib (only for kernel 2.6) $DSL_CPE_API_LIBRARY_BUILD_2_6" --echo -e " DSL data led flash frequency: $DSL_DATA_LED_FLASH_FREQUENCY Hz" --echo -e " Disable debug prints: $DSL_DEBUG_DISABLE" --echo -e " Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET" --echo -e " Preselected max. debug level: $DSL_DBG_MAX_LEVEL_PRE" --echo -e " Include deprecated functions: $INCLUDE_DEPRECATED" --echo -e " Include Device Exception Codes: $INCLUDE_DEVICE_EXCEPTION_CODES" --echo -e " Include FW request support: $INCLUDE_FW_REQUEST_SUPPORT" --echo -e " Include ADSL trace buffer: $INCLUDE_DSL_CPE_TRACE_BUFFER" --echo -e " Include ADSL MIB: $INCLUDE_DSL_ADSL_MIB" --echo -e " Include ADSL LED: $INCLUDE_ADSL_LED" --echo -e " Include CEOC: $INCLUDE_DSL_CEOC" --echo -e " Include config get support: $INCLUDE_DSL_CONFIG_GET" --echo -e " Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE" --echo -e " Include Resource Statistics: $INCLUDE_DSL_RESOURCE_STATISTICS" --echo -e " Include Framing Parameters: $INCLUDE_DSL_FRAMING_PARAMETERS" --echo -e " Include G997 Line Inventory: $INCLUDE_DSL_G997_LINE_INVENTORY" --echo -e " Include G997 Framing Parameters: $INCLUDE_DSL_G997_FRAMING_PARAMETERS" --echo -e " Include G997 per tone data: $INCLUDE_DSL_G997_PER_TONE" --echo -e " Include G997 status: $INCLUDE_DSL_G997_STATUS" --echo -e " Include G997 alarm: $INCLUDE_DSL_G997_ALARM" --echo -e " Include DSL Bonding: $INCLUDE_DSL_BONDING" --echo -e " Include Misc Line Status $INCLUDE_DSL_CPE_MISC_LINE_STATUS" --echo -e " Include DELT: $INCLUDE_DSL_DELT" --echo -e " Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA" --echo -e " Include PM: $INCLUDE_DSL_PM" --echo -e " Include PM config: $INCLUDE_DSL_CPE_PM_CONFIG" --echo -e " Include PM total: $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS" --echo -e " Include PM history: $INCLUDE_DSL_CPE_PM_HISTORY" --echo -e " Include PM showtime: $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS" --echo -e " Include PM optional: $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS" --echo -e " Include PM line: $INCLUDE_DSL_CPE_PM_LINE_COUNTERS" --echo -e " Include PM line event showtime: $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS" --echo -e " Include PM channel: $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS" --echo -e " Include PM channel extended: $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS" --echo -e " Include PM data path: $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS" --echo -e " Include PM data path failure: $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS" --echo -e " Include PM ReTx: $INCLUDE_DSL_CPE_PM_RETX_COUNTERS" --echo -e " Include PM line threshold: $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS" --echo -e " Include PM channel threshold: $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS" --echo -e " Include PM data path threshold: $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS" --echo -e " Include PM ReTx threshold: $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS" --echo -e " Include FW memory free support: $INCLUDE_DSL_FIRMWARE_MEMORY_FREE" --echo -e "----------------------- deprectated ! ----------------------------------" --echo -e " Include PM line failure: $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS" --echo -e "" --echo -e " Settings:" --echo -e " Configure options: $CONFIGURE_OPTIONS" --echo -e "------------------------------------------------------------------------" -+echo "------------------------------------------------------------------------" -+echo " Configuration for drv_dsl_cpe_api:" -+echo " Configure model type: $DSL_CONFIG_MODEL_TYPE" -+echo " Source code location: $srcdir" -+echo " Compiler: $CC" -+echo " Compiler c-flags: $CFLAGS" -+echo " Extra compiler c-flags: $EXTRA_DRV_CFLAGS" -+echo " Host System Type: $host" -+echo " Install path: $prefix" -+echo " Linux kernel include path: $KERNEL_INCL_PATH" -+echo " Linux kernel build path: $KERNEL_BUILD_PATH" -+echo " Linux kernel architecture: $KERNEL_ARCH" -+echo " Include IFXOS: $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT" -+echo " IFXOS include path: $IFXOS_INCLUDE_PATH" -+echo " Driver Include Path $DSL_DRIVER_INCL_PATH" -+echo " DSL device: $DSL_DEVICE_NAME" -+echo " Max device number: $DSL_DRV_MAX_DEVICE_NUMBER" -+echo " Channels per line: $DSL_CHANNELS_PER_LINE" -+echo " Build lib (only for kernel 2.6) $DSL_CPE_API_LIBRARY_BUILD_2_6" -+echo " DSL data led flash frequency: $DSL_DATA_LED_FLASH_FREQUENCY Hz" -+echo " Disable debug prints: $DSL_DEBUG_DISABLE" -+echo " Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET" -+echo " Preselected max. debug level: $DSL_DBG_MAX_LEVEL_PRE" -+echo " Include deprecated functions: $INCLUDE_DEPRECATED" -+echo " Include Device Exception Codes: $INCLUDE_DEVICE_EXCEPTION_CODES" -+echo " Include FW request support: $INCLUDE_FW_REQUEST_SUPPORT" -+echo " Include ADSL trace buffer: $INCLUDE_DSL_CPE_TRACE_BUFFER" -+echo " Include ADSL MIB: $INCLUDE_DSL_ADSL_MIB" -+echo " Include ADSL LED: $INCLUDE_ADSL_LED" -+echo " Include CEOC: $INCLUDE_DSL_CEOC" -+echo " Include config get support: $INCLUDE_DSL_CONFIG_GET" -+echo " Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE" -+echo " Include Resource Statistics: $INCLUDE_DSL_RESOURCE_STATISTICS" -+echo " Include Framing Parameters: $INCLUDE_DSL_FRAMING_PARAMETERS" -+echo " Include G997 Line Inventory: $INCLUDE_DSL_G997_LINE_INVENTORY" -+echo " Include G997 Framing Parameters: $INCLUDE_DSL_G997_FRAMING_PARAMETERS" -+echo " Include G997 per tone data: $INCLUDE_DSL_G997_PER_TONE" -+echo " Include G997 status: $INCLUDE_DSL_G997_STATUS" -+echo " Include G997 alarm: $INCLUDE_DSL_G997_ALARM" -+echo " Include DSL Bonding: $INCLUDE_DSL_BONDING" -+echo " Include Misc Line Status $INCLUDE_DSL_CPE_MISC_LINE_STATUS" -+echo " Include DELT: $INCLUDE_DSL_DELT" -+echo " Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA" -+echo " Include PM: $INCLUDE_DSL_PM" -+echo " Include PM config: $INCLUDE_DSL_CPE_PM_CONFIG" -+echo " Include PM total: $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS" -+echo " Include PM history: $INCLUDE_DSL_CPE_PM_HISTORY" -+echo " Include PM showtime: $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS" -+echo " Include PM optional: $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS" -+echo " Include PM line: $INCLUDE_DSL_CPE_PM_LINE_COUNTERS" -+echo " Include PM line event showtime: $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS" -+echo " Include PM channel: $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS" -+echo " Include PM channel extended: $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS" -+echo " Include PM data path: $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS" -+echo " Include PM data path failure: $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS" -+echo " Include PM ReTx: $INCLUDE_DSL_CPE_PM_RETX_COUNTERS" -+echo " Include PM line threshold: $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS" -+echo " Include PM channel threshold: $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS" -+echo " Include PM data path threshold: $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS" -+echo " Include PM ReTx threshold: $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS" -+echo " Include FW memory free support: $INCLUDE_DSL_FIRMWARE_MEMORY_FREE" -+echo "----------------------- deprectated ! ----------------------------------" -+echo " Include PM line failure: $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS" -+echo "" -+echo " Settings:" -+echo " Configure options: $CONFIGURE_OPTIONS" -+echo "------------------------------------------------------------------------" - ]) - - AC_CONFIG_FILES([Makefile src/Makefile]) ---- a/src/Makefile.am -+++ b/src/Makefile.am -@@ -303,7 +303,7 @@ if KERNEL_2_6 - drv_dsl_cpe_api_OBJS = "$(subst .c,.o,$(filter %.c,$(drv_dsl_cpe_api_SOURCES)))" - - drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SOURCES) -- @echo -e "drv_dsl_cpe_api: Making Linux 2.6.x kernel object" -+ @echo "drv_dsl_cpe_api: Making Linux 2.6.x kernel object" - if test ! -e common/drv_dsl_cpe_api.c ; then \ - echo "copy source files (as links only!)"; \ - for f in $(filter %.c,$(drv_dsl_cpe_api_SOURCES)); do \ -@@ -311,10 +311,10 @@ drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SO - cp -s $(addprefix @abs_srcdir@/,$$f) $(PWD)/`dirname $$f`/ ; \ - done \ - fi -- @echo -e "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild -- @echo -e "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild -- @echo -e "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)" >> $(PWD)/Kbuild -- @echo -e "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild -+ @echo "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild -+ @echo "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild -+ @echo "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)" >> $(PWD)/Kbuild -+ @echo "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild - $(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules - - clean-generic: diff --git a/package/ifxmips-dsl-api/src/Makefile b/package/ifxmips-dsl-api/src/Makefile deleted file mode 100644 index c8211d3712..0000000000 --- a/package/ifxmips-dsl-api/src/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -obj-m = ifxmips_mei.o ifxmips_atm.o - -ifxmips_atm-objs := ifxmips_atm_core.o ifxmips_atm_danube.o diff --git a/package/ifxmips-dsl-api/src/ifx_atm.h b/package/ifxmips-dsl-api/src/ifx_atm.h deleted file mode 100644 index ed90b5d4d7..0000000000 --- a/package/ifxmips-dsl-api/src/ifx_atm.h +++ /dev/null @@ -1,172 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifx_atm.h -** PROJECT : UEIP -** MODULES : ATM -** -** DATE : 17 Jun 2009 -** AUTHOR : Xu Liang -** DESCRIPTION : Global ATM driver header file -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Date $Author $Comment -** 07 JUL 2009 Xu Liang Init Version -*******************************************************************************/ - -#ifndef IFX_ATM_H -#define IFX_ATM_H - - - -/*! - \defgroup IFX_ATM UEIP Project - ATM driver module - \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. - */ - -/*! - \defgroup IFX_ATM_IOCTL IOCTL Commands - \ingroup IFX_ATM - \brief IOCTL Commands used by user application. - */ - -/*! - \defgroup IFX_ATM_STRUCT Structures - \ingroup IFX_ATM - \brief Structures used by user application. - */ - -/*! - \file ifx_atm.h - \ingroup IFX_ATM - \brief ATM driver header file - */ - - - -/* - * #################################### - * Definition - * #################################### - */ - -/*! - \addtogroup IFX_ATM_STRUCT - */ -/*@{*/ - -/* - * ATM MIB - */ - -typedef struct { - __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ - __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ - __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ - __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ - __u32 ifInErrors; /*!< counter of error ingress cells */ - __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ - __u32 ifOutErrors; /*!< counter of error egress cells */ -} atm_cell_ifEntry_t; - -typedef struct { - __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ - __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ - __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ - __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ - __u32 ifInUcastPkts; /*!< counter of ingress packets */ - __u32 ifOutUcastPkts; /*!< counter of egress packets */ - __u32 ifInErrors; /*!< counter of error ingress packets */ - __u32 ifInDiscards; /*!< counter of dropped ingress packets */ - __u32 ifOutErros; /*!< counter of error egress packets */ - __u32 ifOutDiscards; /*!< counter of dropped egress packets */ -} atm_aal5_ifEntry_t; - -typedef struct { - __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ - __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet - __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ -} atm_aal5_vcc_t; - -typedef struct { - int vpi; /*!< VPI of the VCC to get MIB counters */ - int vci; /*!< VCI of the VCC to get MIB counters */ - atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ -} atm_aal5_vcc_x_t; - -/*@}*/ - - - -/* - * #################################### - * IOCTL - * #################################### - */ - -/*! - \addtogroup IFX_ATM_IOCTL - */ -/*@{*/ - -/* - * ioctl Command - */ -/*! - \brief ATM IOCTL Magic Number - */ -#define PPE_ATM_IOC_MAGIC 'o' -/*! - \brief ATM IOCTL Command - Get Cell Level MIB Counters - - This command is obsolete. User can get cell level MIB from DSL API. - This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. - */ -#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) -/*! - \brief ATM IOCTL Command - Get AAL5 Level MIB Counters - - Get AAL5 packet counters. - This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. - */ -#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) -/*! - \brief ATM IOCTL Command - Get Per PVC MIB Counters - - Get AAL5 packet counters for each PVC. - This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. - */ -#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) -/*! - \brief Total Number of ATM IOCTL Commands - */ -#define PPE_ATM_IOC_MAXNR 3 - -/*@}*/ - - - -/* - * #################################### - * API - * #################################### - */ - -#ifdef __KERNEL__ -struct port_cell_info { - unsigned int port_num; - unsigned int tx_link_rate[2]; -}; -#endif - - - -#endif // IFX_ATM_H - diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm.h b/package/ifxmips-dsl-api/src/ifxmips_atm.h deleted file mode 100644 index ed90b5d4d7..0000000000 --- a/package/ifxmips-dsl-api/src/ifxmips_atm.h +++ /dev/null @@ -1,172 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifx_atm.h -** PROJECT : UEIP -** MODULES : ATM -** -** DATE : 17 Jun 2009 -** AUTHOR : Xu Liang -** DESCRIPTION : Global ATM driver header file -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Date $Author $Comment -** 07 JUL 2009 Xu Liang Init Version -*******************************************************************************/ - -#ifndef IFX_ATM_H -#define IFX_ATM_H - - - -/*! - \defgroup IFX_ATM UEIP Project - ATM driver module - \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. - */ - -/*! - \defgroup IFX_ATM_IOCTL IOCTL Commands - \ingroup IFX_ATM - \brief IOCTL Commands used by user application. - */ - -/*! - \defgroup IFX_ATM_STRUCT Structures - \ingroup IFX_ATM - \brief Structures used by user application. - */ - -/*! - \file ifx_atm.h - \ingroup IFX_ATM - \brief ATM driver header file - */ - - - -/* - * #################################### - * Definition - * #################################### - */ - -/*! - \addtogroup IFX_ATM_STRUCT - */ -/*@{*/ - -/* - * ATM MIB - */ - -typedef struct { - __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ - __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ - __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ - __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ - __u32 ifInErrors; /*!< counter of error ingress cells */ - __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ - __u32 ifOutErrors; /*!< counter of error egress cells */ -} atm_cell_ifEntry_t; - -typedef struct { - __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ - __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ - __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ - __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ - __u32 ifInUcastPkts; /*!< counter of ingress packets */ - __u32 ifOutUcastPkts; /*!< counter of egress packets */ - __u32 ifInErrors; /*!< counter of error ingress packets */ - __u32 ifInDiscards; /*!< counter of dropped ingress packets */ - __u32 ifOutErros; /*!< counter of error egress packets */ - __u32 ifOutDiscards; /*!< counter of dropped egress packets */ -} atm_aal5_ifEntry_t; - -typedef struct { - __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ - __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet - __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ -} atm_aal5_vcc_t; - -typedef struct { - int vpi; /*!< VPI of the VCC to get MIB counters */ - int vci; /*!< VCI of the VCC to get MIB counters */ - atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ -} atm_aal5_vcc_x_t; - -/*@}*/ - - - -/* - * #################################### - * IOCTL - * #################################### - */ - -/*! - \addtogroup IFX_ATM_IOCTL - */ -/*@{*/ - -/* - * ioctl Command - */ -/*! - \brief ATM IOCTL Magic Number - */ -#define PPE_ATM_IOC_MAGIC 'o' -/*! - \brief ATM IOCTL Command - Get Cell Level MIB Counters - - This command is obsolete. User can get cell level MIB from DSL API. - This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. - */ -#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) -/*! - \brief ATM IOCTL Command - Get AAL5 Level MIB Counters - - Get AAL5 packet counters. - This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. - */ -#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) -/*! - \brief ATM IOCTL Command - Get Per PVC MIB Counters - - Get AAL5 packet counters for each PVC. - This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. - */ -#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) -/*! - \brief Total Number of ATM IOCTL Commands - */ -#define PPE_ATM_IOC_MAXNR 3 - -/*@}*/ - - - -/* - * #################################### - * API - * #################################### - */ - -#ifdef __KERNEL__ -struct port_cell_info { - unsigned int port_num; - unsigned int tx_link_rate[2]; -}; -#endif - - - -#endif // IFX_ATM_H - diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_core.c b/package/ifxmips-dsl-api/src/ifxmips_atm_core.c deleted file mode 100644 index 5d1af1f7b5..0000000000 --- a/package/ifxmips-dsl-api/src/ifxmips_atm_core.c +++ /dev/null @@ -1,2507 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_atm_core.c -** PROJECT : UEIP -** MODULES : ATM -** -** DATE : 7 Jul 2009 -** AUTHOR : Xu Liang -** DESCRIPTION : ATM driver common source file (core functions) -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Date $Author $Comment -** 07 JUL 2009 Xu Liang Init Version -*******************************************************************************/ - - - -/* - * #################################### - * Version No. - * #################################### - */ - -#define IFX_ATM_VER_MAJOR 1 -#define IFX_ATM_VER_MID 0 -#define IFX_ATM_VER_MINOR 8 - - - -/* - * #################################### - * Head File - * #################################### - */ - -/* - * Common Head File - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Chip Specific Head File - */ -#include -#include -#include -#include "ifxmips_atm_core.h" - - - -/* - * #################################### - * Kernel Version Adaption - * #################################### - */ -#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11) - #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0) - #define MODULE_PARM(a, b) module_param(a, int, 0) -#else - #define MODULE_PARM_ARRAY(a, b) MODULE_PARM(a, b) -#endif - - - -/*! - \addtogroup IFXMIPS_ATM_MODULE_PARAMS - */ -/*@{*/ -/* - * #################################### - * Parameters to Configure PPE - * #################################### - */ -/*! - \brief QSB cell delay variation due to concurrency - */ -static int qsb_tau = 1; /* QSB cell delay variation due to concurrency */ -/*! - \brief QSB scheduler burst length - */ -static int qsb_srvm = 0x0F; /* QSB scheduler burst length */ -/*! - \brief QSB time step, all legal values are 1, 2, 4 - */ -static int qsb_tstep = 4 ; /* QSB time step, all legal values are 1, 2, 4 */ - -/*! - \brief Write descriptor delay - */ -static int write_descriptor_delay = 0x20; /* Write descriptor delay */ - -/*! - \brief AAL5 padding byte ('~') - */ -static int aal5_fill_pattern = 0x007E; /* AAL5 padding byte ('~') */ -/*! - \brief Max frame size for RX - */ -static int aal5r_max_packet_size = 0x0700; /* Max frame size for RX */ -/*! - \brief Min frame size for RX - */ -static int aal5r_min_packet_size = 0x0000; /* Min frame size for RX */ -/*! - \brief Max frame size for TX - */ -static int aal5s_max_packet_size = 0x0700; /* Max frame size for TX */ -/*! - \brief Min frame size for TX - */ -static int aal5s_min_packet_size = 0x0000; /* Min frame size for TX */ -/*! - \brief Drop error packet in RX path - */ -static int aal5r_drop_error_packet = 1; /* Drop error packet in RX path */ - -/*! - \brief Number of descriptors per DMA RX channel - */ -static int dma_rx_descriptor_length = 128; /* Number of descriptors per DMA RX channel */ -/*! - \brief Number of descriptors per DMA TX channel - */ -static int dma_tx_descriptor_length = 64; /* Number of descriptors per DMA TX channel */ -/*! - \brief PPE core clock cycles between descriptor write and effectiveness in external RAM - */ -static int dma_rx_clp1_descriptor_threshold = 38; -/*@}*/ - -MODULE_PARM(qsb_tau, "i"); -MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0"); -MODULE_PARM(qsb_srvm, "i"); -MODULE_PARM_DESC(qsb_srvm, "Maximum burst size"); -MODULE_PARM(qsb_tstep, "i"); -MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4"); - -MODULE_PARM(write_descriptor_delay, "i"); -MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM"); - -MODULE_PARM(aal5_fill_pattern, "i"); -MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames"); -MODULE_PARM(aal5r_max_packet_size, "i"); -MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames"); -MODULE_PARM(aal5r_min_packet_size, "i"); -MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames"); -MODULE_PARM(aal5s_max_packet_size, "i"); -MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames"); -MODULE_PARM(aal5s_min_packet_size, "i"); -MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames"); -MODULE_PARM(aal5r_drop_error_packet, "i"); -MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream"); - -MODULE_PARM(dma_rx_descriptor_length, "i"); -MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)"); -MODULE_PARM(dma_tx_descriptor_length, "i"); -MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)"); -MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i"); -MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1"); - - - -/* - * #################################### - * Definition - * #################################### - */ - -#define DUMP_SKB_LEN ~0 - - - -/* - * #################################### - * Declaration - * #################################### - */ - -/* - * Network Operations - */ -static int ppe_ioctl(struct atm_dev *, unsigned int, void *); -static int ppe_open(struct atm_vcc *); -static void ppe_close(struct atm_vcc *); -static int ppe_send(struct atm_vcc *, struct sk_buff *); -static int ppe_send_oam(struct atm_vcc *, void *, int); -static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int); - -/* - * ADSL LED - */ -static INLINE int adsl_led_flash(void); - -/* - * 64-bit operation used by MIB calculation - */ -static INLINE void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *); - -/* - * buffer manage functions - */ -static INLINE struct sk_buff* alloc_skb_rx(void); -static INLINE struct sk_buff* alloc_skb_tx(unsigned int); -struct sk_buff* atm_alloc_tx(struct atm_vcc *, unsigned int); -static INLINE void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *); -static INLINE struct sk_buff *get_skb_rx_pointer(unsigned int); -static INLINE int get_tx_desc(unsigned int); - -/* - * mailbox handler and signal function - */ -static INLINE void mailbox_oam_rx_handler(void); -static INLINE void mailbox_aal_rx_handler(void); -#if defined(ENABLE_TASKLET) && ENABLE_TASKLET - static void do_ppe_tasklet(unsigned long); -#endif -static irqreturn_t mailbox_irq_handler(int, void *); -static INLINE void mailbox_signal(unsigned int, int); - -/* - * QSB & HTU setting functions - */ -static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int); -static void qsb_global_set(void); -static INLINE void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int); -static INLINE void clear_htu_entry(unsigned int); -static void validate_oam_htu_entry(void); -static void invalidate_oam_htu_entry(void); - -/* - * look up for connection ID - */ -static INLINE int find_vpi(unsigned int); -static INLINE int find_vpivci(unsigned int, unsigned int); -static INLINE int find_vcc(struct atm_vcc *); - -/* - * Debug Functions - */ -#if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB - static void dump_skb(struct sk_buff *, u32, char *, int, int, int); -#else - #define dump_skb(skb, len, title, port, ch, is_tx) do {} while (0) -#endif - -/* - * Proc File Functions - */ -static INLINE void proc_file_create(void); -static INLINE void proc_file_delete(void); -static int proc_read_version(char *, char **, off_t, int, int *, void *); -static int proc_read_mib(char *, char **, off_t, int, int *, void *); -static int proc_write_mib(struct file *, const char *, unsigned long, void *); -#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC - static int proc_read_dbg(char *, char **, off_t, int, int *, void *); - static int proc_write_dbg(struct file *, const char *, unsigned long, void *); -#endif -#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC - static int proc_read_htu(char *, char **, off_t, int, int *, void *); - static int proc_read_txq(char *, char **, off_t, int, int *, void *); -#endif - -/* - * Proc Help Functions - */ -static int stricmp(const char *, const char *); -#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC - static int strincmp(const char *, const char *, int); -#endif -static INLINE int ifx_atm_version(char *); -//static INLINE int print_reset_domain(char *, int); -//static INLINE int print_reset_handler(char *, int, ifx_rcu_handler_t *); - -/* - * Init & clean-up functions - */ -#ifdef MODULE - static INLINE void reset_ppe(void); -#endif -static INLINE void check_parameters(void); -static INLINE int init_priv_data(void); -static INLINE void clear_priv_data(void); -static INLINE void init_rx_tables(void); -static INLINE void init_tx_tables(void); - -/* - * Exteranl Function - */ -#if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE) - extern void ifx_push_oam(unsigned char *); -#else - static inline void ifx_push_oam(unsigned char *dummy) {} -#endif -#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE) - extern int ifx_mei_atm_led_blink(void); - extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr); -#else - static inline int ifx_mei_atm_led_blink(void) { return IFX_SUCCESS; } - static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr) - { - if ( is_showtime != NULL ) - *is_showtime = 0; - return IFX_SUCCESS; - } -#endif - -/* - * External variable - */ -extern struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int); -#if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE) - extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *); - extern int (*ifx_mei_atm_showtime_exit)(void); -#else - int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL; - EXPORT_SYMBOL(ifx_mei_atm_showtime_enter); - int (*ifx_mei_atm_showtime_exit)(void) = NULL; - EXPORT_SYMBOL(ifx_mei_atm_showtime_exit); -#endif - - - -/* - * #################################### - * Local Variable - * #################################### - */ - -static struct atm_priv_data g_atm_priv_data; - -static struct atmdev_ops g_ifx_atm_ops = { - .open = ppe_open, - .close = ppe_close, - .ioctl = ppe_ioctl, - .send = ppe_send, - .send_oam = ppe_send_oam, - .change_qos = ppe_change_qos, - .owner = THIS_MODULE, -}; - -#if defined(ENABLE_TASKLET) && ENABLE_TASKLET - DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0); -#endif - -static int g_showtime = 0; -static void *g_xdata_addr = NULL; - -unsigned int ifx_atm_dbg_enable = 0; - -static struct proc_dir_entry* g_atm_dir = NULL; - - - -/* - * #################################### - * Local Function - * #################################### - */ - -static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg) -{ - int ret = 0; - atm_cell_ifEntry_t mib_cell; - atm_aal5_ifEntry_t mib_aal5; - atm_aal5_vcc_x_t mib_vcc; - unsigned int value; - int conn; - - if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC - || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR ) - return -ENOTTY; - - if ( _IOC_DIR(cmd) & _IOC_READ ) - ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd)); - else if ( _IOC_DIR(cmd) & _IOC_WRITE ) - ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd)); - if ( ret ) - return -EFAULT; - - switch ( cmd ) - { - case PPE_ATM_MIB_CELL: /* cell level MIB */ - /* These MIB should be read at ARC side, now put zero only. */ - mib_cell.ifHCInOctets_h = 0; - mib_cell.ifHCInOctets_l = 0; - mib_cell.ifHCOutOctets_h = 0; - mib_cell.ifHCOutOctets_l = 0; - mib_cell.ifInErrors = 0; - mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell; - mib_cell.ifOutErrors = 0; - - ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell)); - break; - - case PPE_ATM_MIB_AAL5: /* AAL5 MIB */ - value = WAN_MIB_TABLE->wrx_total_byte; - u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte); - g_atm_priv_data.prev_wrx_total_byte = value; - mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h; - mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l; - - value = WAN_MIB_TABLE->wtx_total_byte; - u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte); - g_atm_priv_data.prev_wtx_total_byte = value; - mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h; - mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l; - - mib_aal5.ifInUcastPkts = g_atm_priv_data.wrx_pdu; - mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu; - mib_aal5.ifInErrors = WAN_MIB_TABLE->wrx_err_pdu; - mib_aal5.ifInDiscards = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu; - mib_aal5.ifOutErros = g_atm_priv_data.wtx_err_pdu; - mib_aal5.ifOutDiscards = g_atm_priv_data.wtx_drop_pdu; - - ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5)); - break; - - case PPE_ATM_MIB_VCC: /* VCC related MIB */ - copy_from_user(&mib_vcc, arg, sizeof(mib_vcc)); - conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci); - if ( conn >= 0 ) - { - mib_vcc.mib_vcc.aal5VccCrcErrors = g_atm_priv_data.conn[conn].aal5_vcc_crc_err; - mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu; - mib_vcc.mib_vcc.aal5VccSarTimeOuts = 0; /* no timer support */ - ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc)); - } - else - ret = -EINVAL; - break; - - default: - ret = -ENOIOCTLCMD; - } - - return ret; -} - -static int ppe_open(struct atm_vcc *vcc) -{ - int ret; - short vpi = vcc->vpi; - int vci = vcc->vci; - struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data]; - int conn; - int f_enable_irq = 0; -#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX - int sys_flag; -#endif - - if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 ) - return -EPROTONOSUPPORT; - - /* check bandwidth */ - if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) - || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) - || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) - || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) ) - { - ret = -EINVAL; - goto PPE_OPEN_EXIT; - } - - /* check existing vpi,vci */ - conn = find_vpivci(vpi, vci); - if ( conn >= 0 ) { - ret = -EADDRINUSE; - goto PPE_OPEN_EXIT; - } - - /* check whether it need to enable irq */ - if ( g_atm_priv_data.conn_table == 0 ) - f_enable_irq = 1; - - /* allocate connection */ - for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) { - if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) { - g_atm_priv_data.conn[conn].vcc = vcc; - break; - } - } - if ( conn == MAX_PVC_NUMBER ) - { - ret = -EINVAL; - goto PPE_OPEN_EXIT; - } - - /* reserve bandwidth */ - switch ( vcc->qos.txtp.traffic_class ) { - case ATM_CBR: - case ATM_VBR_RT: - port->tx_current_cell_rate += vcc->qos.txtp.max_pcr; - break; - case ATM_VBR_NRT: - port->tx_current_cell_rate += vcc->qos.txtp.scr; - break; - case ATM_UBR_PLUS: - port->tx_current_cell_rate += vcc->qos.txtp.min_pcr; - break; - } - - /* set qsb */ - set_qsb(vcc, &vcc->qos, conn); - - /* update atm_vcc structure */ - vcc->itf = (int)vcc->dev->dev_data; - vcc->vpi = vpi; - vcc->vci = vci; - set_bit(ATM_VF_READY, &vcc->flags); - - /* enable irq */ - if (f_enable_irq ) { - ifx_atm_alloc_tx = atm_alloc_tx; - - *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM); - *MBOX_IGU1_IER = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM); - - enable_irq(PPE_MAILBOX_IGU1_INT); - } - - /* set port */ - WTX_QUEUE_CONFIG(conn)->sbid = (int)vcc->dev->dev_data; - - /* set htu entry */ - set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0); - -#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX - // ReTX: occupy second QID - local_irq_save(sys_flag); - if ( g_retx_htu && vcc->qos.aal == ATM_AAL5 ) - { - int retx_conn = (conn + 8) % 16; // ReTX queue - - if ( retx_conn < MAX_PVC_NUMBER && test_and_set_bit(retx_conn, &g_atm_priv_data.conn_table) == 0 ) { - g_atm_priv_data.conn[retx_conn].vcc = vcc; - set_htu_entry(vpi, vci, retx_conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 1); - } - } - local_irq_restore(sys_flag); -#endif - - ret = 0; - -PPE_OPEN_EXIT: - return ret; -} - -static void ppe_close(struct atm_vcc *vcc) -{ - int conn; - struct port *port; - struct connection *connection; - - if ( vcc == NULL ) - return; - - /* get connection id */ - conn = find_vcc(vcc); - if ( conn < 0 ) { - err("can't find vcc"); - goto PPE_CLOSE_EXIT; - } - connection = &g_atm_priv_data.conn[conn]; - port = &g_atm_priv_data.port[connection->port]; - - /* clear htu */ - clear_htu_entry(conn); - - /* release connection */ - clear_bit(conn, &g_atm_priv_data.conn_table); - connection->vcc = NULL; - connection->aal5_vcc_crc_err = 0; - connection->aal5_vcc_oversize_sdu = 0; - - /* disable irq */ - if ( g_atm_priv_data.conn_table == 0 ) { - disable_irq(PPE_MAILBOX_IGU1_INT); - ifx_atm_alloc_tx = NULL; - } - - /* release bandwidth */ - switch ( vcc->qos.txtp.traffic_class ) - { - case ATM_CBR: - case ATM_VBR_RT: - port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr; - break; - case ATM_VBR_NRT: - port->tx_current_cell_rate -= vcc->qos.txtp.scr; - break; - case ATM_UBR_PLUS: - port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr; - break; - } - -PPE_CLOSE_EXIT: - return; -} - -static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb) -{ - int ret; - int conn; - int desc_base; - struct tx_descriptor reg_desc = {0}; - - if ( vcc == NULL || skb == NULL ) - return -EINVAL; - - skb_get(skb); - atm_free_tx_skb_vcc(skb, vcc); - - conn = find_vcc(vcc); - if ( conn < 0 ) { - ret = -EINVAL; - goto FIND_VCC_FAIL; - } - - if ( !g_showtime ) { - err("not in showtime"); - ret = -EIO; - goto PPE_SEND_FAIL; - } - - if ( vcc->qos.aal == ATM_AAL5 ) { - int byteoff; - int datalen; - struct tx_inband_header *header; - - datalen = skb->len; - byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1); - - if ( skb_headroom(skb) < byteoff + TX_INBAND_HEADER_LENGTH ) { - struct sk_buff *new_skb; - - new_skb = alloc_skb_tx(datalen); - if ( new_skb == NULL ) { - err("ALLOC_SKB_TX_FAIL"); - ret = -ENOMEM; - goto PPE_SEND_FAIL; - } - skb_put(new_skb, datalen); - memcpy(new_skb->data, skb->data, datalen); - dev_kfree_skb_any(skb); - skb = new_skb; - byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1); - } - - skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH); - - header = (struct tx_inband_header *)skb->data; - - /* setup inband trailer */ - header->uu = 0; - header->cpi = 0; - header->pad = aal5_fill_pattern; - header->res1 = 0; - - /* setup cell header */ - header->clp = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0; - header->pti = ATM_PTI_US0; - header->vci = vcc->vci; - header->vpi = vcc->vpi; - header->gfc = 0; - - /* setup descriptor */ - reg_desc.dataptr = (unsigned int)skb->data >> 2; - reg_desc.datalen = datalen; - reg_desc.byteoff = byteoff; - reg_desc.iscell = 0; - } - else { - /* if data pointer is not aligned, allocate new sk_buff */ - if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 ) { - struct sk_buff *new_skb; - - err("skb->data not aligned"); - - new_skb = alloc_skb_tx(skb->len); - if ( new_skb == NULL ) { - err("ALLOC_SKB_TX_FAIL"); - ret = -ENOMEM; - goto PPE_SEND_FAIL; - } - skb_put(new_skb, skb->len); - memcpy(new_skb->data, skb->data, skb->len); - dev_kfree_skb_any(skb); - skb = new_skb; - } - - reg_desc.dataptr = (unsigned int)skb->data >> 2; - reg_desc.datalen = skb->len; - reg_desc.byteoff = 0; - reg_desc.iscell = 1; - } - - reg_desc.own = 1; - reg_desc.c = 1; - reg_desc.sop = reg_desc.eop = 1; - - desc_base = get_tx_desc(conn); - if ( desc_base < 0 ) { - err("ALLOC_TX_CONNECTION_FAIL"); - ret = -EIO; - goto PPE_SEND_FAIL; - } - - if ( vcc->stats ) - atomic_inc(&vcc->stats->tx); - if ( vcc->qos.aal == ATM_AAL5 ) - g_atm_priv_data.wtx_pdu++; - - /* update descriptor send pointer */ - if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL ) - dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]); - g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb; - - /* write discriptor to memory and write back cache */ - g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc; - dma_cache_wback((unsigned long)skb->data, skb->len); - - dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, 0, conn, 1); - - mailbox_signal(conn, 1); - - adsl_led_flash(); - - return 0; - -FIND_VCC_FAIL: - err("FIND_VCC_FAIL"); - g_atm_priv_data.wtx_err_pdu++; - dev_kfree_skb_any(skb); - return ret; - -PPE_SEND_FAIL: - if ( vcc->qos.aal == ATM_AAL5 ) - g_atm_priv_data.wtx_drop_pdu++; - if ( vcc->stats ) - atomic_inc(&vcc->stats->tx_err); - dev_kfree_skb_any(skb); - return ret; -} - -static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags) -{ - int conn; - struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell; - int desc_base; - struct sk_buff *skb; - struct tx_descriptor reg_desc = {0}; - - if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5) - && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0) - || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04) - && find_vpi(uni_cell_header->vpi) < 0) ) - return -EINVAL; - - if ( !g_showtime ) { - err("not in showtime"); - return -EIO; - } - - conn = find_vcc(vcc); - if ( conn < 0 ) { - err("FIND_VCC_FAIL"); - return -EINVAL; - } - - skb = alloc_skb_tx(CELL_SIZE); - if ( skb == NULL ) { - err("ALLOC_SKB_TX_FAIL"); - return -ENOMEM; - } - memcpy(skb->data, cell, CELL_SIZE); - - reg_desc.dataptr = (unsigned int)skb->data >> 2; - reg_desc.datalen = CELL_SIZE; - reg_desc.byteoff = 0; - reg_desc.iscell = 1; - - reg_desc.own = 1; - reg_desc.c = 1; - reg_desc.sop = reg_desc.eop = 1; - - desc_base = get_tx_desc(conn); - if ( desc_base < 0 ) { - dev_kfree_skb_any(skb); - err("ALLOC_TX_CONNECTION_FAIL"); - return -EIO; - } - - if ( vcc->stats ) - atomic_inc(&vcc->stats->tx); - - /* update descriptor send pointer */ - if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL ) - dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]); - g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb; - - /* write discriptor to memory and write back cache */ - g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc; - dma_cache_wback((unsigned long)skb->data, CELL_SIZE); - - dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, 0, conn, 1); - - mailbox_signal(conn, 1); - - adsl_led_flash(); - - return 0; -} - -static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) -{ - int conn; - - if ( vcc == NULL || qos == NULL ) - return -EINVAL; - - conn = find_vcc(vcc); - if ( conn < 0 ) - return -EINVAL; - - set_qsb(vcc, qos, conn); - - return 0; -} - -static INLINE int adsl_led_flash(void) -{ - return ifx_mei_atm_led_blink(); -} - -/* - * Description: - * Add a 32-bit value to 64-bit value, and put result in a 64-bit variable. - * Input: - * opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value - * opt2 --- unsigned int, second operand, a 32-bit unsigned integer value - * ret --- ppe_u64_t, pointer to a variable to hold result - * Output: - * none - */ -static INLINE void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret) -{ - ret->l = opt1.l + opt2; - if ( ret->l < opt1.l || ret->l < opt2 ) - ret->h++; -} - -static INLINE struct sk_buff* alloc_skb_rx(void) -{ - struct sk_buff *skb; - - skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT); - if ( skb != NULL ) { - /* must be burst length alignment */ - if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 ) - skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)); - /* pub skb in reserved area "skb->data - 4" */ - *((struct sk_buff **)skb->data - 1) = skb; - /* write back and invalidate cache */ - dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb)); - /* invalidate cache */ - dma_cache_inv((unsigned long)skb->data, (unsigned int)skb->end - (unsigned int)skb->data); - } - - return skb; -} - -static INLINE struct sk_buff* alloc_skb_tx(unsigned int size) -{ - struct sk_buff *skb; - - /* allocate memory including header and padding */ - size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES; - size &= ~(DATA_BUFFER_ALIGNMENT - 1); - skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT); - /* must be burst length alignment */ - if ( skb != NULL ) - skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH); - return skb; -} - -struct sk_buff* atm_alloc_tx(struct atm_vcc *vcc, unsigned int size) -{ - int conn; - struct sk_buff *skb; - - /* oversize packet */ - if ( size > aal5s_max_packet_size ) { - err("atm_alloc_tx: oversize packet"); - return NULL; - } - /* send buffer overflow */ - if ( atomic_read(&sk_atm(vcc)->sk_wmem_alloc) && !atm_may_send(vcc, size) ) { - err("atm_alloc_tx: send buffer overflow"); - return NULL; - } - conn = find_vcc(vcc); - if ( conn < 0 ) { - err("atm_alloc_tx: unknown VCC"); - return NULL; - } - - skb = dev_alloc_skb(size); - if ( skb == NULL ) { - err("atm_alloc_tx: sk buffer is used up"); - return NULL; - } - - atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); - - return skb; -} - -static INLINE void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc) -{ - if ( vcc->pop != NULL ) - vcc->pop(vcc, skb); - else - dev_kfree_skb_any(skb); -} - -static INLINE struct sk_buff *get_skb_rx_pointer(unsigned int dataptr) -{ - unsigned int skb_dataptr; - struct sk_buff *skb; - - skb_dataptr = ((dataptr - 1) << 2) | KSEG1; - skb = *(struct sk_buff **)skb_dataptr; - - ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr); - ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr); - - return skb; -} - -static INLINE int get_tx_desc(unsigned int conn) -{ - int desc_base = -1; - struct connection *p_conn = &g_atm_priv_data.conn[conn]; - - if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) { - desc_base = p_conn->tx_desc_pos; - if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length ) - p_conn->tx_desc_pos = 0; - } - - return desc_base; -} - -static INLINE void mailbox_oam_rx_handler(void) -{ - unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes; - struct rx_descriptor reg_desc; - struct uni_cell_header *header; - int conn; - struct atm_vcc *vcc; - unsigned int i; - - for ( i = 0; i < vlddes; i++ ) { - do { - reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos]; - } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready - - header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE]; - - if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 ) - conn = find_vpivci(header->vpi, header->vci); - else if ( header->vci == 0x03 || header->vci == 0x04 ) - conn = find_vpi(header->vpi); - else - conn = -1; - - if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) { - vcc = g_atm_priv_data.conn[conn].vcc; - - if ( vcc->push_oam != NULL ) - vcc->push_oam(vcc, header); - else - ifx_push_oam((unsigned char *)header); - - adsl_led_flash(); - } - - reg_desc.byteoff = 0; - reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE; - reg_desc.own = 1; - reg_desc.c = 0; - - g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc; - if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN ) - g_atm_priv_data.oam_desc_pos = 0; - - mailbox_signal(RX_DMA_CH_OAM, 0); - } -} - -static INLINE void mailbox_aal_rx_handler(void) -{ - unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes; - struct rx_descriptor reg_desc; - int conn; - struct atm_vcc *vcc; - struct sk_buff *skb, *new_skb; - struct rx_inband_trailer *trailer; - unsigned int i; - - for ( i = 0; i < vlddes; i++ ) { - do { - reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos]; - } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready - - conn = reg_desc.id; - - if ( g_atm_priv_data.conn[conn].vcc != NULL ) { - vcc = g_atm_priv_data.conn[conn].vcc; - - skb = get_skb_rx_pointer(reg_desc.dataptr); - - if ( reg_desc.err ) { - if ( vcc->qos.aal == ATM_AAL5 ) { - trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES)); - if ( trailer->stw_crc ) - g_atm_priv_data.conn[conn].aal5_vcc_crc_err++; - if ( trailer->stw_ovz ) - g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++; - g_atm_priv_data.wrx_drop_pdu++; - } - if ( vcc->stats ) { - atomic_inc(&vcc->stats->rx_drop); - atomic_inc(&vcc->stats->rx_err); - } - } - else if ( atm_charge(vcc, skb->truesize) ) { - new_skb = alloc_skb_rx(); - if ( new_skb != NULL ) { - skb_reserve(skb, reg_desc.byteoff); - skb_put(skb, reg_desc.datalen); - ATM_SKB(skb)->vcc = vcc; - - dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, 0, conn, 0); - - vcc->push(vcc, skb); - - if ( vcc->qos.aal == ATM_AAL5 ) - g_atm_priv_data.wrx_pdu++; - if ( vcc->stats ) - atomic_inc(&vcc->stats->rx); - adsl_led_flash(); - - reg_desc.dataptr = (unsigned int)new_skb->data >> 2; - } - else { - atm_return(vcc, skb->truesize); - if ( vcc->qos.aal == ATM_AAL5 ) - g_atm_priv_data.wrx_drop_pdu++; - if ( vcc->stats ) - atomic_inc(&vcc->stats->rx_drop); - } - } - else { - if ( vcc->qos.aal == ATM_AAL5 ) - g_atm_priv_data.wrx_drop_pdu++; - if ( vcc->stats ) - atomic_inc(&vcc->stats->rx_drop); - } - } - else { - g_atm_priv_data.wrx_drop_pdu++; - } - - reg_desc.byteoff = 0; - reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE; - reg_desc.own = 1; - reg_desc.c = 0; - - g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc; - if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length ) - g_atm_priv_data.aal_desc_pos = 0; - - mailbox_signal(RX_DMA_CH_AAL, 0); - } -} - -#if defined(ENABLE_TASKLET) && ENABLE_TASKLET -static void do_ppe_tasklet(unsigned long arg) -{ - *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR; - mailbox_oam_rx_handler(); - mailbox_aal_rx_handler(); - if ( (*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0 ) - tasklet_schedule(&g_dma_tasklet); - else - enable_irq(PPE_MAILBOX_IGU1_INT); -} -#endif - -static irqreturn_t mailbox_irq_handler(int irq, void *dev_id) -{ - if ( !*MBOX_IGU1_ISR ) - return IRQ_HANDLED; - -#if defined(ENABLE_TASKLET) && ENABLE_TASKLET - disable_irq(PPE_MAILBOX_IGU1_INT); - tasklet_schedule(&g_dma_tasklet); -#else - *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR; - mailbox_oam_rx_handler(); - mailbox_aal_rx_handler(); -#endif - - return IRQ_HANDLED; -} - -static INLINE void mailbox_signal(unsigned int queue, int is_tx) -{ - if ( is_tx ) { - while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) ); - *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16); - } - else { - while ( MBOX_IGU3_ISR_ISR(queue) ); - *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue); - } -} - -static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue) -{ - unsigned int qsb_clk = ifx_get_fpi_hz(); - unsigned int qsb_qid = queue + FIRST_QSB_QID; - union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}}; - union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}}; - unsigned int tmp; - -#if defined(DEBUG_QOS) && DEBUG_QOS - if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) { - static char *str_traffic_class[9] = { - "ATM_NONE", - "ATM_UBR", - "ATM_CBR", - "ATM_VBR", - "ATM_ABR", - "ATM_ANYCLASS", - "ATM_VBR_RT", - "ATM_UBR_PLUS", - "ATM_MAX_PCR" - }; - printk(KERN_INFO "QoS Parameters:\n"); - printk(KERN_INFO "\tAAL : %d\n", qos->aal); - printk(KERN_INFO "\tTX Traffic Class: %s\n", str_traffic_class[qos->txtp.traffic_class]); - printk(KERN_INFO "\tTX Max PCR : %d\n", qos->txtp.max_pcr); - printk(KERN_INFO "\tTX Min PCR : %d\n", qos->txtp.min_pcr); - printk(KERN_INFO "\tTX PCR : %d\n", qos->txtp.pcr); - printk(KERN_INFO "\tTX Max CDV : %d\n", qos->txtp.max_cdv); - printk(KERN_INFO "\tTX Max SDU : %d\n", qos->txtp.max_sdu); - printk(KERN_INFO "\tTX SCR : %d\n", qos->txtp.scr); - printk(KERN_INFO "\tTX MBS : %d\n", qos->txtp.mbs); - printk(KERN_INFO "\tTX CDV : %d\n", qos->txtp.cdv); - printk(KERN_INFO "\tRX Traffic Class: %s\n", str_traffic_class[qos->rxtp.traffic_class]); - printk(KERN_INFO "\tRX Max PCR : %d\n", qos->rxtp.max_pcr); - printk(KERN_INFO "\tRX Min PCR : %d\n", qos->rxtp.min_pcr); - printk(KERN_INFO "\tRX PCR : %d\n", qos->rxtp.pcr); - printk(KERN_INFO "\tRX Max CDV : %d\n", qos->rxtp.max_cdv); - printk(KERN_INFO "\tRX Max SDU : %d\n", qos->rxtp.max_sdu); - printk(KERN_INFO "\tRX SCR : %d\n", qos->rxtp.scr); - printk(KERN_INFO "\tRX MBS : %d\n", qos->rxtp.mbs); - printk(KERN_INFO "\tRX CDV : %d\n", qos->rxtp.cdv); - } -#endif // defined(DEBUG_QOS) && DEBUG_QOS - - /* - * Peak Cell Rate (PCR) Limiter - */ - if ( qos->txtp.max_pcr == 0 ) - qsb_queue_parameter_table.bit.tp = 0; /* disable PCR limiter */ - else { - /* peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */ - tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1; - /* check if overflow takes place */ - qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp; - } - - // A funny issue. Create two PVCs, one UBR and one UBR with max_pcr. - // Send packets to these two PVCs at same time, it trigger strange behavior. - // In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000. - // In A4, PPE firmware keep emiting unknown cell and do not respond to driver. - // To work around, create UBR always with max_pcr. - // If user want to create UBR without max_pcr, we give a default one larger than line-rate. - if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) { - int port = g_atm_priv_data.conn[queue].port; - unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000; - - tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1; - if ( tmp > QSB_TP_TS_MAX ) - tmp = QSB_TP_TS_MAX; - else if ( tmp < 1 ) - tmp = 1; - qsb_queue_parameter_table.bit.tp = tmp; - } - - /* - * Weighted Fair Queueing Factor (WFQF) - */ - switch ( qos->txtp.traffic_class ) { - case ATM_CBR: - case ATM_VBR_RT: - /* real time queue gets weighted fair queueing bypass */ - qsb_queue_parameter_table.bit.wfqf = 0; - break; - case ATM_VBR_NRT: - case ATM_UBR_PLUS: - /* WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates */ - /* WFQF is maximum cell rate / garenteed cell rate */ - /* wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate */ - if ( qos->txtp.min_pcr == 0 ) - qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX; - else - { - tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr; - if ( tmp == 0 ) - qsb_queue_parameter_table.bit.wfqf = 1; - else if ( tmp > QSB_WFQ_NONUBR_MAX ) - qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX; - else - qsb_queue_parameter_table.bit.wfqf = tmp; - } - break; - default: - case ATM_UBR: - qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS; - } - - /* - * Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1 - */ - if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) { - if ( qos->txtp.scr == 0 ) { - /* disable shaper */ - qsb_queue_vbr_parameter_table.bit.taus = 0; - qsb_queue_vbr_parameter_table.bit.ts = 0; - } - else { - /* Cell Loss Priority (CLP) */ - if ( (vcc->atm_options & ATM_ATMOPT_CLP) ) - /* CLP1 */ - qsb_queue_parameter_table.bit.vbr = 1; - else - /* CLP0 */ - qsb_queue_parameter_table.bit.vbr = 0; - /* Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */ - tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1; - qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp; - tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64; - if ( tmp == 0 ) - qsb_queue_vbr_parameter_table.bit.taus = 1; - else if ( tmp > QSB_TAUS_MAX ) - qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX; - else - qsb_queue_vbr_parameter_table.bit.taus = tmp; - } - } - else { - qsb_queue_vbr_parameter_table.bit.taus = 0; - qsb_queue_vbr_parameter_table.bit.ts = 0; - } - - /* Queue Parameter Table (QPT) */ - *QSB_RTM = QSB_RTM_DM_SET(QSB_QPT_SET_MASK); - *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword); - *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid); -#if defined(DEBUG_QOS) && DEBUG_QOS - if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) - printk("QPT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC); -#endif - /* Queue VBR Paramter Table (QVPT) */ - *QSB_RTM = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK); - *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword); - *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid); -#if defined(DEBUG_QOS) && DEBUG_QOS - if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) - printk("QVPT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC); -#endif - -#if defined(DEBUG_QOS) && DEBUG_QOS - if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) { - printk("set_qsb\n"); - printk(" qsb_clk = %lu\n", (unsigned long)qsb_clk); - printk(" qsb_queue_parameter_table.bit.tp = %d\n", (int)qsb_queue_parameter_table.bit.tp); - printk(" qsb_queue_parameter_table.bit.wfqf = %d (0x%08X)\n", (int)qsb_queue_parameter_table.bit.wfqf, (int)qsb_queue_parameter_table.bit.wfqf); - printk(" qsb_queue_parameter_table.bit.vbr = %d\n", (int)qsb_queue_parameter_table.bit.vbr); - printk(" qsb_queue_parameter_table.dword = 0x%08X\n", (int)qsb_queue_parameter_table.dword); - printk(" qsb_queue_vbr_parameter_table.bit.ts = %d\n", (int)qsb_queue_vbr_parameter_table.bit.ts); - printk(" qsb_queue_vbr_parameter_table.bit.taus = %d\n", (int)qsb_queue_vbr_parameter_table.bit.taus); - printk(" qsb_queue_vbr_parameter_table.dword = 0x%08X\n", (int)qsb_queue_vbr_parameter_table.dword); - } -#endif -} - -static void qsb_global_set(void) -{ - unsigned int qsb_clk = ifx_get_fpi_hz(); - int i; - unsigned int tmp1, tmp2, tmp3; - - *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau); - *QSB_SBL = QSB_SBL_SBL_SET(qsb_srvm); - *QSB_CFG = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1); -#if defined(DEBUG_QOS) && DEBUG_QOS - if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) { - printk("qsb_clk = %u\n", qsb_clk); - printk("QSB_ICDV (%08X) = %d (%d), QSB_SBL (%08X) = %d (%d), QSB_CFG (%08X) = %d (%d)\n", (unsigned int)QSB_ICDV, *QSB_ICDV, QSB_ICDV_TAU_SET(qsb_tau), (unsigned int)QSB_SBL, *QSB_SBL, QSB_SBL_SBL_SET(qsb_srvm), (unsigned int)QSB_CFG, *QSB_CFG, QSB_CFG_TSTEPC_SET(qsb_tstep >> 1)); - } -#endif - - /* - * set SCT and SPT per port - */ - for ( i = 0; i < ATM_PORT_NUMBER; i++ ) { - if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) { - tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate; - tmp2 = tmp1 >> 6; /* integer value of Tsb */ - tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /* fractional part of Tsb */ - /* carry over to integer part (?) */ - if ( tmp3 == (1 << 6) ) - { - tmp3 = 0; - tmp2++; - } - if ( tmp2 == 0 ) - tmp2 = tmp3 = 1; - /* 1. set mask */ - /* 2. write value to data transfer register */ - /* 3. start the tranfer */ - /* SCT (FracRate) */ - *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SCT_MASK); - *QSB_RTD = QSB_RTD_TTV_SET(tmp3); - *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(i & 0x01); -#if defined(DEBUG_QOS) && DEBUG_QOS - if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) - printk("SCT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC); -#endif - /* SPT (SBV + PN + IntRage) */ - *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SPT_MASK); - *QSB_RTD = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2)); - *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(i & 0x01); -#if defined(DEBUG_QOS) && DEBUG_QOS - if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ) - printk("SPT: QSB_RTM (%08X) = 0x%08X, QSB_RTD (%08X) = 0x%08X, QSB_RAMAC (%08X) = 0x%08X\n", (unsigned int)QSB_RTM, *QSB_RTM, (unsigned int)QSB_RTD, *QSB_RTD, (unsigned int)QSB_RAMAC, *QSB_RAMAC); -#endif - } - } -} - -static INLINE void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx) -{ - struct htu_entry htu_entry = { res1: 0x00, - clp: is_retx ? 0x01 : 0x00, - pid: g_atm_priv_data.conn[queue].port & 0x01, - vpi: vpi, - vci: vci, - pti: 0x00, - vld: 0x01}; - - struct htu_mask htu_mask = { set: 0x01, -#if !defined(ENABLE_ATM_RETX) || !ENABLE_ATM_RETX - clp: 0x01, - pid_mask: 0x02, -#else - clp: g_retx_htu ? 0x00 : 0x01, - pid_mask: RETX_MODE_CFG->retx_en ? 0x03 : 0x02, -#endif - vpi_mask: 0x00, -#if !defined(ENABLE_ATM_RETX) || !ENABLE_ATM_RETX - vci_mask: 0x0000, -#else - vci_mask: RETX_MODE_CFG->retx_en ? 0xFF00 : 0x0000, -#endif - pti_mask: 0x03, // 0xx, user data - clear: 0x00}; - - struct htu_result htu_result = {res1: 0x00, - cellid: queue, - res2: 0x00, - type: aal5 ? 0x00 : 0x01, - ven: 0x01, - res3: 0x00, - qid: queue}; - - *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result; - *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER) = htu_mask; - *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER) = htu_entry; -} - -static INLINE void clear_htu_entry(unsigned int queue) -{ - HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0; -} - -static void validate_oam_htu_entry(void) -{ - HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1; - HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1; - HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1; -#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX - HTU_ENTRY(OAM_ARQ_HTU_ENTRY)->vld = 1; -#endif -} - -static void invalidate_oam_htu_entry(void) -{ - HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0; - HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0; - HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0; -#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX - HTU_ENTRY(OAM_ARQ_HTU_ENTRY)->vld = 0; -#endif -} - -static INLINE int find_vpi(unsigned int vpi) -{ - int i; - unsigned int bit; - - for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) { - if ( (g_atm_priv_data.conn_table & bit) != 0 - && g_atm_priv_data.conn[i].vcc != NULL - && vpi == g_atm_priv_data.conn[i].vcc->vpi ) - return i; - } - - return -1; -} - -static INLINE int find_vpivci(unsigned int vpi, unsigned int vci) -{ - int i; - unsigned int bit; - - for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) { - if ( (g_atm_priv_data.conn_table & bit) != 0 - && g_atm_priv_data.conn[i].vcc != NULL - && vpi == g_atm_priv_data.conn[i].vcc->vpi - && vci == g_atm_priv_data.conn[i].vcc->vci ) - return i; - } - - return -1; -} - -static INLINE int find_vcc(struct atm_vcc *vcc) -{ - int i; - unsigned int bit; - - for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) { - if ( (g_atm_priv_data.conn_table & bit) != 0 - && g_atm_priv_data.conn[i].vcc == vcc ) - return i; - } - - return -1; -} - -#if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB -static void dump_skb(struct sk_buff *skb, u32 len, char *title, int port, int ch, int is_tx) -{ - int i; - - if ( !(ifx_atm_dbg_enable & (is_tx ? DBG_ENABLE_MASK_DUMP_SKB_TX : DBG_ENABLE_MASK_DUMP_SKB_RX)) ) - return; - - if ( skb->len < len ) - len = skb->len; - - if ( len > RX_DMA_CH_AAL_BUF_SIZE ) { - printk("too big data length: skb = %08x, skb->data = %08x, skb->len = %d\n", (u32)skb, (u32)skb->data, skb->len); - return; - } - - if ( ch >= 0 ) - printk("%s (port %d, ch %d)\n", title, port, ch); - else - printk("%s\n", title); - printk(" skb->data = %08X, skb->tail = %08X, skb->len = %d\n", (u32)skb->data, (u32)skb->tail, (int)skb->len); - for ( i = 1; i <= len; i++ ) { - if ( i % 16 == 1 ) - printk(" %4d:", i - 1); - printk(" %02X", (int)(*((char*)skb->data + i - 1) & 0xFF)); - if ( i % 16 == 0 ) - printk("\n"); - } - if ( (i - 1) % 16 != 0 ) - printk("\n"); -} -#endif - -static INLINE void proc_file_create(void) -{ -#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC - struct proc_dir_entry *res; -#endif - - g_atm_dir = proc_mkdir("driver/ifx_atm", NULL); - - create_proc_read_entry("version", - 0, - g_atm_dir, - proc_read_version, - NULL); - - res = create_proc_entry("mib", - 0, - g_atm_dir); - if ( res != NULL ) { - res->read_proc = proc_read_mib; - res->write_proc = proc_write_mib; - } - -#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC - res = create_proc_entry("dbg", - 0, - g_atm_dir); - if ( res != NULL ) { - res->read_proc = proc_read_dbg; - res->write_proc = proc_write_dbg; - } -#endif - -#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC - create_proc_read_entry("htu", - 0, - g_atm_dir, - proc_read_htu, - NULL); - - create_proc_read_entry("txq", - 0, - g_atm_dir, - proc_read_txq, - NULL); -#endif -} - -static INLINE void proc_file_delete(void) -{ -#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC - remove_proc_entry("txq", g_atm_dir); - - remove_proc_entry("htu", g_atm_dir); -#endif - -#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC - remove_proc_entry("dbg", g_atm_dir); -#endif - - remove_proc_entry("version", g_atm_dir); - - remove_proc_entry("driver/ifx_atm", NULL); -} - -static int proc_read_version(char *buf, char **start, off_t offset, int count, int *eof, void *data) -{ - int len = 0; - - len += ifx_atm_version(buf + len); - - if ( offset >= len ) { - *start = buf; - *eof = 1; - return 0; - } - *start = buf + offset; - if ( (len -= offset) > count ) - return count; - *eof = 1; - return len; -} - -static int proc_read_mib(char *page, char **start, off_t off, int count, int *eof, void *data) -{ - int len = 0; - - len += sprintf(page + off + len, "Firmware\n"); - len += sprintf(page + off + len, " wrx_drophtu_cell = %u\n", WAN_MIB_TABLE->wrx_drophtu_cell); - len += sprintf(page + off + len, " wrx_dropdes_pdu = %u\n", WAN_MIB_TABLE->wrx_dropdes_pdu); - len += sprintf(page + off + len, " wrx_correct_pdu = %u\n", WAN_MIB_TABLE->wrx_correct_pdu); - len += sprintf(page + off + len, " wrx_err_pdu = %u\n", WAN_MIB_TABLE->wrx_err_pdu); - len += sprintf(page + off + len, " wrx_dropdes_cell = %u\n", WAN_MIB_TABLE->wrx_dropdes_cell); - len += sprintf(page + off + len, " wrx_correct_cell = %u\n", WAN_MIB_TABLE->wrx_correct_cell); - len += sprintf(page + off + len, " wrx_err_cell = %u\n", WAN_MIB_TABLE->wrx_err_cell); - len += sprintf(page + off + len, " wrx_total_byte = %u\n", WAN_MIB_TABLE->wrx_total_byte); - len += sprintf(page + off + len, " wtx_total_pdu = %u\n", WAN_MIB_TABLE->wtx_total_pdu); - len += sprintf(page + off + len, " wtx_total_cell = %u\n", WAN_MIB_TABLE->wtx_total_cell); - len += sprintf(page + off + len, " wtx_total_byte = %u\n", WAN_MIB_TABLE->wtx_total_byte); - len += sprintf(page + off + len, "Driver\n"); - len += sprintf(page + off + len, " wrx_pdu = %u\n", g_atm_priv_data.wrx_pdu); - len += sprintf(page + off + len, " wrx_drop_pdu = %u\n", g_atm_priv_data.wrx_drop_pdu); - len += sprintf(page + off + len, " wtx_pdu = %u\n", g_atm_priv_data.wtx_pdu); - len += sprintf(page + off + len, " wtx_err_pdu = %u\n", g_atm_priv_data.wtx_err_pdu); - len += sprintf(page + off + len, " wtx_drop_pdu = %u\n", g_atm_priv_data.wtx_drop_pdu); - - *eof = 1; - - return len; -} - -static int proc_write_mib(struct file *file, const char *buf, unsigned long count, void *data) -{ - char str[2048]; - char *p; - int len, rlen; - - len = count < sizeof(str) ? count : sizeof(str) - 1; - rlen = len - copy_from_user(str, buf, len); - while ( rlen && str[rlen - 1] <= ' ' ) - rlen--; - str[rlen] = 0; - for ( p = str; *p && *p <= ' '; p++, rlen-- ); - if ( !*p ) - return 0; - - if ( stricmp(p, "clear") == 0 || stricmp(p, "clear all") == 0 - || stricmp(p, "clean") == 0 || stricmp(p, "clean all") == 0 ) { - memset(WAN_MIB_TABLE, 0, sizeof(*WAN_MIB_TABLE)); - g_atm_priv_data.wrx_pdu = 0; - g_atm_priv_data.wrx_drop_pdu = 0; - g_atm_priv_data.wtx_pdu = 0; - g_atm_priv_data.wtx_err_pdu = 0; - g_atm_priv_data.wtx_drop_pdu = 0; - } - - return count; -} - -#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC - -static int proc_read_dbg(char *page, char **start, off_t off, int count, int *eof, void *data) -{ - int len = 0; - - len += sprintf(page + off + len, "error print - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ? "enabled" : "disabled"); - len += sprintf(page + off + len, "debug print - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ? "enabled" : "disabled"); - len += sprintf(page + off + len, "assert - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) ? "enabled" : "disabled"); - len += sprintf(page + off + len, "dump rx skb - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_RX) ? "enabled" : "disabled"); - len += sprintf(page + off + len, "dump tx skb - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_TX) ? "enabled" : "disabled"); - len += sprintf(page + off + len, "qos - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_QOS) ? "enabled" : "disabled"); - len += sprintf(page + off + len, "dump init - %s\n", (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DUMP_INIT) ? "enabled" : "disabled"); - - *eof = 1; - - return len; -} - -static int proc_write_dbg(struct file *file, const char *buf, unsigned long count, void *data) -{ - static const char *dbg_enable_mask_str[] = { - " error print", - " err", - " debug print", - " dbg", - " assert", - " assert", - " dump rx skb", - " rx", - " dump tx skb", - " tx", - " dump qos", - " qos", - " dump init", - " init", - " all" - }; - static const int dbg_enable_mask_str_len[] = { - 12, 4, - 12, 4, - 7, 7, - 12, 3, - 12, 3, - 9, 4, - 10, 5, - 4 - }; - u32 dbg_enable_mask[] = { - DBG_ENABLE_MASK_ERR, - DBG_ENABLE_MASK_DEBUG_PRINT, - DBG_ENABLE_MASK_ASSERT, - DBG_ENABLE_MASK_DUMP_SKB_RX, - DBG_ENABLE_MASK_DUMP_SKB_TX, - DBG_ENABLE_MASK_DUMP_QOS, - DBG_ENABLE_MASK_DUMP_INIT, - DBG_ENABLE_MASK_ALL - }; - - char str[2048]; - char *p; - - int len, rlen; - - int f_enable = 0; - int i; - - len = count < sizeof(str) ? count : sizeof(str) - 1; - rlen = len - copy_from_user(str, buf, len); - while ( rlen && str[rlen - 1] <= ' ' ) - rlen--; - str[rlen] = 0; - for ( p = str; *p && *p <= ' '; p++, rlen-- ); - if ( !*p ) - return 0; - - if ( strincmp(p, "enable", 6) == 0 ) { - p += 6; - f_enable = 1; - } - else if ( strincmp(p, "disable", 7) == 0 ) { - p += 7; - f_enable = -1; - } - else if ( strincmp(p, "help", 4) == 0 || *p == '?' ) { - printk("echo [err/dbg/assert/rx/tx/init/all] > /proc/eth/dbg\n"); - } - - if ( f_enable ) { - if ( *p == 0 ) { - if ( f_enable > 0 ) - ifx_atm_dbg_enable |= DBG_ENABLE_MASK_ALL; - else - ifx_atm_dbg_enable &= ~DBG_ENABLE_MASK_ALL; - } - else { - do { - for ( i = 0; i < NUM_ENTITY(dbg_enable_mask_str); i++ ) - if ( strincmp(p, dbg_enable_mask_str[i], dbg_enable_mask_str_len[i]) == 0 ) { - if ( f_enable > 0 ) - ifx_atm_dbg_enable |= dbg_enable_mask[i >> 1]; - else - ifx_atm_dbg_enable &= ~dbg_enable_mask[i >> 1]; - p += dbg_enable_mask_str_len[i]; - break; - } - } while ( i < NUM_ENTITY(dbg_enable_mask_str) ); - } - } - - return count; -} - -#endif - -#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC - -static INLINE int print_htu(char *buf, int i) -{ - int len = 0; - - if ( HTU_ENTRY(i)->vld ) { - len += sprintf(buf + len, "%2d. valid\n", i); - len += sprintf(buf + len, " entry 0x%08x - pid %01x vpi %02x vci %04x pti %01x\n", *(u32*)HTU_ENTRY(i), HTU_ENTRY(i)->pid, HTU_ENTRY(i)->vpi, HTU_ENTRY(i)->vci, HTU_ENTRY(i)->pti); - len += sprintf(buf + len, " mask 0x%08x - pid %01x vpi %02x vci %04x pti %01x\n", *(u32*)HTU_MASK(i), HTU_MASK(i)->pid_mask, HTU_MASK(i)->vpi_mask, HTU_MASK(i)->vci_mask, HTU_MASK(i)->pti_mask); - len += sprintf(buf + len, " result 0x%08x - type: %s, qid: %d", *(u32*)HTU_RESULT(i), HTU_RESULT(i)->type ? "cell" : "AAL5", HTU_RESULT(i)->qid); - if ( HTU_RESULT(i)->type ) - len += sprintf(buf + len, ", cell id: %d, verification: %s", HTU_RESULT(i)->cellid, HTU_RESULT(i)->ven ? "on" : "off"); - len += sprintf(buf + len, "\n"); - } - else - len += sprintf(buf + len, "%2d. invalid\n", i); - - return len; -} - -static int proc_read_htu(char *page, char **start, off_t off, int count, int *eof, void *data) -{ - int len = 0; - int len_max = off + count; - char *pstr; - char str[1024]; - int llen; - - int htuts = *CFG_WRX_HTUTS; - int i; - - pstr = *start = page; - - llen = sprintf(pstr, "HTU Table (Max %d):\n", htuts); - pstr += llen; - len += llen; - - for ( i = 0; i < htuts; i++ ) { - llen = print_htu(str, i); - if ( len <= off && len + llen > off ) { - memcpy(pstr, str + off - len, len + llen - off); - pstr += len + llen - off; - } - else if ( len > off ) { - memcpy(pstr, str, llen); - pstr += llen; - } - len += llen; - if ( len >= len_max ) - goto PROC_READ_HTU_OVERRUN_END; - } - - *eof = 1; - - return len - off; - -PROC_READ_HTU_OVERRUN_END: - - return len - llen - off; -} - -static INLINE int print_tx_queue(char *buf, int i) -{ - int len = 0; - - if ( (*WTX_DMACH_ON & (1 << i)) ) { - len += sprintf(buf + len, "%2d. valid\n", i); - len += sprintf(buf + len, " queue 0x%08x - sbid %u, qsb %s\n", *(u32*)WTX_QUEUE_CONFIG(i), (unsigned int)WTX_QUEUE_CONFIG(i)->sbid, WTX_QUEUE_CONFIG(i)->qsben ? "enable" : "disable"); - len += sprintf(buf + len, " dma 0x%08x - base %08x, len %u, vlddes %u\n", *(u32*)WTX_DMA_CHANNEL_CONFIG(i), WTX_DMA_CHANNEL_CONFIG(i)->desba, WTX_DMA_CHANNEL_CONFIG(i)->deslen, WTX_DMA_CHANNEL_CONFIG(i)->vlddes); - } - else - len += sprintf(buf + len, "%2d. invalid\n", i); - - return len; -} - -static int proc_read_txq(char *page, char **start, off_t off, int count, int *eof, void *data) -{ - int len = 0; - int len_max = off + count; - char *pstr; - char str[1024]; - int llen; - - int i; - - pstr = *start = page; - - llen = sprintf(pstr, "TX Queue Config (Max %d):\n", *CFG_WTX_DCHNUM); - pstr += llen; - len += llen; - - for ( i = 0; i < 16; i++ ) { - llen = print_tx_queue(str, i); - if ( len <= off && len + llen > off ) { - memcpy(pstr, str + off - len, len + llen - off); - pstr += len + llen - off; - } - else if ( len > off ) { - memcpy(pstr, str, llen); - pstr += llen; - } - len += llen; - if ( len >= len_max ) - goto PROC_READ_HTU_OVERRUN_END; - } - - *eof = 1; - - return len - off; - -PROC_READ_HTU_OVERRUN_END: - - return len - llen - off; -} - -#endif - -static int stricmp(const char *p1, const char *p2) -{ - int c1, c2; - - while ( *p1 && *p2 ) - { - c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1; - c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2; - if ( (c1 -= c2) ) - return c1; - p1++; - p2++; - } - - return *p1 - *p2; -} - -#if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC -static int strincmp(const char *p1, const char *p2, int n) -{ - int c1 = 0, c2; - - while ( n && *p1 && *p2 ) - { - c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1; - c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2; - if ( (c1 -= c2) ) - return c1; - p1++; - p2++; - n--; - } - - return n ? *p1 - *p2 : c1; -} -#endif - -static INLINE int ifx_atm_version(char *buf) -{ - int len = 0; - unsigned int major, minor; - - ifx_atm_get_fw_ver(&major, &minor); - - len += sprintf(buf + len, "Infineon Technologies ATM driver version %d.%d.%d\n", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR); - len += sprintf(buf + len, "Infineon Technologies ATM (A1) firmware version %d.%d\n", major, minor); - - return len; -} - -#ifdef MODULE -static INLINE void reset_ppe(void) -{ - // TODO: -} -#endif - -static INLINE void check_parameters(void) -{ - /* Please refer to Amazon spec 15.4 for setting these values. */ - if ( qsb_tau < 1 ) - qsb_tau = 1; - if ( qsb_tstep < 1 ) - qsb_tstep = 1; - else if ( qsb_tstep > 4 ) - qsb_tstep = 4; - else if ( qsb_tstep == 3 ) - qsb_tstep = 2; - - /* There is a delay between PPE write descriptor and descriptor is */ - /* really stored in memory. Host also has this delay when writing */ - /* descriptor. So PPE will use this value to determine if the write */ - /* operation makes effect. */ - if ( write_descriptor_delay < 0 ) - write_descriptor_delay = 0; - - if ( aal5_fill_pattern < 0 ) - aal5_fill_pattern = 0; - else - aal5_fill_pattern &= 0xFF; - - /* Because of the limitation of length field in descriptors, the packet */ - /* size could not be larger than 64K minus overhead size. */ - if ( aal5r_max_packet_size < 0 ) - aal5r_max_packet_size = 0; - else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES ) - aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES; - if ( aal5r_min_packet_size < 0 ) - aal5r_min_packet_size = 0; - else if ( aal5r_min_packet_size > aal5r_max_packet_size ) - aal5r_min_packet_size = aal5r_max_packet_size; - if ( aal5s_max_packet_size < 0 ) - aal5s_max_packet_size = 0; - else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES ) - aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES; - if ( aal5s_min_packet_size < 0 ) - aal5s_min_packet_size = 0; - else if ( aal5s_min_packet_size > aal5s_max_packet_size ) - aal5s_min_packet_size = aal5s_max_packet_size; - - if ( dma_rx_descriptor_length < 2 ) - dma_rx_descriptor_length = 2; - if ( dma_tx_descriptor_length < 2 ) - dma_tx_descriptor_length = 2; - if ( dma_rx_clp1_descriptor_threshold < 0 ) - dma_rx_clp1_descriptor_threshold = 0; - else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length ) - dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length; - - if ( dma_tx_descriptor_length < 2 ) - dma_tx_descriptor_length = 2; -} - -static INLINE int init_priv_data(void) -{ - void *p; - int i; - struct rx_descriptor rx_desc = {0}; - struct sk_buff *skb; - volatile struct tx_descriptor *p_tx_desc; - struct sk_buff **ppskb; - - // clear atm private data structure - memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data)); - - // allocate memory for RX (AAL) descriptors - p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL); - if ( p == NULL ) - return IFX_ERROR; - dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT); - g_atm_priv_data.aal_desc_base = p; - p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1); - g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p; - - // allocate memory for RX (OAM) descriptors - p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL); - if ( p == NULL ) - return IFX_ERROR; - dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT); - g_atm_priv_data.oam_desc_base = p; - p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1); - g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p; - - // allocate memory for RX (OAM) buffer - p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL); - if ( p == NULL ) - return IFX_ERROR; - dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT); - g_atm_priv_data.oam_buf_base = p; - p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1)); - g_atm_priv_data.oam_buf = p; - - // allocate memory for TX descriptors - p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL); - if ( p == NULL ) - return IFX_ERROR; - dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT); - g_atm_priv_data.tx_desc_base = p; - - // allocate memory for TX skb pointers - p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL); - if ( p == NULL ) - return IFX_ERROR; - dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4); - g_atm_priv_data.tx_skb_base = p; - - // setup RX (AAL) descriptors - rx_desc.own = 1; - rx_desc.c = 0; - rx_desc.sop = 1; - rx_desc.eop = 1; - rx_desc.byteoff = 0; - rx_desc.id = 0; - rx_desc.err = 0; - rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE; - for ( i = 0; i < dma_rx_descriptor_length; i++ ) { - skb = alloc_skb_rx(); - if ( skb == NULL ) - return IFX_ERROR; - rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF; - g_atm_priv_data.aal_desc[i] = rx_desc; - } - - // setup RX (OAM) descriptors - p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1); - rx_desc.own = 1; - rx_desc.c = 0; - rx_desc.sop = 1; - rx_desc.eop = 1; - rx_desc.byteoff = 0; - rx_desc.id = 0; - rx_desc.err = 0; - rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE; - for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) { - rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF; - g_atm_priv_data.oam_desc[i] = rx_desc; - p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE); - } - - // setup TX descriptors and skb pointers - p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1); - ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3); - for ( i = 0; i < MAX_PVC_NUMBER; i++ ) { - g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length]; - g_atm_priv_data.conn[i].tx_skb = &ppskb[i * dma_tx_descriptor_length]; - } - - for ( i = 0; i < ATM_PORT_NUMBER; i++ ) - g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE; - - return IFX_SUCCESS; -} - -static INLINE void clear_priv_data(void) -{ - int i, j; - struct sk_buff *skb; - - for ( i = 0; i < MAX_PVC_NUMBER; i++ ) { - if ( g_atm_priv_data.conn[i].tx_skb != NULL ) { - for ( j = 0; j < dma_tx_descriptor_length; j++ ) - if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL ) - dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]); - } - } - - if ( g_atm_priv_data.tx_skb_base != NULL ) - kfree(g_atm_priv_data.tx_skb_base); - - if ( g_atm_priv_data.tx_desc_base != NULL ) - kfree(g_atm_priv_data.tx_desc_base); - - if ( g_atm_priv_data.oam_buf_base != NULL ) - kfree(g_atm_priv_data.oam_buf_base); - - if ( g_atm_priv_data.oam_desc_base != NULL ) - kfree(g_atm_priv_data.oam_desc_base); - - if ( g_atm_priv_data.aal_desc_base != NULL ) { - for ( i = 0; i < dma_rx_descriptor_length; i++ ) { - if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { // descriptor initialized - skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr); - dev_kfree_skb_any(skb); - } - } - kfree(g_atm_priv_data.aal_desc_base); - } -} - -static INLINE void init_rx_tables(void) -{ - int i; - struct wrx_queue_config wrx_queue_config = {0}; - struct wrx_dma_channel_config wrx_dma_channel_config = {0}; - struct htu_entry htu_entry = {0}; - struct htu_result htu_result = {0}; - struct htu_mask htu_mask = { set: 0x01, - clp: 0x01, - pid_mask: 0x00, - vpi_mask: 0x00, - vci_mask: 0x00, - pti_mask: 0x00, - clear: 0x00}; - - /* - * General Registers - */ - *CFG_WRX_HTUTS = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER; - *CFG_WRX_QNUM = MAX_QUEUE_NUMBER; - *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL; - *WRX_DMACH_ON = (1 << RX_DMA_CH_TOTAL) - 1; - *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH; - - /* - * WRX Queue Configuration Table - */ - wrx_queue_config.uumask = 0; - wrx_queue_config.cpimask = 0; - wrx_queue_config.uuexp = 0; - wrx_queue_config.cpiexp = 0; - wrx_queue_config.mfs = aal5r_max_packet_size; - wrx_queue_config.oversize = aal5r_max_packet_size; - wrx_queue_config.undersize = aal5r_min_packet_size; - wrx_queue_config.errdp = aal5r_drop_error_packet; - wrx_queue_config.dmach = RX_DMA_CH_AAL; - for ( i = 0; i < MAX_QUEUE_NUMBER; i++ ) - *WRX_QUEUE_CONFIG(i) = wrx_queue_config; - WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM; - - /* - * WRX DMA Channel Configuration Table - */ - wrx_dma_channel_config.chrl = 0; - wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold; - wrx_dma_channel_config.mode = 0; - wrx_dma_channel_config.rlcfg = 0; - - wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN; - wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF; - *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config; - - wrx_dma_channel_config.deslen = dma_rx_descriptor_length; - wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF; - *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config; - - /* - * HTU Tables - */ - for ( i = 0; i < MAX_PVC_NUMBER; i++ ) - { - htu_result.qid = (unsigned int)i; - - *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER) = htu_entry; - *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER) = htu_mask; - *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result; - } - /* OAM HTU Entry */ - htu_entry.vci = 0x03; - htu_mask.pid_mask = 0x03; - htu_mask.vpi_mask = 0xFF; - htu_mask.vci_mask = 0x0000; - htu_mask.pti_mask = 0x07; - htu_result.cellid = OAM_RX_QUEUE; - htu_result.type = 1; - htu_result.ven = 1; - htu_result.qid = OAM_RX_QUEUE; - *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result; - *HTU_MASK(OAM_F4_SEG_HTU_ENTRY) = htu_mask; - *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY) = htu_entry; - htu_entry.vci = 0x04; - htu_result.cellid = OAM_RX_QUEUE; - htu_result.type = 1; - htu_result.ven = 1; - htu_result.qid = OAM_RX_QUEUE; - *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result; - *HTU_MASK(OAM_F4_TOT_HTU_ENTRY) = htu_mask; - *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY) = htu_entry; - htu_entry.vci = 0x00; - htu_entry.pti = 0x04; - htu_mask.vci_mask = 0xFFFF; - htu_mask.pti_mask = 0x01; - htu_result.cellid = OAM_RX_QUEUE; - htu_result.type = 1; - htu_result.ven = 1; - htu_result.qid = OAM_RX_QUEUE; - *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result; - *HTU_MASK(OAM_F5_HTU_ENTRY) = htu_mask; - *HTU_ENTRY(OAM_F5_HTU_ENTRY) = htu_entry; -#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX - htu_entry.pid = 0x0; - htu_entry.vpi = 0x01; - htu_entry.vci = 0x0001; - htu_entry.pti = 0x00; - htu_mask.pid_mask = 0x0; - htu_mask.vpi_mask = 0x00; - htu_mask.vci_mask = 0x0000; - htu_mask.pti_mask = 0x3; - htu_result.cellid = OAM_RX_QUEUE; - htu_result.type = 1; - htu_result.ven = 1; - htu_result.qid = OAM_RX_QUEUE; - *HTU_RESULT(OAM_ARQ_HTU_ENTRY) = htu_result; - *HTU_MASK(OAM_ARQ_HTU_ENTRY) = htu_mask; - *HTU_ENTRY(OAM_ARQ_HTU_ENTRY) = htu_entry; -#endif -} - -static INLINE void init_tx_tables(void) -{ - int i; - struct wtx_queue_config wtx_queue_config = {0}; - struct wtx_dma_channel_config wtx_dma_channel_config = {0}; - struct wtx_port_config wtx_port_config = { res1: 0, - qid: 0, - qsben: 1}; - - /* - * General Registers - */ - *CFG_WTX_DCHNUM = MAX_TX_DMA_CHANNEL_NUMBER; - *WTX_DMACH_ON = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1); - *CFG_WRDES_DELAY = write_descriptor_delay; - - /* - * WTX Port Configuration Table - */ - for ( i = 0; i < ATM_PORT_NUMBER; i++ ) - *WTX_PORT_CONFIG(i) = wtx_port_config; - - /* - * WTX Queue Configuration Table - */ - wtx_queue_config.type = 0x0; - wtx_queue_config.qsben = 1; - wtx_queue_config.sbid = 0; - for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) - *WTX_QUEUE_CONFIG(i) = wtx_queue_config; - - /* - * WTX DMA Channel Configuration Table - */ - wtx_dma_channel_config.mode = 0; - wtx_dma_channel_config.deslen = 0; - wtx_dma_channel_config.desba = 0; - for ( i = 0; i < FIRST_QSB_QID; i++ ) - *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config; - /* normal connection */ - wtx_dma_channel_config.deslen = dma_tx_descriptor_length; - for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) { - wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF; - *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config; - } -} - - - -/* - * #################################### - * Global Function - * #################################### - */ - -static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr) -{ - int i, j; - - ASSERT(port_cell != NULL, "port_cell is NULL"); - ASSERT(xdata_addr != NULL, "xdata_addr is NULL"); - - for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ ) - if ( port_cell->tx_link_rate[j] > 0 ) - break; - for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ ) - g_atm_priv_data.port[i].tx_max_cell_rate = port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j]; - - qsb_global_set(); - - for ( i = 0; i < MAX_PVC_NUMBER; i++ ) - if ( g_atm_priv_data.conn[i].vcc != NULL ) - set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i); - - // TODO: ReTX set xdata_addr - g_xdata_addr = xdata_addr; - - g_showtime = 1; - -#if defined(CONFIG_VR9) - IFX_REG_W32(0x0F, UTP_CFG); -#endif - - printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n", g_atm_priv_data.port[0].tx_max_cell_rate, g_atm_priv_data.port[1].tx_max_cell_rate, (unsigned int)g_xdata_addr); - - return IFX_SUCCESS; -} - -static int atm_showtime_exit(void) -{ -#if defined(CONFIG_VR9) - IFX_REG_W32(0x00, UTP_CFG); -#endif - - g_showtime = 0; - - // TODO: ReTX clean state - g_xdata_addr = NULL; - - printk("leave showtime\n"); - - return IFX_SUCCESS; -} - - - -/* - * #################################### - * Init/Cleanup API - * #################################### - */ - -/* - * Description: - * Initialize global variables, PP32, comunication structures, register IRQ - * and register device. - * Input: - * none - * Output: - * 0 --- successful - * else --- failure, usually it is negative value of error code - */ -static int __devinit ifx_atm_init(void) -{ - int ret; - int port_num; - struct port_cell_info port_cell = {0}; - int i, j; - char ver_str[256]; - -#ifdef MODULE - reset_ppe(); -#endif - - check_parameters(); - - ret = init_priv_data(); - if ( ret != IFX_SUCCESS ) { - err("INIT_PRIV_DATA_FAIL"); - goto INIT_PRIV_DATA_FAIL; - } - - ifx_atm_init_chip(); - init_rx_tables(); - init_tx_tables(); - - /* create devices */ - for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) { - g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", &g_ifx_atm_ops, -1, NULL); - if ( !g_atm_priv_data.port[port_num].dev ) { - err("failed to register atm device %d!", port_num); - ret = -EIO; - goto ATM_DEV_REGISTER_FAIL; - } - else { - g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8; - g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16; - g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate; - g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num; - } - } - - /* register interrupt handler */ - ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "atm_mailbox_isr", &g_atm_priv_data); - if ( ret ) { - if ( ret == -EBUSY ) { - err("IRQ may be occupied by other driver, please reconfig to disable it."); - } - else { - err("request_irq fail"); - } - goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL; - } - disable_irq(PPE_MAILBOX_IGU1_INT); - - ret = ifx_pp32_start(0); - if ( ret ) { - err("ifx_pp32_start fail!"); - goto PP32_START_FAIL; - } - - port_cell.port_num = ATM_PORT_NUMBER; - ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr); - if ( g_showtime ) { - for ( i = 0; i < ATM_PORT_NUMBER; i++ ) - if ( port_cell.tx_link_rate[i] != 0 ) - break; - for ( j = 0; j < ATM_PORT_NUMBER; j++ ) - g_atm_priv_data.port[j].tx_max_cell_rate = port_cell.tx_link_rate[j] != 0 ? port_cell.tx_link_rate[j] : port_cell.tx_link_rate[i]; - } - - qsb_global_set(); - validate_oam_htu_entry(); - - /* create proc file */ - proc_file_create(); - - ifx_mei_atm_showtime_enter = atm_showtime_enter; - ifx_mei_atm_showtime_exit = atm_showtime_exit; - - ifx_atm_version(ver_str); - printk(KERN_INFO "%s", ver_str); - - printk("ifxmips_atm: ATM init succeed\n"); - - return IFX_SUCCESS; - -PP32_START_FAIL: - free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data); -REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL: -ATM_DEV_REGISTER_FAIL: - while ( port_num-- > 0 ) - atm_dev_deregister(g_atm_priv_data.port[port_num].dev); -INIT_PRIV_DATA_FAIL: - clear_priv_data(); - printk("ifxmips_atm: ATM init failed\n"); - return ret; -} - -/* - * Description: - * Release memory, free IRQ, and deregister device. - * Input: - * none - * Output: - * none - */ -static void __exit ifx_atm_exit(void) -{ - int port_num; - - ifx_mei_atm_showtime_enter = NULL; - ifx_mei_atm_showtime_exit = NULL; - - proc_file_delete(); - - invalidate_oam_htu_entry(); - - ifx_pp32_stop(0); - - free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data); - - for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) - atm_dev_deregister(g_atm_priv_data.port[port_num].dev); - - ifx_atm_uninit_chip(); - - clear_priv_data(); -} - -module_init(ifx_atm_init); -module_exit(ifx_atm_exit); diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_core.h b/package/ifxmips-dsl-api/src/ifxmips_atm_core.h deleted file mode 100644 index f7774fbf1f..0000000000 --- a/package/ifxmips-dsl-api/src/ifxmips_atm_core.h +++ /dev/null @@ -1,249 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_atm_core.h -** PROJECT : UEIP -** MODULES : ATM -** -** DATE : 7 Jul 2009 -** AUTHOR : Xu Liang -** DESCRIPTION : ATM driver header file (core functions) -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Date $Author $Comment -** 17 JUN 2009 Xu Liang Init Version -*******************************************************************************/ - -#ifndef IFXMIPS_ATM_CORE_H -#define IFXMIPS_ATM_CORE_H - - - -#include -#include "ifxmips_atm_ppe_common.h" -#include "ifxmips_atm_fw_regs_common.h" - - - -/* - * #################################### - * Definition - * #################################### - */ - -/* - * Compile Options - */ - -#define ENABLE_DEBUG 1 - -#define ENABLE_ASSERT 1 - -#define INLINE - -#define DEBUG_DUMP_SKB 1 - -#define DEBUG_QOS 1 - -#define ENABLE_DBG_PROC 1 - -#define ENABLE_FW_PROC 1 - -#ifdef CONFIG_IFX_ATM_TASKLET - #define ENABLE_TASKLET 1 -#endif - - -/* - * Debug/Assert/Error Message - */ - -#define DBG_ENABLE_MASK_ERR (1 << 0) -#define DBG_ENABLE_MASK_DEBUG_PRINT (1 << 1) -#define DBG_ENABLE_MASK_ASSERT (1 << 2) -#define DBG_ENABLE_MASK_DUMP_SKB_RX (1 << 8) -#define DBG_ENABLE_MASK_DUMP_SKB_TX (1 << 9) -#define DBG_ENABLE_MASK_DUMP_QOS (1 << 10) -#define DBG_ENABLE_MASK_DUMP_INIT (1 << 11) -#define DBG_ENABLE_MASK_ALL (DBG_ENABLE_MASK_ERR | DBG_ENABLE_MASK_DEBUG_PRINT | DBG_ENABLE_MASK_ASSERT | DBG_ENABLE_MASK_DUMP_SKB_RX | DBG_ENABLE_MASK_DUMP_SKB_TX | DBG_ENABLE_MASK_DUMP_QOS | DBG_ENABLE_MASK_DUMP_INIT) - -#define err(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ERR) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 ) - -#if defined(ENABLE_DEBUG) && ENABLE_DEBUG - #undef dbg - #define dbg(format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ) printk(KERN_WARNING __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 ) -#else - #if !defined(dbg) - #define dbg(format, arg...) - #endif -#endif - -#if defined(ENABLE_ASSERT) && ENABLE_ASSERT - #define ASSERT(cond, format, arg...) do { if ( (ifx_atm_dbg_enable & DBG_ENABLE_MASK_ASSERT) && !(cond) ) printk(KERN_ERR __FILE__ ":%d:%s: " format "\n", __LINE__, __FUNCTION__, ##arg); } while ( 0 ) -#else - #define ASSERT(cond, format, arg...) -#endif - - -/* - * Constants - */ -#define DEFAULT_TX_LINK_RATE 3200 // in cells - -/* - * ATM Port, QSB Queue, DMA RX/TX Channel Parameters - */ -#define ATM_PORT_NUMBER 2 -#define MAX_QUEUE_NUMBER 16 -#define OAM_RX_QUEUE 15 -#define QSB_RESERVE_TX_QUEUE 0 -#define FIRST_QSB_QID 1 -#define MAX_PVC_NUMBER (MAX_QUEUE_NUMBER - FIRST_QSB_QID) -#define MAX_RX_DMA_CHANNEL_NUMBER 8 -#define MAX_TX_DMA_CHANNEL_NUMBER 16 -#define DATA_BUFFER_ALIGNMENT EMA_ALIGNMENT -#define DESC_ALIGNMENT 8 -#define DEFAULT_RX_HUNT_BITTH 4 - -/* - * RX DMA Channel Allocation - */ -#define RX_DMA_CH_OAM 0 -#define RX_DMA_CH_AAL 1 -#define RX_DMA_CH_TOTAL 2 -#define RX_DMA_CH_OAM_DESC_LEN 32 -#define RX_DMA_CH_OAM_BUF_SIZE (CELL_SIZE & ~15) -#define RX_DMA_CH_AAL_BUF_SIZE (2048 - 48) - -/* - * OAM Constants - */ -#define OAM_HTU_ENTRY_NUMBER 3 -#define OAM_F4_SEG_HTU_ENTRY 0 -#define OAM_F4_TOT_HTU_ENTRY 1 -#define OAM_F5_HTU_ENTRY 2 -#define OAM_F4_CELL_ID 0 -#define OAM_F5_CELL_ID 15 -//#if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX -// #undef OAM_HTU_ENTRY_NUMBER -// #define OAM_HTU_ENTRY_NUMBER 4 -// #define OAM_ARQ_HTU_ENTRY 3 -//#endif - -/* - * RX Frame Definitions - */ -#define MAX_RX_PACKET_ALIGN_BYTES 3 -#define MAX_RX_PACKET_PADDING_BYTES 3 -#define RX_INBAND_TRAILER_LENGTH 8 -#define MAX_RX_FRAME_EXTRA_BYTES (RX_INBAND_TRAILER_LENGTH + MAX_RX_PACKET_ALIGN_BYTES + MAX_RX_PACKET_PADDING_BYTES) - -/* - * TX Frame Definitions - */ -#define MAX_TX_HEADER_ALIGN_BYTES 12 -#define MAX_TX_PACKET_ALIGN_BYTES 3 -#define MAX_TX_PACKET_PADDING_BYTES 3 -#define TX_INBAND_HEADER_LENGTH 8 -#define MAX_TX_FRAME_EXTRA_BYTES (TX_INBAND_HEADER_LENGTH + MAX_TX_HEADER_ALIGN_BYTES + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES) - -/* - * Cell Constant - */ -#define CELL_SIZE ATM_AAL0_SDU - - - -/* - * #################################### - * Data Type - * #################################### - */ - -typedef struct { - unsigned int h; - unsigned int l; -} ppe_u64_t; - -struct port { - unsigned int tx_max_cell_rate; - unsigned int tx_current_cell_rate; - - struct atm_dev *dev; -}; - -struct connection { - struct atm_vcc *vcc; - - volatile struct tx_descriptor - *tx_desc; - unsigned int tx_desc_pos; - struct sk_buff **tx_skb; - - unsigned int aal5_vcc_crc_err; /* number of packets with CRC error */ - unsigned int aal5_vcc_oversize_sdu; /* number of packets with oversize error */ - - unsigned int port; -}; - -struct atm_priv_data { - unsigned long conn_table; - struct connection conn[MAX_PVC_NUMBER]; - - volatile struct rx_descriptor - *aal_desc; - unsigned int aal_desc_pos; - - volatile struct rx_descriptor - *oam_desc; - unsigned char *oam_buf; - unsigned int oam_desc_pos; - - struct port port[ATM_PORT_NUMBER]; - - unsigned int wrx_pdu; /* successfully received AAL5 packet */ - unsigned int wrx_drop_pdu; /* AAL5 packet dropped by driver on RX */ - unsigned int wtx_pdu; /* successfully tranmitted AAL5 packet */ - unsigned int wtx_err_pdu; /* error AAL5 packet */ - unsigned int wtx_drop_pdu; /* AAL5 packet dropped by driver on TX */ - - ppe_u64_t wrx_total_byte; - ppe_u64_t wtx_total_byte; - unsigned int prev_wrx_total_byte; - unsigned int prev_wtx_total_byte; - - void *aal_desc_base; - void *oam_desc_base; - void *oam_buf_base; - void *tx_desc_base; - void *tx_skb_base; -}; - - - -/* - * #################################### - * Declaration - * #################################### - */ - -extern unsigned int ifx_atm_dbg_enable; - -extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor); - -extern void ifx_atm_init_chip(void); -extern void ifx_atm_uninit_chip(void); - -extern int ifx_pp32_start(int pp32); -extern void ifx_pp32_stop(int pp32); - - - -#endif // IFXMIPS_ATM_CORE_H diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_danube.c b/package/ifxmips-dsl-api/src/ifxmips_atm_danube.c deleted file mode 100644 index 5768678bfe..0000000000 --- a/package/ifxmips-dsl-api/src/ifxmips_atm_danube.c +++ /dev/null @@ -1,272 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : ifxmips_atm_danube.c -** PROJECT : UEIP -** MODULES : ATM -** -** DATE : 7 Jul 2009 -** AUTHOR : Xu Liang -** DESCRIPTION : ATM driver common source file (core functions) -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Date $Author $Comment -** 07 JUL 2009 Xu Liang Init Version -*******************************************************************************/ - - - -/* - * #################################### - * Head File - * #################################### - */ - -/* - * Common Head File - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * Chip Specific Head File - */ -#include -#include -#include -#include -#include "ifxmips_atm_core.h" -#include "ifxmips_atm_fw_danube.h" - - - -/* - * #################################### - * Definition - * #################################### - */ - -/* - * EMA Settings - */ -#define EMA_CMD_BUF_LEN 0x0040 -#define EMA_CMD_BASE_ADDR (0x00001580 << 2) -#define EMA_DATA_BUF_LEN 0x0100 -#define EMA_DATA_BASE_ADDR (0x00001900 << 2) -#define EMA_WRITE_BURST 0x2 -#define EMA_READ_BURST 0x2 - - - -/* - * #################################### - * Declaration - * #################################### - */ - -/* - * Hardware Init/Uninit Functions - */ -static inline void init_pmu(void); -static inline void uninit_pmu(void); -static inline void init_ema(void); -static inline void init_mailbox(void); -static inline void init_atm_tc(void); -static inline void clear_share_buffer(void); - - - -/* - * #################################### - * Local Variable - * #################################### - */ - - - -/* - * #################################### - * Local Function - * #################################### - */ - -static inline void init_pmu(void) -{ - //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9)); - PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE); - PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE); - PPE_TC_PMU_SETUP(IFX_PMU_ENABLE); - PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE); - PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE); - PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE); - DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE); -} - -static inline void uninit_pmu(void) -{ - PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE); - PPE_TC_PMU_SETUP(IFX_PMU_DISABLE); - PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE); - PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE); - PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE); - DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE); - PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE); -} - -static inline void init_ema(void) -{ - IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG); - IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG); - IFX_REG_W32(0x000000FF, EMA_IER); - IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG); -} - -static inline void init_mailbox(void) -{ - IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC); - IFX_REG_W32(0x00000000, MBOX_IGU1_IER); - IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC); - IFX_REG_W32(0x00000000, MBOX_IGU3_IER); -} - -static inline void init_atm_tc(void) -{ - // for ReTX expansion in future - //*FFSM_CFG0 = SET_BITS(*FFSM_CFG0, 5, 0, 6); // pnum = 6 - //*FFSM_CFG1 = SET_BITS(*FFSM_CFG1, 5, 0, 6); // pnum = 6 -} - -static inline void clear_share_buffer(void) -{ - volatile u32 *p = SB_RAM0_ADDR(0); - unsigned int i; - - for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ ) - IFX_REG_W32(0, p++); -} - -/* - * Description: - * Download PPE firmware binary code. - * Input: - * src --- u32 *, binary code buffer - * dword_len --- unsigned int, binary code length in DWORD (32-bit) - * Output: - * int --- IFX_SUCCESS: Success - * else: Error Code - */ -static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) -{ - volatile u32 *dest; - - if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0 - || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 ) - return IFX_ERROR; - - if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) ) - IFX_REG_W32(0x00, CDM_CFG); - else - IFX_REG_W32(0x02, CDM_CFG); - - /* copy code */ - dest = CDM_CODE_MEMORY(0, 0); - while ( code_dword_len-- > 0 ) - IFX_REG_W32(*code_src++, dest++); - - /* copy data */ - dest = CDM_DATA_MEMORY(0, 0); - while ( data_dword_len-- > 0 ) - IFX_REG_W32(*data_src++, dest++); - - return IFX_SUCCESS; -} - - - -/* - * #################################### - * Global Function - * #################################### - */ - -extern void ifx_atm_get_fw_ver(unsigned int *major, unsigned int *minor) -{ - ASSERT(major != NULL, "pointer is NULL"); - ASSERT(minor != NULL, "pointer is NULL"); - - *major = ATM_FW_VER_MAJOR; - *minor = ATM_FW_VER_MINOR; -} - -void ifx_atm_init_chip(void) -{ - init_pmu(); - - init_ema(); - - init_mailbox(); - - init_atm_tc(); - - clear_share_buffer(); -} - -void ifx_atm_uninit_chip(void) -{ - uninit_pmu(); -} - -/* - * Description: - * Initialize and start up PP32. - * Input: - * none - * Output: - * int --- IFX_SUCCESS: Success - * else: Error Code - */ -int ifx_pp32_start(int pp32) -{ - int ret; - - /* download firmware */ - ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data)); - if ( ret != IFX_SUCCESS ) - return ret; - - /* run PP32 */ - IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL); - - /* idle for a while to let PP32 init itself */ - udelay(10); - - return IFX_SUCCESS; -} - -/* - * Description: - * Halt PP32. - * Input: - * none - * Output: - * none - */ -void ifx_pp32_stop(int pp32) -{ - /* halt PP32 */ - IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL); -} diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_fw_danube.h b/package/ifxmips-dsl-api/src/ifxmips_atm_fw_danube.h deleted file mode 100644 index c36c96845c..0000000000 --- a/package/ifxmips-dsl-api/src/ifxmips_atm_fw_danube.h +++ /dev/null @@ -1,429 +0,0 @@ -#ifndef IFXMIPS_ATM_FW_DANUBE_H -#define IFXMIPS_ATM_FW_DANUBE_H - - -/****************************************************************************** -** -** FILE NAME : ifxmips_atm_fw_danube.h -** PROJECT : Danube -** MODULES : ATM (ADSL) -** -** DATE : 1 AUG 2005 -** AUTHOR : Xu Liang -** DESCRIPTION : ATM Driver (PP32 Firmware) -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Date $Author $Comment -** 4 AUG 2005 Xu Liang Initiate Version -** 23 OCT 2006 Xu Liang Add GPL header. -*******************************************************************************/ - - -#define ATM_FW_VER_MAJOR 0 -#define ATM_FW_VER_MINOR 1 - - -static unsigned int firmware_binary_code[] = { - 0x800004A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x8000FFC8, 0x00000000, 0x00000000, 0x00000000, - 0xC1000002, 0xD90C0000, 0xC2000002, 0xDA080001, 0x80004710, 0xC2000000, 0xDA080001, 0x80003D98, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x80003D50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x80004F18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x80003C50, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xC0400000, 0xC0004840, 0xC8840000, 0x800043D0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xC0400002, 0xC0004840, 0xC8840000, 0x80004350, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xC3C00004, 0xDBC80001, 0xC10C0002, 0xD90C0000, 0x8000FEC8, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xC10E0002, 0xD90C0000, 0xC0004808, 0xC8400000, 0x80004380, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xC3E1FFFE, 0x597DFFFE, 0x593DFE14, 0x900004D9, 0x00000000, 0x00000000, 0x00000000, 0x90CC0481, - 0x00000000, 0x00000000, 0x00000000, 0xC3C00000, 0xDBC80001, 0xC1400008, 0xC1900000, 0x71948000, - 0x15000100, 0xC140000A, 0xC1900002, 0x71948000, 0x15000100, 0xC140000C, 0xC1900004, 0x71948000, - 0x15000100, 0xC1400004, 0xC1900006, 0x71948000, 0x15000100, 0xC1400006, 0xC1900008, 0x71948000, - 0x15000100, 0xC140000E, 0xC190000A, 0x71948000, 0x15000100, 0xC1400000, 0xC190000C, 0x71948000, - 0x15000100, 0xC1400002, 0xC190000E, 0x71948000, 0x15000100, 0xC0400000, 0xC11C0000, 0xC000082C, - 0xCD040E08, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0400002, 0xC11C0000, 0xC000082C, 0xCD040E08, - 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0000824, 0x00000000, 0xCBC00001, 0xCB800001, 0xCB400001, - 0xCB000000, 0xC0004878, 0x5BFC4000, 0xCFC00001, 0x5BB84000, 0xCF800001, 0x5B744000, 0xCF400001, - 0x5B304000, 0xCF000000, 0xC0000A10, 0x00000000, 0xCBC00001, 0xCB800000, 0xC0004874, 0x5BFC4000, - 0xCFC00001, 0x5BB84000, 0xCF800000, 0xC30001FE, 0xC000140A, 0xCF000000, 0xC3000000, 0x7F018000, - 0xC000042E, 0xCF000000, 0xC000040E, 0xCF000000, 0xC3C1FFFE, 0xC000490E, 0xCFC00080, 0xC000492C, - 0xCFC00080, 0xC0004924, 0xCFC00040, 0xC0004912, 0xCFC00040, 0xC0004966, 0xCFC00040, 0xC0004968, - 0xCFC00080, 0xC000496A, 0xCFC00080, 0xC3C00000, 0xC2800020, 0xC3000000, 0x7F018000, 0x6FF88000, - 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FFA8, 0x00000000, - 0xC3C00000, 0xC2800010, 0x6FF86000, 0x47F9C000, 0x5BB84C80, 0xC3400000, 0x58380004, 0xCB420080, - 0x00000000, 0x58380008, 0xCF400080, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0xC3C00000, 0xC2800020, - 0xC348001E, 0xC3000000, 0x7F018000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, - 0x58380008, 0xCF400420, 0x5838000A, 0xCF000000, 0x5BFC0002, 0xB7E8FF90, 0x00000000, 0x00000000, - 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0x80000518, 0x00000000, 0x80002118, 0x00000000, - 0x8000FFC8, 0xC0004958, 0xC8400000, 0x00000000, 0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848, - 0xCB840000, 0xC000495C, 0xCAC40000, 0xC0004844, 0xC8840000, 0x46F90000, 0x8400FF6A, 0xC000487C, - 0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC0001624, 0xCB040000, 0xA63C005A, - 0x00000000, 0x00000000, 0xA71EFF02, 0x00000000, 0xC0000824, 0xCA840000, 0x6CA08000, 0x6CA42000, - 0x46610000, 0x42290000, 0xC35E0002, 0xC6340068, 0xC0001624, 0xCF440080, 0xC2000000, 0xC161FFFE, - 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004844, 0xC8840000, 0xC000082C, 0xCA040040, 0x00000000, - 0x00000000, 0x58880002, 0xB608FFF8, 0x00000000, 0xC0800000, 0xC0004844, 0xCC840040, 0x5AEC0002, - 0xC000495C, 0xCEC40000, 0x5E6C0006, 0x84000048, 0xC0004848, 0xCB840000, 0xC0000838, 0xC2500002, - 0xCE440808, 0x5FB80002, 0xC0004848, 0xCF840000, 0x5EEC0002, 0xC000495C, 0xCEC40000, 0x00000000, - 0xC121FFFE, 0x5911FE14, 0x15000000, 0x8000FD80, 0xC000495A, 0xC8400000, 0x00000000, 0xC3C00002, - 0x7BC42000, 0xCC400000, 0xC0004960, 0xCAC40000, 0x00000000, 0x00000000, 0x5EEC0000, 0x840000F2, - 0x00000000, 0xB6FC0030, 0xC0001600, 0xCA040000, 0x00000000, 0x00000000, 0xA61E00B2, 0x6FE90000, - 0xC0000A28, 0xCE840808, 0xC2C00000, 0xC2800004, 0xB6E80080, 0xC0001604, 0xCA840000, 0xC0004960, - 0xCEC40000, 0xA69EFCA2, 0x00000000, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00002, 0xC0001600, - 0xCA040000, 0x00000000, 0x00000000, 0xA61E000A, 0x6FE90000, 0xC0000A28, 0xCE840808, 0xC2C00000, - 0xC0001604, 0xCA840000, 0xC0004960, 0xCEC40000, 0xA69EFC0A, 0xC2400000, 0xC0000A14, 0xCA440030, - 0x00000000, 0x00000000, 0x46E52000, 0xA4400000, 0xC2800000, 0xDFEB0031, 0x8000FFF8, 0xDFEA0031, - 0xB668FB82, 0x00000000, 0xC00048A0, 0xCB040000, 0xC0000A10, 0xCA840000, 0x6F208000, 0x6F242000, - 0x46610000, 0x42A10000, 0xC2400000, 0xC0000A14, 0xCA440030, 0xC35E0002, 0xC6340068, 0xC0001604, - 0xCF440080, 0x5B300002, 0xB670FFF8, 0x5AEC0002, 0xC3000000, 0xC00048A0, 0xCF040000, 0xC0004960, - 0xCEC40000, 0x8000FAC0, 0xC0004918, 0xD2800000, 0xC2000000, 0xDF600040, 0x5E600080, 0x8400025A, - 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC000480A, 0xCA000000, 0xC0004912, - 0xCA400000, 0xC0004924, 0xCA800000, 0xC0004966, 0xCAC00000, 0x00000000, 0xC121FFFE, 0x5911FE14, - 0x15000000, 0x76610000, 0x76A10000, 0x76E10000, 0x840001B2, 0xC0004918, 0xCA400000, 0xC28001FE, - 0x76A10000, 0x5A640002, 0x6A254010, 0x5EE80000, 0x84000002, 0x6AA54000, 0x8000FFF8, 0xC6280000, - 0x62818008, 0xC0004918, 0xCF000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0xC0004966, - 0xCA400000, 0xC2000002, 0x6A310000, 0x7E010000, 0x76252000, 0xCE400000, 0x00000000, 0xC121FFFE, - 0x5911FE14, 0x15000000, 0x6F346000, 0x4735A000, 0x5B744C80, 0xC2800000, 0x58340006, 0xCA800080, - 0xC2C00000, 0x58340000, 0xCAC000E0, 0xC2400000, 0x5834000A, 0xCA420080, 0x6EA82000, 0x42E9E000, - 0x6F2CA000, 0x42E56000, 0x5AEC1400, 0xC3990040, 0xC7381C20, 0xC6F80068, 0x99005930, 0xDB980000, - 0xDBD80001, 0x00000000, 0xDEA00000, 0x47210000, 0x8400FD68, 0xC0004958, 0xC8400000, 0x00000000, - 0xC3C00002, 0x7BC42000, 0xCC400000, 0xC0004848, 0xCB840000, 0xC0004844, 0xC8840000, 0x5FB80000, - 0x8400F7DA, 0xC0001A1C, 0xCA000000, 0xC2400002, 0x6A452000, 0x76610000, 0x8400F7AA, 0xC000487C, - 0xC8040000, 0x00000000, 0x00000000, 0x40080000, 0xCA000000, 0xC4240000, 0x00000000, 0xA63C17BA, - 0x00000000, 0xC0004878, 0xC8040000, 0x6C908000, 0x44908000, 0x44908000, 0x40100000, 0xCA000000, - 0xC4240000, 0x00000000, 0xC0004934, 0xCE000000, 0xC2800002, 0xC4681C10, 0xC62821D8, 0xC2600010, - 0x5A650040, 0xC0004800, 0xCB400000, 0xC2200400, 0x5A200000, 0xC7601048, 0xC0001220, 0xCE800000, - 0xC0001200, 0xCE400000, 0xC0001202, 0xCE000000, 0xC0001240, 0xCB400000, 0x00000000, 0x00000000, - 0xA754FFC0, 0xC2000000, 0xC7600048, 0xA7520022, 0x00000000, 0x00000000, 0x990060A8, 0xC0004822, - 0xC9400000, 0xC1800002, 0x80001668, 0x58204080, 0xC2000000, 0xCA000020, 0xC2400000, 0xCA414008, - 0xC2800000, 0xCA812008, 0xC2C00000, 0xCAC20020, 0xC0004938, 0xCE000000, 0xC0004920, 0xCE400000, - 0xC0004916, 0xCE800000, 0xC0004922, 0xCEC00000, 0xA6400520, 0x00000000, 0xC0004938, 0xCBC00000, - 0x00000000, 0xC3800000, 0x6FF48000, 0x6FD44000, 0x4355A000, 0x5B744A00, 0x58340000, 0xCB802018, - 0x00000000, 0xC2000000, 0x6FB46000, 0x47B5A000, 0x5B744C80, 0x5834000C, 0xCA000028, 0xC000491A, - 0xCF800000, 0x5E200000, 0x84000452, 0xC2000000, 0xDF610050, 0x5E6001E8, 0x8800FFD0, 0xC2000002, - 0xC2400466, 0xC2A00000, 0x5AA80000, 0xC0001006, 0xCE000000, 0xC0001008, 0xCE400000, 0xC000100A, - 0xCE800000, 0x99005370, 0xC1A0FFFE, 0xC0000824, 0xC9840068, 0xC0004934, 0xCA400000, 0xC2000000, - 0xC2800002, 0x990053B0, 0xDA980000, 0xC6140000, 0xC6580000, 0xC161FFFE, 0x5955FFFE, 0x15400000, - 0x00000000, 0x99005498, 0xC000491A, 0xC9400000, 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14, - 0x15000000, 0xC0004922, 0xCA001120, 0xC3C00000, 0xC3800000, 0xC0004930, 0xCE001120, 0xC0004932, - 0xCBC000E0, 0xC2800000, 0xC000491E, 0xCFC00000, 0xC0004862, 0xCA800068, 0xC3A0001A, 0x5BB94000, - 0xC6B80068, 0xC000491C, 0xCF800000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0x00000000, - 0x00000000, 0x00000000, 0xA8E2FFC8, 0xC2000000, 0xC1220002, 0xD90C0000, 0xDF600040, 0x5E600080, - 0x8400FFDA, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000, 0x00000000, 0x99005930, - 0xDA180000, 0xDA580001, 0x00000000, 0xC2000000, 0xDF610050, 0x5E6001FE, 0x8800FFD0, 0xC0004916, - 0xCA800000, 0xC2C00000, 0xDFEC0050, 0xC2400000, 0x46E52000, 0x84000032, 0x5EA80000, 0x84000022, - 0xC2600002, 0x990060A8, 0xC000482E, 0xC9400000, 0xC1800002, 0x80000018, 0xC2600000, 0x990060A8, - 0xC000482C, 0xC9400000, 0xC1800002, 0xC2000068, 0xC6240080, 0xC0004930, 0xCE400088, 0xC000491A, - 0xC9800000, 0xC0004862, 0xC9400000, 0x6D9C6000, 0x459CE000, 0x59DC4C80, 0x99005790, 0xD9580000, - 0xD9980001, 0xD9D40000, 0x99005708, 0xC000491C, 0xC1400000, 0xC9420050, 0xC2000000, 0xDF600040, - 0x5E600080, 0x8400FFD2, 0x00000000, 0xC000491C, 0xCA000000, 0xC000491E, 0xCA400000, 0x00000000, - 0x00000000, 0x99005930, 0xDA180000, 0xDA580001, 0x00000000, 0x800010D0, 0x00000000, 0x990060A8, - 0xC000482A, 0xC9400000, 0xC1800002, 0x800010A0, 0xC0004938, 0xCBC00000, 0x00000000, 0x00000000, - 0x6FF88000, 0x6FD44000, 0x4395C000, 0x5BB84A00, 0x58380008, 0xCA000000, 0x00000000, 0x00000000, - 0xA6000362, 0x00000000, 0xC0004938, 0xCBC00000, 0xC3000000, 0x00000000, 0x6FF88000, 0x6FD44000, - 0x4395C000, 0x5BB84A00, 0x58380000, 0xCB002018, 0xC2000000, 0x58380008, 0xCA020080, 0x5838000C, - 0xCAC00000, 0x5838000E, 0xCA400000, 0xC000491A, 0xCF000000, 0xC0004930, 0xCEC00000, 0xC000493C, - 0xCE000000, 0xC0004932, 0xCE400000, 0x5E200000, 0x84000108, 0xC2800000, 0xA6FE009A, 0x6F206000, - 0x47210000, 0x5A204C80, 0x5820000C, 0xCA800028, 0x00000000, 0x00000000, 0x5EA80000, 0x840001DA, - 0x00000000, 0xC161FFFE, 0x5955FFFE, 0x15400000, 0x00000000, 0x99005498, 0xC000491A, 0xC9400000, - 0x00000000, 0x00000000, 0xC121FFFE, 0x5911FE14, 0x15000000, 0xC0004930, 0xCAC00000, 0xC0004932, - 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0xC1800000, 0xC000082C, 0xC9840030, 0x59540002, 0xC0004848, 0xCD440000, 0x58880002, 0xB49801A8, - 0x00000000, 0xC0800000, 0x80000198, 0xC0004854, 0xC1000000, 0xCD040000, 0xC11C0000, 0xC000082C, - 0xCD040E08, 0x99005348, 0xC0004848, 0xC9440000, 0xC1800000, 0xC2000000, 0xC0000820, 0xCE040000, - 0xC1200000, 0xC0000818, 0xCD041008, 0xC11C0002, 0xC000082C, 0xCD040E08, 0xC0004850, 0xCE040000, - 0xC2000002, 0xC0001ACC, 0xCE040010, 0x800000D0, 0xC2000002, 0xC0004850, 0xCE040000, 0x8000FE70, - 0xC2000000, 0xC0004850, 0xCE040000, 0xA7E60012, 0x00000000, 0xC2000002, 0xC0001B00, 0xCE040008, - 0x8000FE58, 0x00000000, 0xA7860032, 0x00000000, 0xC6800000, 0xC13C0002, 0xCD001E08, 0xC2020002, - 0xC7E2A548, 0xC0001B00, 0xCE040000, 0x8000FE00, 0xC2040002, 0xC0001B00, 0xCE040208, 0x8000FDE0, - 0xC2C80002, 0x6AC56000, 0xDACC0000, 0xC0004854, 0xCB440000, 0xC0004848, 0xCB840000, 0xC0000838, - 0xC3C00000, 0xCBC40030, 0x5EF40004, 0x8400000A, 0xC3000000, 0xC0001ACC, 0xCF040108, 0x47BD8000, - 0x84000012, 0x47BD8000, 0x88000018, 0xC1006E8C, 0x8000B908, 0xC0004840, 0xCC840000, 0x8000F6B8, - 0xC0001AC0, 0xCAC40000, 0xC0004854, 0xCB440000, 0xA6C0FBD2, 0x00000000, 0x5EF40000, 0x8400F712, - 0x5EF40002, 0x8400F9A2, 0x5EF40004, 0x8400FBA2, 0xC1006CE8, 0x8000B880, 0x00000000, 0xC0800000, - 0xDF4B0040, 0xC0004900, 0xCB800000, 0xC2000000, 0xC000490A, 0xA78000B0, 0xCBC00000, 0xC1000000, - 0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF46000, 0x47F5A000, 0x5B744C80, 0xC2400000, 0x58340004, - 0xCA400080, 0xC0004900, 0xCE000008, 0x5A640002, 0x58340004, 0xC6500080, 0xCD000080, 0xC0004914, - 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC0000408, 0xCE000000, 0xA78200B8, - 0xC0004908, 0xCBC00000, 0xC1000000, 0xD9000001, 0xC1000002, 0xD90C0000, 0x6FF4A000, 0x6FD44000, - 0x4575A000, 0x47F5A000, 0x5B744E20, 0xC2800000, 0x58340006, 0xCA800080, 0xC2000000, 0xC0004900, - 0xCE000108, 0x5EA80002, 0x58340006, 0xC6900080, 0xCD000080, 0x5A7C0020, 0xC2000002, 0x6A250000, - 0xC0000408, 0xCE000000, 0xDCA80001, 0x5EA80000, 0x8400B6F0, 0x00000000, 0xA4800210, 0x00000000, - 0xC3C00000, 0xC000140E, 0xCBC00020, 0xC3400000, 0xC2400000, 0x6FF86000, 0x47F9C000, 0x5BB84C80, - 0x58380008, 0xCB400080, 0x58380006, 0xCA400080, 0x5F740002, 0x58380008, 0xC7500080, 0xCD000080, - 0xC2000000, 0x58380004, 0xCA020080, 0xC3000000, 0x5838000C, 0xCB000028, 0x5A640002, 0x46250000, - 0x8400FFF8, 0xC2400000, 0x58380006, 0xC6500080, 0xCD000080, 0xC2000000, 0x5838000A, 0xCA020080, - 0x5B300002, 0x5838000C, 0xC7100028, 0xCD000028, 0xC2420020, 0x5A200004, 0x46612000, 0x8400FFF8, - 0xC2000000, 0x5838000A, 0xC6101080, 0xCD001080, 0xC0004966, 0xCA400000, 0xC2000002, 0x6A3D0000, - 0x72252000, 0xCE400000, 0x5F740000, 0x84000028, 0xC0004912, 0xCA000000, 0xC2C00002, 0x6AFD6000, - 0x7EC16000, 0x76E10000, 0xCE000000, 0x5F300020, 0x84000028, 0xC0004924, 0xCA000000, 0xC2C00002, - 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4820050, 0xC2400000, 0xC000140E, 0xCA408020, - 0xC2000002, 0xC0004900, 0xCE000008, 0xC000490A, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080, - 0xC1000004, 0xD9000001, 0xA4840288, 0x00000000, 0xC3C00000, 0xC000140E, 0xCBC10020, 0xC2800000, - 0xC2000000, 0x6FF8A000, 0x6FD44000, 0x4579C000, 0x47F9C000, 0x5BB84E20, 0x5838002E, 0xCA800080, - 0x58380006, 0xCA020080, 0xC3400000, 0x5838002E, 0xCB420080, 0x5AA80002, 0x46290000, 0x8400FFF8, - 0xC2800000, 0x5838002E, 0xC6900080, 0xCD000080, 0x5F740002, 0x5838002E, 0xC7501080, 0xCD001080, - 0xC0004968, 0xCA400000, 0xC2000002, 0x6A3D0000, 0x72252000, 0xCE400000, 0xC000492A, 0xCA800000, - 0x5E740000, 0x84000028, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, - 0xCE000000, 0x6ABD4010, 0xA68000D2, 0x00000000, 0xC0004910, 0xCA000000, 0xC2C00002, 0x6AFD6000, - 0x7EC16000, 0x76E10000, 0xCE000000, 0x58380032, 0xCA000000, 0x58000002, 0xCA400000, 0x5838000C, - 0x00000000, 0xCE000001, 0xCE400000, 0xC000492A, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000, - 0xCE000000, 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x72E10000, 0xCE000000, 0x80000028, - 0xC000492C, 0xCA000000, 0xC2C00002, 0x6AFD6000, 0x7EC16000, 0x76E10000, 0xCE000000, 0xA4880100, - 0xC2C00000, 0xC000140E, 0xCAC20020, 0xC000490E, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x7E010000, - 0x76252000, 0xCE400000, 0xC000496A, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000, - 0x6EF0A000, 0x6ED44000, 0x45718000, 0x46F18000, 0x5B304E20, 0x58300000, 0xCA000000, 0x00000000, - 0xC2400002, 0x76252000, 0x84000032, 0xC24C0002, 0xC6E40020, 0xC624C408, 0x58300010, 0xCA400508, - 0x00000000, 0xC0001800, 0xCE400000, 0xA4860050, 0xC2400000, 0xC000140E, 0xCA418020, 0xC2020002, - 0xC0004900, 0xCE000108, 0xC0004908, 0xCE400000, 0xC1000000, 0xD9000001, 0xD8400080, 0xC1000004, - 0xD9000001, 0xC0001408, 0xCC800000, 0xC10E0002, 0xD90C0000, 0x8000EDA8, 0xDFBC0001, 0xC000496E, - 0x99006050, 0xC9400000, 0xC7D80000, 0x00000000, 0xC5700000, 0x5EF00020, 0x88000130, 0x6F346000, - 0x4735A000, 0x5B744C80, 0x58340008, 0xC2400000, 0xCA400080, 0x00000000, 0xC2000000, 0x5A640002, - 0xCE400080, 0x58340004, 0xCA000080, 0x00000000, 0x00000000, 0x5E200002, 0xCE000080, 0xC0004912, - 0xCA800000, 0xC2400002, 0x6A712000, 0x72694000, 0xCE800000, 0x5E200000, 0x8400003A, 0xC000480A, - 0xCA000000, 0xC0000408, 0xCA800000, 0x76610000, 0x00000000, 0x72294000, 0xCE800000, 0x80000020, - 0xC0004914, 0xCA000000, 0x7E412000, 0x00000000, 0x76610000, 0xCE000000, 0x800000B8, 0x6EF4A000, - 0x6ED44000, 0x4575A000, 0x46F5A000, 0x5B744E20, 0x5834002E, 0xC2400000, 0xCA420080, 0x00000000, - 0xC2000000, 0x5A640002, 0xC6501080, 0xCD001080, 0x58340006, 0xCA000080, 0x00000000, 0x00000000, - 0x5A200002, 0xCE000080, 0xC0004910, 0xCA400000, 0xC2000002, 0x6A2D0000, 0x72252000, 0xCE400000, - 0xC2000002, 0x6A310000, 0xC000042A, 0xCE000000, 0xC1040002, 0xD90C0000, 0x00000000, 0x8000EB18, - 0x00000000, 0xC4980930, 0x9D000000, 0xC5580030, 0xC0000838, 0xCD840000, 0xC1440200, 0xC1C03200, - 0xC55C1078, 0xC000100E, 0x9D000000, 0xCD800000, 0xC000100C, 0xCDC00000, 0xC0004862, 0xC9C00000, - 0x00000000, 0x00000000, 0xD9D80001, 0xC0007200, 0x401C0000, 0x5DC07400, 0x8800FFFA, 0x5C000200, - 0xCD800000, 0xC1F0000A, 0x71D4A000, 0xDD980000, 0xDD9C0001, 0x41D8E000, 0xC5D40268, 0xC0001010, - 0xCD400000, 0x6C9C8000, 0x449CE000, 0x449CE000, 0x59DC0004, 0xC1601260, 0xC5D40268, 0x9D000000, - 0xC0001012, 0xCD400000, 0x00000000, 0x00000000, 0xD9580000, 0x6D586000, 0x4558C000, 0x59984C80, - 0xD9980001, 0x5818000A, 0xC1800000, 0xC9800080, 0xC0005400, 0x6D5CA000, 0x401C0000, 0x40180000, - 0xC9400000, 0x58000002, 0x00000000, 0xC9C00000, 0xC0004930, 0xCD400000, 0xC0004932, 0xCDC00000, - 0x59980004, 0xC1C20020, 0xB59CFFF8, 0x00000000, 0xC1800000, 0xDD9C0001, 0x581C000A, 0xCD800080, - 0x581C000C, 0xC1800000, 0xC9800028, 0xC1C00002, 0xDD940000, 0x69D4E000, 0x5D980002, 0xCD800028, - 0xC0004924, 0xC9800000, 0x00000000, 0x9D000000, 0x00000000, 0x71D8C000, 0xCD800000, 0xC000492A, - 0xC9400000, 0xC1C00002, 0x69D8E000, 0x7DC0C000, 0x7594A000, 0xCD400000, 0xC000492C, 0xC9400000, - 0xDD800001, 0x58000032, 0x75D4A000, 0x84000078, 0xC9400001, 0xC9800000, 0xDD800001, 0x5800000C, - 0x00000000, 0xCD400001, 0xCD800000, 0xC000492C, 0xC9400000, 0xC000492A, 0xC9800000, 0x71D4A000, - 0xC000492C, 0xCD400000, 0x71D8C000, 0xC000492A, 0xCD800000, 0x9D000000, 0x00000000, 0x00000000, - 0x00000000, 0xC0004862, 0xC9800000, 0x00000000, 0xC1C00200, 0x4194C000, 0x45D8E000, 0x8800FFFA, - 0xC5D80000, 0xC0004862, 0xCD800000, 0xC0001406, 0xC9800000, 0xC1C00002, 0x9D000000, 0xC5D80A08, - 0xC5581050, 0xCD800000, 0xC0004930, 0xC9800000, 0xC0004932, 0xC9C00000, 0xC140000E, 0xC5581C20, - 0xDD940000, 0xC0007200, 0x40140000, 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0x58000002, - 0x5D407400, 0x8800FFFA, 0x5C000200, 0xCDC00000, 0xDD540000, 0xC1C00000, 0x58140006, 0xC9C20080, - 0xC1800000, 0x58140000, 0xC98000E0, 0x6DDC2000, 0xC000491E, 0x41D8E000, 0xCDC00000, 0xDD980000, - 0xC1C00022, 0xC5D80D78, 0xDD940001, 0xC5581C20, 0xC000491C, 0xCD800000, 0xDD540000, 0xC1C00000, - 0x58140006, 0xC9C20080, 0xC1800000, 0x58140004, 0xC9820080, 0x00000000, 0x59DC0002, 0x459CC000, - 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140006, 0xC5D81080, 0xCD801080, 0xC0004860, 0xC9400000, - 0xC1800100, 0xC1D00002, 0x58146B00, 0xD5800000, 0x58000002, 0xD5800001, 0x59540004, 0xB558FFF8, - 0xC0004860, 0xC1400000, 0xCD400000, 0xDD980001, 0x9D000000, 0xDD940000, 0xC0001404, 0xCDC00808, - 0xC1C00000, 0xC1800200, 0x5D980004, 0xDF5D0050, 0x45D8A000, 0x8800FFDA, 0xDD800001, 0x5800000C, - 0x00000000, 0xC9400001, 0xC9800000, 0xC1C00002, 0xC5D43F08, 0xC5D81E08, 0xC0004862, 0xC9C00000, - 0x00000000, 0x00000000, 0x581C7200, 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD400000, 0x58000002, - 0x5DC07400, 0x8800FFFA, 0x5C000200, 0xCD800000, 0xC0004862, 0xC9C00000, 0x00000000, 0xC15004C0, - 0xC5D40068, 0xDD9C0000, 0xC5D41C20, 0xC1C00000, 0xDD800001, 0x58000030, 0xC9C00080, 0xDD800001, - 0x58000002, 0xC9800000, 0x6DDC2000, 0xC000491C, 0x41D8E000, 0xCD400001, 0xCDC00000, 0xDD940001, - 0xC1C00000, 0x58140030, 0xC9C00080, 0xC1800000, 0x58140006, 0xC9820080, 0x00000000, 0x59DC0002, - 0x459CC000, 0x8400FFF8, 0xC1C00000, 0x9D000000, 0x58140030, 0xC5D80080, 0xCD800080, 0xC1C00000, - 0xDF5C0040, 0x5DDC0080, 0x8400FFD2, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, - 0xC160FFFE, 0xC0000A10, 0xC9440068, 0xC1A0FFFE, 0x59980E28, 0xC000100C, 0xCD400000, 0xC000100E, - 0xCD800000, 0xC0004964, 0xC9800000, 0x00000000, 0xC170000A, 0x7194A000, 0x6C988000, 0x4498C000, - 0x4498C000, 0x59980004, 0xC5940278, 0xC0001010, 0xCD400000, 0xC0004946, 0xC9400000, 0x00000000, - 0x00000000, 0x6D58A000, 0x6D5C4000, 0x45D8C000, 0x4558C000, 0xC000494A, 0xC9400000, 0xC0004948, - 0xC9C00000, 0x4194C000, 0xC1400012, 0xC55C1820, 0x9D000000, 0xC59C0270, 0xC0001012, 0xCDC00000, - 0xC1400000, 0x58000012, 0xC9410040, 0xC0004950, 0xC9C00000, 0xC5580000, 0xC5940840, 0xC5581080, - 0xD9940000, 0xC000493C, 0xC9400000, 0xC0004954, 0xC9800000, 0x59DC00A8, 0x455CE000, 0x41D8E000, - 0x5D5C0030, 0x8800FFF8, 0xC1C00030, 0xC1800000, 0xC5D84030, 0xC1400000, 0xC5D40010, 0x5DD40002, - 0x8400005A, 0x5DD40004, 0x84000082, 0x5DD40006, 0x840000AA, 0x5DD80026, 0x840000D2, 0xDD540000, - 0xDD800001, 0x58000008, 0x40180000, 0xCD400000, 0x59980002, 0x8000FFA8, 0xDD540000, 0xDD800001, - 0x58000008, 0x40180000, 0xCD4000C0, 0x59980002, 0x8000FF70, 0xDD540000, 0xDD800001, 0x58000008, - 0x40180000, 0xCD400080, 0x59980002, 0x8000FF38, 0xDD540000, 0xDD800001, 0x58000008, 0x40180000, - 0xCD400040, 0x59980002, 0x8000FF00, 0x00000000, 0x9D000000, 0x00000000, 0x00000000, 0x00000000, - 0x58000012, 0xC9400000, 0xC0004954, 0xC9C00000, 0xC0004950, 0xC9400080, 0xDD800001, 0x58000028, - 0x5D9C0000, 0x8400003A, 0x5D9C0002, 0x8400003A, 0x5D9C0004, 0x84000052, 0xC55B0040, 0xC55C08C0, - 0xCD800041, 0xCDC008C0, 0x80000048, 0xCD400000, 0x80000038, 0xC55900C0, 0xC55C1840, 0xCD8000C1, - 0xCDC01840, 0x80000010, 0xC55A0080, 0xC55C1080, 0xCD800081, 0xCDC01080, 0x9D000000, 0x00000000, - 0x00000000, 0x00000000, 0x59540002, 0x6994E018, 0x61C0C008, 0x4194A000, 0x5D940040, 0x8800FFFA, - 0xC5940000, 0x9D000000, 0xCD400000, 0x00000000, 0x00000000, 0x9D000000, 0x4158A000, 0xCD400000, - 0x00000000, -}; - -static unsigned int firmware_binary_data[] = { -}; - - -#endif // IFXMIPS_ATM_FW_DANUBE_H diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_common.h b/package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_common.h deleted file mode 100644 index a5f59b8c40..0000000000 --- a/package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_common.h +++ /dev/null @@ -1,364 +0,0 @@ -#ifndef IFXMIPS_ATM_FW_REGS_COMMON_H -#define IFXMIPS_ATM_FW_REGS_COMMON_H - - - -#if defined(CONFIG_DANUBE) - #include "ifxmips_atm_fw_regs_danube.h" -#elif defined(CONFIG_AMAZON_SE) - #include "ifxmips_atm_fw_regs_amazon_se.h" -#elif defined(CONFIG_AR9) - #include "ifxmips_atm_fw_regs_ar9.h" -#elif defined(CONFIG_VR9) - #include "ifxmips_atm_fw_regs_vr9.h" -#else - #error Platform is not specified! -#endif - - - -/* - * PPE ATM Cell Header - */ -#if defined(__BIG_ENDIAN) - struct uni_cell_header { - unsigned int gfc :4; - unsigned int vpi :8; - unsigned int vci :16; - unsigned int pti :3; - unsigned int clp :1; - }; -#else - struct uni_cell_header { - unsigned int clp :1; - unsigned int pti :3; - unsigned int vci :16; - unsigned int vpi :8; - unsigned int gfc :4; - }; -#endif // defined(__BIG_ENDIAN) - -/* - * Inband Header and Trailer - */ -#if defined(__BIG_ENDIAN) - struct rx_inband_trailer { - /* 0 - 3h */ - unsigned int uu :8; - unsigned int cpi :8; - unsigned int stw_res1:4; - unsigned int stw_clp :1; - unsigned int stw_ec :1; - unsigned int stw_uu :1; - unsigned int stw_cpi :1; - unsigned int stw_ovz :1; - unsigned int stw_mfl :1; - unsigned int stw_usz :1; - unsigned int stw_crc :1; - unsigned int stw_il :1; - unsigned int stw_ra :1; - unsigned int stw_res2:2; - /* 4 - 7h */ - unsigned int gfc :4; - unsigned int vpi :8; - unsigned int vci :16; - unsigned int pti :3; - unsigned int clp :1; - }; - - struct tx_inband_header { - /* 0 - 3h */ - unsigned int gfc :4; - unsigned int vpi :8; - unsigned int vci :16; - unsigned int pti :3; - unsigned int clp :1; - /* 4 - 7h */ - unsigned int uu :8; - unsigned int cpi :8; - unsigned int pad :8; - unsigned int res1 :8; - }; -#else - struct rx_inband_trailer { - /* 0 - 3h */ - unsigned int stw_res2:2; - unsigned int stw_ra :1; - unsigned int stw_il :1; - unsigned int stw_crc :1; - unsigned int stw_usz :1; - unsigned int stw_mfl :1; - unsigned int stw_ovz :1; - unsigned int stw_cpi :1; - unsigned int stw_uu :1; - unsigned int stw_ec :1; - unsigned int stw_clp :1; - unsigned int stw_res1:4; - unsigned int cpi :8; - unsigned int uu :8; - /* 4 - 7h */ - unsigned int clp :1; - unsigned int pti :3; - unsigned int vci :16; - unsigned int vpi :8; - unsigned int gfc :4; - }; - - struct tx_inband_header { - /* 0 - 3h */ - unsigned int clp :1; - unsigned int pti :3; - unsigned int vci :16; - unsigned int vpi :8; - unsigned int gfc :4; - /* 4 - 7h */ - unsigned int res1 :8; - unsigned int pad :8; - unsigned int cpi :8; - unsigned int uu :8; - }; -#endif // defined(__BIG_ENDIAN) - -/* - * MIB Table Maintained by Firmware - */ -struct wan_mib_table { - u32 res1; - u32 wrx_drophtu_cell; - u32 wrx_dropdes_pdu; - u32 wrx_correct_pdu; - u32 wrx_err_pdu; - u32 wrx_dropdes_cell; - u32 wrx_correct_cell; - u32 wrx_err_cell; - u32 wrx_total_byte; - u32 res2; - u32 wtx_total_pdu; - u32 wtx_total_cell; - u32 wtx_total_byte; -}; - -/* - * Host-PPE Communication Data Structure - */ - -#if defined(__BIG_ENDIAN) - struct wrx_queue_config { - /* 0h */ - unsigned int res2 :27; - unsigned int dmach :4; - unsigned int errdp :1; - /* 1h */ - unsigned int oversize :16; - unsigned int undersize :16; - /* 2h */ - unsigned int res1 :16; - unsigned int mfs :16; - /* 3h */ - unsigned int uumask :8; - unsigned int cpimask :8; - unsigned int uuexp :8; - unsigned int cpiexp :8; - }; - - struct wtx_port_config { - unsigned int res1 :27; - unsigned int qid :4; - unsigned int qsben :1; - }; - - struct wtx_queue_config { - unsigned int res1 :25; - unsigned int sbid :1; - unsigned int res2 :3; - unsigned int type :2; - unsigned int qsben :1; - }; - - struct wrx_dma_channel_config { - /* 0h */ - unsigned int res1 :1; - unsigned int mode :2; - unsigned int rlcfg :1; - unsigned int desba :28; - /* 1h */ - unsigned int chrl :16; - unsigned int clp1th :16; - /* 2h */ - unsigned int deslen :16; - unsigned int vlddes :16; - }; - - struct wtx_dma_channel_config { - /* 0h */ - unsigned int res2 :1; - unsigned int mode :2; - unsigned int res3 :1; - unsigned int desba :28; - /* 1h */ - unsigned int res1 :32; - /* 2h */ - unsigned int deslen :16; - unsigned int vlddes :16; - }; - - struct htu_entry { - unsigned int res1 :1; - unsigned int clp :1; - unsigned int pid :2; - unsigned int vpi :8; - unsigned int vci :16; - unsigned int pti :3; - unsigned int vld :1; - }; - - struct htu_mask { - unsigned int set :1; - unsigned int clp :1; - unsigned int pid_mask :2; - unsigned int vpi_mask :8; - unsigned int vci_mask :16; - unsigned int pti_mask :3; - unsigned int clear :1; - }; - - struct htu_result { - unsigned int res1 :12; - unsigned int cellid :4; - unsigned int res2 :5; - unsigned int type :1; - unsigned int ven :1; - unsigned int res3 :5; - unsigned int qid :4; - }; - - struct rx_descriptor { - /* 0 - 3h */ - unsigned int own :1; - unsigned int c :1; - unsigned int sop :1; - unsigned int eop :1; - unsigned int res1 :3; - unsigned int byteoff :2; - unsigned int res2 :2; - unsigned int id :4; - unsigned int err :1; - unsigned int datalen :16; - /* 4 - 7h */ - unsigned int res3 :4; - unsigned int dataptr :28; - }; - - struct tx_descriptor { - /* 0 - 3h */ - unsigned int own :1; - unsigned int c :1; - unsigned int sop :1; - unsigned int eop :1; - unsigned int byteoff :5; - unsigned int res1 :5; - unsigned int iscell :1; - unsigned int clp :1; - unsigned int datalen :16; - /* 4 - 7h */ - unsigned int res2 :4; - unsigned int dataptr :28; - }; -#else - struct wrx_queue_config { - /* 0h */ - unsigned int errdp :1; - unsigned int dmach :4; - unsigned int res2 :27; - /* 1h */ - unsigned int undersize :16; - unsigned int oversize :16; - /* 2h */ - unsigned int mfs :16; - unsigned int res1 :16; - /* 3h */ - unsigned int cpiexp :8; - unsigned int uuexp :8; - unsigned int cpimask :8; - unsigned int uumask :8; - }; - - struct wtx_port_config { - unsigned int qsben :1; - unsigned int qid :4; - unsigned int res1 :27; - }; - - struct wtx_queue_config { - unsigned int qsben :1; - unsigned int type :2; - unsigned int res2 :3; - unsigned int sbid :1; - unsigned int res1 :25; - }; - - struct wrx_dma_channel_config - { - /* 0h */ - unsigned int desba :28; - unsigned int rlcfg :1; - unsigned int mode :2; - unsigned int res1 :1; - /* 1h */ - unsigned int clp1th :16; - unsigned int chrl :16; - /* 2h */ - unsigned int vlddes :16; - unsigned int deslen :16; - }; - - struct wtx_dma_channel_config { - /* 0h */ - unsigned int desba :28; - unsigned int res3 :1; - unsigned int mode :2; - unsigned int res2 :1; - /* 1h */ - unsigned int res1 :32; - /* 2h */ - unsigned int vlddes :16; - unsigned int deslen :16; - }; - - struct rx_descriptor { - /* 4 - 7h */ - unsigned int dataptr :28; - unsigned int res3 :4; - /* 0 - 3h */ - unsigned int datalen :16; - unsigned int err :1; - unsigned int id :4; - unsigned int res2 :2; - unsigned int byteoff :2; - unsigned int res1 :3; - unsigned int eop :1; - unsigned int sop :1; - unsigned int c :1; - unsigned int own :1; - }; - - struct tx_descriptor { - /* 4 - 7h */ - unsigned int dataptr :28; - unsigned int res2 :4; - /* 0 - 3h */ - unsigned int datalen :16; - unsigned int clp :1; - unsigned int iscell :1; - unsigned int res1 :5; - unsigned int byteoff :5; - unsigned int eop :1; - unsigned int sop :1; - unsigned int c :1; - unsigned int own :1; - }; -#endif // defined(__BIG_ENDIAN) - - - -#endif // IFXMIPS_ATM_FW_REGS_COMMON_H diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_danube.h b/package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_danube.h deleted file mode 100644 index c0dfc6a2e0..0000000000 --- a/package/ifxmips-dsl-api/src/ifxmips_atm_fw_regs_danube.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef IFXMIPS_ATM_FW_REGS_DANUBE_H -#define IFXMIPS_ATM_FW_REGS_DANUBE_H - - - -/* - * Host-PPE Communication Data Address Mapping - */ -#define FW_VER_ID SB_BUFFER(0x2001) -#define CFG_WRX_HTUTS SB_BUFFER(0x2400) /* WAN RX HTU Table Size, must be configured before enable PPE firmware. */ -#define CFG_WRX_QNUM SB_BUFFER(0x2401) /* WAN RX Queue Number */ -#define CFG_WRX_DCHNUM SB_BUFFER(0x2402) /* WAN RX DMA Channel Number, no more than 8, must be configured before enable PPE firmware. */ -#define CFG_WTX_DCHNUM SB_BUFFER(0x2403) /* WAN TX DMA Channel Number, no more than 16, must be configured before enable PPE firmware. */ -#define CFG_WRDES_DELAY SB_BUFFER(0x2404) /* WAN Descriptor Write Delay, must be configured before enable PPE firmware. */ -#define WRX_DMACH_ON SB_BUFFER(0x2405) /* WAN RX DMA Channel Enable, must be configured before enable PPE firmware. */ -#define WTX_DMACH_ON SB_BUFFER(0x2406) /* WAN TX DMA Channel Enable, must be configured before enable PPE firmware. */ -#define WRX_HUNT_BITTH SB_BUFFER(0x2407) /* WAN RX HUNT Threshold, must be between 2 to 8. */ -#define WRX_QUEUE_CONFIG(i) ((struct wrx_queue_config*) SB_BUFFER(0x2500 + (i) * 20)) -#define WRX_DMA_CHANNEL_CONFIG(i) ((struct wrx_dma_channel_config*) SB_BUFFER(0x2640 + (i) * 7)) -#define WTX_PORT_CONFIG(i) ((struct wtx_port_config*) SB_BUFFER(0x2440 + (i))) -#define WTX_QUEUE_CONFIG(i) ((struct wtx_queue_config*) SB_BUFFER(0x2710 + (i) * 27)) -#define WTX_DMA_CHANNEL_CONFIG(i) ((struct wtx_dma_channel_config*) SB_BUFFER(0x2711 + (i) * 27)) -#define WAN_MIB_TABLE ((struct wan_mib_table*) SB_BUFFER(0x2410)) -#define HTU_ENTRY(i) ((struct htu_entry*) SB_BUFFER(0x2000 + (i))) -#define HTU_MASK(i) ((struct htu_mask*) SB_BUFFER(0x2020 + (i))) -#define HTU_RESULT(i) ((struct htu_result*) SB_BUFFER(0x2040 + (i))) - - - -#endif // IFXMIPS_ATM_FW_REGS_DANUBE_H diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_ppe_common.h b/package/ifxmips-dsl-api/src/ifxmips_atm_ppe_common.h deleted file mode 100644 index c9cb38918b..0000000000 --- a/package/ifxmips-dsl-api/src/ifxmips_atm_ppe_common.h +++ /dev/null @@ -1,231 +0,0 @@ -#ifndef IFXMIPS_ATM_PPE_COMMON_H -#define IFXMIPS_ATM_PPE_COMMON_H - - - -#if defined(CONFIG_DANUBE) - #include "ifxmips_atm_ppe_danube.h" -#elif defined(CONFIG_AMAZON_SE) - #include "ifxmips_atm_ppe_amazon_se.h" -#elif defined(CONFIG_AR9) - #include "ifxmips_atm_ppe_ar9.h" -#elif defined(CONFIG_VR9) - #include "ifxmips_atm_ppe_vr9.h" -#else - #error Platform is not specified! -#endif - - - -/* - * Code/Data Memory (CDM) Interface Configuration Register - */ -#define CDM_CFG PPE_REG_ADDR(0x0100) - -#define CDM_CFG_RAM1 GET_BITS(*CDM_CFG, 3, 2) -#define CDM_CFG_RAM0 (*CDM_CFG & (1 << 1)) - -#define CDM_CFG_RAM1_SET(value) SET_BITS(0, 3, 2, value) -#define CDM_CFG_RAM0_SET(value) ((value) ? (1 << 1) : 0) - -/* - * QSB Internal Cell Delay Variation Register - */ -#define QSB_ICDV QSB_CONF_REG_ADDR(0x0007) - -#define QSB_ICDV_TAU GET_BITS(*QSB_ICDV, 5, 0) - -#define QSB_ICDV_TAU_SET(value) SET_BITS(0, 5, 0, value) - -/* - * QSB Scheduler Burst Limit Register - */ -#define QSB_SBL QSB_CONF_REG_ADDR(0x0009) - -#define QSB_SBL_SBL GET_BITS(*QSB_SBL, 3, 0) - -#define QSB_SBL_SBL_SET(value) SET_BITS(0, 3, 0, value) - -/* - * QSB Configuration Register - */ -#define QSB_CFG QSB_CONF_REG_ADDR(0x000A) - -#define QSB_CFG_TSTEPC GET_BITS(*QSB_CFG, 1, 0) - -#define QSB_CFG_TSTEPC_SET(value) SET_BITS(0, 1, 0, value) - -/* - * QSB RAM Transfer Table Register - */ -#define QSB_RTM QSB_CONF_REG_ADDR(0x000B) - -#define QSB_RTM_DM (*QSB_RTM) - -#define QSB_RTM_DM_SET(value) ((value) & 0xFFFFFFFF) - -/* - * QSB RAM Transfer Data Register - */ -#define QSB_RTD QSB_CONF_REG_ADDR(0x000C) - -#define QSB_RTD_TTV (*QSB_RTD) - -#define QSB_RTD_TTV_SET(value) ((value) & 0xFFFFFFFF) - -/* - * QSB RAM Access Register - */ -#define QSB_RAMAC QSB_CONF_REG_ADDR(0x000D) - -#define QSB_RAMAC_RW (*QSB_RAMAC & (1 << 31)) -#define QSB_RAMAC_TSEL GET_BITS(*QSB_RAMAC, 27, 24) -#define QSB_RAMAC_LH (*QSB_RAMAC & (1 << 16)) -#define QSB_RAMAC_TESEL GET_BITS(*QSB_RAMAC, 9, 0) - -#define QSB_RAMAC_RW_SET(value) ((value) ? (1 << 31) : 0) -#define QSB_RAMAC_TSEL_SET(value) SET_BITS(0, 27, 24, value) -#define QSB_RAMAC_LH_SET(value) ((value) ? (1 << 16) : 0) -#define QSB_RAMAC_TESEL_SET(value) SET_BITS(0, 9, 0, value) - -/* - * QSB Queue Scheduling and Shaping Definitions - */ -#define QSB_WFQ_NONUBR_MAX 0x3f00 -#define QSB_WFQ_UBR_BYPASS 0x3fff -#define QSB_TP_TS_MAX 65472 -#define QSB_TAUS_MAX 64512 -#define QSB_GCR_MIN 18 - -/* - * QSB Constant - */ -#define QSB_RAMAC_RW_READ 0 -#define QSB_RAMAC_RW_WRITE 1 - -#define QSB_RAMAC_TSEL_QPT 0x01 -#define QSB_RAMAC_TSEL_SCT 0x02 -#define QSB_RAMAC_TSEL_SPT 0x03 -#define QSB_RAMAC_TSEL_VBR 0x08 - -#define QSB_RAMAC_LH_LOW 0 -#define QSB_RAMAC_LH_HIGH 1 - -#define QSB_QPT_SET_MASK 0x0 -#define QSB_QVPT_SET_MASK 0x0 -#define QSB_SET_SCT_MASK 0x0 -#define QSB_SET_SPT_MASK 0x0 -#define QSB_SET_SPT_SBVALID_MASK 0x7FFFFFFF - -#define QSB_SPT_SBV_VALID (1 << 31) -#define QSB_SPT_PN_SET(value) (((value) & 0x01) ? (1 << 16) : 0) -#define QSB_SPT_INTRATE_SET(value) SET_BITS(0, 13, 0, value) - -/* - * QSB Queue Parameter Table Entry and Queue VBR Parameter Table Entry - */ -#if defined(__BIG_ENDIAN) - union qsb_queue_parameter_table { - struct { - unsigned int res1 :1; - unsigned int vbr :1; - unsigned int wfqf :14; - unsigned int tp :16; - } bit; - u32 dword; - }; - - union qsb_queue_vbr_parameter_table { - struct { - unsigned int taus :16; - unsigned int ts :16; - } bit; - u32 dword; - }; -#else - union qsb_queue_parameter_table { - struct { - unsigned int tp :16; - unsigned int wfqf :14; - unsigned int vbr :1; - unsigned int res1 :1; - } bit; - u32 dword; - }; - - union qsb_queue_vbr_parameter_table { - struct { - unsigned int ts :16; - unsigned int taus :16; - } bit; - u32 dword; - }; -#endif // defined(__BIG_ENDIAN) - -/* - * Mailbox IGU0 Registers - */ -#define MBOX_IGU0_ISRS PPE_REG_ADDR(0x0200) -#define MBOX_IGU0_ISRC PPE_REG_ADDR(0x0201) -#define MBOX_IGU0_ISR PPE_REG_ADDR(0x0202) -#define MBOX_IGU0_IER PPE_REG_ADDR(0x0203) - -#define MBOX_IGU0_ISRS_SET(n) (1 << (n)) -#define MBOX_IGU0_ISRC_CLEAR(n) (1 << (n)) -#define MBOX_IGU0_ISR_ISR(n) (*MBOX_IGU0_ISR & (1 << (n))) -#define MBOX_IGU0_IER_EN(n) (*MBOX_IGU0_IER & (1 << (n))) -#define MBOX_IGU0_IER_EN_SET(n) (1 << (n)) - -/* - * Mailbox IGU1 Registers - */ -#define MBOX_IGU1_ISRS PPE_REG_ADDR(0x0204) -#define MBOX_IGU1_ISRC PPE_REG_ADDR(0x0205) -#define MBOX_IGU1_ISR PPE_REG_ADDR(0x0206) -#define MBOX_IGU1_IER PPE_REG_ADDR(0x0207) - -#define MBOX_IGU1_ISRS_SET(n) (1 << (n)) -#define MBOX_IGU1_ISRC_CLEAR(n) (1 << (n)) -#define MBOX_IGU1_ISR_ISR(n) (*MBOX_IGU1_ISR & (1 << (n))) -#define MBOX_IGU1_IER_EN(n) (*MBOX_IGU1_IER & (1 << (n))) -#define MBOX_IGU1_IER_EN_SET(n) (1 << (n)) - -/* - * Mailbox IGU3 Registers - */ -#define MBOX_IGU3_ISRS PPE_REG_ADDR(0x0214) -#define MBOX_IGU3_ISRC PPE_REG_ADDR(0x0215) -#define MBOX_IGU3_ISR PPE_REG_ADDR(0x0216) -#define MBOX_IGU3_IER PPE_REG_ADDR(0x0217) - -#define MBOX_IGU3_ISRS_SET(n) (1 << (n)) -#define MBOX_IGU3_ISRC_CLEAR(n) (1 << (n)) -#define MBOX_IGU3_ISR_ISR(n) (*MBOX_IGU3_ISR & (1 << (n))) -#define MBOX_IGU3_IER_EN(n) (*MBOX_IGU3_IER & (1 << (n))) -#define MBOX_IGU3_IER_EN_SET(n) (1 << (n)) - -/* - * RTHA/TTHA Registers - */ -#define SFSM_STATE0 PPE_REG_ADDR(0x0410) -#define SFSM_STATE1 PPE_REG_ADDR(0x0411) -#define SFSM_DBA0 PPE_REG_ADDR(0x0412) -#define SFSM_DBA1 PPE_REG_ADDR(0x0413) -#define SFSM_CBA0 PPE_REG_ADDR(0x0414) -#define SFSM_CBA1 PPE_REG_ADDR(0x0415) -#define SFSM_CFG0 PPE_REG_ADDR(0x0416) -#define SFSM_CFG1 PPE_REG_ADDR(0x0417) -#define SFSM_PGCNT0 PPE_REG_ADDR(0x041C) -#define SFSM_PGCNT1 PPE_REG_ADDR(0x041D) -#define FFSM_DBA0 PPE_REG_ADDR(0x0508) -#define FFSM_DBA1 PPE_REG_ADDR(0x0509) -#define FFSM_CFG0 PPE_REG_ADDR(0x050A) -#define FFSM_CFG1 PPE_REG_ADDR(0x050B) -#define FFSM_IDLE_HEAD_BC0 PPE_REG_ADDR(0x050E) -#define FFSM_IDLE_HEAD_BC1 PPE_REG_ADDR(0x050F) -#define FFSM_PGCNT0 PPE_REG_ADDR(0x0514) -#define FFSM_PGCNT1 PPE_REG_ADDR(0x0515) - - - -#endif // IFXMIPS_ATM_PPE_COMMON_H diff --git a/package/ifxmips-dsl-api/src/ifxmips_atm_ppe_danube.h b/package/ifxmips-dsl-api/src/ifxmips_atm_ppe_danube.h deleted file mode 100644 index 3df4e9db0c..0000000000 --- a/package/ifxmips-dsl-api/src/ifxmips_atm_ppe_danube.h +++ /dev/null @@ -1,100 +0,0 @@ -#ifndef IFXMIPS_ATM_PPE_DANUBE_H -#define IFXMIPS_ATM_PPE_DANUBE_H - - - -/* - * FPI Configuration Bus Register and Memory Address Mapping - */ -#define IFX_PPE (KSEG1 | 0x1E180000) -#define PP32_DEBUG_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2))) -#define PPM_INT_REG_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2))) -#define PP32_INTERNAL_RES_ADDR(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2))) -#define CDM_CODE_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2))) -#define PPE_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2))) -#define CDM_DATA_MEMORY(i, x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2))) -#define PPM_INT_UNIT_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2))) -#define PPM_TIMER0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2))) -#define PPM_TASK_IND_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2))) -#define PPS_BRK_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2))) -#define PPM_TIMER1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2))) -#define SB_RAM0_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2))) -#define SB_RAM1_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8400) << 2))) -#define SB_RAM2_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2))) -#define SB_RAM3_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9600) << 2))) -#define QSB_CONF_REG_ADDR(x) ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2))) - -/* - * DWORD-Length of Memory Blocks - */ -#define PP32_DEBUG_REG_DWLEN 0x0030 -#define PPM_INT_REG_DWLEN 0x0010 -#define PP32_INTERNAL_RES_DWLEN 0x00C0 -#define CDM_CODE_MEMORYn_DWLEN(n) ((n) == 0 ? 0x1000 : 0x0800) -#define PPE_REG_DWLEN 0x1000 -#define CDM_DATA_MEMORY_DWLEN CDM_CODE_MEMORYn_DWLEN(1) -#define PPM_INT_UNIT_DWLEN 0x0100 -#define PPM_TIMER0_DWLEN 0x0100 -#define PPM_TASK_IND_REG_DWLEN 0x0100 -#define PPS_BRK_DWLEN 0x0100 -#define PPM_TIMER1_DWLEN 0x0100 -#define SB_RAM0_DWLEN 0x0400 -#define SB_RAM1_DWLEN 0x0800 -#define SB_RAM2_DWLEN 0x0A00 -#define SB_RAM3_DWLEN 0x0400 -#define QSB_CONF_REG_DWLEN 0x0100 - -/* - * PP32 to FPI Address Mapping - */ -#define SB_BUFFER(__sb_addr) ((volatile unsigned int *)((((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x23FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) : \ - (((__sb_addr) >= 0x2400) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2400) : \ - (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x2C00) : \ - (((__sb_addr) >= 0x3600) && ((__sb_addr) <= 0x39FF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3600) : \ - 0)) - -/* - * PP32 Debug Control Register - */ -#define PP32_DBG_CTRL PP32_DEBUG_REG_ADDR(0, 0x0000) - -#define DBG_CTRL_START_SET(value) ((value) ? (1 << 0) : 0) -#define DBG_CTRL_STOP_SET(value) ((value) ? (1 << 1) : 0) -#define DBG_CTRL_STEP_SET(value) ((value) ? (1 << 2) : 0) - -#define PP32_HALT_STAT PP32_DEBUG_REG_ADDR(0, 0x0001) - -#define PP32_BRK_SRC PP32_DEBUG_REG_ADDR(0, 0x0002) - -#define PP32_DBG_PC_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0010 + (i)) -#define PP32_DBG_PC_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x0014 + (i)) -#define PP32_DBG_DATA_MIN(i) PP32_DEBUG_REG_ADDR(0, 0x0018 + (i)) -#define PP32_DBG_DATA_MAX(i) PP32_DEBUG_REG_ADDR(0, 0x001A + (i)) -#define PP32_DBG_DATA_VAL(i) PP32_DEBUG_REG_ADDR(0, 0x001C + (i)) - -#define PP32_DBG_CUR_PC PP32_DEBUG_REG_ADDR(0, 0x0080) - -#define PP32_DBG_TASK_NO PP32_DEBUG_REG_ADDR(0, 0x0081) - -/* - * EMA Registers - */ -#define EMA_CMDCFG PPE_REG_ADDR(0x0A00) -#define EMA_DATACFG PPE_REG_ADDR(0x0A01) -#define EMA_CMDCNT PPE_REG_ADDR(0x0A02) -#define EMA_DATACNT PPE_REG_ADDR(0x0A03) -#define EMA_ISR PPE_REG_ADDR(0x0A04) -#define EMA_IER PPE_REG_ADDR(0x0A05) -#define EMA_CFG PPE_REG_ADDR(0x0A06) -#define EMA_SUBID PPE_REG_ADDR(0x0A07) - -#define EMA_ALIGNMENT 4 - -/* - * Mailbox IGU1 Interrupt - */ -#define PPE_MAILBOX_IGU1_INT INT_NUM_IM2_IRL24 - - - -#endif // IFXMIPS_ATM_PPE_DANUBE_H diff --git a/package/ifxmips-dsl-api/src/ifxmips_mei.c b/package/ifxmips-dsl-api/src/ifxmips_mei.c deleted file mode 100644 index 5651b9f20c..0000000000 --- a/package/ifxmips-dsl-api/src/ifxmips_mei.c +++ /dev/null @@ -1,2998 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2009 - Infineon Technologies AG - Am Campeon 1-12; 81726 Munich, Germany - - For licensing information, see the file 'LICENSE' in the root folder of - this software module. - -******************************************************************************/ - -/*! - \defgroup AMAZON_S_MEI Amazon-S MEI Driver Module - \brief Amazon-S MEI driver module - */ - -/*! - \defgroup Internal Compile Parametere - \ingroup AMAZON_S_MEI - \brief exported functions for other driver use - */ - -/*! - \file amazon_s_mei_bsp.c - \ingroup AMAZON_S_MEI - \brief Amazon-S MEI driver file - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -//#include -#include -#include -#define IFX_MEI_BSP -#include "ifxmips_mei_interface.h" - -#define IFXMIPS_RCU_RST IFX_RCU_RST_REQ -#define IFXMIPS_RCU_RST_REQ_ARC_JTAG IFX_RCU_RST_REQ_ARC_JTAG -#define IFXMIPS_RCU_RST_REQ_DFE IFX_RCU_RST_REQ_DFE -#define IFXMIPS_RCU_RST_REQ_AFE IFX_RCU_RST_REQ_AFE -#define IFXMIPS_FUSE_BASE_ADDR IFX_FUSE_BASE_ADDR -#define IFXMIPS_ICU_IM0_IER IFX_ICU_IM0_IER -#define IFXMIPS_ICU_IM2_IER IFX_ICU_IM2_IER -#define IFXMIPS_MEI_INT IFX_MEI_INT -#define IFXMIPS_MEI_DYING_GASP_INT IFX_MEI_DYING_GASP_INT -#define IFXMIPS_MEI_BASE_ADDR IFX_MEI_SPACE_ACCESS -#define IFXMIPS_PMU_PWDCR IFX_PMU_PWDCR -#define IFXMIPS_MPS_CHIPID IFX_MPS_CHIPID - -#define ifxmips_port_reserve_pin ifx_gpio_pin_reserve -#define ifxmips_port_set_dir_in ifx_gpio_dir_in_set -#define ifxmips_port_clear_altsel0 ifx_gpio_altsel0_set -#define ifxmips_port_clear_altsel1 ifx_gpio_altsel1_clear -#define ifxmips_port_set_open_drain ifx_gpio_open_drain_clear -#define ifxmips_port_free_pin ifx_gpio_pin_free -#define ifxmips_mask_and_ack_irq bsp_mask_and_ack_irq -#define IFXMIPS_MPS_CHIPID_VERSION_GET IFX_MCD_CHIPID_VERSION_GET -#define ifxmips_r32(reg) __raw_readl(reg) -#define ifxmips_w32(val, reg) __raw_writel(val, reg) -#define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg) - -#define IFX_MEI_EMSG(fmt, args...) printk(KERN_ERR "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args) -#define IFX_MEI_DMSG(fmt, args...) printk(KERN_INFO "[%s %d]: " fmt,__FUNCTION__, __LINE__, ## args) - -#ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK -//#define DFE_MEM_TEST -//#define DFE_PING_TEST -#define DFE_ATM_LOOPBACK - -#ifdef DFE_PING_TEST -#include "dsp_xmem_arb_rand_em.h" -#endif - -#ifdef DFE_MEM_TEST -#include "aai_mem_test.h" -#endif - -#ifdef DFE_ATM_LOOPBACK -#include -#endif - -void dfe_loopback_irq_handler (DSL_DEV_Device_t *pDev); - -#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK - -DSL_DEV_Version_t bsp_mei_version = { - major: 5, - minor: 0, - revision:0 -}; -DSL_DEV_HwVersion_t bsp_chip_info; - -#define IFX_MEI_DEVNAME "ifx_mei" -#define BSP_MAX_DEVICES 1 - -DSL_DEV_MeiError_t DSL_BSP_FWDownload (DSL_DEV_Device_t *, const char *, unsigned long, long *, long *); -DSL_DEV_MeiError_t DSL_BSP_Showtime (DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t); -DSL_DEV_MeiError_t DSL_BSP_AdslLedInit (DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t); -//DSL_DEV_MeiError_t DSL_BSP_AdslLedSet (DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedMode_t); -DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess (DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t*, DSL_uint32_t); -DSL_DEV_MeiError_t DSL_BSP_SendCMV (DSL_DEV_Device_t *, u16 *, int, u16 *); - -int DSL_BSP_KernelIoctls (DSL_DEV_Device_t *, unsigned int, unsigned long); - -static DSL_DEV_MeiError_t IFX_MEI_RunAdslModem (DSL_DEV_Device_t *); -static DSL_DEV_MeiError_t IFX_MEI_CpuModeSet (DSL_DEV_Device_t *, DSL_DEV_CpuMode_t); -static DSL_DEV_MeiError_t IFX_MEI_DownloadBootCode (DSL_DEV_Device_t *); -static DSL_DEV_MeiError_t IFX_MEI_ArcJtagEnable (DSL_DEV_Device_t *, int); -static DSL_DEV_MeiError_t IFX_MEI_AdslMailboxIRQEnable (DSL_DEV_Device_t *, int); - -static int IFX_MEI_GetPage (DSL_DEV_Device_t *, u32, u32, u32, u32 *, u32 *); -static int IFX_MEI_BarUpdate (DSL_DEV_Device_t *, int); - -static ssize_t IFX_MEI_Write (DSL_DRV_file_t *, const char *, size_t, loff_t *); -static int IFX_MEI_UserIoctls (DSL_DRV_inode_t *, DSL_DRV_file_t *, unsigned int, unsigned long); -static int IFX_MEI_Open (DSL_DRV_inode_t *, DSL_DRV_file_t *); -static int IFX_MEI_Release (DSL_DRV_inode_t *, DSL_DRV_file_t *); - -void AMAZON_SE_MEI_ARC_MUX_Test(void); - -#ifdef CONFIG_PROC_FS -static int IFX_MEI_ProcRead (struct file *, char *, size_t, loff_t *); -static ssize_t IFX_MEI_ProcWrite (struct file *, const char *, size_t, loff_t *); - -#define PROC_ITEMS 11 -#define MEI_DIRNAME "ifxmips_mei" - -static struct proc_dir_entry *meidir; -static struct file_operations IFX_MEI_ProcOperations = { - read:IFX_MEI_ProcRead, - write:IFX_MEI_ProcWrite, -}; -static reg_entry_t regs[BSP_MAX_DEVICES][PROC_ITEMS]; //total items to be monitored by /proc/mei -#define NUM_OF_REG_ENTRY (sizeof(regs[0])/sizeof(reg_entry_t)) -#endif //CONFIG_PROC_FS - -void IFX_MEI_ARC_MUX_Test(void); - -static int adsl_dummy_ledcallback(void); - -int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL; -EXPORT_SYMBOL(ifx_mei_atm_showtime_enter); - -int (*ifx_mei_atm_showtime_exit)(void) = NULL; -EXPORT_SYMBOL(ifx_mei_atm_showtime_exit); - -static int (*g_adsl_ledcallback)(void) = adsl_dummy_ledcallback; - -static unsigned int g_tx_link_rate[2] = {0}; - -static void *g_xdata_addr = NULL; - -static u32 *mei_arc_swap_buff = NULL; // holding swap pages - -extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr); -#define MEI_MASK_AND_ACK_IRQ ifxmips_mask_and_ack_irq - -static int dev_major = 105; - -static struct file_operations bsp_mei_operations = { - owner:THIS_MODULE, - open:IFX_MEI_Open, - release:IFX_MEI_Release, - write:IFX_MEI_Write, - ioctl:IFX_MEI_UserIoctls, -}; - -static DSL_DEV_Device_t dsl_devices[BSP_MAX_DEVICES]; - -static ifx_mei_device_private_t - sDanube_Mei_Private[BSP_MAX_DEVICES]; - -static DSL_BSP_EventCallBack_t dsl_bsp_event_callback[DSL_BSP_CB_LAST + 1]; - -/** - * Write a value to register - * This function writes a value to danube register - * - * \param ul_address The address to write - * \param ul_data The value to write - * \ingroup Internal - */ -static void -IFX_MEI_LongWordWrite (u32 ul_address, u32 ul_data) -{ - IFX_MEI_WRITE_REGISTER_L (ul_data, ul_address); - wmb(); - return; -} - -/** - * Write a value to register - * This function writes a value to danube register - * - * \param pDev the device pointer - * \param ul_address The address to write - * \param ul_data The value to write - * \ingroup Internal - */ -static void -IFX_MEI_LongWordWriteOffset (DSL_DEV_Device_t * pDev, u32 ul_address, - u32 ul_data) -{ - IFX_MEI_WRITE_REGISTER_L (ul_data, pDev->base_address + ul_address); - wmb(); - return; -} - -/** - * Read the danube register - * This function read the value from danube register - * - * \param ul_address The address to write - * \param pul_data Pointer to the data - * \ingroup Internal - */ -static void -IFX_MEI_LongWordRead (u32 ul_address, u32 * pul_data) -{ - *pul_data = IFX_MEI_READ_REGISTER_L (ul_address); - rmb(); - return; -} - -/** - * Read the danube register - * This function read the value from danube register - * - * \param pDev the device pointer - * \param ul_address The address to write - * \param pul_data Pointer to the data - * \ingroup Internal - */ -static void -IFX_MEI_LongWordReadOffset (DSL_DEV_Device_t * pDev, u32 ul_address, - u32 * pul_data) -{ - *pul_data = IFX_MEI_READ_REGISTER_L (pDev->base_address + ul_address); - rmb(); - return; -} - -/** - * Write several DWORD datas to ARC memory via ARC DMA interface - * This function writes several DWORD datas to ARC memory via DMA interface. - * - * \param pDev the device pointer - * \param destaddr The address to write - * \param databuff Pointer to the data buffer - * \param databuffsize Number of DWORDs to write - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_DMAWrite (DSL_DEV_Device_t * pDev, u32 destaddr, - u32 * databuff, u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - - if (destaddr & 3) - return DSL_DEV_MEI_ERR_FAILURE; - - // Set the write transfer address - IFX_MEI_LongWordWriteOffset (pDev, ME_DX_AD, destaddr); - - // Write the data pushed across DMA - while (databuffsize--) { - temp = *p; - if (destaddr == MEI_TO_ARC_MAILBOX) - MEI_HALF_WORD_SWAP (temp); - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DX_DATA, temp); - p++; - } - - return DSL_DEV_MEI_ERR_SUCCESS; - -} - -/** - * Read several DWORD datas from ARC memory via ARC DMA interface - * This function reads several DWORD datas from ARC memory via DMA interface. - * - * \param pDev the device pointer - * \param srcaddr The address to read - * \param databuff Pointer to the data buffer - * \param databuffsize Number of DWORDs to read - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_DMARead (DSL_DEV_Device_t * pDev, u32 srcaddr, u32 * databuff, - u32 databuffsize) -{ - u32 *p = databuff; - u32 temp; - - if (srcaddr & 3) - return DSL_DEV_MEI_ERR_FAILURE; - - // Set the read transfer address - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DX_AD, srcaddr); - - // Read the data popped across DMA - while (databuffsize--) { - IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DX_DATA, &temp); - if (databuff == (u32 *) DSL_DEV_PRIVATE(pDev)->CMV_RxMsg) // swap half word - MEI_HALF_WORD_SWAP (temp); - *p = temp; - p++; - } - - return DSL_DEV_MEI_ERR_SUCCESS; - -} - -/** - * Switch the ARC control mode - * This function switchs the ARC control mode to JTAG mode or MEI mode - * - * \param pDev the device pointer - * \param mode The mode want to switch: JTAG_MASTER_MODE or MEI_MASTER_MODE. - * \ingroup Internal - */ -static void -IFX_MEI_ControlModeSet (DSL_DEV_Device_t * pDev, int mode) -{ - u32 temp = 0x0; - - IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DBG_MASTER, &temp); - switch (mode) { - case JTAG_MASTER_MODE: - temp &= ~(HOST_MSTR); - break; - case MEI_MASTER_MODE: - temp |= (HOST_MSTR); - break; - default: - IFX_MEI_EMSG ("IFX_MEI_ControlModeSet: unkonwn mode [%d]\n", mode); - return; - } - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_MASTER, temp); -} - -/** - * Disable ARC to MEI interrupt - * - * \param pDev the device pointer - * \ingroup Internal - */ -static void -IFX_MEI_IRQDisable (DSL_DEV_Device_t * pDev) -{ - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_MASK, 0x0); -} - -/** - * Eable ARC to MEI interrupt - * - * \param pDev the device pointer - * \ingroup Internal - */ -static void -IFX_MEI_IRQEnable (DSL_DEV_Device_t * pDev) -{ - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_MASK, MSGAV_EN); -} - -/** - * Poll for transaction complete signal - * This function polls and waits for transaction complete signal. - * - * \param pDev the device pointer - * \ingroup Internal - */ -static void -meiPollForDbgDone (DSL_DEV_Device_t * pDev) -{ - u32 query = 0; - int i = 0; - - while (i < WHILE_DELAY) { - IFX_MEI_LongWordReadOffset (pDev, (u32) ME_ARC2ME_STAT, &query); - query &= (ARC_TO_MEI_DBG_DONE); - if (query) - break; - i++; - if (i == WHILE_DELAY) { - IFX_MEI_EMSG ("PollforDbg fail!\n"); - } - } - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_DBG_DONE); // to clear this interrupt -} - -/** - * ARC Debug Memory Access for a single DWORD reading. - * This function used for direct, address-based access to ARC memory. - * - * \param pDev the device pointer - * \param DEC_mode ARC memory space to used - * \param address Address to read - * \param data Pointer to data - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -_IFX_MEI_DBGLongWordRead (DSL_DEV_Device_t * pDev, u32 DEC_mode, - u32 address, u32 * data) -{ - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DECODE, DEC_mode); - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_RD_AD, address); - meiPollForDbgDone (pDev); - IFX_MEI_LongWordReadOffset (pDev, (u32) ME_DBG_DATA, data); - return DSL_DEV_MEI_ERR_SUCCESS; -} - -/** - * ARC Debug Memory Access for a single DWORD writing. - * This function used for direct, address-based access to ARC memory. - * - * \param pDev the device pointer - * \param DEC_mode ARC memory space to used - * \param address The address to write - * \param data The data to write - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -_IFX_MEI_DBGLongWordWrite (DSL_DEV_Device_t * pDev, u32 DEC_mode, - u32 address, u32 data) -{ - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DECODE, DEC_mode); - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_WR_AD, address); - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_DBG_DATA, data); - meiPollForDbgDone (pDev); - return DSL_DEV_MEI_ERR_SUCCESS; -} - -/** - * ARC Debug Memory Access for writing. - * This function used for direct, address-based access to ARC memory. - * - * \param pDev the device pointer - * \param destaddr The address to read - * \param databuffer Pointer to data - * \param databuffsize The number of DWORDs to read - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ - -static DSL_DEV_MeiError_t -IFX_MEI_DebugWrite (DSL_DEV_Device_t * pDev, u32 destaddr, - u32 * databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - - // Open the debug port before DMP memory write - IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE); - - // For the requested length, write the address and write the data - address = destaddr; - buffer = databuff; - for (i = 0; i < databuffsize; i++) { - temp = *buffer; - _IFX_MEI_DBGLongWordWrite (pDev, ME_DBG_DECODE_DMP1_MASK, address, temp); - address += 4; - buffer++; - } - - // Close the debug port after DMP memory write - IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE); - - return DSL_DEV_MEI_ERR_SUCCESS; -} - -/** - * ARC Debug Memory Access for reading. - * This function used for direct, address-based access to ARC memory. - * - * \param pDev the device pointer - * \param srcaddr The address to read - * \param databuffer Pointer to data - * \param databuffsize The number of DWORDs to read - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_DebugRead (DSL_DEV_Device_t * pDev, u32 srcaddr, u32 * databuff, u32 databuffsize) -{ - u32 i; - u32 temp = 0x0; - u32 address = 0x0; - u32 *buffer = 0x0; - - // Open the debug port before DMP memory read - IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE); - - // For the requested length, write the address and read the data - address = srcaddr; - buffer = databuff; - for (i = 0; i < databuffsize; i++) { - _IFX_MEI_DBGLongWordRead (pDev, ME_DBG_DECODE_DMP1_MASK, address, &temp); - *buffer = temp; - address += 4; - buffer++; - } - - // Close the debug port after DMP memory read - IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE); - - return DSL_DEV_MEI_ERR_SUCCESS; -} - -/** - * Send a message to ARC MailBox. - * This function sends a message to ARC Mailbox via ARC DMA interface. - * - * \param pDev the device pointer - * \param msgsrcbuffer Pointer to message. - * \param msgsize The number of words to write. - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_MailboxWrite (DSL_DEV_Device_t * pDev, u16 * msgsrcbuffer, - u16 msgsize) -{ - int i; - u32 arc_mailbox_status = 0x0; - u32 temp = 0; - DSL_DEV_MeiError_t meiMailboxError = DSL_DEV_MEI_ERR_SUCCESS; - - // Write to mailbox - meiMailboxError = - IFX_MEI_DMAWrite (pDev, MEI_TO_ARC_MAILBOX, (u32 *) msgsrcbuffer, msgsize / 2); - meiMailboxError = - IFX_MEI_DMAWrite (pDev, MEI_TO_ARC_MAILBOXR, (u32 *) (&temp), 1); - - // Notify arc that mailbox write completed - DSL_DEV_PRIVATE(pDev)->cmv_waiting = 1; - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV); - - i = 0; - while (i < WHILE_DELAY) { // wait for ARC to clear the bit - IFX_MEI_LongWordReadOffset (pDev, (u32) ME_ME2ARC_INT, &arc_mailbox_status); - if ((arc_mailbox_status & MEI_TO_ARC_MSGAV) != MEI_TO_ARC_MSGAV) - break; - i++; - if (i == WHILE_DELAY) { - IFX_MEI_EMSG (">>> Timeout waiting for ARC to clear MEI_TO_ARC_MSGAV!!!" - " MEI_TO_ARC message size = %d DWORDs <<<\n", msgsize/2); - meiMailboxError = DSL_DEV_MEI_ERR_FAILURE; - } - } - - return meiMailboxError; -} - -/** - * Read a message from ARC MailBox. - * This function reads a message from ARC Mailbox via ARC DMA interface. - * - * \param pDev the device pointer - * \param msgsrcbuffer Pointer to message. - * \param msgsize The number of words to read - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_MailboxRead (DSL_DEV_Device_t * pDev, u16 * msgdestbuffer, - u16 msgsize) -{ - DSL_DEV_MeiError_t meiMailboxError = DSL_DEV_MEI_ERR_SUCCESS; - // Read from mailbox - meiMailboxError = - IFX_MEI_DMARead (pDev, ARC_TO_MEI_MAILBOX, (u32 *) msgdestbuffer, msgsize / 2); - - // Notify arc that mailbox read completed - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV); - - return meiMailboxError; -} - -/** - * Download boot pages to ARC. - * This function downloads boot pages to ARC. - * - * \param pDev the device pointer - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_DownloadBootPages (DSL_DEV_Device_t * pDev) -{ - int boot_loop; - int page_size; - u32 dest_addr; - - /* - ** DMA the boot code page(s) - */ - - for (boot_loop = 1; - boot_loop < - (DSL_DEV_PRIVATE(pDev)->img_hdr-> count); boot_loop++) { - if ((DSL_DEV_PRIVATE(pDev)-> img_hdr->page[boot_loop].p_size) & BOOT_FLAG) { - page_size = IFX_MEI_GetPage (pDev, boot_loop, - GET_PROG, MAXSWAPSIZE, - mei_arc_swap_buff, - &dest_addr); - if (page_size > 0) { - IFX_MEI_DMAWrite (pDev, dest_addr, - mei_arc_swap_buff, - page_size); - } - } - if ((DSL_DEV_PRIVATE(pDev)-> img_hdr->page[boot_loop].d_size) & BOOT_FLAG) { - page_size = IFX_MEI_GetPage (pDev, boot_loop, - GET_DATA, MAXSWAPSIZE, - mei_arc_swap_buff, - &dest_addr); - if (page_size > 0) { - IFX_MEI_DMAWrite (pDev, dest_addr, - mei_arc_swap_buff, - page_size); - } - } - } - return DSL_DEV_MEI_ERR_SUCCESS; -} - -/** - * Initial efuse rar. - **/ -static void -IFX_MEI_FuseInit (DSL_DEV_Device_t * pDev) -{ - u32 data = 0; - IFX_MEI_DMAWrite (pDev, IRAM0_BASE, &data, 1); - IFX_MEI_DMAWrite (pDev, IRAM0_BASE + 4, &data, 1); - IFX_MEI_DMAWrite (pDev, IRAM1_BASE, &data, 1); - IFX_MEI_DMAWrite (pDev, IRAM1_BASE + 4, &data, 1); - IFX_MEI_DMAWrite (pDev, BRAM_BASE, &data, 1); - IFX_MEI_DMAWrite (pDev, BRAM_BASE + 4, &data, 1); - IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE, &data, 1); - IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE + 4, &data, 1); -} - -/** - * efuse rar program - **/ -static void -IFX_MEI_FuseProg (DSL_DEV_Device_t * pDev) -{ - u32 reg_data, fuse_value; - int i = 0; - - IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data); - while ((reg_data & 0x10000000) == 0) { - IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data); - i++; - /* 0x4000 translate to about 16 ms@111M, so should be enough */ - if (i == 0x4000) - return; - } - // STEP a: Prepare memory for external accesses - // Write fuse_en bit24 - IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data); - IFX_MEI_LongWordWrite ((u32) IFXMIPS_RCU_RST, reg_data | (1 << 24)); - - IFX_MEI_FuseInit (pDev); - for (i = 0; i < 4; i++) { - IFX_MEI_LongWordRead ((u32) (IFXMIPS_FUSE_BASE_ADDR) + i * 4, &fuse_value); - switch (fuse_value & 0xF0000) { - case 0x80000: - reg_data = ((fuse_value & RX_DILV_ADDR_BIT_MASK) | - (RX_DILV_ADDR_BIT_MASK + 0x1)); - IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE, ®_data, 1); - break; - case 0x90000: - reg_data = ((fuse_value & RX_DILV_ADDR_BIT_MASK) | - (RX_DILV_ADDR_BIT_MASK + 0x1)); - IFX_MEI_DMAWrite (pDev, ADSL_DILV_BASE + 4, ®_data, 1); - break; - case 0xA0000: - reg_data = ((fuse_value & IRAM0_ADDR_BIT_MASK) | - (IRAM0_ADDR_BIT_MASK + 0x1)); - IFX_MEI_DMAWrite (pDev, IRAM0_BASE, ®_data, 1); - break; - case 0xB0000: - reg_data = ((fuse_value & IRAM0_ADDR_BIT_MASK) | - (IRAM0_ADDR_BIT_MASK + 0x1)); - IFX_MEI_DMAWrite (pDev, IRAM0_BASE + 4, ®_data, 1); - break; - case 0xC0000: - reg_data = ((fuse_value & IRAM1_ADDR_BIT_MASK) | - (IRAM1_ADDR_BIT_MASK + 0x1)); - IFX_MEI_DMAWrite (pDev, IRAM1_BASE, ®_data, 1); - break; - case 0xD0000: - reg_data = ((fuse_value & IRAM1_ADDR_BIT_MASK) | - (IRAM1_ADDR_BIT_MASK + 0x1)); - IFX_MEI_DMAWrite (pDev, IRAM1_BASE + 4, ®_data, 1); - break; - case 0xE0000: - reg_data = ((fuse_value & BRAM_ADDR_BIT_MASK) | - (BRAM_ADDR_BIT_MASK + 0x1)); - IFX_MEI_DMAWrite (pDev, BRAM_BASE, ®_data, 1); - break; - case 0xF0000: - reg_data = ((fuse_value & BRAM_ADDR_BIT_MASK) | - (BRAM_ADDR_BIT_MASK + 0x1)); - IFX_MEI_DMAWrite (pDev, BRAM_BASE + 4, ®_data, 1); - break; - default: // PPE efuse - break; - } - } - IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data); - IFX_MEI_LongWordWrite ((u32) IFXMIPS_RCU_RST, reg_data & ~(1 << 24)); - IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data); -} - -/** - * Enable DFE Clock - * This function enables DFE Clock - * - * \param pDev the device pointer - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_EnableCLK (DSL_DEV_Device_t * pDev) -{ - u32 arc_debug_data = 0; - IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE); - //enable ac_clk signal - _IFX_MEI_DBGLongWordRead (pDev, ME_DBG_DECODE_DMP1_MASK, - CRI_CCR0, &arc_debug_data); - arc_debug_data |= ACL_CLK_MODE_ENABLE; - _IFX_MEI_DBGLongWordWrite (pDev, ME_DBG_DECODE_DMP1_MASK, - CRI_CCR0, arc_debug_data); - IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE); - return DSL_DEV_MEI_ERR_SUCCESS; -} - -/** - * Halt the ARC. - * This function halts the ARC. - * - * \param pDev the device pointer - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_HaltArc (DSL_DEV_Device_t * pDev) -{ - u32 arc_debug_data = 0x0; - - // Switch arc control from JTAG mode to MEI mode - IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE); - _IFX_MEI_DBGLongWordRead (pDev, MEI_DEBUG_DEC_AUX_MASK, - ARC_DEBUG, &arc_debug_data); - arc_debug_data |= ARC_DEBUG_HALT; - _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, - ARC_DEBUG, arc_debug_data); - // Switch arc control from MEI mode to JTAG mode - IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE); - - MEI_WAIT (10); - - return DSL_DEV_MEI_ERR_SUCCESS; -} - -/** - * Run the ARC. - * This function runs the ARC. - * - * \param pDev the device pointer - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_RunArc (DSL_DEV_Device_t * pDev) -{ - u32 arc_debug_data = 0x0; - - // Switch arc control from JTAG mode to MEI mode- write '1' to bit0 - IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE); - _IFX_MEI_DBGLongWordRead (pDev, MEI_DEBUG_DEC_AUX_MASK, - AUX_STATUS, &arc_debug_data); - - // Write debug data reg with content ANDd with 0xFDFFFFFF (halt bit cleared) - arc_debug_data &= ~ARC_AUX_HALT; - _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, - AUX_STATUS, arc_debug_data); - - // Switch arc control from MEI mode to JTAG mode- write '0' to bit0 - IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE); - // Enable mask for arc codeswap interrupts - IFX_MEI_IRQEnable (pDev); - - return DSL_DEV_MEI_ERR_SUCCESS; - -} - -/** - * Reset the ARC. - * This function resets the ARC. - * - * \param pDev the device pointer - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_ResetARC (DSL_DEV_Device_t * pDev) -{ - u32 arc_debug_data = 0; - - IFX_MEI_HaltArc (pDev); - - IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, &arc_debug_data); - IFX_MEI_LongWordWrite ((u32) IFXMIPS_RCU_RST, - arc_debug_data | IFXMIPS_RCU_RST_REQ_DFE | IFXMIPS_RCU_RST_REQ_AFE); - - // reset ARC - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_RST_CTRL, MEI_SOFT_RESET); - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_RST_CTRL, 0); - - IFX_MEI_IRQDisable (pDev); - - IFX_MEI_EnableCLK (pDev); - -#if 0 - // reset part of PPE - *(unsigned long *) (BSP_PPE32_SRST) = 0xC30; - *(unsigned long *) (BSP_PPE32_SRST) = 0xFFF; -#endif - - DSL_DEV_PRIVATE(pDev)->modem_ready = 0; - - return DSL_DEV_MEI_ERR_SUCCESS; -} - -DSL_DEV_MeiError_t -DSL_BSP_Showtime (DSL_DEV_Device_t * dev, DSL_uint32_t rate_fast, DSL_uint32_t rate_intl) -{ - struct port_cell_info port_cell = {0}; - - IFX_MEI_EMSG ("Datarate US intl = %d, fast = %d\n", (int)rate_intl, - (int)rate_fast); - - if ( rate_fast ) - g_tx_link_rate[0] = rate_fast / (53 * 8); - if ( rate_intl ) - g_tx_link_rate[1] = rate_intl / (53 * 8); - - if ( g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 ) { - IFX_MEI_EMSG ("Got rate fail.\n"); - } - - if ( ifx_mei_atm_showtime_enter ) - { - port_cell.port_num = 2; - port_cell.tx_link_rate[0] = g_tx_link_rate[0]; - port_cell.tx_link_rate[1] = g_tx_link_rate[1]; - ifx_mei_atm_showtime_enter(&port_cell, g_xdata_addr); - } - else - { - IFX_MEI_EMSG("no hookup from ATM driver to set cell rate\n"); - } - - return DSL_DEV_MEI_ERR_SUCCESS; -}; - -/** - * Reset/halt/run the DFE. - * This function provide operations to reset/halt/run the DFE. - * - * \param pDev the device pointer - * \param mode which operation want to do - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_CpuModeSet (DSL_DEV_Device_t *pDev, - DSL_DEV_CpuMode_t mode) -{ - DSL_DEV_MeiError_t err_ret = DSL_DEV_MEI_ERR_FAILURE; - switch (mode) { - case DSL_CPU_HALT: - err_ret = IFX_MEI_HaltArc (pDev); - break; - case DSL_CPU_RUN: - err_ret = IFX_MEI_RunArc (pDev); - break; - case DSL_CPU_RESET: - err_ret = IFX_MEI_ResetARC (pDev); - break; - default: - break; - } - return err_ret; -} - -/** - * Accress DFE memory. - * This function provide a way to access DFE memory; - * - * \param pDev the device pointer - * \param type read or write - * \param destaddr destination address - * \param databuff pointer to hold data - * \param databuffsize size want to read/write - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -DSL_DEV_MeiError_t -DSL_BSP_MemoryDebugAccess (DSL_DEV_Device_t * pDev, - DSL_BSP_MemoryAccessType_t type, - DSL_uint32_t destaddr, DSL_uint32_t *databuff, - DSL_uint32_t databuffsize) -{ - DSL_DEV_MeiError_t meierr = DSL_DEV_MEI_ERR_SUCCESS; - switch (type) { - case DSL_BSP_MEMORY_READ: - meierr = IFX_MEI_DebugRead (pDev, (u32)destaddr, (u32*)databuff, (u32)databuffsize); - break; - case DSL_BSP_MEMORY_WRITE: - meierr = IFX_MEI_DebugWrite (pDev, (u32)destaddr, (u32*)databuff, (u32)databuffsize); - break; - } - return DSL_DEV_MEI_ERR_SUCCESS; -}; - -/** - * Download boot code to ARC. - * This function downloads boot code to ARC. - * - * \param pDev the device pointer - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_DownloadBootCode (DSL_DEV_Device_t *pDev) -{ - IFX_MEI_IRQDisable (pDev); - - IFX_MEI_EnableCLK (pDev); - - IFX_MEI_FuseProg (pDev); //program fuse rar - - IFX_MEI_DownloadBootPages (pDev); - - return DSL_DEV_MEI_ERR_SUCCESS; -}; - -/** - * Enable Jtag debugger interface - * This function setups mips gpio to enable jtag debugger - * - * \param pDev the device pointer - * \param enable enable or disable - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_ArcJtagEnable (DSL_DEV_Device_t *dev, int enable) -{ - int meierr=0; - u32 reg_data; - - switch (enable) { - case 1: - //reserve gpio 9, 10, 11, 14, 19 for ARC JTAG - ifxmips_port_reserve_pin (0, 9); - ifxmips_port_reserve_pin (0, 10); - ifxmips_port_reserve_pin (0, 11); - ifxmips_port_reserve_pin (0, 14); - ifxmips_port_reserve_pin (1, 3); - - ifxmips_port_set_dir_in(0, 11); - ifxmips_port_clear_altsel0(0, 11); - ifxmips_port_clear_altsel1(0, 11); - ifxmips_port_set_open_drain(0, 11); - //enable ARC JTAG - IFX_MEI_LongWordRead ((u32) IFXMIPS_RCU_RST, ®_data); - IFX_MEI_LongWordWrite ((u32) IFXMIPS_RCU_RST, reg_data | IFXMIPS_RCU_RST_REQ_ARC_JTAG); - break; - case 0: - default: - //reserve gpio 9, 10, 11, 14, 19 for ARC JTAG - meierr = ifxmips_port_free_pin (0, 9); - if (meierr < 0) { - IFX_MEI_EMSG ("Reserve GPIO 9 Fail.\n"); - goto jtag_end; - } - meierr = ifxmips_port_free_pin (0, 10); - if (meierr < 0) { - IFX_MEI_EMSG ("Reserve GPIO 10 Fail.\n"); - goto jtag_end; - } - meierr = ifxmips_port_free_pin (0, 11); - if (meierr < 0) { - IFX_MEI_EMSG ("Reserve GPIO 11 Fail.\n"); - goto jtag_end; - } - meierr = ifxmips_port_free_pin (0, 14); - if (meierr < 0) { - IFX_MEI_EMSG ("Reserve GPIO 14 Fail.\n"); - goto jtag_end; - } - meierr = ifxmips_port_free_pin (1, 3); - if (meierr < 0) { - IFX_MEI_EMSG ("Reserve GPIO 19 Fail.\n"); - goto jtag_end; - } - break; - } -jtag_end: - if (meierr) - return DSL_DEV_MEI_ERR_FAILURE; - - return DSL_DEV_MEI_ERR_SUCCESS; -}; - -/** - * Enable DFE to MIPS interrupt - * This function enable DFE to MIPS interrupt - * - * \param pDev the device pointer - * \param enable enable or disable - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_AdslMailboxIRQEnable (DSL_DEV_Device_t *pDev, int enable) -{ - DSL_DEV_MeiError_t meierr; - switch (enable) { - case 0: - meierr = DSL_DEV_MEI_ERR_SUCCESS; - IFX_MEI_IRQDisable (pDev); - break; - case 1: - IFX_MEI_IRQEnable (pDev); - meierr = DSL_DEV_MEI_ERR_SUCCESS; - break; - default: - meierr = DSL_DEV_MEI_ERR_FAILURE; - break; - - } - return meierr; -} - -/** - * Get the modem status - * This function return the modem status - * - * \param pDev the device pointer - * \return 1: modem ready 0: not ready - * \ingroup Internal - */ -static int -IFX_MEI_IsModemReady (DSL_DEV_Device_t * pDev) -{ - return DSL_DEV_PRIVATE(pDev)->modem_ready; -} - -DSL_DEV_MeiError_t -DSL_BSP_AdslLedInit (DSL_DEV_Device_t * dev, - DSL_DEV_LedId_t led_number, - DSL_DEV_LedType_t type, - DSL_DEV_LedHandler_t handler) -{ -#if 0 - struct led_config_param param; - if (led_number == DSL_LED_LINK_ID && type == DSL_LED_LINK_TYPE && handler == /*DSL_LED_HD_CPU*/DSL_LED_HD_FW) { - param.operation_mask = CONFIG_OPERATION_UPDATE_SOURCE; - param.led = 0x01; - param.source = 0x01; -// bsp_led_config (¶m); - - } else if (led_number == DSL_LED_DATA_ID && type == DSL_LED_DATA_TYPE && (handler == DSL_LED_HD_FW)) { - param.operation_mask = CONFIG_OPERATION_UPDATE_SOURCE; - param.led = 0x02; - param.source = 0x02; -// bsp_led_config (¶m); - } -#endif - return DSL_DEV_MEI_ERR_SUCCESS; -}; -#if 0 -DSL_DEV_MeiError_t -DSL_BSP_AdslLedSet (DSL_DEV_Device_t * dev, DSL_DEV_LedId_t led_number, DSL_DEV_LedMode_t mode) -{ - printk(KERN_INFO "[%s %d]: mode = %#x, led_number = %d\n", __func__, __LINE__, mode, led_number); - switch (mode) { - case DSL_LED_OFF: - switch (led_number) { - case DSL_LED_LINK_ID: -#ifdef CONFIG_BSP_LED - bsp_led_set_blink (1, 0); - bsp_led_set_data (1, 0); -#endif - break; - case DSL_LED_DATA_ID: -#ifdef CONFIG_BSP_LED - bsp_led_set_blink (0, 0); - bsp_led_set_data (0, 0); -#endif - break; - } - break; - case DSL_LED_FLASH: - switch (led_number) { - case DSL_LED_LINK_ID: -#ifdef CONFIG_BSP_LED - bsp_led_set_blink (1, 1); // data -#endif - break; - case DSL_LED_DATA_ID: -#ifdef CONFIG_BSP_LED - bsp_led_set_blink (0, 1); // data -#endif - break; - } - break; - case DSL_LED_ON: - switch (led_number) { - case DSL_LED_LINK_ID: -#ifdef CONFIG_BSP_LED - bsp_led_set_blink (1, 0); - bsp_led_set_data (1, 1); -#endif - break; - case DSL_LED_DATA_ID: -#ifdef CONFIG_BSP_LED - bsp_led_set_blink (0, 0); - bsp_led_set_data (0, 1); -#endif - break; - } - break; - } - return DSL_DEV_MEI_ERR_SUCCESS; -}; - -#endif - -/** -* Compose a message. -* This function compose a message from opcode, group, address, index, size, and data -* -* \param opcode The message opcode -* \param group The message group number -* \param address The message address. -* \param index The message index. -* \param size The number of words to read/write. -* \param data The pointer to data. -* \param CMVMSG The pointer to message buffer. -* \ingroup Internal -*/ -void -makeCMV (u8 opcode, u8 group, u16 address, u16 index, int size, u16 * data, u16 *CMVMSG) -{ - memset (CMVMSG, 0, MSG_LENGTH * 2); - CMVMSG[0] = (opcode << 4) + (size & 0xf); - CMVMSG[1] = (((index == 0) ? 0 : 1) << 7) + (group & 0x7f); - CMVMSG[2] = address; - CMVMSG[3] = index; - if (opcode == H2D_CMV_WRITE) - memcpy (CMVMSG + 4, data, size * 2); - return; -} - -/** - * Send a message to ARC and read the response - * This function sends a message to arc, waits the response, and reads the responses. - * - * \param pDev the device pointer - * \param request Pointer to the request - * \param reply Wait reply or not. - * \param response Pointer to the response - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -DSL_DEV_MeiError_t -DSL_BSP_SendCMV (DSL_DEV_Device_t * pDev, u16 * request, int reply, u16 * response) // write cmv to arc, if reply needed, wait for reply -{ - DSL_DEV_MeiError_t meierror; -#if defined(BSP_PORT_RTEMS) - int delay_counter = 0; -#endif - - if (MEI_MUTEX_LOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema)) - return -ERESTARTSYS; - - DSL_DEV_PRIVATE(pDev)->cmv_reply = reply; - memset (DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, 0, - sizeof (DSL_DEV_PRIVATE(pDev)-> - CMV_RxMsg)); - DSL_DEV_PRIVATE(pDev)->arcmsgav = 0; - - meierror = IFX_MEI_MailboxWrite (pDev, request, MSG_LENGTH); - - if (meierror != DSL_DEV_MEI_ERR_SUCCESS) { - DSL_DEV_PRIVATE(pDev)->cmv_waiting = 0; - DSL_DEV_PRIVATE(pDev)->arcmsgav = 0; - IFX_MEI_EMSG ("MailboxWrite Fail!\n"); - IFX_MEI_EMSG ("Resetting ARC...\n"); - IFX_MEI_ResetARC(pDev); - MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema); - return meierror; - } - else { - DSL_DEV_PRIVATE(pDev)->cmv_count++; - } - - if (DSL_DEV_PRIVATE(pDev)->cmv_reply == - NO_REPLY) { - MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema); - return DSL_DEV_MEI_ERR_SUCCESS; - } - -#if !defined(BSP_PORT_RTEMS) - if (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0) - MEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav, CMV_TIMEOUT); -#else - while (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0 && delay_counter < CMV_TIMEOUT / 5) { - MEI_WAIT (5); - delay_counter++; - } -#endif - - DSL_DEV_PRIVATE(pDev)->cmv_waiting = 0; - if (DSL_DEV_PRIVATE(pDev)->arcmsgav == 0) { //CMV_timeout - DSL_DEV_PRIVATE(pDev)->arcmsgav = 0; - IFX_MEI_EMSG ("\%s: DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT\n", - __FUNCTION__); - MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema); - return DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT; - } - else { - DSL_DEV_PRIVATE(pDev)->arcmsgav = 0; - DSL_DEV_PRIVATE(pDev)-> - reply_count++; - memcpy (response, DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH * 2); - MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema); - return DSL_DEV_MEI_ERR_SUCCESS; - } - MEI_MUTEX_UNLOCK (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema); - return DSL_DEV_MEI_ERR_SUCCESS; -} - -/** - * Reset the ARC, download boot codes, and run the ARC. - * This function resets the ARC, downloads boot codes to ARC, and runs the ARC. - * - * \param pDev the device pointer - * \return DSL_DEV_MEI_ERR_SUCCESS or DSL_DEV_MEI_ERR_FAILURE - * \ingroup Internal - */ -static DSL_DEV_MeiError_t -IFX_MEI_RunAdslModem (DSL_DEV_Device_t *pDev) -{ - int nSize = 0, idx = 0; - uint32_t im0_register, im2_register; -// DSL_DEV_WinHost_Message_t m; - - if (mei_arc_swap_buff == NULL) { - mei_arc_swap_buff = - (u32 *) kmalloc (MAXSWAPSIZE * 4, GFP_KERNEL); - if (mei_arc_swap_buff == NULL) { - IFX_MEI_EMSG (">>> malloc fail for codeswap buff!!! <<<\n"); - return DSL_DEV_MEI_ERR_FAILURE; - } - printk("allocate %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff); - } - - DSL_DEV_PRIVATE(pDev)->img_hdr = - (ARC_IMG_HDR *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[0].address; - if ((DSL_DEV_PRIVATE(pDev)->img_hdr-> - count) * sizeof (ARC_SWP_PAGE_HDR) > SDRAM_SEGMENT_SIZE) { - IFX_MEI_EMSG ("firmware header size is bigger than 64K segment size\n"); - return DSL_DEV_MEI_ERR_FAILURE; - } - // check image size - for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) { - nSize += DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].nCopy; - } - if (nSize != - DSL_DEV_PRIVATE(pDev)->image_size) { - IFX_MEI_EMSG ("Firmware download is not completed. Please download firmware again!\n"); - return DSL_DEV_MEI_ERR_FAILURE; - } - // TODO: check crc - /// - - IFX_MEI_ResetARC (pDev); - IFX_MEI_HaltArc (pDev); - IFX_MEI_BarUpdate (pDev, DSL_DEV_PRIVATE(pDev)->nBar); - - //IFX_MEI_DMSG("Starting to meiDownloadBootCode\n"); - - IFX_MEI_DownloadBootCode (pDev); - - im0_register = (*IFXMIPS_ICU_IM0_IER) & (1 << 20); - im2_register = (*IFXMIPS_ICU_IM2_IER) & (1 << 20); - /* Turn off irq */ - #ifdef CONFIG_IFXMIPS_AMAZON_SE - disable_irq (IFXMIPS_USB_OC_INT0); - disable_irq (IFXMIPS_USB_OC_INT2); - #elif defined(CONFIG_IFXMIPS_AR9) - disable_irq (IFXMIPS_USB_OC_INT0); - disable_irq (IFXMIPS_USB_OC_INT2); - #elif defined(CONFIG_IFXMIPS_DANUBE) - disable_irq (IFXMIPS_USB_OC_INT); - #endif - disable_irq (pDev->nIrq[IFX_DYING_GASP]); - - IFX_MEI_RunArc (pDev); - - MEI_WAIT_EVENT_TIMEOUT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready, 1000); - - #ifdef CONFIG_IFXMIPS_AMAZON_SE - MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT0); - MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2); - #elif defined(CONFIG_IFXMIPS_AMAZON_S) - MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT0); - MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT2); - #elif defined(CONFIG_IFXMIPS_DANUBE) - MEI_MASK_AND_ACK_IRQ (IFXMIPS_USB_OC_INT); - #endif - MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]); - - /* Re-enable irq */ - enable_irq(pDev->nIrq[IFX_DYING_GASP]); - *IFXMIPS_ICU_IM0_IER |= im0_register; - *IFXMIPS_ICU_IM2_IER |= im2_register; - - if (DSL_DEV_PRIVATE(pDev)->modem_ready != 1) { - IFX_MEI_EMSG ("Modem failed to be ready!\n"); - return DSL_DEV_MEI_ERR_FAILURE; - } else { - IFX_MEI_DMSG("Modem is ready.\n"); - return DSL_DEV_MEI_ERR_SUCCESS; - } -} - -/** - * Get the page's data pointer - * This function caculats the data address from the firmware header. - * - * \param pDev the device pointer - * \param Page The page number. - * \param data Data page or program page. - * \param MaxSize The maximum size to read. - * \param Buffer Pointer to data. - * \param Dest Pointer to the destination address. - * \return The number of bytes to read. - * \ingroup Internal - */ -static int -IFX_MEI_GetPage (DSL_DEV_Device_t * pDev, u32 Page, u32 data, - u32 MaxSize, u32 * Buffer, u32 * Dest) -{ - u32 size; - u32 i; - u32 *p; - u32 idx, offset, nBar = 0; - - if (Page > DSL_DEV_PRIVATE(pDev)->img_hdr->count) - return -2; - /* - ** Get program or data size, depending on "data" flag - */ - size = (data == GET_DATA) ? (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].d_size) : - (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_size); - size &= BOOT_FLAG_MASK; // Clear boot bit! - if (size > MaxSize) - return -1; - - if (size == 0) - return 0; - /* - ** Get program or data offset, depending on "data" flag - */ - i = data ? (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].d_offset) : - (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_offset); - - /* - ** Copy data/program to buffer - */ - - idx = i / SDRAM_SEGMENT_SIZE; - offset = i % SDRAM_SEGMENT_SIZE; - p = (u32 *) ((u8 *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address + offset); - - for (i = 0; i < size; i++) { - if (offset + i * 4 - (nBar * SDRAM_SEGMENT_SIZE) >= SDRAM_SEGMENT_SIZE) { - idx++; - nBar++; - p = (u32 *) ((u8 *) KSEG1ADDR ((u32)DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address)); - } - Buffer[i] = *p++; - } - - /* - ** Pass back data/program destination address - */ - *Dest = data ? (DSL_DEV_PRIVATE(pDev)-> img_hdr->page[Page].d_dest) : - (DSL_DEV_PRIVATE(pDev)->img_hdr->page[Page].p_dest); - - return size; -} - -/** - * Free the memory for ARC firmware - * - * \param pDev the device pointer - * \param type Free all memory or free the unused memory after showtime - * \ingroup Internal - */ -const char *free_str[4] = {"Invalid", "Free_Reload", "Free_Showtime", "Free_All"}; -static int -IFX_MEI_DFEMemoryFree (DSL_DEV_Device_t * pDev, int type) -{ - int idx = 0; - smmu_mem_info_t *adsl_mem_info = - DSL_DEV_PRIVATE(pDev)->adsl_mem_info; - - for (idx = 0; idx < MAX_BAR_REGISTERS; idx++) { - if (type == FREE_ALL ||adsl_mem_info[idx].type == type) { - if (adsl_mem_info[idx].size > 0) { - IFX_MEI_DMSG ("Freeing memory %p (%s)\n", adsl_mem_info[idx].org_address, free_str[adsl_mem_info[idx].type]); - if ( idx == XDATA_REGISTER ) { - g_xdata_addr = NULL; - if ( ifx_mei_atm_showtime_exit ) - ifx_mei_atm_showtime_exit(); - } - kfree (adsl_mem_info[idx].org_address); - adsl_mem_info[idx].org_address = 0; - adsl_mem_info[idx].address = 0; - adsl_mem_info[idx].size = 0; - adsl_mem_info[idx].type = 0; - adsl_mem_info[idx].nCopy = 0; - } - } - } - - if(mei_arc_swap_buff != NULL){ - printk("free %dKB swap buff memory at: 0x%p\n", ksize(mei_arc_swap_buff)/1024, mei_arc_swap_buff); - kfree(mei_arc_swap_buff); - mei_arc_swap_buff=NULL; - } - - return 0; -} -static int -IFX_MEI_DFEMemoryAlloc (DSL_DEV_Device_t * pDev, long size) -{ - unsigned long mem_ptr; - char *org_mem_ptr = NULL; - int idx = 0; - long total_size = 0; - int err = 0; - smmu_mem_info_t *adsl_mem_info = - ((ifx_mei_device_private_t *) pDev->pPriv)->adsl_mem_info; -// DSL_DEV_PRIVATE(pDev)->adsl_mem_info; - int allocate_size = SDRAM_SEGMENT_SIZE; - - printk(KERN_INFO "[%s %d]: image_size = %ld\n", __func__, __LINE__, size); - // Alloc Swap Pages - for (idx = 0; size > 0 && idx < MAX_BAR_REGISTERS; idx++) { - // skip bar15 for XDATA usage. -#ifndef CONFIG_IFXMIPS_MEI_FW_LOOPBACK - if (idx == XDATA_REGISTER) - continue; -#endif -#if 0 - if (size < SDRAM_SEGMENT_SIZE) { - allocate_size = size; - if (allocate_size < 1024) - allocate_size = 1024; - } -#endif - if (idx == (MAX_BAR_REGISTERS - 1)) - allocate_size = size; - else - allocate_size = SDRAM_SEGMENT_SIZE; - org_mem_ptr = kmalloc (allocate_size + 1024, GFP_KERNEL); - if (org_mem_ptr == NULL) { - IFX_MEI_EMSG ("%d: kmalloc %d bytes memory fail!\n", idx, allocate_size); - err = -ENOMEM; - goto allocate_error; - } - mem_ptr = (unsigned long) (org_mem_ptr + 1023) & ~(1024 -1); - adsl_mem_info[idx].address = (char *) mem_ptr; - adsl_mem_info[idx].org_address = org_mem_ptr; - adsl_mem_info[idx].size = allocate_size; - size -= allocate_size; - total_size += allocate_size; - } - if (size > 0) { - IFX_MEI_EMSG ("Image size is too large!\n"); - err = -EFBIG; - goto allocate_error; - } - err = idx; - return err; - - allocate_error: - IFX_MEI_DFEMemoryFree (pDev, FREE_ALL); - return err; -} - -/** - * Program the BAR registers - * - * \param pDev the device pointer - * \param nTotalBar The number of bar to program. - * \ingroup Internal - */ -static int -IFX_MEI_BarUpdate (DSL_DEV_Device_t * pDev, int nTotalBar) -{ - int idx = 0; - smmu_mem_info_t *adsl_mem_info = - DSL_DEV_PRIVATE(pDev)->adsl_mem_info; - - for (idx = 0; idx < nTotalBar; idx++) { - //skip XDATA register - if (idx == XDATA_REGISTER) - continue; - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XMEM_BAR_BASE + idx * 4, - (((uint32_t) adsl_mem_info[idx].address) & 0x0FFFFFFF)); - } - for (idx = nTotalBar; idx < MAX_BAR_REGISTERS; idx++) { - if (idx == XDATA_REGISTER) - continue; - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XMEM_BAR_BASE + idx * 4, - (((uint32_t)adsl_mem_info[nTotalBar - 1].address) & 0x0FFFFFFF)); - /* These are for /proc/danube_mei/meminfo purpose */ - adsl_mem_info[idx].address = adsl_mem_info[nTotalBar - 1].address; - adsl_mem_info[idx].org_address = adsl_mem_info[nTotalBar - 1].org_address; - adsl_mem_info[idx].size = 0; /* Prevent it from being freed */ - } - - g_xdata_addr = adsl_mem_info[XDATA_REGISTER].address; - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XMEM_BAR_BASE + XDATA_REGISTER * 4, - (((uint32_t) adsl_mem_info [XDATA_REGISTER].address) & 0x0FFFFFFF)); - // update MEI_XDATA_BASE_SH - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XDATA_BASE_SH, - ((unsigned long)adsl_mem_info[XDATA_REGISTER].address) & 0x0FFFFFFF); - - return DSL_DEV_MEI_ERR_SUCCESS; -} - -/* This copies the firmware from secondary storage to 64k memory segment in SDRAM */ -DSL_DEV_MeiError_t -DSL_BSP_FWDownload (DSL_DEV_Device_t * pDev, const char *buf, - unsigned long size, long *loff, long *current_offset) -{ - ARC_IMG_HDR img_hdr_tmp; - smmu_mem_info_t *adsl_mem_info = DSL_DEV_PRIVATE(pDev)->adsl_mem_info; - - size_t nRead = 0, nCopy = 0; - char *mem_ptr; - ssize_t retval = -ENOMEM; - int idx = 0; - - printk("\n%s\n", __func__); - - if (*loff == 0) { - if (size < sizeof (img_hdr_tmp)) { - IFX_MEI_EMSG ("Firmware size is too small!\n"); - return retval; - } - copy_from_user ((char *) &img_hdr_tmp, buf, sizeof (img_hdr_tmp)); - // header of image_size and crc are not included. - DSL_DEV_PRIVATE(pDev)->image_size = le32_to_cpu (img_hdr_tmp.size) + 8; - - if (DSL_DEV_PRIVATE(pDev)->image_size > 1024 * 1024) { - IFX_MEI_EMSG ("Firmware size is too large!\n"); - return retval; - } - // check if arc is halt - IFX_MEI_ResetARC (pDev); - IFX_MEI_HaltArc (pDev); - - IFX_MEI_DFEMemoryFree (pDev, FREE_ALL); //free all - - retval = IFX_MEI_DFEMemoryAlloc (pDev, DSL_DEV_PRIVATE(pDev)->image_size); - if (retval < 0) { - IFX_MEI_EMSG ("Error: No memory space left.\n"); - goto error; - } - for (idx = 0; idx < retval; idx++) { - //skip XDATA register - if (idx == XDATA_REGISTER) - continue; - if (idx * SDRAM_SEGMENT_SIZE < le32_to_cpu (img_hdr_tmp.page[0].p_offset)) - adsl_mem_info[idx].type = FREE_RELOAD; - else - adsl_mem_info[idx].type = FREE_SHOWTIME; - } - DSL_DEV_PRIVATE(pDev)->nBar = retval; - - DSL_DEV_PRIVATE(pDev)->img_hdr = - (ARC_IMG_HDR *) adsl_mem_info[0].address; - - adsl_mem_info[XDATA_REGISTER].org_address = kmalloc (SDRAM_SEGMENT_SIZE + 1024, GFP_KERNEL); - adsl_mem_info[XDATA_REGISTER].address = - (char *) ((unsigned long) (adsl_mem_info[XDATA_REGISTER].org_address + 1023) & 0xFFFFFC00); - - adsl_mem_info[XDATA_REGISTER].size = SDRAM_SEGMENT_SIZE; - - if (adsl_mem_info[XDATA_REGISTER].address == NULL) { - IFX_MEI_EMSG ("kmalloc memory fail!\n"); - retval = -ENOMEM; - goto error; - } - adsl_mem_info[XDATA_REGISTER].type = FREE_RELOAD; - printk(KERN_INFO "[%s %d] -> IFX_MEI_BarUpdate()\n", __func__, __LINE__); - IFX_MEI_BarUpdate (pDev, (DSL_DEV_PRIVATE(pDev)->nBar)); - } - else if (DSL_DEV_PRIVATE(pDev)-> image_size == 0) { - IFX_MEI_EMSG ("Error: Firmware size=0! \n"); - goto error; - } - - nRead = 0; - while (nRead < size) { - long offset = ((long) (*loff) + nRead) % SDRAM_SEGMENT_SIZE; - idx = (((long) (*loff)) + nRead) / SDRAM_SEGMENT_SIZE; - mem_ptr = (char *) KSEG1ADDR ((unsigned long) (adsl_mem_info[idx].address) + offset); - if ((size - nRead + offset) > SDRAM_SEGMENT_SIZE) - nCopy = SDRAM_SEGMENT_SIZE - offset; - else - nCopy = size - nRead; - copy_from_user (mem_ptr, buf + nRead, nCopy); - for (offset = 0; offset < (nCopy / 4); offset++) { - ((unsigned long *) mem_ptr)[offset] = le32_to_cpu (((unsigned long *) mem_ptr)[offset]); - } - nRead += nCopy; - adsl_mem_info[idx].nCopy += nCopy; - } - - *loff += size; - *current_offset = size; - return DSL_DEV_MEI_ERR_SUCCESS; -error: - IFX_MEI_DFEMemoryFree (pDev, FREE_ALL); - return DSL_DEV_MEI_ERR_FAILURE; -} -/* - * Register a callback event. - * Return: - * -1 if the event already has a callback function registered. - * 0 success - */ -int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *p) -{ - if (!p) { - IFX_MEI_EMSG("Invalid parameter!\n"); - return -EINVAL; - } - if (p->event > DSL_BSP_CB_LAST || p->event < DSL_BSP_CB_FIRST) { - IFX_MEI_EMSG("Invalid Event %d\n", p->event); - return -EINVAL; - } - if (dsl_bsp_event_callback[p->event].function) { - IFX_MEI_EMSG("Event %d already has a callback function registered!\n", p->event); - return -1; - } else { - dsl_bsp_event_callback[p->event].function = p->function; - dsl_bsp_event_callback[p->event].event = p->event; - dsl_bsp_event_callback[p->event].pData = p->pData; - } - return 0; -} -int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *p) -{ - if (!p) { - IFX_MEI_EMSG("Invalid parameter!\n"); - return -EINVAL; - } - if (p->event > DSL_BSP_CB_LAST || p->event < DSL_BSP_CB_FIRST) { - IFX_MEI_EMSG("Invalid Event %d\n", p->event); - return -EINVAL; - } - if (dsl_bsp_event_callback[p->event].function) { - IFX_MEI_EMSG("Unregistering Event %d...\n", p->event); - dsl_bsp_event_callback[p->event].function = NULL; - dsl_bsp_event_callback[p->event].pData = NULL; - } else { - IFX_MEI_EMSG("Event %d is not registered!\n", p->event); - return -1; - } - return 0; -} - -/** - * MEI Dying Gasp interrupt handler - * - * \param int1 - * \param void0 - * \param regs Pointer to the structure of danube mips registers - * \ingroup Internal - */ -static irqreturn_t IFX_MEI_Dying_Gasp_IrqHandle (int int1, void *void0) -{ - DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) void0; - DSL_BSP_CB_Type_t event; - - if (pDev == NULL) - IFX_MEI_EMSG("Error: Got Interrupt but pDev is NULL!!!!\n"); - -#ifndef CONFIG_SMP - disable_irq (pDev->nIrq[IFX_DYING_GASP]); -#else - disable_irq_nosync(pDev->nIrq[IFX_DYING_GASP]); -#endif - event = DSL_BSP_CB_DYING_GASP; - - if (dsl_bsp_event_callback[event].function) - (*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData); - -#ifdef CONFIG_USE_EMULATOR - IFX_MEI_EMSG("Dying Gasp! Shutting Down... (Work around for Amazon-S Venus emulator)\n"); -#else - IFX_MEI_EMSG("Dying Gasp! Shutting Down...\n"); -// kill_proc (1, SIGINT, 1); /* Ask init to reboot us */ -#endif - return IRQ_HANDLED; -} - -extern void ifx_usb_enable_afe_oc(void); - -/** - * MEI interrupt handler - * - * \param int1 - * \param void0 - * \param regs Pointer to the structure of danube mips registers - * \ingroup Internal - */ -static irqreturn_t IFX_MEI_IrqHandle (int int1, void *void0) -{ - u32 scratch; - DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) void0; -#if defined(CONFIG_IFXMIPS_MEI_FW_LOOPBACK) && defined(DFE_PING_TEST) - dfe_loopback_irq_handler (pDev); - return IRQ_HANDLED; -#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK - DSL_BSP_CB_Type_t event; - - if (pDev == NULL) - IFX_MEI_EMSG("Error: Got Interrupt but pDev is NULL!!!!\n"); - - IFX_MEI_DebugRead (pDev, ARC_MEI_MAILBOXR, &scratch, 1); - if (scratch & OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK) { - IFX_MEI_EMSG("Receive Code Swap Request interrupt!!!\n"); - return IRQ_HANDLED; - } - else if (scratch & OMB_CLEAREOC_INTERRUPT_CODE) { - // clear eoc message interrupt - IFX_MEI_DMSG("OMB_CLEAREOC_INTERRUPT_CODE\n"); - event = DSL_BSP_CB_CEOC_IRQ; - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV); - if (dsl_bsp_event_callback[event].function) - (*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData); - } else if (scratch & OMB_REBOOT_INTERRUPT_CODE) { - // Reboot - IFX_MEI_DMSG("OMB_REBOOT_INTERRUPT_CODE\n"); - event = DSL_BSP_CB_FIRMWARE_REBOOT; - - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_ARC2ME_STAT, ARC_TO_MEI_MSGAV); - - if (dsl_bsp_event_callback[event].function) - (*dsl_bsp_event_callback[event].function)(pDev, event, dsl_bsp_event_callback[event].pData); - } else { // normal message - IFX_MEI_MailboxRead (pDev, DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH); - if (DSL_DEV_PRIVATE(pDev)-> cmv_waiting == 1) { - DSL_DEV_PRIVATE(pDev)-> arcmsgav = 1; - DSL_DEV_PRIVATE(pDev)-> cmv_waiting = 0; -#if !defined(BSP_PORT_RTEMS) - MEI_WAKEUP_EVENT (DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav); -#endif - } - else { - DSL_DEV_PRIVATE(pDev)-> modem_ready_cnt++; - memcpy ((char *) DSL_DEV_PRIVATE(pDev)->Recent_indicator, - (char *) DSL_DEV_PRIVATE(pDev)->CMV_RxMsg, MSG_LENGTH * 2); - if (((DSL_DEV_PRIVATE(pDev)->CMV_RxMsg[0] & 0xff0) >> 4) == D2H_AUTONOMOUS_MODEM_READY_MSG) { - //check ARC ready message - IFX_MEI_DMSG ("Got MODEM_READY_MSG\n"); - DSL_DEV_PRIVATE(pDev)->modem_ready = 1; - MEI_WAKEUP_EVENT (DSL_DEV_PRIVATE(pDev)->wait_queue_modemready); - } - } - } - - return IRQ_HANDLED; -} - -int -DSL_BSP_ATMLedCBRegister (int (*ifx_adsl_ledcallback) (void)) -{ - g_adsl_ledcallback = ifx_adsl_ledcallback; - return 0; -} - -int -DSL_BSP_ATMLedCBUnregister (int (*ifx_adsl_ledcallback) (void)) -{ - g_adsl_ledcallback = adsl_dummy_ledcallback; - return 0; -} - -#if 0 -int -DSL_BSP_EventCBRegister (int (*ifx_adsl_callback) - (DSL_BSP_CB_Event_t * param)) -{ - int error = 0; - - if (DSL_EventCB == NULL) { - DSL_EventCB = ifx_adsl_callback; - } - else { - error = -EIO; - } - return error; -} - -int -DSL_BSP_EventCBUnregister (int (*ifx_adsl_callback) - (DSL_BSP_CB_Event_t * param)) -{ - int error = 0; - - if (DSL_EventCB == ifx_adsl_callback) { - DSL_EventCB = NULL; - } - else { - error = -EIO; - } - return error; -} - -static int -DSL_BSP_GetEventCB (int (**ifx_adsl_callback) - (DSL_BSP_CB_Event_t * param)) -{ - *ifx_adsl_callback = DSL_EventCB; - return 0; -} -#endif - -#ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK -#define mte_reg_base (0x4800*4+0x20000) - -/* Iridia Registers Address Constants */ -#define MTE_Reg(r) (int)(mte_reg_base + (r*4)) - -#define IT_AMODE MTE_Reg(0x0004) - -#define TIMER_DELAY (1024) -#define BC0_BYTES (32) -#define BC1_BYTES (30) -#define NUM_MB (12) -#define TIMEOUT_VALUE 2000 - -static void -BFMWait (u32 cycle) -{ - u32 i; - for (i = 0; i < cycle; i++); -} - -static void -WriteRegLong (u32 addr, u32 data) -{ - //*((volatile u32 *)(addr)) = data; - IFX_MEI_WRITE_REGISTER_L (data, addr); -} - -static u32 -ReadRegLong (u32 addr) -{ - // u32 rd_val; - //rd_val = *((volatile u32 *)(addr)); - // return rd_val; - return IFX_MEI_READ_REGISTER_L (addr); -} - -/* This routine writes the mailbox with the data in an input array */ -static void -WriteMbox (u32 * mboxarray, u32 size) -{ - IFX_MEI_DebugWrite (&dsl_devices[0], IMBOX_BASE, mboxarray, size); - printk ("write to %X\n", IMBOX_BASE); - IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ME2ARC_INT, MEI_TO_ARC_MSGAV); -} - -/* This routine reads the output mailbox and places the results into an array */ -static void -ReadMbox (u32 * mboxarray, u32 size) -{ - IFX_MEI_DebugRead (&dsl_devices[0], OMBOX_BASE, mboxarray, size); - printk ("read from %X\n", OMBOX_BASE); -} - -static void -MEIWriteARCValue (u32 address, u32 value) -{ - u32 i, check = 0; - - /* Write address register */ - IFX_MEI_WRITE_REGISTER_L (address, ME_DBG_WR_AD + IFXMIPS_MEI_BASE_ADDR); - - /* Write data register */ - IFX_MEI_WRITE_REGISTER_L (value, ME_DBG_DATA + IFXMIPS_MEI_BASE_ADDR); - - /* wait until complete - timeout at 40 */ - for (i = 0; i < 40; i++) { - check = IFX_MEI_READ_REGISTER_L (ME_ARC2ME_STAT + IFXMIPS_MEI_BASE_ADDR); - - if ((check & ARC_TO_MEI_DBG_DONE)) - break; - } - /* clear the flag */ - IFX_MEI_WRITE_REGISTER_L (ARC_TO_MEI_DBG_DONE, ME_ARC2ME_STAT + IFXMIPS_MEI_BASE_ADDR); -} - -void -arc_code_page_download (uint32_t arc_code_length, uint32_t * start_address) -{ - int count; - - printk ("try to download pages,size=%d\n", arc_code_length); - IFX_MEI_ControlModeSet (&dsl_devices[0], MEI_MASTER_MODE); - IFX_MEI_HaltArc (&dsl_devices[0]); - IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_AD, 0); - for (count = 0; count < arc_code_length; count++) { - IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_DX_DATA, - *(start_address + count)); - } - IFX_MEI_ControlModeSet (&dsl_devices[0], JTAG_MASTER_MODE); -} -static int -load_jump_table (unsigned long addr) -{ - int i; - uint32_t addr_le, addr_be; - uint32_t jump_table[32]; - - for (i = 0; i < 16; i++) { - addr_le = i * 8 + addr; - addr_be = ((addr_le >> 16) & 0xffff); - addr_be |= ((addr_le & 0xffff) << 16); - jump_table[i * 2 + 0] = 0x0f802020; - jump_table[i * 2 + 1] = addr_be; - //printk("jt %X %08X %08X\n",i,jump_table[i*2+0],jump_table[i*2+1]); - } - arc_code_page_download (32, &jump_table[0]); -return 0; -} - -int got_int = 0; - -void -dfe_loopback_irq_handler (DSL_DEV_Device_t *pDev) -{ - uint32_t rd_mbox[10]; - - memset (&rd_mbox[0], 0, 10 * 4); - ReadMbox (&rd_mbox[0], 6); - if (rd_mbox[0] == 0x0) { - printk ("Get ARC_ACK\n"); - got_int = 1; - } - else if (rd_mbox[0] == 0x5) { - printk ("Get ARC_BUSY\n"); - got_int = 2; - } - else if (rd_mbox[0] == 0x3) { - printk ("Get ARC_EDONE\n"); - if (rd_mbox[1] == 0x0) { - got_int = 3; - printk ("Get E_MEMTEST\n"); - if (rd_mbox[2] != 0x1) { - got_int = 4; - printk ("Get Result %X\n", rd_mbox[2]); - } - } - } - IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_STAT, - ARC_TO_MEI_DBG_DONE); - MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DFEIR]); - disable_irq (pDev->nIrq[IFX_DFEIR]); - //got_int = 1; - return; -} - -static void -wait_mem_test_result (void) -{ - uint32_t mbox[5]; - mbox[0] = 0; - - printk ("Waiting Starting\n"); - while (mbox[0] == 0) { - ReadMbox (&mbox[0], 5); - } - printk ("Try to get mem test result.\n"); - ReadMbox (&mbox[0], 5); - if (mbox[0] == 0xA) { - printk ("Success.\n"); - } - else if (mbox[0] == 0xA) { - printk ("Fail,address %X,except data %X,receive data %X\n", - mbox[1], mbox[2], mbox[3]); - } - else { - printk ("Fail\n"); - } -} - -static int -arc_ping_testing (DSL_DEV_Device_t *pDev) -{ -#define MEI_PING 0x00000001 - uint32_t wr_mbox[10], rd_mbox[10]; - int i; - - for (i = 0; i < 10; i++) { - wr_mbox[i] = 0; - rd_mbox[i] = 0; - } - - printk ("send ping msg\n"); - wr_mbox[0] = MEI_PING; - WriteMbox (&wr_mbox[0], 10); - - while (got_int == 0) { - MEI_WAIT (100); - } - - printk ("send start event\n"); - got_int = 0; - - wr_mbox[0] = 0x4; - wr_mbox[1] = 0; - wr_mbox[2] = 0; - wr_mbox[3] = (uint32_t) 0xf5acc307e; - wr_mbox[4] = 5; - wr_mbox[5] = 2; - wr_mbox[6] = 0x1c000; - wr_mbox[7] = 64; - wr_mbox[8] = 0; - wr_mbox[9] = 0; - WriteMbox (&wr_mbox[0], 10); - DSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]); - //printk("IFX_MEI_MailboxWrite ret=%d\n",i); - IFX_MEI_LongWordWriteOffset (&dsl_devices[0], - (u32) ME_ME2ARC_INT, - MEI_TO_ARC_MSGAV); - printk ("sleeping\n"); - while (1) { - if (got_int > 0) { - - if (got_int > 3) - printk ("got_int >>>> 3\n"); - else - printk ("got int = %d\n", got_int); - got_int = 0; - //schedule(); - DSL_ENABLE_IRQ (pDev->nIrq[IFX_DFEIR]); - } - //mbox_read(&rd_mbox[0],6); - MEI_WAIT (100); - } - return 0; -} - -static DSL_DEV_MeiError_t -DFE_Loopback_Test (void) -{ - int i = 0; - u32 arc_debug_data = 0, temp; - DSL_DEV_Device_t *pDev = &dsl_devices[0]; - uint32_t wr_mbox[10]; - - IFX_MEI_ResetARC (pDev); - // start the clock - arc_debug_data = ACL_CLK_MODE_ENABLE; - IFX_MEI_DebugWrite (pDev, CRI_CCR0, &arc_debug_data, 1); - -#if defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK) - // WriteARCreg(AUX_XMEM_LTEST,0); - IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE); -#define AUX_XMEM_LTEST 0x128 - _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, AUX_XMEM_LTEST, 0); - IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE); - - // WriteARCreg(AUX_XDMA_GAP,0); - IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE); -#define AUX_XDMA_GAP 0x114 - _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, AUX_XDMA_GAP, 0); - IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE); - - IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE); - temp = 0; - _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, - (u32) ME_XDATA_BASE_SH + IFXMIPS_MEI_BASE_ADDR, temp); - IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE); - - i = IFX_MEI_DFEMemoryAlloc (pDev, SDRAM_SEGMENT_SIZE * 16); - if (i >= 0) { - int idx; - - for (idx = 0; idx < i; idx++) { - DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].type = FREE_RELOAD; - IFX_MEI_WRITE_REGISTER_L ((((uint32_t) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address) & 0x0fffffff), - IFXMIPS_MEI_BASE_ADDR + ME_XMEM_BAR_BASE + idx * 4); - printk ("bar%d(%X)=%X\n", idx, - IFXMIPS_MEI_BASE_ADDR + ME_XMEM_BAR_BASE + - idx * 4, (((uint32_t) - ((ifx_mei_device_private_t *) - pDev->pPriv)->adsl_mem_info[idx]. - address) & 0x0fffffff)); - memset ((u8 *) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[idx].address, 0, SDRAM_SEGMENT_SIZE); - } - - IFX_MEI_LongWordWriteOffset (pDev, (u32) ME_XDATA_BASE_SH, - ((unsigned long) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[XDATA_REGISTER].address) & 0x0FFFFFFF); - } - else { - IFX_MEI_EMSG ("cannot load image: no memory\n"); - return DSL_DEV_MEI_ERR_FAILURE; - } - //WriteARCreg(AUX_IC_CTRL,2); - printk(KERN_INFO "[%s %s %d]: Setting MEI_MASTER_MODE..\n", __FILE__, __func__, __LINE__); - IFX_MEI_ControlModeSet (pDev, MEI_MASTER_MODE); -#define AUX_IC_CTRL 0x11 - _IFX_MEI_DBGLongWordWrite (pDev, MEI_DEBUG_DEC_AUX_MASK, - AUX_IC_CTRL, 2); - printk(KERN_INFO "[%s %s %d]: Setting JTAG_MASTER_MODE..\n", __FILE__, __func__, __LINE__); - IFX_MEI_ControlModeSet (pDev, JTAG_MASTER_MODE); - - printk(KERN_INFO "[%s %s %d]: Halting ARC...\n", __FILE__, __func__, __LINE__); - IFX_MEI_HaltArc (&dsl_devices[0]); - -#ifdef DFE_PING_TEST - - printk ("ping test image size=%d\n", sizeof (arc_ahb_access_code)); - memcpy ((u8 *) (DSL_DEV_PRIVATE(pDev)-> - adsl_mem_info[0].address + 0x1004), - &arc_ahb_access_code[0], sizeof (arc_ahb_access_code)); - load_jump_table (0x80000 + 0x1004); - -#endif //DFE_PING_TEST - - printk ("ARC ping test code download complete\n"); -#endif //defined( DFE_PING_TEST )|| defined( DFE_ATM_LOOPBACK) -#ifdef DFE_MEM_TEST - IFX_MEI_LongWordWriteOffset (&dsl_devices[0], (u32) ME_ARC2ME_MASK, MSGAV_EN); - - arc_code_page_download (1537, &code_array[0]); - printk ("ARC mem test code download complete\n"); -#endif //DFE_MEM_TEST -#ifdef DFE_ATM_LOOPBACK - arc_debug_data = 0xf; - arc_code_page_download (sizeof(code_array) / sizeof(*code_array), &code_array[0]); - wr_mbox[0] = 0; //TIMER_DELAY - org: 1024 - wr_mbox[1] = 0; //TXFB_START0 - wr_mbox[2] = 0x7f; //TXFB_END0 - org: 49 - wr_mbox[3] = 0x80; //TXFB_START1 - org: 80 - wr_mbox[4] = 0xff; //TXFB_END1 - org: 109 - wr_mbox[5] = 0x100; //RXFB_START0 - org: 0 - wr_mbox[6] = 0x17f; //RXFB_END0 - org: 49 - wr_mbox[7] = 0x180; //RXFB_START1 - org: 256 - wr_mbox[8] = 0x1ff; //RXFB_END1 - org: 315 - WriteMbox (&wr_mbox[0], 9); - // Start Iridia IT_AMODE (in dmp access) why is it required? - IFX_MEI_DebugWrite (&dsl_devices[0], 0x32010, &arc_debug_data, 1); -#endif //DFE_ATM_LOOPBACK - IFX_MEI_IRQEnable (pDev); - printk(KERN_INFO "[%s %s %d]: run ARC...\n", __FILE__, __func__, __LINE__); - IFX_MEI_RunArc (&dsl_devices[0]); - -#ifdef DFE_PING_TEST - arc_ping_testing (pDev); -#endif //DFE_PING_TEST -#ifdef DFE_MEM_TEST - wait_mem_test_result (); -#endif //DFE_MEM_TEST - - IFX_MEI_DFEMemoryFree (pDev, FREE_ALL); - return DSL_DEV_MEI_ERR_SUCCESS; -} - -#endif //CONFIG_AMAZON_S_MEI_FW_LOOPBACK - -static int -IFX_MEI_InitDevNode (int num) -{ - if (num == 0) { - if ((dev_major = register_chrdev (dev_major, IFX_MEI_DEVNAME, &bsp_mei_operations)) < 0) { - IFX_MEI_EMSG ("register_chrdev(%d %s) failed!\n", dev_major, IFX_MEI_DEVNAME); - return -ENODEV; - } - } - return 0; -} - -static int -IFX_MEI_CleanUpDevNode (int num) -{ - if (num == 0) - unregister_chrdev (dev_major, MEI_DIRNAME); - return 0; -} - -static int -IFX_MEI_InitDevice (int num) -{ - DSL_DEV_Device_t *pDev; - u32 temp; - pDev = &dsl_devices[num]; - if (pDev == NULL) - return -ENOMEM; - pDev->pPriv = &sDanube_Mei_Private[num]; - memset (pDev->pPriv, 0, sizeof (ifx_mei_device_private_t)); - - memset (&DSL_DEV_PRIVATE(pDev)-> - adsl_mem_info[0], 0, - sizeof (smmu_mem_info_t) * MAX_BAR_REGISTERS); - - if (num == 0) { - pDev->nIrq[IFX_DFEIR] = IFXMIPS_MEI_INT; - pDev->nIrq[IFX_DYING_GASP] = IFXMIPS_MEI_DYING_GASP_INT; - pDev->base_address = IFXMIPS_MEI_BASE_ADDR; - - /* Power up MEI */ -#ifdef CONFIG_IFXMIPS_AMAZON_SE - *IFXMIPS_PMU_PWDCR &= ~(1 << 9); // enable dsl - *IFXMIPS_PMU_PWDCR &= ~(1 << 15); // enable AHB base -#else - temp = ifxmips_r32(IFXMIPS_PMU_PWDCR); - temp &= 0xffff7dbe; - ifxmips_w32(temp, IFXMIPS_PMU_PWDCR); -#endif - } - pDev->nInUse = 0; - DSL_DEV_PRIVATE(pDev)->modem_ready = 0; - DSL_DEV_PRIVATE(pDev)->arcmsgav = 0; - - MEI_INIT_WAKELIST ("arcq", DSL_DEV_PRIVATE(pDev)->wait_queue_arcmsgav); // for ARCMSGAV - MEI_INIT_WAKELIST ("arcr", DSL_DEV_PRIVATE(pDev)->wait_queue_modemready); // for arc modem ready - - MEI_MUTEX_INIT (DSL_DEV_PRIVATE(pDev)->mei_cmv_sema, 1); // semaphore initialization, mutex -#if 0 - MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DFEIR]); - MEI_MASK_AND_ACK_IRQ (pDev->nIrq[IFX_DYING_GASP]); -#endif - if (request_irq (pDev->nIrq[IFX_DFEIR], IFX_MEI_IrqHandle, 0, "DFEIR", pDev) != 0) { - IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DFEIR]); - return -1; - } - if (request_irq (pDev->nIrq[IFX_DYING_GASP], IFX_MEI_Dying_Gasp_IrqHandle, 0, "DYING_GASP", pDev) != 0) { - IFX_MEI_EMSG ("request_irq %d failed!\n", pDev->nIrq[IFX_DYING_GASP]); - return -1; - } -// IFX_MEI_DMSG("Device %d initialized. IER %#x\n", num, bsp_get_irq_ier(pDev->nIrq[IFX_DYING_GASP])); - return 0; -} - -static int -IFX_MEI_ExitDevice (int num) -{ - DSL_DEV_Device_t *pDev; - pDev = &dsl_devices[num]; - - if (pDev == NULL) - return -EIO; - - disable_irq (pDev->nIrq[IFX_DFEIR]); - disable_irq (pDev->nIrq[IFX_DYING_GASP]); - - free_irq(pDev->nIrq[IFX_DFEIR], pDev); - free_irq(pDev->nIrq[IFX_DYING_GASP], pDev); - - return 0; -} - -static DSL_DEV_Device_t * -IFX_BSP_HandleGet (int maj, int num) -{ - if (num > BSP_MAX_DEVICES) - return NULL; - return &dsl_devices[num]; -} - -DSL_DEV_Device_t * -DSL_BSP_DriverHandleGet (int maj, int num) -{ - DSL_DEV_Device_t *pDev; - - if (num > BSP_MAX_DEVICES) - return NULL; - - pDev = &dsl_devices[num]; - if (!try_module_get(pDev->owner)) - return NULL; - - pDev->nInUse++; - return pDev; -} - -int -DSL_BSP_DriverHandleDelete (DSL_DEV_Device_t * nHandle) -{ - DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) nHandle; - if (pDev->nInUse) - pDev->nInUse--; - module_put(pDev->owner); - return 0; -} - -static int -IFX_MEI_Open (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil) -{ - int maj = MAJOR (ino->i_rdev); - int num = MINOR (ino->i_rdev); - - DSL_DEV_Device_t *pDev = NULL; - if ((pDev = DSL_BSP_DriverHandleGet (maj, num)) == NULL) { - IFX_MEI_EMSG("open(%d:%d) fail!\n", maj, num); - return -EIO; - } - fil->private_data = pDev; - return 0; -} - -static int -IFX_MEI_Release (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil) -{ - //int maj = MAJOR(ino->i_rdev); - int num = MINOR (ino->i_rdev); - DSL_DEV_Device_t *pDev; - - pDev = &dsl_devices[num]; - if (pDev == NULL) - return -EIO; - DSL_BSP_DriverHandleDelete (pDev); - return 0; -} - -/** - * Callback function for linux userspace program writing - */ -static ssize_t -IFX_MEI_Write (DSL_DRV_file_t * filp, const char *buf, size_t size, loff_t * loff) -{ - DSL_DEV_MeiError_t mei_error = DSL_DEV_MEI_ERR_FAILURE; - long offset = 0; - DSL_DEV_Device_t *pDev = (DSL_DEV_Device_t *) filp->private_data; - - if (pDev == NULL) - return -EIO; - - mei_error = - DSL_BSP_FWDownload (pDev, buf, size, (long *) loff, &offset); - - if (mei_error == DSL_DEV_MEI_ERR_FAILURE) - return -EIO; - return (ssize_t) offset; -} - -/** - * Callback function for linux userspace program ioctling - */ -static int -IFX_MEI_IoctlCopyFrom (int from_kernel, char *dest, char *from, int size) -{ - int ret = 0; - - if (!from_kernel) - ret = copy_from_user ((char *) dest, (char *) from, size); - else - ret = (int)memcpy ((char *) dest, (char *) from, size); - return ret; -} - -static int -IFX_MEI_IoctlCopyTo (int from_kernel, char *dest, char *from, int size) -{ - int ret = 0; - - if (!from_kernel) - ret = copy_to_user ((char *) dest, (char *) from, size); - else - ret = (int)memcpy ((char *) dest, (char *) from, size); - return ret; -} - -static int -IFX_MEI_Ioctls (DSL_DEV_Device_t * pDev, int from_kernel, unsigned int command, unsigned long lon) -{ - int i = 0; - int meierr = DSL_DEV_MEI_ERR_SUCCESS; - u32 base_address = IFXMIPS_MEI_BASE_ADDR; - DSL_DEV_WinHost_Message_t winhost_msg, m; - DSL_DEV_MeiDebug_t debugrdwr; - DSL_DEV_MeiReg_t regrdwr; - - switch (command) { - - case DSL_FIO_BSP_CMV_WINHOST: - IFX_MEI_IoctlCopyFrom (from_kernel, (char *) winhost_msg.msg.TxMessage, - (char *) lon, MSG_LENGTH * 2); - - if ((meierr = DSL_BSP_SendCMV (pDev, winhost_msg.msg.TxMessage, YES_REPLY, - winhost_msg.msg.RxMessage)) != DSL_DEV_MEI_ERR_SUCCESS) { - IFX_MEI_EMSG ("WINHOST CMV fail :TxMessage:%X %X %X %X, RxMessage:%X %X %X %X %X\n", - winhost_msg.msg.TxMessage[0], winhost_msg.msg.TxMessage[1], winhost_msg.msg.TxMessage[2], winhost_msg.msg.TxMessage[3], - winhost_msg.msg.RxMessage[0], winhost_msg.msg.RxMessage[1], winhost_msg.msg.RxMessage[2], winhost_msg.msg.RxMessage[3], - winhost_msg.msg.RxMessage[4]); - meierr = DSL_DEV_MEI_ERR_FAILURE; - } - else { - IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, - (char *) winhost_msg.msg.RxMessage, - MSG_LENGTH * 2); - } - break; - - case DSL_FIO_BSP_CMV_READ: - IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (®rdwr), - (char *) lon, sizeof (DSL_DEV_MeiReg_t)); - - IFX_MEI_LongWordRead ((u32) regrdwr.iAddress, - (u32 *) & (regrdwr.iData)); - - IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, - (char *) (®rdwr), - sizeof (DSL_DEV_MeiReg_t)); - - break; - - case DSL_FIO_BSP_CMV_WRITE: - IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (®rdwr), - (char *) lon, sizeof (DSL_DEV_MeiReg_t)); - - IFX_MEI_LongWordWrite ((u32) regrdwr.iAddress, - regrdwr.iData); - break; - - case DSL_FIO_BSP_GET_BASE_ADDRESS: - IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, - (char *) (&base_address), - sizeof (base_address)); - break; - - case DSL_FIO_BSP_IS_MODEM_READY: - i = IFX_MEI_IsModemReady (pDev); - IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, - (char *) (&i), sizeof (int)); - meierr = DSL_DEV_MEI_ERR_SUCCESS; - break; - case DSL_FIO_BSP_RESET: - case DSL_FIO_BSP_REBOOT: - meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_RESET); - meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_HALT); - break; - - case DSL_FIO_BSP_HALT: - meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_HALT); - break; - - case DSL_FIO_BSP_RUN: - meierr = IFX_MEI_CpuModeSet (pDev, DSL_CPU_RUN); - break; - case DSL_FIO_BSP_BOOTDOWNLOAD: - meierr = IFX_MEI_DownloadBootCode (pDev); - break; - case DSL_FIO_BSP_JTAG_ENABLE: - meierr = IFX_MEI_ArcJtagEnable (pDev, 1); - break; - - case DSL_FIO_BSP_REMOTE: - IFX_MEI_IoctlCopyFrom (from_kernel, (char *) (&i), - (char *) lon, sizeof (int)); - - meierr = IFX_MEI_AdslMailboxIRQEnable (pDev, i); - break; - - case DSL_FIO_BSP_DSL_START: - printk("\n%s: DSL_FIO_BSP_DSL_START\n",__func__); - if ((meierr = IFX_MEI_RunAdslModem (pDev)) != DSL_DEV_MEI_ERR_SUCCESS) { - IFX_MEI_EMSG ("IFX_MEI_RunAdslModem() error..."); - meierr = DSL_DEV_MEI_ERR_FAILURE; - } - break; - - case DSL_FIO_BSP_DEBUG_READ: - case DSL_FIO_BSP_DEBUG_WRITE: - IFX_MEI_IoctlCopyFrom (from_kernel, - (char *) (&debugrdwr), - (char *) lon, - sizeof (debugrdwr)); - - if (command == DSL_FIO_BSP_DEBUG_READ) - meierr = DSL_BSP_MemoryDebugAccess (pDev, - DSL_BSP_MEMORY_READ, - debugrdwr. - iAddress, - debugrdwr. - buffer, - debugrdwr. - iCount); - else - meierr = DSL_BSP_MemoryDebugAccess (pDev, - DSL_BSP_MEMORY_WRITE, - debugrdwr. - iAddress, - debugrdwr. - buffer, - debugrdwr. - iCount); - - IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&debugrdwr), sizeof (debugrdwr)); - break; - case DSL_FIO_BSP_GET_VERSION: - IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&bsp_mei_version), sizeof (DSL_DEV_Version_t)); - break; - - case DSL_FIO_BSP_GET_CHIP_INFO: - bsp_chip_info.major = 1; - bsp_chip_info.minor = IFXMIPS_MPS_CHIPID_VERSION_GET(*IFXMIPS_MPS_CHIPID); - IFX_MEI_IoctlCopyTo (from_kernel, (char *) lon, (char *) (&bsp_chip_info), sizeof (DSL_DEV_HwVersion_t)); - meierr = DSL_DEV_MEI_ERR_SUCCESS; - break; - - case DSL_FIO_BSP_FREE_RESOURCE: - makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_STAT, 4, 0, 1, NULL, m.msg.TxMessage); - if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS) { - meierr = DSL_DEV_MEI_ERR_FAILURE; - return -EIO; - } - IFX_MEI_DMSG("RxMessage[4] = %#x\n", m.msg.RxMessage[4]); - if (!(m.msg.RxMessage[4] & DSL_DEV_STAT_CODESWAP_COMPLETE)) { - meierr = DSL_DEV_MEI_ERR_FAILURE; - return -EAGAIN; - } - IFX_MEI_DMSG("Freeing all memories marked FREE_SHOWTIME\n"); - IFX_MEI_DFEMemoryFree (pDev, FREE_SHOWTIME); - meierr = DSL_DEV_MEI_ERR_SUCCESS; - break; -#ifdef CONFIG_IFXMIPS_AMAZON_SE - case DSL_FIO_ARC_MUX_TEST: - AMAZON_SE_MEI_ARC_MUX_Test(); - break; -#endif - default: -// IFX_MEI_EMSG("Invalid IOCTL command: %d\n"); - break; - } - return meierr; -} - -#ifdef CONFIG_IFXMIPS_AMAZON_SE -void AMAZON_SE_MEI_ARC_MUX_Test(void) -{ - u32 *p, i; - *IFXMIPS_RCU_RST |= IFXMIPS_RCU_RST_REQ_MUX_ARC; - - p = (u32*)(DFE_LDST_BASE_ADDR + IRAM0_BASE); - IFX_MEI_EMSG("Writing to IRAM0(%p)...\n", p); - for (i = 0; i < IRAM0_SIZE/sizeof(u32); i++, p++) { - *p = 0xdeadbeef; - if (*p != 0xdeadbeef) - IFX_MEI_EMSG("%p: %#x\n", p, *p); - } - - p = (u32*)(DFE_LDST_BASE_ADDR + IRAM1_BASE); - IFX_MEI_EMSG("Writing to IRAM1(%p)...\n", p); - for (i = 0; i < IRAM1_SIZE/sizeof(u32); i++, p++) { - *p = 0xdeadbeef; - if (*p != 0xdeadbeef) - IFX_MEI_EMSG("%p: %#x\n", p, *p); - } - - p = (u32*)(DFE_LDST_BASE_ADDR + BRAM_BASE); - IFX_MEI_EMSG("Writing to BRAM(%p)...\n", p); - for (i = 0; i < BRAM_SIZE/sizeof(u32); i++, p++) { - *p = 0xdeadbeef; - if (*p != 0xdeadbeef) - IFX_MEI_EMSG("%p: %#x\n", p, *p); - } - - p = (u32*)(DFE_LDST_BASE_ADDR + XRAM_BASE); - IFX_MEI_EMSG("Writing to XRAM(%p)...\n", p); - for (i = 0; i < XRAM_SIZE/sizeof(u32); i++, p++) { - *p = 0xdeadbeef; - if (*p != 0xdeadbeef) - IFX_MEI_EMSG("%p: %#x\n", p, *p); - } - - p = (u32*)(DFE_LDST_BASE_ADDR + YRAM_BASE); - IFX_MEI_EMSG("Writing to YRAM(%p)...\n", p); - for (i = 0; i < YRAM_SIZE/sizeof(u32); i++, p++) { - *p = 0xdeadbeef; - if (*p != 0xdeadbeef) - IFX_MEI_EMSG("%p: %#x\n", p, *p); - } - - p = (u32*)(DFE_LDST_BASE_ADDR + EXT_MEM_BASE); - IFX_MEI_EMSG("Writing to EXT_MEM(%p)...\n", p); - for (i = 0; i < EXT_MEM_SIZE/sizeof(u32); i++, p++) { - *p = 0xdeadbeef; - if (*p != 0xdeadbeef) - IFX_MEI_EMSG("%p: %#x\n", p, *p); - } - *IFXMIPS_RCU_RST &= ~IFXMIPS_RCU_RST_REQ_MUX_ARC; -} -#endif -int -DSL_BSP_KernelIoctls (DSL_DEV_Device_t * pDev, unsigned int command, - unsigned long lon) -{ - int error = 0; - - error = IFX_MEI_Ioctls (pDev, 1, command, lon); - return error; -} - -static int -IFX_MEI_UserIoctls (DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil, - unsigned int command, unsigned long lon) -{ - int error = 0; - int maj = MAJOR (ino->i_rdev); - int num = MINOR (ino->i_rdev); - DSL_DEV_Device_t *pDev; - - pDev = IFX_BSP_HandleGet (maj, num); - if (pDev == NULL) - return -EIO; - - error = IFX_MEI_Ioctls (pDev, 0, command, lon); - return error; -} - -#ifdef CONFIG_PROC_FS -/* - * Register a callback function for linux proc filesystem - */ -static int -IFX_MEI_InitProcFS (int num) -{ - struct proc_dir_entry *entry; - int i ; - DSL_DEV_Device_t *pDev; - reg_entry_t regs_temp[PROC_ITEMS] = { - /* flag, name, description } */ - {NULL, "arcmsgav", "arc to mei message ", 0}, - {NULL, "cmv_reply", "cmv needs reply", 0}, - {NULL, "cmv_waiting", "waiting for cmv reply from arc", 0}, - {NULL, "modem_ready_cnt", "ARC to MEI indicator count", 0}, - {NULL, "cmv_count", "MEI to ARC CMVs", 0}, - {NULL, "reply_count", "ARC to MEI Reply", 0}, - {NULL, "Recent_indicator", "most recent indicator", 0}, - {NULL, "fw_version", "Firmware Version", 0}, - {NULL, "fw_date", "Firmware Date", 0}, - {NULL, "meminfo", "Memory Allocation Information", 0}, - {NULL, "version", "MEI version information", 0}, - }; - - pDev = &dsl_devices[num]; - if (pDev == NULL) - return -ENOMEM; - - regs_temp[0].flag = &(DSL_DEV_PRIVATE(pDev)->arcmsgav); - regs_temp[1].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_reply); - regs_temp[2].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_waiting); - regs_temp[3].flag = &(DSL_DEV_PRIVATE(pDev)->modem_ready_cnt); - regs_temp[4].flag = &(DSL_DEV_PRIVATE(pDev)->cmv_count); - regs_temp[5].flag = &(DSL_DEV_PRIVATE(pDev)->reply_count); - regs_temp[6].flag = (int *) &(DSL_DEV_PRIVATE(pDev)->Recent_indicator); - - memcpy ((char *) regs[num], (char *) regs_temp, sizeof (regs_temp)); - // procfs - meidir = proc_mkdir (MEI_DIRNAME, NULL); - if (meidir == NULL) { - IFX_MEI_EMSG ("Failed to create /proc/%s\n", MEI_DIRNAME); - return (-ENOMEM); - } - - for (i = 0; i < NUM_OF_REG_ENTRY; i++) { - entry = create_proc_entry (regs[num][i].name, - S_IWUSR | S_IRUSR | S_IRGRP | - S_IROTH, meidir); - if (entry) { - regs[num][i].low_ino = entry->low_ino; - entry->proc_fops = &IFX_MEI_ProcOperations; - } - else { - IFX_MEI_EMSG ("Failed to create /proc/%s/%s\n", MEI_DIRNAME, regs[num][i].name); - return (-ENOMEM); - } - } - return 0; -} - -/* - * Reading function for linux proc filesystem - */ -static int -IFX_MEI_ProcRead (struct file *file, char *buf, size_t nbytes, loff_t * ppos) -{ - int i_ino = (file->f_dentry->d_inode)->i_ino; - char *p = buf; - int i; - int num; - reg_entry_t *entry = NULL; - DSL_DEV_Device_t *pDev = NULL; - DSL_DEV_WinHost_Message_t m; - - for (num = 0; num < BSP_MAX_DEVICES; num++) { - for (i = 0; i < NUM_OF_REG_ENTRY; i++) { - if (regs[num][i].low_ino == (unsigned short)i_ino) { - entry = ®s[num][i]; - pDev = &dsl_devices[num]; - break; - } - } - } - if (entry == NULL) - return -EINVAL; - else if (strcmp(entry->name, "meminfo") == 0) { - if (*ppos > 0) /* Assume reading completed in previous read */ - return 0; - p += sprintf (p, "No Address Size\n"); - for (i = 0; i < MAX_BAR_REGISTERS; i++) { - p += sprintf (p, "BAR[%02d] Addr:0x%08X Size:%lu\n", - i, (u32) DSL_DEV_PRIVATE(pDev)->adsl_mem_info[i].address, - DSL_DEV_PRIVATE(pDev)-> adsl_mem_info[i].size); - //printk( "BAR[%02d] Addr:0x%08X Size:%d\n",i,adsl_mem_info[i].address,adsl_mem_info[i].size); - } - *ppos += (p - buf); - } else if (strcmp(entry->name, "fw_version") == 0) { - if (*ppos > 0) /* Assume reading completed in previous read */ - return 0; - if (DSL_DEV_PRIVATE(pDev)->modem_ready_cnt < 1) - return -EAGAIN; - //major:bits 0-7 - //minor:bits 8-15 - makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 54, 0, 1, NULL, m.msg.TxMessage); - if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS) - return -EIO; - p += sprintf(p, "FW Version: %d.%d.", m.msg.RxMessage[4] & 0xFF, (m.msg.RxMessage[4] >> 8) & 0xFF); - //sub_version:bits 4-7 - //int_version:bits 0-3 - //spl_appl:bits 8-13 - //rel_state:bits 14-15 - makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 54, 1, 1, NULL, m.msg.TxMessage); - if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS) - return -EIO; - p += sprintf(p, "%d.%d.%d.%d\n", - (m.msg.RxMessage[4] >> 4) & 0xF, m.msg.RxMessage[4] & 0xF, - (m.msg.RxMessage[4] >> 14) & 3, (m.msg.RxMessage[4] >> 8) & 0x3F); - *ppos += (p - buf); - } else if (strcmp(entry->name, "fw_date") == 0) { - if (*ppos > 0) /* Assume reading completed in previous read */ - return 0; - if (DSL_DEV_PRIVATE(pDev)->modem_ready_cnt < 1) - return -EAGAIN; - - makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 0, 1, NULL, m.msg.TxMessage); - if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS) - return -EIO; - /* Day/Month */ - p += sprintf(p, "FW Date: %d.%d.", m.msg.RxMessage[4] & 0xFF, (m.msg.RxMessage[4] >> 8) & 0xFF); - - makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 2, 1, NULL, m.msg.TxMessage); - if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS) - return -EIO; - /* Year */ - p += sprintf(p, "%d ", m.msg.RxMessage[4]); - - makeCMV (H2D_CMV_READ, DSL_CMV_GROUP_INFO, 55, 1, 1, NULL, m.msg.TxMessage); - if (DSL_BSP_SendCMV (pDev, m.msg.TxMessage, YES_REPLY, m.msg.RxMessage) != DSL_DEV_MEI_ERR_SUCCESS) - return -EIO; - /* Hour:Minute */ - p += sprintf(p, "%d:%d\n", (m.msg.RxMessage[4] >> 8) & 0xFF, m.msg.RxMessage[4] & 0xFF); - - *ppos += (p - buf); - } else if (strcmp(entry->name, "version") == 0) { - if (*ppos > 0) /* Assume reading completed in previous read */ - return 0; - p += sprintf (p, "IFX MEI V%ld.%ld.%ld\n", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision); - - *ppos += (p - buf); - } else if (entry->flag != (int *) DSL_DEV_PRIVATE(pDev)->Recent_indicator) { - if (*ppos > 0) /* Assume reading completed in previous read */ - return 0; // indicates end of file - p += sprintf (p, "0x%08X\n\n", *(entry->flag)); - *ppos += (p - buf); - if ((p - buf) > nbytes) /* Assume output can be read at one time */ - return -EINVAL; - } else { - if ((int) (*ppos) / ((int) 7) == 16) - return 0; // indicate end of the message - p += sprintf (p, "0x%04X\n\n", *(((u16 *) (entry->flag)) + (int) (*ppos) / ((int) 7))); - *ppos += (p - buf); - } - return p - buf; -} - -/* - * Writing function for linux proc filesystem - */ -static ssize_t -IFX_MEI_ProcWrite (struct file *file, const char *buffer, size_t count, loff_t * ppos) -{ - int i_ino = (file->f_dentry->d_inode)->i_ino; - reg_entry_t *current_reg = NULL; - int i = 0; - int num = 0; - unsigned long newRegValue = 0; - char *endp = NULL; - DSL_DEV_Device_t *pDev = NULL; - - for (num = 0; num < BSP_MAX_DEVICES; num++) { - for (i = 0; i < NUM_OF_REG_ENTRY; i++) { - if (regs[num][i].low_ino == i_ino) { - current_reg = ®s[num][i]; - pDev = &dsl_devices[num]; - break; - } - } - } - if ((current_reg == NULL) - || (current_reg->flag == - (int *) DSL_DEV_PRIVATE(pDev)-> - Recent_indicator)) - return -EINVAL; - - newRegValue = simple_strtoul (buffer, &endp, 0); - *(current_reg->flag) = (int) newRegValue; - return (count + endp - buffer); -} -#endif //CONFIG_PROC_FS - -static int adsl_dummy_ledcallback(void) -{ - return 0; -} - -int ifx_mei_atm_led_blink(void) -{ - return g_adsl_ledcallback(); -} -EXPORT_SYMBOL(ifx_mei_atm_led_blink); - -int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr) -{ - int i; - - if ( is_showtime ) { - *is_showtime = g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 ? 0 : 1; - } - - if ( port_cell ) { - for ( i = 0; i < port_cell->port_num && i < 2; i++ ) - port_cell->tx_link_rate[i] = g_tx_link_rate[i]; - } - - if ( xdata_addr ) { - if ( g_tx_link_rate[0] == 0 && g_tx_link_rate[1] == 0 ) - *xdata_addr = NULL; - else - *xdata_addr = g_xdata_addr; - } - - return 0; -} -EXPORT_SYMBOL(ifx_mei_atm_showtime_check); - -/* - * Writing function for linux proc filesystem - */ -int __init -IFX_MEI_ModuleInit (void) -{ - int i = 0; - - printk ("IFX MEI Version %ld.%02ld.%02ld", bsp_mei_version.major, bsp_mei_version.minor, bsp_mei_version.revision); - - for (i = 0; i < BSP_MAX_DEVICES; i++) { - if (IFX_MEI_InitDevice (i) != 0) { - printk ("%s: Init device fail!\n", __FUNCTION__); - return -EIO; - } - IFX_MEI_InitDevNode (i); -#ifdef CONFIG_PROC_FS - IFX_MEI_InitProcFS (i); -#endif - } - for (i = 0; i <= DSL_BSP_CB_LAST ; i++) - dsl_bsp_event_callback[i].function = NULL; - -#ifdef CONFIG_IFXMIPS_MEI_FW_LOOPBACK - printk(KERN_INFO "[%s %s %d]: Start loopback test...\n", __FILE__, __func__, __LINE__); - DFE_Loopback_Test (); -#endif - - return 0; -} - -void __exit -IFX_MEI_ModuleExit (void) -{ - int i = 0; - int num; - - for (num = 0; num < BSP_MAX_DEVICES; num++) { - IFX_MEI_CleanUpDevNode (num); -#ifdef CONFIG_PROC_FS - for (i = 0; i < NUM_OF_REG_ENTRY; i++) { - remove_proc_entry (regs[num][i].name, meidir); - } -#endif - } - - remove_proc_entry (MEI_DIRNAME, NULL); - for (i = 0; i < BSP_MAX_DEVICES; i++) { - for (i = 0; i < BSP_MAX_DEVICES; i++) { - IFX_MEI_ExitDevice (i); - } - } -} - -/* export function for DSL Driver */ - -/* The functions of MEI_DriverHandleGet and MEI_DriverHandleDelete are -something like open/close in kernel space , where the open could be used -to register a callback for autonomous messages and returns a mei driver context pointer (comparable to the file descriptor in user space) - The context will be required for the multi line chips future! */ - -EXPORT_SYMBOL (DSL_BSP_DriverHandleGet); -EXPORT_SYMBOL (DSL_BSP_DriverHandleDelete); - -EXPORT_SYMBOL (DSL_BSP_ATMLedCBRegister); -EXPORT_SYMBOL (DSL_BSP_ATMLedCBUnregister); -EXPORT_SYMBOL (DSL_BSP_KernelIoctls); -EXPORT_SYMBOL (DSL_BSP_AdslLedInit); -//EXPORT_SYMBOL (DSL_BSP_AdslLedSet); -EXPORT_SYMBOL (DSL_BSP_FWDownload); -EXPORT_SYMBOL (DSL_BSP_Showtime); - -EXPORT_SYMBOL (DSL_BSP_MemoryDebugAccess); -EXPORT_SYMBOL (DSL_BSP_SendCMV); - -// provide a register/unregister function for DSL driver to register a event callback function -EXPORT_SYMBOL (DSL_BSP_EventCBRegister); -EXPORT_SYMBOL (DSL_BSP_EventCBUnregister); - -module_init (IFX_MEI_ModuleInit); -module_exit (IFX_MEI_ModuleExit); diff --git a/package/ifxmips-dsl-api/src/ifxmips_mei_interface.h b/package/ifxmips-dsl-api/src/ifxmips_mei_interface.h deleted file mode 100644 index ffde6113c8..0000000000 --- a/package/ifxmips-dsl-api/src/ifxmips_mei_interface.h +++ /dev/null @@ -1,700 +0,0 @@ -/****************************************************************************** - - Copyright (c) 2009 - Infineon Technologies AG - Am Campeon 1-12; 81726 Munich, Germany - - For licensing information, see the file 'LICENSE' in the root folder of - this software module. - -******************************************************************************/ - -#ifndef IFXMIPS_MEI_H -#define IFXMIPS_MEI_H - -#define CONFIG_DANUBE 1 - -#if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9) -#error Platform undefined!!! -#endif - -#ifdef IFX_MEI_BSP -/** This is the character datatype. */ -typedef char DSL_char_t; -/** This is the unsigned 8-bit datatype. */ -typedef unsigned char DSL_uint8_t; -/** This is the signed 8-bit datatype. */ -typedef signed char DSL_int8_t; -/** This is the unsigned 16-bit datatype. */ -typedef unsigned short DSL_uint16_t; -/** This is the signed 16-bit datatype. */ -typedef signed short DSL_int16_t; -/** This is the unsigned 32-bit datatype. */ -typedef unsigned long DSL_uint32_t; -/** This is the signed 32-bit datatype. */ -typedef signed long DSL_int32_t; -/** This is the float datatype. */ -typedef float DSL_float_t; -/** This is the void datatype. */ -typedef void DSL_void_t; -/** integer type, width is depending on processor arch */ -typedef int DSL_int_t; -/** unsigned integer type, width is depending on processor arch */ -typedef unsigned int DSL_uint_t; -typedef struct file DSL_DRV_file_t; -typedef struct inode DSL_DRV_inode_t; - -/** - * Defines all possible CMV groups - * */ -typedef enum { - DSL_CMV_GROUP_CNTL = 1, - DSL_CMV_GROUP_STAT = 2, - DSL_CMV_GROUP_INFO = 3, - DSL_CMV_GROUP_TEST = 4, - DSL_CMV_GROUP_OPTN = 5, - DSL_CMV_GROUP_RATE = 6, - DSL_CMV_GROUP_PLAM = 7, - DSL_CMV_GROUP_CNFG = 8 -} DSL_CmvGroup_t; -/** - * Defines all opcode types - * */ -typedef enum { - H2D_CMV_READ = 0x00, - H2D_CMV_WRITE = 0x04, - H2D_CMV_INDICATE_REPLY = 0x10, - H2D_ERROR_OPCODE_UNKNOWN =0x20, - H2D_ERROR_CMV_UNKNOWN =0x30, - - D2H_CMV_READ_REPLY =0x01, - D2H_CMV_WRITE_REPLY = 0x05, - D2H_CMV_INDICATE = 0x11, - D2H_ERROR_OPCODE_UNKNOWN = 0x21, - D2H_ERROR_CMV_UNKNOWN = 0x31, - D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41, - D2H_ERROR_CMV_WRITE_ONLY = 0x51, - D2H_ERROR_CMV_READ_ONLY = 0x61, - - H2D_DEBUG_READ_DM = 0x02, - H2D_DEBUG_READ_PM = 0x06, - H2D_DEBUG_WRITE_DM = 0x0a, - H2D_DEBUG_WRITE_PM = 0x0e, - - D2H_DEBUG_READ_DM_REPLY = 0x03, - D2H_DEBUG_READ_FM_REPLY = 0x07, - D2H_DEBUG_WRITE_DM_REPLY = 0x0b, - D2H_DEBUG_WRITE_FM_REPLY = 0x0f, - D2H_ERROR_ADDR_UNKNOWN = 0x33, - - D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1 -} DSL_CmvOpcode_t; - -/* mutex macros */ -#define MEI_MUTEX_INIT(id,flag) \ - sema_init(&id,flag) -#define MEI_MUTEX_LOCK(id) \ - down_interruptible(&id) -#define MEI_MUTEX_UNLOCK(id) \ - up(&id) -#define MEI_WAIT(ms) \ - {\ - set_current_state(TASK_INTERRUPTIBLE);\ - schedule_timeout(ms);\ - } -#define MEI_INIT_WAKELIST(name,queue) \ - init_waitqueue_head(&queue) - -/* wait for an event, timeout is measured in ms */ -#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\ - interruptible_sleep_on_timeout(&ev,timeout * HZ / 1000) -#define MEI_WAKEUP_EVENT(ev)\ - wake_up_interruptible(&ev) -#endif /* IFX_MEI_BSP */ - -/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ -#define ME_DX_DATA (0x0000) -#define ME_VERSION (0x0004) -#define ME_ARC_GP_STAT (0x0008) -#define ME_DX_STAT (0x000C) -#define ME_DX_AD (0x0010) -#define ME_DX_MWS (0x0014) -#define ME_ME2ARC_INT (0x0018) -#define ME_ARC2ME_STAT (0x001C) -#define ME_ARC2ME_MASK (0x0020) -#define ME_DBG_WR_AD (0x0024) -#define ME_DBG_RD_AD (0x0028) -#define ME_DBG_DATA (0x002C) -#define ME_DBG_DECODE (0x0030) -#define ME_CONFIG (0x0034) -#define ME_RST_CTRL (0x0038) -#define ME_DBG_MASTER (0x003C) -#define ME_CLK_CTRL (0x0040) -#define ME_BIST_CTRL (0x0044) -#define ME_BIST_STAT (0x0048) -#define ME_XDATA_BASE_SH (0x004c) -#define ME_XDATA_BASE (0x0050) -#define ME_XMEM_BAR_BASE (0x0054) -#define ME_XMEM_BAR0 (0x0054) -#define ME_XMEM_BAR1 (0x0058) -#define ME_XMEM_BAR2 (0x005C) -#define ME_XMEM_BAR3 (0x0060) -#define ME_XMEM_BAR4 (0x0064) -#define ME_XMEM_BAR5 (0x0068) -#define ME_XMEM_BAR6 (0x006C) -#define ME_XMEM_BAR7 (0x0070) -#define ME_XMEM_BAR8 (0x0074) -#define ME_XMEM_BAR9 (0x0078) -#define ME_XMEM_BAR10 (0x007C) -#define ME_XMEM_BAR11 (0x0080) -#define ME_XMEM_BAR12 (0x0084) -#define ME_XMEM_BAR13 (0x0088) -#define ME_XMEM_BAR14 (0x008C) -#define ME_XMEM_BAR15 (0x0090) -#define ME_XMEM_BAR16 (0x0094) - -#define WHILE_DELAY 20000 -/* -** Define where in ME Processor's memory map the Stratify chip lives -*/ - -#define MAXSWAPSIZE (8 * 1024) //8k *(32bits) - -// Mailboxes -#define MSG_LENGTH 16 // x16 bits -#define YES_REPLY 1 -#define NO_REPLY 0 - -#define CMV_TIMEOUT 1000 //jiffies - -// Block size per BAR -#define SDRAM_SEGMENT_SIZE (64*1024) -// Number of Bar registers -#define MAX_BAR_REGISTERS (17) - -#define XDATA_REGISTER (15) - -// ARC register addresss -#define ARC_STATUS 0x0 -#define ARC_LP_START 0x2 -#define ARC_LP_END 0x3 -#define ARC_DEBUG 0x5 -#define ARC_INT_MASK 0x10A - -#define IRAM0_BASE (0x00000) -#define IRAM1_BASE (0x04000) -#if defined(CONFIG_DANUBE) -#define BRAM_BASE (0x0A000) -#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9) -#define BRAM_BASE (0x08000) -#endif -#define XRAM_BASE (0x18000) -#define YRAM_BASE (0x1A000) -#define EXT_MEM_BASE (0x80000) -#define ARC_GPIO_CTRL (0xC030) -#define ARC_GPIO_DATA (0xC034) - -#define IRAM0_SIZE (16*1024) -#define IRAM1_SIZE (16*1024) -#define BRAM_SIZE (12*1024) -#define XRAM_SIZE (8*1024) -#define YRAM_SIZE (8*1024) -#define EXT_MEM_SIZE (1536*1024) - -#define ADSL_BASE (0x20000) -#define CRI_BASE (ADSL_BASE + 0x11F00) -#define CRI_CCR0 (CRI_BASE + 0x00) -#define CRI_RST (CRI_BASE + 0x04*4) -#define ADSL_DILV_BASE (ADSL_BASE+0x20000) - -// -#define IRAM0_ADDR_BIT_MASK 0xFFF -#define IRAM1_ADDR_BIT_MASK 0xFFF -#define BRAM_ADDR_BIT_MASK 0xFFF -#define RX_DILV_ADDR_BIT_MASK 0x1FFF - -/*** Bit definitions ***/ -#define ARC_AUX_HALT (1 << 25) -#define ARC_DEBUG_HALT (1 << 1) -#define FALSE 0 -#define TRUE 1 -#define BIT0 (1<<0) -#define BIT1 (1<<1) -#define BIT2 (1<<2) -#define BIT3 (1<<3) -#define BIT4 (1<<4) -#define BIT5 (1<<5) -#define BIT6 (1<<6) -#define BIT7 (1<<7) -#define BIT8 (1<<8) -#define BIT9 (1<<9) -#define BIT10 (1<<10) -#define BIT11 (1<<11) -#define BIT12 (1<<12) -#define BIT13 (1<<13) -#define BIT14 (1<<14) -#define BIT15 (1<<15) -#define BIT16 (1<<16) -#define BIT17 (1<<17) -#define BIT18 (1<<18) -#define BIT19 (1<<19) -#define BIT20 (1<<20) -#define BIT21 (1<<21) -#define BIT22 (1<<22) -#define BIT23 (1<<23) -#define BIT24 (1<<24) -#define BIT25 (1<<25) -#define BIT26 (1<<26) -#define BIT27 (1<<27) -#define BIT28 (1<<28) -#define BIT29 (1<<29) -#define BIT30 (1<<30) -#define BIT31 (1<<31) - -// CRI_CCR0 Register definitions -#define CLK_2M_MODE_ENABLE BIT6 -#define ACL_CLK_MODE_ENABLE BIT4 -#define FDF_CLK_MODE_ENABLE BIT2 -#define STM_CLK_MODE_ENABLE BIT0 - -// CRI_RST Register definitions -#define FDF_SRST BIT3 -#define MTE_SRST BIT2 -#define FCI_SRST BIT1 -#define AAI_SRST BIT0 - -// MEI_TO_ARC_INTERRUPT Register definitions -#define MEI_TO_ARC_INT1 BIT3 -#define MEI_TO_ARC_INT0 BIT2 -#define MEI_TO_ARC_CS_DONE BIT1 //need to check -#define MEI_TO_ARC_MSGAV BIT0 - -// ARC_TO_MEI_INTERRUPT Register definitions -#define ARC_TO_MEI_INT1 BIT8 -#define ARC_TO_MEI_INT0 BIT7 -#define ARC_TO_MEI_CS_REQ BIT6 -#define ARC_TO_MEI_DBG_DONE BIT5 -#define ARC_TO_MEI_MSGACK BIT4 -#define ARC_TO_MEI_NO_ACCESS BIT3 -#define ARC_TO_MEI_CHECK_AAITX BIT2 -#define ARC_TO_MEI_CHECK_AAIRX BIT1 -#define ARC_TO_MEI_MSGAV BIT0 - -// ARC_TO_MEI_INTERRUPT_MASK Register definitions -#define GP_INT1_EN BIT8 -#define GP_INT0_EN BIT7 -#define CS_REQ_EN BIT6 -#define DBG_DONE_EN BIT5 -#define MSGACK_EN BIT4 -#define NO_ACC_EN BIT3 -#define AAITX_EN BIT2 -#define AAIRX_EN BIT1 -#define MSGAV_EN BIT0 - -#define MEI_SOFT_RESET BIT0 - -#define HOST_MSTR BIT0 - -#define JTAG_MASTER_MODE 0x0 -#define MEI_MASTER_MODE HOST_MSTR - -// MEI_DEBUG_DECODE Register definitions -#define MEI_DEBUG_DEC_MASK (0x3) -#define MEI_DEBUG_DEC_AUX_MASK (0x0) -#define ME_DBG_DECODE_DMP1_MASK (0x1) -#define MEI_DEBUG_DEC_DMP2_MASK (0x2) -#define MEI_DEBUG_DEC_CORE_MASK (0x3) - -#define AUX_STATUS (0x0) -#define AUX_ARC_GPIO_CTRL (0x10C) -#define AUX_ARC_GPIO_DATA (0x10D) -// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate -// page swap requests. -#if defined(CONFIG_DANUBE) -#define OMBOX_BASE 0xDF80 -#define ARC_TO_MEI_MAILBOX 0xDFA0 -#define IMBOX_BASE 0xDFC0 -#define MEI_TO_ARC_MAILBOX 0xDFD0 -#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9) -#define OMBOX_BASE 0xAF80 -#define ARC_TO_MEI_MAILBOX 0xAFA0 -#define IMBOX_BASE 0xAFC0 -#define MEI_TO_ARC_MAILBOX 0xAFD0 -#endif - -#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C) -#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C) -#define OMBOX1 (OMBOX_BASE+0x4) - -// Codeswap request messages are indicated by setting BIT31 -#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000) - -// Clear Eoc messages received are indicated by setting BIT17 -#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000) -#define OMB_REBOOT_INTERRUPT_CODE (1 << 18) - -/* -** Swap page header -*/ -// Page must be loaded at boot time if size field has BIT31 set -#define BOOT_FLAG (BIT31) -#define BOOT_FLAG_MASK ~BOOT_FLAG - -#define FREE_RELOAD 1 -#define FREE_SHOWTIME 2 -#define FREE_ALL 3 - -// marcos -#define IFX_MEI_WRITE_REGISTER_L(data,addr) *((volatile u32*)(addr)) = (u32)(data) -#define IFX_MEI_READ_REGISTER_L(addr) (*((volatile u32*)(addr))) -#define SET_BIT(reg, mask) reg |= (mask) -#define CLEAR_BIT(reg, mask) reg &= (~mask) -#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) -//#define SET_BITS(reg, mask) SET_BIT(reg, mask) -#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} - -#define ALIGN_SIZE ( 1L<<10 ) //1K size align -#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) ) - -// swap marco -#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);} -#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);} - - -#ifdef CONFIG_PROC_FS -typedef struct reg_entry -{ - int *flag; - char name[30]; /* big enough to hold names */ - char description[100]; /* big enough to hold description */ - unsigned short low_ino; -} reg_entry_t; -#endif -// Swap page header describes size in 32-bit words, load location, and image offset -// for program and/or data segments -typedef struct _arc_swp_page_hdr { - u32 p_offset; //Offset bytes of progseg from beginning of image - u32 p_dest; //Destination addr of progseg on processor - u32 p_size; //Size in 32-bitwords of program segment - u32 d_offset; //Offset bytes of dataseg from beginning of image - u32 d_dest; //Destination addr of dataseg on processor - u32 d_size; //Size in 32-bitwords of data segment -} ARC_SWP_PAGE_HDR; - -/* -** Swap image header -*/ -#define GET_PROG 0 // Flag used for program mem segment -#define GET_DATA 1 // Flag used for data mem segment - -// Image header contains size of image, checksum for image, and count of -// page headers. Following that are 'count' page headers followed by -// the code and/or data segments to be loaded -typedef struct _arc_img_hdr { - u32 size; // Size of binary image in bytes - u32 checksum; // Checksum for image - u32 count; // Count of swp pages in image - ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy -} ARC_IMG_HDR; - -typedef struct smmu_mem_info { - int type; - int boot; - unsigned long nCopy; - unsigned long size; - unsigned char *address; - unsigned char *org_address; -} smmu_mem_info_t; - -#ifdef __KERNEL__ -typedef struct ifx_mei_device_private { - int modem_ready; - int arcmsgav; - int cmv_reply; - int cmv_waiting; - // Mei to ARC CMV count, reply count, ARC Indicator count - int modem_ready_cnt; - int cmv_count; - int reply_count; - unsigned long image_size; - int nBar; - u16 Recent_indicator[MSG_LENGTH]; - - u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4))); - - smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS]; - ARC_IMG_HDR *img_hdr; - // to wait for arc cmv reply, sleep on wait_queue_arcmsgav; - wait_queue_head_t wait_queue_arcmsgav; - wait_queue_head_t wait_queue_modemready; - struct semaphore mei_cmv_sema; -} ifx_mei_device_private_t; -#endif -typedef struct winhost_message { - union { - u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4))); - u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4))); - } msg; -} DSL_DEV_WinHost_Message_t; -/******************************************************************************************************** - * DSL CPE API Driver Stack Interface Definitions - * *****************************************************************************************************/ -/** IOCTL codes for bsp driver */ -#define DSL_IOC_MEI_BSP_MAGIC 's' - -#define DSL_FIO_BSP_DSL_START _IO (DSL_IOC_MEI_BSP_MAGIC, 0) -#define DSL_FIO_BSP_RUN _IO (DSL_IOC_MEI_BSP_MAGIC, 1) -#define DSL_FIO_BSP_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 2) -#define DSL_FIO_BSP_RESET _IO (DSL_IOC_MEI_BSP_MAGIC, 3) -#define DSL_FIO_BSP_REBOOT _IO (DSL_IOC_MEI_BSP_MAGIC, 4) -#define DSL_FIO_BSP_HALT _IO (DSL_IOC_MEI_BSP_MAGIC, 5) -#define DSL_FIO_BSP_BOOTDOWNLOAD _IO (DSL_IOC_MEI_BSP_MAGIC, 6) -#define DSL_FIO_BSP_JTAG_ENABLE _IO (DSL_IOC_MEI_BSP_MAGIC, 7) -#define DSL_FIO_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 8) -#define DSL_FIO_ARC_MUX_TEST _IO (DSL_IOC_MEI_BSP_MAGIC, 9) -#define DSL_FIO_BSP_REMOTE _IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32) -#define DSL_FIO_BSP_GET_BASE_ADDRESS _IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32) -#define DSL_FIO_BSP_IS_MODEM_READY _IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32) -#define DSL_FIO_BSP_GET_VERSION _IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t) -#define DSL_FIO_BSP_CMV_WINHOST _IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t) -#define DSL_FIO_BSP_CMV_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t) -#define DSL_FIO_BSP_CMV_WRITE _IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t) -#define DSL_FIO_BSP_DEBUG_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t) -#define DSL_FIO_BSP_DEBUG_WRITE _IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t) -#define DSL_FIO_BSP_GET_CHIP_INFO _IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t) - -#define DSL_DEV_MEIDEBUG_BUFFER_SIZES 512 - -typedef struct DSL_DEV_MeiDebug -{ - DSL_uint32_t iAddress; - DSL_uint32_t iCount; - DSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES]; -} DSL_DEV_MeiDebug_t; /* meidebug */ - -/** - * Structure is used for debug access only. - * Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */ -typedef struct struct_meireg -{ - /* - * Specifies that address for debug access */ - unsigned long iAddress; - /* - * Specifies the pointer to the data that has to be written or returns a - * pointer to the data that has been read out*/ - unsigned long iData; -} DSL_DEV_MeiReg_t; /* meireg */ - -typedef struct DSL_DEV_Device -{ - DSL_int_t nInUse; /* modem state, update by bsp driver, */ - DSL_void_t *pPriv; - DSL_uint32_t base_address; /* mei base address */ - DSL_int_t nIrq[2]; /* irq number */ -#define IFX_DFEIR 0 -#define IFX_DYING_GASP 1 - DSL_DEV_MeiDebug_t lop_debugwr; /* dying gasp */ -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)) - struct module *owner; -#endif -} DSL_DEV_Device_t; /* ifx_adsl_device_t */ - -#define DSL_DEV_PRIVATE(dev) ((ifx_mei_device_private_t*)(dev->pPriv)) - -typedef struct DSL_DEV_Version /* ifx_adsl_bsp_version */ -{ - unsigned long major; - unsigned long minor; - unsigned long revision; -} DSL_DEV_Version_t; /* ifx_adsl_bsp_version_t */ - -typedef struct DSL_DEV_ChipInfo -{ - unsigned long major; - unsigned long minor; -} DSL_DEV_HwVersion_t; - -typedef struct -{ - DSL_uint8_t dummy; -} DSL_DEV_DeviceConfig_t; - -/** error code definitions */ -typedef enum DSL_DEV_MeiError -{ - DSL_DEV_MEI_ERR_SUCCESS = 0, - DSL_DEV_MEI_ERR_FAILURE = -1, - DSL_DEV_MEI_ERR_MAILBOX_FULL = -2, - DSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3, - DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4 -} DSL_DEV_MeiError_t; /* MEI_ERROR */ - -typedef enum { - DSL_BSP_MEMORY_READ=0, - DSL_BSP_MEMORY_WRITE, -} DSL_BSP_MemoryAccessType_t; /* ifx_adsl_memory_access_type_t */ - -typedef enum -{ - DSL_LED_LINK_ID=0, - DSL_LED_DATA_ID -} DSL_DEV_LedId_t; /* ifx_adsl_led_id_t */ - -typedef enum -{ - DSL_LED_LINK_TYPE=0, - DSL_LED_DATA_TYPE -} DSL_DEV_LedType_t; /* ifx_adsl_led_type_t */ - -typedef enum -{ - DSL_LED_HD_CPU=0, - DSL_LED_HD_FW -} DSL_DEV_LedHandler_t; /* ifx_adsl_led_handler_t */ - -typedef enum { - DSL_LED_ON=0, - DSL_LED_OFF, - DSL_LED_FLASH, -} DSL_DEV_LedMode_t; /* ifx_adsl_led_mode_t */ - -typedef enum { - DSL_CPU_HALT=0, - DSL_CPU_RUN, - DSL_CPU_RESET, -} DSL_DEV_CpuMode_t; /* ifx_adsl_cpu_mode_t */ - -#if 0 -typedef enum { - DSL_BSP_EVENT_DYING_GASP = 0, - DSL_BSP_EVENT_CEOC_IRQ, -} DSL_BSP_Event_id_t; /* ifx_adsl_event_id_t */ - -typedef union DSL_BSP_CB_Param -{ - DSL_uint32_t nIrqMessage; -} DSL_BSP_CB_Param_t; /* ifx_adsl_cbparam_t */ - -typedef struct DSL_BSP_CB_Event -{ - DSL_BSP_Event_id_t nID; - DSL_DEV_Device_t *pDev; - DSL_BSP_CB_Param_t *pParam; -} DSL_BSP_CB_Event_t; /* ifx_adsl_cb_event_t */ -#endif - -/* external functions (from the BSP Driver) */ -extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int); -extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *); -extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *); -extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long); -extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *); -extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t); -extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t); -extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void)); -extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t); -extern volatile DSL_DEV_Device_t *adsl_dev; - -/** - * Dummy structure by now to show mechanism of extended data that will be - * provided within event callback itself. - * */ -typedef struct -{ - /** - * Dummy value */ - DSL_uint32_t nDummy1; -} DSL_BSP_CB_Event1DataDummy_t; - -/** - * Dummy structure by now to show mechanism of extended data that will be - * provided within event callback itself. - * */ -typedef struct -{ - /** - * Dummy value */ - DSL_uint32_t nDummy2; -} DSL_BSP_CB_Event2DataDummy_t; - -/** - * encapsulate all data structures that are necessary for status event - * callbacks. - * */ -typedef union -{ - DSL_BSP_CB_Event1DataDummy_t dataEvent1; - DSL_BSP_CB_Event2DataDummy_t dataEvent2; -} DSL_BSP_CB_DATA_Union_t; - - -typedef enum -{ - /** - * Informs the upper layer driver (DSL CPE API) about a reboot request from the - * firmware. - * \note This event does NOT include any additional data. - * More detailed information upon reboot reason has to be requested from - * upper layer software via CMV (INFO 109) if necessary. */ - DSL_BSP_CB_FIRST = 0, - DSL_BSP_CB_DYING_GASP, - DSL_BSP_CB_CEOC_IRQ, - DSL_BSP_CB_FIRMWARE_REBOOT, - /** - * Delimiter only */ - DSL_BSP_CB_LAST -} DSL_BSP_CB_Type_t; - -/** - * Specifies the common event type that has to be used for registering and - * signalling of interrupts/autonomous status events from MEI BSP Driver. - * - * \param pDev - * Context pointer from MEI BSP Driver. - * - * \param IFX_ADSL_BSP_CallbackType_t - * Specifies the event callback type (reason of callback). Regrading to the - * setting of this value the data which is included in the following union - * might have different meanings. - * Please refer to the description of the union to get information about the - * meaning of the included data. - * - * \param pData - * Data according to \ref DSL_BSP_CB_DATA_Union_t. - * If this pointer is NULL there is no additional data available. - * - * \return depending on event - */ -typedef int (*DSL_BSP_EventCallback_t) -( - DSL_DEV_Device_t *pDev, - DSL_BSP_CB_Type_t nCallbackType, - DSL_BSP_CB_DATA_Union_t *pData -); - -typedef struct { - DSL_BSP_EventCallback_t function; - DSL_BSP_CB_Type_t event; - DSL_BSP_CB_DATA_Union_t *pData; -} DSL_BSP_EventCallBack_t; - -extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *); -extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *); - -/** Modem states */ -#define DSL_DEV_STAT_InitState 0x0000 -#define DSL_DEV_STAT_ReadyState 0x0001 -#define DSL_DEV_STAT_FailState 0x0002 -#define DSL_DEV_STAT_IdleState 0x0003 -#define DSL_DEV_STAT_QuietState 0x0004 -#define DSL_DEV_STAT_GhsState 0x0005 -#define DSL_DEV_STAT_FullInitState 0x0006 -#define DSL_DEV_STAT_ShowTimeState 0x0007 -#define DSL_DEV_STAT_FastRetrainState 0x0008 -#define DSL_DEV_STAT_LoopDiagMode 0x0009 -#define DSL_DEV_STAT_ShortInit 0x000A /* Bis short initialization */ - -#define DSL_DEV_STAT_CODESWAP_COMPLETE 0x0002 - -#endif //IFXMIPS_MEI_H diff --git a/package/ifxmips-dsl-control/Makefile b/package/ifxmips-dsl-control/Makefile deleted file mode 100644 index e589bdc798..0000000000 --- a/package/ifxmips-dsl-control/Makefile +++ /dev/null @@ -1,88 +0,0 @@ -# -# Copyright (C) 2009 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -# ralph / blogic - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_BASE_NAME:=dsl_cpe_control_danube -PKG_VERSION:=3.24.4.4 -PKG_RELEASE:=1 -PKG_SOURCE:=$(PKG_BASE_NAME)-$(PKG_VERSION).tar.gz -PKG_BUILD_DIR:=$(BUILD_DIR)/dsl_cpe_control-$(PKG_VERSION) -PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources/ -PKG_MD5SUM:=ee315306626b68794d3d3636dabfe161 - -include $(INCLUDE_DIR)/package.mk - -define Package/ifxmips-dsl-control - SECTION:=net - CATEGORY:=Network - TITLE:=DSL CPE control application - URL:=http://www.infineon.com/ - MAINTAINER:=Infineon Technologies AG / Lantiq / blogic@openwrt.org - DEPENDS:=+kmod-ifxmips-dsl-api +libpthread @BROKEN -endef - -define Package/ifxmips-dsl-control/description - Infineon DSL CPE API for Amazon SE, Danube and Vinax. - This package contains the DSL CPE control application for Amazon SE & Danube. - - Supported Devices: - - Amazon SE - - Danube - - This package was kindly contributed to openwrt by Infineon/Lantiq -endef - -IFX_DSL_MAX_DEVICE=1 -IFX_DSL_LINES_PER_DEVICE=1 -IFX_DSL_CHANNELS_PER_LINE=1 -#CONFIG_IFX_CLI=y - -CONFIGURE_ARGS += \ - --with-max-device="$(IFX_DSL_MAX_DEVICE)" \ - --with-lines-per-device="$(IFX_DSL_LINES_PER_DEVICE)" \ - --with-channels-per-line="$(IFX_DSL_CHANNELS_PER_LINE)" \ - --enable-danube \ - --enable-driver-include="-I$(STAGING_DIR)/usr/include" \ - --enable-debug-prints \ - --enable-add-appl-cflags="-DMAX_CLI_PIPES=2" \ - --enable-cmv-scripts \ - --enable-debug-tool-interface \ - --enable-adsl-led \ - --enable-dsl-ceoc \ - --enable-script-notification \ - --enable-dsl-pm \ - --enable-dsl-pm-total \ - --enable-dsl-pm-history \ - --enable-dsl-pm-showtime \ - --enable-dsl-pm-channel-counters \ - --enable-dsl-pm-datapath-counters \ - --enable-dsl-pm-line-counters \ - --enable-dsl-pm-channel-thresholds \ - --enable-dsl-pm-datapath-thresholds \ - --enable-dsl-pm-line-thresholds \ - --enable-dsl-pm-optional-parameters - -ifeq ($(CONFIG_IFX_CLI),y) -CONFIGURE_ARGS += \ - --enable-cli-support \ - --enable-soap-support -endif - -TARGET_CFLAGS += -I$(LINUX_DIR)/include - -define Package/ifxmips-dsl-control/install - $(INSTALL_DIR) $(1)/etc/init.d - $(INSTALL_BIN) ./files/ifx_cpe_control_init.sh $(1)/etc/init.d/ - - $(INSTALL_DIR) $(1)/sbin - $(INSTALL_BIN) $(PKG_BUILD_DIR)/src/dsl_cpe_control $(1)/sbin -endef - -$(eval $(call BuildPackage,ifxmips-dsl-control)) diff --git a/package/ifxmips-dsl-control/files/ifx_cpe_control_init.sh b/package/ifxmips-dsl-control/files/ifx_cpe_control_init.sh deleted file mode 100644 index 91316938ce..0000000000 --- a/package/ifxmips-dsl-control/files/ifx_cpe_control_init.sh +++ /dev/null @@ -1,21 +0,0 @@ -#!/bin/sh /etc/rc.common -# Copyright (C) 2008 OpenWrt.org -START=99 - -start() { - - # start CPE dsl daemon in the background - /sbin/dsl_cpe_control -i -f /lib/firmware/ModemHWE.bin & - -# PS=`ps` -# echo $PS | grep -q dsl_cpe_control && { -# # workaround for nfs: allow write to pipes for non-root -# while [ ! -e /tmp/pipe/dsl_cpe1_ack ] ; do sleep 1; done -# chmod a+w /tmp/pipe/dsl_* -# } - echo $PS | grep -q dsl_cpe_control || { - echo "Start of dsl_cpe_control failed!!!" - false - } - -} diff --git a/package/ifxos/Makefile b/package/ifxos/Makefile deleted file mode 100644 index 1ed61dd257..0000000000 --- a/package/ifxos/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# Copyright (C) 2009-2010 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=lib_ifxos -PKG_VERSION:=1.5.12 -PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz -PKG_RELEASE:=1 -PKG_SOURCE_URL:=http://mirror2.openwrt.org/sources -PKG_MD5SUM:=ba775356bdd5e1b73b3e11a152710ed6 - -include $(INCLUDE_DIR)/package.mk - -define KernelPackage/ifxos - SUBMENU:=Other modules - TITLE:=Lantiq OS abstraction library - URL:=http://www.lantiq.com/ - MAINTAINER:=Lantiq - DEPENDS:=@TARGET_ifxmips @BROKEN - FILES:=$(PKG_BUILD_DIR)/src/drv_ifxos.$(LINUX_KMOD_SUFFIX) - AUTOLOAD:=$(call AutoLoad,10,drv_ifxos) -endef - -CONFIGURE_ARGS += \ - ARCH=$(LINUX_KARCH) \ - --enable-linux-26 \ - --enable-kernelbuild="$(LINUX_DIR)" \ - --enable-kernelincl="$(LINUX_DIR)/include" \ - --enable-add_drv_cflags="-fno-pic -mno-abicalls -mlong-calls -G 0" - -define Build/Configure - (cd $(PKG_BUILD_DIR); aclocal && autoconf && automake) - $(call Build/Configure/Default) -endef - -define Build/InstallDev - $(INSTALL_DIR) $(1)/usr/{lib,include/ifxos} - $(CP) $(PKG_BUILD_DIR)/src/include/* $(1)/usr/include/ifxos - mkdir -p $(1)/usr/lib - $(CP) $(PKG_BUILD_DIR)/src/libifxos.a $(1)/usr/lib/libifxos.a -endef - -$(eval $(call KernelPackage,ifxos)) diff --git a/package/ifxos/patches/100-portability.patch b/package/ifxos/patches/100-portability.patch deleted file mode 100644 index 51d6bbd165..0000000000 --- a/package/ifxos/patches/100-portability.patch +++ /dev/null @@ -1,28 +0,0 @@ -Index: lib_ifxos-1.5.12/src/Makefile.am -=================================================================== ---- lib_ifxos-1.5.12.orig/src/Makefile.am 2010-01-08 18:12:15.000000000 +0100 -+++ lib_ifxos-1.5.12/src/Makefile.am 2010-03-31 18:56:12.000000000 +0200 -@@ -639,7 +639,7 @@ - drv_ifxos_OBJS = "$(subst .c,.o,$(filter %.c,$(drv_ifxos_SOURCES)))" - - drv_ifxos.ko: $(drv_ifxos_SOURCES) -- @echo -e "drv_ifxos: Making Linux 2.6.x kernel object" -+ @echo "drv_ifxos: Making Linux 2.6.x kernel object" - if test ! -e common/ifxos_debug.c ; then \ - echo "copy source files (as links only!)"; \ - for f in $(filter %.c,$(drv_ifxos_SOURCES)); do \ -@@ -647,10 +647,10 @@ - cp -s $(addprefix @abs_srcdir@/,$$f) $(PWD)/`dirname $$f`/ ; \ - done \ - fi -- @echo -e "# drv_ifxos: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild -- @echo -e "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild -- @echo -e "$(subst .ko,,$@)-y := $(drv_ifxos_OBJS)" >> $(PWD)/Kbuild -- @echo -e "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_ifxos_CFLAGS) $(DSL_DRIVER_INCL_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild -+ @echo "# drv_ifxos: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild -+ @echo "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild -+ @echo "$(subst .ko,,$@)-y := $(drv_ifxos_OBJS)" >> $(PWD)/Kbuild -+ @echo "EXTRA_CFLAGS := $(CFLAGS) -DHAVE_CONFIG_H $(drv_ifxos_CFLAGS) $(DSL_DRIVER_INCL_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild - $(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules - - clean-generic: diff --git a/package/uboot-ifxmips/Config.in b/package/uboot-ifxmips/Config.in deleted file mode 100644 index afd1920877..0000000000 --- a/package/uboot-ifxmips/Config.in +++ /dev/null @@ -1,9 +0,0 @@ -menu "Configuration" - depends on PACKAGE_uboot-ifxmips - -config IFXMIPS_UBOOT_A800 - bool "add ARV452 Switch bringup hack" - help - Say Y, if you have a arv452 board (wav-281, A800, ..) - -endmenu diff --git a/package/uboot-ifxmips/Makefile b/package/uboot-ifxmips/Makefile deleted file mode 100644 index 736e322c3c..0000000000 --- a/package/uboot-ifxmips/Makefile +++ /dev/null @@ -1,84 +0,0 @@ -# -# Copyright (C) 2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/kernel.mk - -PKG_NAME:=u-boot -PKG_VERSION:=1.1.5 -PKG_RELEASE:=2 - -PKG_BUILD_DIR:=$(KERNEL_BUILD_DIR)/$(PKG_NAME)-$(PKG_VERSION) -PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 -PKG_SOURCE_URL:=ftp://ftp.denx.de/pub/u-boot -PKG_MD5SUM:=579707c8ecbf1ab4127285d2aac2a9ee -PKG_TARGETS:=bin - -include $(INCLUDE_DIR)/package.mk - -define Package/uboot-ifxmips - SECTION:=boot - CATEGORY:=Boot Loaders - DEPENDS:=@TARGET_ifxmips @BROKEN - TITLE:=U-Boot for Infineon MIPS boards - URL:=http://www.denx.de/wiki/U-Boot - MENU:=1 -endef - -define Build/Prepare - $(call Build/Prepare/Default) - cp -r $(CP_OPTS) ./files/* $(PKG_BUILD_DIR) - find $(PKG_BUILD_DIR) -name .svn | $(XARGS) rm -rf -endef - -define Package/uboot-ifxmips/config - source "$(SOURCE)/Config.in" -endef - -UBOOT_CONFIG:=danube - -UBOOT_MAKE_OPTS:=\ - CROSS_COMPILE=$(TARGET_CROSS) \ - CROSS_COMPILE_UCLIBC=1 \ - COMPRESS=lzma \ - PLATFORM_CPU=mips32r2 \ - UBOOT_RAM_TEXT_BASE=0xA0400000 - -A800_FIX:= -ifeq ($(CONFIG_IFXMIPS_UBOOT_A800),y) -A800_FIX += -DA800_SWITCH -endif - -define Build/Configure - $(MAKE) -s -C $(PKG_BUILD_DIR) \ - $(UBOOT_MAKE_OPTS) \ - $(UBOOT_CONFIG)_config -endef - -define Build/Compile - $(MAKE) -C $(PKG_BUILD_DIR) \ - $(UBOOT_MAKE_OPTS) \ - OWRT_FLAGS="-DTEXT_BASE=0xa0400000 ${A800_FIX}" \ - ifx_all - $(CP) $(PKG_BUILD_DIR)/u-boot.srec $(PKG_BUILD_DIR)/asc.srec - $(PKG_BUILD_DIR)/gct \ - $(PKG_BUILD_DIR)/danube_ref_ddr166.conf \ - $(PKG_BUILD_DIR)/asc.srec \ - $(PKG_BUILD_DIR)/u-boot.asc - $(MAKE) -C $(PKG_BUILD_DIR) \ - $(UBOOT_MAKE_OPTS) \ - OWRT_FLAGS="-DDANUBE_BOOT_FROM_EBU=1 -DTEXT_BASE=0xB0000000 ${A800_FIX}" \ - clean ifx_all -endef - -define Package/uboot-ifxmips/install - mkdir -p $(1) - dd if=$(PKG_BUILD_DIR)/u-boot.ifx of=$(1)/u-boot.ifx bs=64k conv=sync - $(CP) $(PKG_BUILD_DIR)/u-boot.asc $(1) -endef - -$(eval $(call BuildPackage,uboot-ifxmips)) diff --git a/package/uboot-ifxmips/files/board/ifx/danube/Makefile b/package/uboot-ifxmips/files/board/ifx/danube/Makefile deleted file mode 100644 index 565511773c..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o flash.o -SOBJS = lowlevel_init.o pmuenable.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-ifxmips/files/board/ifx/danube/README b/package/uboot-ifxmips/files/board/ifx/danube/README deleted file mode 100644 index d1c5c1e88c..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/README +++ /dev/null @@ -1,55 +0,0 @@ -/* -** Copyright (C) 2005 Wu Qi Ming -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** This program is distributed in the hope that it will be useful, -** but WITHOUT ANY WARRANTY; without even the implied warranty of -** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -** GNU General Public License for more details. -** -** You should have received a copy of the GNU General Public License -** along with this program; if not, write to the Free Software -** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -*/ - -To build a u-boot for danube board, user need to do the following things: -To configure u-boot for a proper board, user need to modify two files accordingly. - -To configure u-boot for evaluation board, in danube-uboot/include/configs/danube.h, set -#define USE_EVALUATION_BOARD -#undef USE_REFERENCE_BOARD -and vice-versa. - -To let u-boot boot from ebu(flash,e.g), in danube-uboot/include/configus/danube.h, set -#define DANUBE_BOOT_FROM_EBU -Otherwise u-boot will be compiled for booting from RAM. - -To use DDR RAM running at 111M, in danube-uboot/include/configus/danube. -h, set -#define DANUBE_DDR_RAM_111M -#undef DANUBE_DDR_RAM_166M -and vice-versa. - -To define RAM size of RAM, in danube-uboot/include/configus/danube. -h, set -#define RAM_SIZE 0x2000000 /*32M ram*/ -This is an example for a 32M RAM. - - -Besides above settings, user need to change danube-uboot/board/danube/config.mk to set the loading address of u-boot. -If U-Boot is to boot from EBU(flash), user needs to set -TEXT_BASE=0xB0000000 -If u-boot is to boot from RAM, user needs to set -TEXT_BASE=0xa0400000 - -Use the script gct to build a uart downloadable u-boot image: -./gct danube_ref_ddr166.conf u-boot.srec u-boot.asc - - - - - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/config.mk b/package/uboot-ifxmips/files/board/ifx/danube/config.mk deleted file mode 100644 index 88680e14f8..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Danube board with MIPS 24Kec CPU core -#boot from ebu -#TEXT_BASE = 0xB0000000 -BOOTSTRAP_TEXT_BASE = 0xB0000000 - -#boot from ram -#TEXT_BASE = 0xa0400000 -#TEXT_BASE = 0x807c0000 - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/danube.c b/package/uboot-ifxmips/files/board/ifx/danube/danube.c deleted file mode 100644 index b6174ba6d8..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/danube.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#ifdef DANUBE_USE_DDR_RAM -long int initdram(int board_type) -{ - return (1024*1024*DANUBE_DDR_RAM_SIZE); -} -#else -extern uint danube_get_cpuclk(void); - -static ulong max_sdram_size(void) /* per Chip Select */ -{ - /* The only supported SDRAM data width is 16bit. - */ -#define CFG_DW 4 - - /* The only supported number of SDRAM banks is 4. - */ -#define CFG_NB 4 - - ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0; - int cols = cfgpb0 & 0xF; - int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; - - return size; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. - */ - -static long int dram_size(long int *base, long int maxsize) -{ - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - return (cnt * sizeof (long)); - } - } - return (maxsize); -} - -long int initdram(int board_type) -{ - int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0; - ulong size, max_size = 0; - ulong our_address; - - /* load t9 into our_address */ - asm volatile ("move %0, $25" : "=r" (our_address) :); - - /* Can't probe for RAM size unless we are running from Flash. - * find out whether running from DRAM or Flash. - */ - if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1)) - { - return max_sdram_size(); - } - - for (cols = 0x8; cols <= 0xC; cols++) - { - for (rows = 0xB; rows <= 0xD; rows++) - { - *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) | - (rows << 4) | cols; - size = dram_size((ulong *)CFG_SDRAM_BASE, - max_sdram_size()); - - if (size > max_size) - { - best_val = *DANUBE_SDRAM_MC_CFGPB0; - max_size = size; - } - } - } - - *DANUBE_SDRAM_MC_CFGPB0 = best_val; - return max_size; -} -#endif - -int checkboard (void) -{ - /* No such register in Amazon */ -#if 0 - unsigned long chipid = *AMAZON_MCD_CHIPID; - int part_num; - - puts ("Board: AMAZON "); - part_num = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid); - switch (part_num) { - case AMAZON_CHIPID_STANDARD: - printf ("Standard Version, "); - break; - case AMAZON_CHIPID_YANGTSE: - printf ("Yangtse Version, "); - break; - default: - printf ("Unknown Part Number 0x%x ", part_num); - break; - } - - printf ("Chip V1.%ld, ", AMAZON_MCD_CHIPID_VERSION_GET(chipid)); - - - printf("CPU Speed %d MHz\n", danube_get_cpuclk()/1000000); - -#endif - return 0; -} - - -/* - * Disk On Chip (NAND) Millenium initialization. - * The NAND lives in the CS2* space - */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -extern void -nand_probe(ulong physadr); - -#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */ -void -nand_init(void) -{ - int devtype; - /* Configure EBU */ -//TODO: should we keep this? - //Set GPIO23 to be Flash CS1; - *DANUBE_GPIO_P1_ALTSEL0 = *DANUBE_GPIO_P1_ALTSEL0 | (1<<7); - *DANUBE_GPIO_P1_ALTSEL1 = *DANUBE_GPIO_P1_ALTSEL1 & ~(1<<7); - *DANUBE_GPIO_P1_DIR = *DANUBE_GPIO_P1_DIR | (1<<7) ; - *DANUBE_GPIO_P1_OD = *DANUBE_GPIO_P1_OD | (1<<7) ; - - *EBU_ADDR_SEL_1 = (NAND_BASE_ADDRESS&0x1fffff00)|0x31; - /* byte swap;minimum delay*/ - *EBU_CON_1 = 0x40C155; - *EBU_NAND_CON = 0x000005F3; - - /* Set bus signals to inactive */ - NAND_READY_CLEAR; - - NAND_CE_CLEAR; - nand_probe(NAND_BASE_ADDRESS); - - - - //nand_probe(AT91_SMARTMEDIA_BASE); -} -#endif - - - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h deleted file mode 100644 index 3a4b1350e4..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 -#define MC_DC21_VALUE 0x1d00 -#define MC_DC22_VALUE 0x1d1d -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* was 0x7f */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_111.h deleted file mode 100644 index b655ca2898..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_166.h deleted file mode 100644 index b655ca2898..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_166.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h deleted file mode 100644 index 54bb6c9e37..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xa02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x0 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_Samsung_166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_Samsung_166.h deleted file mode 100644 index 7975c3ec0d..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_Samsung_166.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1400 -#define MC_DC22_VALUE 0x1414 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x4e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d93 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h deleted file mode 100644 index b655ca2898..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e166.h deleted file mode 100644 index b655ca2898..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e166.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_psc_166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_psc_166.h deleted file mode 100644 index 445b7dac1f..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_psc_166.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1700 -#define MC_DC22_VALUE 0x1717 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h deleted file mode 100644 index fd155973ee..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r166.h deleted file mode 100644 index 742d34f1d3..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r166.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0xd00 -#define MC_DC22_VALUE 0xd0d -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/flash.c b/package/uboot-ifxmips/files/board/ifx/danube/flash.c deleted file mode 100644 index d95888fdf5..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/flash.c +++ /dev/null @@ -1,917 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -//joelin 10/07/2004 for MXIC MX29LV320ABTC-90 -#include -#include - -/* -#ifdef CONFIG_AMAZON - #define FLASH_DELAY {int i; \ - for(i=0;i<800;i++) \ - *((volatile u32 *)CFG_SDRAM_BASE_UNCACHE); \ - } -#else - #define FLASH_DELAY -#endif -*/ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) // 0xffff8000 - -#if 0 -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa -#else -#define FLASH_CYCLE1 0x0554 //joelin for MX29LV320AT/B 0x0555 -#define FLASH_CYCLE2 0x02ab //joelin for MX29LV320AT/B 0x02aa -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { // 1 bank - ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; // 0xb0000000, 0xb4000000 - - volatile ulong * buscon = (ulong *) - ((i == 0) ? DANUBE_EBU_BUSCON0 : DANUBE_EBU_BUSCON1); - - /* Disable write protection */ -// *buscon &= ~AMAZON_EBU_BUSCON0_WRDIS; - /* Enable write protection */ - *buscon |= DANUBE_EBU_BUSCON0_WRDIS; - -#if 1 - memset(&flash_info[i], 0, sizeof(flash_info_t)); -#endif - - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", - i, flash_info[i].size); - } - - size += flash_info[i].size; - } - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE // TEXT_BASE >= 0xB3000000 - /* monitor protection ON by default */ /* only use software protection, info->protect[i]=0/1 */ -/* flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, - flash_get_info(CFG_MONITOR_BASE)); -*/ - flash_protect(FLAG_PROTECT_CLEAR, // clear protect - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, - flash_get_info(CFG_MONITOR_BASE)); - -#endif - -#ifdef CFG_ENV_IS_IN_FLASH /* 1 */ - /* ENV protection ON by default */ -/* flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -*/ - flash_protect(FLAG_PROTECT_CLEAR, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); - -#endif - - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - asm("SYNC"); - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD){ - *base = (FPW)0x00F000F0; /* AMD Read Mode */ - asm("SYNC"); //joelin - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX){ - *base = (FPW)0x00F000F0; /* MXIC Read Mode */ - asm("SYNC"); //joelin - } - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_28F128J3A)){ - int sect_size; - sect_size = 0x20000; - for(i=0;i < info->sector_count; i++) - info->start[i]= base + (i*sect_size); - } - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_28F320J3A)){ - int sect_size; - sect_size = 0x20000; - for(i=0;i < info->sector_count; i++) - info->start[i]= base + (i*sect_size); - } -//joelin add for MX29LV320AB-- SA0~SA7:sector size=8K bytes ,SA9~SA70 :sector size=64k bytes - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV320AB)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV320B)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } -//joelin add for MX29LV160BB-- SA0=16K,SA1,SA2=8K,SA3=32K bytes ,SA4~SA34 :sector size=64k bytes - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV160BB)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); -/* set sector offsets for bottom boot block type */ -//MX29LV160BB - info->start[0] = base ; //SA0=16K bytes - info->start[1] = info->start[0] + (1 * 0x00004000 * (sizeof(FPW)/2)); //SA1=8K bytes - info->start[2] = info->start[1] + (1 * 0x00002000 * (sizeof(FPW)/2)); //SA2=8K bytes - info->start[3] = info->start[2] + (1 * 0x00002000 * (sizeof(FPW)/2)); //SA3=32K bytes - - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i - 3) * sect_size); - } - } -//liupeng add for MX29LV640BB-- SA0~SA7:sector size=8k bytes ,SA8~SA134 :sector size=64k bytes - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV640BB)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else{ - printf("flash get offsets fail\n"); - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base < info->start[0] + info->size) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - uchar *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - case FLASH_MAN_MX: printf ("MXIC "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - case FLASH_28F128J3A: - fmt = "28F128J3A (128 Mbit, 128 uniform sectors)\n"; - break; - case FLASH_28F320J3A: - fmt = "28F320J3A (32 Mbit, 32 uniform sectors)\n"; - break; - case FLASH_29LV640BB: //liupeng for MXIC FLASH_29LV640BB - fmt = "29LV640BB (64 Mbit, boot sector SA0~SA126 size 64k bytes,other sectors SA127~SA135 size 8k bytes)\n"; - break; - case FLASH_29LV320B: //joelin for MXIC FLASH_29LV320AB - case FLASH_29LV320AB: //joelin for MXIC FLASH_29LV320AB - fmt = "29LV320AB (32 Mbit, boot sector SA0~SA7 size 8K bytes,other sectors SA8~SA70 size 64K bytes)\n"; - break; - case FLASH_29LV160BB: //joelin for MXIC FLASH_29LV160BB - fmt = "29LV160BB (16 Mbit, boot sector SA0 size 16K bytes,SA1,SA2 size 8K bytes,SA3 size 32k bytes,other sectors SA4~SA34 size 64K bytes)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - (*DANUBE_EBU_BUSCON0)=0x1d7ff; //value from Aikann, should be used on the real chip - (*EBU_ADDR_SEL_0) = 0x10000031; //starting address from 0xb0000000 - (*EBU_NAND_CON)=0; - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - asm("SYNC"); - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - asm("SYNC"); - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - asm("SYNC"); - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - - printf("\n type is %08lx", addr[1] & 0xff); //joelin 10/06/2004 flash type - printf("\n type is %08lx", addr[0] & 0xff); //joelin 10/06/2004 flash type -// asm("SYNC"); - switch (addr[1] & 0xff) { - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: // 0x0089 - info->flash_id = FLASH_MAN_INTEL; //0x00300000 - break; - -//joelin for MXIC - case (uchar)MX_MANUFACT: // 0x00c2 - info->flash_id = FLASH_MAN_MX ;//0x00030000 - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; -/* default: - info->flash_id = FLASH_MAN_INTEL; //0x00300000 - break;*/ - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) { - case (FPW)EON_ID_EN29LV320B: - info->flash_id += FLASH_29LV320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F128J3A: - info->flash_id +=FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000 * (sizeof(FPW)/2); - break; /* => 16 MB */ - case (FPW)INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; -//joelin for MXIC - case (FPW)MX_ID_29LV320AB: - info->flash_id += FLASH_29LV320AB; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 MB */ - /* => 4 MB */ -//joelin for MXIC - case (FPW)MX_ID_29LV160BB: - info->flash_id += FLASH_29LV160BB; - info->sector_count = 35; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 MB */ - /* => 2 MB */ - /* liupeng*/ - case (FPW)MX_ID_29LV640BB: - info->flash_id += FLASH_29LV640BB; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 2 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ -/* default: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000 * (sizeof(FPW)/2); - break;*/ - } - - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_28F128J3A: - case FLASH_28F320J3A: - case FLASH_AM640U: - case FLASH_29LV640BB: //liupeng for MXIC MX29LV640BB - case FLASH_29LV320B: - case FLASH_29LV320AB: //joelin for MXIC MX29LV320AB - case FLASH_29LV160BB: //joelin for MXIC MX29LV160BB - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - asm("SYNC"); - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Erase Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - -//joelin for MXIC - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_MX: //joelin for MXIC - break; - default: - if((*addr & (FPW)0x00200020) != (FPW)0x0) - printf("Erase Error\n"); - break; - } - - - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - //flash_reset(info); /* reset to read mode */ - } - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - flash_reset(info); /* Homebox Black with JS28F128J3D75 had trouble reading after erase */ - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - case FLASH_MAN_MX: //joelin for MXIC - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - *dest = data; /* start programming the data */ - asm("SYNC"); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - flash_reset(info); - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - return (res); -} diff --git a/package/uboot-ifxmips/files/board/ifx/danube/lowlevel_init.S b/package/uboot-ifxmips/files/board/ifx/danube/lowlevel_init.S deleted file mode 100644 index f5f24a40cf..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/lowlevel_init.S +++ /dev/null @@ -1,582 +0,0 @@ - -/* - * Memory sub-system initialization code for INCA-IP2 development board. - * Andre Messerschmidt - * Copyright (c) 2005 Infineon Technologies AG - * - * Based on Inca-IP code - * Copyright (c) 2003 Wolfgang Denk - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* History: - peng liu May 25, 2006, for PLL setting after reset, 05252006 - */ -#include -#include -#include -#include - - -#ifdef USE_REFERENCE_BOARD -#ifdef DANUBE_DDR_RAM_111M -#include "ddr_settings_r111.h" -#elif defined(PROMOSDDR400) -#include "ddr_settings_PROMOSDDR400.h" -#elif defined(DDR_SAMSUNG_166M) -#include "ddr_settings_Samsung_166.h" -#elif defined(DDR_PSC_166M) -#include "ddr_settings_psc_166.h" -#else -#include "ddr_settings_r166.h" -#endif -#endif - -#ifdef USE_EVALUATION_BOARD -#ifdef DANUBE_DDR_RAM_111M -#include "ddr_settings_e111.h" -#else -#include "ddr_settings_e166.h" -#endif -#endif - - - -/*TODO: liupeng check !!! */ -#define EBU_MODUL_BASE 0xB4102000 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_ADDSEL3(value) 0x002C(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) -#define EBU_BUSCON3(value) 0x006C(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0010(value) -#define MC_ERRADDR(value) 0x0020(value) -#define MC_CON(value) 0x0060(value) - -#define MC_SRAM_ENABLE 0x00000004 -#define MC_SDRAM_ENABLE 0x00000002 -#define MC_DDRRAM_ENABLE 0x00000001 - -#define MC_SDR_MODUL_BASE 0xBF800200 -#define MC_IOGP(value) 0x0000(value) -#define MC_CTRLENA(value) 0x0010(value) -#define MC_MRSCODE(value) 0x0020(value) -#define MC_CFGDW(value) 0x0030(value) -#define MC_CFGPB0(value) 0x0040(value) -#define MC_LATENCY(value) 0x0080(value) -#define MC_TREFRESH(value) 0x0090(value) -#define MC_SELFRFSH(value) 0x00A0(value) - -#define MC_DDR_MODUL_BASE 0xBF801000 -#define MC_DC00(value) 0x0000(value) -#define MC_DC01(value) 0x0010(value) -#define MC_DC02(value) 0x0020(value) -#define MC_DC03(value) 0x0030(value) -#define MC_DC04(value) 0x0040(value) -#define MC_DC05(value) 0x0050(value) -#define MC_DC06(value) 0x0060(value) -#define MC_DC07(value) 0x0070(value) -#define MC_DC08(value) 0x0080(value) -#define MC_DC09(value) 0x0090(value) -#define MC_DC10(value) 0x00A0(value) -#define MC_DC11(value) 0x00B0(value) -#define MC_DC12(value) 0x00C0(value) -#define MC_DC13(value) 0x00D0(value) -#define MC_DC14(value) 0x00E0(value) -#define MC_DC15(value) 0x00F0(value) -#define MC_DC16(value) 0x0100(value) -#define MC_DC17(value) 0x0110(value) -#define MC_DC18(value) 0x0120(value) -#define MC_DC19(value) 0x0130(value) -#define MC_DC20(value) 0x0140(value) -#define MC_DC21(value) 0x0150(value) -#define MC_DC22(value) 0x0160(value) -#define MC_DC23(value) 0x0170(value) -#define MC_DC24(value) 0x0180(value) -#define MC_DC25(value) 0x0190(value) -#define MC_DC26(value) 0x01A0(value) -#define MC_DC27(value) 0x01B0(value) -#define MC_DC28(value) 0x01C0(value) -#define MC_DC29(value) 0x01D0(value) -#define MC_DC30(value) 0x01E0(value) -#define MC_DC31(value) 0x01F0(value) -#define MC_DC32(value) 0x0200(value) -#define MC_DC33(value) 0x0210(value) -#define MC_DC34(value) 0x0220(value) -#define MC_DC35(value) 0x0230(value) -#define MC_DC36(value) 0x0240(value) -#define MC_DC37(value) 0x0250(value) -#define MC_DC38(value) 0x0260(value) -#define MC_DC39(value) 0x0270(value) -#define MC_DC40(value) 0x0280(value) -#define MC_DC41(value) 0x0290(value) -#define MC_DC42(value) 0x02A0(value) -#define MC_DC43(value) 0x02B0(value) -#define MC_DC44(value) 0x02C0(value) -#define MC_DC45(value) 0x02D0(value) -#define MC_DC46(value) 0x02E0(value) - -#define RCU_OFFSET 0xBF203000 -#define RCU_RST_REQ (RCU_OFFSET + 0x0010) -#define RCU_STS (RCU_OFFSET + 0x0014) - -#define CGU_OFFSET 0xBF103000 -#define PLL0_CFG (CGU_OFFSET + 0x0004) -#define PLL1_CFG (CGU_OFFSET + 0x0008) -#define PLL2_CFG (CGU_OFFSET + 0x000C) -#define CGU_SYS (CGU_OFFSET + 0x0010) -#define CGU_UPDATE (CGU_OFFSET + 0x0014) -#define IF_CLK (CGU_OFFSET + 0x0018) -#define CGU_SMD (CGU_OFFSET + 0x0020) -#define CGU_CT1SR (CGU_OFFSET + 0x0028) -#define CGU_CT2SR (CGU_OFFSET + 0x002C) -#define CGU_PCMCR (CGU_OFFSET + 0x0030) -#define PCI_CR_PCI (CGU_OFFSET + 0x0034) -#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C) -#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038) -#define CLK_MEASURE (CGU_OFFSET + 0x003C) - -//05252006 -#define pll0_35MHz_CONFIG 0x9D861059 -#define pll1_35MHz_CONFIG 0x1A260CD9 -#define pll2_35MHz_CONFIG 0x8000f1e5 -#define pll0_36MHz_CONFIG 0x1000125D -#define pll1_36MHz_CONFIG 0x1B1E0C99 -#define pll2_36MHz_CONFIG 0x8002f2a1 -//05252006 - -//06063001-joelin disable the PCI CFRAME mask -start -/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out. -But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled. - -The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus. -The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function. -*/ -#define PCI_CR_PR_OFFSET 0xBE105400 -#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) -#define PCI_CONFIG_SPACE 0xB7000000 -#define CS_CFM (PCI_CONFIG_SPACE + 0x6C) -//06063001-joelin disable the PCI CFRAME mask -end - .set noreorder - - -/* - * void ebu_init(long) - * - * a0 has the clock value we are going to run at - */ - .globl ebu_init - .ent ebu_init -ebu_init: -/*TODO:liupeng */ - j ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: - li t2, CGU_SYS - lw t2,0(t2) - beq t2,a0,freq_up2date - nop - - li t2, RCU_STS - lw t2, 0(t2) - and t2,0x00020000 - beq t2,0x00020000,boot_36MHZ - nop -//05252006 - li t1, PLL0_CFG - li t2, pll0_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_35MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) - b wait_reset - nop -boot_36MHZ: - li t1, PLL0_CFG - li t2, pll0_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_36MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) -//05252006 - -wait_reset: - b wait_reset - nop -freq_up2date: - j ra - nop - .end cgu_init - - -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: - - /* SDRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable SDRAM module in memory controller */ - li t3, MC_SDRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_SDR_MODUL_BASE - - /* disable the controller */ - li t2, 0 - sw t2, MC_CTRLENA(t1) - - li t2, 0x822 - sw t2, MC_IOGP(t1) - - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 - sw t2, MC_MRSCODE(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014d8 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00036325; /* BC PC100 */ - sw t2, MC_LATENCY(t1) - - /* Set SDRAM refresh rate */ - li t2, 0x00000C30 - sw t2, MC_TREFRESH(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Finally enable the controller */ - li t2, 1 - sw t2, MC_CTRLENA(t1) - - - j ra - nop - - - .end sdram_init - -/* - * void ddrram_init(long) - * - * a0 has the clock value - */ - .globl ddrram_init - .ent ddrram_init -ddrram_init: - - /* DDR-DRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable DDR module in memory controller */ - li t3, MC_DDRRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_DDR_MODUL_BASE - - /* Write configuration to DDR controller registers */ - li t2, MC_DC0_VALUE - sw t2, MC_DC00(t1) - - li t2, MC_DC1_VALUE - sw t2, MC_DC01(t1) - - li t2, MC_DC2_VALUE - sw t2, MC_DC02(t1) - - li t2, MC_DC3_VALUE - sw t2, MC_DC03(t1) - - li t2, MC_DC4_VALUE - sw t2, MC_DC04(t1) - - li t2, MC_DC5_VALUE - sw t2, MC_DC05(t1) - - li t2, MC_DC6_VALUE - sw t2, MC_DC06(t1) - - li t2, MC_DC7_VALUE - sw t2, MC_DC07(t1) - - li t2, MC_DC8_VALUE - sw t2, MC_DC08(t1) - - li t2, MC_DC9_VALUE - sw t2, MC_DC09(t1) - - li t2, MC_DC10_VALUE - sw t2, MC_DC10(t1) - - li t2, MC_DC11_VALUE - sw t2, MC_DC11(t1) - - li t2, MC_DC12_VALUE - sw t2, MC_DC12(t1) - - li t2, MC_DC13_VALUE - sw t2, MC_DC13(t1) - - li t2, MC_DC14_VALUE - sw t2, MC_DC14(t1) - - li t2, MC_DC15_VALUE - sw t2, MC_DC15(t1) - - li t2, MC_DC16_VALUE - sw t2, MC_DC16(t1) - - li t2, MC_DC17_VALUE - sw t2, MC_DC17(t1) - - li t2, MC_DC18_VALUE - sw t2, MC_DC18(t1) - - li t2, MC_DC19_VALUE - sw t2, MC_DC19(t1) - - li t2, MC_DC20_VALUE - sw t2, MC_DC20(t1) - - li t2, MC_DC21_VALUE - sw t2, MC_DC21(t1) - - li t2, MC_DC22_VALUE - sw t2, MC_DC22(t1) - - li t2, MC_DC23_VALUE - sw t2, MC_DC23(t1) - - li t2, MC_DC24_VALUE - sw t2, MC_DC24(t1) - - li t2, MC_DC25_VALUE - sw t2, MC_DC25(t1) - - li t2, MC_DC26_VALUE - sw t2, MC_DC26(t1) - - li t2, MC_DC27_VALUE - sw t2, MC_DC27(t1) - - li t2, MC_DC28_VALUE - sw t2, MC_DC28(t1) - - li t2, MC_DC29_VALUE - sw t2, MC_DC29(t1) - - li t2, MC_DC30_VALUE - sw t2, MC_DC30(t1) - - li t2, MC_DC31_VALUE - sw t2, MC_DC31(t1) - - li t2, MC_DC32_VALUE - sw t2, MC_DC32(t1) - - li t2, MC_DC33_VALUE - sw t2, MC_DC33(t1) - - li t2, MC_DC34_VALUE - sw t2, MC_DC34(t1) - - li t2, MC_DC35_VALUE - sw t2, MC_DC35(t1) - - li t2, MC_DC36_VALUE - sw t2, MC_DC36(t1) - - li t2, MC_DC37_VALUE - sw t2, MC_DC37(t1) - - li t2, MC_DC38_VALUE - sw t2, MC_DC38(t1) - - li t2, MC_DC39_VALUE - sw t2, MC_DC39(t1) - - li t2, MC_DC40_VALUE - sw t2, MC_DC40(t1) - - li t2, MC_DC41_VALUE - sw t2, MC_DC41(t1) - - li t2, MC_DC42_VALUE - sw t2, MC_DC42(t1) - - li t2, MC_DC43_VALUE - sw t2, MC_DC43(t1) - - li t2, MC_DC44_VALUE - sw t2, MC_DC44(t1) - - li t2, MC_DC45_VALUE - sw t2, MC_DC45(t1) - - li t2, MC_DC46_VALUE - sw t2, MC_DC46(t1) - - li t2, 0x00000100 - sw t2, MC_DC03(t1) - - j ra - nop - - - .end ddrram_init - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - /* EBU, CGU and SDRAM/DDR-RAM Initialization. - */ - move t0, ra - /* We rely on the fact that neither cgu_init() nor sdram_init() - * modify t0 - */ -#ifdef DANUBE_BOOT_FROM_EBU -#ifdef DANUBE_DDR_RAM_166M -//05252006 - /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */ - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef PROMOSDDR400 - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef DDR_SAMSUNG_166M - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef DDR_PSC_166M - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef DANUBE_DDR_RAM_133M - li a0,0xe9 -//05252006 - bal cgu_init - nop -#endif -#endif -/*TODO:liupeng add this define !!!! */ -/* - #define DANUBE_BOOT_FROM_EBU - #define DANUBE_USE_DDR_RAM -*/ - -//06063001-joelin disable the PCI CFRAME mask-start -#ifdef DISABLE_CFRAME - li t1, PCI_CR_PCI //mw bf103034 80000000 - li t2, 0x80000000 - sw t2,0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x103 - sw t2,0(t1) - - li t1, CS_CFM //mw b700006c 0 - li t2, 0x00 - sw t2, 0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x1000103 - sw t2, 0(t1) -#endif -//06063001-joelin disable the PCI CFRAME mask-end - -#ifdef DANUBE_BOOT_FROM_EBU -#ifdef DANUBE_USE_DDR_RAM - bal ddrram_init - nop -#else - bal sdram_init - nop -#endif -#endif - - move ra, t0 - j ra - nop - - .end lowlevel_init diff --git a/package/uboot-ifxmips/files/board/ifx/danube/pmuenable.S b/package/uboot-ifxmips/files/board/ifx/danube/pmuenable.S deleted file mode 100644 index e0d7971d89..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/pmuenable.S +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Power Management unit initialization code for AMAZON development board. - * - * Copyright (c) 2003 Ou Ke, Infineon. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -#define PMU_PWDCR 0xBF10201C -#define PMU_SR 0xBF102020 - - .globl pmuenable - -pmuenable: - li t0, PMU_PWDCR - li t1, 0x2 /* enable everything */ - sw t1, 0(t0) -#if 0 -1: - li t0, PMU_SR - lw t2, 0(t0) - bne t1, t2, 1b - nop -#endif - j ra - nop - - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/u-boot-bootstrap.lds b/package/uboot-ifxmips/files/board/ifx/danube/u-boot-bootstrap.lds deleted file mode 100644 index 36c658b187..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/u-boot-bootstrap.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start_bootstrap) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { *(.data*) } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - _gp = ALIGN(16); - - __got_start_bootstrap = .; - .got : { *(.got) } - __got_end_bootstrap = .; - - .sdata : { *(.sdata) } - - . = .; - __u_boot_cmd_start_bootstrap = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end_bootstrap = .; - - uboot_end_data_bootstrap = .; - num_got_entries = (__got_end_bootstrap - __got_start_bootstrap) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) } - uboot_end_bootstrap = .; -} diff --git a/package/uboot-ifxmips/files/board/ifx/danube/u-boot.lds b/package/uboot-ifxmips/files/board/ifx/danube/u-boot.lds deleted file mode 100644 index 40645166cb..0000000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/u-boot.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { *(.data*) } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - _gp = ALIGN(16); - - __got_start = .; - .got : { *(.got) } - __got_end = .; - - .sdata : { *(.sdata) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) } - uboot_end = .; -} diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/Makefile b/package/uboot-ifxmips/files/cpu/mips/danube/Makefile deleted file mode 100644 index 6f7b5dc68a..0000000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -######################################################################### -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).a - -COBJS = ifx_asc.o ifx_clock.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_asc.c b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_asc.c deleted file mode 100644 index 52c6cb2715..0000000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_asc.c +++ /dev/null @@ -1,257 +0,0 @@ -/***************************************************************************** - * DANUBE BootROM - * Copyright (c) 2005, Infineon Technologies AG, All rights reserved - * IFAP DC COM SD - *****************************************************************************/ - -#include -//#include -#include -#include -#include - - -#define ASC_FIFO_PRESENT -#define SET_BIT(reg, mask) reg |= (mask) -#define CLEAR_BIT(reg, mask) reg &= (~mask) -#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) -#define SET_BITS(reg, mask) SET_BIT(reg, mask) -#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} - - -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned long u32; -typedef signed long s32; -typedef unsigned int uint; -typedef unsigned long ulong; -typedef volatile unsigned short vuint; - - - -void serial_setbrg (void); - -/*TODO: undefine this !!!*/ -#undef DEBUG_ASC_RAW -#ifdef DEBUG_ASC_RAW -#define DEBUG_ASC_RAW_RX_BUF 0xA0800000 -#define DEBUG_ASC_RAW_TX_BUF 0xA0900000 -#endif - -static volatile DanubeAsc_t *pAsc = (DanubeAsc_t *)DANUBE_ASC1; - -typedef struct{ - u16 fdv; /* 0~511 fractional divider value*/ - u16 reload; /* 13 bit reload value*/ -} ifx_asc_baud_reg_t; - -#ifdef ON_VENUS -/*9600 @1.25M rel 00.08*/ -//#define FDV 503 -//#define RELOAD 7 -/*9600 @0.625M rel final00.01 & rtl_freeze*/ -#define FDV 503 -#define RELOAD 3 -/* first index is DDR_SEL, second index is FPI_SEL */ -#endif -static ifx_asc_baud_reg_t g_danube_asc_baud[4][2] = -{ -#ifdef ON_VENUS - {{503,3},{503,3}}, /* 1152000 @ 166.67M and half*/ - {{503,3},{503,3}}, /* 1152000 @ 133.3M and half*/ - {{503,3},{503,3}}, /* 1152000 @ 111.11M and half*/ - {{503.3},{503,3}} /* 1152000 @ 83.33M and half*/ -#else -/* TAPEOUT table */ - {{436,76},{419,36}}, /* 1152000 @ 166.67M and half*/ - {{453,63},{453,31}}, /* 1152000 @ 133.3M and half*/ - {{501,58},{510,29}}, /* 1152000 @ 111.11M and half*/ - {{419.36},{453,19}} /* 1152000 @ 83.33M and half*/ -#endif -}; -/****************************************************************************** -* -* asc_init - initialize a Danube ASC channel -* -* This routine initializes the number of data bits, parity -* and set the selected baud rate. Interrupts are disabled. -* Set the modem control signals if the option is selected. -* -* RETURNS: N/A -*/ - -int serial_init (void) -{ - - /* and we have to set CLC register*/ - CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS); - SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001); - - /* initialy we are in async mode */ - pAsc->asc_con = ASCCON_M_8ASYNC; - - /* select input port */ - pAsc->asc_pisel = (CONSOLE_TTY & 0x1); - - /* TXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK, - ASCTXFCON_TXFITLOFF, DANUBEASC_TXFIFO_FL); - /* enable TXFIFO */ - SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN); - - /* RXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK, - ASCRXFCON_RXFITLOFF, DANUBEASC_RXFIFO_FL); - /* enable RXFIFO */ - SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN); - - /* set baud rate */ - serial_setbrg(); - - /* enable error signals & Receiver enable */ - SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN); - - return 0; -} - -void serial_setbrg (void) -{ - u32 uiReloadValue, fdv; - -#if defined(ON_IKOS) - /*1200 @77K */ - fdv=472; - uiReloadValue=5; -#else - /*venus & tapeout */ - u32 ddr_sel,fpi_sel; - ddr_sel = (* DANUBE_CGU_SYS) & 0x3; - fpi_sel = ((* DANUBE_CGU_SYS) & 0x40)?1:0; - fdv= g_danube_asc_baud[ddr_sel][fpi_sel].fdv; - uiReloadValue=g_danube_asc_baud[ddr_sel][fpi_sel].reload; -#endif //ON_IKOS - /* Disable Baud Rate Generator; BG should only be written when R=0 */ - CLEAR_BIT(pAsc->asc_con, ASCCON_R); - - /* Enable Fractional Divider */ - SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */ - - /* Set fractional divider value */ - pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK; - - /* Set reload value in BG */ - pAsc->asc_bg = uiReloadValue; - - /* Enable Baud Rate Generator */ - SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */ -} - - -void serial_putc (const char c) -{ - u32 txFl = 0; -#ifdef DEBUG_ASC_RAW - static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF; - *debug++=c; -#endif - if (c == '\n') - serial_putc ('\r'); - /* check do we have a free space in the TX FIFO */ - /* get current filling level */ - do - { - txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; - } - while ( txFl == DANUBEASC_TXFIFO_FULL ); - - pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */ - - /* check for errors */ - if ( pAsc->asc_state & ASCSTATE_TOE ) - { - SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_CLRTOE); - return; - } -} - -void serial_puts (const char *s) -{ - while (*s) - { - serial_putc (*s++); - } -} - -int asc_inb(int timeout) -{ - u32 symbol_mask; - char c; - while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) { - } - symbol_mask = ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff); - c = (char)(pAsc->asc_rbuf & symbol_mask); - return (c); -} - -int serial_getc (void) -{ - char c; - while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ); - c = (char)(pAsc->asc_rbuf & 0xff); - -#ifdef DEBUG_ASC_RAW - static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF); - *debug++=c; -#endif - return c; -} - - - -int serial_tstc (void) -{ - int res = 1; - -#ifdef ASC_FIFO_PRESENT - if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) - { - res = 0; - } -#else - if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & - FBS_ISR_AR)) - - { - res = 0; - } -#endif -#if 0 - else if ( pAsc->asc_con & ASCCON_FE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_PE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_OE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); - res = 0; - } -#endif - return res; -} - - -int serial_start(void) -{ - return 1; -} - -int serial_stop(void) -{ - return 1; -} diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cache.S b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cache.S deleted file mode 100644 index fc482dcd61..0000000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cache.S +++ /dev/null @@ -1,60 +0,0 @@ - -#define IFX_CACHE_EXTRA_INVALID_TAG \ - mtc0 zero, CP0_TAGLO, 1; \ - mtc0 zero, CP0_TAGLO, 2; \ - mtc0 zero, CP0_TAGLO, 3; \ - mtc0 zero, CP0_TAGLO, 4; - -#define IFX_CACHE_EXTRA_OPERATION \ - /* set WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ECCF_WST; \ - or a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - li a0, K0BASE; \ - move a2, t2; /* icacheSize */ \ - move a3, t4; /* icacheLineSize */ \ - move a1, a2; \ - icacheop(a0,a1,a2,a3,(Index_Store_Tag_I)); \ - \ - /* clear WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ~ECCF_WST; \ - and a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - /* 1: initialise dcache tags. */ \ - \ - /* cache line size */ \ - li a2, CFG_CACHELINE_SIZE; \ - /* kseg0 mem address */ \ - li a1, 0; \ - li a3, CFG_CACHE_SETS * CFG_CACHE_WAYS; \ -1: \ - /* store tag (invalid, not locked) */ \ - cache 0x8, 0(a1); \ - cache 0x9, 0(a1); \ - \ - add a3, -1; \ - bne a3, zero, 1b; \ - add a1, a2; \ - \ - /* set WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ECCF_WST; \ - or a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - li a0, K0BASE; \ - move a2, t3; /* dcacheSize */ \ - move a3, t5; /* dcacheLineSize */ \ - move a1, a2; \ - icacheop(a0,a1,a2,a3,(Index_Store_Tag_D)); \ - \ - /* clear WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ~ECCF_WST; \ - and a0, a1; \ - mtc0 a0, CP0_ECC; - diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_clock.c b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_clock.c deleted file mode 100644 index c67cf15eb3..0000000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_clock.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - - - -/******************************************************************************* -* -* get_cpuclk - returns the frequency of the CPU. -* -* NOTE: -* This functions should be used by the hardware driver to get the correct -* frequency of the CPU. -*/ - -unsigned int danube_get_ddr_hz(void) -{ - switch((*DANUBE_CGU_SYS) & 0x3){ - case 0: - default: - return 166666667; - case 1: - return 133333333; - case 2: - return 111111111; - case 3: - return 83333333; - } -} - - -uint danube_get_cpuclk(void) -{ -#ifdef CONFIG_USE_EMULATOR - return EMULATOR_CPU_SPEED; -#else //NOT CONFIG_USE_EMULATOR - unsigned int ddr_clock=danube_get_ddr_hz(); - switch((*DANUBE_CGU_SYS) & 0xc){ - case 0: - default: - return 333333333; - case 4: - return ddr_clock; - case 8: - return ddr_clock << 1; - } -#endif -} - - -uint danube_get_fpiclk(void) -{ -#ifdef CONFIG_USE_EMULATOR - unsigned int clkCPU; - clkCPU = danube_get_cpu_hz(); - return clkCPU >> 2; -#else //NOT CONFIG_USE_EMULATOR - unsigned int ddr_clock=danube_get_ddr_hz(); - if ((*DANUBE_CGU_SYS) & 0x40){ - return ddr_clock >> 1; - } - return ddr_clock; -#endif -} - - diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cpu.c b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cpu.c deleted file mode 100644 index 49355de55a..0000000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cpu.c +++ /dev/null @@ -1,5 +0,0 @@ - -#define IFX_CPU_RESET \ -{ *DANUBE_RCU_RST_REQ |=1<<30; \ -} - diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_start.S b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_start.S deleted file mode 100644 index 17c0b0ae55..0000000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_start.S +++ /dev/null @@ -1,51 +0,0 @@ -/* - * IFX Platform Dependent CPU Initializations - * - for Danube - */ - -#define IFX_EBU_BOOTCFG_DWORD \ - .word INFINEON_EBU_BOOTCFG; /* EBU init code, fetched during booting */ \ - .word 0x00000000; /* phases of the flash */ - -#define IFX_MORE_RESERVED_VECTORS \ - XVECENT(romExcHandle,0x400); /* Int, CauseIV=1 */ \ - RVECENT(romReserved,129); \ - RVECENT(romReserved,130); \ - RVECENT(romReserved,131); \ - RVECENT(romReserved,132); \ - RVECENT(romReserved,133); \ - RVECENT(romReserved,134); \ - RVECENT(romReserved,135); \ - RVECENT(romReserved,136); \ - RVECENT(romReserved,137); \ - RVECENT(romReserved,138); \ - RVECENT(romReserved,139); \ - RVECENT(romReserved,140); \ - RVECENT(romReserved,141); \ - RVECENT(romReserved,142); \ - RVECENT(romReserved,143); \ - RVECENT(romExcHandle,0x480); /* EJTAG debug exception */ - -#define IFX_RESET_PRECHECK \ - mfc0 k0, CP0_EBASE; \ - and k0, EBASEF_CPUNUM; \ - bne k0, zero, ifx_mips_handler_1; \ - nop; - -#define IFX_CPU_EXTRA_INIT \ - mfc0 k0, CP0_CONFIG, 7; \ - li k1, 0x04; \ - or k0, k1; \ - mtc0 k0, CP0_CONFIG, 7; - -#define IFX_CACHE_OPER_MODE \ - li t0, CONF_CM_CACHABLE_NO_WA; - -/* - * Stop VCPU - */ -#define IFX_MIPS_HANDLER_1 \ - wait; \ - b ifx_mips_handler_1; \ - nop; - diff --git a/package/uboot-ifxmips/files/danube_ref_ddr166.conf b/package/uboot-ifxmips/files/danube_ref_ddr166.conf deleted file mode 100755 index 351d6a108f..0000000000 --- a/package/uboot-ifxmips/files/danube_ref_ddr166.conf +++ /dev/null @@ -1,134 +0,0 @@ - 0xbf800060 0x7 - 0xbf800010 0x0 - 0xbf800020 0x0 - 0xbf800200 0x02 - 0xbf800210 0x0 - -;REG32(MC_DC0) = 0x00001B1B; - 0xbf801000 0x1b1b -;REG32(MC_DC1) = 0x00000000; - 0xbf801010 0x0 -;REG32(MC_DC2) = 0x00000000; - 0xbf801020 0x0 -;REG32(MC_DC3) = 0x00000000; - 0xbf801030 0x0 -;REG32(MC_DC4) = 0x00000000; - 0xbf801040 0x0 -;REG32(MC_DC5) = 0x00000200; - 0xbf801050 0x200 -;REG32(MC_DC6) = 0x00000306; -; 0xbf801060 0x0306 - 0xbf801060 0x0605 -;REG32(MC_DC7) = 0x00000303; - 0xbf801070 0x302 -; 0xbf801070 0x0203 -;REG32(MC_DC8) = 0x00000102; - 0xbf801080 0x102 -;REG32(MC_DC9) = 0x0000070A; - 0xbf801090 0x70a -; 0xbf801090 0x608 -;REG32(MC_DC10) = 0x00000203; - 0xbf8010a0 0x203 -;REG32(MC_DC11) = 0x00000C02; - 0xbf8010b0 0xc02 -; 0xbf8010b0 0x0a02 -;REG32(MC_DC12) = 0x000001C8; - 0xbf8010c0 0x1c8 -;REG32(MC_DC13) = 0x00000001; - 0xbf8010d0 0x1 -;REG32(MC_DC14) = 0x00000000; - 0xbf8010e0 0x0 -;REG32(MC_DC15) = 0x00000F5F; -; 0xbf8010f0 0xf5f - 0xbf8010f0 0xf3c -;REG32(MC_DC16) = 0x0000C800; - 0xbf801100 0xc800 -;REG32(MC_DC17) = 0x0000000D; -; 0xbf801110 0xd - 0xbf801110 0xd -;REG32(MC_DC18) = 0x00000300; - 0xbf801120 0x300 -;REG32(MC_DC19) = 0x00000300; -; 0xbf801130 0x300 - 0xbf801130 0x200 -;REG32(MC_DC20) = 0x00000A04; -; 0xbf801140 0xa04 - 0xbf801140 0xa04 -;REG32(MC_DC21) = 0x00001c00; - 0xbf801150 0xd00 -; 0xbf801150 0x1f00 -;REG32(MC_DC22) = 0x00001E1E; - 0xbf801160 0xd0d -; 0xbf801160 0x1f1f -;REG32(MC_DC23) = 0x00000000; - 0xbf801170 0x0 -;//Disable ECC -;REG32(MC_DC24) = 0x0000007F; -; 0xbf801180 0x7f - 0xbf801180 0x062 -; 0xbf801180 0x37f -;REG32(MC_DC25) = 0x00000000; - 0xbf801190 0x0 -;REG32(MC_DC26) = 0x00000000; - 0xbf8011a0 0x0 -;REG32(MC_DC27) = 0x00000000; - 0xbf8011b0 0x0 -;REG32(MC_DC28) = 0x00000A24; -; 0xbf8011c0 0xa24 - 0xbf8011c0 0x510 -;REG32(MC_DC29) = 0x00002D89; - 0xbf8011d0 0x2d89 -; 0xbf8011d0 0x2d92 -;REG32(MC_DC30) = 0x00000022; - 0xbf8011e0 0x8300 -; 0xbf8011e0 0x8235 -;REG32(MC_DC31) = 0x00000000; - 0xbf8011f0 0x0 -;REG32(MC_DC32) = 0x00000000; - 0xbf801200 0x0 -;REG32(MC_DC33) = 0x00000000; - 0xbf801210 0x0 -;REG32(MC_DC34) = 0x00000000; - 0xbf801220 0x0 -;REG32(MC_DC35) = 0x00000000; - 0xbf801230 0x0 -;REG32(MC_DC36) = 0x00000000; - 0xbf801240 0x0 -;REG32(MC_DC37) = 0x00000000; - 0xbf801250 0x0 -;REG32(MC_DC38) = 0x00000000; - 0xbf801260 0x0 -;REG32(MC_DC39) = 0x00000000; - 0xbf801270 0x0 -;REG32(MC_DC40) = 0x00000000; - 0xbf801280 0x0 -;REG32(MC_DC41) = 0x00000000; - 0xbf801290 0x0 -;REG32(MC_DC42) = 0x00000000; - 0xbf8012a0 0x0 -;REG32(MC_DC43) = 0x00000000; - 0xbf8012b0 0x0 -;REG32(MC_DC44) = 0x00000000; - 0xbf8012c0 0x0 -;REG32(MC_DC45) = 0x00000600; - 0xbf8012d0 0x500 -;REG32(MC_DC46) = 0x00000000; - 0xbf8012e0 0x0 - - 0xbf800060 0x05 - 0xbf801030 0x100 - - - - - - - - - - - - - - - diff --git a/package/uboot-ifxmips/files/drivers/ifx_sw.c b/package/uboot-ifxmips/files/drivers/ifx_sw.c deleted file mode 100644 index ac0415a502..0000000000 --- a/package/uboot-ifxmips/files/drivers/ifx_sw.c +++ /dev/null @@ -1,459 +0,0 @@ -/* - * DANUBE internal switch ethernet driver. - * - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ - && defined(CONFIG_DANUBE_SWITCH) - -#include -#include -#include -#include -#include - -#define MII_MODE 1 -#define REV_MII_MODE 2 - -#define TX_CHAN_NO 7 -#define RX_CHAN_NO 6 - -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 8 -#define MAX_PACKET_SIZE 1536 -#define TOUT_LOOP 100 -#define PHY0_ADDR 1 /*fixme: set the correct value here*/ - -#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value -#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) - -#define SW_WRITE_REG(reg, value) *((volatile u32*)reg) = (u32)value -#define SW_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) - -#define TANTOS_CHIP_ID 0x2599 - -typedef struct -{ - union - { - struct - { - volatile u32 OWN :1; - volatile u32 C :1; - volatile u32 Sop :1; - volatile u32 Eop :1; - volatile u32 reserved :3; - volatile u32 Byteoffset :2; - volatile u32 reserve :7; - volatile u32 DataLen :16; - }field; - - volatile u32 word; - }status; - - volatile u32 DataPtr; -} danube_rx_descriptor_t; - -typedef struct -{ - union - { - struct - { - volatile u32 OWN :1; - volatile u32 C :1; - volatile u32 Sop :1; - volatile u32 Eop :1; - volatile u32 Byteoffset :5; - volatile u32 reserved :7; - volatile u32 DataLen :16; - }field; - - volatile u32 word; - }status; - - volatile u32 DataPtr; -} danube_tx_descriptor_t; - - - - -static danube_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8))); -static danube_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8))); -static int tx_num, rx_num; - -int danube_switch_init(struct eth_device *dev, bd_t * bis); -int danube_switch_send(struct eth_device *dev, volatile void *packet,int length); -int danube_switch_recv(struct eth_device *dev); -void danube_switch_halt(struct eth_device *dev); -static void danube_init_switch_chip(int mode); -static void danube_dma_init(void); - - - -int danube_switch_initialize(bd_t * bis) -{ - struct eth_device *dev; - unsigned short chipid; - -#if 0 - printf("Entered danube_switch_initialize()\n"); -#endif - - if (!(dev = (struct eth_device *) malloc (sizeof *dev))) - { - printf("Failed to allocate memory\n"); - return 0; - } - memset(dev, 0, sizeof(*dev)); - - danube_dma_init(); - danube_init_switch_chip(REV_MII_MODE); - -#ifdef CLK_OUT2_25MHZ - *DANUBE_GPIO_P0_DIR=0x0000ae78; - *DANUBE_GPIO_P0_ALTSEL0=0x00008078; - //joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080; - *DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1 - *DANUBE_CGU_IFCCR=0x00400010; - *DANUBE_GPIO_P0_OD=0x0000ae78; -#endif - - /*patch for 6996*/ - - *DANUBE_RCU_RST_REQ |=1; - mdelay(200); - *DANUBE_RCU_RST_REQ &=(unsigned long)~1; - mdelay(1); - /*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602; - */ - /*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602; - */ - /***************/ - sprintf(dev->name, "danube Switch"); - dev->init = danube_switch_init; - dev->halt = danube_switch_halt; - dev->send = danube_switch_send; - dev->recv = danube_switch_recv; - - eth_register(dev); - - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0xc1010000; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - chipid = (unsigned short)(*DANUBE_PPE_ETOP_MDIO_ACC & 0xffff); - - if (chipid != TANTOS_CHIP_ID) // not tantos switch. - { - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F; - while((*DANUBE_PPE_ETOP_MDIO_ACC)&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8003840F; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8005840F; - //while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - //*DANUBE_PPE_ETOP_MDIO_ACC =0x8006840F; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8007840F; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8008840F; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602; -#ifdef CLK_OUT2_25MHZ - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80334000; -#endif - } - else // Tantos switch chip - { - //printf("Tantos Switch detected!!\n\r"); - - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80a10004; - - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80c10004; - - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80f50773; - - /* Software workaround. */ - /* PHY reset from P0 to P4. */ - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - - mdelay(1); - *DANUBE_PPE_ETOP_MDIO_ACC =0x81218000; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - /* P0 */ - *DANUBE_PPE_ETOP_MDIO_ACC =0x81200400; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - /* P1 */ - *DANUBE_PPE_ETOP_MDIO_ACC =0x81200420; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - /* P2 */ - *DANUBE_PPE_ETOP_MDIO_ACC =0x81200440; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - /* P3 */ - *DANUBE_PPE_ETOP_MDIO_ACC =0x81200460; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - /* p4 */ - *DANUBE_PPE_ETOP_MDIO_ACC =0x81200480; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - } - - return 1; -} - -int danube_switch_init(struct eth_device *dev, bd_t * bis) -{ - int i; - - tx_num=0; - rx_num=0; - - /* Reset DMA */ -// serial_puts("i \n\0"); - - *DANUBE_DMA_CS=RX_CHAN_NO; - *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/ - *DANUBE_DMA_CPOLL= 0x80000040; - /*set descriptor base*/ - *DANUBE_DMA_CDBA=(u32)rx_des_ring; - *DANUBE_DMA_CDLEN=NUM_RX_DESC; - *DANUBE_DMA_CIE = 0; - *DANUBE_DMA_CCTRL=0x30000; - - *DANUBE_DMA_CS=TX_CHAN_NO; - *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/ - *DANUBE_DMA_CPOLL= 0x80000040; - *DANUBE_DMA_CDBA=(u32)tx_des_ring; - *DANUBE_DMA_CDLEN=NUM_TX_DESC; - *DANUBE_DMA_CIE = 0; - *DANUBE_DMA_CCTRL=0x30100; - - for(i=0;i < NUM_RX_DESC; i++) - { - danube_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_des_ring[i]); - rx_desc->status.word=0; - rx_desc->status.field.OWN=1; - rx_desc->status.field.DataLen=PKTSIZE_ALIGN; /* 1536 */ - rx_desc->DataPtr=(u32)KSEG1ADDR(NetRxPackets[i]); - } - - for(i=0;i < NUM_TX_DESC; i++) - { - danube_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_des_ring[i]); - memset(tx_desc, 0, sizeof(tx_des_ring[0])); - } - /* turn on DMA rx & tx channel - */ - *DANUBE_DMA_CS=RX_CHAN_NO; - *DANUBE_DMA_CCTRL|=1;/*reset and turn on the channel*/ - - return 0; -} - -void danube_switch_halt(struct eth_device *dev) -{ - int i; - for(i=0;i<8;i++) - { - *DANUBE_DMA_CS=i; - *DANUBE_DMA_CCTRL&=~1;/*stop the dma channel*/ - } -// udelay(1000000); -} - -int danube_switch_send(struct eth_device *dev, volatile void *packet,int length) -{ - - int i; - int res = -1; - - danube_tx_descriptor_t * tx_desc= KSEG1ADDR(&tx_des_ring[tx_num]); - - if (length <= 0) - { - printf ("%s: bad packet size: %d\n", dev->name, length); - goto Done; - } - - for(i=0; tx_desc->status.field.OWN==1; i++) - { - if(i>=TOUT_LOOP) - { - printf("NO Tx Descriptor..."); - goto Done; - } - } - - //serial_putc('s'); - - tx_desc->status.field.Sop=1; - tx_desc->status.field.Eop=1; - tx_desc->status.field.C=0; - tx_desc->DataPtr = (u32)KSEG1ADDR(packet); - if(length<60) - tx_desc->status.field.DataLen = 60; - else - tx_desc->status.field.DataLen = (u32)length; - - asm("SYNC"); - tx_desc->status.field.OWN=1; - - res=length; - tx_num++; - if(tx_num==NUM_TX_DESC) tx_num=0; - *DANUBE_DMA_CS=TX_CHAN_NO; - - if(!(*DANUBE_DMA_CCTRL & 1)) - *DANUBE_DMA_CCTRL|=1; - -Done: - return res; -} - -int danube_switch_recv(struct eth_device *dev) -{ - int length = 0; - danube_rx_descriptor_t * rx_desc; - - for (;;) - { - rx_desc = KSEG1ADDR(&rx_des_ring[rx_num]); - - if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1)) - { - break; - } - - length = rx_desc->status.field.DataLen; - if (length) - { - NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_num]), length - 4); - // serial_putc('*'); - } - else - { - printf("Zero length!!!\n"); - } - - rx_desc->status.field.Sop=0; - rx_desc->status.field.Eop=0; - rx_desc->status.field.C=0; - rx_desc->status.field.DataLen=PKTSIZE_ALIGN; - rx_desc->status.field.OWN=1; - rx_num++; - if(rx_num==NUM_RX_DESC) rx_num=0; - - } - - return length; -} - - -static void danube_init_switch_chip(int mode) -{ - /*get and set mac address for MAC*/ - char *tmp; - tmp = getenv ("ethaddr"); - if (NULL == tmp) { - printf("Can't get environment ethaddr!!!\n"); - // return NULL; - } else { - printf("ethaddr=%s\n", tmp); - } - *DANUBE_PMU_PWDCR = *DANUBE_PMU_PWDCR & 0xFFFFEFDF; - *DANUBE_PPE32_ETOP_MDIO_CFG &= ~0x6; - *DANUBE_PPE32_ENET_MAC_CFG = 0x187; - - // turn on port0, set to rmii and turn off port1. - if (mode==REV_MII_MODE) - { - *DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x0000000a; - } - else if (mode == MII_MODE) - { - *DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x00000008; - } - - *DANUBE_PPE32_ETOP_IG_PLEN_CTRL = 0x4005ee; // set packetlen. - *ENET_MAC_CFG |= 1<<11; /*enable the crc*/ - return; -} - - -static void danube_dma_init(void) -{ -// serial_puts("d \n\0"); - - *DANUBE_PMU_PWDCR &=~(1<$ARGV[2]") || die("\nOutput file open fail\n"); - -$i=0; -while ($line = ){ - if($line=~/\w/){ - if($line!~/[;#\*]/){ - if($i eq 0){ - printf OUTFILE ("33333333"); - } - chomp($line); - $line=~s/\t//; - @array=split(/ +/,$line); - $j=0; - while(@array[$j]!~/\w/) - { - $j=$j+1; - - } - $addr=@array[$j]; - $regval=@array[$j+1]; - $addr=~s/0x//; - $regval=~s/0x//; - printf OUTFILE ("%08x%08x",hex($addr),hex($regval)); - $i=$i+1; - if($i eq 8) - { - $i=0; - printf OUTFILE ("\n"); - } - - } - } - - } - - while($i lt 8 && $i gt 0){ - printf OUTFILE "00"x8; - $i=$i+1; - } - if($i eq 8){ - printf OUTFILE ("\n"); - } - -while($aline=){ - $aline=uc($aline); - chomp($aline); - next if(($aline=~/^S0/) || ($aline=~/^S7/)); - ($lineid, $length, $address, @bytes) = unpack"A2A2A8"."A2"x300, $aline; - $length = hex($length); - $address = hex($address); - $length -=5; - $i=0; - - while($length>0){ - if($firstime==1){ - $addstr = sprintf("%x", $address); - $addstr = "0"x(8-length($addstr)).$addstr; - print OUTFILE $addstr; - addchsum($addstr); - $firstime=0; - $currentaddr=$address; - $loadaddr = $addstr; - } - else{ - if($count==64){ - $addstr = sprintf("%x", $currentaddr); - $addstr = "0"x(8-length($addstr)).$addstr; - print OUTFILE $addstr; - addchsum($addstr); - $count=0; - } - } - while($count<64){ - $bytes[$i]=~tr/ABCDEF/abcdef/; - print OUTFILE "$bytes[$i]"; - addchsum($bytes[$i]); - $i++; - $count++; - $length--; - last if($length==0); - } - if($count==64){ - print OUTFILE "\n"; - #print OUTFILE "\r"; - $currentaddr+=64; - } - } -} -if($count != 64){ - $tmp = "00"; - for($i=0;$i<(64-$count);$i++){ - print OUTFILE "00"; - addchsum($tmp); - } - print OUTFILE "\n"; - #print OUTFILE "\r"; -} - - -print OUTFILE "11"x4; -use integer; -$chsum=$chsum & 0xffffffff; -$chsum = sprintf("%X", $chsum); -$chsum = "0"x(8-length($chsum)).$chsum; -$chsum =~tr/ABCDEF/abcdef/; -print OUTFILE $chsum; -print OUTFILE "00"x60; -print OUTFILE "\n"; -#print OUTFILE "\r"; - -print OUTFILE "99"x4; -print OUTFILE $loadaddr; -print OUTFILE "00"x60; -print OUTFILE "\n"; -#print OUTFILE "\r"; - - -close OUTFILE; -#END of Program - - - -sub addchsum{ - my $cc=$_[0]; - $holder=$holder.$cc; - if(length($holder)==8){ - $holder = hex($holder); - $chsum+=$holder; - $holder=""; - } -} -#END - - diff --git a/package/uboot-ifxmips/files/include/LzmaDecode.h b/package/uboot-ifxmips/files/include/LzmaDecode.h deleted file mode 100644 index 2870eeb9c9..0000000000 --- a/package/uboot-ifxmips/files/include/LzmaDecode.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - LzmaDecode.h - LZMA Decoder interface - - LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) - http://www.7-zip.org/ - - LZMA SDK is licensed under two licenses: - 1) GNU Lesser General Public License (GNU LGPL) - 2) Common Public License (CPL) - It means that you can select one of these two licenses and - follow rules of that license. - - SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions - to this file, however, are subject to the LGPL or CPL terms. -*/ - -#ifndef __LZMADECODE_H -#define __LZMADECODE_H - -#include "LzmaTypes.h" - -/* #define _LZMA_IN_CB */ -/* Use callback for input data */ - -/* #define _LZMA_OUT_READ */ -/* Use read function for output data */ - -/* #define _LZMA_PROB32 */ -/* It can increase speed on some 32-bit CPUs, - but memory usage will be doubled in that case */ - -/* #define _LZMA_LOC_OPT */ -/* Enable local speed optimizations inside code */ - -#ifdef _LZMA_PROB32 -#define CProb UInt32 -#else -#define CProb UInt16 -#endif - -#define LZMA_RESULT_OK 0 -#define LZMA_RESULT_DATA_ERROR 1 - -#ifdef _LZMA_IN_CB -typedef struct _ILzmaInCallback -{ - int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); -} ILzmaInCallback; -#endif - -#define LZMA_BASE_SIZE 1846 -#define LZMA_LIT_SIZE 768 - -#define LZMA_PROPERTIES_SIZE 5 - -typedef struct _CLzmaProperties -{ - int lc; - int lp; - int pb; - #ifdef _LZMA_OUT_READ - UInt32 DictionarySize; - #endif -}CLzmaProperties; - -int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); - -#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) - -#define kLzmaNeedInitId (-2) - -typedef struct _CLzmaDecoderState -{ - CLzmaProperties Properties; - CProb *Probs; - - #ifdef _LZMA_IN_CB - const unsigned char *Buffer; - const unsigned char *BufferLim; - #endif - - #ifdef _LZMA_OUT_READ - unsigned char *Dictionary; - UInt32 Range; - UInt32 Code; - UInt32 DictionaryPos; - UInt32 GlobalPos; - UInt32 DistanceLimit; - UInt32 Reps[4]; - int State; - int RemainLen; - unsigned char TempDictionary[4]; - #endif -} CLzmaDecoderState; - -#ifdef _LZMA_OUT_READ -#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } -#endif - -int LzmaDecode(CLzmaDecoderState *vs, - #ifdef _LZMA_IN_CB - ILzmaInCallback *inCallback, - #else - const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, - #endif - unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); - -#endif diff --git a/package/uboot-ifxmips/files/include/LzmaTypes.h b/package/uboot-ifxmips/files/include/LzmaTypes.h deleted file mode 100644 index 288c5e45d7..0000000000 --- a/package/uboot-ifxmips/files/include/LzmaTypes.h +++ /dev/null @@ -1,45 +0,0 @@ -/* -LzmaTypes.h - -Types for LZMA Decoder - -This file written and distributed to public domain by Igor Pavlov. -This file is part of LZMA SDK 4.40 (2006-05-01) -*/ - -#ifndef __LZMATYPES_H -#define __LZMATYPES_H - -#ifndef _7ZIP_BYTE_DEFINED -#define _7ZIP_BYTE_DEFINED -typedef unsigned char Byte; -#endif - -#ifndef _7ZIP_UINT16_DEFINED -#define _7ZIP_UINT16_DEFINED -typedef unsigned short UInt16; -#endif - -#ifndef _7ZIP_UINT32_DEFINED -#define _7ZIP_UINT32_DEFINED -#ifdef _LZMA_UINT32_IS_ULONG -typedef unsigned long UInt32; -#else -typedef unsigned int UInt32; -#endif -#endif - -/* #define _LZMA_SYSTEM_SIZE_T */ -/* Use system's size_t. You can use it to enable 64-bit sizes supporting */ - -#ifndef _7ZIP_SIZET_DEFINED -#define _7ZIP_SIZET_DEFINED -#ifdef _LZMA_SYSTEM_SIZE_T -#include -typedef size_t SizeT; -#else -typedef UInt32 SizeT; -#endif -#endif - -#endif diff --git a/package/uboot-ifxmips/files/include/LzmaWrapper.h b/package/uboot-ifxmips/files/include/LzmaWrapper.h deleted file mode 100644 index 2f9a3ffbbb..0000000000 --- a/package/uboot-ifxmips/files/include/LzmaWrapper.h +++ /dev/null @@ -1,36 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : LzmaWrapper.h -** PROJECT : bootloader -** MODULES : U-boot -** -** DATE : 2 Nov 2006 -** AUTHOR : Lin Mars -** DESCRIPTION : LZMA decoder support for U-boot 1.1.5 -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Date $Author $Comment -** 2 Nov 2006 Lin Mars init version which derived from LzmaTest.c from -** LZMA v4.43 SDK -*******************************************************************************/ -#ifndef __LZMA_WRAPPER_H__ -#define __LZMA_WRAPPER_H__ - -#ifndef LZMA_RESULT_OK -#define LZMA_RESULT_OK 0 -#endif -#ifndef LZMA_RESULT_DATA_ERROR -#define LZMA_RESULT_DATA_ERROR 1 -#endif - -extern int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len); - -#endif /*__LZMA_WRAPPER_H__*/ diff --git a/package/uboot-ifxmips/files/include/asm-mips/danube.h b/package/uboot-ifxmips/files/include/asm-mips/danube.h deleted file mode 100644 index c0be9fbd61..0000000000 --- a/package/uboot-ifxmips/files/include/asm-mips/danube.h +++ /dev/null @@ -1,2033 +0,0 @@ -#ifndef DANUBE_H -#define DANUBE_H -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - -/***********************************************************************/ -/* Module : MEI register address and bits */ -/***********************************************************************/ -#define MEI_SPACE_ACCESS 0xB0100C00 -#define MEI_DATA_XFR (0x0000 + MEI_SPACE_ACCESS) -#define MEI_VERSION (0x0200 + MEI_SPACE_ACCESS) -#define ARC_GP_STAT (0x0204 + MEI_SPACE_ACCESS) -#define MEI_XFR_ADDR (0x020C + MEI_SPACE_ACCESS) -#define MEI_TO_ARC_INT (0x021C + MEI_SPACE_ACCESS) -#define ARC_TO_MEI_INT (0x0220 + MEI_SPACE_ACCESS) -#define ARC_TO_MEI_INT_MASK (0x0224 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_WAD (0x0228 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_RAD (0x022C + MEI_SPACE_ACCESS) -#define MEI_DEBUG_DATA (0x0230 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_DEC (0x0234 + MEI_SPACE_ACCESS) -#define MEI_CONTROL (0x0238 + MEI_SPACE_ACCESS) -#define AT_CELLRDY_BC0 (0x023C + MEI_SPACE_ACCESS) -#define AT_CELLRDY_BC1 (0x0240 + MEI_SPACE_ACCESS) -#define AR_CELLRDY_BC0 (0x0244 + MEI_SPACE_ACCESS) -#define AR_CELLRDY_BC1 (0x0248 + MEI_SPACE_ACCESS) -#define AAI_ACCESS (0x024C + MEI_SPACE_ACCESS) -#define AAITXCB0 (0x0300 + MEI_SPACE_ACCESS) -#define AAITXCB1 (0x0304 + MEI_SPACE_ACCESS) -#define AAIRXCB0 (0x0308 + MEI_SPACE_ACCESS) -#define AAIRXCB1 (0x030C + MEI_SPACE_ACCESS) - - -/***********************************************************************/ -/* Module : WDT register address and bits */ -/***********************************************************************/ -#define DANUBE_BIU_WDT_BASE (0xBf8803F0) -#define DANUBE_BIU_WDT_CR (0x0000 + DANUBE_BIU_WDT_BASE) -#define DANUBE_BIU_WDT_SR (0x0008 + DANUBE_BIU_WDT_BASE) - - -/***********************************************************************/ -/* Module : PMU register address and bits */ -/***********************************************************************/ -#define DANUBE_PMU_BASE_ADDR (KSEG1+0x1F102000) - -/***PM Control Register***/ -#define DANUBE_PMU_CR ((volatile u32*)(0x001C + DANUBE_PMU_BASE_ADDR)) -#define DANUBE_PMU_PWDCR DANUBE_PMU_CR -#define DANUBE_PMU_SR ((volatile u32*)(0x0020 + DANUBE_PMU_BASE_ADDR)) - -#define DANUBE_PMU_DMA_SHIFT 5 -#define DANUBE_PMU_PPE_SHIFT 13 -#define DANUBE_PMU_ETOP_SHIFT 22 -#define DANUBE_PMU_ENET0_SHIFT 24 -#define DANUBE_PMU_ENET1_SHIFT 25 - - -#define DANUBE_PMU DANUBE_PMU_BASE_ADDR -/***PM Global Enable Register***/ -#define DANUBE_PMU_PM_GEN ((volatile u32*)(DANUBE_PMU+ 0x0000)) -#define DANUBE_PMU_PM_GEN_EN16 (1 << 16) -#define DANUBE_PMU_PM_GEN_EN15 (1 << 15) -#define DANUBE_PMU_PM_GEN_EN14 (1 << 14) -#define DANUBE_PMU_PM_GEN_EN13 (1 << 13) -#define DANUBE_PMU_PM_GEN_EN12 (1 << 12) -#define DANUBE_PMU_PM_GEN_EN11 (1 << 11) -#define DANUBE_PMU_PM_GEN_EN10 (1 << 10) -#define DANUBE_PMU_PM_GEN_EN9 (1 << 9) -#define DANUBE_PMU_PM_GEN_EN8 (1 << 8) -#define DANUBE_PMU_PM_GEN_EN7 (1 << 7) -#define DANUBE_PMU_PM_GEN_EN6 (1 << 6) -#define DANUBE_PMU_PM_GEN_EN5 (1 << 5) -#define DANUBE_PMU_PM_GEN_EN4 (1 << 4) -#define DANUBE_PMU_PM_GEN_EN3 (1 << 3) -#define DANUBE_PMU_PM_GEN_EN2 (1 << 2) -#define DANUBE_PMU_PM_GEN_EN0 (1 << 0) - -/***PM Power Down Enable Register***/ -#define DANUBE_PMU_PM_PDEN ((volatile u32*)(DANUBE_PMU+ 0x0008)) -#define DANUBE_PMU_PM_PDEN_EN16 (1 << 16) -#define DANUBE_PMU_PM_PDEN_EN15 (1 << 15) -#define DANUBE_PMU_PM_PDEN_EN14 (1 << 14) -#define DANUBE_PMU_PM_PDEN_EN13 (1 << 13) -#define DANUBE_PMU_PM_PDEN_EN12 (1 << 12) -#define DANUBE_PMU_PM_PDEN_EN11 (1 << 11) -#define DANUBE_PMU_PM_PDEN_EN10 (1 << 10) -#define DANUBE_PMU_PM_PDEN_EN9 (1 << 9) -#define DANUBE_PMU_PM_PDEN_EN8 (1 << 8) -#define DANUBE_PMU_PM_PDEN_EN7 (1 << 7) -#define DANUBE_PMU_PM_PDEN_EN5 (1 << 5) -#define DANUBE_PMU_PM_PDEN_EN4 (1 << 4) -#define DANUBE_PMU_PM_PDEN_EN3 (1 << 3) -#define DANUBE_PMU_PM_PDEN_EN2 (1 << 2) -#define DANUBE_PMU_PM_PDEN_EN0 (1 << 0) - -/***PM Wake-Up from Power Down Register***/ -#define DANUBE_PMU_PM_WUP ((volatile u32*)(DANUBE_PMU+ 0x0010)) -#define DANUBE_PMU_PM_WUP_WUP16 (1 << 16) -#define DANUBE_PMU_PM_WUP_WUP15 (1 << 15) -#define DANUBE_PMU_PM_WUP_WUP14 (1 << 14) -#define DANUBE_PMU_PM_WUP_WUP13 (1 << 13) -#define DANUBE_PMU_PM_WUP_WUP12 (1 << 12) -#define DANUBE_PMU_PM_WUP_WUP11 (1 << 11) -#define DANUBE_PMU_PM_WUP_WUP10 (1 << 10) -#define DANUBE_PMU_PM_WUP_WUP9 (1 << 9) -#define DANUBE_PMU_PM_WUP_WUP8 (1 << 8) -#define DANUBE_PMU_PM_PDEN_EN7 (1 << 7) -#define DANUBE_PMU_PM_PDEN_EN5 (1 << 5) -#define DANUBE_PMU_PM_PDEN_EN4 (1 << 4) -#define DANUBE_PMU_PM_PDEN_EN3 (1 << 3) -#define DANUBE_PMU_PM_PDEN_EN2 (1 << 2) -#define DANUBE_PMU_PM_PDEN_EN0 (1 << 0) - -/***PM Wake-Up from Power Down Register***/ -#define DANUBE_PMU_PM_WUP ((volatile u32*)(DANUBE_PMU+ 0x0010)) -#define DANUBE_PMU_PM_WUP_WUP16 (1 << 16) -#define DANUBE_PMU_PM_WUP_WUP15 (1 << 15) -#define DANUBE_PMU_PM_WUP_WUP14 (1 << 14) -#define DANUBE_PMU_PM_WUP_WUP13 (1 << 13) -#define DANUBE_PMU_PM_WUP_WUP12 (1 << 12) -#define DANUBE_PMU_PM_WUP_WUP11 (1 << 11) -#define DANUBE_PMU_PM_WUP_WUP10 (1 << 10) -#define DANUBE_PMU_PM_WUP_WUP9 (1 << 9) -#define DANUBE_PMU_PM_WUP_WUP8 (1 << 8) -#define DANUBE_PMU_PM_WUP_WUP7 (1 << 7) -#define DANUBE_PMU_PM_WUP_WUP5 (1 << 5) -#define DANUBE_PMU_PM_WUP_WUP4 (1 << 4) -#define DANUBE_PMU_PM_WUP_WUP3 (1 << 3) -#define DANUBE_PMU_PM_WUP_WUP2 (1 << 2) -#define DANUBE_PMU_PM_WUP_WUP0 (1 << 0) - -/***PM Control Register***/ -#define DANUBE_PMU_PM_CR ((volatile u32*)(DANUBE_PMU+ 0x0014)) -#define DANUBE_PMU_PM_CR_AWEN (1 << 31) -#define DANUBE_PMU_PM_CR_SWRST (1 << 30) -#define DANUBE_PMU_PM_CR_SWCR (1 << 2) -#define DANUBE_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : RCU register address and bits */ -/***********************************************************************/ -#define DANUBE_RCU_BASE_ADDR (0xBF203000) - -#define DANUBE_RCU_REQ (0x0010 + DANUBE_RCU_BASE_ADDR) -#define DANUBE_RCU_RST_REQ ((volatile u32*)(DANUBE_RCU_REQ)) -#define DANUBE_RCU_STAT (0x0014 + DANUBE_RCU_BASE_ADDR) -#define DANUBE_RCU_RST_SR ( (volatile u32 *)(DANUBE_RCU_STAT)) -#define DANUBE_RCU_PCI_RDY ( (volatile u32 *)(DANUBE_RCU_BASE_ADDR+0x28)) -#define DANUBE_RCU_MON (0x0030 + DANUBE_RCU_BASE_ADDR) - - -/***********************************************************************/ -/* Module : BCU register address and bits */ -/***********************************************************************/ -#define DANUBE_BCU_BASE_ADDR (0xB0100000) -/***BCU Control Register (0010H)***/ -#define DANUBE_BCU_CON (0x0010 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24) -#define DANUBE_BCU_BCU_CON_SPE (1 << 19) -#define DANUBE_BCU_BCU_CON_PSE (1 << 18) -#define DANUBE_BCU_BCU_CON_DBG (1 << 16) -#define DANUBE_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0) - - -/***BCU Error Control Capture Register (0020H)***/ -#define DANUBE_BCU_ECON (0x0020 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24) -#define DANUBE_BCU_BCU_ECON_RDN (1 << 23) -#define DANUBE_BCU_BCU_ECON_WRN (1 << 22) -#define DANUBE_BCU_BCU_ECON_SVM (1 << 21) -#define DANUBE_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19) -#define DANUBE_BCU_BCU_ECON_ABT (1 << 18) -#define DANUBE_BCU_BCU_ECON_RDY (1 << 17) -#define DANUBE_BCU_BCU_ECON_TOUT (1 << 16) -#define DANUBE_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0) -#define DANUBE_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28) - -/***BCU Error Address Capture Register (0024 H)***/ -#define DANUBE_BCU_EADD (0x0024 + DANUBE_BCU_BASE_ADDR) - -/***BCU Error Data Capture Register (0028H)***/ -#define DANUBE_BCU_EDAT (0x0028 + DANUBE_BCU_BASE_ADDR) - -#define DANUBE_BCU_IRNEN (0x00F4 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_IRNICR (0x00F8 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_IRNCR (0x00FC + DANUBE_BCU_BASE_ADDR) - - -/***********************************************************************/ -/* Module : MBC register address and bits */ -/***********************************************************************/ - -#define DANUBE_MBC (0xBF103000) -/***********************************************************************/ - - -/***Mailbox CPU Configuration Register***/ -#define DANUBE_MBC_MBC_CFG ((volatile u32*)(DANUBE_MBC+ 0x0080)) -#define DANUBE_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6) -#define DANUBE_MBC_MBC_CFG_RES (1 << 5) -#define DANUBE_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1) -#define DANUBE_MBC_MBC_CFG_SIZE (1 << 0) - -/***Mailbox CPU Interrupt Status Register***/ -#define DANUBE_MBC_MBC_ISR ((volatile u32*)(DANUBE_MBC+ 0x0084)) -#define DANUBE_MBC_MBC_ISR_B3DA (1 << 31) -#define DANUBE_MBC_MBC_ISR_B2DA (1 << 30) -#define DANUBE_MBC_MBC_ISR_B1E (1 << 29) -#define DANUBE_MBC_MBC_ISR_B0E (1 << 28) -#define DANUBE_MBC_MBC_ISR_WDT (1 << 27) -#define DANUBE_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask Register***/ -#define DANUBE_MBC_MBC_MSK ((volatile u32*)(DANUBE_MBC+ 0x0088)) -#define DANUBE_MBC_MBC_MSK_B3DA (1 << 31) -#define DANUBE_MBC_MBC_MSK_B2DA (1 << 30) -#define DANUBE_MBC_MBC_MSK_B1E (1 << 29) -#define DANUBE_MBC_MBC_MSK_B0E (1 << 28) -#define DANUBE_MBC_MBC_MSK_WDT (1 << 27) -#define DANUBE_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 01 Register***/ -#define DANUBE_MBC_MBC_MSK01 ((volatile u32*)(DANUBE_MBC+ 0x008C)) -#define DANUBE_MBC_MBC_MSK01_B3DA (1 << 31) -#define DANUBE_MBC_MBC_MSK01_B2DA (1 << 30) -#define DANUBE_MBC_MBC_MSK01_B1E (1 << 29) -#define DANUBE_MBC_MBC_MSK01_B0E (1 << 28) -#define DANUBE_MBC_MBC_MSK01_WDT (1 << 27) -#define DANUBE_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 10 Register***/ -#define DANUBE_MBC_MBC_MSK10 ((volatile u32*)(DANUBE_MBC+ 0x0090)) -#define DANUBE_MBC_MBC_MSK10_B3DA (1 << 31) -#define DANUBE_MBC_MBC_MSK10_B2DA (1 << 30) -#define DANUBE_MBC_MBC_MSK10_B1E (1 << 29) -#define DANUBE_MBC_MBC_MSK10_B0E (1 << 28) -#define DANUBE_MBC_MBC_MSK10_WDT (1 << 27) -#define DANUBE_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Short Command Register***/ -#define DANUBE_MBC_MBC_CMD ((volatile u32*)(DANUBE_MBC+ 0x0094)) -#define DANUBE_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***Mailbox CPU Input Data of Buffer 0***/ -#define DANUBE_MBC_MBC_ID0 ((volatile u32*)(DANUBE_MBC+ 0x0000)) -#define DANUBE_MBC_MBC_ID0_INDATA - -/***Mailbox CPU Input Data of Buffer 1***/ -#define DANUBE_MBC_MBC_ID1 ((volatile u32*)(DANUBE_MBC+ 0x0020)) -#define DANUBE_MBC_MBC_ID1_INDATA - -/***Mailbox CPU Output Data of Buffer 2***/ -#define DANUBE_MBC_MBC_OD2 ((volatile u32*)(DANUBE_MBC+ 0x0040)) -#define DANUBE_MBC_MBC_OD2_OUTDATA - -/***Mailbox CPU Output Data of Buffer 3***/ -#define DANUBE_MBC_MBC_OD3 ((volatile u32*)(DANUBE_MBC+ 0x0060)) -#define DANUBE_MBC_MBC_OD3_OUTDATA - -/***Mailbox CPU Control Register of Buffer 0***/ -#define DANUBE_MBC_MBC_CR0 ((volatile u32*)(DANUBE_MBC+ 0x0004)) -#define DANUBE_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 1***/ -#define DANUBE_MBC_MBC_CR1 ((volatile u32*)(DANUBE_MBC+ 0x0024)) -#define DANUBE_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 2***/ -#define DANUBE_MBC_MBC_CR2 ((volatile u32*)(DANUBE_MBC+ 0x0044)) -#define DANUBE_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 3***/ -#define DANUBE_MBC_MBC_CR3 ((volatile u32*)(DANUBE_MBC+ 0x0064)) -#define DANUBE_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Free Space of Buffer 0***/ -#define DANUBE_MBC_MBC_FS0 ((volatile u32*)(DANUBE_MBC+ 0x0008)) -#define DANUBE_MBC_MBC_FS0_FS - -/***Mailbox CPU Free Space of Buffer 1***/ -#define DANUBE_MBC_MBC_FS1 ((volatile u32*)(DANUBE_MBC+ 0x0028)) -#define DANUBE_MBC_MBC_FS1_FS - -/***Mailbox CPU Free Space of Buffer 2***/ -#define DANUBE_MBC_MBC_FS2 ((volatile u32*)(DANUBE_MBC+ 0x0048)) -#define DANUBE_MBC_MBC_FS2_FS - -/***Mailbox CPU Free Space of Buffer 3***/ -#define DANUBE_MBC_MBC_FS3 ((volatile u32*)(DANUBE_MBC+ 0x0068)) -#define DANUBE_MBC_MBC_FS3_FS - -/***Mailbox CPU Data Available in Buffer 0***/ -#define DANUBE_MBC_MBC_DA0 ((volatile u32*)(DANUBE_MBC+ 0x000C)) -#define DANUBE_MBC_MBC_DA0_DA - -/***Mailbox CPU Data Available in Buffer 1***/ -#define DANUBE_MBC_MBC_DA1 ((volatile u32*)(DANUBE_MBC+ 0x002C)) -#define DANUBE_MBC_MBC_DA1_DA - -/***Mailbox CPU Data Available in Buffer 2***/ -#define DANUBE_MBC_MBC_DA2 ((volatile u32*)(DANUBE_MBC+ 0x004C)) -#define DANUBE_MBC_MBC_DA2_DA - -/***Mailbox CPU Data Available in Buffer 3***/ -#define DANUBE_MBC_MBC_DA3 ((volatile u32*)(DANUBE_MBC+ 0x006C)) -#define DANUBE_MBC_MBC_DA3_DA - -/***Mailbox CPU Input Absolute Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_IABS0 ((volatile u32*)(DANUBE_MBC+ 0x0010)) -#define DANUBE_MBC_MBC_IABS0_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_IABS1 ((volatile u32*)(DANUBE_MBC+ 0x0030)) -#define DANUBE_MBC_MBC_IABS1_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_IABS2 ((volatile u32*)(DANUBE_MBC+ 0x0050)) -#define DANUBE_MBC_MBC_IABS2_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_IABS3 ((volatile u32*)(DANUBE_MBC+ 0x0070)) -#define DANUBE_MBC_MBC_IABS3_IABS - -/***Mailbox CPU Input Temporary Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_ITMP0 ((volatile u32*)(DANUBE_MBC+ 0x0014)) -#define DANUBE_MBC_MBC_ITMP0_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_ITMP1 ((volatile u32*)(DANUBE_MBC+ 0x0034)) -#define DANUBE_MBC_MBC_ITMP1_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_ITMP2 ((volatile u32*)(DANUBE_MBC+ 0x0054)) -#define DANUBE_MBC_MBC_ITMP2_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_ITMP3 ((volatile u32*)(DANUBE_MBC+ 0x0074)) -#define DANUBE_MBC_MBC_ITMP3_ITMP - -/***Mailbox CPU Output Absolute Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_OABS0 ((volatile u32*)(DANUBE_MBC+ 0x0018)) -#define DANUBE_MBC_MBC_OABS0_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_OABS1 ((volatile u32*)(DANUBE_MBC+ 0x0038)) -#define DANUBE_MBC_MBC_OABS1_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_OABS2 ((volatile u32*)(DANUBE_MBC+ 0x0058)) -#define DANUBE_MBC_MBC_OABS2_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_OABS3 ((volatile u32*)(DANUBE_MBC+ 0x0078)) -#define DANUBE_MBC_MBC_OABS3_OABS - -/***Mailbox CPU Output Temporary Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_OTMP0 ((volatile u32*)(DANUBE_MBC+ 0x001C)) -#define DANUBE_MBC_MBC_OTMP0_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_OTMP1 ((volatile u32*)(DANUBE_MBC+ 0x003C)) -#define DANUBE_MBC_MBC_OTMP1_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_OTMP2 ((volatile u32*)(DANUBE_MBC+ 0x005C)) -#define DANUBE_MBC_MBC_OTMP2_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_OTMP3 ((volatile u32*)(DANUBE_MBC+ 0x007C)) -#define DANUBE_MBC_MBC_OTMP3_OTMP - -/***DSP Control Register***/ -#define DANUBE_MBC_DCTRL ((volatile u32*)(DANUBE_MBC+ 0x00A0)) -#define DANUBE_MBC_DCTRL_BA (1 << 0) -#define DANUBE_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1) -#define DANUBE_MBC_DCTRL_IDL (1 << 4) -#define DANUBE_MBC_DCTRL_RES (1 << 15) - -/***DSP Status Register***/ -#define DANUBE_MBC_DSTA ((volatile u32*)(DANUBE_MBC+ 0x00A4)) -#define DANUBE_MBC_DSTA_IDLE (1 << 0) -#define DANUBE_MBC_DSTA_PD (1 << 1) - -/***DSP Test 1 Register***/ -#define DANUBE_MBC_DTST1 ((volatile u32*)(DANUBE_MBC+ 0x00A8)) -#define DANUBE_MBC_DTST1_ABORT (1 << 0) -#define DANUBE_MBC_DTST1_HWF32 (1 << 1) -#define DANUBE_MBC_DTST1_HWF4M (1 << 2) -#define DANUBE_MBC_DTST1_HWFOP (1 << 3) - - -/***********************************************************************/ -/* Module : SSC1 register address and bits */ -/***********************************************************************/ -#define DANUBE_SSC1 (KSEG1+0x1e100800) -/***********************************************************************/ -/***SSC Clock Control Register***/ -#define DANUBE_SSC_CLC (0x0000) -#define DANUBE_SSC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_SSC_CLC_DISS (1 << 1) -#define DANUBE_SSC_CLC_DISR (1 << 0) -/***SSC Port Input Selection Register***/ -#define DANUBE_SSC_PISEL (0x0004) -/***SSC Identification Register***/ -#define DANUBE_SSC_ID (0x0008) -/***Control Register (Programming Mode)***/ -#define DANUBE_SSC_CON (0x0010) -#define DANUBE_SSC_CON_RUEN (1 << 12) -#define DANUBE_SSC_CON_TUEN (1 << 11) -#define DANUBE_SSC_CON_AEN (1 << 10) -#define DANUBE_SSC_CON_REN (1 << 9) -#define DANUBE_SSC_CON_TEN (1 << 8) -#define DANUBE_SSC_CON_LB (1 << 7) -#define DANUBE_SSC_CON_PO (1 << 6) -#define DANUBE_SSC_CON_PH (1 << 5) -#define DANUBE_SSC_CON_HB (1 << 4) -#define DANUBE_SSC_CON_BM(value) (((( 1 << 5) - 1) & (value)) << 16) -#define DANUBE_SSC_CON_RX_OFF (1 << 1) -#define DANUBE_SSC_CON_TX_OFF (1 << 0) -/***SCC Status Register***/ -#define DANUBE_SSC_STATE (0x0014) -#define DANUBE_SSC_STATE_EN (1 << 0) -#define DANUBE_SSC_STATE_MS (1 << 1) -#define DANUBE_SSC_STATE_BSY (1 << 13) -#define DANUBE_SSC_STATE_RUE (1 << 12) -#define DANUBE_SSC_STATE_TUE (1 << 11) -#define DANUBE_SSC_STATE_AE (1 << 10) -#define DANUBE_SSC_STATE_RE (1 << 9) -#define DANUBE_SSC_STATE_TE (1 << 8) -#define DANUBE_SSC_STATE_BC(value) (((( 1 << 5) - 1) & (value)) << 16) -/***SSC Write Hardware Modified Control Register***/ -#define DANUBE_SSC_WHBSTATE ( 0x0018) -#define DANUBE_SSC_WHBSTATE_SETBE (1 << 15) -#define DANUBE_SSC_WHBSTATE_SETPE (1 << 14) -#define DANUBE_SSC_WHBSTATE_SETRE (1 << 13) -#define DANUBE_SSC_WHBSTATE_SETTE (1 << 12) -#define DANUBE_SSC_WHBSTATE_CLRBE (1 << 11) -#define DANUBE_SSC_WHBSTATE_CLRPE (1 << 10) -#define DANUBE_SSC_WHBSTATE_CLRRE (1 << 9) -#define DANUBE_SSC_WHBSTATE_CLRTE (1 << 8) -/***SSC Transmitter Buffer Register***/ -#define DANUBE_SSC_TB (0x0020) -#define DANUBE_SSC_TB_TB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) -/***SSC Receiver Buffer Register***/ -#define DANUBE_SSC_RB (0x0024) -#define DANUBE_SSC_RB_RB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) -/***SSC Receive FIFO Control Register***/ -#define DANUBE_SSC_RXFCON (0x0030) -#define DANUBE_SSC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_SSC_RXFCON_RXTMEN (1 << 2) -#define DANUBE_SSC_RXFCON_RXFLU (1 << 1) -#define DANUBE_SSC_RXFCON_RXFEN (1 << 0) -/***SSC Transmit FIFO Control Register***/ -#define DANUBE_SSC_TXFCON ( 0x0034) -#define DANUBE_SSC_TXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_SSC_TXFCON_TXTMEN (1 << 2) -#define DANUBE_SSC_TXFCON_TXFLU (1 << 1) -#define DANUBE_SSC_TXFCON_TXFEN (1 << 0) -/***SSC FIFO Status Register***/ -#define DANUBE_SSC_FSTAT (0x0038) -#define DANUBE_SSC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_SSC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) -/***SSC Baudrate Timer Reload Register***/ -#define DANUBE_SSC_BR (0x0040) -#define DANUBE_SSC_BR_BR_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) -#define DANUBE_SSC_BRSTAT (0x0044) -#define DANUBE_SSC_SFCON (0x0060) -#define DANUBE_SSC_SFSTAT (0x0064) -#define DANUBE_SSC_GPOCON (0x0070) -#define DANUBE_SSC_GPOSTAT (0x0074) -#define DANUBE_SSC_WHBGPOSTAT (0x0078) -#define DANUBE_SSC_RXREQ (0x0080) -#define DANUBE_SSC_RXCNT (0x0084) -/*DMA Registers in Bus Clock Domain*/ -#define DANUBE_SSC_DMA_CON (0x00EC) -/*interrupt Node Registers in Bus Clock Domain*/ -#define DANUBE_SSC_IRNEN (0x00F4) -#define DANUBE_SSC_IRNCR (0x00F8) -#define DANUBE_SSC_IRNICR (0x00FC) -#define DANUBE_SSC_IRN_FIR 0x8 -#define DANUBE_SSC_IRN_EIR 0x4 -#define DANUBE_SSC_IRN_RIR 0x2 -#define DANUBE_SSC_IRN_TIR 0x1 - - -#define DANUBE_SSC1_CLC ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CLC)) -#define DANUBE_SSC1_ID ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_ID)) -#define DANUBE_SSC1_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CON)) -#define DANUBE_SSC1_STATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_STATE)) -#define DANUBE_SSC1_WHBSTATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBSTATE)) -#define DANUBE_SSC1_TB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TB)) -#define DANUBE_SSC1_RB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RB)) -#define DANUBE_SSC1_FSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_FSTAT)) -#define DANUBE_SSC1_PISEL ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_PISEL)) -#define DANUBE_SSC1_RXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXFCON)) -#define DANUBE_SSC1_TXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TXFCON)) -#define DANUBE_SSC1_BR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BR)) -#define DANUBE_SSC1_BRSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BRSTAT)) -#define DANUBE_SSC1_SFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFCON)) -#define DANUBE_SSC1_SFSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFSTAT)) -#define DANUBE_SSC1_GPOCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOCON)) -#define DANUBE_SSC1_GPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOSTAT)) -#define DANUBE_SSC1_WHBGPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBGPOSTAT)) -#define DANUBE_SSC1_RXREQ ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXREQ)) -#define DANUBE_SSC1_RXCNT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXCNT)) -#define DANUBE_SSC1_DMA_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_DMA_CON)) -#define DANUBE_SSC1_IRNEN ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNEN)) -#define DANUBE_SSC1_IRNICR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNICR)) -#define DANUBE_SSC1_IRNCR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNCR)) - -/***********************************************************************/ -/* Module : GPIO register address and bits */ -/***********************************************************************/ -#define DANUBE_GPIO (0xBE100B00) -/***Port 0 Data Output Register (0010H)***/ -#define DANUBE_GPIO_P0_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0010)) -/***Port 1 Data Output Register (0040H)***/ -#define DANUBE_GPIO_P1_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0040)) -/***Port 0 Data Input Register (0014H)***/ -#define DANUBE_GPIO_P0_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0014)) -/***Port 1 Data Input Register (0044H)***/ -#define DANUBE_GPIO_P1_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0044)) -/***Port 0 Direction Register (0018H)***/ -#define DANUBE_GPIO_P0_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0018)) -/***Port 1 Direction Register (0048H)***/ -#define DANUBE_GPIO_P1_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0048)) -/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -#define DANUBE_GPIO_P0_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x001C)) -/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -#define DANUBE_GPIO_P1_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x004C)) -/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -#define DANUBE_GPIO_P0_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0020)) -/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -#define DANUBE_GPIO_P1_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0050)) -/***Port 0 Open Drain Control Register (0024H)***/ -#define DANUBE_GPIO_P0_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0024)) -/***Port 1 Open Drain Control Register (0054H)***/ -#define DANUBE_GPIO_P1_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0054)) -/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -#define DANUBE_GPIO_P0_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0028)) -/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -#define DANUBE_GPIO_P1_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0058)) -/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -#define DANUBE_GPIO_P0_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x002C)) -/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -#define DANUBE_GPIO_P1_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x005C)) -/***Port 0 Pull Up Device Enable Register (0030 H)***/ -#define DANUBE_GPIO_P0_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0030)) -/***Port 1 Pull Up Device Enable Register (0060 H)***/ -#define DANUBE_GPIO_P1_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0060)) -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ - -#define DANUBE_CGU (0xBF103000) -/***********************************************************************/ - -/***CGU Clock PLL0 ***/ -#define DANUBE_CGU_PLL0_CFG ((volatile u32*)(DANUBE_CGU+ 0x0004)) -/***CGU Clock PLL1 ***/ -#define DANUBE_CGU_PLL1_CFG ((volatile u32*)(DANUBE_CGU+ 0x0008)) -/***CGU Clock SYS Mux Register***/ -#define DANUBE_CGU_SYS ((volatile u32*)(DANUBE_CGU+ 0x0010)) -/***CGU Interface Clock Control Register***/ -#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018)) -/***CGU PCI Clock Control Register**/ -#define DANUBE_CGU_PCICR ((volatile u32*)(DANUBE_CGU+ 0x0034)) - - -/***********************************************************************/ -/* Module : PCI register address and bits */ -/***********************************************************************/ -#define PCI_CR_PR_OFFSET 0xBE105400 -#define PCI_CR_CLK_CTRL_REG (PCI_CR_PR_OFFSET + 0x0000) - -#define PCI_CR_PCI_ID_REG (PCI_CR_PR_OFFSET + 0x0004) -#define PCI_CR_SFT_RST_REG (PCI_CR_PR_OFFSET + 0x0010) -#define PCI_CR_PCI_FPI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0014) -#define PCI_CR_FCI_PCI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0018) -#define PCI_CR_FPI_ERR_TAG_REG (PCI_CR_PR_OFFSET + 0x001C) -#define PCI_CR_PCI_IRR_REG (PCI_CR_PR_OFFSET + 0x0020) -#define PCI_CR_PCI_IRA_REG (PCI_CR_PR_OFFSET + 0x0024) -#define PCI_CR_PCI_IRM_REG (PCI_CR_PR_OFFSET + 0x0028) -#define PCI_CR_PCI_EOI_REG (PCI_CR_PR_OFFSET + 0x002C) -#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) -#define PCI_CR_DV_ID_REG (PCI_CR_PR_OFFSET + 0x0034) -#define PCI_CR_SUBSYS_ID_REG (PCI_CR_PR_OFFSET + 0x0038) -#define PCI_CR_PCI_PM_REG (PCI_CR_PR_OFFSET + 0x003C) -#define PCI_CR_CLASS_CODE1_REG (PCI_CR_PR_OFFSET + 0x0040) -#define PCI_CR_BAR11MASK_REG (PCI_CR_PR_OFFSET + 0x0044) -#define PCI_CR_BAR12MASK_REG (PCI_CR_PR_OFFSET + 0x0048) -#define PCI_CR_BAR13MASK_REG (PCI_CR_PR_OFFSET + 0x004C) -#define PCI_CR_BAR14MASK_REG (PCI_CR_PR_OFFSET + 0x0050) -#define PCI_CR_BAR15MASK_REG (PCI_CR_PR_OFFSET + 0x0054) -#define PCI_CR_BAR16MASK_REG (PCI_CR_PR_OFFSET + 0x0058) -#define PCI_CR_CIS_PT1_REG (PCI_CR_PR_OFFSET + 0x005C) -#define PCI_CR_SUBSYS_ID1_REG (PCI_CR_PR_OFFSET + 0x0060) -#define PCI_CR_PCI_ADDR_MAP11_REG (PCI_CR_PR_OFFSET + 0x0064) -#define PCI_CR_PCI_ADDR_MAP12_REG (PCI_CR_PR_OFFSET + 0x0068) -#define PCI_CR_PCI_ADDR_MAP13_REG (PCI_CR_PR_OFFSET + 0x006C) -#define PCI_CR_PCI_ADDR_MAP14_REG (PCI_CR_PR_OFFSET + 0x0070) -#define PCI_CR_PCI_ADDR_MAP15_REG (PCI_CR_PR_OFFSET + 0x0074) -#define PCI_CR_PCI_ADDR_MAP16_REG (PCI_CR_PR_OFFSET + 0x0078) -#define PCI_CR_FPI_SEG_EN_REG (PCI_CR_PR_OFFSET + 0x007C) -#define PCI_CR_PC_ARB_REG (PCI_CR_PR_OFFSET + 0x0080) -#define PCI_CR_BAR21MASK_REG (PCI_CR_PR_OFFSET + 0x0084) -#define PCI_CR_BAR22MASK_REG (PCI_CR_PR_OFFSET + 0x0088) -#define PCI_CR_BAR23MASK_REG (PCI_CR_PR_OFFSET + 0x008C) -#define PCI_CR_BAR24MASK_REG (PCI_CR_PR_OFFSET + 0x0090) -#define PCI_CR_BAR25MASK_REG (PCI_CR_PR_OFFSET + 0x0094) -#define PCI_CR_BAR26MASK_REG (PCI_CR_PR_OFFSET + 0x0098) -#define PCI_CR_CIS_PT2_REG (PCI_CR_PR_OFFSET + 0x009C) -#define PCI_CR_SUBSYS_ID2_REG (PCI_CR_PR_OFFSET + 0x00A0) -#define PCI_CR_PCI_ADDR_MAP21_REG (PCI_CR_PR_OFFSET + 0x00A4) -#define PCI_CR_PCI_ADDR_MAP22_REG (PCI_CR_PR_OFFSET + 0x00A8) -#define PCI_CR_PCI_ADDR_MAP23_REG (PCI_CR_PR_OFFSET + 0x00AC) - - -/***********************************************************************/ -/* Module : MCD register address and bits */ -/***********************************************************************/ -#define DANUBE_MCD (KSEG1+0x1F106000) - -/***Manufacturer Identification Register***/ -#define DANUBE_MCD_MANID ((volatile u32*)(DANUBE_MCD+ 0x0024)) -#define DANUBE_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) - -/***Chip Identification Register***/ -#define DANUBE_MCD_CHIPID ((volatile u32*)(DANUBE_MCD+ 0x0028)) -#define DANUBE_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define DANUBE_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -#define DANUBE_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define DANUBE_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define DANUBE_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) -#define DANUBE_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) - -#define DANUBE_CHIPID_STANDARD 0x00EB -#define DANUBE_CHIPID_YANGTSE 0x00ED - -/***Redesign Tracing Identification Register***/ -#define DANUBE_MCD_RTID ((volatile u32*)(DANUBE_MCD+ 0x002C)) -#define DANUBE_MCD_RTID_LC (1 << 15) -#define DANUBE_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ - -#define DANUBE_EBU (0xBE105300) -#define EBU_ADDR_SEL_0 (volatile u32*)(DANUBE_EBU + 0x20) -#define EBU_ADDR_SEL_1 (volatile u32*)(DANUBE_EBU + 0x24) -#define EBU_CON_0 (volatile u32*)(DANUBE_EBU + 0x60) -#define EBU_CON_1 (volatile u32*)(DANUBE_EBU + 0x64) -#define EBU_NAND_CON (volatile u32*)(DANUBE_EBU + 0xB0) -#define EBU_NAND_WAIT (volatile u32*)(DANUBE_EBU + 0xB4) -#define EBU_NAND_ECC0 (volatile u32*)(DANUBE_EBU + 0xB8) -#define EBU_NAND_ECC_AC (volatile u32*)(DANUBE_EBU + 0xBC) - -/***********************************************************************/ - - -/***EBU Clock Control Register***/ -#define DANUBE_EBU_CLC ((volatile u32*)(DANUBE_EBU+ 0x0000)) -#define DANUBE_EBU_CLC_DISS (1 << 1) -#define DANUBE_EBU_CLC_DISR (1 << 0) - -/***EBU Global Control Register***/ -#define DANUBE_EBU_CON ((volatile u32*)(DANUBE_EBU+ 0x0010)) -#define DANUBE_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) -#define DANUBE_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) -#define DANUBE_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) -#define DANUBE_EBU_CON_ARBSYNC (1 << 5) -#define DANUBE_EBU_CON_1 (1 << 3) - -/***EBU Address Select Register 0***/ -#define DANUBE_EBU_ADDSEL0 ((volatile u32*)(DANUBE_EBU+ 0x0020)) -#define DANUBE_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL0_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL0_REGEN (1 << 0) - -/***EBU Address Select Register 1***/ -#define DANUBE_EBU_ADDSEL1 ((volatile u32*)(DANUBE_EBU+ 0x0024)) -#define DANUBE_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL1_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL1_REGEN (1 << 0) - -/***EBU Address Select Register 2***/ -#define DANUBE_EBU_ADDSEL2 ((volatile u32*)(DANUBE_EBU+ 0x0028)) -#define DANUBE_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL2_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL2_REGEN (1 << 0) - -/***EBU Address Select Register 3***/ -#define DANUBE_EBU_ADDSEL3 ((volatile u32*)(DANUBE_EBU+ 0x0028)) -#define DANUBE_EBU_ADDSEL3_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL3_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL3_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL3_REGEN (1 << 0) - -/***EBU Bus Configuration Register 0***/ -#define DANUBE_EBU_BUSCON0 ((volatile u32*)(DANUBE_EBU+ 0x0060)) -#define DANUBE_EBU_BUSCON0_WRDIS (1 << 31) -#define DANUBE_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define DANUBE_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define DANUBE_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define DANUBE_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define DANUBE_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define DANUBE_EBU_BUSCON0_WAITINV (1 << 19) -#define DANUBE_EBU_BUSCON0_SETUP (1 << 18) -#define DANUBE_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define DANUBE_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define DANUBE_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define DANUBE_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 1***/ -#define DANUBE_EBU_BUSCON1 ((volatile u32*)(DANUBE_EBU+ 0x0064)) -#define DANUBE_EBU_BUSCON1_WRDIS (1 << 31) -#define DANUBE_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define DANUBE_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define DANUBE_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define DANUBE_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define DANUBE_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define DANUBE_EBU_BUSCON1_WAITINV (1 << 19) -#define DANUBE_EBU_BUSCON1_SETUP (1 << 18) -#define DANUBE_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define DANUBE_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define DANUBE_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define DANUBE_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ -#define DANUBE_EBU_BUSCON2 ((volatile u32*)(DANUBE_EBU+ 0x0068)) -#define DANUBE_EBU_BUSCON2_WRDIS (1 << 31) -#define DANUBE_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define DANUBE_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define DANUBE_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define DANUBE_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define DANUBE_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define DANUBE_EBU_BUSCON2_WAITINV (1 << 19) -#define DANUBE_EBU_BUSCON2_SETUP (1 << 18) -#define DANUBE_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define DANUBE_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define DANUBE_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define DANUBE_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : SDRAM register address and bits */ -/***********************************************************************/ - -#define DANUBE_SDRAM (0xBF800000) -/***********************************************************************/ - - -/***MC Access Error Cause Register***/ -#define DANUBE_SDRAM_MC_ERRCAUSE ((volatile u32*)(DANUBE_SDRAM+ 0x0100)) -#define DANUBE_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -#define DANUBE_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***MC Access Error Address Register***/ -#define DANUBE_SDRAM_MC_ERRADDR ((volatile u32*)(DANUBE_SDRAM+ 0x0108)) -#define DANUBE_SDRAM_MC_ERRADDR_ADDR - -/***MC I/O General Purpose Register***/ -#define DANUBE_SDRAM_MC_IOGP ((volatile u32*)(DANUBE_SDRAM+ 0x0800)) -#define DANUBE_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28) -#define DANUBE_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24) -#define DANUBE_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20) -#define DANUBE_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define DANUBE_SDRAM_MC_IOGP_CPS (1 << 11) -#define DANUBE_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8) -#define DANUBE_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***MC Self Refresh Register***/ -#define DANUBE_SDRAM_MC_SELFRFSH ((volatile u32*)(DANUBE_SDRAM+ 0x0A00)) -#define DANUBE_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -#define DANUBE_SDRAM_MC_SELFRFSH_PWD (1 << 0) -#define DANUBE_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2) - -/***MC Enable Register***/ -#define DANUBE_SDRAM_MC_CTRLENA ((volatile u32*)(DANUBE_SDRAM+ 0x1000)) -#define DANUBE_SDRAM_MC_CTRLENA_ENA (1 << 0) -#define DANUBE_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1) - -/***MC Mode Register Setup Code***/ -#define DANUBE_SDRAM_MC_MRSCODE ((volatile u32*)(DANUBE_SDRAM+ 0x1008)) -#define DANUBE_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7) -#define DANUBE_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_MRSCODE_WT (1 << 3) -#define DANUBE_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***MC Configuration Data-word Width Register***/ -#define DANUBE_SDRAM_MC_CFGDW ((volatile u32*)(DANUBE_SDRAM+ 0x1010)) -#define DANUBE_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4) - -/***MC Configuration Physical Bank 0 Register***/ -#define DANUBE_SDRAM_MC_CFGPB0 ((volatile u32*)(DANUBE_SDRAM+ 0x1018)) -#define DANUBE_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define DANUBE_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8) -#define DANUBE_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16) - -/***MC Latency Register***/ -#define DANUBE_SDRAM_MC_LATENCY ((volatile u32*)(DANUBE_SDRAM+ 0x1038)) -#define DANUBE_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12) -#define DANUBE_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8) -#define DANUBE_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20) - -/***MC Refresh Cycle Time Register***/ -#define DANUBE_SDRAM_MC_TREFRESH ((volatile u32*)(DANUBE_SDRAM+ 0x1040)) -#define DANUBE_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - - -/***********************************************************************/ -/* Module : GPTU register address and bits */ -/***********************************************************************/ - -#define DANUBE_GPTU (0xB8000300) -/***********************************************************************/ - - -/***GPT Clock Control Register***/ -#define DANUBE_GPTU_GPT_CLC ((volatile u32*)(DANUBE_GPTU+ 0x0000)) -#define DANUBE_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_GPTU_GPT_CLC_DISS (1 << 1) -#define DANUBE_GPTU_GPT_CLC_DISR (1 << 0) - -/***GPT Timer 3 Control Register***/ -#define DANUBE_GPTU_GPT_T3CON ((volatile u32*)(DANUBE_GPTU+ 0x0014)) -#define DANUBE_GPTU_GPT_T3CON_T3RDIR (1 << 15) -#define DANUBE_GPTU_GPT_T3CON_T3CHDIR (1 << 14) -#define DANUBE_GPTU_GPT_T3CON_T3EDGE (1 << 13) -#define DANUBE_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define DANUBE_GPTU_GPT_T3CON_T3OTL (1 << 10) -#define DANUBE_GPTU_GPT_T3CON_T3UD (1 << 7) -#define DANUBE_GPTU_GPT_T3CON_T3R (1 << 6) -#define DANUBE_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write Hardware Modified Timer 3 Control Register -If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT3CON ((volatile u32*)(DANUBE_GPTU+ 0x004C)) -#define DANUBE_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15) -#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14) -#define DANUBE_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13) -#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12) -#define DANUBE_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11) -#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10) - -/***GPT Timer 2 Control Register***/ -#define DANUBE_GPTU_GPT_T2CON ((volatile u32*)(DANUBE_GPTU+ 0x0010)) -#define DANUBE_GPTU_GPT_T2CON_TxRDIR (1 << 15) -#define DANUBE_GPTU_GPT_T2CON_TxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_T2CON_TxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_T2CON_TxIRDIS (1 << 12) -#define DANUBE_GPTU_GPT_T2CON_TxRC (1 << 9) -#define DANUBE_GPTU_GPT_T2CON_TxUD (1 << 7) -#define DANUBE_GPTU_GPT_T2CON_TxR (1 << 6) -#define DANUBE_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Timer 4 Control Register***/ -#define DANUBE_GPTU_GPT_T4CON ((volatile u32*)(DANUBE_GPTU+ 0x0018)) -#define DANUBE_GPTU_GPT_T4CON_TxRDIR (1 << 15) -#define DANUBE_GPTU_GPT_T4CON_TxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_T4CON_TxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_T4CON_TxIRDIS (1 << 12) -#define DANUBE_GPTU_GPT_T4CON_TxRC (1 << 9) -#define DANUBE_GPTU_GPT_T4CON_TxUD (1 << 7) -#define DANUBE_GPTU_GPT_T4CON_TxR (1 << 6) -#define DANUBE_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 2 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT2CON ((volatile u32*)(DANUBE_GPTU+ 0x0048)) -#define DANUBE_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15) -#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12) - -/***GPT Write HW Modified Timer 4 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT4CON ((volatile u32*)(DANUBE_GPTU+ 0x0050)) -#define DANUBE_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15) -#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12) - -/***GPT Capture Reload Register***/ -#define DANUBE_GPTU_GPT_CAPREL ((volatile u32*)(DANUBE_GPTU+ 0x0030)) -#define DANUBE_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 2 Register***/ -#define DANUBE_GPTU_GPT_T2 ((volatile u32*)(DANUBE_GPTU+ 0x0034)) -#define DANUBE_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 3 Register***/ -#define DANUBE_GPTU_GPT_T3 ((volatile u32*)(DANUBE_GPTU+ 0x0038)) -#define DANUBE_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 4 Register***/ -#define DANUBE_GPTU_GPT_T4 ((volatile u32*)(DANUBE_GPTU+ 0x003C)) -#define DANUBE_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 5 Register***/ -#define DANUBE_GPTU_GPT_T5 ((volatile u32*)(DANUBE_GPTU+ 0x0040)) -#define DANUBE_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Register***/ -#define DANUBE_GPTU_GPT_T6 ((volatile u32*)(DANUBE_GPTU+ 0x0044)) -#define DANUBE_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Control Register***/ -#define DANUBE_GPTU_GPT_T6CON ((volatile u32*)(DANUBE_GPTU+ 0x0020)) -#define DANUBE_GPTU_GPT_T6CON_T6SR (1 << 15) -#define DANUBE_GPTU_GPT_T6CON_T6CLR (1 << 14) -#define DANUBE_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define DANUBE_GPTU_GPT_T6CON_T6OTL (1 << 10) -#define DANUBE_GPTU_GPT_T6CON_T6UD (1 << 7) -#define DANUBE_GPTU_GPT_T6CON_T6R (1 << 6) -#define DANUBE_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 6 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT6CON ((volatile u32*)(DANUBE_GPTU+ 0x0054)) -#define DANUBE_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11) -#define DANUBE_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10) - -/***GPT Timer 5 Control Register***/ -#define DANUBE_GPTU_GPT_T5CON ((volatile u32*)(DANUBE_GPTU+ 0x001C)) -#define DANUBE_GPTU_GPT_T5CON_T5SC (1 << 15) -#define DANUBE_GPTU_GPT_T5CON_T5CLR (1 << 14) -#define DANUBE_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12) -#define DANUBE_GPTU_GPT_T5CON_T5CC (1 << 11) -#define DANUBE_GPTU_GPT_T5CON_CT3 (1 << 10) -#define DANUBE_GPTU_GPT_T5CON_T5RC (1 << 9) -#define DANUBE_GPTU_GPT_T5CON_T5UDE (1 << 8) -#define DANUBE_GPTU_GPT_T5CON_T5UD (1 << 7) -#define DANUBE_GPTU_GPT_T5CON_T5R (1 << 6) -#define DANUBE_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : IOM register address and bits */ -/***********************************************************************/ - -#define DANUBE_IOM (0xBF105000) -/***********************************************************************/ - - -/***Receive FIFO***/ -#define DANUBE_IOM_RFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000)) -#define DANUBE_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Transmit FIFO***/ -#define DANUBE_IOM_XFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000)) -#define DANUBE_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Interrupt Status Register HDLC***/ -#define DANUBE_IOM_ISTAH ((volatile u32*)(DANUBE_IOM+ 0x0080)) -#define DANUBE_IOM_ISTAH_RME (1 << 7) -#define DANUBE_IOM_ISTAH_RPF (1 << 6) -#define DANUBE_IOM_ISTAH_RFO (1 << 5) -#define DANUBE_IOM_ISTAH_XPR (1 << 4) -#define DANUBE_IOM_ISTAH_XMR (1 << 3) -#define DANUBE_IOM_ISTAH_XDU (1 << 2) - -/***Interrupt Mask Register HDLC***/ -#define DANUBE_IOM_MASKH ((volatile u32*)(DANUBE_IOM+ 0x0080)) -#define DANUBE_IOM_MASKH_RME (1 << 7) -#define DANUBE_IOM_MASKH_RPF (1 << 6) -#define DANUBE_IOM_MASKH_RFO (1 << 5) -#define DANUBE_IOM_MASKH_XPR (1 << 4) -#define DANUBE_IOM_MASKH_XMR (1 << 3) -#define DANUBE_IOM_MASKH_XDU (1 << 2) - -/***Status Register***/ -#define DANUBE_IOM_STAR ((volatile u32*)(DANUBE_IOM+ 0x0084)) -#define DANUBE_IOM_STAR_XDOV (1 << 7) -#define DANUBE_IOM_STAR_XFW (1 << 6) -#define DANUBE_IOM_STAR_RACI (1 << 3) -#define DANUBE_IOM_STAR_XACI (1 << 1) - -/***Command Register***/ -#define DANUBE_IOM_CMDR ((volatile u32*)(DANUBE_IOM+ 0x0084)) -#define DANUBE_IOM_CMDR_RMC (1 << 7) -#define DANUBE_IOM_CMDR_RRES (1 << 6) -#define DANUBE_IOM_CMDR_XTF (1 << 3) -#define DANUBE_IOM_CMDR_XME (1 << 1) -#define DANUBE_IOM_CMDR_XRES (1 << 0) - -/***Mode Register***/ -#define DANUBE_IOM_MODEH ((volatile u32*)(DANUBE_IOM+ 0x0088)) -#define DANUBE_IOM_MODEH_MDS2 (1 << 7) -#define DANUBE_IOM_MODEH_MDS1 (1 << 6) -#define DANUBE_IOM_MODEH_MDS0 (1 << 5) -#define DANUBE_IOM_MODEH_RAC (1 << 3) -#define DANUBE_IOM_MODEH_DIM2 (1 << 2) -#define DANUBE_IOM_MODEH_DIM1 (1 << 1) -#define DANUBE_IOM_MODEH_DIM0 (1 << 0) - -/***Extended Mode Register***/ -#define DANUBE_IOM_EXMR ((volatile u32*)(DANUBE_IOM+ 0x008C)) -#define DANUBE_IOM_EXMR_XFBS (1 << 7) -#define DANUBE_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5) -#define DANUBE_IOM_EXMR_SRA (1 << 4) -#define DANUBE_IOM_EXMR_XCRC (1 << 3) -#define DANUBE_IOM_EXMR_RCRC (1 << 2) -#define DANUBE_IOM_EXMR_ITF (1 << 0) - -/***SAPI1 Register***/ -#define DANUBE_IOM_SAP1 ((volatile u32*)(DANUBE_IOM+ 0x0094)) -#define DANUBE_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define DANUBE_IOM_SAP1_MHA (1 << 0) - -/***Receive Frame Byte Count Low***/ -#define DANUBE_IOM_RBCL ((volatile u32*)(DANUBE_IOM+ 0x0098)) -#define DANUBE_IOM_RBCL_RBC(value) (1 << value) - - -/***SAPI2 Register***/ -#define DANUBE_IOM_SAP2 ((volatile u32*)(DANUBE_IOM+ 0x0098)) -#define DANUBE_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define DANUBE_IOM_SAP2_MLA (1 << 0) - -/***Receive Frame Byte Count High***/ -#define DANUBE_IOM_RBCH ((volatile u32*)(DANUBE_IOM+ 0x009C)) -#define DANUBE_IOM_RBCH_OV (1 << 4) -#define DANUBE_IOM_RBCH_RBC11 (1 << 3) -#define DANUBE_IOM_RBCH_RBC10 (1 << 2) -#define DANUBE_IOM_RBCH_RBC9 (1 << 1) -#define DANUBE_IOM_RBCH_RBC8 (1 << 0) - -/***TEI1 Register 1***/ -#define DANUBE_IOM_TEI1 ((volatile u32*)(DANUBE_IOM+ 0x009C)) -#define DANUBE_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define DANUBE_IOM_TEI1_EA (1 << 0) - -/***Receive Status Register***/ -#define DANUBE_IOM_RSTA ((volatile u32*)(DANUBE_IOM+ 0x00A0)) -#define DANUBE_IOM_RSTA_VFR (1 << 7) -#define DANUBE_IOM_RSTA_RDO (1 << 6) -#define DANUBE_IOM_RSTA_CRC (1 << 5) -#define DANUBE_IOM_RSTA_RAB (1 << 4) -#define DANUBE_IOM_RSTA_SA1 (1 << 3) -#define DANUBE_IOM_RSTA_SA0 (1 << 2) -#define DANUBE_IOM_RSTA_TA (1 << 0) -#define DANUBE_IOM_RSTA_CR (1 << 1) - -/***TEI2 Register***/ -#define DANUBE_IOM_TEI2 ((volatile u32*)(DANUBE_IOM+ 0x00A0)) -#define DANUBE_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define DANUBE_IOM_TEI2_EA (1 << 0) - -/***Test Mode Register HDLC***/ -#define DANUBE_IOM_TMH ((volatile u32*)(DANUBE_IOM+ 0x00A4)) -#define DANUBE_IOM_TMH_TLP (1 << 0) - -/***Command/Indication Receive 0***/ -#define DANUBE_IOM_CIR0 ((volatile u32*)(DANUBE_IOM+ 0x00B8)) -#define DANUBE_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_IOM_CIR0_CIC0 (1 << 3) -#define DANUBE_IOM_CIR0_CIC1 (1 << 2) -#define DANUBE_IOM_CIR0_SG (1 << 1) -#define DANUBE_IOM_CIR0_BAS (1 << 0) - -/***Command/Indication Transmit 0***/ -#define DANUBE_IOM_CIX0 ((volatile u32*)(DANUBE_IOM+ 0x00B8)) -#define DANUBE_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_IOM_CIX0_TBA2 (1 << 3) -#define DANUBE_IOM_CIX0_TBA1 (1 << 2) -#define DANUBE_IOM_CIX0_TBA0 (1 << 1) -#define DANUBE_IOM_CIX0_BAC (1 << 0) - -/***Command/Indication Receive 1***/ -#define DANUBE_IOM_CIR1 ((volatile u32*)(DANUBE_IOM+ 0x00BC)) -#define DANUBE_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2) - -/***Command/Indication Transmit 1***/ -#define DANUBE_IOM_CIX1 ((volatile u32*)(DANUBE_IOM+ 0x00BC)) -#define DANUBE_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define DANUBE_IOM_CIX1_CICW (1 << 1) -#define DANUBE_IOM_CIX1_CI1E (1 << 0) - -/***Controller Data Access Reg. (CH10)***/ -#define DANUBE_IOM_CDA10 ((volatile u32*)(DANUBE_IOM+ 0x0100)) -#define DANUBE_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH11)***/ -#define DANUBE_IOM_CDA11 ((volatile u32*)(DANUBE_IOM+ 0x0104)) -#define DANUBE_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH20)***/ -#define DANUBE_IOM_CDA20 ((volatile u32*)(DANUBE_IOM+ 0x0108)) -#define DANUBE_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH21)***/ -#define DANUBE_IOM_CDA21 ((volatile u32*)(DANUBE_IOM+ 0x010C)) -#define DANUBE_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define DANUBE_IOM_CDA_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0110)) -#define DANUBE_IOM_CDA_TSDP10_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define DANUBE_IOM_CDA_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0114)) -#define DANUBE_IOM_CDA_TSDP11_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define DANUBE_IOM_CDA_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0118)) -#define DANUBE_IOM_CDA_TSDP20_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define DANUBE_IOM_CDA_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x011C)) -#define DANUBE_IOM_CDA_TSDP21_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define DANUBE_IOM_CO_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0120)) -#define DANUBE_IOM_CO_TSDP10_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define DANUBE_IOM_CO_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0124)) -#define DANUBE_IOM_CO_TSDP11_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define DANUBE_IOM_CO_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0128)) -#define DANUBE_IOM_CO_TSDP20_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define DANUBE_IOM_CO_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x012C)) -#define DANUBE_IOM_CO_TSDP21_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define DANUBE_IOM_CDA1_CR ((volatile u32*)(DANUBE_IOM+ 0x0138)) -#define DANUBE_IOM_CDA1_CR_EN_TBM (1 << 5) -#define DANUBE_IOM_CDA1_CR_EN_I1 (1 << 4) -#define DANUBE_IOM_CDA1_CR_EN_I0 (1 << 3) -#define DANUBE_IOM_CDA1_CR_EN_O1 (1 << 2) -#define DANUBE_IOM_CDA1_CR_EN_O0 (1 << 1) -#define DANUBE_IOM_CDA1_CR_SWAP (1 << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define DANUBE_IOM_CDA2_CR ((volatile u32*)(DANUBE_IOM+ 0x013C)) -#define DANUBE_IOM_CDA2_CR_EN_TBM (1 << 5) -#define DANUBE_IOM_CDA2_CR_EN_I1 (1 << 4) -#define DANUBE_IOM_CDA2_CR_EN_I0 (1 << 3) -#define DANUBE_IOM_CDA2_CR_EN_O1 (1 << 2) -#define DANUBE_IOM_CDA2_CR_EN_O0 (1 << 1) -#define DANUBE_IOM_CDA2_CR_SWAP (1 << 0) - -/***Control Register B-Channel Data***/ -#define DANUBE_IOM_BCHA_CR ((volatile u32*)(DANUBE_IOM+ 0x0144)) -#define DANUBE_IOM_BCHA_CR_EN_BC2 (1 << 4) -#define DANUBE_IOM_BCHA_CR_EN_BC1 (1 << 3) - -/***Control Register B-Channel Data***/ -#define DANUBE_IOM_BCHB_CR ((volatile u32*)(DANUBE_IOM+ 0x0148)) -#define DANUBE_IOM_BCHB_CR_EN_BC2 (1 << 4) -#define DANUBE_IOM_BCHB_CR_EN_BC1 (1 << 3) - -/***Control Reg. for HDLC and CI1 Data***/ -#define DANUBE_IOM_DCI_CR ((volatile u32*)(DANUBE_IOM+ 0x014C)) -#define DANUBE_IOM_DCI_CR_DPS_CI1 (1 << 7) -#define DANUBE_IOM_DCI_CR_EN_CI1 (1 << 6) -#define DANUBE_IOM_DCI_CR_EN_D (1 << 5) - -/***Control Reg. for HDLC and CI1 Data***/ -#define DANUBE_IOM_DCIC_CR ((volatile u32*)(DANUBE_IOM+ 0x014C)) -#define DANUBE_IOM_DCIC_CR_DPS_CI0 (1 << 7) -#define DANUBE_IOM_DCIC_CR_EN_CI0 (1 << 6) -#define DANUBE_IOM_DCIC_CR_DPS_D (1 << 5) - -/***Control Reg. Serial Data Strobe x***/ -#define DANUBE_IOM_SDS_CR ((volatile u32*)(DANUBE_IOM+ 0x0154)) -#define DANUBE_IOM_SDS_CR_ENS_TSS (1 << 7) -#define DANUBE_IOM_SDS_CR_ENS_TSS_1 (1 << 6) -#define DANUBE_IOM_SDS_CR_ENS_TSS_3 (1 << 5) -#define DANUBE_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Control Register IOM Data***/ -#define DANUBE_IOM_IOM_CR ((volatile u32*)(DANUBE_IOM+ 0x015C)) -#define DANUBE_IOM_IOM_CR_SPU (1 << 7) -#define DANUBE_IOM_IOM_CR_CI_CS (1 << 5) -#define DANUBE_IOM_IOM_CR_TIC_DIS (1 << 4) -#define DANUBE_IOM_IOM_CR_EN_BCL (1 << 3) -#define DANUBE_IOM_IOM_CR_CLKM (1 << 2) -#define DANUBE_IOM_IOM_CR_Res (1 << 1) -#define DANUBE_IOM_IOM_CR_DIS_IOM (1 << 0) - -/***Synchronous Transfer Interrupt***/ -#define DANUBE_IOM_STI ((volatile u32*)(DANUBE_IOM+ 0x0160)) -#define DANUBE_IOM_STI_STOV21 (1 << 7) -#define DANUBE_IOM_STI_STOV20 (1 << 6) -#define DANUBE_IOM_STI_STOV11 (1 << 5) -#define DANUBE_IOM_STI_STOV10 (1 << 4) -#define DANUBE_IOM_STI_STI21 (1 << 3) -#define DANUBE_IOM_STI_STI20 (1 << 2) -#define DANUBE_IOM_STI_STI11 (1 << 1) -#define DANUBE_IOM_STI_STI10 (1 << 0) - -/***Acknowledge Synchronous Transfer Interrupt***/ -#define DANUBE_IOM_ASTI ((volatile u32*)(DANUBE_IOM+ 0x0160)) -#define DANUBE_IOM_ASTI_ACK21 (1 << 3) -#define DANUBE_IOM_ASTI_ACK20 (1 << 2) -#define DANUBE_IOM_ASTI_ACK11 (1 << 1) -#define DANUBE_IOM_ASTI_ACK10 (1 << 0) - -/***Mask Synchronous Transfer Interrupt***/ -#define DANUBE_IOM_MSTI ((volatile u32*)(DANUBE_IOM+ 0x0164)) -#define DANUBE_IOM_MSTI_STOV21 (1 << 7) -#define DANUBE_IOM_MSTI_STOV20 (1 << 6) -#define DANUBE_IOM_MSTI_STOV11 (1 << 5) -#define DANUBE_IOM_MSTI_STOV10 (1 << 4) -#define DANUBE_IOM_MSTI_STI21 (1 << 3) -#define DANUBE_IOM_MSTI_STI20 (1 << 2) -#define DANUBE_IOM_MSTI_STI11 (1 << 1) -#define DANUBE_IOM_MSTI_STI10 (1 << 0) - -/***Configuration Register for Serial Data Strobes***/ -#define DANUBE_IOM_SDS_CONF ((volatile u32*)(DANUBE_IOM+ 0x0168)) -#define DANUBE_IOM_SDS_CONF_SDS_BCL (1 << 0) - -/***Monitoring CDA Bits***/ -#define DANUBE_IOM_MCDA ((volatile u32*)(DANUBE_IOM+ 0x016C)) -#define DANUBE_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6) -#define DANUBE_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : ASC0 register address and bits */ -/***********************************************************************/ -#define DANUBE_ASC0 (KSEG1+0x1E100400) -/***********************************************************************/ -#define DANUBE_ASC0_TBUF ((volatile u32*)(DANUBE_ASC0 + 0x0020)) -#define DANUBE_ASC0_RBUF ((volatile u32*)(DANUBE_ASC0 + 0x0024)) -#define DANUBE_ASC0_FSTAT ((volatile u32*)(DANUBE_ASC0 + 0x0048)) -#define DANUBE_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -#define DANUBE_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -#define DANUBE_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : ASC1 register address and bits */ -/***********************************************************************/ - -#define DANUBE_ASC1 (KSEG1+0x1E100C00) - /***********************************************************************/ - -#define DANUBE_ASC1_TBUF ((volatile u32*)(DANUBE_ASC1 + 0x0020)) -#define DANUBE_ASC1_RBUF ((volatile u32*)(DANUBE_ASC1 + 0x0024)) -#define DANUBE_ASC1_FSTAT ((volatile u32*)(DANUBE_ASC1 + 0x0048)) -#define DANUBE_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -#define DANUBE_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -#define DANUBE_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ - -#define DANUBE_DMA (0xBE104100) -/***********************************************************************/ - -#define DANUBE_DMA_BASE DANUBE_DMA -#define DANUBE_DMA_CLC (volatile u32*)DANUBE_DMA_BASE -#define DANUBE_DMA_ID (volatile u32*)(DANUBE_DMA_BASE+0x08) -#define DANUBE_DMA_CTRL (volatile u32*)(DANUBE_DMA_BASE+0x10) -#define DANUBE_DMA_CPOLL (volatile u32*)(DANUBE_DMA_BASE+0x14) -#define DANUBE_DMA_CS (volatile u32*)(DANUBE_DMA_BASE+0x18) -#define DANUBE_DMA_CCTRL (volatile u32*)(DANUBE_DMA_BASE+0x1C) -#define DANUBE_DMA_CDBA (volatile u32*)(DANUBE_DMA_BASE+0x20) -#define DANUBE_DMA_CDLEN (volatile u32*)(DANUBE_DMA_BASE+0x24) -#define DANUBE_DMA_CIS (volatile u32*)(DANUBE_DMA_BASE+0x28) -#define DANUBE_DMA_CIE (volatile u32*)(DANUBE_DMA_BASE+0x2C) - -#define DANUBE_DMA_PS (volatile u32*)(DANUBE_DMA_BASE+0x40) -#define DANUBE_DMA_PCTRL (volatile u32*)(DANUBE_DMA_BASE+0x44) - -#define DANUBE_DMA_IRNEN (volatile u32*)(DANUBE_DMA_BASE+0xf4) -#define DANUBE_DMA_IRNCR (volatile u32*)(DANUBE_DMA_BASE+0xf8) -#define DANUBE_DMA_IRNICR (volatile u32*)(DANUBE_DMA_BASE+0xfc) -/***********************************************************************/ -/* Module : Debug register address and bits */ -/***********************************************************************/ - -#define DANUBE_Debug (0xBF106000) -/***********************************************************************/ - - -/***MCD Break Bus Switch Register***/ -#define DANUBE_Debug_MCD_BBS ((volatile u32*)(DANUBE_Debug+ 0x0000)) -#define DANUBE_Debug_MCD_BBS_BTP1 (1 << 19) -#define DANUBE_Debug_MCD_BBS_BTP0 (1 << 18) -#define DANUBE_Debug_MCD_BBS_BSP1 (1 << 17) -#define DANUBE_Debug_MCD_BBS_BSP0 (1 << 16) -#define DANUBE_Debug_MCD_BBS_BT5EN (1 << 15) -#define DANUBE_Debug_MCD_BBS_BT4EN (1 << 14) -#define DANUBE_Debug_MCD_BBS_BT5 (1 << 13) -#define DANUBE_Debug_MCD_BBS_BT4 (1 << 12) -#define DANUBE_Debug_MCD_BBS_BS5EN (1 << 7) -#define DANUBE_Debug_MCD_BBS_BS4EN (1 << 6) -#define DANUBE_Debug_MCD_BBS_BS5 (1 << 5) -#define DANUBE_Debug_MCD_BBS_BS4 (1 << 4) - -/***MCD Multiplexer Control Register***/ -#define DANUBE_Debug_MCD_MCR ((volatile u32*)(DANUBE_Debug+ 0x0008)) -#define DANUBE_Debug_MCD_MCR_MUX5 (1 << 4) -#define DANUBE_Debug_MCD_MCR_MUX4 (1 << 3) -#define DANUBE_Debug_MCD_MCR_MUX1 (1 << 0) - - -/***********************************************************************/ -/* Module : SRAM register address and bits */ -/***********************************************************************/ - -#define DANUBE_SRAM (0xBF980000) -/***********************************************************************/ - - -/***SRAM Size Register***/ -#define DANUBE_SRAM_SRAM_SIZE ((volatile u32*)(DANUBE_SRAM+ 0x0800)) -#define DANUBE_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : BIU register address and bits */ -/***********************************************************************/ - -#define DANUBE_BIU (0xBFA80000) -/***********************************************************************/ - - -/***BIU Identification Register***/ -#define DANUBE_BIU_BIU_ID ((volatile u32*)(DANUBE_BIU+ 0x0000)) -#define DANUBE_BIU_BIU_ID_ARCH (1 << 16) -#define DANUBE_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***BIU Access Error Cause Register***/ -#define DANUBE_BIU_BIU_ERRCAUSE ((volatile u32*)(DANUBE_BIU+ 0x0100)) -#define DANUBE_BIU_BIU_ERRCAUSE_ERR (1 << 31) -#define DANUBE_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***BIU Access Error Address Register***/ -#define DANUBE_BIU_BIU_ERRADDR ((volatile u32*)(DANUBE_BIU+ 0x0108)) -#define DANUBE_BIU_BIU_ERRADDR_ADDR - - -/***********************************************************************/ -/* Module : ICU register address and bits */ -/***********************************************************************/ - -#define DANUBE_ICU (0xBF880200) -#define DANUBE_ICU (0xBF880200) -#define DANUBE_ICU_EXI (0xBF101000) -/***********************************************************************/ - - -/***IM0 Interrupt Status Register***/ -#define DANUBE_ICU_IM0_ISR ((volatile u32*)(DANUBE_ICU+ 0x0000)) -#define DANUBE_ICU_IM0_ISR_IR(value) (1 << (value)) - - -/***IM1 Interrupt Status Register***/ -#define DANUBE_ICU_IM1_ISR ((volatile u32*)(DANUBE_ICU+ 0x0020)) -#define DANUBE_ICU_IM1_ISR_IR(value) (1 << (value)) - - -/***IM2 Interrupt Status Register***/ -#define DANUBE_ICU_IM2_ISR ((volatile u32*)(DANUBE_ICU+ 0x0040)) -#define DANUBE_ICU_IM2_ISR_IR(value) (1 << (value)) - -/***IM3 Interrupt Status Register***/ -#define DANUBE_ICU_IM3_ISR ((volatile u32*)(DANUBE_ICU+ 0x0060)) -#define DANUBE_ICU_IM3_ISR_IR(value) (1 << (value)) - -/***IM4 Interrupt Status Register***/ -#define DANUBE_ICU_IM4_ISR ((volatile u32*)(DANUBE_ICU+ 0x0080)) -#define DANUBE_ICU_IM4_ISR_IR(value) (1 << (value)) - - -/***IM0 Interrupt Enable Register***/ -#define DANUBE_ICU_IM0_IER ((volatile u32*)(DANUBE_ICU+ 0x0008)) -#define DANUBE_ICU_IM0_IER_IR(value) (1 << (value)) - - -/***IM1 Interrupt Enable Register***/ -#define DANUBE_ICU_IM1_IER ((volatile u32*)(DANUBE_ICU+ 0x0028)) -#define DANUBE_ICU_IM1_IER_IR(value) (1 << (value)) - - -/***IM2 Interrupt Enable Register***/ -#define DANUBE_ICU_IM2_IER ((volatile u32*)(DANUBE_ICU+ 0x0048)) -#define DANUBE_ICU_IM2_IER_IR(value) (1 << (value)8 - -/***IM3 Interrupt Enable Register***/ -#define DANUBE_ICU_IM3_IER ((volatile u32*)(DANUBE_ICU+ 0x0068)) -#define DANUBE_ICU_IM3_IER_IR(value) (1 << (value)) - -/***IM4 Interrupt Enable Register***/ -#define DANUBE_ICU_IM4_IER ((volatile u32*)(DANUBE_ICU+ 0x0088)) -#define DANUBE_ICU_IM4_IER_IR(value) (1 << (value)) - - -/***IM0 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM0_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0010)) -#define DANUBE_ICU_IM0_IOSR_IR(value) (1 << (value)) - - -/***IM1 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM1_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0030)) -#define DANUBE_ICU_IM1_IOSR_IR(value) (1 << (value)) - - -/***IM2 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM2_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0050)) -#define DANUBE_ICU_IM2_IOSR_IR(value) (1 << (value)) - -/***IM3 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM3_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0070)) -#define DANUBE_ICU_IM3_IOSR_IR(value) (1 << (value)) - -/***IM4 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM4_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0090)) -#define DANUBE_ICU_IM4_IOSR_IR(value) (1 << (value)) - - -/***IM0 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM0_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0018)) -#define DANUBE_ICU_IM0_IRSR_IR(value) (1 << (value)) - - -/***IM1 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM1_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0038)) -#define DANUBE_ICU_IM1_IRSR_IR(value) (1 << (value)) - - -/***IM2 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM2_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0058)) -#define DANUBE_ICU_IM2_IRSR_IR(value) (1 << (value)) - -/***IM3 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM3_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0078)) -#define DANUBE_ICU_IM3_IRSR_IR(value) (1 << (value)) - -/***IM4 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM4_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0098)) -#define DANUBE_ICU_IM4_IRSR_IR(value) (1 << (value)) - -/***Interrupt Vector Value Register***/ -#define DANUBE_ICU_IM_VEC ((volatile u32*)(DANUBE_ICU+ 0x0060)) - -/***Interrupt Vector Value Mask***/ -#define DANUBE_ICU_IM0_VEC_MASK 0x0000001f -#define DANUBE_ICU_IM1_VEC_MASK 0x000003e0 -#define DANUBE_ICU_IM2_VEC_MASK 0x00007c00 -#define DANUBE_ICU_IM3_VEC_MASK 0x000f8000 -#define DANUBE_ICU_IM4_VEC_MASK 0x01f00000 - -/***DMA Interrupt Mask Value***/ -#define DANUBE_DMA_H_MASK 0x00000fff - -/***External Interrupt Control Register***/ -#define DANUBE_ICU_EXTINTCR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0000)) -#define DANUBE_ICU_IRNICR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0004)) -#define DANUBE_ICU_IRNCR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0008)) -#define DANUBE_ICU_IRNEN ((volatile u32*)(DANUBE_ICU_EXI+ 0x000c)) -#define DANUBE_ICU_NMI_CR ((volatile u32*)(DANUBE_ICU_EXI+ 0x00f0)) -#define DANUBE_ICU_NMI_SR ((volatile u32*)(DANUBE_ICU_EXI+ 0x00f4)) - -/***********************************************************************/ -/* Module : MPS register address and bits */ -/***********************************************************************/ - -#define DANUBE_MPS (KSEG1+0x1F107000) -/***********************************************************************/ - -#define DANUBE_MPS_CHIPID ((volatile u32*)(DANUBE_MPS + 0x0344)) -#define DANUBE_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define DANUBE_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -#define DANUBE_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define DANUBE_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define DANUBE_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -#define DANUBE_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) - - -/* voice channel 0 ... 3 interrupt enable register */ -#define DANUBE_MPS_VC0ENR ((volatile u32*)(DANUBE_MPS + 0x0000)) -#define DANUBE_MPS_VC1ENR ((volatile u32*)(DANUBE_MPS + 0x0004)) -#define DANUBE_MPS_VC2ENR ((volatile u32*)(DANUBE_MPS + 0x0008)) -#define DANUBE_MPS_VC3ENR ((volatile u32*)(DANUBE_MPS + 0x000C)) -/* voice channel 0 ... 3 interrupt status read register */ -#define DANUBE_MPS_RVC0SR ((volatile u32*)(DANUBE_MPS + 0x0010)) -#define DANUBE_MPS_RVC1SR ((volatile u32*)(DANUBE_MPS + 0x0014)) -#define DANUBE_MPS_RVC2SR ((volatile u32*)(DANUBE_MPS + 0x0018)) -#define DANUBE_MPS_RVC3SR ((volatile u32*)(DANUBE_MPS + 0x001C)) -/* voice channel 0 ... 3 interrupt status set register */ -#define DANUBE_MPS_SVC0SR ((volatile u32*)(DANUBE_MPS + 0x0020)) -#define DANUBE_MPS_SVC1SR ((volatile u32*)(DANUBE_MPS + 0x0024)) -#define DANUBE_MPS_SVC2SR ((volatile u32*)(DANUBE_MPS + 0x0028)) -#define DANUBE_MPS_SVC3SR ((volatile u32*)(DANUBE_MPS + 0x002C)) -/* voice channel 0 ... 3 interrupt status clear register */ -#define DANUBE_MPS_CVC0SR ((volatile u32*)(DANUBE_MPS + 0x0030)) -#define DANUBE_MPS_CVC1SR ((volatile u32*)(DANUBE_MPS + 0x0034)) -#define DANUBE_MPS_CVC2SR ((volatile u32*)(DANUBE_MPS + 0x0038)) -#define DANUBE_MPS_CVC3SR ((volatile u32*)(DANUBE_MPS + 0x003C)) -/* common status 0 and 1 read register */ -#define DANUBE_MPS_RAD0SR ((volatile u32*)(DANUBE_MPS + 0x0040)) -#define DANUBE_MPS_RAD1SR ((volatile u32*)(DANUBE_MPS + 0x0044)) -/* common status 0 and 1 set register */ -#define DANUBE_MPS_SAD0SR ((volatile u32*)(DANUBE_MPS + 0x0048)) -#define DANUBE_MPS_SAD1SR ((volatile u32*)(DANUBE_MPS + 0x004C)) -/* common status 0 and 1 clear register */ -#define DANUBE_MPS_CAD0SR ((volatile u32*)(DANUBE_MPS + 0x0050)) -#define DANUBE_MPS_CAD1SR ((volatile u32*)(DANUBE_MPS + 0x0054)) -/* common status 0 and 1 enable register */ -#define DANUBE_MPS_AD0ENR ((volatile u32*)(DANUBE_MPS + 0x0058)) -#define DANUBE_MPS_AD1ENR ((volatile u32*)(DANUBE_MPS + 0x005C)) -/* notification enable register */ -#define DANUBE_MPS_CPU0_NFER ((volatile u32*)(DANUBE_MPS + 0x0060)) -#define DANUBE_MPS_CPU1_NFER ((volatile u32*)(DANUBE_MPS + 0x0064)) -/* CPU to CPU interrup request register */ -#define DANUBE_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(DANUBE_MPS + 0x0070)) -#define DANUBE_MPS_CPU0_2_CPU1_IER ((volatile u32*)(DANUBE_MPS + 0x0074)) -/* Global interrupt request and request enable register */ -#define DANUBE_MPS_GIRR ((volatile u32*)(DANUBE_MPS + 0x0078)) -#define DANUBE_MPS_GIER ((volatile u32*)(DANUBE_MPS + 0x007C)) - - -#define DANUBE_MPS_CPU0_SMP0 ((volatile u32*)(DANUBE_MPS + 0x00100)) - -#define DANUBE_MPS_CPU1_SMP0 ((volatile u32*)(DANUBE_MPS + 0x00200)) - -/************************************************************************/ -/* Module : DEU register address and bits */ -/************************************************************************/ -#define DANUBE_DEU_BASE_ADDR (0xBE102000) -/* DEU Control Register */ -#define DANUBE_DEU_CLK ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0000)) -#define DANUBE_DEU_ID ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0008)) - -/* DEU control register */ -#define DANUBE_DEU_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0010)) -#define DANUBE_DEU_IHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0014)) -#define DANUBE_DEU_ILR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0018)) -#define DANUBE_DEU_K1HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x001C)) -#define DANUBE_DEU_K1LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0020)) -#define DANUBE_DEU_K3HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0024)) -#define DANUBE_DEU_K3LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0028)) -#define DANUBE_DEU_IVHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x002C)) -#define DANUBE_DEU_IVLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0030)) -#define DANUBE_DEU_OHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0040)) -#define DANUBE_DEU_OLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050)) - -/* AES DEU register */ -#define DANUBE_AES_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050)) -#define DANUBE_AES_ID3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0054)) -#define DANUBE_AES_ID2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0058)) -#define DANUBE_AES_ID1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x005C)) -#define DANUBE_AES_ID0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0060)) - -/* AES Key register */ -#define DANUBE_AES_K7R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0064)) -#define DANUBE_AES_K6R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0068)) -#define DANUBE_AES_K5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x006C)) -#define DANUBE_AES_K4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0070)) -#define DANUBE_AES_K3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0074)) -#define DANUBE_AES_K2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0078)) -#define DANUBE_AES_K1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x007C)) -#define DANUBE_AES_K0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0080)) - -/* AES vector register */ -#define DANUBE_AES_IV3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0084)) -#define DANUBE_AES_IV2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0088)) -#define DANUBE_AES_IV1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x008C)) -#define DANUBE_AES_IV0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0090)) -#define DANUBE_AES_0D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0094)) -#define DANUBE_AES_0D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0098)) -#define DANUBE_AES_OD1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x009C)) -#define DANUBE_AES_OD0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00A0)) - -/* hash control registe */ -#define DANUBE_HASH_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B0)) -#define DANUBE_HASH_MR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B4)) -#define DANUBE_HASH_D1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B8 )) -#define DANUBE_HASH_D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00BC )) -#define DANUBE_HASH_D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C0 )) -#define DANUBE_HASH_D4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C4)) -#define DANUBE_HASH_D5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C8)) - -#define DANUBE_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00EC)) - - - - -/************************************************************************/ -/* Module : PPE register address and bits */ -/************************************************************************/ -#define DANUBE_PPE_BASE_ADDR (KSEG1 + 0x1E180000) -#define DANUBE_PPE_PP32_DEBUG_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0000) << 2))) -#define DANUBE_PPE_PPM_INT_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0030) << 2))) -#define DANUBE_PPE_PP32_INTERNAL_RES_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0040) << 2))) -#define DANUBE_PPE_PPE_CLOCK_CONTROL_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0100) << 2))) -#define DANUBE_PPE_CDM_CODE_MEMORY_RAM0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x1000) << 2))) -#define DANUBE_PPE_CDM_CODE_MEMORY_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x2000) << 2))) -#define DANUBE_PPE_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x4000) << 2))) -#define DANUBE_PPE_PP32_DATA_MEMORY_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x5000) << 2))) -#define DANUBE_PPE_PPM_INT_UNIT_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6000) << 2))) -#define DANUBE_PPE_PPM_TIMER0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6100) << 2))) -#define DANUBE_PPE_PPM_TASK_IND_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6200) << 2))) -#define DANUBE_PPE_PPS_BRK_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6300) << 2))) -#define DANUBE_PPE_PPM_TIMER1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6400) << 2))) -#define DANUBE_PPE_SB_RAM0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8000) << 2))) -#define DANUBE_PPE_SB_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8400) << 2))) -#define DANUBE_PPE_SB_RAM2_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8C00) << 2))) -#define DANUBE_PPE_SB_RAM3_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x9600) << 2))) - -#define DANUBE_PPE_PP32_SLEEP DANUBE_PPE_REG_ADDR(0x0010) /* PP32 Power Saving Register */ -#define DANUBE_PPE_CDM_CFG DANUBE_PPE_REG_ADDR(0x0100) /* Code/Data Memory (CDM) Register */ - -/* Mailbox Registers */ -#define DANUBE_PPE_MBOX_IGU0_ISRS DANUBE_PPE_REG_ADDR(0x0200) -#define DANUBE_PPE_MBOX_IGU0_ISRC DANUBE_PPE_REG_ADDR(0x0201) -#define DANUBE_PPE_MBOX_IGU0_ISR DANUBE_PPE_REG_ADDR(0x0202) -#define DANUBE_PPE_MBOX_IGU0_IER DANUBE_PPE_REG_ADDR(0x0203) -#define DANUBE_PPE_MBOX_IGU1_ISRS0 DANUBE_PPE_REG_ADDR(0x0204) -#define DANUBE_PPE_MBOX_IGU1_ISRC0 DANUBE_PPE_REG_ADDR(0x0205) -#define DANUBE_PPE_MBOX_IGU1_ISR0 DANUBE_PPE_REG_ADDR(0x0206) -#define DANUBE_PPE_MBOX_IGU1_IER0 DANUBE_PPE_REG_ADDR(0x0207) -#define DANUBE_PPE_MBOX_IGU1_ISRS1 DANUBE_PPE_REG_ADDR(0x0208) -#define DANUBE_PPE_MBOX_IGU1_ISRC1 DANUBE_PPE_REG_ADDR(0x0209) -#define DANUBE_PPE_MBOX_IGU1_ISR1 DANUBE_PPE_REG_ADDR(0x020A) -#define DANUBE_PPE_MBOX_IGU1_IER1 DANUBE_PPE_REG_ADDR(0x020B) -#define DANUBE_PPE_MBOX_IGU1_ISRS2 DANUBE_PPE_REG_ADDR(0x020C) -#define DANUBE_PPE_MBOX_IGU1_ISRC2 DANUBE_PPE_REG_ADDR(0x020D) -#define DANUBE_PPE_MBOX_IGU1_ISR2 DANUBE_PPE_REG_ADDR(0x020E) -#define DANUBE_PPE_MBOX_IGU1_IER2 DANUBE_PPE_REG_ADDR(0x020F) -#define DANUBE_PPE_MBOX_IGU2_ISRS DANUBE_PPE_REG_ADDR(0x0210) -#define DANUBE_PPE_MBOX_IGU2_ISRC DANUBE_PPE_REG_ADDR(0x0211) -#define DANUBE_PPE_MBOX_IGU2_ISR DANUBE_PPE_REG_ADDR(0x0212) -#define DANUBE_PPE_MBOX_IGU2_IER DANUBE_PPE_REG_ADDR(0x0213) -#define DANUBE_PPE_MBOX_IGU3_ISRS DANUBE_PPE_REG_ADDR(0x0214) -#define DANUBE_PPE_MBOX_IGU3_ISRC DANUBE_PPE_REG_ADDR(0x0215) -#define DANUBE_PPE_MBOX_IGU3_ISR DANUBE_PPE_REG_ADDR(0x0216) -#define DANUBE_PPE_MBOX_IGU3_IER DANUBE_PPE_REG_ADDR(0x0217) -#define DANUBE_PPE_MBOX_IGU4_ISRS DANUBE_PPE_REG_ADDR(0x0218) -#define DANUBE_PPE_MBOX_IGU4_ISRC DANUBE_PPE_REG_ADDR(0x0219) -#define DANUBE_PPE_MBOX_IGU4_ISR DANUBE_PPE_REG_ADDR(0x021A) -#define DANUBE_PPE_MBOX_IGU4_IER DANUBE_PPE_REG_ADDR(0x021B) -/* - * Shared Buffer (SB) Registers - */ -#define DANUBE_PPE_SB_MST_PRI0 DANUBE_PPE_REG_ADDR(0x0300) -#define DANUBE_PPE_SB_MST_PRI1 DANUBE_PPE_REG_ADDR(0x0301) -#define DANUBE_PPE_SB_MST_PRI2 DANUBE_PPE_REG_ADDR(0x0302) -#define DANUBE_PPE_SB_MST_PRI3 DANUBE_PPE_REG_ADDR(0x0303) -#define DANUBE_PPE_SB_MST_PRI4 DANUBE_PPE_REG_ADDR(0x0304) -#define DANUBE_PPE_SB_MST_SEL DANUBE_PPE_REG_ADDR(0x0305) -/* - * RTHA Registers - */ -#define DANUBE_PPE_RFBI_CFG DANUBE_PPE_REG_ADDR(0x0400) -#define DANUBE_PPE_RBA_CFG0 DANUBE_PPE_REG_ADDR(0x0404) -#define DANUBE_PPE_RBA_CFG1 DANUBE_PPE_REG_ADDR(0x0405) -#define DANUBE_PPE_RCA_CFG0 DANUBE_PPE_REG_ADDR(0x0408) -#define DANUBE_PPE_RCA_CFG1 DANUBE_PPE_REG_ADDR(0x0409) -#define DANUBE_PPE_RDES_CFG0 DANUBE_PPE_REG_ADDR(0x040C) -#define DANUBE_PPE_RDES_CFG1 DANUBE_PPE_REG_ADDR(0x040D) -#define DANUBE_PPE_SFSM_STATE0 DANUBE_PPE_REG_ADDR(0x0410) -#define DANUBE_PPE_SFSM_STATE1 DANUBE_PPE_REG_ADDR(0x0411) -#define DANUBE_PPE_SFSM_DBA0 DANUBE_PPE_REG_ADDR(0x0412) -#define DANUBE_PPE_SFSM_DBA1 DANUBE_PPE_REG_ADDR(0x0413) -#define DANUBE_PPE_SFSM_CBA0 DANUBE_PPE_REG_ADDR(0x0414) -#define DANUBE_PPE_SFSM_CBA1 DANUBE_PPE_REG_ADDR(0x0415) -#define DANUBE_PPE_SFSM_CFG0 DANUBE_PPE_REG_ADDR(0x0416) -#define DANUBE_PPE_SFSM_CFG1 DANUBE_PPE_REG_ADDR(0x0417) -#define DANUBE_PPE_SFSM_PGCNT0 DANUBE_PPE_REG_ADDR(0x041C) -#define DANUBE_PPE_SFSM_PGCNT1 DANUBE_PPE_REG_ADDR(0x041D) -/* - * TTHA Registers - */ -#define DANUBE_PPE_FFSM_DBA0 DANUBE_PPE_REG_ADDR(0x0508) -#define DANUBE_PPE_FFSM_DBA1 DANUBE_PPE_REG_ADDR(0x0509) -#define DANUBE_PPE_FFSM_CFG0 DANUBE_PPE_REG_ADDR(0x050A) -#define DANUBE_PPE_FFSM_CFG1 DANUBE_PPE_REG_ADDR(0x050B) -#define DANUBE_PPE_FFSM_IDLE_HEAD_BC0 DANUBE_PPE_REG_ADDR(0x050E) -#define DANUBE_PPE_FFSM_IDLE_HEAD_BC1 DANUBE_PPE_REG_ADDR(0x050F) -#define DANUBE_PPE_FFSM_PGCNT0 DANUBE_PPE_REG_ADDR(0x0514) -#define DANUBE_PPE_FFSM_PGCNT1 DANUBE_PPE_REG_ADDR(0x0515) -/* - * ETOP MDIO Registers - */ -#define DANUBE_PPE_ETOP_MDIO_CFG DANUBE_PPE_REG_ADDR(0x0600) -#define DANUBE_PPE_ETOP_MDIO_ACC DANUBE_PPE_REG_ADDR(0x0601) -#define DANUBE_PPE_ETOP_CFG DANUBE_PPE_REG_ADDR(0x0602) -#define DANUBE_PPE_ETOP_IG_VLAN_COS DANUBE_PPE_REG_ADDR(0x0603) -#define DANUBE_PPE_ETOP_IG_DSCP_COS3 DANUBE_PPE_REG_ADDR(0x0604) -#define DANUBE_PPE_ETOP_IG_DSCP_COS2 DANUBE_PPE_REG_ADDR(0x0605) -#define DANUBE_PPE_ETOP_IG_DSCP_COS1 DANUBE_PPE_REG_ADDR(0x0606) -#define DANUBE_PPE_ETOP_IG_DSCP_COS0 DANUBE_PPE_REG_ADDR(0x0607) -#define DANUBE_PPE_ETOP_IG_PLEN_CTRL0 DANUBE_PPE_REG_ADDR(0x0608) -#define DANUBE_PPE_ETOP_IG_PLEN_CTRL1 DANUBE_PPE_REG_ADDR(0x0609) -#define DANUBE_PPE_ETOP_ISR DANUBE_PPE_REG_ADDR(0x060A) -#define DANUBE_PPE_ETOP_IER DANUBE_PPE_REG_ADDR(0x060B) -#define DANUBE_PPE_ETOP_VPID DANUBE_PPE_REG_ADDR(0x060C) -#define DANUBE_PPE_ENET_MAC_CFG DANUBE_PPE_REG_ADDR(0x0610) -#define DANUBE_PPE_ENETS_DBA DANUBE_PPE_REG_ADDR(0x0612) -#define DANUBE_PPE_ENETS_CBA DANUBE_PPE_REG_ADDR(0x0613) -#define DANUBE_PPE_ENETS_CFG DANUBE_PPE_REG_ADDR(0x0614) -#define DANUBE_PPE_ENETS_PGCNT DANUBE_PPE_REG_ADDR(0x0615) -#define DANUBE_PPE_ENETS_PGCNT_DSRC_PP32 (0x00020000) -#define DANUBE_PPE_ENETS_PGCNT_DVAL_SHIFT (9) -#define DANUBE_PPE_ENETS_PGCNT_DCMD (0x00000100) -#define DANUBE_PPE_ENETS_PKTCNT DANUBE_PPE_REG_ADDR(0x0616) -#define DANUBE_PPE_ENETS_PKTCNT_DSRC_PP32 (0x00000200) -#define DANUBE_PPE_ENETS_PKTCNT_DCMD (0x00000100) -#define DANUBE_PPE_ENETS_PKTCNT_UPKT (0x000000FF) -#define DANUBE_PPE_ENETS_BUF_CTRL DANUBE_PPE_REG_ADDR(0x0617) -#define DANUBE_PPE_ENETS_COS_CFG DANUBE_PPE_REG_ADDR(0x0618) -#define DANUBE_PPE_ENETS_IGDROP DANUBE_PPE_REG_ADDR(0x0619) -#define DANUBE_PPE_ENETF_DBA DANUBE_PPE_REG_ADDR(0x0630) -#define DANUBE_PPE_ENETF_CBA DANUBE_PPE_REG_ADDR(0x0631) -#define DANUBE_PPE_ENETF_CFG DANUBE_PPE_REG_ADDR(0x0632) -#define DANUBE_PPE_ENETF_PGCNT DANUBE_PPE_REG_ADDR(0x0633) -#define DANUBE_PPE_ENETF_PGCNT_ISRC_PP32 (0x00020000) -#define DANUBE_PPE_ENETF_PGCNT_IVAL_SHIFT (9) -#define DANUBE_PPE_ENETF_PGCNT_ICMD (0x00000100) -#define DANUBE_PPE_ENETF_PKTCNT DANUBE_PPE_REG_ADDR(0x0634) -#define DANUBE_PPE_ENETF_PKTCNT_ISRC_PP32 (0x00000200) -#define DANUBE_PPE_ENETF_PKTCNT_ICMD (0x00000100) -#define DANUBE_PPE_ENETF_PKTCNT_VPKT (0x000000FF) -#define DANUBE_PPE_ENETF_HFCTRL DANUBE_PPE_REG_ADDR(0x0635) -#define DANUBE_PPE_ENETF_TXCTRL DANUBE_PPE_REG_ADDR(0x0636) -#define DANUBE_PPE_ENETF_VLCOS0 DANUBE_PPE_REG_ADDR(0x0638) -#define DANUBE_PPE_ENETF_VLCOS1 DANUBE_PPE_REG_ADDR(0x0639) -#define DANUBE_PPE_ENETF_VLCOS2 DANUBE_PPE_REG_ADDR(0x063A) -#define DANUBE_PPE_ENETF_VLCOS3 DANUBE_PPE_REG_ADDR(0x063B) -#define DANUBE_PPE_ENETF_EGERR DANUBE_PPE_REG_ADDR(0x063C) -#define DANUBE_PPE_ENETF_EGDROP DANUBE_PPE_REG_ADDR(0x063D) -/* - * DPLUS Registers - */ -#define DANUBE_PPE_DPLUS_TXDB DANUBE_PPE_REG_ADDR(0x0700) -#define DANUBE_PPE_DPLUS_TXCB DANUBE_PPE_REG_ADDR(0x0701) -#define DANUBE_PPE_DPLUS_TXCFG DANUBE_PPE_REG_ADDR(0x0702) -#define DANUBE_PPE_DPLUS_TXPGCNT DANUBE_PPE_REG_ADDR(0x0703) -#define DANUBE_PPE_DPLUS_RXDB DANUBE_PPE_REG_ADDR(0x0710) -#define DANUBE_PPE_DPLUS_RXCB DANUBE_PPE_REG_ADDR(0x0711) -#define DANUBE_PPE_DPLUS_RXCFG DANUBE_PPE_REG_ADDR(0x0712) -#define DANUBE_PPE_DPLUS_RXPGCNT DANUBE_PPE_REG_ADDR(0x0713) -/* - * BMC Registers - */ -#define DANUBE_PPE_BMC_CMD3 DANUBE_PPE_REG_ADDR(0x0800) -#define DANUBE_PPE_BMC_CMD2 DANUBE_PPE_REG_ADDR(0x0801) -#define DANUBE_PPE_BMC_CMD1 DANUBE_PPE_REG_ADDR(0x0802) -#define DANUBE_PPE_BMC_CMD0 DANUBE_PPE_REG_ADDR(0x0803) -#define DANUBE_PPE_BMC_CFG0 DANUBE_PPE_REG_ADDR(0x0804) -#define DANUBE_PPE_BMC_CFG1 DANUBE_PPE_REG_ADDR(0x0805) -#define DANUBE_PPE_BMC_POLY0 DANUBE_PPE_REG_ADDR(0x0806) -#define DANUBE_PPE_BMC_POLY1 DANUBE_PPE_REG_ADDR(0x0807) -#define DANUBE_PPE_BMC_CRC0 DANUBE_PPE_REG_ADDR(0x0808) -#define DANUBE_PPE_BMC_CRC1 DANUBE_PPE_REG_ADDR(0x0809) -/* - * SLL Registers - */ -#define DANUBE_PPE_SLL_CMD1 DANUBE_PPE_REG_ADDR(0x0900) -#define DANUBE_PPE_SLL_CMD0 DANUBE_PPE_REG_ADDR(0x0901) -#define DANUBE_PPE_SLL_KEY0 DANUBE_PPE_REG_ADDR(0x0910) -#define DANUBE_PPE_SLL_KEY1 DANUBE_PPE_REG_ADDR(0x0911) -#define DANUBE_PPE_SLL_KEY2 DANUBE_PPE_REG_ADDR(0x0912) -#define DANUBE_PPE_SLL_KEY3 DANUBE_PPE_REG_ADDR(0x0913) -#define DANUBE_PPE_SLL_KEY4 DANUBE_PPE_REG_ADDR(0x0914) -#define DANUBE_PPE_SLL_KEY5 DANUBE_PPE_REG_ADDR(0x0915) -#define DANUBE_PPE_SLL_RESULT DANUBE_PPE_REG_ADDR(0x0920) -/* - * EMA Registers - */ -#define DANUBE_PPE_EMA_CMD2 DANUBE_PPE_REG_ADDR(0x0A00) -#define DANUBE_PPE_EMA_CMD1 DANUBE_PPE_REG_ADDR(0x0A01) -#define DANUBE_PPE_EMA_CMD0 DANUBE_PPE_REG_ADDR(0x0A02) -#define DANUBE_PPE_EMA_ISR DANUBE_PPE_REG_ADDR(0x0A04) -#define DANUBE_PPE_EMA_IER DANUBE_PPE_REG_ADDR(0x0A05) -#define DANUBE_PPE_EMA_CFG DANUBE_PPE_REG_ADDR(0x0A06) -/* - * UTPS Registers - */ -#define DANUBE_PPE_UTP_TXCA0 DANUBE_PPE_REG_ADDR(0x0B00) -#define DANUBE_PPE_UTP_TXNA0 DANUBE_PPE_REG_ADDR(0x0B01) -#define DANUBE_PPE_UTP_TXCA1 DANUBE_PPE_REG_ADDR(0x0B02) -#define DANUBE_PPE_UTP_TXNA1 DANUBE_PPE_REG_ADDR(0x0B03) -#define DANUBE_PPE_UTP_RXCA0 DANUBE_PPE_REG_ADDR(0x0B10) -#define DANUBE_PPE_UTP_RXNA0 DANUBE_PPE_REG_ADDR(0x0B11) -#define DANUBE_PPE_UTP_RXCA1 DANUBE_PPE_REG_ADDR(0x0B12) -#define DANUBE_PPE_UTP_RXNA1 DANUBE_PPE_REG_ADDR(0x0B13) -#define DANUBE_PPE_UTP_CFG DANUBE_PPE_REG_ADDR(0x0B20) -#define DANUBE_PPE_UTP_ISR DANUBE_PPE_REG_ADDR(0x0B30) -#define DANUBE_PPE_UTP_IER DANUBE_PPE_REG_ADDR(0x0B31) -/* - * QSB Registers - */ -#define DANUBE_PPE_QSB_RELOG DANUBE_PPE_REG_ADDR(0x0C00) -#define DANUBE_PPE_QSB_EMIT0 DANUBE_PPE_REG_ADDR(0x0C01) -#define DANUBE_PPE_QSB_EMIT1 DANUBE_PPE_REG_ADDR(0x0C02) -#define DANUBE_PPE_QSB_ICDV DANUBE_PPE_REG_ADDR(0x0C07) -#define DANUBE_PPE_QSB_SBL DANUBE_PPE_REG_ADDR(0x0C09) -#define DANUBE_PPE_QSB_CFG DANUBE_PPE_REG_ADDR(0x0C0A) -#define DANUBE_PPE_QSB_RTM DANUBE_PPE_REG_ADDR(0x0C0B) -#define DANUBE_PPE_QSB_RTD DANUBE_PPE_REG_ADDR(0x0C0C) -#define DANUBE_PPE_QSB_RAMAC DANUBE_PPE_REG_ADDR(0x0C0D) -#define DANUBE_PPE_QSB_ISTAT DANUBE_PPE_REG_ADDR(0x0C0E) -#define DANUBE_PPE_QSB_IMR DANUBE_PPE_REG_ADDR(0x0C0F) -#define DANUBE_PPE_QSB_SRC DANUBE_PPE_REG_ADDR(0x0C10) -/* - * DSP User Registers - */ -#define DANUBE_PPE_DREG_A_VERSION DANUBE_PPE_REG_ADDR(0x0D00) -#define DANUBE_PPE_DREG_A_CFG DANUBE_PPE_REG_ADDR(0x0D01) -#define DANUBE_PPE_DREG_AT_CTRL DANUBE_PPE_REG_ADDR(0x0D02) -#define DANUBE_PPE_DREG_AR_CTRL DANUBE_PPE_REG_ADDR(0x0D08) -#define DANUBE_PPE_DREG_A_UTPCFG DANUBE_PPE_REG_ADDR(0x0D0E) -#define DANUBE_PPE_DREG_A_STATUS DANUBE_PPE_REG_ADDR(0x0D0F) -#define DANUBE_PPE_DREG_AT_CFG0 DANUBE_PPE_REG_ADDR(0x0D20) -#define DANUBE_PPE_DREG_AT_CFG1 DANUBE_PPE_REG_ADDR(0x0D21) -#define DANUBE_PPE_DREG_FB_SIZE0 DANUBE_PPE_REG_ADDR(0x0D22) -#define DANUBE_PPE_DREG_FB_SIZE1 DANUBE_PPE_REG_ADDR(0x0D23) -#define DANUBE_PPE_DREG_AT_CELL0 DANUBE_PPE_REG_ADDR(0x0D24) -#define DANUBE_PPE_DREG_AT_CELL1 DANUBE_PPE_REG_ADDR(0x0D25) -#define DANUBE_PPE_DREG_AT_IDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D26) -#define DANUBE_PPE_DREG_AT_IDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D27) -#define DANUBE_PPE_DREG_AT_IDLE0 DANUBE_PPE_REG_ADDR(0x0D28) -#define DANUBE_PPE_DREG_AT_IDLE1 DANUBE_PPE_REG_ADDR(0x0D29) -#define DANUBE_PPE_DREG_AR_CFG0 DANUBE_PPE_REG_ADDR(0x0D60) -#define DANUBE_PPE_DREG_AR_CFG1 DANUBE_PPE_REG_ADDR(0x0D61) -#define DANUBE_PPE_DREG_AR_FB_START0 DANUBE_PPE_REG_ADDR(0x0D62) -#define DANUBE_PPE_DREG_AR_FB_START1 DANUBE_PPE_REG_ADDR(0x0D63) -#define DANUBE_PPE_DREG_AR_FB_END0 DANUBE_PPE_REG_ADDR(0x0D64) -#define DANUBE_PPE_DREG_AR_FB_END1 DANUBE_PPE_REG_ADDR(0x0D65) -#define DANUBE_PPE_DREG_AR_ATM_STAT0 DANUBE_PPE_REG_ADDR(0x0D66) -#define DANUBE_PPE_DREG_AR_ATM_STAT1 DANUBE_PPE_REG_ADDR(0x0D67) -#define DANUBE_PPE_DREG_AR_CELL0 DANUBE_PPE_REG_ADDR(0x0D68) -#define DANUBE_PPE_DREG_AR_CELL1 DANUBE_PPE_REG_ADDR(0x0D69) -#define DANUBE_PPE_DREG_AR_IDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6A) -#define DANUBE_PPE_DREG_AR_IDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6B) -#define DANUBE_PPE_DREG_AR_AIIDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6C) -#define DANUBE_PPE_DREG_AR_AIIDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6D) -#define DANUBE_PPE_DREG_AR_BE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6E) -#define DANUBE_PPE_DREG_AR_BE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6F) -#define DANUBE_PPE_DREG_AR_HEC_CNT0 DANUBE_PPE_REG_ADDR(0x0D70) -#define DANUBE_PPE_DREG_AR_HEC_CNT1 DANUBE_PPE_REG_ADDR(0x0D71) -#define DANUBE_PPE_DREG_AR_CD_CNT0 DANUBE_PPE_REG_ADDR(0x0D72) -#define DANUBE_PPE_DREG_AR_CD_CNT1 DANUBE_PPE_REG_ADDR(0x0D73) -#define DANUBE_PPE_DREG_AR_IDLE0 DANUBE_PPE_REG_ADDR(0x0D74) -#define DANUBE_PPE_DREG_AR_IDLE1 DANUBE_PPE_REG_ADDR(0x0D75) -#define DANUBE_PPE_DREG_AR_DELIN0 DANUBE_PPE_REG_ADDR(0x0D76) -#define DANUBE_PPE_DREG_AR_DELIN1 DANUBE_PPE_REG_ADDR(0x0D77) -#define DANUBE_PPE_DREG_RESV0 DANUBE_PPE_REG_ADDR(0x0D78) -#define DANUBE_PPE_DREG_RESV1 DANUBE_PPE_REG_ADDR(0x0D79) -#define DANUBE_PPE_DREG_RX_MIB_CMD0 DANUBE_PPE_REG_ADDR(0x0D80) -#define DANUBE_PPE_DREG_RX_MIB_CMD1 DANUBE_PPE_REG_ADDR(0x0D81) -#define DANUBE_PPE_DREG_AR_OVDROP_CNT0 DANUBE_PPE_REG_ADDR(0x0D98) -#define DANUBE_PPE_DREG_AR_OVDROP_CNT1 DANUBE_PPE_REG_ADDR(0x0D99) - - -/************************************************************************/ -/* Module : PPE register address and bits */ -/************************************************************************/ -#define DANUBE_PPE32_BASE 0xBE180000 -#define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4)) -#define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4)) -#define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4)) -#define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4)) -#define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4)) -#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4)) - -/************************************************************************/ -/* Module : PPE register address and bits */ -/************************************************************************/ -#define DANUBE_PPE32_BASE 0xBE180000 -#define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4)) -#define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4)) -#define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4)) -#define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4)) -#define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4)) -#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4)) - -/* - * ETOP MDIO Registers - */ -#define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -#define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -#define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -#define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -#define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -#define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -#define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -#define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -#define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -#define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -#define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -#define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) -#define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -#define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) -#define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) -#define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) -#define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) -#define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) -#define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) -#define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) -#define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -#define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) -#define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) -#define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) - -#define ENETF_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) -#define ENETF_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) -#define ENETF_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) -#define ENETF_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) -#define ENETF_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) -#define ENETF_HFCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) -#define ENETF_TXCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) - -#define ENETF_VLCOS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) -#define ENETF_VLCOS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) -#define ENETF_VLCOS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) -#define ENETF_VLCOS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) -#define ENETF_EGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) -#define ENETF_EGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) - - -/* - * ETOP MDIO Registers - */ -#define DANUBE_PPE32_ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -#define DANUBE_PPE32_ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -#define DANUBE_PPE32_ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -#define DANUBE_PPE32_ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -#define DANUBE_PPE32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -#define DANUBE_PPE32_ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -#define DANUBE_PPE32_ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -#define DANUBE_PPE32_ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) - - -/* ENET Register */ -#define DANUBE_PPE32_ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -#define DANUBE_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -#define DANUBE_PPE32_ENET_CoS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) - -/*********LED register definition****************/ - -#define DANUBE_LED 0xBE100BB0 -#define DANUBE_LED_CON0 ((volatile u32*)(DANUBE_LED + 0x0000)) -#define DANUBE_LED_CON1 ((volatile u32*)(DANUBE_LED + 0x0004)) -#define DANUBE_LED_CPU0 ((volatile u32*)(DANUBE_LED + 0x0008)) -#define DANUBE_LED_CPU1 ((volatile u32*)(DANUBE_LED + 0x000C)) -#define DANUBE_LED_AR ((volatile u32*)(DANUBE_LED + 0x0010)) - - - - -/***********************************************************************/ -#define DANUBE_REG32(addr) *((volatile u32 *)(addr)) -/***********************************************************************/ -#endif //DANUBE_H diff --git a/package/uboot-ifxmips/files/include/asm-mips/ifx_asc.h b/package/uboot-ifxmips/files/include/asm-mips/ifx_asc.h deleted file mode 100644 index 51abc950e1..0000000000 --- a/package/uboot-ifxmips/files/include/asm-mips/ifx_asc.h +++ /dev/null @@ -1,220 +0,0 @@ -/***************************************************************************** - * DANUBE BootROM - * Copyright (c) 2005, Infineon Technologies AG, All rights reserved - * IFAP DC COM SD - *****************************************************************************/ -#ifndef __ASC_H -#define __ASC_H - -#define DANUBEASC_TXFIFO_FL 1 -#define DANUBEASC_RXFIFO_FL 1 -#define DANUBEASC_TXFIFO_FULL 16 - -/* channel operating modes */ -#define ASCOPT_CSIZE 0x00000003 -#define ASCOPT_CS7 0x00000001 -#define ASCOPT_CS8 0x00000002 -#define ASCOPT_PARENB 0x00000004 -#define ASCOPT_STOPB 0x00000008 -#define ASCOPT_PARODD 0x00000010 -#define ASCOPT_CREAD 0x00000020 - -#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) - -/* ASC input select (0 or 1) */ -#define CONSOLE_TTY 0 - -#define DANUBEASC_TXFIFO_FL 1 -#define DANUBEASC_RXFIFO_FL 1 -#define DANUBEASC_TXFIFO_FULL 16 - -/* interrupt lines masks for the ASC device interrupts*/ -/* change these macroses if it's necessary */ -#define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */ - -#define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */ -#define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */ -#define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */ -#define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */ -#define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */ -#define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */ -#define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */ - -/* interrupt controller access macros */ -#define ASC_INTERRUPTS_ENABLE(X) \ -*((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X; -#define ASC_INTERRUPTS_DISABLE(X) \ -*((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X; -#define ASC_INTERRUPTS_CLEAR(X) \ -*((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X; - -/* CLC register's bits and bitfields */ -#define ASCCLC_DISR 0x00000001 -#define ASCCLC_DISS 0x00000002 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 - -/* CON register's bits and bitfields */ -#define ASCCON_MODEMASK 0x0000000f -#define ASCCON_M_8ASYNC 0x0 -#define ASCCON_M_8IRDA 0x1 -#define ASCCON_M_7ASYNC 0x2 -#define ASCCON_M_7IRDA 0x3 -#define ASCCON_WLSMASK 0x0000000c -#define ASCCON_WLSOFFSET 2 -#define ASCCON_WLS_8BIT 0x0 -#define ASCCON_WLS_7BIT 0x1 -#define ASCCON_PEN 0x00000010 -#define ASCCON_ODD 0x00000020 -#define ASCCON_SP 0x00000040 -#define ASCCON_STP 0x00000080 -#define ASCCON_BRS 0x00000100 -#define ASCCON_FDE 0x00000200 -#define ASCCON_ERRCLK 0x00000400 -#define ASCCON_EMMASK 0x00001800 -#define ASCCON_EMOFFSET 11 -#define ASCCON_EM_ECHO_OFF 0x0 -#define ASCCON_EM_ECHO_AB 0x1 -#define ASCCON_EM_ECHO_ON 0x2 -#define ASCCON_LB 0x00002000 -#define ASCCON_ACO 0x00004000 -#define ASCCON_R 0x00008000 -#define ASCCON_PAL 0x00010000 -#define ASCCON_FEN 0x00020000 -#define ASCCON_RUEN 0x00040000 -#define ASCCON_ROEN 0x00080000 -#define ASCCON_TOEN 0x00100000 -#define ASCCON_BEN 0x00200000 -#define ASCCON_TXINV 0x01000000 -#define ASCCON_RXINV 0x02000000 -#define ASCCON_TXMSB 0x04000000 -#define ASCCON_RXMSB 0x08000000 - -/* STATE register's bits and bitfields */ -#define ASCSTATE_REN 0x00000001 -#define ASCSTATE_PE 0x00010000 -#define ASCSTATE_FE 0x00020000 -#define ASCSTATE_RUE 0x00040000 -#define ASCSTATE_ROE 0x00080000 -#define ASCSTATE_TOE 0x00100000 -#define ASCSTATE_BE 0x00200000 -#define ASCSTATE_TXBVMASK 0x07000000 -#define ASCSTATE_TXBVOFFSET 24 -#define ASCSTATE_TXEOM 0x08000000 -#define ASCSTATE_RXBVMASK 0x70000000 -#define ASCSTATE_RXBVOFFSET 28 -#define ASCSTATE_RXEOM 0x80000000 - -/* WHBSTATE register's bits and bitfields */ -#define ASCWHBSTATE_CLRREN 0x00000001 -#define ASCWHBSTATE_SETREN 0x00000002 -#define ASCWHBSTATE_CLRPE 0x00000004 -#define ASCWHBSTATE_CLRFE 0x00000008 -#define ASCWHBSTATE_CLRRUE 0x00000010 -#define ASCWHBSTATE_CLRROE 0x00000020 -#define ASCWHBSTATE_CLRTOE 0x00000040 -#define ASCWHBSTATE_CLRBE 0x00000080 -#define ASCWHBSTATE_SETPE 0x00000100 -#define ASCWHBSTATE_SETFE 0x00000200 -#define ASCWHBSTATE_SETRUE 0x00000400 -#define ASCWHBSTATE_SETROE 0x00000800 -#define ASCWHBSTATE_SETTOE 0x00001000 -#define ASCWHBSTATE_SETBE 0x00002000 - -/* ABCON register's bits and bitfields */ -#define ASCABCON_ABEN 0x0001 -#define ASCABCON_AUREN 0x0002 -#define ASCABCON_ABSTEN 0x0004 -#define ASCABCON_ABDETEN 0x0008 -#define ASCABCON_FCDETEN 0x0010 - -/* FDV register mask, offset and bitfields*/ -#define ASCFDV_VALUE_MASK 0x000001FF - -/* WHBABCON register's bits and bitfields */ -#define ASCWHBABCON_CLRABEN 0x0001 -#define ASCWHBABCON_SETABEN 0x0002 - -/* ABSTAT register's bits and bitfields */ -#define ASCABSTAT_FCSDET 0x0001 -#define ASCABSTAT_FCCDET 0x0002 -#define ASCABSTAT_SCSDET 0x0004 -#define ASCABSTAT_SCCDET 0x0008 -#define ASCABSTAT_DETWAIT 0x0010 - -/* WHBABSTAT register's bits and bitfields */ -#define ASCWHBABSTAT_CLRFCSDET 0x0001 -#define ASCWHBABSTAT_SETFCSDET 0x0002 -#define ASCWHBABSTAT_CLRFCCDET 0x0004 -#define ASCWHBABSTAT_SETFCCDET 0x0008 -#define ASCWHBABSTAT_CLRSCSDET 0x0010 -#define ASCWHBABSTAT_SETSCSDET 0x0020 -#define ASCWHBABSTAT_CLRSCCDET 0x0040 -#define ASCWHBABSTAT_SETSCCDET 0x0080 -#define ASCWHBABSTAT_CLRDETWAIT 0x0100 -#define ASCWHBABSTAT_SETDETWAIT 0x0200 - -/* TXFCON register's bits and bitfields */ -#define ASCTXFCON_TXFIFO1 0x00000400 -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 - -/* RXFCON register's bits and bitfields */ -#define ASCRXFCON_RXFIFO1 0x00000400 -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 - -/* FSTAT register's bits and bitfields */ -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - -typedef struct /* DanubeAsc_t */ -{ - volatile unsigned long asc_clc; /*0x0000*/ - volatile unsigned long asc_pisel; /*0x0004*/ - volatile unsigned long asc_id; /*0x0008*/ - volatile unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/ - volatile unsigned long asc_con; /*0x0010*/ - volatile unsigned long asc_state; /*0x0014*/ - volatile unsigned long asc_whbstate; /*0x0018*/ - volatile unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/ - volatile unsigned long asc_tbuf; /*0x0020*/ - volatile unsigned long asc_rbuf; /*0x0024*/ - volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/ - volatile unsigned long asc_abcon; /*0x0030*/ - volatile unsigned long asc_abstat; /* not used */ /*0x0034*/ - volatile unsigned long asc_whbabcon; /*0x0038*/ - volatile unsigned long asc_whbabstat; /* not used */ /*0x003C*/ - volatile unsigned long asc_rxfcon; /*0x0040*/ - volatile unsigned long asc_txfcon; /*0x0044*/ - volatile unsigned long asc_fstat; /*0x0048*/ - volatile unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/ - volatile unsigned long asc_bg; /*0x0050*/ - volatile unsigned long asc_bg_timer; /*0x0054*/ - volatile unsigned long asc_fdv; /*0x0058*/ - volatile unsigned long asc_pmw; /*0x005C*/ - volatile unsigned long asc_modcon; /*0x0060*/ - volatile unsigned long asc_modstat; /*0x0064*/ - volatile unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/ - volatile unsigned long asc_sfcc; /*0x0070*/ - volatile unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/ - volatile unsigned long asc_eomcon; /*0x0080*/ - volatile unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/ - volatile unsigned long asc_dmacon; /*0x00EC*/ - volatile unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/ - volatile unsigned long asc_irnen; /*0x00F4*/ - volatile unsigned long asc_irnicr; /*0x00F8*/ - volatile unsigned long asc_irncr; /*0x00FC*/ -} DanubeAsc_t; - -int asc_init (void); -void asc_puts (const char *s); -void asc_putc (const char c); -int asc_getc (void); - -#endif /* __ASC_H */ diff --git a/package/uboot-ifxmips/files/include/asm-mips/inca-ip2.h b/package/uboot-ifxmips/files/include/asm-mips/inca-ip2.h deleted file mode 100644 index 19c8ceb5cb..0000000000 --- a/package/uboot-ifxmips/files/include/asm-mips/inca-ip2.h +++ /dev/null @@ -1,634 +0,0 @@ -/************************************************************************ - * - * Copyright (c) 2005 - * Infineon Technologies AG - * St. Martin Strasse 53; 81669 Muenchen; Germany - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - ************************************************************************/ - -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_DMA (KSEG1+0x14101000) -/***********************************************************************/ -#define CONFIGURATION_REGISTERS_CLC (INCA_IP2_DMA + 0x00) -#define CONFIGURATION_REGISTERS_ID (INCA_IP2_DMA + 0x08) -#define GENERAL_REGISTERS_DMA_CTRL (INCA_IP2_DMA + 0x10) -#define CHANNEL_RELATED_REGISTERS_DMA_CS (INCA_IP2_DMA + 0x18) -#define CHANNEL_RELATED_REGISTERS_DMA_CCTRL (INCA_IP2_DMA + 0x1C) -#define CHANNEL_RELATED_REGISTERS_DMA_CDBA (INCA_IP2_DMA + 0x20) -#define CHANNEL_RELATED_REGISTERS_DMA_CDLEN (INCA_IP2_DMA + 0x24) -#define CHANNEL_RELATED_REGISTERS_DMA_CIE (INCA_IP2_DMA + 0x2C) -#define CHANNEL_RELATED_REGISTERS_DMA_CIS (INCA_IP2_DMA + 0x28) -#define CHANNEL_RELATED_REGISTERS_DMA_CPOLL (INCA_IP2_DMA + 0x14) - -#define PORT_RELATED_REGISTERS_DMA_PS (INCA_IP2_DMA + 0x40) -#define PORT_RELATED_REGISTERS_DMA_PCTRL (INCA_IP2_DMA + 0x44) - -#define INTERRUPT_NODE_REGISTERS_DMA_IRNEN (INCA_IP2_DMA + 0xF4) -#define INTERRUPT_NODE_REGISTERS_DMA_IRNCR (INCA_IP2_DMA + 0xF8) -#define INTERRUPT_NODE_REGISTERS_DMA_IRNICR (INCA_IP2_DMA + 0xFC) - -#if 0 -/* ISR */ -#define DMA_ISR_RDERR 0x20 -#define DMA_ISR_CMDCPT 0x10 -#define DMA_ISR_CPT 0x8 -#define DMA_ISR_DURR 0x4 -#define DMA_ISR_EOP 0x2 -#endif -#define DMA_RESET_CHANNEL 0x00000002 -#define DMA_ENABLE_CHANNEL 0x00000001 -#define DMA_DESC_BYTEOFF_SHIFT 22 - -#define DMA_POLLING_ENABLE 0x80000000 -#define DMA_POLLING_CNT 0x50 /*minimum 0x10, max 0xfff0*/ - -/***********************************************************************/ -/* Module : ICU register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_ICU (KSEG1+0x1F880200) -/***********************************************************************/ - -#define INCA_IP2_ICU_IM0_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0000)) -#define INCA_IP2_ICU_IM0_IER ((volatile u32*)(INCA_IP2_ICU + 0x0008)) -#define INCA_IP2_ICU_IM0_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0010)) -#define INCA_IP2_ICU_IM0_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0018)) -#define INCA_IP2_ICU_IM0_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0020)) -#define INCA_IP2_ICU_IM0_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM0_IR(value) (1 << (value)) - -#define INCA_IP2_ICU_IM1_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0028)) -#define INCA_IP2_ICU_IM1_IER ((volatile u32*)(INCA_IP2_ICU + 0x0030)) -#define INCA_IP2_ICU_IM1_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0038)) -#define INCA_IP2_ICU_IM1_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0040)) -#define INCA_IP2_ICU_IM1_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0048)) -#define INCA_IP2_ICU_IM1_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM1_IR(value) (1 << (value)) - -#define INCA_IP2_ICU_IM2_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0050)) -#define INCA_IP2_ICU_IM2_IER ((volatile u32*)(INCA_IP2_ICU + 0x0058)) -#define INCA_IP2_ICU_IM2_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0060)) -#define INCA_IP2_ICU_IM2_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0068)) -#define INCA_IP2_ICU_IM2_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0070)) -#define INCA_IP2_ICU_IM2_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM2_IR(value) (1 << (value)) - -#define INCA_IP2_ICU_IM3_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0078)) -#define INCA_IP2_ICU_IM3_IER ((volatile u32*)(INCA_IP2_ICU + 0x0080)) -#define INCA_IP2_ICU_IM3_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0088)) -#define INCA_IP2_ICU_IM3_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0090)) -#define INCA_IP2_ICU_IM3_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0098)) -#define INCA_IP2_ICU_IM3_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM3_IR(value) (1 << (value)) - -#define INCA_IP2_ICU_IM4_ISR ((volatile u32*)(INCA_IP2_ICU + 0x00A0)) -#define INCA_IP2_ICU_IM4_IER ((volatile u32*)(INCA_IP2_ICU + 0x00A8)) -#define INCA_IP2_ICU_IM4_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x00B0)) -#define INCA_IP2_ICU_IM4_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x00B8)) -#define INCA_IP2_ICU_IM4_IMR ((volatile u32*)(INCA_IP2_ICU + 0x00C0)) -#define INCA_IP2_ICU_IM4_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM4_IR(value) (1 << (value)) - -#define INCA_IP2_ICU_IM5_ISR ((volatile u32*)(INCA_IP2_ICU + 0x00C8)) -#define INCA_IP2_ICU_IM5_IER ((volatile u32*)(INCA_IP2_ICU + 0x00D0)) -#define INCA_IP2_ICU_IM5_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x00D8)) -#define INCA_IP2_ICU_IM5_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x00E0)) -#define INCA_IP2_ICU_IM5_IMR ((volatile u32*)(INCA_IP2_ICU + 0x00E8)) -#define INCA_IP2_ICU_IM5_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM5_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM5_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM5_IR(value) (1 << (value)) - - -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_CGU (KSEG1+0x1F100800) -/***********************************************************************/ - -#define INCA_IP2_CGU_PLL2CR ((volatile u32*)(INCA_IP2_CGU + 0x0008)) -#define INCA_IP2_CGU_FBSCR ((volatile u32*)(INCA_IP2_CGU + 0x0018)) -#define INCA_IP2_CGU_FBSCR_LPBSDIV_GET(value) (((value) >> 6) & ((1 << 2) - 1)) -#define INCA_IP2_CGU_FBSCR_DIV0_GET(value) (((value) >> 0) & ((1 << 3) - 1)) -#define INCA_IP2_CGU_FBSCR_DIV1_GET(value) (((value) >> 4) & ((1 << 2) - 1)) - -/***********************************************************************/ -/* Module : MPS register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_MPS (KSEG1+0x1F101400) -/***********************************************************************/ - -#define INCA_IP2_MPS_CHIPID ((volatile u32*)(INCA_IP2_MPS + 0x0344)) -#define INCA_IP2_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define INCA_IP2_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -#define INCA_IP2_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define INCA_IP2_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define INCA_IP2_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -#define INCA_IP2_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) - - -/* voice channel 0 ... 3 interrupt enable register */ -#define INCA_IP2_MPS_VC0ENR ((volatile u32*)(INCA_IP2_MPS + 0x0000)) -#define INCA_IP2_MPS_VC1ENR ((volatile u32*)(INCA_IP2_MPS + 0x0004)) -#define INCA_IP2_MPS_VC2ENR ((volatile u32*)(INCA_IP2_MPS + 0x0008)) -#define INCA_IP2_MPS_VC3ENR ((volatile u32*)(INCA_IP2_MPS + 0x000C)) -/* voice channel 0 ... 3 interrupt status read register */ -#define INCA_IP2_MPS_RVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0010)) -#define INCA_IP2_MPS_RVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0014)) -#define INCA_IP2_MPS_RVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0018)) -#define INCA_IP2_MPS_RVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x001C)) -/* voice channel 0 ... 3 interrupt status set register */ -#define INCA_IP2_MPS_SVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0020)) -#define INCA_IP2_MPS_SVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0024)) -#define INCA_IP2_MPS_SVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0028)) -#define INCA_IP2_MPS_SVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x002C)) -/* voice channel 0 ... 3 interrupt status clear register */ -#define INCA_IP2_MPS_CVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0030)) -#define INCA_IP2_MPS_CVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0034)) -#define INCA_IP2_MPS_CVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0038)) -#define INCA_IP2_MPS_CVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x003C)) -/* common status 0 and 1 read register */ -#define INCA_IP2_MPS_RAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0040)) -#define INCA_IP2_MPS_RAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x0044)) -/* common status 0 and 1 set register */ -#define INCA_IP2_MPS_SAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0048)) -#define INCA_IP2_MPS_SAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x004C)) -/* common status 0 and 1 clear register */ -#define INCA_IP2_MPS_CAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0050)) -#define INCA_IP2_MPS_CAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x0054)) -/* notification enable register */ -#define INCA_IP2_MPS_CPU0_NFER ((volatile u32*)(INCA_IP2_MPS + 0x0060)) -#define INCA_IP2_MPS_CPU1_NFER ((volatile u32*)(INCA_IP2_MPS + 0x0064)) -/* CPU to CPU interrup request register */ -#define INCA_IP2_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(INCA_IP2_MPS + 0x0070)) -#define INCA_IP2_MPS_CPU0_2_CPU1_IER ((volatile u32*)(INCA_IP2_MPS + 0x0074)) -/* Global interrupt request and request enable register */ -#define INCA_IP2_MPS_GIRR ((volatile u32*)(INCA_IP2_MPS + 0x0078)) -#define INCA_IP2_MPS_GIER ((volatile u32*)(INCA_IP2_MPS + 0x007C)) - -/* Addresses of enable registers not yet defined -#define INCA_IP2_MPS_AD0ENR ((volatile u32*)(INCA_IP2_MPS + 0x????)) -#define INCA_IP2_MPS_AD1ENR ((volatile u32*)(INCA_IP2_MPS + 0x????)) -*/ - - -/***********************************************************************/ -/* Module : ASC0 register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_ASC0 (KSEG1+0x1E000400) -/***********************************************************************/ - -#define INCA_IP2_ASC0_TBUF ((volatile u32*)(INCA_IP2_ASC0 + 0x0020)) -#define INCA_IP2_ASC0_RBUF ((volatile u32*)(INCA_IP2_ASC0 + 0x0024)) -#define INCA_IP2_ASC0_FSTAT ((volatile u32*)(INCA_IP2_ASC0 + 0x0048)) -#define INCA_IP2_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -#define INCA_IP2_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -#define INCA_IP2_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -#define INCA_IP2_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP2_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -#define INCA_IP2_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP2_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -#define INCA_IP2_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : ASC1 register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_ASC1 (KSEG1+0x1E000800) -/***********************************************************************/ - -#define INCA_IP2_ASC1_TBUF ((volatile u32*)(INCA_IP2_ASC1 + 0x0020)) -#define INCA_IP2_ASC1_RBUF ((volatile u32*)(INCA_IP2_ASC1 + 0x0024)) -#define INCA_IP2_ASC1_FSTAT ((volatile u32*)(INCA_IP2_ASC1 + 0x0048)) -#define INCA_IP2_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -#define INCA_IP2_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -#define INCA_IP2_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -#define INCA_IP2_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP2_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -#define INCA_IP2_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP2_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -#define INCA_IP2_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : RCU register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_RCU (KSEG1+0x1E001C00) -/***********************************************************************/ - -/***Reset Request Register***/ -#define INCA_IP2_RCU_RST_REQ ((volatile u32*)(INCA_IP2_RCU + 0x0000)) -#define INCA_IP2_RCU_RST_REQ_CPU0 (1 << 31) -#define INCA_IP2_RCU_RST_REQ_CPU1 (1 << 30) -#define INCA_IP2_RCU_RST_REQ_CPUSUB (1 << 29) -#define INCA_IP2_RCU_RST_REQ_HRST (1 << 28) -#define INCA_IP2_RCU_RST_REQ_WDT0 (1 << 27) -#define INCA_IP2_RCU_RST_REQ_WDT1 (1 << 26) -#define INCA_IP2_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1)) -#define INCA_IP2_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23) -#define INCA_IP2_RCU_RST_REQ_SWTBOOT (1 << 22) -#define INCA_IP2_RCU_RST_REQ_DMA (1 << 21) -#define INCA_IP2_RCU_RST_REQ_ETHPHY1 (1 << 20) -#define INCA_IP2_RCU_RST_REQ_ETHPHY0 (1 << 19) -#define INCA_IP2_RCU_RST_REQ_CPU0_BR (1 << 18) - -/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ -#define INCA_IP2_RCU_RST_REQ_ALL 0xFC380000 - -/***NMI Status Register***/ -#define INCA_IP2_RCU_NMISR ((volatile u32*)(INCA_IP2_RCU + 0x00F4)) -#define INCA_IP2_RCU_NMISR_NMIEXT (1 << 2) -#define INCA_IP2_RCU_NMISR_NMIPLL2 (1 << 1) -#define INCA_IP2_RCU_NMISR_NMIPLL1 (1 << 0) - - -/***********************************************************************/ -/* Module : WDT register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_WDT (KSEG1+0x1F880000) -/***********************************************************************/ - -/***Watchdog Timer Control Register ***/ -#define INCA_IP2_WDT_BIU_WDT_CR ((volatile u32*)(INCA_IP2_WDT + 0x03F0)) -#define INCA_IP2_WDT_BIU_WDT_CR_GEN (1 << 31) -#define INCA_IP2_WDT_BIU_WDT_CR_DSEN (1 << 30) -#define INCA_IP2_WDT_BIU_WDT_CR_LPEN (1 << 29) -#define INCA_IP2_WDT_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) -#define INCA_IP2_WDT_BIU_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP2_WDT_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) -#define INCA_IP2_WDT_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP2_WDT_BIU_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) -#define INCA_IP2_WDT_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP2_WDT_BIU_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -#define INCA_IP2_WDT_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Watchdog Timer Status Register***/ -#define INCA_IP2_WDT_BIU_WDT_SR ((volatile u32*)(INCA_IP2_WDT + 0x03F8)) -#define INCA_IP2_WDT_BIU_WDT_SR_EN (1 << 31) -#define INCA_IP2_WDT_BIU_WDT_SR_AE (1 << 30) -#define INCA_IP2_WDT_BIU_WDT_SR_PRW (1 << 29) -#define INCA_IP2_WDT_BIU_WDT_SR_EXP (1 << 28) -#define INCA_IP2_WDT_BIU_WDT_SR_PWD (1 << 27) -#define INCA_IP2_WDT_BIU_WDT_SR_DS (1 << 26) -#define INCA_IP2_WDT_BIU_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -#define INCA_IP2_WDT_BIU_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : BCU0 register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_BCU0 (KSEG1+0x14100000) -/***********************************************************************/ - -#define INCA_IP2_BCU0_CON ((volatile u32*)(INCA_IP2_BCU0 + 0x0010)) -#define INCA_IP2_BCU0_ECON ((volatile u32*)(INCA_IP2_BCU0 + 0x0020)) -#define INCA_IP2_BCU0_EADD ((volatile u32*)(INCA_IP2_BCU0 + 0x0024)) -#define INCA_IP2_BCU0_EDAT ((volatile u32*)(INCA_IP2_BCU0 + 0x0028)) -#define INCA_IP2_BCU0_IRNCR1 ((volatile u32*)(INCA_IP2_BCU0 + 0x00F8)) -#define INCA_IP2_BCU0_IRNCR0 ((volatile u32*)(INCA_IP2_BCU0 + 0x00FC)) - - -/***********************************************************************/ -/* Module : BCU1 register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_BCU1 (KSEG1+0x1E000000) -/***********************************************************************/ - -#define INCA_IP2_BCU1_CON ((volatile u32*)(INCA_IP2_BCU1 + 0x0010)) -#define INCA_IP2_BCU1_ECON ((volatile u32*)(INCA_IP2_BCU1 + 0x0020)) -#define INCA_IP2_BCU1_EADD ((volatile u32*)(INCA_IP2_BCU1 + 0x0024)) -#define INCA_IP2_BCU1_EDAT ((volatile u32*)(INCA_IP2_BCU1 + 0x0028)) -#define INCA_IP2_BCU1_IRNCR1 ((volatile u32*)(INCA_IP2_BCU1 + 0x00F8)) -#define INCA_IP2_BCU1_IRNCR0 ((volatile u32*)(INCA_IP2_BCU1 + 0x00FC)) - - -/***********************************************************************/ -/* Module : MC register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_MC (KSEG1+0x1F800000) -/***********************************************************************/ - -#define INCA_IP2_MC_ERRCAUSE ((volatile u32*)(INCA_IP2_MC + 0x0010)) -#define INCA_IP2_MC_ERRADDR ((volatile u32*)(INCA_IP2_MC + 0x0020)) -#define INCA_IP2_MC_CON ((volatile u32*)(INCA_IP2_MC + 0x0060)) - -/***********************************************************************/ -/* Module : MC SDRAM register address and bits */ -/***********************************************************************/ -#define INCA_IP2_SDRAM (KSEG1+0x1F800200) -/***********************************************************************/ -#define INCA_IP2_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP2_SDRAM + 0x0040)) - -/***********************************************************************/ -/* Module : MC DDR register address and bits */ -/***********************************************************************/ -#define INCA_IP2_DDR (KSEG1+0x1F801000) -/***********************************************************************/ -#define INCA_IP2_DDR_MC_DC19 ((volatile u32*)(INCA_IP2_DDR + 0x0130)) -#define INCA_IP2_DDR_MC_DC20 ((volatile u32*)(INCA_IP2_DDR + 0x0140)) - - -/***********************************************************************/ -/* Module : PMS register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_PMS (KSEG1 + 0x1F100C00) - -#define INCA_IP2_PMS_PMS_SR ((volatile u32*) (INCA_IP2_PMS + 0x0000)) -#define INCA_IP2_PMS_PMS_SR_ASC1 (1 << 14) -#define INCA_IP2_PMS_PMS_SR_ASC0 (1 << 13) -#define INCA_IP2_PMS_PMS_GEN ((volatile u32*) (INCA_IP2_PMS + 0x0004)) -#define INCA_IP2_PMS_PMS_GEN_DMA (1 << 16) -#define INCA_IP2_PMS_PMS_GEN_ASC1 (1 << 14) -#define INCA_IP2_PMS_PMS_GEN_ASC0 (1 << 13) -#define INCA_IP2_PMS_PMS_GEN_SPI0 (1 << 11) -#define INCA_IP2_PMS_PMS_GEN_SPI1 (1 << 12) -#define INCA_IP2_PMS_PMS_CFG ((volatile u32*) (INCA_IP2_PMS + 0x0008)) - - -/***********************************************************************/ -/* Module : GPIO register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_GPIO (KSEG1 + 0x1F102600) - -#define INCA_IP2_GPIO_OUT ((volatile u32*) (INCA_IP2_GPIO + 0x0000)) -#define INCA_IP2_GPIO_IN ((volatile u32*) (INCA_IP2_GPIO + 0x0004)) -#define INCA_IP2_GPIO_DIR ((volatile u32*) (INCA_IP2_GPIO + 0x0008)) -#define INCA_IP2_GPIO_ALTSEL1 ((volatile u32*) (INCA_IP2_GPIO + 0x000C)) -#define INCA_IP2_GPIO_ALTSEL2 ((volatile u32*) (INCA_IP2_GPIO + 0x0010)) -#define INCA_IP2_GPIO_STOFF ((volatile u32*) (INCA_IP2_GPIO + 0x0014)) -#define INCA_IP2_GPIO_OD ((volatile u32*) (INCA_IP2_GPIO + 0x0018)) -#define INCA_IP2_GPIO_PUDEB ((volatile u32*) (INCA_IP2_GPIO + 0x001C)) - -/***********************************************************************/ -/* Module : RCU register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_RCU (KSEG1+0x1E001C00) -/***********************************************************************/ - -/***Reset Request Register***/ -#define INCA_IP2_RCU_RST_REQ ((volatile u32*)(INCA_IP2_RCU + 0x0000)) -#define INCA_IP2_RCU_RST_REQ_CPU0 (1 << 31) -#define INCA_IP2_RCU_RST_REQ_CPU1 (1 << 30) -#define INCA_IP2_RCU_RST_REQ_CPUSUB (1 << 29) -#define INCA_IP2_RCU_RST_REQ_HRST (1 << 28) -#define INCA_IP2_RCU_RST_REQ_WDT0 (1 << 27) -#define INCA_IP2_RCU_RST_REQ_WDT1 (1 << 26) -#define INCA_IP2_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1)) -#define INCA_IP2_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23) -#define INCA_IP2_RCU_RST_REQ_SWTBOOT (1 << 22) -#define INCA_IP2_RCU_RST_REQ_DMA (1 << 21) -#define INCA_IP2_RCU_RST_REQ_ETHPHY1 (1 << 20) -#define INCA_IP2_RCU_RST_REQ_ETHPHY0 (1 << 19) -#define INCA_IP2_RCU_RST_REQ_CPU0_BR (1 << 18) - -/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ -#define INCA_IP2_RCU_RST_REQ_ALL 0xFC380000 - -/***Reset Status Register***/ -#define INCA_IP2_RCU_SR ((volatile u32*)(INCA_IP2_RCU + 0x0008)) - -/***NMI Status Register***/ -#define INCA_IP2_RCU_NMISR ((volatile u32*)(INCA_IP2_RCU + 0x00F4)) -#define INCA_IP2_RCU_NMISR_NMIEXT (1 << 2) -#define INCA_IP2_RCU_NMISR_NMIPLL2 (1 << 1) -#define INCA_IP2_RCU_NMISR_NMIPLL1 (1 << 0) - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_EBU (KSEG1+0x14102000) -/***********************************************************************/ - -#define INCA_IP2_EBU_ADDSEL0 ((volatile u32*)(INCA_IP2_EBU + 0x0020)) -#define INCA_IP2_EBU_ADDSEL1 ((volatile u32*)(INCA_IP2_EBU + 0x0024)) -#define INCA_IP2_EBU_ADDSEL2 ((volatile u32*)(INCA_IP2_EBU + 0x0028)) -#define INCA_IP2_EBU_ADDSEL3 ((volatile u32*)(INCA_IP2_EBU + 0x002C)) -#define INCA_IP2_EBU_CON0 ((volatile u32*)(INCA_IP2_EBU + 0x0060)) -#define INCA_IP2_EBU_CON1 ((volatile u32*)(INCA_IP2_EBU + 0x0064)) -#define INCA_IP2_EBU_CON2 ((volatile u32*)(INCA_IP2_EBU + 0x0068)) -#define INCA_IP2_EBU_CON3 ((volatile u32*)(INCA_IP2_EBU + 0x006C)) -#define INCA_IP2_EBU_CON_WRDIS (1 << 31) - - - - -/***********************************************************************/ -/* Module : SWITCH register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_SWITCH (KSEG1+0x18000000) -/***********************************************************************/ - -/* PR Base address */ -#define PR_BASE (INCA_IP2_SWITCH + 0x00008000) - -/* SE Base Address */ -#define SE_BASE (INCA_IP2_SWITCH + 0x00009000) - -#define PR_CTRL_REG (PR_BASE + 0x0000) -#define MA_LEARN_REG (PR_BASE + 0x0004) -#define DST_LOOKUP_REG (PR_BASE + 0x0008) - -#define COS_SEL_REG (PR_BASE + 0x000c) -#define PRI2_COS_REG (PR_BASE + 0x0010) -#define UNKNOWN_DEST_REG (PR_BASE + 0x0014) - -#define CPU_ACS_CTRL_REG (PR_BASE + 0x0018) -#define CPU_ACS_DATA_REG (PR_BASE + 0x001c) - -#define MA_READ_REG (PR_BASE + 0x0020) -#define TB_CTRL_REG (PR_BASE + 0x0024) -#define RATE_REG (PR_BASE + 0x0028) -#define BURST_REG (PR_BASE + 0x0048) -#define EBURST_REG (PR_BASE + 0x0068) - -#define RULE_SEL_REG (PR_BASE + 0x0088) - -#define GEN_SFT_AGE_STB (PR_BASE + 0x008C) -#define PR_ISR_REG (PR_BASE + 0x0090) -#define PR_IMR_REG (PR_BASE + 0x0094) -#define PR_IPR_REG (PR_BASE + 0x0098) -#define BPDU_REG (PR_BASE + 0x00A4) - -/* Switching Engine Register Description */ -#define QLL_CMD_REG (SE_BASE) -#define QLL_DATA_REG0 (SE_BASE + 0x0004) -#define QLL_DATA_REG1 (SE_BASE + 0x0008) - -#define VLAN_MIBS_CMD_REG (SE_BASE + 0x000c) -#define VLAN_MIBS_DATA_REG (SE_BASE + 0x0010) - -#define SD_CMD_REG (SE_BASE + 0x0014) -#define SD_DATA_REGS0 (SE_BASE + 0x0018) -#define SD_DATA_REGS1 (SE_BASE + 0x001C) -#define SD_DATA_REGS2 (SE_BASE + 0x0020) - -#define VLAN_TBL_CMD_REG (SE_BASE + 0x0024) -#define VLAN_TBL_DATA_REG (SE_BASE + 0x0028) - -#define FD_TBL_CMD_REG (SE_BASE + 0x002c) -#define FD_TBL_DATA_REG (SE_BASE + 0x0030) - -#define SYMM_VLAN_REG (SE_BASE + 0x0038) -#define PORT_AUTH (SE_BASE + 0x0048) -#define CPU_LINK_OK_REG (SE_BASE + 0x0050) -/* #define TRUNK_CTRL_REGS (SE_BASE + 0x0054) */ -#define MIRROR_PORT_REG (SE_BASE + 0x0064) - -#define ST_PT_REG (SE_BASE + 0x0068) -#define JUMBO_ENABLE_REG (SE_BASE + 0x006C) -#define STACK_PORT_REG (SE_BASE + 0x0074) -#define EG_MON_REG (SE_BASE + 0x007C) -#define VR_MIB_REG (SE_BASE + 0x0080) -#define QUEUE_CMD_REGS (SE_BASE + 0x0090) - -#define GLOBAL_RX_WM_REG (SE_BASE + 0x0200) -#define PORT0_RX_WM_REG0 (SE_BASE + 0x0204) -#define PORT1_RX_WM_REG0 (SE_BASE + 0x0208) -#define PORT2_RX_WM_REG0 (SE_BASE + 0x020C) - -#define PORT_RX_WM_REGS (SE_BASE + 0x0200) -#define PORT_TX_WM_REGS (SE_BASE + 0x0300) -#define PORT0_TX_WM_REG0 (SE_BASE + 0x0330) -#define PORT1_TX_WM_REG0 (SE_BASE + 0x0338) -#define PORT2_TX_WM_REG0 (SE_BASE + 0x0340) -#define PORT0_TX_WM_REG1 (SE_BASE + 0x0334) -#define PORT1_TX_WM_REG1 (SE_BASE + 0x033C) -#define PORT2_TX_WM_REG1 (SE_BASE + 0x0344) - - -#define QUEUE_STATUS_REGS (SE_BASE + 0x0400) - -#define SE_INT_STS_REG (SE_BASE + 0x08e0) -#define SE_INT_MSK_REG_RD (SE_BASE + 0x08e4) -#define SE_INT_MSK_REG_WR (SE_BASE + 0x08e8) -#define SE_INT_PRI_REG_RD (SE_BASE + 0x08ec) -#define SE_INT_PRI_REG_WR (SE_BASE + 0x08f0) /* address too be defined*/ - -/***********************************************************************/ -/* Module : Ethernet Switch port related addresses and bits */ -/***********************************************************************/ -#define GPORT0_BASE (KSEG1+0x18006000) -#define GPORT1_BASE (KSEG1+0x18007000) -#define GPORT2_BASE (KSEG1+0x1800C000) - -#define PORTREG_BASE GPORT0_BASE - -#define SWITCH_P0_GMAC_REG (GPORT0_BASE + 0x0004) -#define SWITCH_P0_GMAC_CTRL (GPORT0_BASE + 0x000C) -#define SWITCH_P0_RTX_INT_STATUS (GPORT0_BASE + 0x0010) -#define SWITCH_P0_RTX_INT_MASK (GPORT0_BASE + 0x0014) -#define SWITCH_P0_INT_PRIORITY (GPORT0_BASE + 0x0018) -#define SWITCH_P0_RX_CONF (GPORT0_BASE + 0x0400) -#define SWITCH_P0_OFFSET0_REG (GPORT0_BASE + 0x0404) -#define SWITCH_P0_OFFSET1_REG (GPORT0_BASE + 0x0408) -#define SWITCH_P0_PORT_MASK0_REG (GPORT0_BASE + 0x0420) -#define SWITCH_P0_PORT_MASK1_REG (GPORT0_BASE + 0x0424) -#define SWITCH_P0_PORT_MASK2_REG (GPORT0_BASE + 0x0428) -#define SWITCH_P0_PORT_MASK3_REG (GPORT0_BASE + 0x042C) -#define SWITCH_P0_PORT_RULE0_REG (GPORT0_BASE + 0x0430) -#define SWITCH_P0_PORT_RULE1_REG (GPORT0_BASE + 0x0434) -#define SWITCH_P0_PORT_RULE2_REG (GPORT0_BASE + 0x0438) -#define SWITCH_P0_PORT_RULE3_REG (GPORT0_BASE + 0x043C) -#define SWITCH_P0_PORT_IKEY_SEL (GPORT0_BASE + 0x0440) -#define SWITCH_P0_PORT_RX_VLAN_ID (GPORT0_BASE + 0x0450) -#define SWITCH_P0_TX_CONF (GPORT0_BASE + 0x0800) -#define SWITCH_P0_PORT_TX_VLAN_ID (GPORT0_BASE + 0x0804) -#define SWITCH_P0_PORT_MIB_REG_0 (GPORT0_BASE + 0x0C00) -#define SWITCH_P0_GMAC_MIB_REG_0 (GPORT0_BASE + 0x0C54) - -#define SWITCH_P1_GMAC_REG (GPORT1_BASE + 0x0004) -#define SWITCH_P1_GMAC_CTRL (GPORT1_BASE + 0x000C) -#define SWITCH_P1_RTX_INT_STATUS (GPORT1_BASE + 0x0010) -#define SWITCH_P1_RTX_INT_MASK (GPORT1_BASE + 0x0014) -#define SWITCH_P1_INT_PRIORITY (GPORT1_BASE + 0x0018) -#define SWITCH_P1_RX_CONF (GPORT1_BASE + 0x0400) -#define SWITCH_P1_OFFSET0_REG (GPORT1_BASE + 0x0404) -#define SWITCH_P1_OFFSET1_REG (GPORT1_BASE + 0x0408) -#define SWITCH_P1_PORT_MASK0_REG (GPORT1_BASE + 0x0420) -#define SWITCH_P1_PORT_MASK1_REG (GPORT1_BASE + 0x0424) -#define SWITCH_P1_PORT_MASK2_REG (GPORT1_BASE + 0x0428) -#define SWITCH_P1_PORT_MASK3_REG (GPORT1_BASE + 0x042C) -#define SWITCH_P1_PORT_RULE0_REG (GPORT1_BASE + 0x0430) -#define SWITCH_P1_PORT_RULE1_REG (GPORT1_BASE + 0x0434) -#define SWITCH_P1_PORT_RULE2_REG (GPORT1_BASE + 0x0438) -#define SWITCH_P1_PORT_RULE3_REG (GPORT1_BASE + 0x043C) -#define SWITCH_P1_PORT_IKEY_SEL (GPORT1_BASE + 0x0440) -#define SWITCH_P1_PORT_RX_VLAN_ID (GPORT1_BASE + 0x0450) -#define SWITCH_P1_TX_CONF (GPORT1_BASE + 0x0800) -#define SWITCH_P1_PORT_TX_VLAN_ID (GPORT1_BASE + 0x0804) -#define SWITCH_P1_PORT_MIB_REG_0 (GPORT1_BASE + 0x0C00) -#define SWITCH_P1_GMAC_MIB_REG_0 (GPORT1_BASE + 0x0C54) - -#define SWITCH_P2_GMAC_REG (GPORT2_BASE + 0x0004) -#define SWITCH_P2_GMAC_CTRL (GPORT2_BASE + 0x000C) -#define SWITCH_P2_RTX_INT_STATUS (GPORT2_BASE + 0x0010) -#define SWITCH_P2_RTX_INT_MASK (GPORT2_BASE + 0x0014) -#define SWITCH_P2_INT_PRIORITY (GPORT2_BASE + 0x0018) -#define SWITCH_P2_MDIO_ID_1 (GPORT2_BASE + 0x00A8) -#define SWITCH_P2_PAUSE_CTL_1 (GPORT2_BASE + 0x00B0) -#define SWITCH_P2_MDIO_MOD_SEL (GPORT2_BASE + 0x00B4) -#define SWITCH_P2_MDIO_ACC_0 (GPORT2_BASE + 0x00B8) -#define SWITCH_P2_RX_CONF (GPORT2_BASE + 0x0400) -#define SWITCH_P2_OFFSET0_REG (GPORT2_BASE + 0x0404) -#define SWITCH_P2_OFFSET1_REG (GPORT2_BASE + 0x0408) -#define SWITCH_P2_PORT_MASK0_REG (GPORT2_BASE + 0x0420) -#define SWITCH_P2_PORT_MASK1_REG (GPORT2_BASE + 0x0424) -#define SWITCH_P2_PORT_MASK2_REG (GPORT2_BASE + 0x0428) -#define SWITCH_P2_PORT_MASK3_REG (GPORT2_BASE + 0x042C) -#define SWITCH_P2_PORT_RULE0_REG (GPORT2_BASE + 0x0430) -#define SWITCH_P2_PORT_RULE1_REG (GPORT2_BASE + 0x0434) -#define SWITCH_P2_PORT_RULE2_REG (GPORT2_BASE + 0x0438) -#define SWITCH_P2_PORT_RULE3_REG (GPORT2_BASE + 0x043C) -#define SWITCH_P2_PORT_IKEY_SEL (GPORT2_BASE + 0x0440) -#define SWITCH_P2_PORT_RX_VLAN_ID (GPORT2_BASE + 0x0450) -#define SWITCH_P2_TX_CONF (GPORT2_BASE + 0x0800) -#define SWITCH_P2_PORT_TX_VLAN_ID (GPORT2_BASE + 0x0804) -#define SWITCH_P2_PORT_MIB_REG_0 (GPORT2_BASE + 0x0C00) -#define SWITCH_P2_GMAC_MIB_REG_0 (GPORT2_BASE + 0x0C54) - -#define MDIO_MOD_SEL SWITCH_P2_MDIO_MOD_SEL -#define SWITCH_MDIO_ACC SWITCH_P2_MDIO_ACC_0 -#define SWITCH_MDIO_ID SWITCH_P2_MDIO_ID_1 -/* #define TX_CONFIG_REG SWITCH_P0_TX_CONF */ - -#define SWITCH_PMAC_HD_CTL (GPORT2_BASE + 0x0070) -#define SWITCH_PMAC_SA1 (GPORT2_BASE + 0x0074) -#define SWITCH_PMAC_SA2 (GPORT2_BASE + 0x0078) -#define SWITCH_PMAC_DA1 (GPORT2_BASE + 0x007C) -#define SWITCH_PMAC_DA2 (GPORT2_BASE + 0x0080) -#define SWITCH_PMAC_VLAN (GPORT2_BASE + 0x0084) -#define SWITCH_PMAC_TX_IPG (GPORT2_BASE + 0x0088) -#define SWITCH_PMAC_RX_IPG (GPORT2_BASE + 0x008C) - diff --git a/package/uboot-ifxmips/files/include/asm-mips/pinstrap.h b/package/uboot-ifxmips/files/include/asm-mips/pinstrap.h deleted file mode 100644 index 1a446fa916..0000000000 --- a/package/uboot-ifxmips/files/include/asm-mips/pinstrap.h +++ /dev/null @@ -1,12 +0,0 @@ -#define FLASH_STRAP 0x1 -#define MII_0_STRAP 0x2 -#define MII_1_STRAP 0x3 -#define ASC_STRAP 0x4 -#define SFLASH_STRAP 0x5 -#define RESERVE_STRAP 0x6 -#define PRODUCT_TEST_STRAP 0x7 -#define PIN_STRAP_MASK 0x001C0000 -#define PIN_STRAP_SHIFT 18 -#define PIN_STRAP 0xB0100914 -#define SDRAM_WIDTH_MASK 0x400000 -#define SDRAM_WIDTH_SHIFT 22 diff --git a/package/uboot-ifxmips/files/include/boot.h b/package/uboot-ifxmips/files/include/boot.h deleted file mode 100644 index 8f70ebb43d..0000000000 --- a/package/uboot-ifxmips/files/include/boot.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef _BOOT_H -#define _BOOT_H - -/* All this should be defined somewhere in danube.h later... */ - -#define MPS_SRAM_BASE_ADDRESS 0xBF200000 -#define MPS_SRAM_BOOT_OFFSET 0x1C0 - -/* Offset for CPU1 (both CPUs have same register set) */ -#define BOOT_BASE_ADDRESS (MPS_SRAM_BASE_ADDRESS + MPS_SRAM_BOOT_OFFSET) -#define BOOT_CPU_OFFSET 0x20 - - -#ifdef __ASSEMBLY__ -#define BOOT_RVEC (BOOT_BASE_ADDRESS + 0x00) -#define BOOT_NVEC (BOOT_BASE_ADDRESS + 0x04) -#define BOOT_EVEC (BOOT_BASE_ADDRESS + 0x08) -#define BOOT_CP0_CAUSE (BOOT_BASE_ADDRESS + 0x0C) -#define BOOT_CP0_EPC (BOOT_BASE_ADDRESS + 0x10) -#define BOOT_CP0_EEPC (BOOT_BASE_ADDRESS + 0x14) -#define BOOT_SIZE (BOOT_BASE_ADDRESS + 0x18) /* for CPU1 */ -#define BOOT_RCU_SR (BOOT_BASE_ADDRESS + 0x18) /* for CPU0 */ -#define BOOT_CFG_STAT (BOOT_BASE_ADDRESS + 0x1C) -#else -#define BOOT_RVEC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x00) -#define BOOT_NVEC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x04) -#define BOOT_EVEC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x08) -#define BOOT_CP0_STATUS(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x0C) -#define BOOT_CP0_EPC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x10) -#define BOOT_CP0_EEPC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x14) -#define BOOT_SIZE(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x18) /* for CPU1 */ -#define BOOT_RCU_SR(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x18) /* for CPU0 */ -#define BOOT_CFG_STAT(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x1C) -#endif - -#define BOOT_CFG_NOR 0x01 -#define BOOT_CFG_MII 0x02 -#define BOOT_CFG_PCI 0x03 -#define BOOT_CFG_ASC 0x04 -#define BOOT_CFG_SFLASH 0x05 -#define BOOT_CFG_NAND 0x06 -#define BOOT_CFG_RMII 0x07 -#define BOOT_CFG_TEST 0x00 - -#define BOOT_NUM_RETRY 3 - -#define BOOT_STAT_MASK_ALL 0x0000FFFF -#define BOOT_STAT_MASK_STAT 0x0000F000 -#define BOOT_STAT_MASK_BERR 0x00000F00 -#define BOOT_STAT_MASK_BSTRAP 0x000000F0 -#define BOOT_STAT_MASK_BMODULE 0x0000000F - -#define BOOT_STAT_INIT 0x00000000 -#define BOOT_STAT_BSTRAP 0x00001000 -#define BOOT_STAT_RETRY 0x00002000 -#define BOOT_STAT_START 0x00003000 -#define BOOT_STAT_HALT 0x0000F000 - -#define BOOT_ERR_NO_RVEC 0x00000100 -#define BOOT_ERR_NO_NVEC 0x00000200 -#define BOOT_ERR_NO_EVEC 0x00000300 -#define BOOT_ERR_BSTRAP 0x00000400 -#define BOOT_ERR_EXC 0x00000800 - -#ifndef __ASSEMBLY__ -void boot_set_status( u32 status, u32 mask); -void boot_set_config( u32 config); -void boot_set_rvec( u32 vector); -void boot_set_size( u32 size); -void boot_sdbg( u8* string, u32 value); -void boot_error( u32 berr); -int boot_from_ebu(void); -void _boot_rvec(void); -typedef struct -{ - u32 cpu; /** CPU number */ - u32 config; /** Boot configuration */ - u32 endian; /** CPU endianess */ - u32 debug; /** Debug mode */ - u32 (*exit)(void); /** application vector */ -} boot_data; - -extern boot_data bootrom; -#endif - -#endif /* #ifdef _BOOT_H */ diff --git a/package/uboot-ifxmips/files/include/configs/danube.h b/package/uboot-ifxmips/files/include/configs/danube.h deleted file mode 100644 index cd2d247fe1..0000000000 --- a/package/uboot-ifxmips/files/include/configs/danube.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file contains the configuration parameters for the danube board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define USE_REFERENCE_BOARD -//#define USE_EVALUATION_BOARD - -//#define DANUBE_BOOT_FROM_EBU -#define DANUBE_USE_DDR_RAM - -#ifdef DANUBE_USE_DDR_RAM -//#define DANUBE_DDR_RAM_111M -//#define DANUBE_DDR_RAM_166M -//#define PROMOSDDR400 -//#define DDR_SAMSUNG_166M -#define DDR_PSC_166M -//#define DANUBE_DDR_RAM_133M -#define DANUBE_DDR_RAM_SIZE 32 /* 32M DDR-DRAM for reference board */ -#endif - -#define CONFIG_LZMA 1 /* use LZMA for compression */ - -#define CLK_OUT2_25MHZ -#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ -#define CONFIG_IFX_MIPS 1 /* in an Infineon chip */ -#define CONFIG_DANUBE 1 /* on a danube Board */ -#define RAM_SIZE 0x2000000 /*32M ram*/ - -#define CPU_CLOCK_RATE 235000000 /* 235 MHz clock for the MIPS core */ - -#define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */ - -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define DEBUG_PARSER 2 - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 300, 9600, 19200, 38400, 57600, 115200 } - -#ifndef CFG_BOOTSTRAP_CODE -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#endif - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS -/* by MarsLin 2005/05/10, to support different hardware configuations */ -//#define CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ethaddr=11:22:33:44:55:66\0" \ - "serverip=192.168.45.100\0" \ - "ipaddr=192.168.45.108\0" \ - "ram_addr=0x80500000\0" \ - "kernel_addr=0xb0030000\0" \ - "flashargs=setenv bootargs rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} init=/etc/preinit\0" \ - "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} console=ttyS1,115200 ethaddr=${ethaddr} ${mtdparts}\0" \ - "flash_flash=run flashargs addip addmisc;bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \ - "net_flash=run load_kernel flashargs addip addmisc;bootm ${ram_addr}\0" \ - "net_nfs=run load_kernel nfsargs addip addmisc;bootm ${ram_addr}\0" \ - "load_kernel=tftp ${ram_addr} ${tftppath}openwrt-ifxmips-uImage\0" \ - "update_uboot=tftp 0x80500000 u-boot.ifx;era 1:0-10; cp.b 0x80500000 0xb0000000 0x10000\0" \ - "update_openwrt=tftp ${ram_addr} ${tftppath}openwrt-ifxmips-squashfs.image; era ${kernel_addr} +${filesize} 0; cp.b ${ram_addr} ${kernel_addr} ${filesize}\0" - -#define CONFIG_BOOTCOMMAND "run flash_flash" - -#define CONFIG_COMMANDS_YES (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_NET ) - -#define CONFIG_COMMANDS_NO (CFG_CMD_NFS | \ - CFG_CMD_FPGA | \ - CFG_CMD_IMLS | \ - CFG_CMD_ITEST | \ - CFG_CMD_XING | \ - CFG_CMD_IMI | \ - CFG_CMD_BMP | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CONSOLE | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB ) - -#define CONFIG_COMMANDS (CONFIG_COMMANDS_YES & ~CONFIG_COMMANDS_NO) - -#if 0 - CFG_CMD_DHCP - CFG_CMD_ELF - CFG_CMD_NAND -#endif - -#include - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "DANUBE # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args*/ - -#define CFG_MALLOC_LEN 128*1024 - -#define CFG_BOOTPARAMS_LEN 128*1024 - -#define CFG_HZ (CPU_CLOCK_RATE / 2) - -#define CFG_LOAD_ADDR 0x80100000 /* default load address */ - -#define CFG_MEMTEST_START 0x80100000 -#define CFG_MEMTEST_END 0x80400000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (135) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xB0000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xB4000000 /* Flash Bank #2 */ - -#define BOOTSTRAP_TEXT_BASE 0xb0000000 - -/* The following #defines are needed to get flash environment right */ -#define CFG_MONITOR_BASE UBOOT_RAM_TEXT_BASE /* board/danube/config.mk. = 0xA0800000 */ -#define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE /* board/danube/config.mk. = 0xA0800000 */ -#define CFG_MONITOR_LEN (256 << 10) - -#define CFG_INIT_SP_OFFSET 0x400000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20 * CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20 * CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -//#define CFG_ENV_IS_NOWHERE 1 -//#define CFG_ENV_IS_IN_NVRAM 1 -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR 0xB0020000 -#define CFG_ENV_SIZE 0x10000 - -#define CONFIG_FLASH_16BIT - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_DANUBE_SWITCH -#define CONFIG_NET_MULTI -#define CONFIG_ENV_OVERWRITE - -#define EXCEPTION_BASE 0x200 - -/** - *\brief definition for nand - * - */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_ChipID_UNKNOWN 0x00 -#define SECTORSIZE 512 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - - -#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ -#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ - -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) -#define NAND_WAIT_READY(nand) -#define WRITE_NAND_COMMAND(d, adr) -#define WRITE_NAND_ADDRESS(d, adr) -#define WRITE_NAND(d, adr) -#define READ_NAND(adr) -/* the following are NOP's in our implementation */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) - - - -#define NAND_BASE_ADDRESS 0xB4000000 - -#define NAND_WRITE(addr, val) *((u8*)(NAND_BASE_ADDRESS | (addr))) = val;while((*EBU_NAND_WAIT & 0x08) == 0); -#define NAND_READ(addr, val) val = *((u8*)(NAND_BASE_ADDRESS | (addr))) -#define NAND_CE_SET -#define NAND_CE_CLEAR -#define NAND_READY ( ((*EBU_NAND_WAIT)&0x07) == 7) -#define NAND_READY_CLEAR *EBU_NAND_WAIT = 0; -#define WRITE_CMD 0x18 -#define WRITE_ADDR 0x14 -#define WRITE_LADDR 0x10 -#define WRITE_DATA 0x10 -#define READ_DATA 0x10 -#define READ_LDATA 0x00 -#define ACCESS_WAIT -#define IFX_ATC_NAND 0xc176 -#define IFX_BTC_NAND 0xc166 -#define ST_512WB2_NAND 0x2076 - -#define NAND_OK 0x00000000 /* Bootstrap succesful, start address in BOOT_RVEC */ -#define NAND_ERR 0x80000000 -#define NAND_ACC_TIMEOUT (NAND_ERR | 0x00000001) -#define NAND_ACC_ERR (NAND_ERR | 0x00000002) - - -/***************************************************************************** - * DANUBE - *****************************************************************************/ -/* lock cache for C program stack */ -/* points to ROM */ -/* stack size is 16K */ -#define LOCK_DCACHE_ADDR 0x9FC00000 -#define LOCK_DCACHE_SIZE 0x1000 - -/* - * Memory layout - */ -#define CFG_SDRAM_BASE 0x80000000 -#define CFG_SDRAM_BASE_UNCACHE 0xA0000000 -#define CFG_CACHE_LOCK_SIZE LOCK_DCACHE_SIZE - -/* - * Cache settings - */ -#define CFG_CACHE_SIZE 16384 -#define CFG_CACHE_LINES 32 -#define CFG_CACHE_WAYS 4 -#define CFG_CACHE_SETS 128 - -#define CFG_ICACHE_SIZE CFG_CACHE_SIZE -#define CFG_DCACHE_SIZE CFG_CACHE_SIZE -#define CFG_CACHELINE_SIZE CFG_CACHE_LINES - -#endif /* __CONFIG_H */ diff --git a/package/uboot-ifxmips/files/lib_bootstrap/Makefile b/package/uboot-ifxmips/files/lib_bootstrap/Makefile deleted file mode 100644 index 9dc77df218..0000000000 --- a/package/uboot-ifxmips/files/lib_bootstrap/Makefile +++ /dev/null @@ -1,60 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB := $(obj)libbootstrap.a - -OBJS := board.o LzmaDecode.o string.o crc32.o LzmaWrapper.o -CFLAGS += -DCFG_BOOTSTRAP_CODE - -ifeq ($(BOOTSTRAP_PRINTF_STATUS), BOOTSTRAP_PRINTF_ENABLED) -OBJS += time.o console.o ctype.o display_options.o vsprintf.o lists.o devices.o -CFLAGS += -DDEBUG_ENABLE_BOOTSTRAP_PRINTF -endif - -SRCS := $(OBJS:.o=.c) -OBJS := $(addprefix $(obj),$(OBJS)) - -all: $(SRCS) $(obj).depend $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -vpath %.c ../common ../lib_generic ../lib_$(CPU) - -board_bootstrap.c: - ln -s ../lib_$(CPU)/board.c $@ - -#LzmaDecode.c LzmaWrapper.c string.c crc32.c: -# ln -s ../lib_generic/$@ $@ - -######################################################################### - -#include $(SRCTREE)/rules.mk -$(obj).depend: $(SRCS) - $(CC) -M $(CFLAGS) $^ > $@ - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-ifxmips/files/lib_generic/LzmaDecode.c b/package/uboot-ifxmips/files/lib_generic/LzmaDecode.c deleted file mode 100644 index 1ce2398f47..0000000000 --- a/package/uboot-ifxmips/files/lib_generic/LzmaDecode.c +++ /dev/null @@ -1,620 +0,0 @@ -/* - LzmaDecode.c - LZMA Decoder (optimized for Speed version) - - LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) - http://www.7-zip.org/ - - LZMA SDK is licensed under two licenses: - 1) GNU Lesser General Public License (GNU LGPL) - 2) Common Public License (CPL) - It means that you can select one of these two licenses and - follow rules of that license. - - SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions - to this file, however, are subject to the LGPL or CPL terms. -*/ - -#include -#include - -#ifdef CONFIG_LZMA - -#include "LzmaDecode.h" - -#define kNumTopBits 24 -#define kTopValue ((UInt32)1 << kNumTopBits) - -#define kNumBitModelTotalBits 11 -#define kBitModelTotal (1 << kNumBitModelTotalBits) -#define kNumMoveBits 5 - -#define RC_READ_BYTE (*Buffer++) - -#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ - { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} - -#ifdef _LZMA_IN_CB - -#ifndef CFG_BOOTSTRAP_CODE -#define RC_TEST { if (Buffer == BufferLim) \ - { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return result; } \ - BufferLim = Buffer + size; if (size == 0) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return LZMA_RESULT_DATA_ERROR; } }} -#else //CFG_BOOTSTRAP_CODE -#define RC_TEST { if (Buffer == BufferLim) \ - { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) { return result; } \ - BufferLim = Buffer + size; if (size == 0) { return LZMA_RESULT_DATA_ERROR; } }} -#endif //CFG_BOOTSTRAP_CODE - -#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 - -#else //_LZMA_IN_CB - -#ifndef CFG_BOOTSTRAP_CODE -#define RC_TEST { if (Buffer == BufferLim) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return LZMA_RESULT_DATA_ERROR; } } -#else //CFG_BOOTSTRAP_CODE -#define RC_TEST { if (Buffer == BufferLim) { return LZMA_RESULT_DATA_ERROR; } } -#endif //CFG_BOOTSTRAP_CODE - -#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - -#endif //_LZMA_IN_CB - -#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } -#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) -#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; -#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; - -#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ - { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) - -#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ - { int i = numLevels; res = 1; \ - do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ - res -= (1 << numLevels); } - - -#define kNumPosBitsMax 4 -#define kNumPosStatesMax (1 << kNumPosBitsMax) - -#define kLenNumLowBits 3 -#define kLenNumLowSymbols (1 << kLenNumLowBits) -#define kLenNumMidBits 3 -#define kLenNumMidSymbols (1 << kLenNumMidBits) -#define kLenNumHighBits 8 -#define kLenNumHighSymbols (1 << kLenNumHighBits) - -#define LenChoice 0 -#define LenChoice2 (LenChoice + 1) -#define LenLow (LenChoice2 + 1) -#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) -#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) - - -#define kNumStates 12 -#define kNumLitStates 7 - -#define kStartPosModelIndex 4 -#define kEndPosModelIndex 14 -#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) - -#define kNumPosSlotBits 6 -#define kNumLenToPosStates 4 - -#define kNumAlignBits 4 -#define kAlignTableSize (1 << kNumAlignBits) - -#define kMatchMinLen 2 - -#define IsMatch 0 -#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) -#define IsRepG0 (IsRep + kNumStates) -#define IsRepG1 (IsRepG0 + kNumStates) -#define IsRepG2 (IsRepG1 + kNumStates) -#define IsRep0Long (IsRepG2 + kNumStates) -#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) -#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) -#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) -#define LenCoder (Align + kAlignTableSize) -#define RepLenCoder (LenCoder + kNumLenProbs) -#define Literal (RepLenCoder + kNumLenProbs) - -#if Literal != LZMA_BASE_SIZE -StopCompilingDueBUG -#endif - -int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) -{ - unsigned char prop0; - if (size < LZMA_PROPERTIES_SIZE) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("ERROR: %s, %d\n", __FILE__, __LINE__); -#endif - return LZMA_RESULT_DATA_ERROR; - } - prop0 = propsData[0]; - if (prop0 >= (9 * 5 * 5)) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("ERROR: %s, %d\n", __FILE__, __LINE__); -#endif - return LZMA_RESULT_DATA_ERROR; - } - { - for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); - for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); - propsRes->lc = prop0; - /* - unsigned char remainder = (unsigned char)(prop0 / 9); - propsRes->lc = prop0 % 9; - propsRes->pb = remainder / 5; - propsRes->lp = remainder % 5; - */ - } - - #ifdef _LZMA_OUT_READ - { - int i; - propsRes->DictionarySize = 0; - for (i = 0; i < 4; i++) - propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); - if (propsRes->DictionarySize == 0) - propsRes->DictionarySize = 1; - } - #endif - return LZMA_RESULT_OK; -} - -#define kLzmaStreamWasFinishedId (-1) - -int LzmaDecode(CLzmaDecoderState *vs, - #ifdef _LZMA_IN_CB - ILzmaInCallback *InCallback, - #else - const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, - #endif - unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) -{ - CProb *p = vs->Probs; - SizeT nowPos = 0; - Byte previousByte = 0; - UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; - UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; - int lc = vs->Properties.lc; - - #ifdef _LZMA_OUT_READ - - UInt32 Range = vs->Range; - UInt32 Code = vs->Code; - #ifdef _LZMA_IN_CB - const Byte *Buffer = vs->Buffer; - const Byte *BufferLim = vs->BufferLim; - #else - const Byte *Buffer = inStream; - const Byte *BufferLim = inStream + inSize; - #endif - int state = vs->State; - UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; - int len = vs->RemainLen; - UInt32 globalPos = vs->GlobalPos; - UInt32 distanceLimit = vs->DistanceLimit; - - Byte *dictionary = vs->Dictionary; - UInt32 dictionarySize = vs->Properties.DictionarySize; - UInt32 dictionaryPos = vs->DictionaryPos; - - Byte tempDictionary[4]; - - #ifndef _LZMA_IN_CB - *inSizeProcessed = 0; - #endif - *outSizeProcessed = 0; - if (len == kLzmaStreamWasFinishedId) - return LZMA_RESULT_OK; - - if (dictionarySize == 0) - { - dictionary = tempDictionary; - dictionarySize = 1; - tempDictionary[0] = vs->TempDictionary[0]; - } - - if (len == kLzmaNeedInitId) - { - { - UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); - UInt32 i; - for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; - rep0 = rep1 = rep2 = rep3 = 1; - state = 0; - globalPos = 0; - distanceLimit = 0; - dictionaryPos = 0; - dictionary[dictionarySize - 1] = 0; - #ifdef _LZMA_IN_CB - RC_INIT; - #else - RC_INIT(inStream, inSize); - #endif - } - len = 0; - } - while(len != 0 && nowPos < outSize) - { - UInt32 pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - len--; - } - if (dictionaryPos == 0) - previousByte = dictionary[dictionarySize - 1]; - else - previousByte = dictionary[dictionaryPos - 1]; - - #else /* if !_LZMA_OUT_READ */ - - int state = 0; - UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; - int len = 0; - const Byte *Buffer; - const Byte *BufferLim; - UInt32 Range; - UInt32 Code; - - #ifndef _LZMA_IN_CB - *inSizeProcessed = 0; - #endif - *outSizeProcessed = 0; - - { - UInt32 i; - UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); - for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; - } - - #ifdef _LZMA_IN_CB - RC_INIT; - #else - RC_INIT(inStream, inSize); - #endif - - #endif /* _LZMA_OUT_READ */ - - while(nowPos < outSize) - { - CProb *prob; - UInt32 bound; - int posState = (int)( - (nowPos - #ifdef _LZMA_OUT_READ - + globalPos - #endif - ) - & posStateMask); - - prob = p + IsMatch + (state << kNumPosBitsMax) + posState; - IfBit0(prob) - { - int symbol = 1; - UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * - ((( - (nowPos - #ifdef _LZMA_OUT_READ - + globalPos - #endif - ) - & literalPosMask) << lc) + (previousByte >> (8 - lc)))); - - if (state >= kNumLitStates) - { - int matchByte; - #ifdef _LZMA_OUT_READ - UInt32 pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - matchByte = dictionary[pos]; - #else - matchByte = outStream[nowPos - rep0]; - #endif - do - { - int bit; - CProb *probLit; - matchByte <<= 1; - bit = (matchByte & 0x100); - probLit = prob + 0x100 + bit + symbol; - RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) - } - while (symbol < 0x100); - } - while (symbol < 0x100) - { - CProb *probLit = prob + symbol; - RC_GET_BIT(probLit, symbol) - } - previousByte = (Byte)symbol; - - outStream[nowPos++] = previousByte; - #ifdef _LZMA_OUT_READ - if (distanceLimit < dictionarySize) - distanceLimit++; - - dictionary[dictionaryPos] = previousByte; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - #endif - if (state < 4) state = 0; - else if (state < 10) state -= 3; - else state -= 6; - } - else - { - UpdateBit1(prob); - prob = p + IsRep + state; - IfBit0(prob) - { - UpdateBit0(prob); - rep3 = rep2; - rep2 = rep1; - rep1 = rep0; - state = state < kNumLitStates ? 0 : 3; - prob = p + LenCoder; - } - else - { - UpdateBit1(prob); - prob = p + IsRepG0 + state; - IfBit0(prob) - { - UpdateBit0(prob); - prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; - IfBit0(prob) - { - #ifdef _LZMA_OUT_READ - UInt32 pos; - #endif - UpdateBit0(prob); - - #ifdef _LZMA_OUT_READ - if (distanceLimit == 0) - #else - if (nowPos == 0) - #endif - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("ERROR: %s, %d\n", __FILE__, __LINE__); -#endif - return LZMA_RESULT_DATA_ERROR; - } - - state = state < kNumLitStates ? 9 : 11; - #ifdef _LZMA_OUT_READ - pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - previousByte = dictionary[pos]; - dictionary[dictionaryPos] = previousByte; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - #else - previousByte = outStream[nowPos - rep0]; - #endif - outStream[nowPos++] = previousByte; - #ifdef _LZMA_OUT_READ - if (distanceLimit < dictionarySize) - distanceLimit++; - #endif - - continue; - } - else - { - UpdateBit1(prob); - } - } - else - { - UInt32 distance; - UpdateBit1(prob); - prob = p + IsRepG1 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep1; - } - else - { - UpdateBit1(prob); - prob = p + IsRepG2 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep2; - } - else - { - UpdateBit1(prob); - distance = rep3; - rep3 = rep2; - } - rep2 = rep1; - } - rep1 = rep0; - rep0 = distance; - } - state = state < kNumLitStates ? 8 : 11; - prob = p + RepLenCoder; - } - { - int numBits, offset; - CProb *probLen = prob + LenChoice; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenLow + (posState << kLenNumLowBits); - offset = 0; - numBits = kLenNumLowBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenChoice2; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenMid + (posState << kLenNumMidBits); - offset = kLenNumLowSymbols; - numBits = kLenNumMidBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenHigh; - offset = kLenNumLowSymbols + kLenNumMidSymbols; - numBits = kLenNumHighBits; - } - } - RangeDecoderBitTreeDecode(probLen, numBits, len); - len += offset; - } - - if (state < 4) - { - int posSlot; - state += kNumLitStates; - prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << - kNumPosSlotBits); - RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); - if (posSlot >= kStartPosModelIndex) - { - int numDirectBits = ((posSlot >> 1) - 1); - rep0 = (2 | ((UInt32)posSlot & 1)); - if (posSlot < kEndPosModelIndex) - { - rep0 <<= numDirectBits; - prob = p + SpecPos + rep0 - posSlot - 1; - } - else - { - numDirectBits -= kNumAlignBits; - do - { - RC_NORMALIZE - Range >>= 1; - rep0 <<= 1; - if (Code >= Range) - { - Code -= Range; - rep0 |= 1; - } - } - while (--numDirectBits != 0); - prob = p + Align; - rep0 <<= kNumAlignBits; - numDirectBits = kNumAlignBits; - } - { - int i = 1; - int mi = 1; - do - { - CProb *prob3 = prob + mi; - RC_GET_BIT2(prob3, mi, ; , rep0 |= i); - i <<= 1; - } - while(--numDirectBits != 0); - } - } - else - rep0 = posSlot; - if (++rep0 == (UInt32)(0)) - { - /* it's for stream version */ - len = kLzmaStreamWasFinishedId; - break; - } - } - - len += kMatchMinLen; - #ifdef _LZMA_OUT_READ - if (rep0 > distanceLimit) - #else - if (rep0 > nowPos) - #endif - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("ERROR: %s, %d\n", __FILE__, __LINE__); -#endif - return LZMA_RESULT_DATA_ERROR; - } - - #ifdef _LZMA_OUT_READ - if (dictionarySize - distanceLimit > (UInt32)len) - distanceLimit += len; - else - distanceLimit = dictionarySize; - #endif - - do - { - #ifdef _LZMA_OUT_READ - UInt32 pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - previousByte = dictionary[pos]; - dictionary[dictionaryPos] = previousByte; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - #else - previousByte = outStream[nowPos - rep0]; - #endif - len--; - outStream[nowPos++] = previousByte; - } - while(len != 0 && nowPos < outSize); - } - } - RC_NORMALIZE; - - #ifdef _LZMA_OUT_READ - vs->Range = Range; - vs->Code = Code; - vs->DictionaryPos = dictionaryPos; - vs->GlobalPos = globalPos + (UInt32)nowPos; - vs->DistanceLimit = distanceLimit; - vs->Reps[0] = rep0; - vs->Reps[1] = rep1; - vs->Reps[2] = rep2; - vs->Reps[3] = rep3; - vs->State = state; - vs->RemainLen = len; - vs->TempDictionary[0] = tempDictionary[0]; - #endif - - #ifdef _LZMA_IN_CB - vs->Buffer = Buffer; - vs->BufferLim = BufferLim; - #else - *inSizeProcessed = (SizeT)(Buffer - inStream); - #endif - *outSizeProcessed = nowPos; - return LZMA_RESULT_OK; -} - -#endif /* CONFIG_LZMA */ diff --git a/package/uboot-ifxmips/files/lib_generic/LzmaWrapper.c b/package/uboot-ifxmips/files/lib_generic/LzmaWrapper.c deleted file mode 100644 index 1ee5c12ba8..0000000000 --- a/package/uboot-ifxmips/files/lib_generic/LzmaWrapper.c +++ /dev/null @@ -1,220 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : LzmaWrapper.c -** PROJECT : bootloader -** MODULES : U-boot -** -** DATE : 2 Nov 2006 -** AUTHOR : Lin Mars -** DESCRIPTION : LZMA decoder support for U-boot 1.1.5 -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Date $Author $Comment -** 2 Nov 2006 Lin Mars init version which derived from LzmaTest.c from -** LZMA v4.43 SDK -** 24 May 2007 Lin Mars Fix issue for multiple lzma_inflate involved -*******************************************************************************/ -#define LZMA_NO_STDIO -#ifndef LZMA_NO_STDIO -#include -#include -#include -#endif - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_LZMA - -#include "LzmaDecode.h" -#include "LzmaWrapper.h" - -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) -static const char *kCantReadMessage = "Can not read from source buffer"; -static const char *kCantAllocateMessage = "Not enough buffer for decompression"; -#endif - -static size_t rpos=0, dpos=0; - -static int MyReadFileAndCheck(unsigned char *src, void *dest, size_t size) -{ - if (size == 0) - return 0; - memcpy(dest, src + rpos, size); - rpos += size; - return 1; -} - -int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len) -{ - /* We use two 32-bit integers to construct 64-bit integer for file size. - You can remove outSizeHigh, if you don't need >= 4GB supporting, - or you can use UInt64 outSize, if your compiler supports 64-bit integers*/ - UInt32 outSize = 0; - UInt32 outSizeHigh = 0; - SizeT outSizeFull; - unsigned char *outStream; - - int waitEOS = 1; - /* waitEOS = 1, if there is no uncompressed size in headers, - so decoder will wait EOS (End of Stream Marker) in compressed stream */ - - SizeT compressedSize; - unsigned char *inStream; - - CLzmaDecoderState state; /* it's about 24-80 bytes structure, if int is 32-bit */ - unsigned char properties[LZMA_PROPERTIES_SIZE]; - - int res; - - rpos=0; dpos=0; - - if (sizeof(UInt32) < 4) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("LZMA decoder needs correct UInt32\n"); -#endif - return LZMA_RESULT_DATA_ERROR; - } - - { - long length=s_len; - if ((long)(SizeT)length != length) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("Too big compressed stream\n"); -#endif - return LZMA_RESULT_DATA_ERROR; - } - compressedSize = (SizeT)(length - (LZMA_PROPERTIES_SIZE + 8)); - } - - /* Read LZMA properties for compressed stream */ - - if (!MyReadFileAndCheck(source, properties, sizeof(properties))) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("%s\n", kCantReadMessage); -#endif - return LZMA_RESULT_DATA_ERROR; - } - - /* Read uncompressed size */ - { - int i; - for (i = 0; i < 8; i++) - { - unsigned char b; - if (!MyReadFileAndCheck(source, &b, 1)) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("%s\n", kCantReadMessage); -#endif - return LZMA_RESULT_DATA_ERROR; - } - if (b != 0xFF) - waitEOS = 0; - if (i < 4) - outSize += (UInt32)(b) << (i * 8); - else - outSizeHigh += (UInt32)(b) << ((i - 4) * 8); - } - - if (waitEOS) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("Stream with EOS marker is not supported"); -#endif - return LZMA_RESULT_DATA_ERROR; - } - outSizeFull = (SizeT)outSize; - if (sizeof(SizeT) >= 8) - outSizeFull |= (((SizeT)outSizeHigh << 16) << 16); - else if (outSizeHigh != 0 || (UInt32)(SizeT)outSize != outSize) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("Too big uncompressed stream"); -#endif - return LZMA_RESULT_DATA_ERROR; - } - } - - /* Decode LZMA properties and allocate memory */ - if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("Incorrect stream properties"); -#endif - return LZMA_RESULT_DATA_ERROR; - } - state.Probs = (CProb *)malloc(LzmaGetNumProbs(&state.Properties) * sizeof(CProb)); - - if (outSizeFull == 0) - outStream = 0; - else - { - if (outSizeFull > d_len) - outStream = 0; - else - outStream = dest; - } - - if (compressedSize == 0) - inStream = 0; - else - { - if ((compressedSize+rpos) > s_len ) - inStream = 0; - else - inStream = source + rpos; - } - - if (state.Probs == 0 - || (outStream == 0 && outSizeFull != 0) - || (inStream == 0 && compressedSize != 0) - ) - { - free(state.Probs); -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("%s\n", kCantAllocateMessage); -#endif - return LZMA_RESULT_DATA_ERROR; - } - - /* Decompress */ - { - SizeT inProcessed; - SizeT outProcessed; - res = LzmaDecode(&state, - inStream, compressedSize, &inProcessed, - outStream, outSizeFull, &outProcessed); - if (res != 0) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("\nDecoding error = %d\n", res); -#endif - res = 1; - } - else - { - *d_len = outProcessed; - } - } - - free(state.Probs); - return res; -} - -#endif /* CONFIG_LZMA */ diff --git a/package/uboot-ifxmips/files/net/ifx_eth.c b/package/uboot-ifxmips/files/net/ifx_eth.c deleted file mode 100644 index 02e72aef3d..0000000000 --- a/package/uboot-ifxmips/files/net/ifx_eth.c +++ /dev/null @@ -1,4 +0,0 @@ - -#define IFX_ETH_INITIALIZE_EXTERN extern int danube_switch_initialize(bd_t *); -#define IFX_ETH_INITIALIZE(bd_t) danube_switch_initialize(bd_t); - diff --git a/package/uboot-ifxmips/patches/001-portability.patch b/package/uboot-ifxmips/patches/001-portability.patch deleted file mode 100644 index 02af987a41..0000000000 --- a/package/uboot-ifxmips/patches/001-portability.patch +++ /dev/null @@ -1,30 +0,0 @@ ---- a/Makefile -+++ b/Makefile -@@ -275,10 +275,10 @@ $(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot - cat nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin - - version: -- @echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \ -- echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \ -- echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \ -- $(TOPDIR)) >> $(VERSION_FILE); \ -+ @printf "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \ -+ printf "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \ -+ printf "$(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \ -+ $(TOPDIR))" >> $(VERSION_FILE); \ - echo "\"" >> $(VERSION_FILE) - - gdbtools: -@@ -1593,10 +1593,10 @@ MPC8540EVAL_66_slave_config: unconf - @mkdir -p $(obj)include - @echo "" >$(obj)include/config.h ; \ - if [ "$(findstring _33_,$@)" ] ; then \ -- echo -n "... 33 MHz PCI" ; \ -+ printf "... 33 MHz PCI" ; \ - else \ - echo "#define CONFIG_SYSCLK_66M" >>$(obj)include/config.h ; \ -- echo -n "... 66 MHz PCI" ; \ -+ printf "... 66 MHz PCI" ; \ - fi ; \ - if [ "$(findstring _slave_,$@)" ] ; then \ - echo "#define CONFIG_PCI_SLAVE" >>$(obj)include/config.h ; \ diff --git a/package/uboot-ifxmips/patches/100-ifx.patch b/package/uboot-ifxmips/patches/100-ifx.patch deleted file mode 100644 index 5360099fb2..0000000000 --- a/package/uboot-ifxmips/patches/100-ifx.patch +++ /dev/null @@ -1,2102 +0,0 @@ ---- a/Makefile -+++ b/Makefile -@@ -24,7 +24,7 @@ - VERSION = 1 - PATCHLEVEL = 1 - SUBLEVEL = 5 --EXTRAVERSION = -+EXTRAVERSION = -IFX-LXDB - U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) - VERSION_FILE = $(obj)include/version_autogenerated.h - -@@ -44,6 +44,25 @@ export HOSTARCH HOSTOS - # Deal with colliding definitions from tcsh etc. - VENDOR= - -+# Default algorithm form compressing u-boot.bin -+ifndef COMPRESS -+COMPRESS=none -+COMPRESS_FILE=$(obj)u-boot.img -+else -+ifeq ($(COMPRESS),lzma) -+COMPRESS_FILE=$(obj)u-boot.limg -+endif -+ifeq ($(COMPRESS),bz2) -+COMPRESS_FILE=$(obj)u-boot.bzimg -+endif -+ifeq ($(COMPRESS),gzip) -+COMPRESS_FILE=$(obj)u-boot.zimg -+endif -+ifeq ($(COMPRESS),none) -+COMPRESS_FILE=$(obj)u-boot.img -+endif -+endif -+ - ######################################################################### - # - # U-boot build supports producing a object files to the separate external -@@ -164,6 +183,11 @@ include $(TOPDIR)/config.mk - # U-Boot objects....order is important (i.e. start must be first) - - OBJS = cpu/$(CPU)/start.o -+OBJS_BOOTSTRAP = cpu/$(CPU)/start_bootstrap.o -+ -+cpu/$(CPU)/start_bootstrap.S: cpu/$(CPU)/start.S -+ ln -s start.S cpu/$(CPU)/start_bootstrap.S -+ - ifeq ($(CPU),i386) - OBJS += cpu/$(CPU)/start16.o - OBJS += cpu/$(CPU)/reset.o -@@ -183,6 +207,7 @@ OBJS += cpu/$(CPU)/cplbhdlr.o cpu/$(CPU) - endif - - OBJS := $(addprefix $(obj),$(OBJS)) -+OBJS_BOOTSTRAP := $(addprefix $(obj),$(OBJS_BOOTSTRAP)) - - LIBS = lib_generic/libgeneric.a - LIBS += board/$(BOARDDIR)/lib$(BOARD).a -@@ -206,15 +231,24 @@ LIBS += common/libcommon.a - LIBS += $(BOARDLIBS) - - LIBS := $(addprefix $(obj),$(LIBS)) -+ -+LIBS_BOOTSTRAP = lib_bootstrap/libbootstrap.a -+LIBS_BOOTSTRAP+= board/$(BOARDDIR)/lib$(BOARD).a -+#LIBS_BOOTSTRAP+= board/ifx/libifx.a -+LIBS_BOOTSTRAP+= cpu/$(CPU)/lib$(CPU).a -+ -+LIBS_BOOTSTRAP := $(addprefix $(obj),$(LIBS_BOOTSTRAP)) -+ - .PHONY : $(LIBS) -+.PHONY : $(obj)lib_bootstrap/libbootstrap.a - - # Add GCC lib - PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc - - # The "tools" are needed early, so put this first - # Don't include stuff already done in $(LIBS) -+ #examples - SUBDIRS = tools \ -- examples \ - post \ - post/cpu - .PHONY : $(SUBDIRS) -@@ -226,14 +260,75 @@ endif - - __OBJS := $(subst $(obj),,$(OBJS)) - __LIBS := $(subst $(obj),,$(LIBS)) -+__LIBS_BOOTSTRAP := $(subst $(obj),,$(LIBS_BOOTSTRAP)) -+ -+#__HEAD_OBJS := $(subst $(obj),,$(HEAD_OBJS)) -+#__HEAD_LIBS := $(subst $(obj),,$(HEAD_LIBS)) - - ######################################################################### - ######################################################################### - - ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) -+#IFX_ALL = $(obj)u-boot.ifx $(obj)head.srec $(obj)head.bin $(obj)head $(obj)head.map $(COMPRESS_FILE) $(obj)u-boot.srec -+IFX_ALL = $(obj)u-boot.srec $(obj)u-boot.ifx $(obj)u-boot.lzimg $(obj)System.map $(obj)bootstrap.bin $(obj)System_bootstrap.map -+IFX_BOOTSTRAP = $(obj)bootstrap.bin - - all: $(ALL) - -+ifx_all: $(IFX_ALL) -+ -+ifx_bootstrap: $(IFX_BOOTSTRAP) -+ -+$(obj)u-boot.ifx: $(obj)bootstrap.bin $(obj)u-boot.lzimg -+ @cat $(obj)bootstrap.bin > $(obj)u-boot.ifx -+ @cat $(obj)u-boot.lzimg >> $(obj)u-boot.ifx -+ -+$(obj)u-boot.lzimg: $(obj)u-boot.bin $(obj)System.map -+ @lzma e $(obj)u-boot.bin $(obj)u-boot.lzma -+ $(obj)tools/mkimage -A mips -T firmware -C lzma \ -+ -a 0x$(shell grep "T _start" $(obj)System.map | awk '{ printf "%s", $$1 }') \ -+ -e 0x$(shell grep "T _start" $(obj)System.map | awk '{ printf "%s", $$1 }') \ -+ -n 'u-boot image' -d $(obj)u-boot.lzma $@ -+ -+$(obj)ld_uboot.img: $(obj)u-boot.ifx $(obj)u-boot.lzimg $(obj)bootstrap.bin -+ @ cp -f $(obj)u-boot.ifx $(obj)u-boot.bin -+ @ ./mkbootimg.incaip2 $(obj)ld_uboot.img < ld_uboot.conf -+ -+$(obj)u-boot.zimg: $(obj)u-boot.bin $(obj)System.map -+ gzip $(obj)u-boot.bin -+ $(obj)tools/mkimage -A $(ARCH) -T firmware -C gzip \ -+ -a 0x$(shell grep "T _start" $(obj)System.map | awk '{ printf "%s", $$1 }') \ -+ -e 0x$(shell grep "T _start" $(obj)System.map | awk '{ printf "%s", $$1 }') \ -+ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ -+ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -+ -d u-boot.gz $@ -+ -+$(obj)u-boot.bzimg: $(obj)u-boot.bin $(obj)System.map -+ bzip $(obj)u-boot.bin -+ $(obj)tools/mkimage -A $(ARCH) -T firmware -C bzip2 \ -+ -a 0x$(shell grep "T _start" $(obj)System.map | awk '{ printf "%s", $$1 }') \ -+ -e 0x$(shell grep "T _start" $(obj)System.map | awk '{ printf "%s", $$1 }') \ -+ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ -+ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -+ -d u-boot.bz2 $@ -+ -+$(obj)u-boot.limg: $(obj)u-boot.bin $(obj)System.map -+ @lzma e $(obj)u-boot.bin $(obj)u-boot.lzma -+ $(obj)tools/mkimage -A $(ARCH) -T firmware -C lzma \ -+ -a 0x$(shell grep "T _start" $(obj)System.map | awk '{ printf "%s", $$1 }') \ -+ -e 0x$(shell grep "T _start" $(obj)System.map | awk '{ printf "%s", $$1 }') \ -+ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ -+ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -+ -d u-boot.lzma $@ -+ -+$(obj)u-boot.img: $(obj)u-boot.bin $(obj)System.map -+ $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ -+ -a 0x$(shell grep "T _start" $(obj)System.map | awk '{ printf "%s", $$1 }') \ -+ -e 0x$(shell grep "T _start" $(obj)System.map | awk '{ printf "%s", $$1 }') \ -+ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ -+ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -+ -d u-boot.bin $@ -+ - $(obj)u-boot.hex: $(obj)u-boot - $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ - -@@ -243,28 +338,33 @@ $(obj)u-boot.srec: $(obj)u-boot - $(obj)u-boot.bin: $(obj)u-boot - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - --$(obj)u-boot.img: $(obj)u-boot.bin -- ./tools/mkimage -A $(ARCH) -T firmware -C none \ -- -a $(TEXT_BASE) -e 0 \ -- -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ -- sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -- -d $< $@ -- - $(obj)u-boot.dis: $(obj)u-boot - $(OBJDUMP) -d $< > $@ - --$(obj)u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT) -+$(obj)u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT) - UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ - cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ - --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ - -Map u-boot.map -o u-boot - -+$(obj)bootstrap.bin: $(obj)bootstrap -+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -+ -+$(obj)bootstrap : depend version $(SUBDIRS) $(OBJS_BOOTSTRAP) $(LIBS_BOOTSTRAP) $(LDSCRIPT_BOOTSTRAP) -+ UNDEF_SYM=`$(OBJDUMP) -x $(LIBS_BOOTSTRAP) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\ -+ $(LD) $(LDFLAGS_BOOTSTRAP) $$UNDEF_SYM $(OBJS_BOOTSTRAP) \ -+ --start-group $(__LIBS_BOOTSTRAP) --end-group $(PLATFORM_LIBS) \ -+ -Map bootstrap.map -o bootstrap -+ - $(OBJS): - $(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@)) - - $(LIBS): - $(MAKE) -C $(dir $(subst $(obj),,$@)) - -+$(obj)lib_bootstrap/libbootstrap.a: -+ $(MAKE) -C $(dir $(subst $(obj),,$@)) -+ - $(SUBDIRS): - $(MAKE) -C $@ all - -@@ -310,7 +410,12 @@ etags: - $(obj)System.map: $(obj)u-boot - @$(NM) $< | \ - grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ -- sort > $(obj)System.map -+ sort > $@ -+ -+$(obj)System_bootstrap.map: $(obj)bootstrap -+ @$(NM) $< | \ -+ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ -+ sort > $@ - - ######################################################################### - else -@@ -2032,7 +2137,20 @@ sc520_spunk_rel_config : unconfig - # MIPS - #======================================================================== - ######################################################################### --## MIPS32 4Kc -+## Infineon MIPS generic u-boot config -+######################################################################### -+danube_config: unconfig -+ @$(MKCONFIG) $(@:_config=) mips mips danube ifx danube -+ -+amazon_config: unconfig -+ @$(MKCONFIG) $(@:_config=) mips mips amazon -+ -+ -+incaip2_config: unconfig -+ @$(MKCONFIG) $(@:_config=) mips mips incaip2 -+ -+######################################################################### -+## MIPS32 4kc - ######################################################################### - - xtract_incaip = $(subst _100MHz,,$(subst _133MHz,,$(subst _150MHz,,$(subst _config,,$1)))) -@@ -2254,7 +2372,7 @@ clobber: clean - | xargs -0 rm -f - rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS $(obj)include/version_autogenerated.h - rm -fr $(obj)*.*~ -- rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) -+ rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) $(IFX_ALL) - rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c - rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c - rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm ---- a/common/cmd_bootm.c -+++ b/common/cmd_bootm.c -@@ -31,6 +31,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -79,6 +80,8 @@ DECLARE_GLOBAL_DATA_PTR; - # define CHUNKSZ (64 * 1024) - #endif - -+#ifndef CFG_HEAD_CODE -+ - int gunzip (void *, int, unsigned char *, unsigned long *); - - static void *zalloc(void *, unsigned, unsigned); -@@ -341,6 +344,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag - #endif /* CONFIG_HW_WATCHDOG || CONFIG_WATCHDOG */ - } - break; -+#ifndef CONFIG_REMOVE_GZIP - case IH_COMP_GZIP: - printf (" Uncompressing %s ... ", name); - if (gunzip ((void *)ntohl(hdr->ih_load), unc_len, -@@ -350,6 +354,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag - do_reset (cmdtp, flag, argc, argv); - } - break; -+#endif /* CONFIG_REMOVE_GZIP */ - #ifdef CONFIG_BZIP2 - case IH_COMP_BZIP2: - printf (" Uncompressing %s ... ", name); -@@ -369,6 +374,18 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag - } - break; - #endif /* CONFIG_BZIP2 */ -+#ifdef CONFIG_LZMA -+ case IH_COMP_LZMA: -+ printf (" Uncompressing %s ... ", name); -+ i = lzma_inflate ((unsigned char *)data, len, (unsigned char*)ntohl(hdr->ih_load), &unc_len); -+ if (i != LZMA_RESULT_OK) { -+ printf ("LZMA ERROR %d - must RESET board to recover\n", i); -+ SHOW_BOOT_PROGRESS (-6); -+ udelay(100000); -+ do_reset (cmdtp, flag, argc, argv); -+ } -+ break; -+#endif /* CONFIG_LZMA */ - default: - if (iflag) - enable_interrupts(); -@@ -1176,6 +1193,8 @@ U_BOOT_CMD( - ); - #endif /* CFG_CMD_IMLS */ - -+#endif /* ! CFG_HEAD_CODE */ -+ - void - print_image_hdr (image_header_t *hdr) - { -@@ -1270,12 +1289,15 @@ print_type (image_header_t *hdr) - case IH_COMP_NONE: comp = "uncompressed"; break; - case IH_COMP_GZIP: comp = "gzip compressed"; break; - case IH_COMP_BZIP2: comp = "bzip2 compressed"; break; -+ case IH_COMP_LZMA: comp = "lzma compressed"; break; - default: comp = "unknown compression"; break; - } - - printf ("%s %s %s (%s)", arch, os, type, comp); - } - -+#ifndef CFG_HEAD_CODE -+ - #define ZALLOC_ALIGNMENT 16 - - static void *zalloc(void *x, unsigned items, unsigned size) -@@ -1427,3 +1449,5 @@ do_bootm_lynxkdi (cmd_tbl_t *cmdtp, int - } - - #endif /* CONFIG_LYNXKDI */ -+ -+#endif /* ! CFG_HEAD_CODE */ ---- a/common/cmd_flash.c -+++ b/common/cmd_flash.c -@@ -196,9 +196,17 @@ addr_spec(char *arg1, char *arg2, ulong - } - - static int --flash_fill_sect_ranges (ulong addr_first, ulong addr_last, -- int *s_first, int *s_last, -- int *s_count ) -+flash_fill_sect_ranges( -+ ulong *addr_first_sect_start, -+ ulong addr_first, -+ ulong *addr_last_sect_end, -+ ulong addr_last, -+ int *s_first, -+ int *s_last, -+ int *bPartialStart, -+ int *bPartialEnd, -+ int *s_count, -+ unsigned int bPartialErase) - { - flash_info_t *info; - ulong bank; -@@ -211,9 +219,7 @@ flash_fill_sect_ranges (ulong addr_first - s_last [bank] = -1; /* last sector to erase */ - } - -- for (bank=0,info=&flash_info[0]; -- (bank < CFG_MAX_FLASH_BANKS) && (addr_first <= addr_last); -- ++bank, ++info) { -+ for (bank=0, info=&flash_info[0]; (bank < CFG_MAX_FLASH_BANKS) && (addr_first <= addr_last); ++bank, ++info) { - ulong b_end; - int sect; - short s_end; -@@ -225,7 +231,6 @@ flash_fill_sect_ranges (ulong addr_first - b_end = info->start[0] + info->size - 1; /* bank end addr */ - s_end = info->sector_count - 1; /* last sector */ - -- - for (sect=0; sect < info->sector_count; ++sect) { - ulong end; /* last address in current sect */ - -@@ -238,11 +243,21 @@ flash_fill_sect_ranges (ulong addr_first - - if (addr_first == info->start[sect]) { - s_first[bank] = sect; -+ } else if (addr_first > info->start[sect] && addr_first <= end && bPartialErase) { -+ *addr_first_sect_start = info->start[sect]; -+ s_first[bank] = sect; -+ *bPartialStart = 1; - } -+ - if (addr_last == end) { - s_last[bank] = sect; -+ } else if (addr_last >= info->start[sect] && addr_last < end && bPartialErase) { -+ *addr_last_sect_end = end; -+ s_last[bank] = sect; -+ *bPartialEnd = 1; - } - } -+ - if (s_first[bank] >= 0) { - if (s_last[bank] < 0) { - if (addr_last > b_end) { -@@ -316,6 +331,8 @@ int do_flerase (cmd_tbl_t *cmdtp, int fl - struct part_info *part; - u8 dev_type, dev_num, pnum; - #endif -+ unsigned int bPartialErase = 0; -+ - int rcode = 0; - - if (argc < 2) { -@@ -369,7 +386,7 @@ int do_flerase (cmd_tbl_t *cmdtp, int fl - } - #endif - -- if (argc != 3) { -+ if (argc != 4) { - printf ("Usage:\n%s\n", cmdtp->usage); - return 1; - } -@@ -397,11 +414,117 @@ int do_flerase (cmd_tbl_t *cmdtp, int fl - return 1; - } - -- rcode = flash_sect_erase(addr_first, addr_last); -+ printf ("Erase Flash from 0x%08lx to 0x%08lx\n", addr_first, addr_last); -+ if(argc == 4) { -+ bPartialErase = simple_strtoul(argv[3], NULL, 10); -+ } -+ -+ rcode = flash_sect_erase(addr_first, addr_last, bPartialErase); - return rcode; - } - --int flash_sect_erase (ulong addr_first, ulong addr_last) -+int flerase_Partial( -+ ulong addr_first_sect_start, -+ ulong addr_first, -+ ulong addr_last_sect_end, -+ ulong addr_last, -+ flash_info_t *info, -+ int first_sect, -+ int last_sect, -+ int bFirstPartial, -+ int bLastPartial) { -+ unsigned int firstMemLen = 0; -+ unsigned int lastMemLen = 0; -+ unsigned int sectMemLen = 0; -+ uchar *pSavedFirstMem = NULL; -+ uchar *pSavedLastMem = NULL; -+ uchar *pSavedSectMem = NULL; -+ int bSectPartial = 0; -+ int rt_code = 0; -+ -+ debug("%s ... 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%p, %d, %d, %d, %d\n", __FUNCTION__, addr_first_sect_start, addr_first, addr_last_sect_end, addr_last, info, first_sect, last_sect, bFirstPartial, bLastPartial); -+ -+ if (bFirstPartial && bLastPartial && (first_sect == last_sect)) -+ { -+ ulong b_end = info->start[0] + info->size - 1; -+ ulong end = (first_sect == (info->sector_count - 1)) ? b_end : info->start[first_sect + 1] - 1; -+ sectMemLen = end - info->start[first_sect] + 1; -+ pSavedSectMem = (uchar *)calloc(sectMemLen, sizeof(char)); -+ if (pSavedSectMem == NULL) -+ { -+ debug("calloc %u FAILED\n", sectMemLen); -+ rt_code = 1; -+ goto ret; -+ } -+ memset(pSavedSectMem, 0xff, sectMemLen); -+ bSectPartial = 1; -+ memcpy(pSavedSectMem, (uchar *)addr_first_sect_start, addr_first - addr_first_sect_start); -+ memcpy(pSavedSectMem + (addr_last - info->start[first_sect]) + 1, addr_last + 1, end - addr_last); -+ } -+ else -+ { -+ if (bFirstPartial){ -+ firstMemLen = addr_first - addr_first_sect_start + 1; -+ pSavedFirstMem = (uchar *)calloc(firstMemLen,sizeof(char)); -+ memcpy(pSavedFirstMem,(uchar *)addr_first_sect_start,firstMemLen - 1); -+ } -+ if (bLastPartial){ -+ lastMemLen = addr_last_sect_end - addr_last + 1; -+ pSavedLastMem = (uchar *)calloc(lastMemLen,sizeof(char)); -+ memcpy(pSavedLastMem,(uchar *)addr_last + 1,lastMemLen - 1); -+ } -+ } -+ -+ if (bFirstPartial){ -+ if(flash_erase (info, first_sect, first_sect)) { -+ printf("%s ... Couldn't erase sector %d\n", __FUNCTION__, first_sect); -+ rt_code = 1; -+ goto ret; -+ } -+ debug("%s ... erase sector %d done!\n", __FUNCTION__, first_sect); -+ } -+ -+ if (bLastPartial && first_sect != last_sect){ -+ if(flash_erase (info, last_sect, last_sect)) { -+ printf("%s ... Couldn't erase sector %d\n", __FUNCTION__, last_sect); -+ rt_code = 1; -+ goto ret; -+ } -+ debug("%s ... erase sector %d done!\n", __FUNCTION__, last_sect); -+ } -+ -+ if (bFirstPartial && bLastPartial && (first_sect == last_sect)) -+ { -+ flash_write(pSavedSectMem, (uchar *)addr_first_sect_start, sectMemLen); -+ debug("flash_write from 0x%08x with len %u\n", addr_first_sect_start, sectMemLen); -+ } -+ else -+ { -+ if (bFirstPartial){ -+ if(flash_write(pSavedFirstMem,(uchar *)addr_first_sect_start,firstMemLen - 1)) { -+ printf("%s ... Couldn't write at 0x%08lx length %d\n", __FUNCTION__, addr_first_sect_start,firstMemLen - 1); -+ rt_code = 1; -+ goto ret; -+ } -+ } -+ if (bLastPartial){ -+ if(flash_write(pSavedLastMem,(uchar *)addr_last + 1,lastMemLen - 1)) { -+ printf("%s ... Couldn't write at 0x%08lx length %d\n", __FUNCTION__, addr_last, lastMemLen - 1); -+ rt_code = 1; -+ } -+ } -+ } -+ret: -+ if (bFirstPartial) -+ free(pSavedFirstMem); -+ if (bLastPartial) -+ free(pSavedLastMem); -+ if (bSectPartial) -+ free(pSavedSectMem); -+ return rt_code; -+} -+ -+int flash_sect_erase (ulong addr_first, ulong addr_last, unsigned int bPartialErase) - { - flash_info_t *info; - ulong bank; -@@ -413,27 +536,66 @@ int flash_sect_erase (ulong addr_first, - int erased = 0; - int planned; - int rcode = 0; -- -- rcode = flash_fill_sect_ranges (addr_first, addr_last, -- s_first, s_last, &planned ); -+ int bPartialStart = 0; // Start sector has to be erased partially -+ int bPartialEnd = 0; // End sector has to be erased partially -+ ulong addr_first_sect_start = 0;// Sector start address of location addr_start -+ ulong addr_last_sect_end = 0; // Sector end address of location addr_last -+ -+ rcode = flash_fill_sect_ranges ( -+ &addr_first_sect_start, -+ addr_first, -+ &addr_last_sect_end, -+ addr_last, -+ s_first, -+ s_last, -+ &bPartialStart, -+ &bPartialEnd, -+ &planned, -+ bPartialErase ); - - if (planned && (rcode == 0)) { -- for (bank=0,info=&flash_info[0]; -- (bank < CFG_MAX_FLASH_BANKS) && (rcode == 0); -- ++bank, ++info) { -+ for (bank=0, info=&flash_info[0]; (bank < CFG_MAX_FLASH_BANKS) && (rcode == 0); ++bank, ++info) { -+ ulong b_end = info->start[0] + info->size - 1; /* bank end addr */ - if (s_first[bank]>=0) { -- erased += s_last[bank] - s_first[bank] + 1; -- debug ("Erase Flash from 0x%08lx to 0x%08lx " -- "in Bank # %ld ", -- info->start[s_first[bank]], -- (s_last[bank] == info->sector_count) ? -- info->start[0] + info->size - 1: -- info->start[s_last[bank]+1] - 1, -- bank+1); -- rcode = flash_erase (info, s_first[bank], s_last[bank]); -+ if(bPartialErase) { -+ rcode = flerase_Partial( -+ addr_first_sect_start, -+ addr_first, -+ addr_last_sect_end, -+ addr_last, -+ info, -+ s_first[bank], -+ s_last[bank], -+ bPartialStart, -+ bPartialEnd); -+ } -+ -+ //Erase full sectores -+ if (bPartialStart) -+ s_first[bank] += 1; -+ if (bPartialEnd) -+ s_last[bank] -= 1; -+ if (s_last[bank] >= s_first[bank]) { -+ erased += s_last[bank] - s_first[bank] + 1; -+ debug ("Erase Flash from 0x%08lx to 0x%08lx in Bank # %ld ", -+ info->start[s_first[bank]], -+ (s_last[bank] == info->sector_count) ? -+ info->start[0] + info->size - 1: -+ info->start[s_last[bank]+1] - 1, -+ bank + 1); -+ rcode = flash_erase (info, s_first[bank], s_last[bank]); -+ } - } - } -- printf ("Erased %d sectors\n", erased); -+ -+ if (erased && !bPartialErase) { -+ printf ("Erased %d sectors\n", erased); -+ } else if (bPartialErase){ -+ printf ("Partial erased from 0x%08lx to 0x%08lx\n", addr_first, addr_last); -+ } else { -+ printf ("Error: start and/or end address not on sector boundary\n"); -+ rcode = 1; -+ } - } else if (rcode == 0) { - puts ("Error: start and/or end address" - " not on sector boundary\n"); -@@ -629,8 +791,22 @@ int flash_sect_protect (int p, ulong add - int protected, i; - int planned; - int rcode; -- -- rcode = flash_fill_sect_ranges( addr_first, addr_last, s_first, s_last, &planned ); -+ int bPartialStart = 0; // Start sector has to be erased partially -+ int bPartialEnd = 0; // End sector has to be erased partially -+ ulong addr_first_sect_start = 0;// Sector start address of location addr_start -+ ulong addr_last_sect_end = 0; // Sector end address of location addr_last -+ -+ rcode = flash_fill_sect_ranges ( -+ &addr_first_sect_start, -+ addr_first, -+ &addr_last_sect_end, -+ addr_last, -+ s_first, -+ s_last, -+ &bPartialStart, -+ &bPartialEnd, -+ &planned, -+ 1 ); - - protected = 0; - -@@ -690,7 +866,7 @@ U_BOOT_CMD( - ); - - U_BOOT_CMD( -- erase, 3, 1, do_flerase, -+ erase, 4, 1, do_flerase, - "erase - erase FLASH memory\n", - "start end\n" - " - erase FLASH from addr 'start' to addr 'end'\n" ---- a/common/cmd_nvedit.c -+++ b/common/cmd_nvedit.c -@@ -540,8 +540,19 @@ int do_saveenv (cmd_tbl_t *cmdtp, int fl - extern char * env_name_spec; - - printf ("Saving Environment to %s...\n", env_name_spec); -- -+#if 1 -+ if(saveenv() == 0) { -+#ifdef UBOOT_ENV_COPY -+ saveenv_copy(); -+#else -+ ; -+#endif //UBOOT_ENV_COPY -+ } else -+ return 1; -+ return 0; -+#else - return (saveenv() ? 1 : 0); -+#endif - } - - ---- a/common/console.c -+++ b/common/console.c -@@ -324,7 +324,7 @@ inline void dbg(const char *fmt, ...) - #endif - - /** U-Boot INIT FUNCTIONS *************************************************/ -- -+#ifndef CFG_HEAD_CODE - int console_assign (int file, char *devname) - { - int flag, i; -@@ -357,7 +357,7 @@ int console_assign (int file, char *devn - - return -1; - } -- -+#endif //CFG_HEAD_CODE - /* Called before relocation - use serial functions */ - int console_init_f (void) - { -@@ -392,6 +392,7 @@ device_t *search_device (int flags, char - } - #endif /* CFG_CONSOLE_IS_IN_ENV || CONFIG_SPLASH_SCREEN */ - -+#ifndef CFG_HEAD_CODE - #ifdef CFG_CONSOLE_IS_IN_ENV - /* Called after the relocation - use desired console functions */ - int console_init_r (void) -@@ -570,3 +571,4 @@ int console_init_r (void) - } - - #endif /* CFG_CONSOLE_IS_IN_ENV */ -+#endif //CFG_HEAD_CODE ---- a/common/devices.c -+++ b/common/devices.c -@@ -39,6 +39,7 @@ DECLARE_GLOBAL_DATA_PTR; - list_t devlist = 0; - device_t *stdio_devices[] = { NULL, NULL, NULL }; - char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" }; -+#ifndef CFG_HEAD_CODE - - #if defined(CONFIG_SPLASH_SCREEN) && !defined(CFG_DEVICE_NULLDEV) - #define CFG_DEVICE_NULLDEV 1 -@@ -214,3 +215,5 @@ int devices_done (void) - - return 0; - } -+#endif //CFG_HEAD_CODE -+ ---- a/common/env_common.c -+++ b/common/env_common.c -@@ -219,7 +219,9 @@ void env_relocate (void) - * We must allocate a buffer for the environment - */ - env_ptr = (env_t *)malloc (CFG_ENV_SIZE); -- DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr); -+ if(!env_ptr) -+ DEBUGF ("malloc env_ptr error!!\n"); -+ DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__, __LINE__, env_ptr); - #endif - - /* -@@ -227,6 +229,10 @@ void env_relocate (void) - */ - env_get_char = env_get_char_memory; - -+ //leejack -+ DEBUGF ("%s[%d] gd->env_valid=%d\n", __FUNCTION__, __LINE__, gd->env_valid); -+ DEBUGF ("%s[%d] CFG_ENV_SIZE=%d\n", __FUNCTION__, __LINE__, CFG_ENV_SIZE); -+ - if (gd->env_valid == 0) { - #if defined(CONFIG_GTH) || defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */ - puts ("Using default environment\n\n"); -@@ -242,18 +248,17 @@ void env_relocate (void) - } - - memset (env_ptr, 0, sizeof(env_t)); -- memcpy (env_ptr->data, -- default_environment, -- sizeof(default_environment)); -+ memcpy (env_ptr->data, default_environment, sizeof(default_environment)); -+ - #ifdef CFG_REDUNDAND_ENVIRONMENT - env_ptr->flags = 0xFF; - #endif - env_crc_update (); - gd->env_valid = 1; -- } -- else { -+ } else { - env_relocate_spec (); - } -+ - gd->env_addr = (ulong)&(env_ptr->data); - - #ifdef CONFIG_AMIGAONEG3SE ---- a/common/env_flash.c -+++ b/common/env_flash.c -@@ -66,7 +66,6 @@ static env_t *flash_addr = (env_t *)CFG_ - #endif - - #else /* ! ENV_IS_EMBEDDED */ -- - env_t *env_ptr = (env_t *)CFG_ENV_ADDR; - #ifdef CMD_SAVEENV - static env_t *flash_addr = (env_t *)CFG_ENV_ADDR; -@@ -201,6 +200,7 @@ int saveenv(void) - debug (" %08lX ... %08lX ...", - (ulong)&(flash_addr_new->data), - sizeof(env_ptr->data)+(ulong)&(flash_addr_new->data)); -+ - if ((rc = flash_write((char *)env_ptr->data, - (ulong)&(flash_addr_new->data), - sizeof(env_ptr->data))) || -@@ -256,7 +256,6 @@ Done: - #endif /* CMD_SAVEENV */ - - #else /* ! CFG_ENV_ADDR_REDUND */ -- - int env_init(void) - { - #ifdef CONFIG_OMAP2420H4 -@@ -280,6 +279,52 @@ bad_flash: - - #ifdef CMD_SAVEENV - -+#ifdef UBOOT_ENV_COPY -+int saveenv_copy(void) { -+ uchar *env_buffer = (char *)env_ptr; -+ char *kernel_addr; -+ char *rootfs_addr; -+ char *rootfs_size; -+ ulong start_addr,end_addr,rootfs_end_addr; -+ ulong flash_start; -+ -+ kernel_addr = getenv("f_kernel_addr"); -+ end_addr = simple_strtoul(kernel_addr,NULL,16) - 1; -+ start_addr = end_addr - CFG_ENV_SIZE - sizeof(UBOOTCONFIG_COPY_HEADER) + 1; -+ -+ rootfs_addr = getenv("f_rootfs_addr"); -+ rootfs_size = getenv("f_rootfs_size"); -+ rootfs_end_addr = simple_strtoul(rootfs_addr,NULL,16) + simple_strtoul(rootfs_size,NULL,16); -+ -+ if(rootfs_end_addr >= start_addr) -+ { -+ printf("Can not copy the environment at 0x%08lx as no space left.\nf_kernel_addr = 0x%08lx while rootfs_end_addr = 0x%08lx\n",start_addr,end_addr,rootfs_end_addr); -+ return 1; -+ } -+ -+ debug ("Protect off %08lX ... %08lX\n", (ulong)rootfs_end_addr, end_addr); -+ if (flash_sect_protect (0, rootfs_end_addr, end_addr)) -+ return 1; -+ -+ //delete the old environment copy, if found -+ flash_start = rootfs_end_addr; -+ while(flash_start + sizeof(UBOOTCONFIG_COPY_HEADER) + ENV_SIZE < end_addr) -+ { -+ if(strncmp((char *)flash_start,UBOOTCONFIG_COPY_HEADER,sizeof(UBOOTCONFIG_COPY_HEADER)) == 0) -+ { -+ flash_sect_erase(flash_start,flash_start + sizeof(UBOOTCONFIG_COPY_HEADER),1); -+ } -+ flash_start += 1; -+ } -+ flash_sect_erase(start_addr,end_addr,1); -+ flash_write(UBOOTCONFIG_COPY_HEADER,start_addr,sizeof(UBOOTCONFIG_COPY_HEADER)); -+ flash_write(env_buffer,start_addr + sizeof(UBOOTCONFIG_COPY_HEADER), CFG_ENV_SIZE); -+ flash_sect_protect (1, rootfs_end_addr, end_addr); -+ printf("saved copy of the env at 0x%08lx\n",start_addr); -+ return 0; -+} -+#endif //UBOOT_ENV_COPY -+ - int saveenv(void) - { - int len, rc; -@@ -331,7 +376,7 @@ int saveenv(void) - return 1; - - puts ("Erasing Flash..."); -- if (flash_sect_erase (flash_sect_addr, end_addr)) -+ if (flash_sect_erase (flash_sect_addr, end_addr, 1)) - return 1; - - puts ("Writing to Flash... "); ---- a/config.mk -+++ b/config.mk -@@ -127,10 +127,15 @@ OBJCOPY = $(CROSS_COMPILE)objcopy - OBJDUMP = $(CROSS_COMPILE)objdump - RANLIB = $(CROSS_COMPILE)RANLIB - -+ifneq (,$(findstring s,$(MAKEFLAGS))) -+ARFLAGS = cr -+else - ARFLAGS = crv -+endif - RELFLAGS= $(PLATFORM_RELFLAGS) - DBGFLAGS= -g # -DDEBUG - OPTFLAGS= -Os #-fomit-frame-pointer -+OWRT_FLAGS?= - ifndef LDSCRIPT - #LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds.debug - ifeq ($(CONFIG_NAND_U_BOOT),y) -@@ -139,12 +144,15 @@ else - LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot.lds - endif - endif -+ -+LDSCRIPT_BOOTSTRAP := $(TOPDIR)/board/$(BOARDDIR)/u-boot-bootstrap.lds -+ - OBJCFLAGS += --gap-fill=0xff - - gccincdir := $(shell $(CC) -print-file-name=include) - --CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \ -- -D__KERNEL__ -DTEXT_BASE=$(TEXT_BASE) \ -+CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) $(OWRT_FLAGS) \ -+ -D__KERNEL__ -DUBOOT_RAM_TEXT_BASE=$(UBOOT_RAM_TEXT_BASE) \ - - ifneq ($(OBJTREE),$(SRCTREE)) - CPPFLAGS += -I$(OBJTREE)/include2 -I$(OBJTREE)/include -@@ -180,7 +188,8 @@ endif - - AFLAGS := $(AFLAGS_DEBUG) -D__ASSEMBLY__ $(CPPFLAGS) - --LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) -+LDFLAGS += -Bstatic -T $(LDSCRIPT) -Ttext $(UBOOT_RAM_TEXT_BASE) $(PLATFORM_LDFLAGS) -+LDFLAGS_BOOTSTRAP += -Bstatic -T $(LDSCRIPT_BOOTSTRAP) -Ttext $(BOOTSTRAP_TEXT_BASE) $(PLATFORM_LDFLAGS) - - # Location of a usable BFD library, where we define "usable" as - # "built for ${HOST}, supports ${TARGET}". Sensible values are -@@ -214,12 +223,19 @@ endif - export CONFIG_SHELL HPATH HOSTCC HOSTCFLAGS CROSS_COMPILE \ - AS LD CC CPP AR NM STRIP OBJCOPY OBJDUMP \ - MAKE --export TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS -+export UBOOT_RAM_TEXT_BASE BOOTSTRAP_TEXT_BASE PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS - - ######################################################################### - - ifndef REMOTE_BUILD - -+%_bootstrap.s: %_bootstrap.S -+ $(CPP) $(AFLAGS) -DCFG_BOOTSTRAP_CODE -o $@ $< -+%_bootstrap.o: %_bootstrap.S -+ $(CC) $(AFLAGS) -DCFG_BOOTSTRAP_CODE -c -o $@ $< -+%_bootstrap.o: %_bootstrap.c -+ $(CC) $(CFLAGS) -DCFG_BOOTSTRAP_CODE -c -o $@ $< -+ - %.s: %.S - $(CPP) $(AFLAGS) -o $@ $< - %.o: %.S -@@ -229,12 +245,20 @@ ifndef REMOTE_BUILD - - else - -+$(obj)%_bootstrap.s: %_bootstrap.S -+ $(CPP) $(AFLAGS) -DCFG_BOOTSTRAP_CODE -o $@ $< -+$(obj)%_bootstrap.o: %_bootstrap.S -+ $(CC) $(AFLAGS) -DCFG_BOOTSTRAP_CODE -c -o $@ $< -+$(obj)%_bootstrap.o: %_bootstrap.c -+ $(CC) $(CFLAGS) -DCFG_BOOTSTRAP_CODE -c -o $@ $< -+ - $(obj)%.s: %.S - $(CPP) $(AFLAGS) -o $@ $< - $(obj)%.o: %.S - $(CC) $(AFLAGS) -c -o $@ $< - $(obj)%.o: %.c - $(CC) $(CFLAGS) -c -o $@ $< -+ - endif - - ######################################################################### ---- a/drivers/Makefile -+++ b/drivers/Makefile -@@ -50,7 +50,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o \ - videomodes.o w83c553f.o \ - ks8695eth.o \ - pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ -- rpx_pcmcia.o -+ rpx_pcmcia.o ifx_sw.o - - SRCS := $(COBJS:.o=.c) - OBJS := $(addprefix $(obj),$(COBJS)) ---- a/include/asm-mips/mipsregs.h -+++ b/include/asm-mips/mipsregs.h -@@ -48,6 +48,7 @@ - #define CP0_CAUSE $13 - #define CP0_EPC $14 - #define CP0_PRID $15 -+#define CP0_EBASE $15,1 - #define CP0_CONFIG $16 - #define CP0_LLADDR $17 - #define CP0_WATCHLO $18 -@@ -330,11 +331,32 @@ __BUILD_SET_CP0(config,CP0_CONFIG) - # define KSU_USER 0x00000010 - # define KSU_SUPERVISOR 0x00000008 - # define KSU_KERNEL 0x00000000 -+#ifdef CONFIG_DANUBE /* MIPS 24KE */ -+/* bits 5 & 6 & 7: reserved */ -+/* bits 8~15: IM0~7 */ -+/* bits 16: reserved */ -+#define ST0_CEE 0x00020000 -+/* bits 18: always 0 */ -+#define ST0_NMI 0x00080000 -+#define ST0_SR 0x00100000 -+#define ST0_TS 0x00200000 -+#define ST0_BEV 0x00400000 -+/* bits 23: reserved */ -+#define ST0_MX 0x01000000 -+#define ST0_RE 0x02000000 -+#define ST0_FR 0x04000000 -+#define ST0_RP 0x08000000 -+#define ST0_CU0 0x10000000 -+#define ST0_CU1 0x20000000 -+#define ST0_CU2 0x40000000 -+#define ST0_CU3 0x80000000 -+#else - #define ST0_UX 0x00000020 - #define ST0_SX 0x00000040 - #define ST0_KX 0x00000080 - #define ST0_DE 0x00010000 - #define ST0_CE 0x00020000 -+#endif - - /* - * Bitfields in the R[23]000 cp0 status register. -@@ -471,6 +493,14 @@ __BUILD_SET_CP0(config,CP0_CONFIG) - #define CAUSEF_BD (1 << 31) - - /* -+ * Bits in the coprocessor 0 EBase register -+ */ -+#define EBASEB_CPUNUM 0 -+#define EBASEF_CPUNUM (0x3ff << EBASEB_CPUNUM) -+#define EBASEB_EXPBASE 12 -+#define EBASEF_EXPBASE (0x3ffff << EBASEB_EXPBASE) -+ -+/* - * Bits in the coprozessor 0 config register. - */ - #define CONF_CM_CACHABLE_NO_WA 0 -@@ -544,4 +574,10 @@ __BUILD_SET_CP0(config,CP0_CONFIG) - #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ - #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ - -+/* -+ * Bits in ErrCtl register -+ */ -+#define ECCB_WST 29 -+#define ECCF_WST (0x1 << ECCB_WST) -+ - #endif /* _ASM_MIPSREGS_H */ ---- a/include/cmd_confdefs.h -+++ b/include/cmd_confdefs.h -@@ -94,6 +94,7 @@ - #define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */ - #define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */ - #define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */ -+#define CFG_CMD_DHRYSTONE 0x8000000000000000ULL /* Dhrystone benchmark support */ - - #define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */ - -@@ -141,6 +142,7 @@ - CFG_CMD_SPI | \ - CFG_CMD_UNIVERSE | \ - CFG_CMD_USB | \ -+ CFG_CMD_DHRYSTONE | \ - CFG_CMD_VFD ) - - /* Default configuration ---- /dev/null -+++ b/include/config.h -@@ -0,0 +1,2 @@ -+/* Automatically generated - do not edit */ -+#include ---- /dev/null -+++ b/include/config.mk -@@ -0,0 +1,5 @@ -+ARCH = mips -+CPU = mips -+BOARD = danube -+VENDOR = ifx -+SOC = danube ---- a/include/flash.h -+++ b/include/flash.h -@@ -79,7 +79,7 @@ typedef struct { - extern unsigned long flash_init (void); - extern void flash_print_info (flash_info_t *); - extern int flash_erase (flash_info_t *, int, int); --extern int flash_sect_erase (ulong addr_first, ulong addr_last); -+extern int flash_sect_erase (ulong addr_first, ulong addr_last, unsigned int bPartialErase); - extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last); - - /* common/flash.c */ -@@ -131,7 +131,9 @@ extern void flash_read_factory_serial(fl - #define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/ - #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ - -- /* Micron Technologies (INTEL compat.) */ -+#define EON_ID_EN29LV320B 0x22f9 -+#define FLASH_29LV320B 0xE0 -+/* Micron Technologies (INTEL compat.) */ - #define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ - #define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */ - -@@ -299,6 +301,10 @@ extern void flash_read_factory_serial(fl - #define TOSH_ID_FVT160 0xC2 /* TC58FVT160 ID (16 M, top ) */ - #define TOSH_ID_FVB160 0x43 /* TC58FVT160 ID (16 M, bottom ) */ - -+#define MX_ID_29LV320AB 0x22A822A8 /* MXIC MX29LV320AB ID (32 M, bottom ) joelin */ -+#define MX_ID_29LV160BB 0x22492249 /* MXIC MX29LV160BB ID (16 M, bottom ) joelin */ -+#define MX_ID_29LV640BB 0x22cb22cb /* MXIC MX29LV640BB ID (64 M, bottom ) joelin */ -+ - /*----------------------------------------------------------------------- - * Internal FLASH identification codes - * -@@ -422,6 +428,10 @@ extern void flash_read_factory_serial(fl - #define FLASH_S29GL064M 0x00F0 /* Spansion S29GL064M-R6 */ - #define FLASH_S29GL128N 0x00F1 /* Spansion S29GL128N */ - -+#define FLASH_29LV320AB 0x00B0 /* MXIC MX29LV320AB( 32M = 4M x 16 ) joelin 10/07/2004*/ -+#define FLASH_29LV160BB 0x00B1 /* MXIC MX29LV160BB( 16M = 2M x 16 ) joelin 11/22/2004*/ -+#define FLASH_29LV640BB 0x00B2 /* MXIC MX29LV640BB( 64M = 8M x 16 ) liupeng*/ -+ - #define FLASH_UNKNOWN 0xFFFF /* unknown flash type */ - - ---- a/include/image.h -+++ b/include/image.h -@@ -132,6 +132,7 @@ - #define IH_COMP_NONE 0 /* No Compression Used */ - #define IH_COMP_GZIP 1 /* gzip Compression Used */ - #define IH_COMP_BZIP2 2 /* bzip2 Compression Used */ -+#define IH_COMP_LZMA 3 /* lzma Compression Used */ - - #define IH_MAGIC 0x27051956 /* Image Magic Number */ - #define IH_NMLEN 32 /* Image Name Length */ ---- /dev/null -+++ b/include/syscall.h -@@ -0,0 +1,42 @@ -+#ifndef __MON_SYS_CALL_H__ -+#define __MON_SYS_CALL_H__ -+ -+#ifndef __ASSEMBLY__ -+ -+#include -+ -+/* These are declarations of system calls available in C code */ -+int mon_getc(void); -+int mon_tstc(void); -+void mon_putc(const char); -+void mon_puts(const char*); -+void mon_printf(const char* fmt, ...); -+void mon_install_hdlr(int, interrupt_handler_t*, void*); -+void mon_free_hdlr(int); -+void *mon_malloc(size_t); -+void mon_free(void*); -+void mon_udelay(unsigned long); -+unsigned long mon_get_timer(unsigned long); -+ -+#endif /* ifndef __ASSEMBLY__ */ -+ -+#define NR_SYSCALLS 11 /* number of syscalls */ -+ -+ -+/* -+ * Make sure these functions are in the same order as they -+ * appear in the "examples/syscall.S" file !!! -+ */ -+#define SYSCALL_GETC 0 -+#define SYSCALL_TSTC 1 -+#define SYSCALL_PUTC 2 -+#define SYSCALL_PUTS 3 -+#define SYSCALL_PRINTF 4 -+#define SYSCALL_INSTALL_HDLR 5 -+#define SYSCALL_FREE_HDLR 6 -+#define SYSCALL_MALLOC 7 -+#define SYSCALL_FREE 8 -+#define SYSCALL_UDELAY 9 -+#define SYSCALL_GET_TIMER 10 -+ -+#endif ---- /dev/null -+++ b/ld_uboot.conf -@@ -0,0 +1,8 @@ -+TAG_DWNLD() -+{ -+ 0xA0B00000 "u-boot.bin" /* Download u-boot image */ -+}; -+TAG_START() -+{ -+ 0xA0B00000 -+}; /* Start u-boot image */ ---- a/lib_generic/Makefile -+++ b/lib_generic/Makefile -@@ -28,7 +28,7 @@ LIB = $(obj)libgeneric.a - COBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \ - bzlib_randtable.o bzlib_huffman.o \ - crc32.o ctype.o display_options.o ldiv.o \ -- string.o vsprintf.o zlib.o -+ string.o vsprintf.o zlib.o LzmaDecode.o LzmaWrapper.o - - SRCS := $(COBJS:.o=.c) - OBJS := $(addprefix $(obj),$(COBJS)) ---- a/lib_mips/board.c -+++ b/lib_mips/board.c -@@ -29,9 +29,30 @@ - #include - #include - -+#ifdef CFG_BOOTSTRAP_CODE -+//#include -+#undef CONFIG_MICROBZIP2 -+ -+#ifdef CONFIG_BZIP2 -+#include -+#endif -+ -+#ifdef CONFIG_MICROBZIP2 -+#include -+#endif -+ -+#ifdef CONFIG_LZMA -+#include -+#endif -+#endif //CFG_BOOTSTRAP_CODE -+ - DECLARE_GLOBAL_DATA_PTR; - --#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \ -+#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < BOOTSTRAP_CFG_MONITOR_BASE) || \ -+ (CFG_ENV_ADDR >= (BOOTSTRAP_CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \ -+ defined(CFG_ENV_IS_IN_NVRAM) && defined(CFG_BOOTSTRAP_CODE) -+#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) -+#elif ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \ - (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \ - defined(CFG_ENV_IS_IN_NVRAM) - #define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE) -@@ -39,21 +60,24 @@ DECLARE_GLOBAL_DATA_PTR; - #define TOTAL_MALLOC_LEN CFG_MALLOC_LEN - #endif - --#undef DEBUG -- - extern int timer_init(void); -- - extern int incaip_set_cpuclk(void); - -+#ifdef CFG_BOOTSTRAP_CODE -+extern ulong uboot_end_data_bootstrap; -+extern ulong uboot_end_bootstrap; -+#else //CFG_BOOTSTRAP_CODE - extern ulong uboot_end_data; - extern ulong uboot_end; -+#endif //CFG_BOOTSTRAP_CODE - - ulong monitor_flash_len; - --const char version_string[] = -- U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"; -+const char version_string[] = U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")"; - -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF - static char *failed = "*** failed ***\n"; -+#endif - - /* - * Begin and End of memory area for malloc(), and current "brk" -@@ -62,14 +86,15 @@ static ulong mem_malloc_start; - static ulong mem_malloc_end; - static ulong mem_malloc_brk; - -- - /* - * The Malloc area is immediately below the monitor copy in DRAM - */ --static void mem_malloc_init (void) --{ -+#ifdef CFG_BOOTSTRAP_CODE -+static void mem_malloc_init (ulong dest_addr) { -+#else //CFG_BOOTSTRAP_CODE -+static void mem_malloc_init (void) { - ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off; -- -+#endif //CFG_BOOTSTRAP_CODE - mem_malloc_end = dest_addr; - mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN; - mem_malloc_brk = mem_malloc_start; -@@ -79,6 +104,25 @@ static void mem_malloc_init (void) - mem_malloc_end - mem_malloc_start); - } - -+#ifdef CFG_BOOTSTRAP_CODE -+void *malloc(unsigned int size) { -+ if(size < (mem_malloc_end - mem_malloc_start)) { -+ mem_malloc_start += size; -+ debug ("malloc : size required = 0x%08lx and pointer = 0x%08lx\n",size,mem_malloc_start - size); -+ return (void *)(mem_malloc_start - size); -+ } -+ return NULL; -+} -+ -+void *realloc(void *src,unsigned int size) { -+ return NULL; -+} -+ -+void free(void *src) { -+ return; -+} -+#endif //CFG_BOOTSTRAP_CODE -+ - void *sbrk (ptrdiff_t increment) - { - ulong old = mem_malloc_brk; -@@ -99,42 +143,58 @@ static int init_func_ram (void) - #else - int board_type = 0; /* use dummy arg */ - #endif -- puts ("DRAM: "); - -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+#ifdef CONFIG_USE_DDR_RAM -+ puts ("DDR-DRAM: "); -+#else -+ puts ("DRAM: "); -+#endif -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF - if ((gd->ram_size = initdram (board_type)) > 0) { -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF - print_size (gd->ram_size, "\n"); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF - return (0); - } -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF - puts (failed); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF - return (1); - } - -+#if !defined(CFG_BOOTSTRAP_CODE) || defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) - static int display_banner(void) - { -- - printf ("\n\n%s\n\n", version_string); - return (0); - } -+#endif - -+#ifndef CFG_BOOTSTRAP_CODE - static void display_flash_config(ulong size) - { - puts ("Flash: "); - print_size (size, "\n"); - } -+#endif //CFG_BOOTSTRAP_CODE - -- -+#if !defined(CFG_BOOTSTRAP_CODE) || defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) - static int init_baudrate (void) - { -+#ifndef CFG_BOOTSTRAP_CODE - char tmp[64]; /* long enough for environment variables */ - int i = getenv_r ("baudrate", tmp, sizeof (tmp)); - - gd->baudrate = (i > 0) - ? (int) simple_strtoul (tmp, NULL, 10) - : CONFIG_BAUDRATE; -- -+#else //CFG_BOOTSTRAP_CODE -+ gd->baudrate = CONFIG_BAUDRATE; -+#endif //CFG_BOOTSTRAP_CODE - return (0); - } -- -+#endif - - /* - * Breath some life into the board... -@@ -159,27 +219,49 @@ static int init_baudrate (void) - typedef int (init_fnc_t) (void); - - init_fnc_t *init_sequence[] = { -+#ifdef CFG_BOOTSTRAP_CODE -+ //fuse_prg, -+ //timer_init, -+ //env_init, /* initialize environment */ -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ init_baudrate, /* initialze baudrate settings */ -+ serial_init, /* serial communications setup */ -+ console_init_f, -+ display_banner, /* say that we are here */ -+ checkboard, -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ init_func_ram, -+ NULL, -+#else /********** CFG_BOOTSTRAP_CODE **********/ - timer_init, -- env_init, /* initialize environment */ --#ifdef CONFIG_INCA_IP -- incaip_set_cpuclk, /* set cpu clock according to environment variable */ --#endif - init_baudrate, /* initialze baudrate settings */ - serial_init, /* serial communications setup */ - console_init_f, - display_banner, /* say that we are here */ - checkboard, - init_func_ram, -+ env_init, /* initialize environment */ - NULL, -+#endif //CFG_BOOTSTRAP_CODE - }; - -+#ifdef CFG_BOOTSTRAP_CODE -+extern void bootstrap_relocate_code(ulong addr_sp, gd_t *id, ulong addr); - -+void bootstrap_board_init_f(ulong bootflag) -+#else - void board_init_f(ulong bootflag) -+#endif - { - gd_t gd_data, *id; - bd_t *bd; - init_fnc_t **init_fnc_ptr; -- ulong addr, addr_sp, len = (ulong)&uboot_end - CFG_MONITOR_BASE; -+#ifdef CFG_BOOTSTRAP_CODE -+ ulong addr, addr_sp, len = (ulong)&uboot_end_bootstrap - BOOTSTRAP_CFG_MONITOR_BASE; -+ ulong lzmaImageaddr = 0; -+#else //CFG_BOOTSTRAP_CODE -+ ulong addr, addr_sp, len = CFG_MONITOR_LEN; -+#endif //CFG_BOOTSTRAP_CODE - ulong *s; - #ifdef CONFIG_PURPLE - void copy_code (ulong); -@@ -219,13 +301,12 @@ void board_init_f(ulong bootflag) - addr -= len; - addr &= ~(16 * 1024 - 1); - -- debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); -+ debug ("Reserving %d Bytes for U-Boot at: %08lx\n", len, addr); - - /* Reserve memory for malloc() arena. - */ - addr_sp = addr - TOTAL_MALLOC_LEN; -- debug ("Reserving %dk for malloc() at: %08lx\n", -- TOTAL_MALLOC_LEN >> 10, addr_sp); -+ debug ("Reserving %d Bytes for malloc() at: %08lx\n", TOTAL_MALLOC_LEN, addr_sp); - - /* - * (permanently) allocate a Board Info struct -@@ -234,20 +315,17 @@ void board_init_f(ulong bootflag) - addr_sp -= sizeof(bd_t); - bd = (bd_t *)addr_sp; - gd->bd = bd; -- debug ("Reserving %d Bytes for Board Info at: %08lx\n", -- sizeof(bd_t), addr_sp); -+ debug ("Reserving %d Bytes for Board Info at: %08lx\n", sizeof(bd_t), addr_sp); - - addr_sp -= sizeof(gd_t); - id = (gd_t *)addr_sp; -- debug ("Reserving %d Bytes for Global Data at: %08lx\n", -- sizeof (gd_t), addr_sp); -+ debug ("Reserving %d Bytes for Global Data at: %08lx\n", sizeof (gd_t), addr_sp); - - /* Reserve memory for boot params. - */ - addr_sp -= CFG_BOOTPARAMS_LEN; - bd->bi_boot_params = addr_sp; -- debug ("Reserving %dk for boot params() at: %08lx\n", -- CFG_BOOTPARAMS_LEN >> 10, addr_sp); -+ debug ("Reserving %dk for boot params() at: %08lx\n", CFG_BOOTPARAMS_LEN >> 10, addr_sp); - - /* - * Finally, we set up a new (bigger) stack. -@@ -279,7 +357,16 @@ void board_init_f(ulong bootflag) - copy_code(addr); - #endif - -+#ifdef CFG_BOOTSTRAP_CODE -+ lzmaImageaddr = (ulong)&uboot_end_data_bootstrap; -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ puts("\n BOOTSTRAP: relocate_code start"); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ bootstrap_relocate_code (addr_sp, id, addr); -+#else //CFG_BOOTSTRAP_CODE -+ puts("\n relocate_code start"); - relocate_code (addr_sp, id, addr); -+#endif //CFG_BOOTSTRAP_CODE - - /* NOTREACHED - relocate_code() does not return */ - } -@@ -292,7 +379,110 @@ void board_init_f(ulong bootflag) - * - ************************************************************************ - */ -+#ifdef CFG_BOOTSTRAP_CODE -+void bootstrap_board_init_r (gd_t *id, ulong dest_addr) { -+ int i; -+ ulong addr; -+ ulong data, len, checksum; -+ ulong *len_ptr; -+ image_header_t header; -+ image_header_t *hdr = &header; -+ unsigned int destLen; -+ int (*fn)(void); -+ -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ puts("\n BOOTSTRAP: relocate_code finish.\n"); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ -+ /* initialize malloc() area */ -+ mem_malloc_init(dest_addr); -+ -+ addr = (char *)(BOOTSTRAP_CFG_MONITOR_BASE + ((ulong)&uboot_end_data_bootstrap - dest_addr)); -+ memmove (&header, (char *)addr, sizeof(image_header_t)); -+ -+ if (ntohl(hdr->ih_magic) != IH_MAGIC) { -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ printf ("Bad Magic Number at address 0x%08lx\n",addr); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ return; -+ } - -+ data = (ulong)&header; -+ len = sizeof(image_header_t); -+ -+ checksum = ntohl(hdr->ih_hcrc); -+ hdr->ih_hcrc = 0; -+ if (crc32 (0, (unsigned char *)data, len) != checksum) { -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ printf ("Bad Header Checksum\n"); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ return; -+ } -+ -+ data = addr + sizeof(image_header_t); -+ len = ntohl(hdr->ih_size); -+ len_ptr = (ulong *)data; -+ -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ debug ("Disabling all the interrupts\n"); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ disable_interrupts(); -+ -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ debug (" Uncompressing UBoot Image ... \n" ); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ /* -+ * If we've got less than 4 MB of malloc() space, -+ * use slower decompression algorithm which requires -+ * at most 2300 KB of memory. -+ */ -+ destLen = 0x0; -+ -+#ifdef CONFIG_BZIP2 -+ i = BZ2_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load), -+ 0x400000, (char *)data, len, -+ CFG_MALLOC_LEN < (4096 * 1024), 0); -+ if (i != BZ_OK) { -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ return; -+ } -+#elif CONFIG_MICROBZIP2 -+ i = micro_bzBuffToBuffDecompress ((char*)ntohl(hdr->ih_load), -+ &destLen, (char *)data, len, -+ CFG_MALLOC_LEN < (4096 * 1024), 0); -+ if (i != RETVAL_OK) { -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ printf ("MICRO_BUNZIP2 ERROR %d - must RESET board to recover\n", i); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ return; -+ } -+#elif CONFIG_LZMA -+ i = lzma_inflate ((unsigned char *)data, len, (unsigned char*)ntohl(hdr->ih_load), &destLen); -+ if (i != LZMA_RESULT_OK) { -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ printf ("LZMA ERROR %d - must RESET board to recover\n", i); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ return; -+ } -+#else -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ printf ("NONE Compressing u-boot body!!\n"); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ memmove ((void *)ntohl(hdr->ih_load), (uchar *)data, len); -+ destLen = len; -+#endif -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ debug (" Uncompression completed successfully with destLen %d.\n ",destLen ); -+ debug ("Head: Jumping to u-boot in the ram at 0x%08lx\n", CFG_MONITOR_BASE); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF -+ -+ fn = ntohl(hdr->ih_load); -+ (*fn)(); -+ hang (); -+} -+#else //CFG_BOOTSTRAP_CODE - void board_init_r (gd_t *id, ulong dest_addr) - { - cmd_tbl_t *cmdtp; -@@ -305,6 +495,8 @@ void board_init_r (gd_t *id, ulong dest_ - bd_t *bd; - int i; - -+ puts("\n relocate_code finish.\n"); -+ - gd = id; - gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ - -@@ -321,12 +513,10 @@ void board_init_r (gd_t *id, ulong dest_ - ulong addr; - - addr = (ulong) (cmdtp->cmd) + gd->reloc_off; --#if 0 -- printf ("Command \"%s\": 0x%08lx => 0x%08lx\n", -- cmdtp->name, (ulong) (cmdtp->cmd), addr); --#endif -- cmdtp->cmd = -- (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; -+ -+ debug ("Command \"%s\": 0x%08lx => 0x%08lx\n", cmdtp->name, (ulong) (cmdtp->cmd), addr); -+ -+ cmdtp->cmd = (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; - - addr = (ulong)(cmdtp->name) + gd->reloc_off; - cmdtp->name = (char *)addr; -@@ -363,7 +553,13 @@ void board_init_r (gd_t *id, ulong dest_ - /* initialize malloc() area */ - mem_malloc_init(); - malloc_bin_reloc(); -+#if (CONFIG_COMMANDS & CFG_CMD_NAND) -+ nand_init(); /* go init the NAND */ -+#endif - -+#ifdef CONFIG_SPI -+ spi_init_f(); /* go init the SPI flash */ -+#endif - /* relocate environment function pointers etc. */ - env_relocate(); - -@@ -424,9 +620,12 @@ void board_init_r (gd_t *id, ulong dest_ - - /* NOTREACHED - no way out of command loop except booting */ - } -+#endif //CFG_BOOTSTRAP_CODE - - void hang (void) - { -+#ifdef DEBUG_ENABLE_BOOTSTRAP_PRINTF - puts ("### ERROR ### Please RESET the board ###\n"); -+#endif //DEBUG_ENABLE_BOOTSTRAP_PRINTF - for (;;); - } ---- a/lib_mips/time.c -+++ b/lib_mips/time.c -@@ -80,6 +80,19 @@ void udelay (unsigned long usec) - /*NOP*/; - } - -+#ifndef CFG_BOOTSTRAP_CODE -+void mdelay (unsigned long msec) -+{ -+ int i,j; -+ for(i=0;i - #include - #include -+#if defined(CONFIG_IFX_MIPS) -+# include "ifx_eth.c" -+#endif - - #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) - -@@ -54,6 +57,9 @@ extern int scc_initialize(bd_t*); - extern int skge_initialize(bd_t*); - extern int tsec_initialize(bd_t*, int, char *); - extern int npe_initialize(bd_t *); -+#if defined(CONFIG_IFX_MIPS) -+ IFX_ETH_INITIALIZE_EXTERN -+#endif - - static struct eth_device *eth_devices, *eth_current; - -@@ -235,7 +241,9 @@ int eth_initialize(bd_t *bis) - #if defined(CONFIG_RTL8169) - rtl8169_initialize(bis); - #endif -- -+#if defined(CONFIG_IFX_MIPS) -+ IFX_ETH_INITIALIZE(bis) -+#endif - if (!eth_devices) { - puts ("No ethernet found.\n"); - } else { ---- a/tools/mkimage.c -+++ b/tools/mkimage.c -@@ -28,6 +28,7 @@ - #ifndef __WIN32__ - #include /* for host / network byte order conversions */ - #endif -+#include - #include - #include - #include -@@ -138,6 +139,7 @@ table_entry_t comp_name[] = { - { IH_COMP_NONE, "none", "uncompressed", }, - { IH_COMP_BZIP2, "bzip2", "bzip2 compressed", }, - { IH_COMP_GZIP, "gzip", "gzip compressed", }, -+ { IH_COMP_LZMA, "lzma", "lzma compressed", }, - { -1, "", "", }, - }; - -@@ -445,7 +447,7 @@ NXTARG: ; - } - - /* We're a bit of paranoid */ --#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) -+#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__) - (void) fdatasync (ifd); - #else - (void) fsync (ifd); -@@ -495,7 +497,7 @@ NXTARG: ; - (void) munmap((void *)ptr, sbuf.st_size); - - /* We're a bit of paranoid */ --#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) -+#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__) - (void) fdatasync (ifd); - #else - (void) fsync (ifd); ---- a/cpu/mips/cache.S -+++ b/cpu/mips/cache.S -@@ -29,7 +29,9 @@ - #include - #include - #include -- -+#if defined(CONFIG_IFX_MIPS) -+# include "danube/ifx_cache.S" -+#endif - - /* 16KB is the maximum size of instruction and data caches on - * MIPS 4K. -@@ -155,6 +157,9 @@ mips_cache_reset: - */ - - mtc0 zero, CP0_TAGLO -+#if defined(CONFIG_IFX_MIPS) && defined(IFX_CACHE_EXTRA_INVALID_TAG) -+ IFX_CACHE_EXTRA_INVALID_TAG -+#endif - - /* - * The caches are probably in an indeterminate state, -@@ -171,6 +176,9 @@ mips_cache_reset: - move a1, a2 - icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill)) - -+#if defined(CONFIG_IFX_MIPS) && defined(IFX_CACHE_EXTRA_OPERATION) -+ IFX_CACHE_EXTRA_OPERATION -+#else - /* To support Orion/R4600, we initialise the data cache in 3 passes. - */ - -@@ -200,6 +208,7 @@ mips_cache_reset: - move a3, t5 # dcacheLineSize - move a1, a2 - icacheop(a0,a1,a2,a3,Index_Store_Tag_D) -+#endif - - j ra - .end mips_cache_reset ---- a/cpu/mips/config.mk -+++ b/cpu/mips/config.mk -@@ -20,20 +20,26 @@ - # Foundation, Inc., 59 Temple Place, Suite 330, Boston, - # MA 02111-1307 USA - # --v=$(shell \ --$(CROSS_COMPILE)as --version|grep "GNU assembler"|awk '{print $$3}'|awk -F . '{print $$2}') --MIPSFLAGS=$(shell \ --if [ "$v" -lt "14" ]; then \ -- echo "-mcpu=4kc"; \ --else \ -- echo "-march=4kc -mtune=4kc"; \ --fi) - -+ifndef PLATFORM_CPU -+PLATFORM_CPU = mips32 -+endif -+ -+MIPSFLAGS +=$(call cc-option,-march=$(PLATFORM_CPU) -mtune=$(PLATFORM_CPU),-mcpu=$(PLATFORM_CPU)) -+ -+ifeq ($(CROSS_COMPILE_UCLIBC),1) -+ifneq (,$(findstring mipsel,$(CROSS_COMIPLE))) -+ENDIANNESS = -el -+else -+ENDIANNESS = -eb -+endif -+else - ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) - ENDIANNESS = -EL - else - ENDIANNESS = -EB - endif -+endif - - MIPSFLAGS += $(ENDIANNESS) -mabicalls - ---- a/cpu/mips/cpu.c -+++ b/cpu/mips/cpu.c -@@ -23,7 +23,12 @@ - - #include - #include --#include -+#if defined(CONFIG_INCA_IP) -+# include -+#elif defined(CONFIG_IFX_MIPS) -+# include -+# include "danube/ifx_cpu.c" -+#endif - #include - - int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -@@ -34,6 +39,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, - void (*f)(void) = (void *) 0xbfc00000; - - f(); -+#elif defined(CONFIG_IFX_MIPS) -+ IFX_CPU_RESET; - #endif - fprintf(stderr, "*** reset failed ***\n"); - return 0; ---- a/cpu/mips/incaip_clock.c -+++ b/cpu/mips/incaip_clock.c -@@ -22,8 +22,9 @@ - */ - - #include --#include - -+#ifdef CONFIG_INCA_IP -+#include - - /******************************************************************************* - * -@@ -114,3 +115,5 @@ int incaip_set_cpuclk (void) - - return 0; - } -+ -+#endif /* CONFIG_INCA_IP */ ---- a/cpu/mips/start.S -+++ b/cpu/mips/start.S -@@ -27,7 +27,9 @@ - #include - #include - #include -- -+#if defined(CONFIG_IFX_MIPS) -+# include "danube/ifx_start.S" -+#endif - - #define RVECENT(f,n) \ - b f; nop -@@ -36,15 +38,24 @@ - li k0,bev - - .set noreorder -- -+#ifdef CFG_BOOTSTRAP_CODE -+ .globl _start_bootstrap -+#else - .globl _start -+#endif - .text -+#ifdef CFG_BOOTSTRAP_CODE -+_start_bootstrap: -+#else - _start: -+#endif - RVECENT(reset,0) /* U-boot entry point */ - RVECENT(reset,1) /* software reboot */ --#if defined(CONFIG_INCA_IP) -+#if defined(CONFIG_INCA_IP) || defined(CONFIG_INCA_IP2) - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ - .word 0x00000000 /* phase of the flash */ -+#elif defined(CONFIG_IFX_MIPS) && defined(IFX_EBU_BOOTCFG_DWORD) -+ IFX_EBU_BOOTCFG_DWORD - #elif defined(CONFIG_PURPLE) - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ - .word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */ -@@ -181,6 +192,9 @@ _start: - * 128 * 8 == 1024 == 0x400 - * so this is address R_VEC+0x400 == 0xbfc00400 - */ -+#if defined(CONFIG_IFX_MIPS) && defined(IFX_MORE_RESERVED_VECTORS) -+ IFX_MORE_RESERVED_VECTORS -+#else - #ifdef CONFIG_PURPLE - /* 0xbfc00400 */ - .word 0xdc870000 -@@ -205,8 +219,12 @@ _start: - .word 0x00000000 - .word 0x00000000 - #endif /* CONFIG_PURPLE */ -+#endif /* CONFIG_IFX_MIPS */ - .align 4 - reset: -+#if defined(CONFIG_IFX_MIPS) && defined(IFX_RESET_PRECHECK) -+ IFX_RESET_PRECHECK -+#endif - - /* Clear watch registers. - */ -@@ -226,6 +244,10 @@ reset: - /* CAUSE register */ - mtc0 zero, CP0_CAUSE - -+#if defined(CONFIG_IFX_MIPS) && defined(IFX_CPU_EXTRA_INIT) -+ IFX_CPU_EXTRA_INIT -+#endif -+ - /* Init Timer */ - mtc0 zero, CP0_COUNT - mtc0 zero, CP0_COMPARE -@@ -252,12 +274,26 @@ reset: - nop - #endif - -+#if defined(CONFIG_IFX_MIPS) && defined(IFX_CPU1_SUPPORT) && defined(IFX_SKIP_LOWLEVEL_INIT) -+ IFX_SKIP_LOWLEVEL_INIT -+#endif -+#ifdef CFG_BOOTSTRAP_CODE - /* Initialize any external memory. - */ - la t9, lowlevel_init - jalr t9 - nop -+#endif -+lowlevel_init_done: -+ -+ beq s0, zero, init_cache_0 -+ nop -+ -+#if defined(CONFIG_IFX_MIPS) && defined(IFX_CPU1_SUPPORT) && defined(IFX_CPU1_INIT) -+ IFX_CPU1_INIT -+#endif - -+init_cache_0: - /* Initialize caches... - */ - la t9, mips_cache_reset -@@ -266,7 +302,11 @@ reset: - - /* ... and enable them. - */ -+#if defined(CONFIG_IFX_MIPS) && defined(IFX_CACHE_OPER_MODE) -+ IFX_CACHE_OPER_MODE -+#else - li t0, CONF_CM_CACHABLE_NONCOHERENT -+#endif - mtc0 t0, CP0_CONFIG - - -@@ -280,13 +320,38 @@ reset: - li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET - la sp, 0(t0) - -+#if defined(CONFIG_IFX_MIPS) && defined(IFX_CPU1_SUPPORT) && defined(IFX_BOOT_CLEAR) -+ IFX_BOOT_CLEAR -+#endif -+ -+#ifdef CFG_BOOTSTRAP_CODE -+ la t9, bootstrap_board_init_f -+#else - la t9, board_init_f -+#endif - j t9 - nop - -+#ifdef CFG_BOOTSTRAP_CODE -+/* -+ * void jump_unconditional (addr) -+ * This function simply jumps to the location pointed by a0. -+ * a0 = target_location -+ * -+ */ -+ .globl jump_unconditional -+ .ent jump_unconditional -+jump_unconditional: -+ move t9, a0 -+ j t9 -+ nop -+ .end jump_unconditional -+ -+#endif - - /* - * void relocate_code (addr_sp, gd, addr_moni) -+ * void bootstrap_relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. -@@ -295,12 +360,22 @@ reset: - * a1 = gd - * a2 = destination address - */ -+#ifdef CFG_BOOTSTRAP_CODE -+ .globl bootstrap_relocate_code -+ .ent bootstrap_relocate_code -+bootstrap_relocate_code: -+#else - .globl relocate_code - .ent relocate_code - relocate_code: -+#endif - move sp, a0 /* Set new stack pointer */ - -+#ifdef CFG_BOOTSTRAP_CODE -+ li t0, BOOTSTRAP_CFG_MONITOR_BASE -+#else - li t0, CFG_MONITOR_BASE -+#endif - la t3, in_ram - lw t2, -12(t3) /* t2 <-- uboot_end_data */ - move t1, a2 -@@ -311,7 +386,11 @@ relocate_code: - * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address - */ - move t6, gp -+#ifdef CFG_BOOTSTRAP_CODE -+ sub gp, BOOTSTRAP_CFG_MONITOR_BASE -+#else - sub gp, CFG_MONITOR_BASE -+#endif - add gp, a2 /* gp now adjusted */ - sub t6, gp, t6 /* t6 <-- relocation offset */ - -@@ -337,12 +416,21 @@ relocate_code: - - /* Jump to where we've relocated ourselves. - */ -+#ifdef CFG_BOOTSTRAP_CODE -+ addi t0, a2, in_ram - _start_bootstrap -+#else - addi t0, a2, in_ram - _start -+#endif - j t0 - nop - -+#ifdef CFG_BOOTSTRAP_CODE -+ .word uboot_end_data_bootstrap -+ .word uboot_end_bootstrap -+#else - .word uboot_end_data - .word uboot_end -+#endif - .word num_got_entries - - in_ram: -@@ -374,12 +462,19 @@ in_ram: - sw zero, 0(t1) /* delay slot */ - - move a0, a1 -+#ifdef CFG_BOOTSTRAP_CODE -+ la t9, bootstrap_board_init_r -+#else - la t9, board_init_r -+#endif - j t9 - move a1, a2 /* delay slot */ - -+#ifdef CFG_BOOTSTRAP_CODE -+ .end bootstrap_relocate_code -+#else - .end relocate_code -- -+#endif - - /* Exception handlers. - */ -@@ -388,3 +483,20 @@ romReserved: - - romExcHandle: - b romExcHandle -+ -+romEjtagHandle: -+#ifdef CFG_BOOTSTRAP_CODE -+ deret -+ nop -+#endif /* CFG_BOOTSTRAP_CODE */ -+1: -+ b 1b -+ -+ /* Additional handlers. -+ */ -+#if defined(CONFIG_IFX_MIPS) -+#if defined(IFX_MIPS_HANDLER_1) -+ifx_mips_handler_1: -+ IFX_MIPS_HANDLER_1 -+#endif -+#endif ---- a/tools/Makefile -+++ b/tools/Makefile -@@ -21,7 +21,7 @@ - # MA 02111-1307 USA - # - --BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) -+BIN_FILES = mkimage$(SFX) - - OBJ_LINKS = environment.o crc32.o - OBJ_FILES = img2srec.o mkimage.o envcrc.o gen_eth_addr.o bmp_logo.o diff --git a/package/uboot-ifxmips/patches/110-compile_fix.patch b/package/uboot-ifxmips/patches/110-compile_fix.patch deleted file mode 100644 index 34d0ac6e53..0000000000 --- a/package/uboot-ifxmips/patches/110-compile_fix.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- a/cpu/mips/Makefile -+++ b/cpu/mips/Makefile -@@ -36,6 +36,9 @@ START := $(addprefix $(obj),$(START)) - - all: $(obj).depend $(START) $(LIB) - -+start.o: start.S -+ $(CC) $(AFLAGS) -fPIC -c -o $@ $< -+ - $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - ---- a/Makefile -+++ b/Makefile -@@ -185,8 +185,8 @@ include $(TOPDIR)/config.mk - OBJS = cpu/$(CPU)/start.o - OBJS_BOOTSTRAP = cpu/$(CPU)/start_bootstrap.o - --cpu/$(CPU)/start_bootstrap.S: cpu/$(CPU)/start.S -- ln -s start.S cpu/$(CPU)/start_bootstrap.S -+cpu/$(CPU)/start_bootstrap.o: cpu/$(CPU)/start.S -+ $(CC) $(AFLAGS) -fPIC -DCFG_BOOTSTRAP_CODE -c -o $@ $< - - ifeq ($(CPU),i386) - OBJS += cpu/$(CPU)/start16.o diff --git a/package/uboot-ifxmips/patches/120-eon_flash.patch b/package/uboot-ifxmips/patches/120-eon_flash.patch deleted file mode 100644 index 0b0da3c69b..0000000000 --- a/package/uboot-ifxmips/patches/120-eon_flash.patch +++ /dev/null @@ -1,24 +0,0 @@ ---- a/board/ifx/danube/flash.c -+++ b/board/ifx/danube/flash.c -@@ -470,7 +470,10 @@ ulong flash_get_size (FPWV *addr, flash_ - case (uchar)MX_MANUFACT: // 0x00c2 - info->flash_id = FLASH_MAN_MX ;//0x00030000 - break; -- -+ case (uchar)EON_MANUFACT: -+ printf("%s:%s[%d]\n", __FILE__, __func__, __LINE__); -+ info->flash_id = FLASH_MAN_AMD ; -+ break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; ---- a/include/flash.h -+++ b/include/flash.h -@@ -130,6 +130,7 @@ extern void flash_read_factory_serial(fl - #define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */ - #define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/ - #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ -+#define EON_MANUFACT 0x0000007F - - #define EON_ID_EN29LV320B 0x22f9 - #define FLASH_29LV320B 0xE0 diff --git a/package/uboot-ifxmips/patches/130-a800.patch b/package/uboot-ifxmips/patches/130-a800.patch deleted file mode 100644 index f358201d18..0000000000 --- a/package/uboot-ifxmips/patches/130-a800.patch +++ /dev/null @@ -1,31 +0,0 @@ ---- a/drivers/ifx_sw.c -+++ b/drivers/ifx_sw.c -@@ -118,7 +118,7 @@ int danube_switch_initialize(bd_t * bis) - { - struct eth_device *dev; - unsigned short chipid; -- -+ int i; - #if 0 - printf("Entered danube_switch_initialize()\n"); - #endif -@@ -130,6 +130,19 @@ int danube_switch_initialize(bd_t * bis) - } - memset(dev, 0, sizeof(*dev)); - -+#ifdef A800_SWITCH -+ printf ("bring up a800 switch and leds\n"); -+ *EBU_CON_1 = 0x1e7ff; -+ *EBU_ADDR_SEL_1 = 0x14000001; -+ -+ *((volatile u16*)0xb4000000) = 0x0; -+ for(i = 0; i < 1000; i++) -+ udelay(1000); -+ *((volatile u16*)0xb4000000) = (1 << 10); -+ *EBU_CON_1 = 0x8001e7ff; -+#define CLK_OUT2_25MHZ -+#endif -+ - danube_dma_init(); - danube_init_switch_chip(REV_MII_MODE); - diff --git a/target/linux/ifxmips/Makefile b/target/linux/ifxmips/Makefile deleted file mode 100644 index b82f78263f..0000000000 --- a/target/linux/ifxmips/Makefile +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright (C) 2007-2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk - -ARCH:=mips -BOARD:=ifxmips -BOARDNAME:=Infineon Mips -FEATURES:=squashfs jffs2 atm - -LINUX_VERSION:=2.6.30.10 - -CFLAGS=-Os -pipe -mips32r2 -mtune=mips32r2 -funit-at-a-time - -include $(INCLUDE_DIR)/target.mk -DEFAULT_PACKAGES+=uboot-lantiq -#kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl ifxmips-dsl-api ifxmips-dsl-control ifx-tapidemo - -define Target/Description - Build firmware images for Infineon Mips Controllers -endef - -$(eval $(call BuildTarget)) diff --git a/target/linux/ifxmips/base-files/etc/config/network b/target/linux/ifxmips/base-files/etc/config/network deleted file mode 100644 index 183e6bf34c..0000000000 --- a/target/linux/ifxmips/base-files/etc/config/network +++ /dev/null @@ -1,26 +0,0 @@ -config interface loopback - option ifname lo - option proto static - option ipaddr 127.0.0.1 - option netmask 255.0.0.0 - -config interface lan - option ifname eth0 - option type bridge - option proto static - option ipaddr 192.168.1.1 - option netmask 255.255.255.0 - -config atm-bridge - option unit 0 - option encaps llc - option vpi 1 - option vci 32 - option payload bridged # some ISPs need this set to 'routed' - -config interface wan - option ifname nas0 - option proto pppoe - option username "" - option password "" - option unit 0 diff --git a/target/linux/ifxmips/base-files/etc/hotplug.d/button/00-reset b/target/linux/ifxmips/base-files/etc/hotplug.d/button/00-reset deleted file mode 100644 index ef70cd49a5..0000000000 --- a/target/linux/ifxmips/base-files/etc/hotplug.d/button/00-reset +++ /dev/null @@ -1,3 +0,0 @@ -[ "$ACTION" = "released" -a "$BUTTON" = reset ] && { - reboot -} diff --git a/target/linux/ifxmips/base-files/etc/inittab b/target/linux/ifxmips/base-files/etc/inittab deleted file mode 100644 index 7989a7f60e..0000000000 --- a/target/linux/ifxmips/base-files/etc/inittab +++ /dev/null @@ -1,4 +0,0 @@ -::sysinit:/etc/init.d/rcS S boot -::shutdown:/etc/init.d/rcS K stop -ttyS0::askfirst:/bin/ash --login -ttyS1::askfirst:/bin/ash --login diff --git a/target/linux/ifxmips/base-files/lib/upgrade/platform.sh b/target/linux/ifxmips/base-files/lib/upgrade/platform.sh deleted file mode 100755 index 247ba1a25c..0000000000 --- a/target/linux/ifxmips/base-files/lib/upgrade/platform.sh +++ /dev/null @@ -1,25 +0,0 @@ -PART_NAME=linux - -platform_check_image() { - [ "$ARGC" -gt 1 ] && return 1 - - case "$(get_magic_word "$1")" in - # .trx files - 2705) return 0;; - *) - echo "Invalid image type" - return 1 - ;; - esac -} - -# use default for platform_do_upgrade() - -disable_watchdog() { - killall watchdog - ( ps | grep -v 'grep' | grep '/dev/watchdog' ) && { - echo 'Could not disable watchdog' - return 1 - } -} -append sysupgrade_pre_upgrade disable_watchdog diff --git a/target/linux/ifxmips/config-2.6.30 b/target/linux/ifxmips/config-2.6.30 deleted file mode 100644 index 27e4b8096a..0000000000 --- a/target/linux/ifxmips/config-2.6.30 +++ /dev/null @@ -1,162 +0,0 @@ -CONFIG_32BIT=y -# CONFIG_64BIT is not set -CONFIG_ADM6996_PHY=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_ARCH_REQUIRE_GPIOLIB=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -# CONFIG_BCM47XX is not set -# CONFIG_BINARY_PRINTF is not set -CONFIG_BITREVERSE=y -# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set -# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set -CONFIG_CEVT_R4K=y -CONFIG_CEVT_R4K_LIB=y -CONFIG_CMDLINE="console=ttyS0,9600 rootfstype=squashfs,jffs2" -CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_CAVIUM_OCTEON is not set -CONFIG_CPU_HAS_LLSC=y -CONFIG_CPU_HAS_PREFETCH=y -CONFIG_CPU_HAS_SYNC=y -# CONFIG_CPU_LITTLE_ENDIAN is not set -# CONFIG_CPU_LOONGSON2 is not set -CONFIG_CPU_MIPS32=y -# CONFIG_CPU_MIPS32_R1 is not set -CONFIG_CPU_MIPS32_R2=y -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -CONFIG_CPU_MIPSR2=y -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R5500 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_VR41XX is not set -CONFIG_CSRC_R4K=y -CONFIG_CSRC_R4K_LIB=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DEVPORT=y -# CONFIG_DM9000 is not set -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_EARLY_PRINTK=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_GPIO=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_GPIOLIB=y -CONFIG_GPIO_IFXMIPS_EBU=y -CONFIG_GPIO_SYSFS=y -CONFIG_HARDWARE_WATCHPOINTS=y -CONFIG_HAS_DMA=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_HAVE_IDE=y -CONFIG_HAVE_MLOCK=y -CONFIG_HAVE_OPROFILE=y -CONFIG_HAVE_STD_PC_SERIAL_PORT=y -# CONFIG_HIGH_RES_TIMERS is not set -CONFIG_HW_HAS_PCI=y -CONFIG_HW_RANDOM=y -CONFIG_HZ=250 -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -CONFIG_IFXMIPS=y -CONFIG_IFXMIPS_GPIO_RST_BTN=y -CONFIG_IFXMIPS_MII0=y -# CONFIG_IFXMIPS_PROM_ASC0 is not set -CONFIG_IFXMIPS_PROM_ASC1=y -CONFIG_IFXMIPS_WDT=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_IRQ_CPU=y -CONFIG_KALLSYMS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_IFXMIPS=y -# CONFIG_LEMOTE_FULONG is not set -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_MIKROTIK_RB532 is not set -CONFIG_MIPS=y -# CONFIG_MIPS_COBALT is not set -CONFIG_MIPS_L1_CACHE_SHIFT=5 -# CONFIG_MIPS_MACHINE is not set -# CONFIG_MIPS_MALTA is not set -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MIPS_VPE_LOADER is not set -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_IFXMIPS=y -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -# CONFIG_NO_IOPORT is not set -# CONFIG_NXP_STB220 is not set -# CONFIG_NXP_STB225 is not set -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PHYLIB=y -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_PROBE_INITRD_HEADER is not set -CONFIG_RTL8306_PHY=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y -# CONFIG_SCSI_DMA is not set -# CONFIG_SERIAL_8250 is not set -CONFIG_SERIAL_IFXMIPS=y -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SLOW_WORK is not set -CONFIG_SWAP_IO_SPACE=y -CONFIG_SWCONFIG=y -CONFIG_SYS_HAS_CPU_MIPS32_R1=y -CONFIG_SYS_HAS_CPU_MIPS32_R2=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y -CONFIG_SYS_SUPPORTS_MULTITHREADING=y -# CONFIG_TC35815 is not set -CONFIG_TRACING_SUPPORT=y -CONFIG_TRAD_SIGNALS=y -CONFIG_USB_SUPPORT=y -CONFIG_ZONE_DMA_FLAG=0 diff --git a/target/linux/ifxmips/extract.py b/target/linux/ifxmips/extract.py deleted file mode 100755 index 91b4a578d6..0000000000 --- a/target/linux/ifxmips/extract.py +++ /dev/null @@ -1,9 +0,0 @@ -#!/usr/bin/python -from sys import stdin, stdout -while True: - c = stdin.read(2) - if len(c) < 2: - break - n1, n2 = ord(c[0]), ord(c[1]) - stdout.write(chr(((n2 & 15) << 4) + ((n2 & 240) >> 4))) - stdout.write(chr(((n1 & 15) << 4) + ((n1 & 240) >> 4))) diff --git a/target/linux/ifxmips/extract.sh b/target/linux/ifxmips/extract.sh deleted file mode 100755 index 52dfbd56ea..0000000000 --- a/target/linux/ifxmips/extract.sh +++ /dev/null @@ -1,42 +0,0 @@ -#!/bin/sh - -DIR="$1/" -FILE="$1/$2" - -echo "This tool downloads the arcor a800 firmware release and extracts the voip firmware for the danube." -echo "Please only do so if it is legal in your country" - -[ ! -f ${FILE} ] && { - echo ${FILE} is missing - exit 1 -} - -[ -f ${DIR}/ifxmips_fw_decodev2.tar.bz2 -a ! -f ${DIR}voip_coef.bin ] && { - [ ! -f ${DIR}decode_ifx_fw ] && { - tar xjf ${DIR}ifxmips_fw_decodev2.tar.bz2 ifxmips_fw_decode/decode.c -O > ${DIR}decode.c - gcc -o ${DIR}decode_ifx_fw ${DIR}decode.c - } - [ ! -f ${DIR}voip_coef.lzma ] && { - ${DIR}decode_ifx_fw $FILE ${DIR}voip_coef.lzma - } - lzma d ${DIR}voip_coef.lzma ${DIR}voip_coef.bin -} -[ ! -f ${DIR}dsl_a.bin ] && { - dd if=${FILE} of=${DIR}dsl1.lzma bs=1 skip=2168832 count=150724 - lzma d ${DIR}dsl2.lzma ${DIR}dsl_a.bin -} - -[ ! -f ${DIR}dsl_b.bin ] && { - dd if=${FILE} of=${DIR}dsl2.lzma bs=1 skip=2320384 count=148343 - lzma d ${DIR}dsl1.lzma ${DIR}dsl_b.bin -} - -[ ! -f ${DIR}voip.bin ] && { - dd if=${FILE} of=${DIR}voip.lzma bs=1 skip=2468864 count=452105 - lzma d ${DIR}voip.lzma ${DIR}voip.bin -} -exit 0 - -# get lzma offsets -# hexdump -C arcor_A800_452CPW_FW_1.02.206\(20081201\).bin | grep "5d 00 00 80" -# hexdump -C arcor_A800_452CPW_FW_1.02.206\(20081201\).bin | grep "00 d5 08 00" diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/Kconfig b/target/linux/ifxmips/files/arch/mips/ifxmips/Kconfig deleted file mode 100644 index 549ffe2bb0..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/Kconfig +++ /dev/null @@ -1,28 +0,0 @@ -# copyright 2007 john crispin - -menu "IFXMips built-in" - -config MTD_IFXMIPS - bool "IFXMips flash map" - default y - -config IFXMIPS_GPIO_RST_BTN - bool "Reset Button" - default y - -choice - prompt "prom_printf ASC" - help - Choose which serial port is used, until the console driver is loaded - -config IFXMIPS_PROM_ASC0 - bool "ASC0" - -config IFXMIPS_PROM_ASC1 - bool "ASC1" - -endchoice - - -endmenu - diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/Makefile b/target/linux/ifxmips/files/arch/mips/ifxmips/Makefile deleted file mode 100644 index c330be6344..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/Makefile +++ /dev/null @@ -1 +0,0 @@ -obj-y := reset.o prom.o setup.o irq.o dma-core.o pmu.o board.o clock.o gpio.o timer.o diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/board.c b/target/linux/ifxmips/files/arch/mips/ifxmips/board.c deleted file mode 100644 index 0f084a81b0..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/board.c +++ /dev/null @@ -1,404 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#define MAX_BOARD_NAME_LEN 32 -#define MAX_IFXMIPS_DEVS 9 - -#define SYSTEM_DANUBE "Danube" -#define SYSTEM_DANUBE_CHIPID1 0x00129083 -#define SYSTEM_DANUBE_CHIPID2 0x0012B083 - -#define SYSTEM_TWINPASS "Twinpass" -#define SYSTEM_TWINPASS_CHIPID 0x0012D083 - -enum { - EASY50712, - EASY4010, - ARV4519, -}; - -extern int ifxmips_pci_external_clock; -extern int ifxmips_pci_req_mask; - -static unsigned int chiprev; -static int cmdline_mac; -char board_name[MAX_BOARD_NAME_LEN + 1] = { 0 }; - -struct ifxmips_board { - int type; - char name[32]; - unsigned int system_type; - struct platform_device **devs; - struct resource reset_resource; - struct resource gpiodev_resource; - struct gpio_led *ifxmips_leds; - struct gpio_led *gpio_leds; - int pci_external_clock; - int pci_req_mask; - int num_devs; -}; - -DEFINE_SPINLOCK(ebu_lock); -EXPORT_SYMBOL_GPL(ebu_lock); - -static unsigned char ifxmips_ethaddr[6]; -static int ifxmips_brn; - -static struct gpio_led_platform_data ifxmips_led_data; - -static struct platform_device ifxmips_led = { - .id = 0, - .name = "ifxmips_led", - .dev = { - .platform_data = (void *) &ifxmips_led_data, - } -}; - -static struct platform_device ifxmips_gpio = { - .id = 0, - .name = "ifxmips_gpio", - .num_resources = 1, -}; - -static struct platform_device ifxmips_mii = { - .id = 0, - .name = "ifxmips_mii0", - .dev = { - .platform_data = ifxmips_ethaddr, - } -}; - -static struct platform_device ifxmips_wdt = { - .id = 0, - .name = "ifxmips_wdt", -}; - -static struct resource ifxmips_mtd_resource = { - .start = IFXMIPS_FLASH_START, - .end = IFXMIPS_FLASH_START + IFXMIPS_FLASH_MAX - 1, - .flags = IORESOURCE_MEM, -}; - -static struct platform_device ifxmips_mtd = { - .id = 0, - .name = "ifxmips_mtd", - .num_resources = 1, - .resource = &ifxmips_mtd_resource, -}; - -static struct platform_device ifxmips_gpio_dev = { - .name = "GPIODEV", - .id = -1, - .num_resources = 1, -}; - -#ifdef CONFIG_LEDS_GPIO -static struct gpio_led arv4519_gpio_leds[] = { - { .name = "ifx:green:power", .gpio = 3, .active_low = 1, }, - { .name = "ifx:red:power", .gpio = 7, .active_low = 1, }, - { .name = "ifx:green:adsl", .gpio = 4, .active_low = 1, }, - { .name = "ifx:green:internet", .gpio = 5, .active_low = 1, }, - { .name = "ifx:red:internet", .gpio = 8, .active_low = 1, }, - { .name = "ifx:green:wlan", .gpio = 6, .active_low = 1, }, - { .name = "ifx:green:usbpwr", .gpio = 14, .active_low = 1, }, - { .name = "ifx:green:usb", .gpio = 19, .active_low = 1, }, -}; - -static struct gpio_led_platform_data ifxmips_gpio_led_data; - -static struct platform_device ifxmips_gpio_leds = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = (void *) &ifxmips_gpio_led_data, - } -}; -#endif - -static struct resource dwc_usb_res[] = { - { - .name = "dwc_usb_membase", - .flags = IORESOURCE_MEM, - .start = 0x1E101000, - .end = 0x1E101FFF - }, - { - .name = "dwc_usb_irq", - .flags = IORESOURCE_IRQ, - .start = IFXMIPS_USB_INT, - } -}; - -static struct platform_device dwc_usb = -{ - .id = 0, - .name = "dwc_usb", - .resource = dwc_usb_res, - .num_resources = ARRAY_SIZE(dwc_usb_res), -}; - -struct platform_device *easy50712_devs[] = { - &ifxmips_led, &ifxmips_gpio, &ifxmips_mii, - &ifxmips_mtd, &ifxmips_wdt, &ifxmips_gpio_dev, &dwc_usb -}; - -struct platform_device *easy4010_devs[] = { - &ifxmips_led, &ifxmips_gpio, &ifxmips_mii, - &ifxmips_mtd, &ifxmips_wdt, &ifxmips_gpio_dev, &dwc_usb -}; - -struct platform_device *arv5419_devs[] = { - &ifxmips_gpio, &ifxmips_mii, &ifxmips_mtd, - &ifxmips_gpio_dev, &ifxmips_wdt, &dwc_usb, -#ifdef CONFIG_LEDS_GPIO - &ifxmips_gpio_leds, -#endif -}; - -static struct gpio_led easy50712_leds[] = { - { .name = "ifx:green:test0", .gpio = 0,}, - { .name = "ifx:green:test1", .gpio = 1,}, - { .name = "ifx:green:test2", .gpio = 2,}, - { .name = "ifx:green:test3", .gpio = 3,}, -}; - -static struct gpio_led easy4010_leds[] = { - { .name = "ifx:green:test0", .gpio = 0,}, - { .name = "ifx:green:test1", .gpio = 1,}, - { .name = "ifx:green:test2", .gpio = 2,}, - { .name = "ifx:green:test3", .gpio = 3,}, -}; - -static struct ifxmips_board boards[] = { - { - /* infineon eval kit */ - .type = EASY50712, - .name = "EASY50712", - .system_type = SYSTEM_DANUBE_CHIPID1, - .devs = easy50712_devs, - .reset_resource = {.name = "reset", .start = 1, .end = 15,}, - .gpiodev_resource = { .name = "gpio", - .start = (1 << 0) | (1 << 1), - .end = (1 << 0) | (1 << 1)}, - .ifxmips_leds = easy50712_leds, - }, { - /* infineon eval kit */ - .type = EASY4010, - .name = "EASY4010", - .system_type = SYSTEM_TWINPASS_CHIPID, - .devs = easy4010_devs, - .reset_resource = {.name = "reset", .start = 1, .end = 15}, - .gpiodev_resource = { .name = "gpio", - .start = (1 << 0) | (1 << 1), - .end = (1 << 0) | (1 << 1)}, - .ifxmips_leds = easy4010_leds, - }, { - /* arcaydian annex-a board used by thompson, airties, ... */ - .type = ARV4519, - .name = "ARV4519", - .system_type = SYSTEM_DANUBE_CHIPID2, - .devs = arv5419_devs, - .reset_resource = {.name = "reset", .start = 1, .end = 14}, - .pci_external_clock = 1, - .gpio_leds = arv4519_gpio_leds, - }, -}; - -const char *get_system_type(void) -{ - chiprev = (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0x0FFFFFFF); - - switch (chiprev) { - case SYSTEM_DANUBE_CHIPID1: - case SYSTEM_DANUBE_CHIPID2: - return SYSTEM_DANUBE; - - case SYSTEM_TWINPASS_CHIPID: - return SYSTEM_TWINPASS; - } - - return BOARD_SYSTEM_TYPE; -} - -static int __init ifxmips_set_board_type(char *str) -{ - str = strchr(str, '='); - if (!str) - goto out; - str++; - if (strlen(str) > MAX_BOARD_NAME_LEN) - goto out; - strncpy(board_name, str, MAX_BOARD_NAME_LEN); - printk(KERN_INFO "bootloader told us, that this is a %s board\n", - board_name); -out: - return 1; -} -__setup("ifxmips_board", ifxmips_set_board_type); - -static int __init ifxmips_set_ethaddr(char *str) -{ -#define IS_HEX(x) \ - (((x >= '0' && x <= '9') || (x >= 'a' && x <= 'f') \ - || (x >= 'A' && x <= 'F')) ? (1) : (0)) - int i; - str = strchr(str, '='); - if (!str) - goto out; - str++; - if (strlen(str) != 17) - goto out; - for (i = 0; i < 6; i++) { - if (!IS_HEX(str[3 * i]) || !IS_HEX(str[(3 * i) + 1])) - goto out; - if ((i != 5) && (str[(3 * i) + 2] != ':')) - goto out; - ifxmips_ethaddr[i] = simple_strtoul(&str[3 * i], NULL, 16); - } - if (is_valid_ether_addr(ifxmips_ethaddr)) - cmdline_mac = 1; -out: - return 1; -} -__setup("ethaddr", ifxmips_set_ethaddr); - -int ifxmips_find_brn_block(void) -{ - unsigned char temp[8]; - memcpy_fromio(temp, - (void *)KSEG1ADDR(IFXMIPS_FLASH_START + 0x800000 - 0x10000), 8); - if (memcmp(temp, "BRN-BOOT", 8) == 0) { - if (!cmdline_mac) - memcpy_fromio(ifxmips_ethaddr, - (void *)KSEG1ADDR(IFXMIPS_FLASH_START + - 0x800000 - 0x10000 + 0x16), 6); - if (is_valid_ether_addr(ifxmips_ethaddr)) - cmdline_mac = 1; - return 1; - } else { - return 0; - } -} - -int ifxmips_has_brn_block(void) -{ - return ifxmips_brn; -} -EXPORT_SYMBOL(ifxmips_has_brn_block); - -struct ifxmips_board *ifxmips_find_board(void) -{ - int i; - if (!*board_name) - return 0; - for (i = 0; i < ARRAY_SIZE(boards); i++) - if ((boards[i].system_type == chiprev) && - (!strcmp(boards[i].name, board_name))) - return &boards[i]; - return 0; -} - -int __init ifxmips_init_devices(void) -{ - struct ifxmips_board *board; - - chiprev = (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0x0FFFFFFF); - board = ifxmips_find_board(); - ifxmips_brn = ifxmips_find_brn_block(); - - if (!cmdline_mac) - random_ether_addr(ifxmips_ethaddr); - - if (!board) { - switch (chiprev) { - case SYSTEM_DANUBE_CHIPID1: - case SYSTEM_DANUBE_CHIPID2: - default: - board = &boards[0]; - break; - case SYSTEM_TWINPASS_CHIPID: - board = &boards[1]; - break; - } - } - - switch (board->type) { - case EASY50712: - board->num_devs = ARRAY_SIZE(easy50712_devs); - ifxmips_led_data.num_leds = ARRAY_SIZE(easy50712_leds); - break; - case EASY4010: - board->num_devs = ARRAY_SIZE(easy4010_devs); - ifxmips_led_data.num_leds = ARRAY_SIZE(easy4010_leds); - break; - case ARV4519: - /* set some sane defaults for the gpios */ - gpio_set_value(3, 0); - gpio_set_value(4, 0); - gpio_set_value(5, 0); - gpio_set_value(6, 0); - gpio_set_value(7, 1); - gpio_set_value(8, 1); - gpio_set_value(19, 0); - board->num_devs = ARRAY_SIZE(arv5419_devs); -#ifdef CONFIG_LEDS_GPIO - ifxmips_gpio_led_data.num_leds = ARRAY_SIZE(arv4519_gpio_leds); -#endif - break; - } -#ifdef CONFIG_LEDS_GPIO - ifxmips_gpio_led_data.leds = board->gpio_leds; -#endif - ifxmips_led_data.leds = board->ifxmips_leds; - - printk(KERN_INFO "%s: adding %d devs\n", - __func__, board->num_devs); - - ifxmips_gpio.resource = &board->reset_resource; - ifxmips_gpio_dev.resource = &board->gpiodev_resource; - if (board->pci_external_clock) - ifxmips_pci_external_clock = 1; - if (board->pci_req_mask) - ifxmips_pci_req_mask = board->pci_req_mask; - printk(KERN_INFO "using board definition %s\n", board->name); - return platform_add_devices(board->devs, board->num_devs); -} - -arch_initcall(ifxmips_init_devices); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c b/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c deleted file mode 100644 index d951be8f49..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/clock.c +++ /dev/null @@ -1,204 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 Xu Liang, infineon - * Copyright (C) 2008 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -static unsigned int cgu_get_pll0_fdiv(void); -unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; - -#define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3] - -static inline unsigned int get_input_clock(int pll) -{ - switch (pll) { - case 0: - if (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC) - return BASIS_INPUT_CRYSTAL_USB; - else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_INPUT_CLOCK_FREQUENCY_1; - else - return BASIC_INPUT_CLOCK_FREQUENCY_2; - case 1: - if (CGU_PLL1_SRC) - return BASIS_INPUT_CRYSTAL_USB; - else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) - return BASIC_INPUT_CLOCK_FREQUENCY_1; - else - return BASIC_INPUT_CLOCK_FREQUENCY_2; - case 2: - switch (CGU_PLL2_SRC) { - case 0: - return cgu_get_pll0_fdiv(); - case 1: - return CGU_PLL2_PHASE_DIVIDER_ENABLE ? - BASIC_INPUT_CLOCK_FREQUENCY_1 : - BASIC_INPUT_CLOCK_FREQUENCY_2; - case 2: - return BASIS_INPUT_CRYSTAL_USB; - } - default: - return 0; - } -} - -static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) -{ - u64 res, clock = get_input_clock(pll); - - res = num * clock; - do_div(res, den); - return res; -} - -static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = ((N + 1) << 10) + K; - unsigned int den = (M + 1) << 10; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = ((N + 1) << 11) + K + 512; - unsigned int den = (M + 1) << 11; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, - unsigned int K) -{ - unsigned int num = K >= 512 ? - ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; - unsigned int den = (M + 1) << 12; - - return cal_dsm(pll, num, den); -} - -static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, - unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) -{ - if (!dsmsel) - return mash_dsm(pll, M, N, K); - else if (!phase_div_en) - return mash_dsm(pll, M, N, K); - else - return ssff_dsm_2(pll, M, N, K); -} - -static inline unsigned int cgu_get_pll0_fosc(void) -{ - if (CGU_PLL0_BYPASS) - return get_input_clock(0); - else - return !CGU_PLL0_CFG_FRAC_EN - ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL, - CGU_PLL0_PHASE_DIVIDER_ENABLE) - : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK, - CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE); -} - -static unsigned int cgu_get_pll0_fdiv(void) -{ - unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; - return (cgu_get_pll0_fosc() + (div >> 1)) / div; -} - -unsigned int cgu_get_io_region_clock(void) -{ - unsigned int ret = cgu_get_pll0_fosc(); - switch (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { - default: - case 0: - return (ret + 1) / 2; - case 1: - return (ret * 2 + 2) / 5; - case 2: - return (ret + 1) / 3; - case 3: - return (ret + 2) / 4; - } -} - -void cgu_setup_pci_clk(int external_clock) -{ - /* set clock to 33Mhz */ - ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000, - IFXMIPS_CGU_IFCCR); - ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000, - IFXMIPS_CGU_IFCCR); - if (external_clock) { - ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~(1 << 16), - IFXMIPS_CGU_IFCCR); - ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR); - } else { - ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16), - IFXMIPS_CGU_IFCCR); - ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR); - } -} - -unsigned int cgu_get_fpi_bus_clock(int fpi) -{ - unsigned int ret = cgu_get_io_region_clock(); - if ((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL)) - ret >>= 1; - return ret; -} -EXPORT_SYMBOL(cgu_get_fpi_bus_clock); - -unsigned int ifxmips_get_cpu_hz(void) -{ - unsigned int ddr_clock = DDR_HZ; - switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc) { - case 0: - return CLOCK_333M; - case 4: - return ddr_clock; - } - return ddr_clock << 1; -} -EXPORT_SYMBOL(ifxmips_get_cpu_hz); - -unsigned int ifxmips_get_fpi_hz(void) -{ - unsigned int ddr_clock = DDR_HZ; - if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40) - return ddr_clock >> 1; - return ddr_clock; -} -EXPORT_SYMBOL(ifxmips_get_fpi_hz); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c b/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c deleted file mode 100644 index 084b2839a7..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/dma-core.c +++ /dev/null @@ -1,690 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -/*25 descriptors for each dma channel,4096/8/20=25.xx*/ -#define IFXMIPS_DMA_DESCRIPTOR_OFFSET 25 - -#define MAX_DMA_DEVICE_NUM 6 /*max ports connecting to dma */ -#define MAX_DMA_CHANNEL_NUM 20 /*max dma channels */ -#define DMA_INT_BUDGET 100 /*budget for interrupt handling */ -#define DMA_POLL_COUNTER 4 /*fix me, set the correct counter value here! */ - -extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr); -extern void ifxmips_enable_irq(unsigned int irq_nr); -extern void ifxmips_disable_irq(unsigned int irq_nr); - -u64 *g_desc_list; -struct dma_device_info dma_devs[MAX_DMA_DEVICE_NUM]; -struct dma_channel_info dma_chan[MAX_DMA_CHANNEL_NUM]; - -static const char *global_device_name[MAX_DMA_DEVICE_NUM] = - { "PPE", "DEU", "SPI", "SDIO", "MCTRL0", "MCTRL1" }; - -struct dma_chan_map default_dma_map[MAX_DMA_CHANNEL_NUM] = { - {"PPE", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH0_INT, 0}, - {"PPE", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH1_INT, 0}, - {"PPE", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH2_INT, 1}, - {"PPE", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH3_INT, 1}, - {"PPE", IFXMIPS_DMA_RX, 2, IFXMIPS_DMA_CH4_INT, 2}, - {"PPE", IFXMIPS_DMA_TX, 2, IFXMIPS_DMA_CH5_INT, 2}, - {"PPE", IFXMIPS_DMA_RX, 3, IFXMIPS_DMA_CH6_INT, 3}, - {"PPE", IFXMIPS_DMA_TX, 3, IFXMIPS_DMA_CH7_INT, 3}, - {"DEU", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH8_INT, 0}, - {"DEU", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH9_INT, 0}, - {"DEU", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH10_INT, 1}, - {"DEU", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH11_INT, 1}, - {"SPI", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH12_INT, 0}, - {"SPI", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH13_INT, 0}, - {"SDIO", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH14_INT, 0}, - {"SDIO", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH15_INT, 0}, - {"MCTRL0", IFXMIPS_DMA_RX, 0, IFXMIPS_DMA_CH16_INT, 0}, - {"MCTRL0", IFXMIPS_DMA_TX, 0, IFXMIPS_DMA_CH17_INT, 0}, - {"MCTRL1", IFXMIPS_DMA_RX, 1, IFXMIPS_DMA_CH18_INT, 1}, - {"MCTRL1", IFXMIPS_DMA_TX, 1, IFXMIPS_DMA_CH19_INT, 1} -}; - -struct dma_chan_map *chan_map = default_dma_map; -volatile u32 g_ifxmips_dma_int_status; -volatile int g_ifxmips_dma_in_process; /* 0=not in process, 1=in process */ - -void do_dma_tasklet(unsigned long); -DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0); - -u8 *common_buffer_alloc(int len, int *byte_offset, void **opt) -{ - u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL); - - *byte_offset = 0; - - return buffer; -} - -void common_buffer_free(u8 *dataptr, void *opt) -{ - kfree(dataptr); -} - -void enable_ch_irq(struct dma_channel_info *pCh) -{ - int chan_no = (int)(pCh - dma_chan); - unsigned long flag; - - local_irq_save(flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(0x4a, IFXMIPS_DMA_CIE); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN); - local_irq_restore(flag); - ifxmips_enable_irq(pCh->irq); -} - -void disable_ch_irq(struct dma_channel_info *pCh) -{ - unsigned long flag; - int chan_no = (int) (pCh - dma_chan); - - local_irq_save(flag); - g_ifxmips_dma_int_status &= ~(1 << chan_no); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(0, IFXMIPS_DMA_CIE); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); - local_irq_restore(flag); - ifxmips_mask_and_ack_irq(pCh->irq); -} - -void open_chan(struct dma_channel_info *pCh) -{ - unsigned long flag; - int chan_no = (int)(pCh - dma_chan); - - local_irq_save(flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 1, IFXMIPS_DMA_CCTRL); - if (pCh->dir == IFXMIPS_DMA_RX) - enable_ch_irq(pCh); - local_irq_restore(flag); -} - -void close_chan(struct dma_channel_info *pCh) -{ - unsigned long flag; - int chan_no = (int) (pCh - dma_chan); - - local_irq_save(flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - disable_ch_irq(pCh); - local_irq_restore(flag); -} - -void reset_chan(struct dma_channel_info *pCh) -{ - int chan_no = (int) (pCh - dma_chan); - - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL); -} - -void rx_chan_intr_handler(int chan_no) -{ - struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev; - struct dma_channel_info *pCh = &dma_chan[chan_no]; - struct rx_desc *rx_desc_p; - int tmp; - unsigned long flag; - - /*handle command complete interrupt */ - rx_desc_p = (struct rx_desc *)pCh->desc_base + pCh->curr_desc; - if (rx_desc_p->status.field.OWN == CPU_OWN - && rx_desc_p->status.field.C - && rx_desc_p->status.field.data_length < 1536){ - /* Every thing is correct, then we inform the upper layer */ - pDev->current_rx_chan = pCh->rel_chan_no; - if (pDev->intr_handler) - pDev->intr_handler(pDev, RCV_INT); - pCh->weight--; - } else { - local_irq_save(flag); - tmp = ifxmips_r32(IFXMIPS_DMA_CS); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS); - ifxmips_w32(tmp, IFXMIPS_DMA_CS); - g_ifxmips_dma_int_status &= ~(1 << chan_no); - local_irq_restore(flag); - ifxmips_enable_irq(dma_chan[chan_no].irq); - } -} - -inline void tx_chan_intr_handler(int chan_no) -{ - struct dma_device_info *pDev = (struct dma_device_info *)dma_chan[chan_no].dma_dev; - struct dma_channel_info *pCh = &dma_chan[chan_no]; - int tmp; - unsigned long flag; - - local_irq_save(flag); - tmp = ifxmips_r32(IFXMIPS_DMA_CS); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CIS) | 0x7e, IFXMIPS_DMA_CIS); - ifxmips_w32(tmp, IFXMIPS_DMA_CS); - g_ifxmips_dma_int_status &= ~(1 << chan_no); - local_irq_restore(flag); - pDev->current_tx_chan = pCh->rel_chan_no; - if (pDev->intr_handler) - pDev->intr_handler(pDev, TRANSMIT_CPT_INT); -} - -void do_dma_tasklet(unsigned long unused) -{ - int i; - int chan_no = 0; - int budget = DMA_INT_BUDGET; - int weight = 0; - unsigned long flag; - - while (g_ifxmips_dma_int_status) { - if (budget-- < 0) { - tasklet_schedule(&dma_tasklet); - return; - } - chan_no = -1; - weight = 0; - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) { - if ((g_ifxmips_dma_int_status & (1 << i)) && dma_chan[i].weight > 0) { - if (dma_chan[i].weight > weight) { - chan_no = i; - weight = dma_chan[chan_no].weight; - } - } - } - - if (chan_no >= 0) { - if (chan_map[chan_no].dir == IFXMIPS_DMA_RX) - rx_chan_intr_handler(chan_no); - else - tx_chan_intr_handler(chan_no); - } else { - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - dma_chan[i].weight = dma_chan[i].default_weight; - } - } - - local_irq_save(flag); - g_ifxmips_dma_in_process = 0; - if (g_ifxmips_dma_int_status) { - g_ifxmips_dma_in_process = 1; - tasklet_schedule(&dma_tasklet); - } - local_irq_restore(flag); -} - -irqreturn_t dma_interrupt(int irq, void *dev_id) -{ - struct dma_channel_info *pCh; - int chan_no = 0; - int tmp; - - pCh = (struct dma_channel_info *)dev_id; - chan_no = (int)(pCh - dma_chan); - if (chan_no < 0 || chan_no > 19) - BUG(); - - tmp = ifxmips_r32(IFXMIPS_DMA_IRNEN); - ifxmips_w32(0, IFXMIPS_DMA_IRNEN); - g_ifxmips_dma_int_status |= 1 << chan_no; - ifxmips_w32(tmp, IFXMIPS_DMA_IRNEN); - ifxmips_mask_and_ack_irq(irq); - - if (!g_ifxmips_dma_in_process) { - g_ifxmips_dma_in_process = 1; - tasklet_schedule(&dma_tasklet); - } - - return IRQ_HANDLED; -} - -struct dma_device_info *dma_device_reserve(char *dev_name) -{ - int i; - - for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) { - if (strcmp(dev_name, dma_devs[i].device_name) == 0) { - if (dma_devs[i].reserved) - return NULL; - dma_devs[i].reserved = 1; - break; - } - } - - return &dma_devs[i]; -} -EXPORT_SYMBOL(dma_device_reserve); - -void dma_device_release(struct dma_device_info *dev) -{ - dev->reserved = 0; -} -EXPORT_SYMBOL(dma_device_release); - -void dma_device_register(struct dma_device_info *dev) -{ - int i, j; - int chan_no = 0; - u8 *buffer; - int byte_offset; - unsigned long flag; - struct dma_device_info *pDev; - struct dma_channel_info *pCh; - struct rx_desc *rx_desc_p; - struct tx_desc *tx_desc_p; - - for (i = 0; i < dev->max_tx_chan_num; i++) { - pCh = dev->tx_chan[i]; - if (pCh->control == IFXMIPS_DMA_CH_ON) { - chan_no = (int)(pCh - dma_chan); - for (j = 0; j < pCh->desc_len; j++) { - tx_desc_p = (struct tx_desc *)pCh->desc_base + j; - memset(tx_desc_p, 0, sizeof(struct tx_desc)); - } - local_irq_save(flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - /* check if the descriptor length is changed */ - if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len) - ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN); - - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2) - ; - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN); - ifxmips_w32(0x30100, IFXMIPS_DMA_CCTRL); /* reset and enable channel,enable channel later */ - local_irq_restore(flag); - } - } - - for (i = 0; i < dev->max_rx_chan_num; i++) { - pCh = dev->rx_chan[i]; - if (pCh->control == IFXMIPS_DMA_CH_ON) { - chan_no = (int)(pCh - dma_chan); - - for (j = 0; j < pCh->desc_len; j++) { - rx_desc_p = (struct rx_desc *)pCh->desc_base + j; - pDev = (struct dma_device_info *)(pCh->dma_dev); - buffer = pDev->buffer_alloc(pCh->packet_size, &byte_offset, (void *)&(pCh->opt[j])); - if (!buffer) - break; - - dma_cache_inv((unsigned long) buffer, pCh->packet_size); - - rx_desc_p->Data_Pointer = (u32)CPHYSADDR((u32)buffer); - rx_desc_p->status.word = 0; - rx_desc_p->status.field.byte_offset = byte_offset; - rx_desc_p->status.field.OWN = DMA_OWN; - rx_desc_p->status.field.data_length = pCh->packet_size; - } - - local_irq_save(flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - /* check if the descriptor length is changed */ - if (ifxmips_r32(IFXMIPS_DMA_CDLEN) != pCh->desc_len) - ifxmips_w32(pCh->desc_len, IFXMIPS_DMA_CDLEN); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) | 2, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 2) - ; - ifxmips_w32(0x0a, IFXMIPS_DMA_CIE); /* fix me, should enable all the interrupts here? */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) | (1 << chan_no), IFXMIPS_DMA_IRNEN); - ifxmips_w32(0x30000, IFXMIPS_DMA_CCTRL); - local_irq_restore(flag); - ifxmips_enable_irq(dma_chan[chan_no].irq); - } - } -} -EXPORT_SYMBOL(dma_device_register); - -void dma_device_unregister(struct dma_device_info *dev) -{ - int i, j; - int chan_no; - struct dma_channel_info *pCh; - struct rx_desc *rx_desc_p; - struct tx_desc *tx_desc_p; - unsigned long flag; - - for (i = 0; i < dev->max_tx_chan_num; i++) { - pCh = dev->tx_chan[i]; - if (pCh->control == IFXMIPS_DMA_CH_ON) { - chan_no = (int)(dev->tx_chan[i] - dma_chan); - local_irq_save(flag); - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - pCh->curr_desc = 0; - pCh->prev_desc = 0; - pCh->control = IFXMIPS_DMA_CH_OFF; - ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) - ; - local_irq_restore(flag); - - for (j = 0; j < pCh->desc_len; j++) { - tx_desc_p = (struct tx_desc *)pCh->desc_base + j; - if ((tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) - || (tx_desc_p->status.field.OWN == DMA_OWN && tx_desc_p->status.field.data_length > 0)) { - dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), (void *)pCh->opt[j]); - } - tx_desc_p->status.field.OWN = CPU_OWN; - memset(tx_desc_p, 0, sizeof(struct tx_desc)); - } - /* TODO should free buffer that is not transferred by dma */ - } - } - - for (i = 0; i < dev->max_rx_chan_num; i++) { - pCh = dev->rx_chan[i]; - chan_no = (int)(dev->rx_chan[i] - dma_chan); - ifxmips_disable_irq(pCh->irq); - - local_irq_save(flag); - g_ifxmips_dma_int_status &= ~(1 << chan_no); - pCh->curr_desc = 0; - pCh->prev_desc = 0; - pCh->control = IFXMIPS_DMA_CH_OFF; - - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - ifxmips_w32(0, IFXMIPS_DMA_CIE); /* fix me, should disable all the interrupts here? */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_IRNEN) & ~(1 << chan_no), IFXMIPS_DMA_IRNEN); /* disable interrupts */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~1, IFXMIPS_DMA_CCTRL); - while (ifxmips_r32(IFXMIPS_DMA_CCTRL) & 1) - ; - - local_irq_restore(flag); - for (j = 0; j < pCh->desc_len; j++) { - rx_desc_p = (struct rx_desc *) pCh->desc_base + j; - if ((rx_desc_p->status.field.OWN == CPU_OWN - && rx_desc_p->status.field.C) - || (rx_desc_p->status.field.OWN == DMA_OWN - && rx_desc_p->status.field.data_length > 0)) { - dev->buffer_free((u8 *) - __va(rx_desc_p->Data_Pointer), - (void *) pCh->opt[j]); - } - } - } -} -EXPORT_SYMBOL(dma_device_unregister); - -int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt) -{ - u8 *buf; - int len; - int byte_offset = 0; - void *p = NULL; - struct dma_channel_info *pCh = dma_dev->rx_chan[dma_dev->current_rx_chan]; - struct rx_desc *rx_desc_p; - - /* get the rx data first */ - rx_desc_p = (struct rx_desc *) pCh->desc_base + pCh->curr_desc; - if (!(rx_desc_p->status.field.OWN == CPU_OWN && rx_desc_p->status.field.C)) - return 0; - - buf = (u8 *) __va(rx_desc_p->Data_Pointer); - *(u32 *)dataptr = (u32)buf; - len = rx_desc_p->status.field.data_length; - - if (opt) - *(int *)opt = (int)pCh->opt[pCh->curr_desc]; - - /* replace with a new allocated buffer */ - buf = dma_dev->buffer_alloc(pCh->packet_size, &byte_offset, &p); - - if (buf) { - dma_cache_inv((unsigned long) buf, pCh->packet_size); - pCh->opt[pCh->curr_desc] = p; - wmb(); - - rx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) buf); - rx_desc_p->status.word = (DMA_OWN << 31) | ((byte_offset) << 23) | pCh->packet_size; - wmb(); - } else { - *(u32 *) dataptr = 0; - if (opt) - *(int *) opt = 0; - len = 0; - } - - /* increase the curr_desc pointer */ - pCh->curr_desc++; - if (pCh->curr_desc == pCh->desc_len) - pCh->curr_desc = 0; - - return len; -} -EXPORT_SYMBOL(dma_device_read); - -int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, void *opt) -{ - unsigned long flag; - u32 tmp, byte_offset; - struct dma_channel_info *pCh; - int chan_no; - struct tx_desc *tx_desc_p; - local_irq_save(flag); - - pCh = dma_dev->tx_chan[dma_dev->current_tx_chan]; - chan_no = (int)(pCh - (struct dma_channel_info *) dma_chan); - - tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc; - while (tx_desc_p->status.field.OWN == CPU_OWN && tx_desc_p->status.field.C) { - dma_dev->buffer_free((u8 *) __va(tx_desc_p->Data_Pointer), pCh->opt[pCh->prev_desc]); - memset(tx_desc_p, 0, sizeof(struct tx_desc)); - pCh->prev_desc = (pCh->prev_desc + 1) % (pCh->desc_len); - tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->prev_desc; - } - tx_desc_p = (struct tx_desc *)pCh->desc_base + pCh->curr_desc; - /* Check whether this descriptor is available */ - if (tx_desc_p->status.field.OWN == DMA_OWN || tx_desc_p->status.field.C) { - /* if not, the tell the upper layer device */ - dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT); - local_irq_restore(flag); - printk(KERN_INFO "%s %d: failed to write!\n", __func__, __LINE__); - - return 0; - } - pCh->opt[pCh->curr_desc] = opt; - /* byte offset----to adjust the starting address of the data buffer, should be multiple of the burst length. */ - byte_offset = ((u32) CPHYSADDR((u32) dataptr)) % ((dma_dev->tx_burst_len) * 4); - dma_cache_wback((unsigned long) dataptr, len); - wmb(); - tx_desc_p->Data_Pointer = (u32) CPHYSADDR((u32) dataptr) - byte_offset; - wmb(); - tx_desc_p->status.word = (DMA_OWN << 31) | DMA_DESC_SOP_SET | DMA_DESC_EOP_SET | ((byte_offset) << 23) | len; - wmb(); - - pCh->curr_desc++; - if (pCh->curr_desc == pCh->desc_len) - pCh->curr_desc = 0; - - /*Check whether this descriptor is available */ - tx_desc_p = (struct tx_desc *) pCh->desc_base + pCh->curr_desc; - if (tx_desc_p->status.field.OWN == DMA_OWN) { - /*if not , the tell the upper layer device */ - dma_dev->intr_handler (dma_dev, TX_BUF_FULL_INT); - } - - ifxmips_w32(chan_no, IFXMIPS_DMA_CS); - tmp = ifxmips_r32(IFXMIPS_DMA_CCTRL); - - if (!(tmp & 1)) - pCh->open(pCh); - - local_irq_restore(flag); - - return len; -} -EXPORT_SYMBOL(dma_device_write); - -int map_dma_chan(struct dma_chan_map *map) -{ - int i, j; - int result; - - for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) - strcpy(dma_devs[i].device_name, global_device_name[i]); - - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) { - dma_chan[i].irq = map[i].irq; - result = request_irq(dma_chan[i].irq, dma_interrupt, IRQF_DISABLED, map[i].dev_name, (void *)&dma_chan[i]); - if (result) { - printk(KERN_WARNING "error, cannot get dma_irq!\n"); - free_irq(dma_chan[i].irq, (void *) &dma_interrupt); - - return -EFAULT; - } - } - - for (i = 0; i < MAX_DMA_DEVICE_NUM; i++) { - dma_devs[i].num_tx_chan = 0; /*set default tx channel number to be one */ - dma_devs[i].num_rx_chan = 0; /*set default rx channel number to be one */ - dma_devs[i].max_rx_chan_num = 0; - dma_devs[i].max_tx_chan_num = 0; - dma_devs[i].buffer_alloc = &common_buffer_alloc; - dma_devs[i].buffer_free = &common_buffer_free; - dma_devs[i].intr_handler = NULL; - dma_devs[i].tx_burst_len = 4; - dma_devs[i].rx_burst_len = 4; - if (i == 0) { - ifxmips_w32(0, IFXMIPS_DMA_PS); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_PCTRL) | ((0xf << 8) | (1 << 6)), IFXMIPS_DMA_PCTRL); /*enable dma drop */ - } - - if (i == 1) { - ifxmips_w32(1, IFXMIPS_DMA_PS); - ifxmips_w32(0x14, IFXMIPS_DMA_PCTRL); /*deu port setting */ - } - - for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) { - dma_chan[j].byte_offset = 0; - dma_chan[j].open = &open_chan; - dma_chan[j].close = &close_chan; - dma_chan[j].reset = &reset_chan; - dma_chan[j].enable_irq = &enable_ch_irq; - dma_chan[j].disable_irq = &disable_ch_irq; - dma_chan[j].rel_chan_no = map[j].rel_chan_no; - dma_chan[j].control = IFXMIPS_DMA_CH_OFF; - dma_chan[j].default_weight = IFXMIPS_DMA_CH_DEFAULT_WEIGHT; - dma_chan[j].weight = dma_chan[j].default_weight; - dma_chan[j].curr_desc = 0; - dma_chan[j].prev_desc = 0; - } - - for (j = 0; j < MAX_DMA_CHANNEL_NUM; j++) { - if (strcmp(dma_devs[i].device_name, map[j].dev_name) == 0) { - if (map[j].dir == IFXMIPS_DMA_RX) { - dma_chan[j].dir = IFXMIPS_DMA_RX; - dma_devs[i].max_rx_chan_num++; - dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1] = &dma_chan[j]; - dma_devs[i].rx_chan[dma_devs[i].max_rx_chan_num - 1]->pri = map[j].pri; - dma_chan[j].dma_dev = (void *)&dma_devs[i]; - } else if (map[j].dir == IFXMIPS_DMA_TX) { - /*TX direction */ - dma_chan[j].dir = IFXMIPS_DMA_TX; - dma_devs[i].max_tx_chan_num++; - dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1] = &dma_chan[j]; - dma_devs[i].tx_chan[dma_devs[i].max_tx_chan_num - 1]->pri = map[j].pri; - dma_chan[j].dma_dev = (void *)&dma_devs[i]; - } else { - printk(KERN_WARNING "WRONG DMA MAP!\n"); - } - } - } - } - - return 0; -} - -void dma_chip_init(void) -{ - int i; - - /* enable DMA from PMU */ - ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA); - - /* reset DMA */ - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CTRL) | 1, IFXMIPS_DMA_CTRL); - - /* disable all interrupts */ - ifxmips_w32(0, IFXMIPS_DMA_IRNEN); - - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) { - ifxmips_w32(i, IFXMIPS_DMA_CS); - ifxmips_w32(0x2, IFXMIPS_DMA_CCTRL); - ifxmips_w32(0x80000040, IFXMIPS_DMA_CPOLL); - ifxmips_w32(ifxmips_r32(IFXMIPS_DMA_CCTRL) & ~0x1, IFXMIPS_DMA_CCTRL); - } -} - -int ifxmips_dma_init(void) -{ - int i; - - dma_chip_init(); - if (map_dma_chan(default_dma_map)) - BUG(); - - g_desc_list = (u64 *)KSEG1ADDR(__get_free_page(GFP_DMA)); - - if (g_desc_list == NULL) { - printk(KERN_WARNING "no memory for desriptor\n"); - return -ENOMEM; - } - - memset(g_desc_list, 0, PAGE_SIZE); - - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) { - dma_chan[i].desc_base = (u32)g_desc_list + i * IFXMIPS_DMA_DESCRIPTOR_OFFSET * 8; - dma_chan[i].curr_desc = 0; - dma_chan[i].desc_len = IFXMIPS_DMA_DESCRIPTOR_OFFSET; - - ifxmips_w32(i, IFXMIPS_DMA_CS); - ifxmips_w32((u32)CPHYSADDR(dma_chan[i].desc_base), IFXMIPS_DMA_CDBA); - ifxmips_w32(dma_chan[i].desc_len, IFXMIPS_DMA_CDLEN); - } - - return 0; -} - -arch_initcall(ifxmips_dma_init); - -void dma_cleanup(void) -{ - int i; - - free_page(KSEG0ADDR((unsigned long) g_desc_list)); - for (i = 0; i < MAX_DMA_CHANNEL_NUM; i++) - free_irq(dma_chan[i].irq, (void *)&dma_interrupt); -} - -MODULE_LICENSE("GPL"); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c b/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c deleted file mode 100644 index 1ac00ded5b..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/gpio.c +++ /dev/null @@ -1,345 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2004 btxu Generate from INCA-IP project - * Copyright (C) 2005 Jin-Sze.Sow Comments edited - * Copyright (C) 2006 Huang Xiaogang Modification & verification on Danube chip - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#define MAX_PORTS 2 -#define PINS_PER_PORT 16 - -#define IFXMIPS_GPIO_SANITY {if (port > MAX_PORTS || pin > PINS_PER_PORT) return -EINVAL; } - -#define GPIO_TO_PORT(x) ((x > 15) ? (1) : (0)) -#define GPIO_TO_GPIO(x) ((x > 15) ? (x - 16) : (x)) - -int -ifxmips_port_reserve_pin(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - printk(KERN_INFO "%s : call to obseleted function\n", __func__); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_reserve_pin); - -int -ifxmips_port_free_pin(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - printk(KERN_INFO "%s : call to obseleted function\n", __func__); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_free_pin); - -int -ifxmips_port_set_open_drain(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_OD + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_open_drain); - -int -ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OD + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_OD + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_open_drain); - -int -ifxmips_port_set_pudsel(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_pudsel); - -int -ifxmips_port_clear_pudsel(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_PUDSEL + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_pudsel); - -int -ifxmips_port_set_puden(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_puden); - -int -ifxmips_port_clear_puden(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_PUDEN + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_puden); - -int -ifxmips_port_set_stoff(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_STOFF + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_stoff); - -int -ifxmips_port_clear_stoff(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_STOFF + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_STOFF + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_stoff); - -int -ifxmips_port_set_dir_out(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_DIR + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_dir_out); - -int -ifxmips_port_set_dir_in(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_DIR + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_DIR + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_dir_in); - -int -ifxmips_port_set_output(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_OUT + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_output); - -int -ifxmips_port_clear_output(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_OUT + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_OUT + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_output); - -int -ifxmips_port_get_input(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - if (ifxmips_r32(IFXMIPS_GPIO_P0_IN + (port * 0xC)) & (1 << pin)) - return 0; - else - return 1; -} -EXPORT_SYMBOL(ifxmips_port_get_input); - -int -ifxmips_port_set_altsel0(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_altsel0); - -int -ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_ALTSEL0 + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_altsel0); - -int -ifxmips_port_set_altsel1(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) | (1 << pin), - IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_set_altsel1); - -int -ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin) -{ - IFXMIPS_GPIO_SANITY; - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)) & ~(1 << pin), - IFXMIPS_GPIO_P0_ALTSEL1 + (port * 0xC)); - return 0; -} -EXPORT_SYMBOL(ifxmips_port_clear_altsel1); - -static void -ifxmips_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) -{ - int port = GPIO_TO_PORT(offset); - int gpio = GPIO_TO_GPIO(offset); - if(value) - ifxmips_port_set_output(port, gpio); - else - ifxmips_port_clear_output(port, gpio); -} - -static int -ifxmips_gpio_get(struct gpio_chip *chip, unsigned int offset) -{ - int port = GPIO_TO_PORT(offset); - int gpio = GPIO_TO_GPIO(offset); - return ifxmips_port_get_input(port, gpio); -} - -static int -ifxmips_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) -{ - int port = GPIO_TO_PORT(offset); - int gpio = GPIO_TO_GPIO(offset); - ifxmips_port_set_open_drain(port, gpio); - ifxmips_port_clear_altsel0(port, gpio); - ifxmips_port_clear_altsel1(port, gpio); - ifxmips_port_set_dir_in(port, gpio); - return 0; -} - -static int -ifxmips_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value) -{ - int port = GPIO_TO_PORT(offset); - int gpio = GPIO_TO_GPIO(offset); - ifxmips_port_clear_open_drain(port, gpio); - ifxmips_port_clear_altsel0(port, gpio); - ifxmips_port_clear_altsel1(port, gpio); - ifxmips_port_set_dir_out(port, gpio); - ifxmips_gpio_set(chip, offset, value); - return 0; -} - -int -gpio_to_irq(unsigned int gpio) -{ - return -EINVAL; -} -EXPORT_SYMBOL(gpio_to_irq); - -struct gpio_chip -ifxmips_gpio_chip = -{ - .label = "ifxmips-gpio", - .direction_input = ifxmips_gpio_direction_input, - .direction_output = ifxmips_gpio_direction_output, - .get = ifxmips_gpio_get, - .set = ifxmips_gpio_set, - .base = 0, - .ngpio = 32, -}; - -static int -ifxmips_gpio_probe(struct platform_device *dev) -{ - gpiochip_add(&ifxmips_gpio_chip); - return 0; -} - -static int -ifxmips_gpio_remove(struct platform_device *pdev) -{ - gpiochip_remove(&ifxmips_gpio_chip); - return 0; -} - -static struct platform_driver -ifxmips_gpio_driver = { - .probe = ifxmips_gpio_probe, - .remove = ifxmips_gpio_remove, - .driver = { - .name = "ifxmips_gpio", - .owner = THIS_MODULE, - }, -}; - -int __init -ifxmips_gpio_init(void) -{ - int ret = platform_driver_register(&ifxmips_gpio_driver); - if (ret) - printk(KERN_INFO "ifxmips_gpio : Error registering platfom driver!"); - return ret; -} - -void __exit -ifxmips_gpio_exit(void) -{ - platform_driver_unregister(&ifxmips_gpio_driver); -} - -module_init(ifxmips_gpio_init); -module_exit(ifxmips_gpio_exit); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/irq.c b/target/linux/ifxmips/files/arch/mips/ifxmips/irq.c deleted file mode 100644 index b7326c72d2..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/irq.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2005 Wu Qi Ming infineon - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -void ifxmips_disable_irq(unsigned int irq_nr) -{ - int i; - u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER; - - irq_nr -= INT_NUM_IRQ0; - for (i = 0; i <= 4; i++) { - if (irq_nr < INT_NUM_IM_OFFSET) { - ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr), - ifxmips_ier); - return; - } - ifxmips_ier += IFXMIPS_ICU_OFFSET; - irq_nr -= INT_NUM_IM_OFFSET; - } -} -EXPORT_SYMBOL(ifxmips_disable_irq); - -void ifxmips_mask_and_ack_irq(unsigned int irq_nr) -{ - int i; - u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER; - u32 *ifxmips_isr = IFXMIPS_ICU_IM0_ISR; - - irq_nr -= INT_NUM_IRQ0; - for (i = 0; i <= 4; i++) { - if (irq_nr < INT_NUM_IM_OFFSET) { - ifxmips_w32(ifxmips_r32(ifxmips_ier) & ~(1 << irq_nr), - ifxmips_ier); - ifxmips_w32((1 << irq_nr), ifxmips_isr); - return; - } - ifxmips_ier += IFXMIPS_ICU_OFFSET; - ifxmips_isr += IFXMIPS_ICU_OFFSET; - irq_nr -= INT_NUM_IM_OFFSET; - } -} -EXPORT_SYMBOL(ifxmips_mask_and_ack_irq); - -void ifxmips_enable_irq(unsigned int irq_nr) -{ - int i; - u32 *ifxmips_ier = IFXMIPS_ICU_IM0_IER; - - irq_nr -= INT_NUM_IRQ0; - for (i = 0; i <= 4; i++) { - if (irq_nr < INT_NUM_IM_OFFSET) { - ifxmips_w32(ifxmips_r32(ifxmips_ier) | (1 << irq_nr), - ifxmips_ier); - return; - } - ifxmips_ier += IFXMIPS_ICU_OFFSET; - irq_nr -= INT_NUM_IM_OFFSET; - } -} -EXPORT_SYMBOL(ifxmips_enable_irq); - -static unsigned int ifxmips_startup_irq(unsigned int irq) -{ - ifxmips_enable_irq(irq); - return 0; -} - -static void ifxmips_end_irq(unsigned int irq) -{ - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) - ifxmips_enable_irq(irq); -} - -static struct hw_interrupt_type ifxmips_irq_type = { - "IFXMIPS", - .startup = ifxmips_startup_irq, - .enable = ifxmips_enable_irq, - .disable = ifxmips_disable_irq, - .unmask = ifxmips_enable_irq, - .ack = ifxmips_end_irq, - .mask = ifxmips_disable_irq, - .mask_ack = ifxmips_mask_and_ack_irq, - .end = ifxmips_end_irq, -}; - -/* silicon bug causes only the msb set to 1 to be valid. all - other bits might be bogus */ -static inline int ls1bit32(unsigned long x) -{ - __asm__ ( - ".set push \n" - ".set mips32 \n" - "clz %0, %1 \n" - ".set pop \n" - : "=r" (x) - : "r" (x)); - return 31 - x; -} - -void ifxmips_hw_irqdispatch(int module) -{ - u32 irq; - - irq = ifxmips_r32(IFXMIPS_ICU_IM0_IOSR + (module * IFXMIPS_ICU_OFFSET)); - if (irq == 0) - return; - - /* we need to do this due to a silicon bug */ - irq = ls1bit32(irq); - do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); - - if ((irq == 22) && (module == 0)) - ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_ISTAT) | 0x10, - IFXMIPS_EBU_PCC_ISTAT); -} - -#ifdef CONFIG_CPU_MIPSR2_IRQ_VI -#define DEFINE_HWx_IRQDISPATCH(x) \ -static void ifxmips_hw ## x ## _irqdispatch(void)\ -{\ - ifxmips_hw_irqdispatch(x); \ -} -static void ifxmips_hw5_irqdispatch(void) -{ - do_IRQ(MIPS_CPU_TIMER_IRQ); -} -DEFINE_HWx_IRQDISPATCH(0) -DEFINE_HWx_IRQDISPATCH(1) -DEFINE_HWx_IRQDISPATCH(2) -DEFINE_HWx_IRQDISPATCH(3) -DEFINE_HWx_IRQDISPATCH(4) -/*DEFINE_HWx_IRQDISPATCH(5)*/ -#endif /* #ifdef CONFIG_CPU_MIPSR2_IRQ_VI */ - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - unsigned int i; - - if (pending & CAUSEF_IP7) { - do_IRQ(MIPS_CPU_TIMER_IRQ); - goto out; - } else { - for (i = 0; i < 5; i++) { - if (pending & (CAUSEF_IP2 << i)) { - ifxmips_hw_irqdispatch(i); - goto out; - } - } - } - printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status()); - -out: - return; -} - -static struct irqaction cascade = { - .handler = no_action, - .flags = IRQF_DISABLED, - .name = "cascade", -}; - -void __init arch_init_irq(void) -{ - int i; - - for (i = 0; i < 5; i++) - ifxmips_w32(0, IFXMIPS_ICU_IM0_IER + (i * IFXMIPS_ICU_OFFSET)); - - mips_cpu_irq_init(); - - for (i = 2; i <= 6; i++) - setup_irq(i, &cascade); - -#ifdef CONFIG_CPU_MIPSR2_IRQ_VI - if (cpu_has_vint) { - printk(KERN_INFO "Setting up vectored interrupts\n"); - set_vi_handler(2, ifxmips_hw0_irqdispatch); - set_vi_handler(3, ifxmips_hw1_irqdispatch); - set_vi_handler(4, ifxmips_hw2_irqdispatch); - set_vi_handler(5, ifxmips_hw3_irqdispatch); - set_vi_handler(6, ifxmips_hw4_irqdispatch); - set_vi_handler(7, ifxmips_hw5_irqdispatch); - } -#endif /* CONFIG_CPU_MIPSR2_IRQ_VI */ - - for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); - i++) - set_irq_chip_and_handler(i, &ifxmips_irq_type, - handle_level_irq); - - #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) - set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | - IE_IRQ3 | IE_IRQ4 | IE_IRQ5); - #else - set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 | - IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); - #endif -} - -void __cpuinit arch_fixup_c0_irqs(void) -{ - /* FIXME: check for CPUID and only do fix for specific chips/versions */ - cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; - cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ; -} diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c b/target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c deleted file mode 100644 index 29d710451b..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/pmu.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - * - * code used for handling the power management unit of the danube. using - * the pmu we can turn the power of the seperate ip cores on/off. - */ - -#include -#include -#include - -#include - -void ifxmips_pmu_enable(unsigned int module) -{ - int err = 1000000; - - ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) & ~module, - IFXMIPS_PMU_PWDCR); - while (--err && (ifxmips_r32(IFXMIPS_PMU_PWDSR) & module)) - ; - - if (!err) - panic("activating PMU module failed!"); -} -EXPORT_SYMBOL(ifxmips_pmu_enable); - -void ifxmips_pmu_disable(unsigned int module) -{ - ifxmips_w32(ifxmips_r32(IFXMIPS_PMU_PWDCR) | module, IFXMIPS_PMU_PWDCR); -} -EXPORT_SYMBOL(ifxmips_pmu_disable); diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c b/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c deleted file mode 100644 index ef5a68a819..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/prom.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2005 Wu Qi Ming infineon - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include - -#include - -#include - -static char buf[1024]; /* for prom_printf() */ - -/* for voice cpu (MIPS24K) */ -unsigned int *prom_cp1_base; -unsigned int prom_cp1_size; - -/* for Multithreading (APRP) on MIPS34K */ -unsigned long physical_memsize; - -/* early printk on asc0 or asc1 ? */ -#ifdef CONFIG_IFXMIPS_PROM_ASC0 -#define IFXMIPS_ASC_DIFF 0 -#else -#define IFXMIPS_ASC_DIFF IFXMIPS_ASC_BASE_DIFF -#endif - -static inline u32 asc_r32(unsigned long r) -{ - return ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r)); -} - -static inline void asc_w32(u32 v, unsigned long r) -{ - ifxmips_w32(v, (u32 *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_DIFF + r)); -} - -void prom_free_prom_memory(void) -{ -} - -void prom_putchar(char c) -{ - unsigned long flags; - - local_irq_save(flags); - while ((asc_r32(IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) >> ASCFSTAT_TXFFLOFF) - ; - - if (c == '\n') - asc_w32('\r', IFXMIPS_ASC_TBUF); - asc_w32(c, IFXMIPS_ASC_TBUF); - local_irq_restore(flags); -} - -void prom_printf(const char *fmt, ...) -{ - va_list args; - int l; - char *p, *buf_end; - - va_start(args, fmt); - l = vsprintf(buf, fmt, args); - va_end(args); - buf_end = buf + l; - - for (p = buf; p < buf_end; p++) - prom_putchar(*p); -} - -unsigned int *prom_get_cp1_base(void) -{ - return prom_cp1_base; -} -EXPORT_SYMBOL(prom_get_cp1_base); - -unsigned int prom_get_cp1_size(void) -{ - /* return size im MB */ - return prom_cp1_size>>20; -} -EXPORT_SYMBOL(prom_get_cp1_size); - -void __init prom_init(void) -{ - int argc = fw_arg0; - char **argv = (char **) fw_arg1; - char **envp = (char **) fw_arg2; - - int memsize = 16; /* assume 16M as default */ - int i; - - mips_machtype = MACH_INFINEON_IFXMIPS; - - if (argc) { - argv = (char **)KSEG1ADDR((unsigned long)argv); - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - char *a = (char *)KSEG1ADDR(argv[i]); - if (!argv[i]) - continue; - /* for voice cpu on Twinpass/Danube */ - if (cpu_data[0].cputype == CPU_24K) - if (!strncmp(a, "cp1_size=", 9)) { - prom_cp1_size = memparse(a + 9, &a); - continue; - } - if (strlen(arcs_cmdline) + strlen(a + 1) >= sizeof(arcs_cmdline)) { - prom_printf("cmdline overflow, skipping: %s\n", a); - break; - } - strcat(arcs_cmdline, a); - strcat(arcs_cmdline, " "); - } - if (!*arcs_cmdline) - strcpy(&(arcs_cmdline[0]), - "console=ttyS0,115200 rootfstype=squashfs,jffs2"); - } - envp = (char **)KSEG1ADDR((unsigned long)envp); - while (*envp) { - char *e = (char *)KSEG1ADDR(*envp); - - if (!strncmp(e, "memsize=", 8)) { - e += 8; - memsize = simple_strtoul(e, NULL, 10); - } - envp++; - } - memsize *= 1024 * 1024; - - /* only on Twinpass/Danube a second CPU is used for Voice */ - if ((cpu_data[0].cputype == CPU_24K) && (prom_cp1_size)) { - memsize -= prom_cp1_size; - prom_cp1_base = (unsigned int *)KSEG1ADDR(memsize); - - prom_printf("Using %dMB Ram and reserving %dMB for cp1\n", - memsize>>20, prom_cp1_size>>20); - } - - add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); -} diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c b/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c deleted file mode 100644 index c3119bce7d..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/reset.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ - -#include -#include -#include - -#include -#include -#include - -static void ifxmips_machine_restart(char *command) -{ - printk(KERN_NOTICE "System restart\n"); - local_irq_disable(); - - ifxmips_w32(ifxmips_r32(IFXMIPS_RCU_RST) | IFXMIPS_RCU_RST_ALL, - IFXMIPS_RCU_RST); - for (;;) - ; -} - -static void ifxmips_machine_halt(void) -{ - printk(KERN_NOTICE "System halted.\n"); - local_irq_disable(); - for (;;) - ; -} - -static void ifxmips_machine_power_off(void) -{ - printk(KERN_NOTICE "Please turn off the power now.\n"); - local_irq_disable(); - for (;;) - ; -} - -void ifxmips_reboot_setup(void) -{ - _machine_restart = ifxmips_machine_restart; - _machine_halt = ifxmips_machine_halt; - pm_power_off = ifxmips_machine_power_off; -} diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c b/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c deleted file mode 100644 index 06fa2f0b4b..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/setup.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2004 peng.liu@infineon.com - * Copyright (C) 2007 John Crispin - */ - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -static unsigned int r4k_offset; -static unsigned int r4k_cur; - -/* required in arch/mips/kernel/kspd.c */ -unsigned long cpu_khz; - -extern void ifxmips_reboot_setup(void); - -unsigned int ifxmips_get_cpu_ver(void) -{ - return (ifxmips_r32(IFXMIPS_MPS_CHIPID) & 0xF0000000) >> 28; -} -EXPORT_SYMBOL(ifxmips_get_cpu_ver); - -static inline u32 ifxmips_get_counter_resolution(void) -{ - u32 res; - __asm__ __volatile__( - ".set push\n" - ".set mips32r2\n" - ".set noreorder\n" - "rdhwr %0, $3\n" - "ehb\n" - ".set pop\n" - : "=&r" (res) - : /* no input */ - : "memory"); - instruction_hazard(); - return res; -} - -void __init plat_time_init(void) -{ - mips_hpt_frequency = ifxmips_get_cpu_hz() / ifxmips_get_counter_resolution(); - r4k_cur = (read_c0_count() + r4k_offset); - write_c0_compare(r4k_cur); - - ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI); - ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC); /* set clock divider to 1 */ - cpu_khz = ifxmips_get_cpu_hz(); -} - -void __init plat_mem_setup(void) -{ - u32 status; - prom_printf("This %s system has a cpu rev of %d\n", get_system_type(), ifxmips_get_cpu_ver()); - - /* make sure to have no "reverse endian" for user mode! */ - status = read_c0_status(); - status &= (~(1<<25)); - write_c0_status(status); - - ifxmips_reboot_setup(); - - ioport_resource.start = IOPORT_RESOURCE_START; - ioport_resource.end = IOPORT_RESOURCE_END; - iomem_resource.start = IOMEM_RESOURCE_START; - iomem_resource.end = IOMEM_RESOURCE_END; -} diff --git a/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c b/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c deleted file mode 100644 index 31e606c85a..0000000000 --- a/target/linux/ifxmips/files/arch/mips/ifxmips/timer.c +++ /dev/null @@ -1,829 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 - -#ifdef TIMER1A -#define FIRST_TIMER TIMER1A -#else -#define FIRST_TIMER 2 -#endif - -/* - * GPTC divider is set or not. - */ -#define GPTU_CLC_RMC_IS_SET 0 - -/* - * Timer Interrupt (IRQ) - */ -/* Must be adjusted when ICU driver is available */ -#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) - -/* - * Bits Operation - */ -#define GET_BITS(x, msb, lsb) \ - (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) -#define SET_BITS(x, msb, lsb, value) \ - (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ - (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) - -/* - * GPTU Register Mapping - */ -#define IFXMIPS_GPTU (KSEG1 + 0x1E100A00) -#define IFXMIPS_GPTU_CLC ((volatile u32 *)(IFXMIPS_GPTU + 0x0000)) -#define IFXMIPS_GPTU_ID ((volatile u32 *)(IFXMIPS_GPTU + 0x0008)) -#define IFXMIPS_GPTU_CON(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -#define IFXMIPS_GPTU_RUN(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -#define IFXMIPS_GPTU_RELOAD(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -#define IFXMIPS_GPTU_COUNT(n, X) ((volatile u32 *)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -#define IFXMIPS_GPTU_IRNEN ((volatile u32 *)(IFXMIPS_GPTU + 0x00F4)) -#define IFXMIPS_GPTU_IRNICR ((volatile u32 *)(IFXMIPS_GPTU + 0x00F8)) -#define IFXMIPS_GPTU_IRNCR ((volatile u32 *)(IFXMIPS_GPTU + 0x00FC)) - -/* - * Clock Control Register - */ -#define GPTU_CLC_SMC GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16) -#define GPTU_CLC_RMC GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8) -#define GPTU_CLC_FSOE (*IFXMIPS_GPTU_CLC & (1 << 5)) -#define GPTU_CLC_EDIS (*IFXMIPS_GPTU_CLC & (1 << 3)) -#define GPTU_CLC_SPEN (*IFXMIPS_GPTU_CLC & (1 << 2)) -#define GPTU_CLC_DISS (*IFXMIPS_GPTU_CLC & (1 << 1)) -#define GPTU_CLC_DISR (*IFXMIPS_GPTU_CLC & (1 << 0)) - -#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) -#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) -#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) -#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) -#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) -#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) -#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) - -/* - * ID Register - */ -#define GPTU_ID_ID GET_BITS(*IFXMIPS_GPTU_ID, 15, 8) -#define GPTU_ID_CFG GET_BITS(*IFXMIPS_GPTU_ID, 7, 5) -#define GPTU_ID_REV GET_BITS(*IFXMIPS_GPTU_ID, 4, 0) - -/* - * Control Register of Timer/Counter nX - * n is the index of block (1 based index) - * X is either A or B - */ -#define GPTU_CON_SRC_EG(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 10)) -#define GPTU_CON_SRC_EXT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 9)) -#define GPTU_CON_SYNC(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 8)) -#define GPTU_CON_EDGE(n, X) GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6) -#define GPTU_CON_INV(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 5)) -#define GPTU_CON_EXT(n, X) (*IFXMIPS_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ -#define GPTU_CON_STP(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 3)) -#define GPTU_CON_CNT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 2)) -#define GPTU_CON_DIR(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 1)) -#define GPTU_CON_EN(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 0)) - -#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) -#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) -#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) -#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) -#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) -#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) -#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) -#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) -#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) - -#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) -#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) -#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) - -#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) - -#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) -#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) -#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) -#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) -#define TIMER_FLAG_NONE_EDGE 0x0000 -#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) -#define TIMER_FLAG_REAL 0x0000 -#define TIMER_FLAG_INVERT 0x0040 -#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) -#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) -#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) -#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 -#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) -#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) - -struct timer_dev_timer { - unsigned int f_irq_on; - unsigned int irq; - unsigned int flag; - unsigned long arg1; - unsigned long arg2; -}; - -struct timer_dev { - struct mutex gptu_mutex; - unsigned int number_of_timers; - unsigned int occupation; - unsigned int f_gptu_on; - struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; -}; - -static int gptu_ioctl(struct inode *, struct file *, unsigned int, unsigned long); -static int gptu_open(struct inode *, struct file *); -static int gptu_release(struct inode *, struct file *); - -static struct file_operations gptu_fops = { - .owner = THIS_MODULE, - .ioctl = gptu_ioctl, - .open = gptu_open, - .release = gptu_release -}; - -static struct miscdevice gptu_miscdev = { - .minor = MISC_DYNAMIC_MINOR, - .name = "gptu", - .fops = &gptu_fops, -}; - -static struct timer_dev timer_dev; - -static irqreturn_t timer_irq_handler(int irq, void *p) -{ - unsigned int timer; - unsigned int flag; - struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; - - timer = irq - TIMER_INTERRUPT; - if (timer < timer_dev.number_of_timers - && dev_timer == &timer_dev.timer[timer]) { - /* Clear interrupt. */ - ifxmips_w32(1 << timer, IFXMIPS_GPTU_IRNCR); - - /* Call user hanler or signal. */ - flag = dev_timer->flag; - if (!(timer & 0x01) - || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { - /* 16-bit timer or timer A of 32-bit timer */ - switch (TIMER_FLAG_MASK_HANDLE(flag)) { - case TIMER_FLAG_CALLBACK_IN_IRQ: - case TIMER_FLAG_CALLBACK_IN_HB: - if (dev_timer->arg1) - (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); - break; - case TIMER_FLAG_SIGNAL: - send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); - break; - } - } - } - return IRQ_HANDLED; -} - -static inline void ifxmips_enable_gptu(void) -{ - ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT); - - /* Set divider as 1, disable write protection for SPEN, enable module. */ - *IFXMIPS_GPTU_CLC = - GPTU_CLC_SMC_SET(0x00) | - GPTU_CLC_RMC_SET(0x01) | - GPTU_CLC_FSOE_SET(0) | - GPTU_CLC_SBWE_SET(1) | - GPTU_CLC_EDIS_SET(0) | - GPTU_CLC_SPEN_SET(0) | - GPTU_CLC_DISR_SET(0); -} - -static inline void ifxmips_disable_gptu(void) -{ - ifxmips_w32(0x00, IFXMIPS_GPTU_IRNEN); - ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR); - - /* Set divider as 0, enable write protection for SPEN, disable module. */ - *IFXMIPS_GPTU_CLC = - GPTU_CLC_SMC_SET(0x00) | - GPTU_CLC_RMC_SET(0x00) | - GPTU_CLC_FSOE_SET(0) | - GPTU_CLC_SBWE_SET(0) | - GPTU_CLC_EDIS_SET(0) | - GPTU_CLC_SPEN_SET(0) | - GPTU_CLC_DISR_SET(1); - - ifxmips_pmu_disable(IFXMIPS_PMU_PWDCR_GPT); -} - -int ifxmips_request_timer(unsigned int timer, unsigned int flag, - unsigned long value, unsigned long arg1, unsigned long arg2) -{ - int ret = 0; - unsigned int con_reg, irnen_reg; - int n, X; - - if (timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", - timer, flag, value); - - if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) - value &= 0xFFFF; - else - timer &= ~0x01; - - mutex_lock(&timer_dev.gptu_mutex); - - /* - * Allocate timer. - */ - if (timer < FIRST_TIMER) { - unsigned int mask; - unsigned int shift; - /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ - unsigned int offset = TIMER2A; - - /* - * Pick up a free timer. - */ - if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { - mask = 1 << offset; - shift = 1; - } else { - mask = 3 << offset; - shift = 2; - } - for (timer = offset; - timer < offset + timer_dev.number_of_timers; - timer += shift, mask <<= shift) - if (!(timer_dev.occupation & mask)) { - timer_dev.occupation |= mask; - break; - } - if (timer >= offset + timer_dev.number_of_timers) { - printk("failed![%d]\n", __LINE__); - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } else - ret = timer; - } else { - register unsigned int mask; - - /* - * Check if the requested timer is free. - */ - mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if ((timer_dev.occupation & mask)) { - printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", - __LINE__, mask, timer_dev.occupation); - mutex_unlock(&timer_dev.gptu_mutex); - return -EBUSY; - } else { - timer_dev.occupation |= mask; - ret = 0; - } - } - - /* - * Prepare control register value. - */ - switch (TIMER_FLAG_MASK_EDGE(flag)) { - default: - case TIMER_FLAG_NONE_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x00); - break; - case TIMER_FLAG_RISE_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x01); - break; - case TIMER_FLAG_FALL_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x02); - break; - case TIMER_FLAG_ANY_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x03); - break; - } - if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) - con_reg |= - TIMER_FLAG_MASK_SRC(flag) == - TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : - GPTU_CON_SRC_EXT_SET(0); - else - con_reg |= - TIMER_FLAG_MASK_SRC(flag) == - TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : - GPTU_CON_SRC_EG_SET(0); - con_reg |= - TIMER_FLAG_MASK_SYNC(flag) == - TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : - GPTU_CON_SYNC_SET(1); - con_reg |= - TIMER_FLAG_MASK_INVERT(flag) == - TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); - con_reg |= - TIMER_FLAG_MASK_SIZE(flag) == - TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : - GPTU_CON_EXT_SET(1); - con_reg |= - TIMER_FLAG_MASK_STOP(flag) == - TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); - con_reg |= - TIMER_FLAG_MASK_TYPE(flag) == - TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : - GPTU_CON_CNT_SET(1); - con_reg |= - TIMER_FLAG_MASK_DIR(flag) == - TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); - - /* - * Fill up running data. - */ - timer_dev.timer[timer - FIRST_TIMER].flag = flag; - timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; - timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; - if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) - timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; - - /* - * Enable GPTU module. - */ - if (!timer_dev.f_gptu_on) { - ifxmips_enable_gptu(); - timer_dev.f_gptu_on = 1; - } - - /* - * Enable IRQ. - */ - if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { - if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) - timer_dev.timer[timer - FIRST_TIMER].arg1 = - (unsigned long) find_task_by_vpid((int) arg1); - - irnen_reg = 1 << (timer - FIRST_TIMER); - - if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL - || (TIMER_FLAG_MASK_HANDLE(flag) == - TIMER_FLAG_CALLBACK_IN_IRQ - && timer_dev.timer[timer - FIRST_TIMER].arg1)) { - enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); - timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; - } - } else - irnen_reg = 0; - - /* - * Write config register, reload value and enable interrupt. - */ - n = timer >> 1; - X = timer & 0x01; - *IFXMIPS_GPTU_CON(n, X) = con_reg; - *IFXMIPS_GPTU_RELOAD(n, X) = value; - /* printk("reload value = %d\n", (u32)value); */ - *IFXMIPS_GPTU_IRNEN |= irnen_reg; - - mutex_unlock(&timer_dev.gptu_mutex); - printk("successful!\n"); - return ret; -} -EXPORT_SYMBOL(ifxmips_request_timer); - -int ifxmips_free_timer(unsigned int timer) -{ - unsigned int flag; - unsigned int mask; - int n, X; - - if (!timer_dev.f_gptu_on) - return -EINVAL; - - if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if (((timer_dev.occupation & mask) ^ mask)) { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - if (GPTU_CON_EN(n, X)) - *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); - - *IFXMIPS_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); - *IFXMIPS_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); - - if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { - disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); - timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; - } - - timer_dev.occupation &= ~mask; - if (!timer_dev.occupation && timer_dev.f_gptu_on) { - ifxmips_disable_gptu(); - timer_dev.f_gptu_on = 0; - } - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} -EXPORT_SYMBOL(ifxmips_free_timer); - -int ifxmips_start_timer(unsigned int timer, int is_resume) -{ - unsigned int flag; - unsigned int mask; - int n, X; - - if (!timer_dev.f_gptu_on) - return -EINVAL; - - if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE(flag) == - TIMER_FLAG_16BIT ? 1 : 3) << timer; - if (((timer_dev.occupation & mask) ^ mask)) { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} -EXPORT_SYMBOL(ifxmips_start_timer); - -int ifxmips_stop_timer(unsigned int timer) -{ - unsigned int flag; - unsigned int mask; - int n, X; - - if (!timer_dev.f_gptu_on) - return -EINVAL; - - if (timer < FIRST_TIMER - || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if (((timer_dev.occupation & mask) ^ mask)) { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - *IFXMIPS_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} -EXPORT_SYMBOL(ifxmips_stop_timer); - -int ifxmips_reset_counter_flags(u32 timer, u32 flags) -{ - unsigned int oflag; - unsigned int mask, con_reg; - int n, X; - - if (!timer_dev.f_gptu_on) - return -EINVAL; - - if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - oflag = timer_dev.timer[timer - FIRST_TIMER].flag; - if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if (((timer_dev.occupation & mask) ^ mask)) { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - switch (TIMER_FLAG_MASK_EDGE(flags)) { - default: - case TIMER_FLAG_NONE_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x00); - break; - case TIMER_FLAG_RISE_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x01); - break; - case TIMER_FLAG_FALL_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x02); - break; - case TIMER_FLAG_ANY_EDGE: - con_reg = GPTU_CON_EDGE_SET(0x03); - break; - } - if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) - con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); - else - con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); - con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); - con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); - con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); - con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); - con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); - con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); - - timer_dev.timer[timer - FIRST_TIMER].flag = flags; - if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) - timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; - - n = timer >> 1; - X = timer & 0x01; - - *IFXMIPS_GPTU_CON(n, X) = con_reg; - smp_wmb(); - printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *IFXMIPS_GPTU_CON(n, X)); - mutex_unlock(&timer_dev.gptu_mutex); - return 0; -} -EXPORT_SYMBOL(ifxmips_reset_counter_flags); - -int ifxmips_get_count_value(unsigned int timer, unsigned long *value) -{ - unsigned int flag; - unsigned int mask; - int n, X; - - if (!timer_dev.f_gptu_on) - return -EINVAL; - - if (timer < FIRST_TIMER - || timer >= FIRST_TIMER + timer_dev.number_of_timers) - return -EINVAL; - - mutex_lock(&timer_dev.gptu_mutex); - - flag = timer_dev.timer[timer - FIRST_TIMER].flag; - if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) - timer &= ~0x01; - - mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; - if (((timer_dev.occupation & mask) ^ mask)) { - mutex_unlock(&timer_dev.gptu_mutex); - return -EINVAL; - } - - n = timer >> 1; - X = timer & 0x01; - - *value = *IFXMIPS_GPTU_COUNT(n, X); - - mutex_unlock(&timer_dev.gptu_mutex); - - return 0; -} -EXPORT_SYMBOL(ifxmips_get_count_value); - -u32 ifxmips_cal_divider(unsigned long freq) -{ - u64 module_freq, fpi = cgu_get_fpi_bus_clock(2); - u32 clock_divider = 1; - module_freq = fpi * 1000; - do_div(module_freq, clock_divider * freq); - return module_freq; -} -EXPORT_SYMBOL(ifxmips_cal_divider); - -int ifxmips_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, - int is_ext_src, unsigned int handle_flag, unsigned long arg1, - unsigned long arg2) -{ - unsigned long divider; - unsigned int flag; - - divider = ifxmips_cal_divider(freq); - if (divider == 0) - return -EINVAL; - flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) - | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) - | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) - | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN - | TIMER_FLAG_MASK_HANDLE(handle_flag); - - printk(KERN_INFO "ifxmips_set_timer(%d, %d), divider = %lu\n", - timer, freq, divider); - return ifxmips_request_timer(timer, flag, divider, arg1, arg2); -} -EXPORT_SYMBOL(ifxmips_set_timer); - -int ifxmips_set_counter(unsigned int timer, unsigned int flag, u32 reload, - unsigned long arg1, unsigned long arg2) -{ - printk(KERN_INFO "ifxmips_set_counter(%d, %#x, %d)\n", timer, flag, reload); - return ifxmips_request_timer(timer, flag, reload, arg1, arg2); -} -EXPORT_SYMBOL(ifxmips_set_counter); - -static int gptu_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) -{ - int ret; - struct gptu_ioctl_param param; - - if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param))) - return -EFAULT; - copy_from_user(¶m, (void *) arg, sizeof(param)); - - if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER - || GPTU_SET_COUNTER) && param.timer < 2) - || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) - && !access_ok(VERIFY_WRITE, arg, - sizeof(struct gptu_ioctl_param))) - return -EFAULT; - - switch (cmd) { - case GPTU_REQUEST_TIMER: - ret = ifxmips_request_timer(param.timer, param.flag, param.value, - (unsigned long) param.pid, - (unsigned long) param.sig); - if (ret > 0) { - copy_to_user(&((struct gptu_ioctl_param *) arg)-> - timer, &ret, sizeof(&ret)); - ret = 0; - } - break; - case GPTU_FREE_TIMER: - ret = ifxmips_free_timer(param.timer); - break; - case GPTU_START_TIMER: - ret = ifxmips_start_timer(param.timer, param.flag); - break; - case GPTU_STOP_TIMER: - ret = ifxmips_stop_timer(param.timer); - break; - case GPTU_GET_COUNT_VALUE: - ret = ifxmips_get_count_value(param.timer, ¶m.value); - if (!ret) - copy_to_user(&((struct gptu_ioctl_param *) arg)-> - value, ¶m.value, - sizeof(param.value)); - break; - case GPTU_CALCULATE_DIVIDER: - param.value = ifxmips_cal_divider(param.value); - if (param.value == 0) - ret = -EINVAL; - else { - copy_to_user(&((struct gptu_ioctl_param *) arg)-> - value, ¶m.value, - sizeof(param.value)); - ret = 0; - } - break; - case GPTU_SET_TIMER: - ret = ifxmips_set_timer(param.timer, param.value, - TIMER_FLAG_MASK_STOP(param.flag) != - TIMER_FLAG_ONCE ? 1 : 0, - TIMER_FLAG_MASK_SRC(param.flag) == - TIMER_FLAG_EXT_SRC ? 1 : 0, - TIMER_FLAG_MASK_HANDLE(param.flag) == - TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : - TIMER_FLAG_NO_HANDLE, - (unsigned long) param.pid, - (unsigned long) param.sig); - if (ret > 0) { - copy_to_user(&((struct gptu_ioctl_param *) arg)-> - timer, &ret, sizeof(&ret)); - ret = 0; - } - break; - case GPTU_SET_COUNTER: - ifxmips_set_counter(param.timer, param.flag, param.value, 0, 0); - if (ret > 0) { - copy_to_user(&((struct gptu_ioctl_param *) arg)-> - timer, &ret, sizeof(&ret)); - ret = 0; - } - break; - default: - ret = -ENOTTY; - } - - return ret; -} - -static int gptu_open(struct inode *inode, struct file *file) -{ - return 0; -} - -static int gptu_release(struct inode *inode, struct file *file) -{ - return 0; -} - -int __init ifxmips_gptu_init(void) -{ - int ret; - unsigned int i; - - ifxmips_w32(0, IFXMIPS_GPTU_IRNEN); - ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR); - - memset(&timer_dev, 0, sizeof(timer_dev)); - mutex_init(&timer_dev.gptu_mutex); - - ifxmips_enable_gptu(); - timer_dev.number_of_timers = GPTU_ID_CFG * 2; - ifxmips_disable_gptu(); - if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) - timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; - printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); - - ret = misc_register(&gptu_miscdev); - if (ret) { - printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); - return ret; - } else { - printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); - } - - for (i = 0; i < timer_dev.number_of_timers; i++) { - ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); - if (ret) { - for (; i >= 0; i--) - free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); - misc_deregister(&gptu_miscdev); - printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); - return ret; - } else { - timer_dev.timer[i].irq = TIMER_INTERRUPT + i; - disable_irq(timer_dev.timer[i].irq); - printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); - } - } - - return 0; -} - -void __exit ifxmips_gptu_exit(void) -{ - unsigned int i; - - for (i = 0; i < timer_dev.number_of_timers; i++) { - if (timer_dev.timer[i].f_irq_on) - disable_irq(timer_dev.timer[i].irq); - free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); - } - ifxmips_disable_gptu(); - misc_deregister(&gptu_miscdev); -} - -module_init(ifxmips_gptu_init); -module_exit(ifxmips_gptu_exit); diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips.h deleted file mode 100644 index 7d5ae23bee..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips.h +++ /dev/null @@ -1,517 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2005 infineon - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_H__ -#define _IFXMIPS_H__ - -#define ifxmips_r32(reg) __raw_readl(reg) -#define ifxmips_w32(val, reg) __raw_writel(val, reg) -#define ifxmips_w32_mask(clear, set, reg) ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg) - -/*------------ GENERAL */ - -#define BOARD_SYSTEM_TYPE "IFXMIPS" - -#define IOPORT_RESOURCE_START 0x10000000 -#define IOPORT_RESOURCE_END 0xffffffff -#define IOMEM_RESOURCE_START 0x10000000 -#define IOMEM_RESOURCE_END 0xffffffff - -#define IFXMIPS_FLASH_START 0x10000000 -#define IFXMIPS_FLASH_MAX 0x02000000 - -/*------------ ASC0/1 */ - -#define IFXMIPS_ASC_BASE_ADDR (KSEG1 + 0x1E100400) -#define IFXMIPS_ASC_BASE_DIFF (0x1E100C00 - 0x1E100400) - -#define IFXMIPS_ASC_FSTAT 0x0048 -#define IFXMIPS_ASC_TBUF 0x0020 -#define IFXMIPS_ASC_WHBSTATE 0x0018 -#define IFXMIPS_ASC_RBUF 0x0024 -#define IFXMIPS_ASC_STATE 0x0014 -#define IFXMIPS_ASC_IRNCR 0x00F8 -#define IFXMIPS_ASC_CLC 0x0000 -#define IFXMIPS_ASC_PISEL 0x0004 -#define IFXMIPS_ASC_TXFCON 0x0044 -#define IFXMIPS_ASC_RXFCON 0x0040 -#define IFXMIPS_ASC_CON 0x0010 -#define IFXMIPS_ASC_BG 0x0050 -#define IFXMIPS_ASC_IRNREN 0x00F4 - -#define IFXMIPS_ASC_CLC_DISS 0x2 -#define ASC_IRNREN_RX_BUF 0x8 -#define ASC_IRNREN_TX_BUF 0x4 -#define ASC_IRNREN_ERR 0x2 -#define ASC_IRNREN_TX 0x1 -#define ASC_IRNCR_TIR 0x4 -#define ASC_IRNCR_RIR 0x2 -#define ASC_IRNCR_EIR 0x4 -#define ASCOPT_CSIZE 0x3 -#define ASCOPT_CS7 0x1 -#define ASCOPT_CS8 0x2 -#define ASCOPT_PARENB 0x4 -#define ASCOPT_STOPB 0x8 -#define ASCOPT_PARODD 0x0 -#define ASCOPT_CREAD 0x20 -#define TXFIFO_FL 1 -#define RXFIFO_FL 1 -#define TXFIFO_FULL 16 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 -#define ASCCON_M_8ASYNC 0x0 -#define ASCCON_M_7ASYNC 0x2 -#define ASCCON_ODD 0x00000020 -#define ASCCON_STP 0x00000080 -#define ASCCON_BRS 0x00000100 -#define ASCCON_FDE 0x00000200 -#define ASCCON_R 0x00008000 -#define ASCCON_FEN 0x00020000 -#define ASCCON_ROEN 0x00080000 -#define ASCCON_TOEN 0x00100000 -#define ASCSTATE_PE 0x00010000 -#define ASCSTATE_FE 0x00020000 -#define ASCSTATE_ROE 0x00080000 -#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE) -#define ASCWHBSTATE_CLRREN 0x00000001 -#define ASCWHBSTATE_SETREN 0x00000002 -#define ASCWHBSTATE_CLRPE 0x00000004 -#define ASCWHBSTATE_CLRFE 0x00000008 -#define ASCWHBSTATE_CLRROE 0x00000020 -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - - - -/*------------ RCU */ -#define IFXMIPS_RCU_BASE_ADDR 0xBF203000 - -/* reset request */ -#define IFXMIPS_RCU_RST ((u32 *)(IFXMIPS_RCU_BASE_ADDR + 0x0010)) -#define IFXMIPS_RCU_RST_CPU1 (1 << 3) -#define IFXMIPS_RCU_RST_ALL 0x40000000 - -#define IFXMIPS_RCU_RST_REQ_DFE (1 << 7) -#define IFXMIPS_RCU_RST_REQ_AFE (1 << 11) -#define IFXMIPS_RCU_RST_REQ_ARC_JTAG (1 << 20) - - -/*------------ GPTU */ - -#define IFXMIPS_GPTU_BASE_ADDR 0xB8000300 - -/* clock control register */ -#define IFXMIPS_GPTU_GPT_CLC ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0000)) - -/* captur reload register */ -#define IFXMIPS_GPTU_GPT_CAPREL ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0030)) - -/* timer 6 control register */ -#define IFXMIPS_GPTU_GPT_T6CON ((u32 *)(IFXMIPS_GPTU_BASE_ADDR + 0x0020)) - - -/*------------ EBU */ - -#define IFXMIPS_EBU_BASE_ADDR 0xBE105300 - -/* bus configuration register */ -#define IFXMIPS_EBU_BUSCON0 ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0060)) -#define IFXMIPS_EBU_PCC_CON ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0090)) -#define IFXMIPS_EBU_PCC_IEN ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A4)) -#define IFXMIPS_EBU_PCC_ISTAT ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x00A0)) -#define IFXMIPS_EBU_BUSCON1 ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0064)) -#define IFXMIPS_EBU_ADDRSEL1 ((u32 *)(IFXMIPS_EBU_BASE_ADDR + 0x0024)) - -/*------------ CGU */ -#define IFXMIPS_CGU_BASE_ADDR (KSEG1 + 0x1F103000) -#define IFXMIPS_CGU_PLL0_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0004)) -#define IFXMIPS_CGU_PLL1_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0008)) -#define IFXMIPS_CGU_PLL2_CFG ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x000C)) -#define IFXMIPS_CGU_SYS ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) -#define IFXMIPS_CGU_UPDATE ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0014)) -#define IFXMIPS_CGU_IF_CLK ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) -#define IFXMIPS_CGU_OSC_CON ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x001C)) -#define IFXMIPS_CGU_SMD ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0020)) -#define IFXMIPS_CGU_CT1SR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0028)) -#define IFXMIPS_CGU_CT2SR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x002C)) -#define IFXMIPS_CGU_PCMCR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0030)) -#define IFXMIPS_CGU_PCI_CR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) -#define IFXMIPS_CGU_PD_PC ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0038)) -#define IFXMIPS_CGU_FMR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x003C)) - -/* clock mux */ -#define IFXMIPS_CGU_SYS ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0010)) -#define IFXMIPS_CGU_IFCCR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0018)) -#define IFXMIPS_CGU_PCICR ((u32 *)(IFXMIPS_CGU_BASE_ADDR + 0x0034)) - -#define CLOCK_60M 60000000 -#define CLOCK_83M 83333333 -#define CLOCK_111M 111111111 -#define CLOCK_133M 133333333 -#define CLOCK_167M 166666667 -#define CLOCK_333M 333333333 - - -/*------------ CGU */ - -#define IFXMIPS_PMU_BASE_ADDR (KSEG1 + 0x1F102000) - -#define IFXMIPS_PMU_PWDCR ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x001C)) -#define IFXMIPS_PMU_PWDSR ((u32 *)(IFXMIPS_PMU_BASE_ADDR + 0x0020)) - - -/*------------ ICU */ - -#define IFXMIPS_ICU_BASE_ADDR 0xBF880200 - - -#define IFXMIPS_ICU_IM0_ISR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0000)) -#define IFXMIPS_ICU_IM0_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0008)) -#define IFXMIPS_ICU_IM0_IOSR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0010)) -#define IFXMIPS_ICU_IM0_IRSR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0018)) -#define IFXMIPS_ICU_IM0_IMR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0020)) - -#define IFXMIPS_ICU_IM1_ISR ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0028)) -#define IFXMIPS_ICU_IM2_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0058)) -#define IFXMIPS_ICU_IM3_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x0080)) -#define IFXMIPS_ICU_IM4_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00A8)) -#define IFXMIPS_ICU_IM5_IER ((u32 *)(IFXMIPS_ICU_BASE_ADDR + 0x00D0)) - -#define IFXMIPS_ICU_OFFSET (IFXMIPS_ICU_IM1_ISR - IFXMIPS_ICU_IM0_ISR) - - -/*------------ ETOP */ - -#define IFXMIPS_PPE32_BASE_ADDR 0xBE180000 - -#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600 - -#define IFXMIPS_PPE32_MEM_MAP ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10000)) -#define IFXMIPS_PPE32_SRST ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x10080)) - -#define MII_MODE 1 -#define REV_MII_MODE 2 - -/* mdio access */ -#define IFXMIPS_PPE32_MDIO_CFG ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11800)) -#define IFXMIPS_PPE32_MDIO_ACC ((u32 *)(IFXMIPS_PPE32_BASE_ADDR + 0x11804)) - -#define MDIO_ACC_REQUEST 0x80000000 -#define MDIO_ACC_READ 0x40000000 -#define MDIO_ACC_ADDR_MASK 0x1f -#define MDIO_ACC_ADDR_OFFSET 0x15 -#define MDIO_ACC_REG_MASK 0x1f -#define MDIO_ACC_REG_OFFSET 0x10 -#define MDIO_ACC_VAL_MASK 0xffff - -/* configuration */ -#define IFXMIPS_PPE32_CFG ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1808)) - -#define PPE32_MII_MASK 0xfffffffc -#define PPE32_MII_NORMAL 0x8 -#define PPE32_MII_REVERSE 0xe - -/* packet length */ -#define IFXMIPS_PPE32_IG_PLEN_CTRL ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1820)) - -#define PPE32_PLEN_OVER 0x5ee -#define PPE32_PLEN_UNDER 0x400000 - -/* enet */ -#define IFXMIPS_PPE32_ENET_MAC_CFG ((u32 *)(IFXMIPS_PPE32_MEM_MAP + 0x1840)) - -#define PPE32_CGEN 0x800 - - -/*------------ DMA */ -#define IFXMIPS_DMA_BASE_ADDR 0xBE104100 - -#define IFXMIPS_DMA_CS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x18)) -#define IFXMIPS_DMA_CIE ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x2C)) -#define IFXMIPS_DMA_IRNEN ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0xf4)) -#define IFXMIPS_DMA_CCTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x1C)) -#define IFXMIPS_DMA_CIS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x28)) -#define IFXMIPS_DMA_CDLEN ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x24)) -#define IFXMIPS_DMA_PS ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x40)) -#define IFXMIPS_DMA_PCTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x44)) -#define IFXMIPS_DMA_CTRL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x10)) -#define IFXMIPS_DMA_CPOLL ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x14)) -#define IFXMIPS_DMA_CDBA ((u32 *)(IFXMIPS_DMA_BASE_ADDR + 0x20)) - - -/*------------ PCI */ -#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400) - -#define PCI_CR_FCI_ADDR_MAP0 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C0)) -#define PCI_CR_FCI_ADDR_MAP1 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C4)) -#define PCI_CR_FCI_ADDR_MAP2 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00C8)) -#define PCI_CR_FCI_ADDR_MAP3 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00CC)) -#define PCI_CR_FCI_ADDR_MAP4 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D0)) -#define PCI_CR_FCI_ADDR_MAP5 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D4)) -#define PCI_CR_FCI_ADDR_MAP6 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00D8)) -#define PCI_CR_FCI_ADDR_MAP7 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00DC)) -#define PCI_CR_CLK_CTRL ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0000)) -#define PCI_CR_PCI_MOD ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0030)) -#define PCI_CR_PC_ARB ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0080)) -#define PCI_CR_FCI_ADDR_MAP11hg ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E4)) -#define PCI_CR_BAR11MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0044)) -#define PCI_CR_BAR12MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0048)) -#define PCI_CR_BAR13MASK ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x004C)) -#define PCI_CS_BASE_ADDR1 ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0010)) -#define PCI_CR_PCI_ADDR_MAP11 ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x0064)) -#define PCI_CR_FCI_BURST_LENGTH ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x00E8)) -#define PCI_CR_PCI_EOI ((u32 *)(PCI_CR_PR_BASE_ADDR + 0x002C)) - -#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000) - -#define PCI_CS_STS_CMD ((u32 *)(PCI_CS_PR_BASE_ADDR + 0x0004)) - -#define PCI_MASTER0_REQ_MASK_2BITS 8 -#define PCI_MASTER1_REQ_MASK_2BITS 10 -#define PCI_MASTER2_REQ_MASK_2BITS 12 -#define INTERNAL_ARB_ENABLE_BIT 0 - - -/*------------ WDT */ - -#define IFXMIPS_WDT_BASE_ADDR (KSEG1 + 0x1F880000) - -#define IFXMIPS_BIU_WDT_CR ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F0)) -#define IFXMIPS_BIU_WDT_SR ((u32 *)(IFXMIPS_WDT_BASE_ADDR + 0x03F8)) - - -/*------------ LED */ - -#define IFXMIPS_LED_BASE_ADDR (KSEG1 + 0x1E100BB0) -#define IFXMIPS_LED_CON0 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0000)) -#define IFXMIPS_LED_CON1 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0004)) -#define IFXMIPS_LED_CPU0 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0008)) -#define IFXMIPS_LED_CPU1 ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x000C)) -#define IFXMIPS_LED_AR ((u32 *)(IFXMIPS_LED_BASE_ADDR + 0x0010)) - -#define LED_CON0_SWU (1 << 31) -#define LED_CON0_AD1 (1 << 25) -#define LED_CON0_AD0 (1 << 24) - -#define IFXMIPS_LED_2HZ (0) -#define IFXMIPS_LED_4HZ (1 << 23) -#define IFXMIPS_LED_8HZ (2 << 23) -#define IFXMIPS_LED_10HZ (3 << 23) -#define IFXMIPS_LED_MASK (0xf << 23) - -#define IFXMIPS_LED_UPD_SRC_FPI (1 << 31) -#define IFXMIPS_LED_UPD_MASK (3 << 30) -#define IFXMIPS_LED_ADSL_SRC (3 << 24) - -#define IFXMIPS_LED_GROUP0 (1 << 0) -#define IFXMIPS_LED_GROUP1 (1 << 1) -#define IFXMIPS_LED_GROUP2 (1 << 2) - -#define IFXMIPS_LED_RISING 0 -#define IFXMIPS_LED_FALLING (1 << 26) -#define IFXMIPS_LED_EDGE_MASK (1 << 26) - - -/*------------ GPIO */ - -#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00) - -#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010)) -#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040)) -#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014)) -#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044)) -#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018)) -#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048)) -#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C)) -#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C)) -#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020)) -#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050)) -#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024)) -#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054)) -#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028)) -#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058)) -#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C)) -#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C)) -#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030)) -#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060)) - - -/*------------ SSC */ - -#define IFXMIPS_SSC_BASE_ADDR (KSEG1 + 0x1e100800) - - -#define IFXMIPS_SSC_CLC ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0000)) -#define IFXMIPS_SSC_IRN ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x00F4)) -#define IFXMIPS_SSC_SFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0060)) -#define IFXMIPS_SSC_WHBGPOSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0078)) -#define IFXMIPS_SSC_STATE ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0014)) -#define IFXMIPS_SSC_WHBSTATE ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0018)) -#define IFXMIPS_SSC_FSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0038)) -#define IFXMIPS_SSC_ID ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0008)) -#define IFXMIPS_SSC_TB ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0020)) -#define IFXMIPS_SSC_RXFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0030)) -#define IFXMIPS_SSC_TXFCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0034)) -#define IFXMIPS_SSC_CON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0010)) -#define IFXMIPS_SSC_GPOSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0074)) -#define IFXMIPS_SSC_RB ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0024)) -#define IFXMIPS_SSC_RXCNT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084)) -#define IFXMIPS_SSC_GPOCON ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0070)) -#define IFXMIPS_SSC_BR ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0040)) -#define IFXMIPS_SSC_RXREQ ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0080)) -#define IFXMIPS_SSC_SFSTAT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0064)) -#define IFXMIPS_SSC_RXCNT ((u32 *)(IFXMIPS_SSC_BASE_ADDR + 0x0084)) - - -/*------------ MEI */ - -#define IFXMIPS_MEI_BASE_ADDR (KSEG1 + 0x1E116000) - -#define MEI_DATA_XFR ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0000)) -#define MEI_VERSION ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0004)) -#define MEI_ARC_GP_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0008)) -#define MEI_DATA_XFR_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x000C)) -#define MEI_XFR_ADDR ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0010)) -#define MEI_MAX_WAIT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0014)) -#define MEI_TO_ARC_INT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0018)) -#define ARC_TO_MEI_INT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x001C)) -#define ARC_TO_MEI_INT_MASK ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0020)) -#define MEI_DEBUG_WAD ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0024)) -#define MEI_DEBUG_RAD ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0028)) -#define MEI_DEBUG_DATA ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x002C)) -#define MEI_DEBUG_DEC ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0030)) -#define MEI_CONFIG ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0034)) -#define MEI_RST_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0038)) -#define MEI_DBG_MASTER ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x003C)) -#define MEI_CLK_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0040)) -#define MEI_BIST_CONTROL ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0044)) -#define MEI_BIST_STAT ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0048)) -#define MEI_XDATA_BASE_SH ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x004c)) -#define MEI_XDATA_BASE ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0050)) -#define MEI_XMEM_BAR_BASE ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054)) -#define MEI_XMEM_BAR0 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0054)) -#define MEI_XMEM_BAR1 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0058)) -#define MEI_XMEM_BAR2 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x005C)) -#define MEI_XMEM_BAR3 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0060)) -#define MEI_XMEM_BAR4 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0064)) -#define MEI_XMEM_BAR5 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0068)) -#define MEI_XMEM_BAR6 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x006C)) -#define MEI_XMEM_BAR7 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0070)) -#define MEI_XMEM_BAR8 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0074)) -#define MEI_XMEM_BAR9 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0078)) -#define MEI_XMEM_BAR10 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x007C)) -#define MEI_XMEM_BAR11 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0080)) -#define MEI_XMEM_BAR12 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0084)) -#define MEI_XMEM_BAR13 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0088)) -#define MEI_XMEM_BAR14 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x008C)) -#define MEI_XMEM_BAR15 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0090)) -#define MEI_XMEM_BAR16 ((u32 *)(IFXMIPS_MEI_BASE_ADDR + 0x0094)) - - -/*------------ DEU */ - -#define IFXMIPS_DEU_BASE (KSEG1 + 0x1E103100) -#define IFXMIPS_DEU_CLK ((u32 *)(IFXMIPS_DEU_BASE + 0x0000)) -#define IFXMIPS_DEU_ID ((u32 *)(IFXMIPS_DEU_BASE + 0x0008)) - -#define IFXMIPS_DES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0010)) -#define IFXMIPS_DES_IHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0014)) -#define IFXMIPS_DES_ILR ((u32 *)(IFXMIPS_DEU_BASE + 0x0018)) -#define IFXMIPS_DES_K1HR ((u32 *)(IFXMIPS_DEU_BASE + 0x001C)) -#define IFXMIPS_DES_K1LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0020)) -#define IFXMIPS_DES_K3HR ((u32 *)(IFXMIPS_DEU_BASE + 0x0024)) -#define IFXMIPS_DES_K3LR ((u32 *)(IFXMIPS_DEU_BASE + 0x0028)) -#define IFXMIPS_DES_IVHR ((u32 *)(IFXMIPS_DEU_BASE + 0x002C)) -#define IFXMIPS_DES_IVLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0030)) -#define IFXMIPS_DES_OHR ((u32 *)(IFXMIPS_DEU_BASE + 0x0040)) -#define IFXMIPS_DES_OLR ((u32 *)(IFXMIPS_DEU_BASE + 0x0050)) -#define IFXMIPS_AES_CON ((u32 *)(IFXMIPS_DEU_BASE + 0x0050)) -#define IFXMIPS_AES_ID3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0054)) -#define IFXMIPS_AES_ID2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0058)) -#define IFXMIPS_AES_ID1R ((u32 *)(IFXMIPS_DEU_BASE + 0x005C)) -#define IFXMIPS_AES_ID0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0060)) -#define IFXMIPS_AES_K7R ((u32 *)(IFXMIPS_DEU_BASE + 0x0064)) -#define IFXMIPS_AES_K6R ((u32 *)(IFXMIPS_DEU_BASE + 0x0068)) -#define IFXMIPS_AES_K5R ((u32 *)(IFXMIPS_DEU_BASE + 0x006C)) -#define IFXMIPS_AES_K4R ((u32 *)(IFXMIPS_DEU_BASE + 0x0070)) -#define IFXMIPS_AES_K3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0074)) -#define IFXMIPS_AES_K2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0078)) -#define IFXMIPS_AES_K1R ((u32 *)(IFXMIPS_DEU_BASE + 0x007C)) -#define IFXMIPS_AES_K0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0080)) -#define IFXMIPS_AES_IV3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0084)) -#define IFXMIPS_AES_IV2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0088)) -#define IFXMIPS_AES_IV1R ((u32 *)(IFXMIPS_DEU_BASE + 0x008C)) -#define IFXMIPS_AES_IV0R ((u32 *)(IFXMIPS_DEU_BASE + 0x0090)) -#define IFXMIPS_AES_0D3R ((u32 *)(IFXMIPS_DEU_BASE + 0x0094)) -#define IFXMIPS_AES_0D2R ((u32 *)(IFXMIPS_DEU_BASE + 0x0098)) -#define IFXMIPS_AES_OD1R ((u32 *)(IFXMIPS_DEU_BASE + 0x009C)) -#define IFXMIPS_AES_OD0R ((u32 *)(IFXMIPS_DEU_BASE + 0x00A0)) - -/*------------ FUSE */ - -#define IFXMIPS_FUSE_BASE_ADDR (KSEG1 + 0x1F107354) - - -/*------------ MPS */ - -#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000) -#define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000)) - -#define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344)) -#define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000)) -#define IFXMIPS_MPS_VC1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004)) -#define IFXMIPS_MPS_VC2ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008)) -#define IFXMIPS_MPS_VC3ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C)) -#define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010)) -#define IFXMIPS_MPS_RVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014)) -#define IFXMIPS_MPS_RVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018)) -#define IFXMIPS_MPS_RVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C)) -#define IFXMIPS_MPS_SVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020)) -#define IFXMIPS_MPS_SVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024)) -#define IFXMIPS_MPS_SVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028)) -#define IFXMIPS_MPS_SVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C)) -#define IFXMIPS_MPS_CVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030)) -#define IFXMIPS_MPS_CVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034)) -#define IFXMIPS_MPS_CVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038)) -#define IFXMIPS_MPS_CVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C)) -#define IFXMIPS_MPS_RAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040)) -#define IFXMIPS_MPS_RAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044)) -#define IFXMIPS_MPS_SAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048)) -#define IFXMIPS_MPS_SAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C)) -#define IFXMIPS_MPS_CAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050)) -#define IFXMIPS_MPS_CAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054)) -#define IFXMIPS_MPS_AD0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058)) -#define IFXMIPS_MPS_AD1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C)) - -#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) ((((1 << 4) - 1) & (value)) << 28) -#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) ((((1 << 16) - 1) & (value)) << 12) -#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -#define IFXMIPS_MPS_CHIPID_MANID_SET(value) ((((1 << 10) - 1) & (value)) << 1) - -#endif diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_cgu.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_cgu.h deleted file mode 100644 index 9ee287b421..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_cgu.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ - -#ifndef _IFXMIPS_CGU_H__ -#define _IFXMIPS_CGU_H__ - -#define BASIC_INPUT_CLOCK_FREQUENCY_1 35328000 -#define BASIC_INPUT_CLOCK_FREQUENCY_2 36000000 - -#define BASIS_INPUT_CRYSTAL_USB 12000000 - -#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) - -#define CGU_PLL0_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 31)) -#define CGU_PLL0_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 30)) -#define CGU_PLL0_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 28)) -#define CGU_PLL0_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & (1 << 27)) -#define CGU_PLL1_SRC (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 31)) -#define CGU_PLL1_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 30)) -#define CGU_PLL1_CFG_DSMSEL (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 28)) -#define CGU_PLL1_CFG_FRAC_EN (ifxmips_r32(IFXMIPS_CGU_PLL1_CFG) & (1 << 27)) -#define CGU_PLL2_PHASE_DIVIDER_ENABLE (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 20)) -#define CGU_PLL2_BYPASS (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & (1 << 19)) -#define CGU_SYS_FPI_SEL (1 << 6) -#define CGU_SYS_DDR_SEL 0x3 -#define CGU_PLL0_SRC (1 << 29) - -#define CGU_PLL0_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 26, 17) -#define CGU_PLL0_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 12, 6) -#define CGU_PLL0_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL0_CFG, 5, 2) -#define CGU_PLL1_CFG_PLLK GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 26, 17) -#define CGU_PLL1_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 12, 6) -#define CGU_PLL1_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL1_CFG, 5, 2) -#define CGU_PLL2_SRC GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 18, 17) -#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 16, 13) -#define CGU_PLL2_CFG_PLLN GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 12, 6) -#define CGU_PLL2_CFG_PLLM GET_BITS(*IFXMIPS_CGU_PLL2_CFG, 5, 2) -#define CGU_IF_CLK_PCI_CLK GET_BITS(*IFXMIPS_CGU_IF_CLK, 23, 20) - - -unsigned int cgu_get_mips_clock(int cpu); -unsigned int cgu_get_io_region_clock(void); -unsigned int cgu_get_fpi_bus_clock(int fpi); -void cgu_setup_pci_clk(int internal_clock); -unsigned int ifxmips_get_ddr_hz(void); -unsigned int ifxmips_get_fpi_hz(void); -unsigned int ifxmips_get_cpu_hz(void); - -#endif diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_dma.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_dma.h deleted file mode 100644 index 8ba852a1ec..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_dma.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2005 infineon - * Copyright (C) 2007 John Crispin - * - */ -#ifndef _IFXMIPS_DMA_H__ -#define _IFXMIPS_DMA_H__ - -#define RCV_INT 1 -#define TX_BUF_FULL_INT 2 -#define TRANSMIT_CPT_INT 4 -#define IFXMIPS_DMA_CH_ON 1 -#define IFXMIPS_DMA_CH_OFF 0 -#define IFXMIPS_DMA_CH_DEFAULT_WEIGHT 100 - -enum attr_t{ - TX = 0, - RX = 1, - RESERVED = 2, - DEFAULT = 3, -}; - -#define DMA_OWN 1 -#define CPU_OWN 0 -#define DMA_MAJOR 250 - -#define DMA_DESC_OWN_CPU 0x0 -#define DMA_DESC_OWN_DMA 0x80000000 -#define DMA_DESC_CPT_SET 0x40000000 -#define DMA_DESC_SOP_SET 0x20000000 -#define DMA_DESC_EOP_SET 0x10000000 - -#define MISCFG_MASK 0x40 -#define RDERR_MASK 0x20 -#define CHOFF_MASK 0x10 -#define DESCPT_MASK 0x8 -#define DUR_MASK 0x4 -#define EOP_MASK 0x2 - -#define DMA_DROP_MASK (1<<31) - -#define IFXMIPS_DMA_RX -1 -#define IFXMIPS_DMA_TX 1 - -struct dma_chan_map { - const char *dev_name; - enum attr_t dir; - int pri; - int irq; - int rel_chan_no; -}; - -#ifdef CONFIG_CPU_LITTLE_ENDIAN -struct rx_desc { - u32 data_length:16; - volatile u32 reserved:7; - volatile u32 byte_offset:2; - volatile u32 Burst_length_offset:3; - volatile u32 EoP:1; - volatile u32 Res:1; - volatile u32 C:1; - volatile u32 OWN:1; - volatile u32 Data_Pointer; /* fixme: should be 28 bits here */ -}; - -struct tx_desc { - volatile u32 data_length:16; - volatile u32 reserved1:7; - volatile u32 byte_offset:5; - volatile u32 EoP:1; - volatile u32 SoP:1; - volatile u32 C:1; - volatile u32 OWN:1; - volatile u32 Data_Pointer; /* fixme: should be 28 bits here */ -}; -#else /* BIG */ -struct rx_desc { - union { - struct { - volatile u32 OWN:1; - volatile u32 C:1; - volatile u32 SoP:1; - volatile u32 EoP:1; - volatile u32 Burst_length_offset:3; - volatile u32 byte_offset:2; - volatile u32 reserve:7; - volatile u32 data_length:16; - } field; - volatile u32 word; - } status; - volatile u32 Data_Pointer; -}; - -struct tx_desc { - union { - struct { - volatile u32 OWN:1; - volatile u32 C:1; - volatile u32 SoP:1; - volatile u32 EoP:1; - volatile u32 byte_offset:5; - volatile u32 reserved:7; - volatile u32 data_length:16; - } field; - volatile u32 word; - } status; - volatile u32 Data_Pointer; -}; -#endif /* ENDIAN */ - -struct dma_channel_info { - /* relative channel number */ - int rel_chan_no; - /* class for this channel for QoS */ - int pri; - /* specify byte_offset */ - int byte_offset; - /* direction */ - int dir; - /* irq number */ - int irq; - /* descriptor parameter */ - int desc_base; - int desc_len; - int curr_desc; - int prev_desc; /* only used if it is a tx channel*/ - /* weight setting for WFQ algorithm*/ - int weight; - int default_weight; - int packet_size; - int burst_len; - /* on or off of this channel */ - int control; - /* optional information for the upper layer devices */ -#if defined(CONFIG_IFXMIPS_ETHERNET_D2) || defined(CONFIG_IFXMIPS_PPA) - void *opt[64]; -#else - void *opt[25]; -#endif - /* Pointer to the peripheral device who is using this channel */ - void *dma_dev; - /* channel operations */ - void (*open)(struct dma_channel_info *pCh); - void (*close)(struct dma_channel_info *pCh); - void (*reset)(struct dma_channel_info *pCh); - void (*enable_irq)(struct dma_channel_info *pCh); - void (*disable_irq)(struct dma_channel_info *pCh); -}; - -struct dma_device_info { - /* device name of this peripheral */ - char device_name[15]; - int reserved; - int tx_burst_len; - int rx_burst_len; - int default_weight; - int current_tx_chan; - int current_rx_chan; - int num_tx_chan; - int num_rx_chan; - int max_rx_chan_num; - int max_tx_chan_num; - struct dma_channel_info *tx_chan[20]; - struct dma_channel_info *rx_chan[20]; - /*functions, optional*/ - u8 *(*buffer_alloc)(int len, int *offset, void **opt); - void (*buffer_free)(u8 *dataptr, void *opt); - int (*intr_handler)(struct dma_device_info *info, int status); - void *priv; /* used by peripheral driver only */ -}; - -struct dma_device_info *dma_device_reserve(char *dev_name); -void dma_device_release(struct dma_device_info *dev); -void dma_device_register(struct dma_device_info *info); -void dma_device_unregister(struct dma_device_info *info); -int dma_device_read(struct dma_device_info *info, u8 **dataptr, void **opt); -int dma_device_write(struct dma_device_info *info, u8 *dataptr, int len, - void *opt); - -#endif - diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_ebu.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_ebu.h deleted file mode 100644 index 4c9396ae88..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_ebu.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_EBU_H__ -#define _IFXMIPS_EBU_H__ - -extern spinlock_t ebu_lock; - -#endif diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gpio.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gpio.h deleted file mode 100644 index a4c8c3ffb1..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gpio.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_GPIO_H__ -#define _IFXMIPS_GPIO_H__ - -extern int ifxmips_port_reserve_pin(unsigned int port, unsigned int pin); -extern int ifxmips_port_free_pin(unsigned int port, unsigned int pin); -extern int ifxmips_port_set_open_drain(unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_open_drain(unsigned int port, unsigned int pin); -extern int ifxmips_port_set_pudsel(unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_pudsel(unsigned int port, unsigned int pin); -extern int ifxmips_port_set_puden(unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_puden(unsigned int port, unsigned int pin); -extern int ifxmips_port_set_stoff(unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_stoff(unsigned int port, unsigned int pin); -extern int ifxmips_port_set_dir_out(unsigned int port, unsigned int pin); -extern int ifxmips_port_set_dir_in(unsigned int port, unsigned int pin); -extern int ifxmips_port_set_output(unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_output(unsigned int port, unsigned int pin); -extern int ifxmips_port_get_input(unsigned int port, unsigned int pin); -extern int ifxmips_port_set_altsel0(unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_altsel0(unsigned int port, unsigned int pin); -extern int ifxmips_port_set_altsel1(unsigned int port, unsigned int pin); -extern int ifxmips_port_clear_altsel1(unsigned int port, unsigned int pin); - -#endif diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gptu.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gptu.h deleted file mode 100644 index 330c3cfd55..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_gptu.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ - - -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - - -/* - * #################################### - * Definition - * #################################### - */ - -/* - * Available Timer/Counter Index - */ -#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) -#define TIMER_ANY 0x00 -#define TIMER1A TIMER(1, 0) -#define TIMER1B TIMER(1, 1) -#define TIMER2A TIMER(2, 0) -#define TIMER2B TIMER(2, 1) -#define TIMER3A TIMER(3, 0) -#define TIMER3B TIMER(3, 1) - -/* - * Flag of Timer/Counter - * These flags specify the way in which timer is configured. - */ -/* Bit size of timer/counter. */ -#define TIMER_FLAG_16BIT 0x0000 -#define TIMER_FLAG_32BIT 0x0001 -/* Switch between timer and counter. */ -#define TIMER_FLAG_TIMER 0x0000 -#define TIMER_FLAG_COUNTER 0x0002 -/* Stop or continue when overflowing/underflowing. */ -#define TIMER_FLAG_ONCE 0x0000 -#define TIMER_FLAG_CYCLIC 0x0004 -/* Count up or counter down. */ -#define TIMER_FLAG_UP 0x0000 -#define TIMER_FLAG_DOWN 0x0008 -/* Count on specific level or edge. */ -#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 -#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 -#define TIMER_FLAG_RISE_EDGE 0x0010 -#define TIMER_FLAG_FALL_EDGE 0x0020 -#define TIMER_FLAG_ANY_EDGE 0x0030 -/* Signal is syncronous to module clock or not. */ -#define TIMER_FLAG_UNSYNC 0x0000 -#define TIMER_FLAG_SYNC 0x0080 -/* Different interrupt handle type. */ -#define TIMER_FLAG_NO_HANDLE 0x0000 -#if defined(__KERNEL__) - #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 -#endif // defined(__KERNEL__) -#define TIMER_FLAG_SIGNAL 0x0300 -/* Internal clock source or external clock source */ -#define TIMER_FLAG_INT_SRC 0x0000 -#define TIMER_FLAG_EXT_SRC 0x1000 - - -/* - * ioctl Command - */ -#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ -#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ -#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ -#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ -#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ -#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ -#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ -#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ - -/* - * Data Type Used to Call ioctl - */ -struct gptu_ioctl_param { - unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * - * GPTU_SET_COUNTER, this field is ID of expected * - * timer/counter. If it's zero, a timer/counter would * - * be dynamically allocated and ID would be stored in * - * this field. * - * In command GPTU_GET_COUNT_VALUE, this field is * - * ignored. * - * In other command, this field is ID of timer/counter * - * allocated. */ - unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * - * GPTU_SET_COUNTER, this field contains flags to * - * specify how to configure timer/counter. * - * In command GPTU_START_TIMER, zero indicate start * - * and non-zero indicate resume timer/counter. * - * In other command, this field is ignored. */ - unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * - * init/reload value. * - * In command GPTU_SET_TIMER, this field contains * - * frequency (0.001Hz) of timer. * - * In command GPTU_GET_COUNT_VALUE, current count * - * value would be stored in this field. * - * In command GPTU_CALCULATE_DIVIDER, this field * - * contains frequency wanted, and after calculation, * - * divider would be stored in this field to overwrite * - * the frequency. * - * In other command, this field is ignored. */ - int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * - * if signal is required, this field contains process * - * ID to which signal would be sent. * - * In other command, this field is ignored. */ - int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * - * if signal is required, this field contains signal * - * number which would be sent. * - * In other command, this field is ignored. */ -}; - -/* - * #################################### - * Data Type - * #################################### - */ -typedef void (*timer_callback)(unsigned long arg); - -extern int ifxmips_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); -extern int ifxmips_free_timer(unsigned int); -extern int ifxmips_start_timer(unsigned int, int); -extern int ifxmips_stop_timer(unsigned int); -extern int ifxmips_reset_counter_flags(u32 timer, u32 flags); -extern int ifxmips_get_count_value(unsigned int, unsigned long *); -extern u32 ifxmips_cal_divider(unsigned long); -extern int ifxmips_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); -extern int ifxmips_set_counter(unsigned int timer, unsigned int flag, - u32 reload, unsigned long arg1, unsigned long arg2); - -#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h deleted file mode 100644 index e6ca59baf9..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_irq.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2005 infineon - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_IRQ__ -#define _IFXMIPS_IRQ__ - -#define INT_NUM_IRQ0 8 -#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) -#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) -#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64) -#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96) -#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) -#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) - -#define IFXMIPSASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 7)) -#define IFXMIPSASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 2) -#define IFXMIPSASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 7) + 3) - -#define IFXMIPS_SSC_TIR (INT_NUM_IM0_IRL0 + 15) -#define IFXMIPS_SSC_RIR (INT_NUM_IM0_IRL0 + 14) -#define IFXMIPS_SSC_EIR (INT_NUM_IM0_IRL0 + 16) - -#define IFXMIPS_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21) -#define IFXMIPS_MEI_INT (INT_NUM_IM1_IRL0 + 23) - -#define IFXMIPS_TIMER6_INT (INT_NUM_IM1_IRL0 + 23) -#define IFXMIPS_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) - -#define MIPS_CPU_TIMER_IRQ 7 - -#define IFXMIPS_DMA_CH0_INT (INT_NUM_IM2_IRL0) -#define IFXMIPS_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1) -#define IFXMIPS_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2) -#define IFXMIPS_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3) -#define IFXMIPS_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4) -#define IFXMIPS_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5) -#define IFXMIPS_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6) -#define IFXMIPS_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7) -#define IFXMIPS_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8) -#define IFXMIPS_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9) -#define IFXMIPS_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10) -#define IFXMIPS_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11) -#define IFXMIPS_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25) -#define IFXMIPS_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26) -#define IFXMIPS_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27) -#define IFXMIPS_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28) -#define IFXMIPS_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29) -#define IFXMIPS_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30) -#define IFXMIPS_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16) -#define IFXMIPS_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21) - -#define IFXMIPS_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24) - -#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) -#define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18) -#define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19) -#define IFXMIPS_USB_INT (INT_NUM_IM4_IRL0 + 22) -#define IFXMIPS_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) - - -extern void ifxmips_mask_and_ack_irq(unsigned int irq_nr); - -#endif diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_led.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_led.h deleted file mode 100644 index c97657a89f..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_led.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_LED_H__ -#define _IFXMIPS_LED_H__ - -extern void ifxmips_led_set(unsigned int led); -extern void ifxmips_led_clear(unsigned int led); -extern void ifxmips_led_blink_set(unsigned int led); -extern void ifxmips_led_blink_clear(unsigned int led); - -#endif diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_pmu.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_pmu.h deleted file mode 100644 index dd1f0d6f12..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_pmu.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - */ -#ifndef _IFXMIPS_PMU_H__ -#define _IFXMIPS_PMU_H__ - - -#define IFXMIPS_PMU_PWDCR_DMA 0x0020 -#define IFXMIPS_PMU_PWDCR_USB 0x8041 -#define IFXMIPS_PMU_PWDCR_LED 0x0800 -#define IFXMIPS_PMU_PWDCR_GPT 0x1000 -#define IFXMIPS_PMU_PWDCR_PPE 0x2000 -#define IFXMIPS_PMU_PWDCR_FPI 0x4000 - -void ifxmips_pmu_enable(unsigned int module); -void ifxmips_pmu_disable(unsigned int module); - -#endif diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_prom.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_prom.h deleted file mode 100644 index e640ad7acc..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/ifxmips_prom.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2008 John Crispin - */ -#ifndef _IFXPROM_H__ -#define _IFXPROM_H__ - -extern void prom_printf(const char *fmt, ...); -extern u32 *prom_get_cp1_base(void); -extern u32 prom_get_cp1_size(void); -extern int ifxmips_has_brn_block(void); - -#endif diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/irq.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/irq.h deleted file mode 100644 index 80342ae3a9..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/irq.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * include/asm-mips/mach-ifxmips/irq.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. - * - * Copyright (C) 2007 John Crispin - * - */ - -#ifndef __IFXMIPS_IRQ_H -#define __IFXMIPS_IRQ_H - -#define NR_IRQS 256 -#include_next - -#endif diff --git a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/war.h b/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/war.h deleted file mode 100644 index de3584ecf6..0000000000 --- a/target/linux/ifxmips/files/arch/mips/include/asm/mach-ifxmips/war.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - */ -#ifndef __ASM_MIPS_MACH_IFXMIPS_WAR_H -#define __ASM_MIPS_MACH_IFXMIPS_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif diff --git a/target/linux/ifxmips/files/arch/mips/pci/ops-ifxmips.c b/target/linux/ifxmips/files/arch/mips/pci/ops-ifxmips.c deleted file mode 100644 index fde6357e41..0000000000 --- a/target/linux/ifxmips/files/arch/mips/pci/ops-ifxmips.c +++ /dev/null @@ -1,120 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IFXMIPS_PCI_CFG_BUSNUM_SHF 16 -#define IFXMIPS_PCI_CFG_DEVNUM_SHF 11 -#define IFXMIPS_PCI_CFG_FUNNUM_SHF 8 - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -extern u32 ifxmips_pci_mapped_cfg; - -static int -ifxmips_pci_config_access(unsigned char access_type, - struct pci_bus *bus, unsigned int devfn, unsigned int where, u32 *data) -{ - unsigned long cfg_base; - unsigned long flags; - - u32 temp; - - /* IFXMips support slot from 0 to 15 */ - /* dev_fn 0&0x68 (AD29) is ifxmips itself */ - if ((bus->number != 0) || ((devfn & 0xf8) > 0x78) - || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68)) - return 1; - - spin_lock_irqsave(&ebu_lock, flags); - - cfg_base = ifxmips_pci_mapped_cfg; - cfg_base |= (bus->number << IFXMIPS_PCI_CFG_BUSNUM_SHF) | (devfn << - IFXMIPS_PCI_CFG_FUNNUM_SHF) | (where & ~0x3); - - /* Perform access */ - if (access_type == PCI_ACCESS_WRITE) - { -#ifdef CONFIG_SWAP_IO_SPACE - ifxmips_w32(swab32(*data), ((u32*)cfg_base)); -#else - ifxmips_w32(*data, ((u32*)cfg_base)); -#endif - } else { - *data = ifxmips_r32(((u32*)(cfg_base))); -#ifdef CONFIG_SWAP_IO_SPACE - *data = swab32(*data); -#endif - } - wmb(); - - /* clean possible Master abort */ - cfg_base = (ifxmips_pci_mapped_cfg | (0x0 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4; - temp = ifxmips_r32(((u32*)(cfg_base))); -#ifdef CONFIG_SWAP_IO_SPACE - temp = swab32 (temp); -#endif - cfg_base = (ifxmips_pci_mapped_cfg | (0x68 << IFXMIPS_PCI_CFG_FUNNUM_SHF)) + 4; - ifxmips_w32(temp, ((u32*)cfg_base)); - - spin_unlock_irqrestore(&ebu_lock, flags); - - if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ)) - return 1; - - return 0; -} - -int -ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * val) -{ - u32 data = 0; - - if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - -int -ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 data = 0; - - if (size == 4) - { - data = val; - } else { - if (ifxmips_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - } - - if (ifxmips_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return PCIBIOS_DEVICE_NOT_FOUND; - - return PCIBIOS_SUCCESSFUL; -} diff --git a/target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c b/target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c deleted file mode 100644 index 6ff765e85f..0000000000 --- a/target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c +++ /dev/null @@ -1,209 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define IFXMIPS_PCI_MEM_BASE 0x18000000 -#define IFXMIPS_PCI_MEM_SIZE 0x02000000 -#define IFXMIPS_PCI_IO_BASE 0x1AE00000 -#define IFXMIPS_PCI_IO_SIZE 0x00200000 - -extern int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val); -extern int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val); - -struct pci_ops ifxmips_pci_ops = -{ - .read = ifxmips_pci_read_config_dword, - .write = ifxmips_pci_write_config_dword -}; - -static struct resource pci_io_resource = -{ - .name = "io pci IO space", - .start = IFXMIPS_PCI_IO_BASE, - .end = IFXMIPS_PCI_IO_BASE + IFXMIPS_PCI_IO_SIZE - 1, - .flags = IORESOURCE_IO -}; - -static struct resource pci_mem_resource = -{ - .name = "ext pci memory space", - .start = IFXMIPS_PCI_MEM_BASE, - .end = IFXMIPS_PCI_MEM_BASE + IFXMIPS_PCI_MEM_SIZE - 1, - .flags = IORESOURCE_MEM -}; - -static struct pci_controller ifxmips_pci_controller = -{ - .pci_ops = &ifxmips_pci_ops, - .mem_resource = &pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_resource = &pci_io_resource, - .io_offset = 0x00000000UL, -}; - -/* the cpu can can generate the 33Mhz or rely on an external clock the cgu needs the - proper setting, otherwise the cpu hangs. we have no way of runtime detecting this */ -u32 ifxmips_pci_mapped_cfg; -int ifxmips_pci_external_clock = 0; - -/* Since the PCI REQ pins can be reused for other functionality, make it possible - to exclude those from interpretation by the PCI controller */ -int ifxmips_pci_req_mask = 0xf; - -static int __init -ifxmips_pci_set_external_clk(char *str) -{ - printk("cgu: setting up external pci clock\n"); - ifxmips_pci_external_clock = 1; - return 1; -} -__setup("pci_external_clk", ifxmips_pci_set_external_clk); - -int -pcibios_plat_dev_init(struct pci_dev *dev) -{ - u8 pin; - - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); - switch(pin) - { - case 0: - break; - case 1: - //falling edge level triggered:0x4, low level:0xc, rising edge:0x2 - ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON); - ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN); - break; - case 2: - case 3: - case 4: - printk ("WARNING: interrupt pin %d not supported yet!\n", pin); - default: - printk ("WARNING: invalid interrupt pin %d\n", pin); - return 1; - } - return 0; -} - -static u32 calc_bar11mask(void) -{ - u32 mem, bar11mask; - - /* BAR11MASK value depends on available memory on system. */ - mem = num_physpages * PAGE_SIZE; - bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) -1)) -1)) | 8; - - return bar11mask; -} - -static void __init -ifxmips_pci_startup(void) -{ - u32 temp_buffer; - - cgu_setup_pci_clk(ifxmips_pci_external_clock); - - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0); - /* enable auto-switching between PCI and EBU */ - ifxmips_w32(0xa, PCI_CR_CLK_CTRL); - /* busy, i.e. configuration is not done, PCI access has to be retried */ - ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD); - wmb (); - /* BUS Master/IO/MEM access */ - ifxmips_w32(ifxmips_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD); - - /* enable external 2 PCI masters */ - temp_buffer = ifxmips_r32(PCI_CR_PC_ARB); - temp_buffer &= (~(ifxmips_pci_req_mask << 16)); - /* enable internal arbiter */ - temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT); - /* enable internal PCI master reqest */ - temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS)); - - /* enable EBU reqest */ - temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS)); - - /* enable all external masters request */ - temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS)); - ifxmips_w32(temp_buffer, PCI_CR_PC_ARB); - wmb (); - - ifxmips_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0); - ifxmips_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1); - ifxmips_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2); - ifxmips_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3); - ifxmips_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4); - ifxmips_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5); - ifxmips_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6); - ifxmips_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7); - ifxmips_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg); - ifxmips_w32(calc_bar11mask(), PCI_CR_BAR11MASK); - ifxmips_w32(0, PCI_CR_PCI_ADDR_MAP11); - ifxmips_w32(0, PCI_CS_BASE_ADDR1); -#ifdef CONFIG_SWAP_IO_SPACE - /* both TX and RX endian swap are enabled */ - ifxmips_w32(ifxmips_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI); - wmb (); -#endif - /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */ - ifxmips_w32(ifxmips_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK); - ifxmips_w32(ifxmips_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK); - /*use 8 dw burst length */ - ifxmips_w32(0x303, PCI_CR_FCI_BURST_LENGTH); - ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD); - wmb(); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT); - wmb(); - mdelay(1); - ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT); -} - -int __init -pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){ - switch(slot) - { - case 13: - /* IDSEL = AD29 --> USB Host Controller */ - return (INT_NUM_IM1_IRL0 + 17); - case 14: - /* IDSEL = AD30 --> mini PCI connector */ - return (INT_NUM_IM0_IRL0 + 22); - default: - printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin); - return 0; - } -} - -int __init -pcibios_init(void) -{ - extern int pci_probe_only; - - pci_probe_only = 0; - printk("PCI: Probing PCI hardware on host bus 0.\n"); - ifxmips_pci_startup (); - ifxmips_pci_mapped_cfg = (u32)ioremap_nocache(0x17000000, 0x800 * 16); - printk("IFXMips PCI mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_mapped_cfg); - ifxmips_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1); - printk("IFXMips PCI I/O mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_controller.io_map_base); - register_pci_controller(&ifxmips_pci_controller); - return 0; -} - -arch_initcall(pcibios_init); diff --git a/target/linux/ifxmips/generic/target.mk b/target/linux/ifxmips/generic/target.mk deleted file mode 100644 index dc7655093d..0000000000 --- a/target/linux/ifxmips/generic/target.mk +++ /dev/null @@ -1,5 +0,0 @@ -BOARDNAME:=Generic - -define Target/Description - Build standard images for Infineon CPE devices -endef diff --git a/target/linux/ifxmips/image/Makefile b/target/linux/ifxmips/image/Makefile deleted file mode 100644 index 52dfcd7570..0000000000 --- a/target/linux/ifxmips/image/Makefile +++ /dev/null @@ -1,39 +0,0 @@ -# -# Copyright (C) 2006-2010 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# -include $(TOPDIR)/rules.mk -include $(INCLUDE_DIR)/image.mk - -define Image/BuildKernel - $(STAGING_DIR_HOST)/bin/lzma e $(KDIR)/vmlinux $(KDIR)/vmlinux.lzma - mkimage -A mips -O linux -T kernel -a 0x80002000 -C lzma -e \ - 0x80002000 \ - -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ - -d $(KDIR)/vmlinux.lzma $(KDIR)/uImage - - cp $(KDIR)/uImage $(BIN_DIR)/$(IMG_PREFIX)-uImage -endef - -define Image/Build/squashfs - cat $(KDIR)/uImage $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(1).image - $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(1).image) -endef - -define Image/Build/jffs2-64k - dd if=$(KDIR)/uImage of=$(KDIR)/uImage.$(1) bs=64k conv=sync - cat $(KDIR)/uImage.$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(1).image -endef - -define Image/Build/jffs2-128k - dd if=$(KDIR)/uImage of=$(KDIR)/uImage.$(1) bs=128k conv=sync - cat $(KDIR)/uImage.$(1) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(1).image -endef - -define Image/Build - $(call Image/Build/$(1),$(1)) -endef - -$(eval $(call BuildImage)) diff --git a/target/linux/ifxmips/nfs/base-files/etc/config/network b/target/linux/ifxmips/nfs/base-files/etc/config/network deleted file mode 100644 index f2e8a5ecd5..0000000000 --- a/target/linux/ifxmips/nfs/base-files/etc/config/network +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (C) 2006 OpenWrt.org - -config interface loopback - option ifname lo - option proto static - option ipaddr 127.0.0.1 - option netmask 255.0.0.0 diff --git a/target/linux/ifxmips/nfs/base-files/lib/preinit/01_init_nfs_ifxmips b/target/linux/ifxmips/nfs/base-files/lib/preinit/01_init_nfs_ifxmips deleted file mode 100644 index 7008928204..0000000000 --- a/target/linux/ifxmips/nfs/base-files/lib/preinit/01_init_nfs_ifxmips +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/sh - - -init_nfs() { - grep "/dev/root" /proc/mounts | grep -q nfs && { - echo "- init nfs -" - exec /sbin/init - } -} - -boot_hook_add preinit_main init_nfs - diff --git a/target/linux/ifxmips/nfs/config-default b/target/linux/ifxmips/nfs/config-default deleted file mode 100644 index 8e1884211e..0000000000 --- a/target/linux/ifxmips/nfs/config-default +++ /dev/null @@ -1,23 +0,0 @@ -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_RNG2=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_DHCP is not set -# CONFIG_IP_PNP_RARP is not set -CONFIG_IP_PNP=y -CONFIG_LOCKD=y -# CONFIG_NETFILTER is not set -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -CONFIG_RPCSEC_GSS_KRB5=y -CONFIG_SUNRPC_GSS=y -CONFIG_SUNRPC=y diff --git a/target/linux/ifxmips/nfs/target.mk b/target/linux/ifxmips/nfs/target.mk deleted file mode 100644 index 8d454e2795..0000000000 --- a/target/linux/ifxmips/nfs/target.mk +++ /dev/null @@ -1,8 +0,0 @@ -BOARDNAME:=NFS Root -FEATURES:=tgz -DEVICE_TYPE:=modem - -define Target/Description - Build images for Infineon CPE devices for NFS boot -endef - diff --git a/target/linux/ifxmips/patches-2.6.30/000-mips-bad-intctl.patch b/target/linux/ifxmips/patches-2.6.30/000-mips-bad-intctl.patch deleted file mode 100644 index bd1b399c12..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/000-mips-bad-intctl.patch +++ /dev/null @@ -1,36 +0,0 @@ -Index: linux-2.6.30.5/arch/mips/kernel/traps.c -=================================================================== ---- linux-2.6.30.5.orig/arch/mips/kernel/traps.c 2009-08-16 23:19:38.000000000 +0200 -+++ linux-2.6.30.5/arch/mips/kernel/traps.c 2009-09-02 18:23:37.000000000 +0200 -@@ -1542,7 +1542,16 @@ - */ - if (cpu_has_mips_r2) { - cp0_compare_irq = (read_c0_intctl() >> 29) & 7; -+ if (!cp0_compare_irq) -+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; -+ - cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; -+ if (!cp0_perfcount_irq) -+ cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ; -+ -+ if (arch_fixup_c0_irqs) -+ arch_fixup_c0_irqs(); -+ - if (cp0_perfcount_irq == cp0_compare_irq) - cp0_perfcount_irq = -1; - } else { -Index: linux-2.6.30.5/arch/mips/include/asm/irq.h -=================================================================== ---- linux-2.6.30.5.orig/arch/mips/include/asm/irq.h 2009-09-02 18:24:49.000000000 +0200 -+++ linux-2.6.30.5/arch/mips/include/asm/irq.h 2009-09-02 18:26:05.000000000 +0200 -@@ -157,8 +157,10 @@ - * IE7. Since R2 their number has to be read from the c0_intctl register. - */ - #define CP0_LEGACY_COMPARE_IRQ 7 -+#define CP0_LEGACY_PERFCNT_IRQ 7 - - extern int cp0_compare_irq; - extern int cp0_perfcount_irq; -+extern void __weak arch_fixup_c0_irqs(void); - - #endif /* _ASM_IRQ_H */ diff --git a/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch deleted file mode 100644 index 49ff663105..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/010-mips_clocksource_init_war.patch +++ /dev/null @@ -1,35 +0,0 @@ -Index: linux-2.6.30.5/arch/mips/kernel/cevt-r4k.c -=================================================================== ---- linux-2.6.30.5.orig/arch/mips/kernel/cevt-r4k.c 2009-08-16 23:19:38.000000000 +0200 -+++ linux-2.6.30.5/arch/mips/kernel/cevt-r4k.c 2009-09-02 18:26:26.000000000 +0200 -@@ -21,6 +21,22 @@ - - #ifndef CONFIG_MIPS_MT_SMTC - -+/* -+ * Compare interrupt can be routed and latched outside the core, -+ * so a single execution hazard barrier may not be enough to give -+ * it time to clear as seen in the Cause register. 4 time the -+ * pipeline depth seems reasonably conservative, and empirically -+ * works better in configurations with high CPU/bus clock ratios. -+ */ -+ -+#define compare_change_hazard() \ -+ do { \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ } while (0) -+ - static int mips_next_event(unsigned long delta, - struct clock_event_device *evt) - { -@@ -30,6 +46,7 @@ - cnt = read_c0_count(); - cnt += delta; - write_c0_compare(cnt); -+ compare_change_hazard(); - res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; - return res; - } diff --git a/target/linux/ifxmips/patches-2.6.30/100-board.patch b/target/linux/ifxmips/patches-2.6.30/100-board.patch deleted file mode 100644 index 5e7530ecde..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/100-board.patch +++ /dev/null @@ -1,67 +0,0 @@ -Index: linux-2.6.30.10/arch/mips/Kconfig -=================================================================== ---- linux-2.6.30.10.orig/arch/mips/Kconfig 2010-03-24 15:32:02.000000000 +0100 -+++ linux-2.6.30.10/arch/mips/Kconfig 2010-03-24 21:56:29.000000000 +0100 -@@ -79,6 +79,23 @@ - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - -+config IFXMIPS -+ bool "Infineon Twinpass, Danube, Amazon-SE" -+ select DMA_NONCOHERENT -+ select IRQ_CPU -+ select CEVT_R4K -+ select CSRC_R4K -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_HAS_CPU_MIPS32_R2 -+ select HAVE_STD_PC_SERIAL_PORT -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_MULTITHREADING -+ select SYS_HAS_EARLY_PRINTK -+ select HW_HAS_PCI -+ select ARCH_REQUIRE_GPIOLIB -+ select SWAP_IO_SPACE -+ - config MACH_DECSTATION - bool "DECstations" - select BOOT_ELF32 -@@ -643,6 +660,7 @@ - source "arch/mips/txx9/Kconfig" - source "arch/mips/vr41xx/Kconfig" - source "arch/mips/cavium-octeon/Kconfig" -+source "arch/mips/ifxmips/Kconfig" - - endmenu - -Index: linux-2.6.30.10/arch/mips/Makefile -=================================================================== ---- linux-2.6.30.10.orig/arch/mips/Makefile 2010-03-24 15:32:02.000000000 +0100 -+++ linux-2.6.30.10/arch/mips/Makefile 2010-03-24 15:32:04.000000000 +0100 -@@ -290,6 +290,13 @@ - load-$(CONFIG_MIPS_COBALT) += 0xffffffff80080000 - - # -+# Infineon IFXMIPS -+# -+core-$(CONFIG_IFXMIPS) += arch/mips/ifxmips/ -+cflags-$(CONFIG_IFXMIPS) += -I$(srctree)/arch/mips/include/asm/mach-ifxmips -+load-$(CONFIG_IFXMIPS) += 0xffffffff80002000 -+ -+# - # DECstation family - # - core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/ -Index: linux-2.6.30.10/arch/mips/include/asm/bootinfo.h -=================================================================== ---- linux-2.6.30.10.orig/arch/mips/include/asm/bootinfo.h 2009-12-04 07:00:07.000000000 +0100 -+++ linux-2.6.30.10/arch/mips/include/asm/bootinfo.h 2010-03-24 15:32:04.000000000 +0100 -@@ -57,6 +57,8 @@ - #define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */ - #define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */ - -+#define MACH_INFINEON_IFXMIPS 0 -+ - #define CL_SIZE COMMAND_LINE_SIZE - - extern char *system_type; diff --git a/target/linux/ifxmips/patches-2.6.30/110-pci.patch b/target/linux/ifxmips/patches-2.6.30/110-pci.patch deleted file mode 100644 index fae887b4d9..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/110-pci.patch +++ /dev/null @@ -1,9 +0,0 @@ -Index: linux-2.6.30.5/arch/mips/pci/Makefile -=================================================================== ---- linux-2.6.30.5.orig/arch/mips/pci/Makefile 2009-09-02 22:12:48.000000000 +0200 -+++ linux-2.6.30.5/arch/mips/pci/Makefile 2009-09-02 22:12:53.000000000 +0200 -@@ -52,3 +52,4 @@ - obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o - obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o - obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o -+obj-$(CONFIG_IFXMIPS) += pci-ifxmips.o ops-ifxmips.o diff --git a/target/linux/ifxmips/patches-2.6.30/120-serial.patch b/target/linux/ifxmips/patches-2.6.30/120-serial.patch deleted file mode 100644 index 1169378e42..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/120-serial.patch +++ /dev/null @@ -1,588 +0,0 @@ -Index: linux-2.6.30.10/drivers/serial/Kconfig -=================================================================== ---- linux-2.6.30.10.orig/drivers/serial/Kconfig 2009-12-04 07:00:07.000000000 +0100 -+++ linux-2.6.30.10/drivers/serial/Kconfig 2010-03-18 12:24:20.000000000 +0100 -@@ -1365,6 +1365,14 @@ - help - Support for Console on the NWP serial ports. - -+config SERIAL_IFXMIPS -+ bool "IFXMips serial driver" -+ depends on IFXMIPS -+ select SERIAL_CORE -+ select SERIAL_CORE_CONSOLE -+ help -+ Driver for the ifxmipss built in ASC hardware -+ - config SERIAL_QE - tristate "Freescale QUICC Engine serial port support" - depends on QUICC_ENGINE -Index: linux-2.6.30.10/drivers/serial/Makefile -=================================================================== ---- linux-2.6.30.10.orig/drivers/serial/Makefile 2009-12-04 07:00:07.000000000 +0100 -+++ linux-2.6.30.10/drivers/serial/Makefile 2010-03-18 12:24:20.000000000 +0100 -@@ -77,3 +77,4 @@ - obj-$(CONFIG_SERIAL_KS8695) += serial_ks8695.o - obj-$(CONFIG_KGDB_SERIAL_CONSOLE) += kgdboc.o - obj-$(CONFIG_SERIAL_QE) += ucc_uart.o -+obj-$(CONFIG_SERIAL_IFXMIPS) += ifxmips_asc.o -Index: linux-2.6.30.10/drivers/serial/ifxmips_asc.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.30.10/drivers/serial/ifxmips_asc.c 2010-03-18 14:04:58.000000000 +0100 -@@ -0,0 +1,555 @@ -+/* -+ * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * Copyright (C) 2004 Infineon IFAP DC COM CPE -+ * Copyright (C) 2007 Felix Fietkau -+ * Copyright (C) 2007 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+ -+#define PORT_IFXMIPSASC 111 -+ -+#include -+ -+#define UART_DUMMY_UER_RX 1 -+ -+static void ifxmipsasc_tx_chars(struct uart_port *port); -+extern void prom_printf(const char *fmt, ...); -+static struct uart_port ifxmipsasc_port[2]; -+static struct uart_driver ifxmipsasc_reg; -+extern unsigned int ifxmips_get_fpi_hz(void); -+ -+static void ifxmipsasc_stop_tx(struct uart_port *port) -+{ -+ return; -+} -+ -+static void ifxmipsasc_start_tx(struct uart_port *port) -+{ -+ unsigned long flags; -+ local_irq_save(flags); -+ ifxmipsasc_tx_chars(port); -+ local_irq_restore(flags); -+ return; -+} -+ -+static void ifxmipsasc_stop_rx(struct uart_port *port) -+{ -+ ifxmips_w32(ASCWHBSTATE_CLRREN, port->membase + IFXMIPS_ASC_WHBSTATE); -+} -+ -+static void ifxmipsasc_enable_ms(struct uart_port *port) -+{ -+} -+ -+#include -+ -+static void ifxmipsasc_rx_chars(struct uart_port *port) -+{ -+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 26)) -+ struct tty_struct *tty = port->info->port.tty; -+#else -+ struct tty_struct *tty = port->info->tty; -+#endif -+ unsigned int ch = 0, rsr = 0, fifocnt; -+ -+ fifocnt = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_RXFFLMASK; -+ while (fifocnt--) { -+ u8 flag = TTY_NORMAL; -+ ch = ifxmips_r32(port->membase + IFXMIPS_ASC_RBUF); -+ rsr = (ifxmips_r32(port->membase + IFXMIPS_ASC_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX; -+ tty_flip_buffer_push(tty); -+ port->icount.rx++; -+ -+ /* -+ * Note that the error handling code is -+ * out of the main execution path -+ */ -+ if (rsr & ASCSTATE_ANY) { -+ if (rsr & ASCSTATE_PE) { -+ port->icount.parity++; -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE, port->membase + IFXMIPS_ASC_WHBSTATE); -+ } else if (rsr & ASCSTATE_FE) { -+ port->icount.frame++; -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRFE, port->membase + IFXMIPS_ASC_WHBSTATE); -+ } -+ if (rsr & ASCSTATE_ROE) { -+ port->icount.overrun++; -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE); -+ } -+ -+ rsr &= port->read_status_mask; -+ -+ if (rsr & ASCSTATE_PE) -+ flag = TTY_PARITY; -+ else if (rsr & ASCSTATE_FE) -+ flag = TTY_FRAME; -+ } -+ -+ if ((rsr & port->ignore_status_mask) == 0) -+ tty_insert_flip_char(tty, ch, flag); -+ -+ if (rsr & ASCSTATE_ROE) -+ /* -+ * Overrun is special, since it's reported -+ * immediately, and doesn't affect the current -+ * character -+ */ -+ tty_insert_flip_char(tty, 0, TTY_OVERRUN); -+ } -+ if (ch != 0) -+ tty_flip_buffer_push(tty); -+ return; -+} -+ -+ -+static void ifxmipsasc_tx_chars(struct uart_port *port) -+{ -+ struct circ_buf *xmit = &port->info->xmit; -+ if (uart_tx_stopped(port)) { -+ ifxmipsasc_stop_tx(port); -+ return; -+ } -+ -+ while (((ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK) -+ >> ASCFSTAT_TXFFLOFF) != TXFIFO_FULL) { -+ if (port->x_char) { -+ ifxmips_w32(port->x_char, port->membase + IFXMIPS_ASC_TBUF); -+ port->icount.tx++; -+ port->x_char = 0; -+ continue; -+ } -+ -+ if (uart_circ_empty(xmit)) -+ break; -+ -+ ifxmips_w32(port->info->xmit.buf[port->info->xmit.tail], port->membase + IFXMIPS_ASC_TBUF); -+ xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); -+ port->icount.tx++; -+ } -+ -+ if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) -+ uart_write_wakeup(port); -+} -+ -+static irqreturn_t ifxmipsasc_tx_int(int irq, void *_port) -+{ -+ struct uart_port *port = (struct uart_port *)_port; -+ ifxmips_w32(ASC_IRNCR_TIR, port->membase + IFXMIPS_ASC_IRNCR); -+ ifxmipsasc_start_tx(port); -+ ifxmips_mask_and_ack_irq(irq); -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t ifxmipsasc_er_int(int irq, void *_port) -+{ -+ struct uart_port *port = (struct uart_port *)_port; -+ /* clear any pending interrupts */ -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_WHBSTATE) | ASCWHBSTATE_CLRPE | -+ ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, port->membase + IFXMIPS_ASC_WHBSTATE); -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t ifxmipsasc_rx_int(int irq, void *_port) -+{ -+ struct uart_port *port = (struct uart_port *)_port; -+ ifxmips_w32(ASC_IRNCR_RIR, port->membase + IFXMIPS_ASC_IRNCR); -+ ifxmipsasc_rx_chars((struct uart_port *)port); -+ ifxmips_mask_and_ack_irq(irq); -+ return IRQ_HANDLED; -+} -+ -+static unsigned int ifxmipsasc_tx_empty(struct uart_port *port) -+{ -+ int status; -+ status = ifxmips_r32(port->membase + IFXMIPS_ASC_FSTAT) & ASCFSTAT_TXFFLMASK; -+ return status ? 0 : TIOCSER_TEMT; -+} -+ -+static unsigned int ifxmipsasc_get_mctrl(struct uart_port *port) -+{ -+ return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR; -+} -+ -+static void ifxmipsasc_set_mctrl(struct uart_port *port, u_int mctrl) -+{ -+} -+ -+static void ifxmipsasc_break_ctl(struct uart_port *port, int break_state) -+{ -+} -+ -+static int ifxmipsasc_startup(struct uart_port *port) -+{ -+ int retval; -+ -+ port->uartclk = ifxmips_get_fpi_hz(); -+ -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~IFXMIPS_ASC_CLC_DISS, port->membase + IFXMIPS_ASC_CLC); -+ ifxmips_w32(((ifxmips_r32(port->membase + IFXMIPS_ASC_CLC) & ~ASCCLC_RMCMASK)) | (1 << ASCCLC_RMCOFFSET), port->membase + IFXMIPS_ASC_CLC); -+ ifxmips_w32(0, port->membase + IFXMIPS_ASC_PISEL); -+ ifxmips_w32(((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON); -+ ifxmips_w32(((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON); -+ wmb(); -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN, port->membase + IFXMIPS_ASC_CON); -+ -+ retval = request_irq(port->irq, ifxmipsasc_tx_int, IRQF_DISABLED, "asc_tx", port); -+ if (retval) { -+ printk(KERN_ERR "failed to request ifxmipsasc_tx_int\n"); -+ return retval; -+ } -+ -+ retval = request_irq(port->irq + 2, ifxmipsasc_rx_int, IRQF_DISABLED, "asc_rx", port); -+ if (retval) { -+ printk(KERN_ERR "failed to request ifxmipsasc_rx_int\n"); -+ goto err1; -+ } -+ -+ retval = request_irq(port->irq + 3, ifxmipsasc_er_int, IRQF_DISABLED, "asc_er", port); -+ if (retval) { -+ printk(KERN_ERR "failed to request ifxmipsasc_er_int\n"); -+ goto err2; -+ } -+ -+ ifxmips_w32(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX, port->membase + IFXMIPS_ASC_IRNREN); -+ return 0; -+ -+err2: -+ free_irq(port->irq + 2, port); -+err1: -+ free_irq(port->irq, port); -+ return retval; -+} -+ -+static void ifxmipsasc_shutdown(struct uart_port *port) -+{ -+ free_irq(port->irq, port); -+ free_irq(port->irq + 2, port); -+ free_irq(port->irq + 3, port); -+ -+ ifxmips_w32(0, port->membase + IFXMIPS_ASC_CON); -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) | ASCRXFCON_RXFFLU, port->membase + IFXMIPS_ASC_RXFCON); -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_RXFCON) & ~ASCRXFCON_RXFEN, port->membase + IFXMIPS_ASC_RXFCON); -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) | ASCTXFCON_TXFFLU, port->membase + IFXMIPS_ASC_TXFCON); -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_TXFCON) & ~ASCTXFCON_TXFEN, port->membase + IFXMIPS_ASC_TXFCON); -+} -+ -+static void ifxmipsasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old) -+{ -+ unsigned int cflag; -+ unsigned int iflag; -+ unsigned int quot; -+ unsigned int baud; -+ unsigned int con = 0; -+ unsigned long flags; -+ -+ cflag = new->c_cflag; -+ iflag = new->c_iflag; -+ -+ switch (cflag & CSIZE) { -+ case CS7: -+ con = ASCCON_M_7ASYNC; -+ break; -+ -+ case CS5: -+ case CS6: -+ default: -+ con = ASCCON_M_8ASYNC; -+ break; -+ } -+ -+ if (cflag & CSTOPB) -+ con |= ASCCON_STP; -+ -+ if (cflag & PARENB) { -+ if (!(cflag & PARODD)) -+ con &= ~ASCCON_ODD; -+ else -+ con |= ASCCON_ODD; -+ } -+ -+ port->read_status_mask = ASCSTATE_ROE; -+ if (iflag & INPCK) -+ port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE; -+ -+ port->ignore_status_mask = 0; -+ if (iflag & IGNPAR) -+ port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE; -+ -+ if (iflag & IGNBRK) { -+ /* -+ * If we're ignoring parity and break indicators, -+ * ignore overruns too (for real raw support). -+ */ -+ if (iflag & IGNPAR) -+ port->ignore_status_mask |= ASCSTATE_ROE; -+ } -+ -+ if ((cflag & CREAD) == 0) -+ port->ignore_status_mask |= UART_DUMMY_UER_RX; -+ -+ /* set error signals - framing, parity and overrun, enable receiver */ -+ con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN; -+ -+ local_irq_save(flags); -+ -+ /* set up CON */ -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | con, port->membase + IFXMIPS_ASC_CON); -+ -+ /* Set baud rate - take a divider of 2 into account */ -+ baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); -+ quot = uart_get_divisor(port, baud); -+ quot = quot / 2 - 1; -+ -+ /* disable the baudrate generator */ -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_R, port->membase + IFXMIPS_ASC_CON); -+ -+ /* make sure the fractional divider is off */ -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_FDE, port->membase + IFXMIPS_ASC_CON); -+ -+ /* set up to use divisor of 2 */ -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) & ~ASCCON_BRS, port->membase + IFXMIPS_ASC_CON); -+ -+ /* now we can write the new baudrate into the register */ -+ ifxmips_w32(quot, port->membase + IFXMIPS_ASC_BG); -+ -+ /* turn the baudrate generator back on */ -+ ifxmips_w32(ifxmips_r32(port->membase + IFXMIPS_ASC_CON) | ASCCON_R, port->membase + IFXMIPS_ASC_CON); -+ -+ /* enable rx */ -+ ifxmips_w32(ASCWHBSTATE_SETREN, port->membase + IFXMIPS_ASC_WHBSTATE); -+ -+ local_irq_restore(flags); -+} -+ -+static const char *ifxmipsasc_type(struct uart_port *port) -+{ -+ if (port->type == PORT_IFXMIPSASC) { -+ if (port->membase == (void *)IFXMIPS_ASC_BASE_ADDR) -+ return "asc0"; -+ else -+ return "asc1"; -+ } else { -+ return NULL; -+ } -+} -+ -+static void ifxmipsasc_release_port(struct uart_port *port) -+{ -+} -+ -+static int ifxmipsasc_request_port(struct uart_port *port) -+{ -+ return 0; -+} -+ -+static void ifxmipsasc_config_port(struct uart_port *port, int flags) -+{ -+ if (flags & UART_CONFIG_TYPE) { -+ port->type = PORT_IFXMIPSASC; -+ ifxmipsasc_request_port(port); -+ } -+} -+ -+static int ifxmipsasc_verify_port(struct uart_port *port, struct serial_struct *ser) -+{ -+ int ret = 0; -+ if (ser->type != PORT_UNKNOWN && ser->type != PORT_IFXMIPSASC) -+ ret = -EINVAL; -+ if (ser->irq < 0 || ser->irq >= NR_IRQS) -+ ret = -EINVAL; -+ if (ser->baud_base < 9600) -+ ret = -EINVAL; -+ return ret; -+} -+ -+static struct uart_ops ifxmipsasc_pops = { -+ .tx_empty = ifxmipsasc_tx_empty, -+ .set_mctrl = ifxmipsasc_set_mctrl, -+ .get_mctrl = ifxmipsasc_get_mctrl, -+ .stop_tx = ifxmipsasc_stop_tx, -+ .start_tx = ifxmipsasc_start_tx, -+ .stop_rx = ifxmipsasc_stop_rx, -+ .enable_ms = ifxmipsasc_enable_ms, -+ .break_ctl = ifxmipsasc_break_ctl, -+ .startup = ifxmipsasc_startup, -+ .shutdown = ifxmipsasc_shutdown, -+ .set_termios = ifxmipsasc_set_termios, -+ .type = ifxmipsasc_type, -+ .release_port = ifxmipsasc_release_port, -+ .request_port = ifxmipsasc_request_port, -+ .config_port = ifxmipsasc_config_port, -+ .verify_port = ifxmipsasc_verify_port, -+}; -+ -+static struct uart_port ifxmipsasc_port[2] = { -+ { -+ .membase = (void *)IFXMIPS_ASC_BASE_ADDR, -+ .mapbase = IFXMIPS_ASC_BASE_ADDR, -+ .iotype = SERIAL_IO_MEM, -+ .irq = IFXMIPSASC_TIR(0), -+ .uartclk = 0, -+ .fifosize = 16, -+ .type = PORT_IFXMIPSASC, -+ .ops = &ifxmipsasc_pops, -+ .flags = ASYNC_BOOT_AUTOCONF, -+ .line = 0 -+ }, { -+ .membase = (void *)(IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF), -+ .mapbase = IFXMIPS_ASC_BASE_ADDR + IFXMIPS_ASC_BASE_DIFF, -+ .iotype = SERIAL_IO_MEM, -+ .irq = IFXMIPSASC_TIR(1), -+ .uartclk = 0, -+ .fifosize = 16, -+ .type = PORT_IFXMIPSASC, -+ .ops = &ifxmipsasc_pops, -+ .flags = ASYNC_BOOT_AUTOCONF, -+ .line = 1 -+ } -+}; -+ -+static void ifxmipsasc_console_write(struct console *co, const char *s, u_int count) -+{ -+ int port = co->index; -+ int i, fifocnt; -+ unsigned long flags; -+ local_irq_save(flags); -+ for (i = 0; i < count; i++) { -+ do { -+ fifocnt = (ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK) -+ >> ASCFSTAT_TXFFLOFF; -+ } while (fifocnt == TXFIFO_FULL); -+ -+ if (s[i] == '\0') -+ break; -+ -+ if (s[i] == '\n') { -+ ifxmips_w32('\r', (u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF)); -+ do { -+ fifocnt = (ifxmips_r32((u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_FSTAT)) & ASCFSTAT_TXFFLMASK) -+ >> ASCFSTAT_TXFFLOFF; -+ } while (fifocnt == TXFIFO_FULL); -+ } -+ ifxmips_w32(s[i], (u32 *)(IFXMIPS_ASC_BASE_ADDR + (port * IFXMIPS_ASC_BASE_DIFF) + IFXMIPS_ASC_TBUF)); -+ } -+ -+ local_irq_restore(flags); -+} -+ -+static int __init ifxmipsasc_console_setup(struct console *co, char *options) -+{ -+ int port = co->index; -+ int baud = 115200; -+ int bits = 8; -+ int parity = 'n'; -+ int flow = 'n'; -+ ifxmipsasc_port[port].uartclk = ifxmips_get_fpi_hz(); -+ ifxmipsasc_port[port].type = PORT_IFXMIPSASC; -+ if (options) -+ uart_parse_options(options, &baud, &parity, &bits, &flow); -+ return uart_set_options(&ifxmipsasc_port[port], co, baud, parity, bits, flow); -+} -+ -+static struct console ifxmipsasc_console[2] = -+{ -+ { -+ .name = "ttyS", -+ .write = ifxmipsasc_console_write, -+ .device = uart_console_device, -+ .setup = ifxmipsasc_console_setup, -+ .flags = CON_PRINTBUFFER, -+ .index = 0, -+ .data = &ifxmipsasc_reg, -+ }, { -+ .name = "ttyS", -+ .write = ifxmipsasc_console_write, -+ .device = uart_console_device, -+ .setup = ifxmipsasc_console_setup, -+ .flags = CON_PRINTBUFFER, -+ .index = 1, -+ .data = &ifxmipsasc_reg, -+ } -+}; -+ -+static int __init ifxmipsasc_console_init(void) -+{ -+ register_console(&ifxmipsasc_console[0]); -+ register_console(&ifxmipsasc_console[1]); -+ return 0; -+} -+console_initcall(ifxmipsasc_console_init); -+ -+static struct uart_driver ifxmipsasc_reg = { -+ .owner = THIS_MODULE, -+ .driver_name = "serial", -+ .dev_name = "ttyS", -+ .major = TTY_MAJOR, -+ .minor = 64, -+ .nr = 2, -+ .cons = &ifxmipsasc_console[1], -+}; -+ -+int __init ifxmipsasc_init(void) -+{ -+ int ret; -+ uart_register_driver(&ifxmipsasc_reg); -+ ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[0]); -+ ret = uart_add_one_port(&ifxmipsasc_reg, &ifxmipsasc_port[1]); -+ return 0; -+} -+ -+void __exit ifxmipsasc_exit(void) -+{ -+ uart_unregister_driver(&ifxmipsasc_reg); -+} -+ -+module_init(ifxmipsasc_init); -+module_exit(ifxmipsasc_exit); -+ -+MODULE_AUTHOR("John Crispin "); -+MODULE_DESCRIPTION("MIPS IFXMips serial port driver"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/ifxmips/patches-2.6.30/130-ethernet.patch b/target/linux/ifxmips/patches-2.6.30/130-ethernet.patch deleted file mode 100644 index 30f169304e..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/130-ethernet.patch +++ /dev/null @@ -1,524 +0,0 @@ -Index: linux-2.6.30.8/drivers/net/Kconfig -=================================================================== ---- linux-2.6.30.8.orig/drivers/net/Kconfig 2009-10-19 21:31:30.000000000 +0200 -+++ linux-2.6.30.8/drivers/net/Kconfig 2009-10-19 21:31:32.000000000 +0200 -@@ -353,6 +353,12 @@ - - source "drivers/net/arm/Kconfig" - -+config IFXMIPS_MII0 -+ tristate "Infineon IFXMips eth0 driver" -+ depends on IFXMIPS -+ help -+ Support for the MII0 inside the IFXMips SOC -+ - config AX88796 - tristate "ASIX AX88796 NE2000 clone support" - depends on ARM || MIPS || SUPERH -Index: linux-2.6.30.8/drivers/net/Makefile -=================================================================== ---- linux-2.6.30.8.orig/drivers/net/Makefile 2009-10-19 21:31:30.000000000 +0200 -+++ linux-2.6.30.8/drivers/net/Makefile 2009-10-19 21:31:32.000000000 +0200 -@@ -234,6 +234,7 @@ - obj-$(CONFIG_MLX4_CORE) += mlx4/ - obj-$(CONFIG_ENC28J60) += enc28j60.o - obj-$(CONFIG_ETHOC) += ethoc.o -+obj-$(CONFIG_IFXMIPS_MII0) += ifxmips_mii0.o - - obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o - -Index: linux-2.6.30.8/drivers/net/ifxmips_mii0.c -=================================================================== ---- /dev/null 2010-01-25 20:01:36.843225078 +0100 -+++ linux-2.6.30.10/drivers/net/ifxmips_mii0.c 2010-03-13 19:04:25.000000000 +0100 -@@ -0,0 +1,489 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2005 Wu Qi Ming -+ * Copyright (C) 2008 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+ -+struct ifxmips_mii_priv { -+ struct net_device_stats stats; -+ struct dma_device_info *dma_device; -+ struct sk_buff *skb; -+ -+ struct mii_bus *mii_bus; -+ struct phy_device *phydev; -+ int oldlink, oldspeed, oldduplex; -+}; -+ -+static struct net_device *ifxmips_mii0_dev; -+static unsigned char mac_addr[MAX_ADDR_LEN]; -+ -+static int ifxmips_mdiobus_write(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data) -+{ -+ u32 val = MDIO_ACC_REQUEST | -+ ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) | -+ ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) | -+ phy_data; -+ -+ while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST) -+ ; -+ ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC); -+ -+ return 0; -+} -+ -+static int ifxmips_mdiobus_read(struct mii_bus *bus, int phy_addr, int phy_reg) -+{ -+ u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ | -+ ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) | -+ ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET); -+ -+ while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST) -+ ; -+ ifxmips_w32(val, IFXMIPS_PPE32_MDIO_ACC); -+ while (ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST) -+ ; -+ val = ifxmips_r32(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK; -+ return val; -+} -+ -+int ifxmips_ifxmips_mii_open(struct net_device *dev) -+{ -+ struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev); -+ struct dma_device_info *dma_dev = priv->dma_device; -+ int i; -+ -+ for (i = 0; i < dma_dev->max_rx_chan_num; i++) { -+ if ((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON) -+ (dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]); -+ } -+ netif_start_queue(dev); -+ return 0; -+} -+ -+int ifxmips_mii_release(struct net_device *dev) -+{ -+ struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev); -+ struct dma_device_info *dma_dev = priv->dma_device; -+ int i; -+ -+ for (i = 0; i < dma_dev->max_rx_chan_num; i++) -+ dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]); -+ netif_stop_queue(dev); -+ return 0; -+} -+ -+int ifxmips_mii_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev) -+{ -+ struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev); -+ unsigned char *buf = NULL; -+ struct sk_buff *skb = NULL; -+ int len = 0; -+ -+ len = dma_device_read(dma_dev, &buf, (void **)&skb); -+ -+ if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) { -+ printk(KERN_INFO "ifxmips_mii0: packet too large %d\n", len); -+ goto ifxmips_mii_hw_receive_err_exit; -+ } -+ -+ /* remove CRC */ -+ len -= 4; -+ if (skb == NULL) { -+ printk(KERN_INFO "ifxmips_mii0: cannot restore pointer\n"); -+ goto ifxmips_mii_hw_receive_err_exit; -+ } -+ -+ if (len > (skb->end - skb->tail)) { -+ printk(KERN_INFO "ifxmips_mii0: BUG, len:%d end:%p tail:%p\n", -+ (len+4), skb->end, skb->tail); -+ goto ifxmips_mii_hw_receive_err_exit; -+ } -+ -+ skb_put(skb, len); -+ skb->dev = dev; -+ skb->protocol = eth_type_trans(skb, dev); -+ netif_rx(skb); -+ -+ priv->stats.rx_packets++; -+ priv->stats.rx_bytes += len; -+ return 0; -+ -+ifxmips_mii_hw_receive_err_exit: -+ if (len == 0) { -+ if (skb) -+ dev_kfree_skb_any(skb); -+ priv->stats.rx_errors++; -+ priv->stats.rx_dropped++; -+ return -EIO; -+ } else { -+ return len; -+ } -+} -+ -+int ifxmips_mii_hw_tx(char *buf, int len, struct net_device *dev) -+{ -+ int ret = 0; -+ struct ifxmips_mii_priv *priv = netdev_priv(dev); -+ struct dma_device_info *dma_dev = priv->dma_device; -+ ret = dma_device_write(dma_dev, buf, len, priv->skb); -+ return ret; -+} -+ -+int ifxmips_mii_tx(struct sk_buff *skb, struct net_device *dev) -+{ -+ int len; -+ char *data; -+ struct ifxmips_mii_priv *priv = netdev_priv(dev); -+ struct dma_device_info *dma_dev = priv->dma_device; -+ -+ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; -+ data = skb->data; -+ priv->skb = skb; -+ dev->trans_start = jiffies; -+ /* TODO: we got more than 1 dma channel, -+ so we should do something intelligent here to select one */ -+ dma_dev->current_tx_chan = 0; -+ -+ wmb(); -+ -+ if (ifxmips_mii_hw_tx(data, len, dev) != len) { -+ dev_kfree_skb_any(skb); -+ priv->stats.tx_errors++; -+ priv->stats.tx_dropped++; -+ } else { -+ priv->stats.tx_packets++; -+ priv->stats.tx_bytes += len; -+ } -+ -+ return 0; -+} -+ -+void ifxmips_mii_tx_timeout(struct net_device *dev) -+{ -+ int i; -+ struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev); -+ -+ priv->stats.tx_errors++; -+ for (i = 0; i < priv->dma_device->max_tx_chan_num; i++) -+ priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]); -+ netif_wake_queue(dev); -+ return; -+} -+ -+int dma_intr_handler(struct dma_device_info *dma_dev, int status) -+{ -+ int i; -+ -+ switch (status) { -+ case RCV_INT: -+ ifxmips_mii_hw_receive(ifxmips_mii0_dev, dma_dev); -+ break; -+ -+ case TX_BUF_FULL_INT: -+ printk(KERN_INFO "ifxmips_mii0: tx buffer full\n"); -+ netif_stop_queue(ifxmips_mii0_dev); -+ for (i = 0; i < dma_dev->max_tx_chan_num; i++) { -+ if ((dma_dev->tx_chan[i])->control == IFXMIPS_DMA_CH_ON) -+ dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]); -+ } -+ break; -+ -+ case TRANSMIT_CPT_INT: -+ for (i = 0; i < dma_dev->max_tx_chan_num; i++) -+ dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]); -+ -+ netif_wake_queue(ifxmips_mii0_dev); -+ break; -+ } -+ -+ return 0; -+} -+ -+unsigned char *ifxmips_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt) -+{ -+ unsigned char *buffer = NULL; -+ struct sk_buff *skb = NULL; -+ -+ skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE); -+ if (skb == NULL) -+ return NULL; -+ -+ buffer = (unsigned char *)(skb->data); -+ skb_reserve(skb, 2); -+ *(int *)opt = (int)skb; -+ *byte_offset = 2; -+ -+ return buffer; -+} -+ -+void ifxmips_etop_dma_buffer_free(unsigned char *dataptr, void *opt) -+{ -+ struct sk_buff *skb = NULL; -+ -+ if (opt == NULL) { -+ kfree(dataptr); -+ } else { -+ skb = (struct sk_buff *)opt; -+ dev_kfree_skb_any(skb); -+ } -+} -+ -+static struct net_device_stats *ifxmips_get_stats(struct net_device *dev) -+{ -+ return &((struct ifxmips_mii_priv *)netdev_priv(dev))->stats; -+} -+ -+static void -+ifxmips_adjust_link(struct net_device *dev) -+{ -+ struct ifxmips_mii_priv *priv = netdev_priv(dev); -+ struct phy_device *phydev = priv->phydev; -+ int new_state = 0; -+ -+ /* Did anything change? */ -+ if (priv->oldlink != phydev->link || -+ priv->oldduplex != phydev->duplex || -+ priv->oldspeed != phydev->speed) { -+ /* Yes, so update status and mark as changed */ -+ new_state = 1; -+ priv->oldduplex = phydev->duplex; -+ priv->oldspeed = phydev->speed; -+ priv->oldlink = phydev->link; -+ } -+ -+ /* If link status changed, show new status */ -+ if (new_state) -+ phy_print_status(phydev); -+} -+ -+static int mii_probe(struct net_device *dev) -+{ -+ struct ifxmips_mii_priv *priv = netdev_priv(dev); -+ struct phy_device *phydev = NULL; -+ int phy_addr; -+ -+ priv->oldlink = 0; -+ priv->oldspeed = 0; -+ priv->oldduplex = -1; -+ -+ /* find the first (lowest address) PHY on the current MAC's MII bus */ -+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { -+ if (priv->mii_bus->phy_map[phy_addr]) { -+ phydev = priv->mii_bus->phy_map[phy_addr]; -+ break; /* break out with first one found */ -+ } -+ } -+ -+ if (!phydev) { -+ printk (KERN_ERR "%s: no PHY found\n", dev->name); -+ return -ENODEV; -+ } -+ -+ /* now we are supposed to have a proper phydev, to attach to... */ -+ BUG_ON(!phydev); -+ BUG_ON(phydev->attached_dev); -+ -+ phydev = phy_connect(dev, dev_name(&phydev->dev), &ifxmips_adjust_link, -+ 0, PHY_INTERFACE_MODE_MII); -+ -+ if (IS_ERR(phydev)) { -+ printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); -+ return PTR_ERR(phydev); -+ } -+ -+ /* mask with MAC supported features */ -+ phydev->supported &= (SUPPORTED_10baseT_Half -+ | SUPPORTED_10baseT_Full -+ | SUPPORTED_100baseT_Half -+ | SUPPORTED_100baseT_Full -+ | SUPPORTED_Autoneg -+ /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */ -+ | SUPPORTED_MII -+ | SUPPORTED_TP); -+ -+ phydev->advertising = phydev->supported; -+ -+ priv->phydev = phydev; -+ -+ printk(KERN_INFO "%s: attached PHY driver [%s] " -+ "(mii_bus:phy_addr=%s, irq=%d)\n", -+ dev->name, phydev->drv->name, dev_name(&phydev->dev), phydev->irq); -+ -+ return 0; -+} -+ -+ -+static int ifxmips_mii_dev_init(struct net_device *dev) -+{ -+ int i; -+ struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(dev); -+ ether_setup(dev); -+ dev->open = ifxmips_ifxmips_mii_open; -+ dev->stop = ifxmips_mii_release; -+ dev->hard_start_xmit = ifxmips_mii_tx; -+ dev->get_stats = ifxmips_get_stats; -+ dev->tx_timeout = ifxmips_mii_tx_timeout; -+ dev->watchdog_timeo = 10 * HZ; -+ memset(priv, 0, sizeof(struct ifxmips_mii_priv)); -+ priv->dma_device = dma_device_reserve("PPE"); -+ if (!priv->dma_device) { -+ BUG(); -+ return -ENODEV; -+ } -+ priv->dma_device->buffer_alloc = &ifxmips_etop_dma_buffer_alloc; -+ priv->dma_device->buffer_free = &ifxmips_etop_dma_buffer_free; -+ priv->dma_device->intr_handler = &dma_intr_handler; -+ priv->dma_device->max_rx_chan_num = 4; -+ -+ for (i = 0; i < priv->dma_device->max_rx_chan_num; i++) { -+ priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE; -+ priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON; -+ } -+ -+ for (i = 0; i < priv->dma_device->max_tx_chan_num; i++) -+ if (i == 0) -+ priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON; -+ else -+ priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF; -+ -+ dma_device_register(priv->dma_device); -+ -+ printk(KERN_INFO "%s: using mac=", dev->name); -+ for (i = 0; i < 6; i++) { -+ dev->dev_addr[i] = mac_addr[i]; -+ printk("%02X%c", dev->dev_addr[i], (i == 5) ? ('\n') : (':')); -+ } -+ -+ priv->mii_bus = mdiobus_alloc(); -+ if (priv->mii_bus == NULL) -+ return -ENOMEM; -+ -+ priv->mii_bus->priv = dev; -+ priv->mii_bus->read = ifxmips_mdiobus_read; -+ priv->mii_bus->write = ifxmips_mdiobus_write; -+ priv->mii_bus->name = "ifxmips_mii"; -+ snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); -+ priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); -+ for(i = 0; i < PHY_MAX_ADDR; ++i) -+ priv->mii_bus->irq[i] = PHY_POLL; -+ -+ mdiobus_register(priv->mii_bus); -+ -+ return mii_probe(dev); -+} -+ -+static void ifxmips_mii_chip_init(int mode) -+{ -+ ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA); -+ ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE); -+ -+ if (mode == REV_MII_MODE) -+ ifxmips_w32_mask(PPE32_MII_MASK, PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG); -+ else if (mode == MII_MODE) -+ ifxmips_w32_mask(PPE32_MII_MASK, PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG); -+ ifxmips_w32(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL); -+ ifxmips_w32(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG); -+ wmb(); -+} -+ -+static int ifxmips_mii_probe(struct platform_device *dev) -+{ -+ int result = 0; -+ unsigned char *mac = (unsigned char *)dev->dev.platform_data; -+ ifxmips_mii0_dev = alloc_etherdev(sizeof(struct ifxmips_mii_priv)); -+ ifxmips_mii0_dev->init = ifxmips_mii_dev_init; -+ memcpy(mac_addr, mac, 6); -+ strcpy(ifxmips_mii0_dev->name, "eth%d"); -+ ifxmips_mii_chip_init(REV_MII_MODE); -+ result = register_netdev(ifxmips_mii0_dev); -+ if (result) { -+ printk(KERN_INFO "ifxmips_mii0: error %i registering device \"%s\"\n", result, ifxmips_mii0_dev->name); -+ goto out; -+ } -+ -+ printk(KERN_INFO "ifxmips_mii0: driver loaded!\n"); -+ -+out: -+ return result; -+} -+ -+static int ifxmips_mii_remove(struct platform_device *dev) -+{ -+ struct ifxmips_mii_priv *priv = (struct ifxmips_mii_priv *)netdev_priv(ifxmips_mii0_dev); -+ -+ printk(KERN_INFO "ifxmips_mii0: ifxmips_mii0 cleanup\n"); -+ -+ dma_device_unregister(priv->dma_device); -+ dma_device_release(priv->dma_device); -+ kfree(priv->dma_device); -+ unregister_netdev(ifxmips_mii0_dev); -+ return 0; -+} -+ -+static struct platform_driver ifxmips_mii_driver = { -+ .probe = ifxmips_mii_probe, -+ .remove = ifxmips_mii_remove, -+ .driver = { -+ .name = "ifxmips_mii0", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int __init ifxmips_mii_init(void) -+{ -+ int ret = platform_driver_register(&ifxmips_mii_driver); -+ if (ret) -+ printk(KERN_INFO "ifxmips_mii0: Error registering platfom driver!"); -+ return ret; -+} -+ -+static void __exit ifxmips_mii_cleanup(void) -+{ -+ platform_driver_unregister(&ifxmips_mii_driver); -+} -+ -+module_init(ifxmips_mii_init); -+module_exit(ifxmips_mii_cleanup); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("John Crispin "); -+MODULE_DESCRIPTION("ethernet driver for IFXMIPS boards"); -+ diff --git a/target/linux/ifxmips/patches-2.6.30/140-mtd.patch b/target/linux/ifxmips/patches-2.6.30/140-mtd.patch deleted file mode 100644 index 184c78ca98..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/140-mtd.patch +++ /dev/null @@ -1,296 +0,0 @@ -Index: linux-2.6.30.10/drivers/mtd/maps/Makefile -=================================================================== ---- linux-2.6.30.10.orig/drivers/mtd/maps/Makefile 2009-12-04 07:00:07.000000000 +0100 -+++ linux-2.6.30.10/drivers/mtd/maps/Makefile 2010-03-24 15:32:04.000000000 +0100 -@@ -62,3 +62,4 @@ - obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-async-flash.o - obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o - obj-$(CONFIG_MTD_VMU) += vmu-flash.o -+obj-$(CONFIG_MTD_IFXMIPS) += ifxmips.o -Index: linux-2.6.30.10/drivers/mtd/maps/ifxmips.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.30.10/drivers/mtd/maps/ifxmips.c 2010-03-24 16:46:26.000000000 +0100 -@@ -0,0 +1,282 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * Copyright (C) 2004 Liu Peng Infineon IFAP DC COM CPE -+ * Copyright (C) 2008 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#ifndef CONFIG_MTD_PARTITIONS -+#error Please enable CONFIG_MTD_PARTITIONS -+#endif -+ -+static struct map_info ifxmips_map = { -+ .name = "ifx-nor", -+ .bankwidth = 2, -+ .size = 0x400000, -+}; -+ -+static map_word ifxmips_read16(struct map_info *map, unsigned long adr) -+{ -+ unsigned long flags; -+ map_word temp; -+ spin_lock_irqsave(&ebu_lock, flags); -+ adr ^= 2; -+ temp.x[0] = *((__u16 *)(map->virt + adr)); -+ spin_unlock_irqrestore(&ebu_lock, flags); -+ return temp; -+} -+ -+static void ifxmips_write16(struct map_info *map, map_word d, unsigned long adr) -+{ -+ unsigned long flags; -+ spin_lock_irqsave(&ebu_lock, flags); -+ adr ^= 2; -+ *((__u16 *)(map->virt + adr)) = d.x[0]; -+ spin_unlock_irqrestore(&ebu_lock, flags); -+} -+ -+void ifxmips_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len) -+{ -+ unsigned char *p; -+ unsigned char *to_8; -+ unsigned long flags; -+ spin_lock_irqsave(&ebu_lock, flags); -+ from = (unsigned long)(from + map->virt); -+ p = (unsigned char *) from; -+ to_8 = (unsigned char *) to; -+ while (len--) -+ *to_8++ = *p++; -+ spin_unlock_irqrestore(&ebu_lock, flags); -+} -+ -+void ifxmips_copy_to(struct map_info *map, -+ unsigned long to, -+ const void *from, -+ ssize_t len) -+{ -+ unsigned char *p = (unsigned char *)from; -+ unsigned char *to_8; -+ unsigned long flags; -+ spin_lock_irqsave(&ebu_lock, flags); -+ to += (unsigned long) map->virt; -+ to_8 = (unsigned char *)to; -+ while (len--) -+ *p++ = *to_8++; -+ spin_unlock_irqrestore(&ebu_lock, flags); -+} -+ -+static struct mtd_partition ifxmips_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0x00000000, -+ .size = 0x00020000, -+ }, -+ { -+ .name = "uboot_env", -+ .offset = 0x00020000, -+ .size = 0x0, -+ }, -+ { -+ .name = "kernel", -+ .offset = 0x0, -+ .size = 0x0, -+ }, -+ { -+ .name = "rootfs", -+ .offset = 0x0, -+ .size = 0x0, -+ }, -+ { -+ .name = "board_config", -+ .offset = 0x0, -+ .size = 0x0, -+ }, -+}; -+ -+static struct mtd_partition ifxmips_meta_partition = { -+ .name = "linux", -+ .offset = 0x00030000, -+ .size = 0x0, -+}; -+ -+static const char *part_probe_types[] = { "cmdlinepart", NULL }; -+ -+int find_uImage_size(unsigned long start_offset) -+{ -+ unsigned long magic; -+ unsigned long temp; -+ ifxmips_copy_from(&ifxmips_map, &magic, start_offset, 4); -+ if (le32_to_cpu(magic) != 0x56190527) { -+ printk(KERN_INFO "ifxmips_mtd: invalid magic (0x%08X) of kernel at 0x%08lx \n", le32_to_cpu(magic), start_offset); -+ return 0; -+ } -+ ifxmips_copy_from(&ifxmips_map, &temp, start_offset + 12, 4); -+ printk(KERN_INFO "ifxmips_mtd: kernel size is %ld \n", temp + 0x40); -+ return temp + 0x40; -+} -+ -+int find_brn_block(unsigned long start_offset) -+{ -+ unsigned char temp[9]; -+ ifxmips_copy_from(&ifxmips_map, &temp, start_offset, 8); -+ temp[8] = '\0'; -+ printk(KERN_INFO "data in brn block %s\n", temp); -+ if (memcmp(temp, "BRN-BOOT", 8) == 0) -+ return 1; -+ else -+ return 0; -+} -+ -+int detect_squashfs_partition(unsigned long start_offset) -+{ -+ unsigned long temp; -+ ifxmips_copy_from(&ifxmips_map, &temp, start_offset, 4); -+ return le32_to_cpu(temp) == SQUASHFS_MAGIC; -+} -+ -+static int ifxmips_mtd_probe(struct platform_device *dev) -+{ -+ struct mtd_info *ifxmips_mtd = NULL; -+ struct mtd_partition *parts = NULL; -+ unsigned long uimage_size; -+ int err, i; -+ int kernel_part = 2, rootfs_part = 3; -+ int num_parts = ARRAY_SIZE(ifxmips_partitions); -+ -+ ifxmips_w32(0x1d7ff, IFXMIPS_EBU_BUSCON0); -+ -+ ifxmips_map.read = ifxmips_read16; -+ ifxmips_map.write = ifxmips_write16; -+ ifxmips_map.copy_from = ifxmips_copy_from; -+ ifxmips_map.copy_to = ifxmips_copy_to; -+ ifxmips_map.phys = dev->resource->start; -+ ifxmips_map.size = dev->resource->end - ifxmips_map.phys + 1; -+ ifxmips_map.virt = ioremap_nocache(ifxmips_map.phys, ifxmips_map.size); -+ -+ if (!ifxmips_map.virt) { -+ printk(KERN_WARNING "ifxmips_mtd: failed to ioremap!\n"); -+ return -EIO; -+ } -+ -+ ifxmips_mtd = (struct mtd_info *) do_map_probe("cfi_probe", &ifxmips_map); -+ if (!ifxmips_mtd) { -+ iounmap(ifxmips_map.virt); -+ printk(KERN_WARNING "ifxmips_mtd: probing failed\n"); -+ return -ENXIO; -+ } -+ -+ ifxmips_mtd->owner = THIS_MODULE; -+ -+ err = parse_mtd_partitions(ifxmips_mtd, part_probe_types, &parts, 0); -+ if (err > 0) { -+ printk(KERN_INFO "ifxmips_mtd: found %d partitions from cmdline\n", err); -+ num_parts = err; -+ kernel_part = 0; -+ rootfs_part = 0; -+ for (i = 0; i < num_parts; i++) { -+ if (strcmp(parts[i].name, "kernel") == 0) -+ kernel_part = i; -+ if (strcmp(parts[i].name, "rootfs") == 0) -+ rootfs_part = i; -+ } -+ } else { -+ /* if the flash is 64k sectors, the kernel will reside at 0xb0030000 -+ if the flash is 128k sectors, the kernel will reside at 0xb0040000 */ -+ ifxmips_partitions[1].size = ifxmips_mtd->erasesize; -+ ifxmips_partitions[2].offset = ifxmips_partitions[1].offset + ifxmips_mtd->erasesize; -+ parts = &ifxmips_partitions[0]; -+ } -+ -+ /* dynamic size detection only if rootfs-part follows kernel-part */ -+ if (kernel_part+1 == rootfs_part) { -+ uimage_size = find_uImage_size(parts[kernel_part].offset); -+ -+ if (detect_squashfs_partition(parts[kernel_part].offset + uimage_size)) { -+ printk(KERN_INFO "ifxmips_mtd: found a squashfs following the uImage\n"); -+ } else { -+ uimage_size &= ~(ifxmips_mtd->erasesize -1); -+ uimage_size += ifxmips_mtd->erasesize; -+ } -+ -+ parts[kernel_part].size = uimage_size; -+ parts[rootfs_part].offset = parts[kernel_part].offset + parts[kernel_part].size; -+ parts[rootfs_part].size = ((ifxmips_mtd->size >> 20) * 1024 * 1024) - parts[rootfs_part].offset; -+ -+ ifxmips_meta_partition.offset = parts[kernel_part].offset; -+ ifxmips_meta_partition.size = parts[kernel_part].size + parts[rootfs_part].size; -+ } -+ -+ if (err <= 0) { -+ if (ifxmips_has_brn_block()) { -+ parts[3].size -= ifxmips_mtd->erasesize; -+ parts[4].offset = ifxmips_mtd->size - ifxmips_mtd->erasesize; -+ parts[4].size = ifxmips_mtd->erasesize; -+ ifxmips_meta_partition.size -= ifxmips_mtd->erasesize; -+ } else { -+ num_parts--; -+ } -+ } -+ -+ add_mtd_partitions(ifxmips_mtd, parts, num_parts); -+ add_mtd_partitions(ifxmips_mtd, &ifxmips_meta_partition, 1); -+ -+ printk(KERN_INFO "ifxmips_mtd: added %s flash with %dMB\n", -+ ifxmips_map.name, ((int)ifxmips_mtd->size) >> 20); -+ return 0; -+} -+ -+static struct platform_driver ifxmips_mtd_driver = { -+ .probe = ifxmips_mtd_probe, -+ .driver = { -+ .name = "ifxmips_mtd", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int __init init_ifxmips_mtd(void) -+{ -+ int ret = platform_driver_register(&ifxmips_mtd_driver); -+ if (ret) -+ printk(KERN_INFO "ifxmips_mtd: error registering platfom driver!"); -+ return ret; -+} -+ -+static void __exit cleanup_ifxmips_mtd(void) -+{ -+ platform_driver_unregister(&ifxmips_mtd_driver); -+} -+ -+module_init(init_ifxmips_mtd); -+module_exit(cleanup_ifxmips_mtd); -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("John Crispin "); -+MODULE_DESCRIPTION("MTD map driver for IFXMIPS boards"); diff --git a/target/linux/ifxmips/patches-2.6.30/150-wdt.patch b/target/linux/ifxmips/patches-2.6.30/150-wdt.patch deleted file mode 100644 index 8e668da9a8..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/150-wdt.patch +++ /dev/null @@ -1,229 +0,0 @@ -Index: linux-2.6.30.8/drivers/watchdog/Makefile -=================================================================== ---- linux-2.6.30.8.orig/drivers/watchdog/Makefile 2009-09-24 17:28:02.000000000 +0200 -+++ linux-2.6.30.8/drivers/watchdog/Makefile 2009-10-19 21:31:32.000000000 +0200 -@@ -105,6 +105,7 @@ - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o -+obj-$(CONFIG_IFXMIPS_WDT) += ifxmips_wdt.o - - # PARISC Architecture - -Index: linux-2.6.30.8/drivers/watchdog/Kconfig -=================================================================== ---- linux-2.6.30.8.orig/drivers/watchdog/Kconfig 2009-09-24 17:28:02.000000000 +0200 -+++ linux-2.6.30.8/drivers/watchdog/Kconfig 2009-10-19 21:31:32.000000000 +0200 -@@ -764,6 +764,12 @@ - help - Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs. - -+config IFXMIPS_WDT -+ bool "IFXMips watchdog" -+ depends on IFXMIPS -+ help -+ Hardware driver for the IFXMIPS Watchdog Timer. -+ - # PARISC Architecture - - # POWERPC Architecture -Index: linux-2.6.30.8/drivers/watchdog/ifxmips_wdt.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.30.8/drivers/watchdog/ifxmips_wdt.c 2009-10-19 21:40:17.000000000 +0200 -@@ -0,0 +1,195 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -+ * -+ * Copyright (C) 2008 John Crispin -+ * Based on EP93xx wdt driver -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define IFXMIPS_WDT_PW1 0x00BE0000 -+#define IFXMIPS_WDT_PW2 0x00DC0000 -+ -+#ifndef CONFIG_WATCHDOG_NOWAYOUT -+static int wdt_ok_to_close; -+#endif -+ -+static int wdt_timeout = 30; -+ -+int ifxmips_wdt_enable(unsigned int timeout) -+{ -+ u32 fpi; -+ fpi = cgu_get_io_region_clock(); -+ ifxmips_w32(IFXMIPS_WDT_PW1, IFXMIPS_BIU_WDT_CR); -+ ifxmips_w32(IFXMIPS_WDT_PW2 | -+ (0x3 << 26) | /* PWL */ -+ (0x3 << 24) | /* CLKDIV */ -+ (0x1 << 31) | /* enable */ -+ ((timeout * (fpi / 0x40000)) + 0x1000), /* reload */ -+ IFXMIPS_BIU_WDT_CR); -+ return 0; -+} -+ -+void ifxmips_wdt_disable(void) -+{ -+#ifndef CONFIG_WATCHDOG_NOWAYOUT -+ wdt_ok_to_close = 0; -+#endif -+ ifxmips_w32(IFXMIPS_WDT_PW1, IFXMIPS_BIU_WDT_CR); -+ ifxmips_w32(IFXMIPS_WDT_PW2, IFXMIPS_BIU_WDT_CR); -+} -+ -+static ssize_t ifxmips_wdt_write(struct file *file, const char __user *data, -+ size_t len, loff_t *ppos) -+{ -+ size_t i; -+ -+ if (!len) -+ return 0; -+ -+#ifndef CONFIG_WATCHDOG_NOWAYOUT -+ for (i = 0; i != len; i++) { -+ char c; -+ if (get_user(c, data + i)) -+ return -EFAULT; -+ if (c == 'V') -+ wdt_ok_to_close = 1; -+ } -+#endif -+ ifxmips_wdt_enable(wdt_timeout); -+ return len; -+} -+ -+static struct watchdog_info ident = { -+ .options = WDIOF_MAGICCLOSE, -+ .identity = "ifxmips Watchdog", -+}; -+ -+static int ifxmips_wdt_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, unsigned long arg) -+{ -+ int ret = -ENOTTY; -+ -+ switch (cmd) { -+ case WDIOC_GETSUPPORT: -+ ret = copy_to_user((struct watchdog_info __user *)arg, &ident, -+ sizeof(ident)) ? -EFAULT : 0; -+ break; -+ -+ case WDIOC_GETTIMEOUT: -+ ret = put_user(wdt_timeout, (int __user *)arg); -+ break; -+ -+ case WDIOC_SETTIMEOUT: -+ ret = get_user(wdt_timeout, (int __user *)arg); -+ break; -+ -+ case WDIOC_KEEPALIVE: -+ ifxmips_wdt_enable(wdt_timeout); -+ ret = 0; -+ break; -+ } -+ return ret; -+} -+ -+static int ifxmips_wdt_open(struct inode *inode, struct file *file) -+{ -+ ifxmips_wdt_enable(wdt_timeout); -+ return nonseekable_open(inode, file); -+} -+ -+static int ifxmips_wdt_release(struct inode *inode, struct file *file) -+{ -+#ifndef CONFIG_WATCHDOG_NOWAYOUT -+ if (wdt_ok_to_close) -+ ifxmips_wdt_disable(); -+ else -+#endif -+ printk(KERN_ERR "ifxmips_wdt: watchdog closed without warning," -+ " rebooting system\n"); -+ return 0; -+} -+ -+static const struct file_operations ifxmips_wdt_fops = { -+ .owner = THIS_MODULE, -+ .write = ifxmips_wdt_write, -+ .ioctl = ifxmips_wdt_ioctl, -+ .open = ifxmips_wdt_open, -+ .release = ifxmips_wdt_release, -+}; -+ -+static struct miscdevice ifxmips_wdt_miscdev = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &ifxmips_wdt_fops, -+}; -+ -+static int ifxmips_wdt_probe(struct platform_device *dev) -+{ -+ int err; -+ err = misc_register(&ifxmips_wdt_miscdev); -+ if (err) -+ printk(KERN_INFO "ifxmips_wdt: error creating device\n"); -+ else -+ printk(KERN_INFO "ifxmips_wdt: loaded\n"); -+ return err; -+} -+ -+static int ifxmips_wdt_remove(struct platform_device *dev) -+{ -+ ifxmips_wdt_disable(); -+ misc_deregister(&ifxmips_wdt_miscdev); -+ return 0; -+} -+ -+ -+static struct platform_driver ifxmips_wdt_driver = { -+ .probe = ifxmips_wdt_probe, -+ .remove = ifxmips_wdt_remove, -+ .driver = { -+ .name = "ifxmips_wdt", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init init_ifxmips_wdt(void) -+{ -+ int ret = platform_driver_register(&ifxmips_wdt_driver); -+ if (ret) -+ printk(KERN_INFO "ifxmips_wdt: error registering platfom driver!"); -+ return ret; -+} -+ -+static void __exit exit_ifxmips_wdt(void) -+{ -+ platform_driver_unregister(&ifxmips_wdt_driver); -+} -+ -+module_init(init_ifxmips_wdt); -+module_exit(exit_ifxmips_wdt); -+ -+MODULE_AUTHOR("John Crispin "); -+MODULE_DESCRIPTION("ifxmips Watchdog"); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); diff --git a/target/linux/ifxmips/patches-2.6.30/160-led.patch b/target/linux/ifxmips/patches-2.6.30/160-led.patch deleted file mode 100644 index 3d4c997454..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/160-led.patch +++ /dev/null @@ -1,230 +0,0 @@ -Index: linux-2.6.30.8/drivers/leds/Kconfig -=================================================================== ---- linux-2.6.30.8.orig/drivers/leds/Kconfig 2009-10-19 21:31:31.000000000 +0200 -+++ linux-2.6.30.8/drivers/leds/Kconfig 2009-10-19 21:31:32.000000000 +0200 -@@ -227,6 +227,12 @@ - This option enables support for BD2802GU RGB LED driver chips - accessed via the I2C bus. - -+config LEDS_IFXMIPS -+ tristate "LED Support for IFXMIPS LEDs" -+ depends on LEDS_CLASS && IFXMIPS -+ help -+ This option enables support for the CM-X270 LEDs. -+ - comment "LED Triggers" - - config LEDS_TRIGGERS -Index: linux-2.6.30.8/drivers/leds/Makefile -=================================================================== ---- linux-2.6.30.8.orig/drivers/leds/Makefile 2009-10-19 21:31:31.000000000 +0200 -+++ linux-2.6.30.8/drivers/leds/Makefile 2009-10-19 21:31:32.000000000 +0200 -@@ -27,6 +27,7 @@ - obj-$(CONFIG_LEDS_DA903X) += leds-da903x.o - obj-$(CONFIG_LEDS_WM8350) += leds-wm8350.o - obj-$(CONFIG_LEDS_PWM) += leds-pwm.o -+obj-$(CONFIG_LEDS_IFXMIPS) += leds-ifxmips.o - - # LED SPI Drivers - obj-$(CONFIG_LEDS_DAC124S085) += leds-dac124s085.o -Index: linux-2.6.30.8/drivers/leds/leds-ifxmips.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.30.8/drivers/leds/leds-ifxmips.c 2009-10-19 21:39:59.000000000 +0200 -@@ -0,0 +1,196 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2006 infineon -+ * Copyright (C) 2007 John Crispin -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#define DRVNAME "ifxmips_led" -+ -+/* might need to be changed depending on shift register used on the pcb */ -+#if 1 -+#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_FALLING -+#else -+#define IFXMIPS_LED_CLK_EDGE IFXMIPS_LED_RISING -+#endif -+ -+#define IFXMIPS_LED_SPEED IFXMIPS_LED_8HZ -+ -+#define IFXMIPS_LED_GPIO_PORT 0 -+ -+#define IFXMIPS_MAX_LED 24 -+ -+struct ifxmips_led { -+ struct led_classdev cdev; -+ u8 bit; -+}; -+ -+void ifxmips_led_set(unsigned int led) -+{ -+ led &= 0xffffff; -+ ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) | led, IFXMIPS_LED_CPU0); -+} -+EXPORT_SYMBOL(ifxmips_led_set); -+ -+void ifxmips_led_clear(unsigned int led) -+{ -+ led = ~(led & 0xffffff); -+ ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CPU0) & led, IFXMIPS_LED_CPU0); -+} -+EXPORT_SYMBOL(ifxmips_led_clear); -+ -+void ifxmips_led_blink_set(unsigned int led) -+{ -+ led &= 0xffffff; -+ ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | led, IFXMIPS_LED_CON0); -+} -+EXPORT_SYMBOL(ifxmips_led_blink_set); -+ -+void ifxmips_led_blink_clear(unsigned int led) -+{ -+ led = ~(led & 0xffffff); -+ ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & led, IFXMIPS_LED_CON0); -+} -+EXPORT_SYMBOL(ifxmips_led_blink_clear); -+ -+static void ifxmips_ledapi_set(struct led_classdev *led_cdev, -+ enum led_brightness value) -+{ -+ struct ifxmips_led *led_dev = -+ container_of(led_cdev, struct ifxmips_led, cdev); -+ -+ if (value) -+ ifxmips_led_set(1 << led_dev->bit); -+ else -+ ifxmips_led_clear(1 << led_dev->bit); -+} -+ -+void ifxmips_led_setup_gpio(void) -+{ -+ int i = 0; -+ -+ /* leds are controlled via a shift register -+ we need to setup pins SH,D,ST (4,5,6) to make it work */ -+ for (i = 4; i < 7; i++) { -+ ifxmips_port_set_altsel0(IFXMIPS_LED_GPIO_PORT, i); -+ ifxmips_port_clear_altsel1(IFXMIPS_LED_GPIO_PORT, i); -+ ifxmips_port_set_dir_out(IFXMIPS_LED_GPIO_PORT, i); -+ ifxmips_port_set_open_drain(IFXMIPS_LED_GPIO_PORT, i); -+ } -+} -+ -+static int ifxmips_led_probe(struct platform_device *dev) -+{ -+ int i = 0; -+ -+ ifxmips_led_setup_gpio(); -+ -+ ifxmips_w32(0, IFXMIPS_LED_AR); -+ ifxmips_w32(0, IFXMIPS_LED_CPU0); -+ ifxmips_w32(0, IFXMIPS_LED_CPU1); -+ ifxmips_w32(LED_CON0_SWU, IFXMIPS_LED_CON0); -+ ifxmips_w32(0, IFXMIPS_LED_CON1); -+ -+ /* setup the clock edge that the shift register is triggered on */ -+ ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) & ~IFXMIPS_LED_EDGE_MASK, -+ IFXMIPS_LED_CON0); -+ ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_CLK_EDGE, -+ IFXMIPS_LED_CON0); -+ -+ /* per default leds 15-0 are set */ -+ ifxmips_w32(IFXMIPS_LED_GROUP1 | IFXMIPS_LED_GROUP0, IFXMIPS_LED_CON1); -+ -+ /* leds are update periodically by the FPID */ -+ ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_UPD_MASK, -+ IFXMIPS_LED_CON1); -+ ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_UPD_SRC_FPI, -+ IFXMIPS_LED_CON1); -+ -+ /* set led update speed */ -+ ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) & ~IFXMIPS_LED_MASK, -+ IFXMIPS_LED_CON1); -+ ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON1) | IFXMIPS_LED_SPEED, -+ IFXMIPS_LED_CON1); -+ -+ /* adsl 0 and 1 leds are updated by the arc */ -+ ifxmips_w32(ifxmips_r32(IFXMIPS_LED_CON0) | IFXMIPS_LED_ADSL_SRC, -+ IFXMIPS_LED_CON0); -+ -+ /* per default, the leds are turned on */ -+ ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_LED); -+ -+ for (i = 0; i < IFXMIPS_MAX_LED; i++) { -+ struct ifxmips_led *tmp = -+ kzalloc(sizeof(struct ifxmips_led), GFP_KERNEL); -+ tmp->cdev.brightness_set = ifxmips_ledapi_set; -+ tmp->cdev.name = kmalloc(sizeof("ifxmips:led:00"), GFP_KERNEL); -+ sprintf((char *)tmp->cdev.name, "ifxmips:led:%02d", i); -+ tmp->cdev.default_trigger = NULL; -+ tmp->bit = i; -+ led_classdev_register(&dev->dev, &tmp->cdev); -+ } -+ -+ return 0; -+} -+ -+static int ifxmips_led_remove(struct platform_device *pdev) -+{ -+ return 0; -+} -+ -+static struct platform_driver ifxmips_led_driver = { -+ .probe = ifxmips_led_probe, -+ .remove = ifxmips_led_remove, -+ .driver = { -+ .name = DRVNAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int __init ifxmips_led_init(void) -+{ -+ int ret = platform_driver_register(&ifxmips_led_driver); -+ if (ret) -+ printk(KERN_INFO -+ "ifxmips_led: Error registering platfom driver!"); -+ -+ return ret; -+} -+ -+void __exit ifxmips_led_exit(void) -+{ -+ platform_driver_unregister(&ifxmips_led_driver); -+} -+ -+module_init(ifxmips_led_init); -+module_exit(ifxmips_led_exit); diff --git a/target/linux/ifxmips/patches-2.6.30/200-genirq_fix.patch b/target/linux/ifxmips/patches-2.6.30/200-genirq_fix.patch deleted file mode 100644 index 1fbd4c86e0..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/200-genirq_fix.patch +++ /dev/null @@ -1,14 +0,0 @@ -Index: linux-2.6.30.5/kernel/irq/chip.c -=================================================================== ---- linux-2.6.30.5.orig/kernel/irq/chip.c 2009-09-02 20:09:15.000000000 +0200 -+++ linux-2.6.30.5/kernel/irq/chip.c 2009-09-02 20:09:25.000000000 +0200 -@@ -537,6 +537,9 @@ - - kstat_incr_irqs_this_cpu(irq, desc); - -+ if (unlikely(!desc->action || (desc->status & IRQ_DISABLED))) -+ return; -+ - if (desc->chip->ack) - desc->chip->ack(irq); - diff --git a/target/linux/ifxmips/patches-2.6.30/300-cfi0001-swap.patch b/target/linux/ifxmips/patches-2.6.30/300-cfi0001-swap.patch deleted file mode 100644 index 1a546a80b5..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/300-cfi0001-swap.patch +++ /dev/null @@ -1,25 +0,0 @@ ---- linux-2.6.30.5.orig/drivers/mtd/chips/cfi_cmdset_0001.c 2009-08-17 00:19:38.000000000 +0300 -+++ linux-2.6.30.5/drivers/mtd/chips/cfi_cmdset_0001.c 2010-03-16 18:04:09.000000000 +0200 -@@ -41,7 +41,11 @@ - /* #define CMDSET0001_DISABLE_WRITE_SUSPEND */ - - // debugging, turns off buffer write mode if set to 1 --#define FORCE_WORD_WRITE 0 -+#ifdef CONFIG_IFXMIPS -+# define FORCE_WORD_WRITE 1 -+#else -+# define FORCE_WORD_WRITE 0 -+#endif - - #define MANUFACTURER_INTEL 0x0089 - #define I82802AB 0x00ad -@@ -1462,6 +1466,9 @@ - int ret=0; - - adr += chip->start; -+#ifdef CONFIG_IFXMIPS -+ adr ^= 2; -+#endif - - switch (mode) { - case FL_WRITING: diff --git a/target/linux/ifxmips/patches-2.6.30/310-cfi0002-swap.patch b/target/linux/ifxmips/patches-2.6.30/310-cfi0002-swap.patch deleted file mode 100644 index 6584e1f2ca..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/310-cfi0002-swap.patch +++ /dev/null @@ -1,15 +0,0 @@ -Index: linux-2.6.30.5/drivers/mtd/chips/cfi_cmdset_0002.c -=================================================================== ---- linux-2.6.30.5.orig/drivers/mtd/chips/cfi_cmdset_0002.c 2009-09-02 18:22:49.000000000 +0200 -+++ linux-2.6.30.5/drivers/mtd/chips/cfi_cmdset_0002.c 2009-09-02 18:31:31.000000000 +0200 -@@ -1118,7 +1118,9 @@ - int retry_cnt = 0; - - adr += chip->start; -- -+#ifdef CONFIG_IFXMIPS -+ adr ^= 2; -+#endif - spin_lock(chip->mutex); - ret = get_chip(map, chip, adr, FL_WRITING); - if (ret) { diff --git a/target/linux/ifxmips/patches-2.6.30/400-atm_hack.patch b/target/linux/ifxmips/patches-2.6.30/400-atm_hack.patch deleted file mode 100644 index c14d1399db..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/400-atm_hack.patch +++ /dev/null @@ -1,48 +0,0 @@ -Index: linux-2.6.30.9/arch/mips/mm/cache.c -=================================================================== ---- linux-2.6.30.9.orig/arch/mips/mm/cache.c 2009-11-01 16:10:29.000000000 +0100 -+++ linux-2.6.30.9/arch/mips/mm/cache.c 2009-11-01 16:11:56.000000000 +0100 -@@ -52,6 +52,8 @@ - void (*_dma_cache_inv)(unsigned long start, unsigned long size); - - EXPORT_SYMBOL(_dma_cache_wback_inv); -+EXPORT_SYMBOL(_dma_cache_wback); -+EXPORT_SYMBOL(_dma_cache_inv); - - #endif /* CONFIG_DMA_NONCOHERENT */ - -Index: linux-2.6.30.9/net/atm/proc.c -=================================================================== ---- linux-2.6.30.9.orig/net/atm/proc.c 2009-11-01 16:34:42.000000000 +0100 -+++ linux-2.6.30.9/net/atm/proc.c 2009-11-01 16:35:59.000000000 +0100 -@@ -151,7 +151,7 @@ - - static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) - { -- static const char *class_name[] = { "off","UBR","CBR","VBR","ABR" }; -+ static const char *class_name[] = { "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR" }; - static const char *aal_name[] = { - "---", "1", "2", "3/4", /* 0- 3 */ - "???", "5", "???", "???", /* 4- 7 */ -Index: linux-2.6.30.9/net/atm/common.c -=================================================================== ---- linux-2.6.30.9.orig/net/atm/common.c 2009-11-01 16:38:12.000000000 +0100 -+++ linux-2.6.30.9/net/atm/common.c 2009-11-01 16:47:06.000000000 +0100 -@@ -56,12 +56,17 @@ - write_unlock_irq(&vcc_sklist_lock); - } - -+struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL; -+EXPORT_SYMBOL(ifx_atm_alloc_tx); - - static struct sk_buff *alloc_tx(struct atm_vcc *vcc,unsigned int size) - { - struct sk_buff *skb; - struct sock *sk = sk_atm(vcc); - -+ if (ifx_atm_alloc_tx != NULL) -+ return ifx_atm_alloc_tx(vcc, size); -+ - if (atomic_read(&sk->sk_wmem_alloc) && !atm_may_send(vcc, size)) { - pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n", - atomic_read(&sk->sk_wmem_alloc), size, diff --git a/target/linux/ifxmips/patches-2.6.30/500-arv452.patch b/target/linux/ifxmips/patches-2.6.30/500-arv452.patch deleted file mode 100644 index 3ceeb2ca5e..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/500-arv452.patch +++ /dev/null @@ -1,79 +0,0 @@ -Index: linux-2.6.30.10/arch/mips/ifxmips/board.c -=================================================================== ---- linux-2.6.30.10.orig/arch/mips/ifxmips/board.c 2010-03-24 16:45:31.000000000 +0100 -+++ linux-2.6.30.10/arch/mips/ifxmips/board.c 2010-03-24 17:16:53.000000000 +0100 -@@ -52,6 +52,7 @@ - EASY50712, - EASY4010, - ARV4519, -+ ARV452, - }; - - extern int ifxmips_pci_external_clock; -@@ -141,6 +142,15 @@ - { .name = "ifx:green:usb", .gpio = 19, .active_low = 1, }, - }; - -+static struct gpio_led arv452_gpio_leds[] = { -+ { .name = "ifx:blue:power", .gpio = 3, .active_low = 1, }, -+ { .name = "ifx:blue:adsl", .gpio = 4, .active_low = 1, }, -+ { .name = "ifx:pink:internet", .gpio = 5, .active_low = 1, }, -+ { .name = "ifx:red:power", .gpio = 6, .active_low = 1, }, -+ { .name = "ifx:yello:wps", .gpio = 7, .active_low = 1, }, -+ { .name = "ifx:red:wps", .gpio = 9, .active_low = 1, }, -+}; -+ - static struct gpio_led_platform_data ifxmips_gpio_led_data; - - static struct platform_device ifxmips_gpio_leds = { -@@ -192,6 +202,14 @@ - #endif - }; - -+struct platform_device *arv452_devs[] = { -+ &ifxmips_gpio, &ifxmips_mii, &ifxmips_mtd, -+ &ifxmips_gpio_dev, &ifxmips_wdt, &dwc_usb, -+#ifdef CONFIG_LEDS_GPIO -+ &ifxmips_gpio_leds, -+#endif -+}; -+ - static struct gpio_led easy50712_leds[] = { - { .name = "ifx:green:test0", .gpio = 0,}, - { .name = "ifx:green:test1", .gpio = 1,}, -@@ -237,7 +255,20 @@ - .devs = arv5419_devs, - .reset_resource = {.name = "reset", .start = 1, .end = 14}, - .pci_external_clock = 1, -+#ifdef CONFIG_LEDS_GPIO - .gpio_leds = arv4519_gpio_leds, -+#endif -+ }, { -+ /* arcaydian annex-b board used by airties, arcor */ -+ .type = ARV452, -+ .name = "ARV452", -+ .system_type = SYSTEM_DANUBE_CHIPID2, -+ .devs = arv452_devs, -+ .reset_resource = {.name = "reset", .start = 1, .end = 14}, -+ .pci_external_clock = 1, -+#ifdef CONFIG_LEDS_GPIO -+ .gpio_leds = arv452_gpio_leds, -+#endif - }, - }; - -@@ -382,6 +413,14 @@ - ifxmips_gpio_led_data.num_leds = ARRAY_SIZE(arv4519_gpio_leds); - #endif - break; -+ case ARV452: -+ /* set some sane defaults for the gpios */ -+ board->num_devs = ARRAY_SIZE(arv452_devs); -+ ifxmips_w32(0x8001e7ff, IFXMIPS_EBU_BUSCON1); -+#ifdef CONFIG_LEDS_GPIO -+ ifxmips_gpio_led_data.num_leds = ARRAY_SIZE(arv452_gpio_leds); -+#endif -+ break; - } - #ifdef CONFIG_LEDS_GPIO - ifxmips_gpio_led_data.leds = board->gpio_leds; diff --git a/target/linux/ifxmips/patches-2.6.30/600-ebu-gpio.patch b/target/linux/ifxmips/patches-2.6.30/600-ebu-gpio.patch deleted file mode 100644 index 01e428a183..0000000000 --- a/target/linux/ifxmips/patches-2.6.30/600-ebu-gpio.patch +++ /dev/null @@ -1,196 +0,0 @@ -Index: linux-2.6.30.10/drivers/gpio/Kconfig -=================================================================== ---- linux-2.6.30.10.orig/drivers/gpio/Kconfig 2010-03-24 21:55:56.000000000 +0100 -+++ linux-2.6.30.10/drivers/gpio/Kconfig 2010-03-24 21:56:36.000000000 +0100 -@@ -176,4 +176,12 @@ - SPI driver for Microchip MCP23S08 I/O expander. This provides - a GPIO interface supporting inputs and outputs. - -+comment "EBU GPIO expanders:" -+ -+config GPIO_IFXMIPS_EBU -+ boolean "IFXMIPS EBU attached I/O expander" -+ depends on IFXMIPS -+ help -+ This driver allows you to drive latches attached to the SoCc External Bus Unit -+ - endif -Index: linux-2.6.30.10/drivers/gpio/Makefile -=================================================================== ---- linux-2.6.30.10.orig/drivers/gpio/Makefile 2010-03-24 21:55:56.000000000 +0100 -+++ linux-2.6.30.10/drivers/gpio/Makefile 2010-03-24 21:56:36.000000000 +0100 -@@ -12,3 +12,4 @@ - obj-$(CONFIG_GPIO_TWL4030) += twl4030-gpio.o - obj-$(CONFIG_GPIO_XILINX) += xilinx_gpio.o - obj-$(CONFIG_GPIO_BT8XX) += bt8xxgpio.o -+obj-$(CONFIG_GPIO_IFXMIPS_EBU) += ifxmips_ebu_gpio.o -Index: linux-2.6.30.10/arch/mips/ifxmips/board.c -=================================================================== ---- linux-2.6.30.10.orig/arch/mips/ifxmips/board.c 2010-03-25 10:43:06.000000000 +0100 -+++ linux-2.6.30.10/arch/mips/ifxmips/board.c 2010-03-25 12:40:54.000000000 +0100 -@@ -111,6 +111,11 @@ - .name = "ifxmips_wdt", - }; - -+static struct platform_device ifxmips_ebu = { -+ .id = 0, -+ .name = "ifxmips_ebu", -+}; -+ - static struct resource ifxmips_mtd_resource = { - .start = IFXMIPS_FLASH_START, - .end = IFXMIPS_FLASH_START + IFXMIPS_FLASH_MAX - 1, -@@ -145,10 +150,18 @@ - static struct gpio_led arv452_gpio_leds[] = { - { .name = "ifx:blue:power", .gpio = 3, .active_low = 1, }, - { .name = "ifx:blue:adsl", .gpio = 4, .active_low = 1, }, -- { .name = "ifx:pink:internet", .gpio = 5, .active_low = 1, }, -+ { .name = "ifx:blue:internet", .gpio = 5, .active_low = 1, }, - { .name = "ifx:red:power", .gpio = 6, .active_low = 1, }, - { .name = "ifx:yello:wps", .gpio = 7, .active_low = 1, }, - { .name = "ifx:red:wps", .gpio = 9, .active_low = 1, }, -+ { .name = "ifx:blue:voip", .gpio = 32, .active_low = 1, }, -+ { .name = "ifx:blue:fxs1", .gpio = 33, .active_low = 1, }, -+ { .name = "ifx:blue:fxs2", .gpio = 34, .active_low = 1, }, -+ { .name = "ifx:blue:fxo", .gpio = 35, .active_low = 1, }, -+ { .name = "ifx:blue:voice", .gpio = 36, .active_low = 1, }, -+ { .name = "ifx:blue:usb", .gpio = 37, .active_low = 1, }, -+ { .name = "ifx:blue:wlan", .gpio = 38, .active_low = 1, }, -+ { .name = "ifx:red:internet", .gpio = 41, .active_low = 1, }, - }; - - static struct gpio_led_platform_data ifxmips_gpio_led_data; -@@ -205,6 +218,7 @@ - struct platform_device *arv452_devs[] = { - &ifxmips_gpio, &ifxmips_mii, &ifxmips_mtd, - &ifxmips_gpio_dev, &ifxmips_wdt, &dwc_usb, -+ &ifxmips_ebu, - #ifdef CONFIG_LEDS_GPIO - &ifxmips_gpio_leds, - #endif -Index: linux-2.6.30.10/drivers/gpio/ifxmips_ebu_gpio.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-2.6.30.10/drivers/gpio/ifxmips_ebu_gpio.c 2010-03-25 12:47:07.000000000 +0100 -@@ -0,0 +1,121 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2010 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define IFXMIPS_EBU_START 0x14000000 -+#define IFXMIPS_EBU_MAX 0x00001000 -+#define IFXMIPS_EBU_BUSCON 0x1e7ff -+#define IFXMIPS_EBU_WP 0x80000000 -+ -+static int shadow = (1 << 10) | (1 << 8); -+static void __iomem *virt; -+ -+static int -+ifxmips_ebu_direction_input(struct gpio_chip *chip, unsigned offset) -+{ -+ return -EINVAL; -+} -+ -+static int -+ifxmips_ebu_direction_output(struct gpio_chip *chip, unsigned offset, int value) -+{ -+ return 0; -+} -+ -+static int -+ifxmips_ebu_get(struct gpio_chip *chip, unsigned offset) -+{ -+ return -EINVAL; -+} -+ -+static void -+ifxmips_ebu_set(struct gpio_chip *chip, unsigned offset, int value) -+{ -+ if(value) -+ shadow |= (1 << offset); -+ else -+ shadow &= ~(1 << offset); -+ ifxmips_w32(IFXMIPS_EBU_BUSCON, IFXMIPS_EBU_BUSCON1); -+ *((__u16*)virt) = shadow; -+ ifxmips_w32(IFXMIPS_EBU_BUSCON | IFXMIPS_EBU_WP, IFXMIPS_EBU_BUSCON1); -+} -+ -+static struct gpio_chip -+ifxmips_ebu_chip = -+{ -+ .label = "ifxmips_ebu", -+ .direction_input = ifxmips_ebu_direction_input, -+ .direction_output = ifxmips_ebu_direction_output, -+ .set = ifxmips_ebu_set, -+ .get = ifxmips_ebu_get, -+ .base = 32, -+ .ngpio = 16, -+ .can_sleep = 1, -+ .owner = THIS_MODULE, -+}; -+ -+static int __devinit -+ifxmips_ebu_probe(struct platform_device *dev) -+{ -+ ifxmips_w32(IFXMIPS_EBU_START | 0x1, IFXMIPS_EBU_ADDRSEL1); -+ ifxmips_w32(IFXMIPS_EBU_BUSCON | IFXMIPS_EBU_WP, IFXMIPS_EBU_BUSCON1); -+ virt = ioremap_nocache(IFXMIPS_EBU_START, IFXMIPS_EBU_MAX); -+ if(gpiochip_add(&ifxmips_ebu_chip)) -+ return -EINVAL; -+ return 0; -+} -+ -+static int -+ifxmips_ebu_remove(struct platform_device *dev) -+{ -+ return gpiochip_remove(&ifxmips_ebu_chip); -+} -+ -+static struct platform_driver -+ifxmips_ebu_driver = { -+ .probe = ifxmips_ebu_probe, -+ .remove = ifxmips_ebu_remove, -+ .driver = { -+ .name = "ifxmips_ebu", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init -+ifxmips_ebu_init(void) -+{ -+ return platform_driver_register(&ifxmips_ebu_driver); -+} -+ -+static void __exit -+ifxmips_ebu_exit(void) -+{ -+ platform_driver_unregister(&ifxmips_ebu_driver); -+} -+ -+module_init(ifxmips_ebu_init); -+module_exit(ifxmips_ebu_exit); -+ -+MODULE_AUTHOR("John Crispin "); -+MODULE_LICENSE("GPL v2"); -+MODULE_DESCRIPTION("ifxmips - EBU Latch GPIO-Expander"); diff --git a/target/linux/ifxmips/profiles/000-None.mk b/target/linux/ifxmips/profiles/000-None.mk deleted file mode 100644 index 95b04eed9d..0000000000 --- a/target/linux/ifxmips/profiles/000-None.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (C) 2006-2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/None - NAME:=Generic, No WiFi - PACKAGES:=-wpad-mini -endef - -define Profile/None/Description - Package set without WiFi support -endef -$(eval $(call Profile,None)) - diff --git a/target/linux/ifxmips/profiles/100-Atheros.mk b/target/linux/ifxmips/profiles/100-Atheros.mk deleted file mode 100644 index 71804b294f..0000000000 --- a/target/linux/ifxmips/profiles/100-Atheros.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (C) 2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Atheros - NAME:=Atheros WiFi (default) - PACKAGES:=kmod-madwifi -endef - -define Profile/Atheros/Description - Package set compatible with hardware using Atheros WiFi cards -endef -$(eval $(call Profile,Atheros)) - diff --git a/target/linux/ifxmips/profiles/200-Ralink.mk b/target/linux/ifxmips/profiles/200-Ralink.mk deleted file mode 100644 index dd9716ab59..0000000000 --- a/target/linux/ifxmips/profiles/200-Ralink.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (C) 2008 OpenWrt.org -# -# This is free software, licensed under the GNU General Public License v2. -# See /LICENSE for more information. -# - -define Profile/Ralink - NAME:=Ralink RT61 Wifi (ARV452) - PACKAGES:=kmod-rt61-pci -endef - -define Profile/Ralink/Description - Package set compatible with hardware using Ralink WiFi cards -endef -$(eval $(call Profile,Ralink)) - -- 2.30.2