From fb0c3eb5a31b891d3462311e42f5ec72b78395e8 Mon Sep 17 00:00:00 2001 From: Koen Vandeputte Date: Wed, 18 Sep 2019 12:49:31 +0200 Subject: [PATCH] kernel: bump 4.14 to 4.14.144 Refreshed all patches. Altered patches: - 816-pcie-support-layerscape.patch Fixes: -CVE-2019-15030 Compile-tested on: cns3xxx, layerscape Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte --- include/kernel-version.mk | 4 +- ...otentially-missed-IRQ-handling-durin.patch | 7 +- ...PS-ath79-add-support-for-QCA953x-SoC.patch | 8 +- ...PS-ath79-add-support-for-QCA956x-SoC.patch | 6 +- ...0-MIPS-ath79-fix-chained-irq-disable.patch | 10 +- .../952-qca955x-enable-ddr-wb-flush.patch | 4 +- .../generic/hack-4.14/204-module_strip.patch | 4 +- .../816-pcie-support-layerscape.patch | 238 ++++++------------ 8 files changed, 99 insertions(+), 182 deletions(-) diff --git a/include/kernel-version.mk b/include/kernel-version.mk index af57ad6ae1..c46ff6d61c 100644 --- a/include/kernel-version.mk +++ b/include/kernel-version.mk @@ -7,11 +7,11 @@ ifdef CONFIG_TESTING_KERNEL endif LINUX_VERSION-4.9 = .193 -LINUX_VERSION-4.14 = .143 +LINUX_VERSION-4.14 = .144 LINUX_VERSION-4.19 = .72 LINUX_KERNEL_HASH-4.9.193 = 9be5081cc0fa6b720e6b3e5cb90296f3d857469bb3cda09ff93db00f9e16fd01 -LINUX_KERNEL_HASH-4.14.143 = 2534f2f03cb937700a03dd85dcf1cb6e6f46fdd29d489580cc3183d6c0643d93 +LINUX_KERNEL_HASH-4.14.144 = cb8b84675ba060b249ffa62de2366d16e842e3edfcb355ebbfb06bf3de03ca54 LINUX_KERNEL_HASH-4.19.72 = f9fcb6b3bd29115ac55fc154e300c3dce2044502732f6842ad6c25e6f9f51f6d remove_uri_prefix=$(subst git://,,$(subst http://,,$(subst https://,,$(1)))) diff --git a/target/linux/ar71xx/patches-4.14/343-MIPS-ath79-Fix-potentially-missed-IRQ-handling-durin.patch b/target/linux/ar71xx/patches-4.14/343-MIPS-ath79-Fix-potentially-missed-IRQ-handling-durin.patch index b1389bc28d..05a1d7ef0c 100644 --- a/target/linux/ar71xx/patches-4.14/343-MIPS-ath79-Fix-potentially-missed-IRQ-handling-durin.patch +++ b/target/linux/ar71xx/patches-4.14/343-MIPS-ath79-Fix-potentially-missed-IRQ-handling-durin.patch @@ -23,11 +23,9 @@ CC: stable@vger.kernel.org # v3.2+ arch/mips/ath79/irq.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) -diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c -index 2dfff1f19004..a03a6bcaf6fd 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c -@@ -32,15 +32,21 @@ static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) +@@ -32,15 +32,21 @@ static void ar934x_ip2_irq_dispatch(stru u32 status; status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS); @@ -52,6 +50,3 @@ index 2dfff1f19004..a03a6bcaf6fd 100644 } } --- -2.17.1 - diff --git a/target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch index 4381cb8faf..722d127ec5 100644 --- a/target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch +++ b/target/linux/ar71xx/patches-4.14/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch @@ -307,7 +307,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. return; --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c -@@ -56,6 +56,34 @@ static void ar934x_ip2_irq_init(void) +@@ -62,6 +62,34 @@ static void ar934x_ip2_irq_init(void) irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); } @@ -342,7 +342,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. static void qca955x_ip2_irq_dispatch(struct irq_desc *desc) { u32 status; -@@ -143,7 +171,7 @@ void __init arch_init_irq(void) +@@ -149,7 +177,7 @@ void __init arch_init_irq(void) soc_is_ar913x() || soc_is_ar933x()) { irq_wb_chan2 = 3; irq_wb_chan3 = 2; @@ -351,7 +351,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. irq_wb_chan3 = 2; } -@@ -154,6 +182,7 @@ void __init arch_init_irq(void) +@@ -160,6 +188,7 @@ void __init arch_init_irq(void) else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x() || @@ -359,7 +359,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed. soc_is_qca955x()) misc_is_ar71xx = false; else -@@ -164,6 +193,8 @@ void __init arch_init_irq(void) +@@ -170,6 +199,8 @@ void __init arch_init_irq(void) if (soc_is_ar934x()) ar934x_ip2_irq_init(); diff --git a/target/linux/ar71xx/patches-4.14/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.14/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch index 3d79463545..670f7bef0a 100644 --- a/target/linux/ar71xx/patches-4.14/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch +++ b/target/linux/ar71xx/patches-4.14/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch @@ -291,7 +291,7 @@ return; --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c -@@ -156,6 +156,87 @@ static void qca955x_irq_init(void) +@@ -162,6 +162,87 @@ static void qca955x_irq_init(void) irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); } @@ -379,7 +379,7 @@ void __init arch_init_irq(void) { unsigned irq_wb_chan2 = -1; -@@ -183,7 +264,9 @@ void __init arch_init_irq(void) +@@ -189,7 +270,9 @@ void __init arch_init_irq(void) soc_is_ar933x() || soc_is_ar934x() || soc_is_qca953x() || @@ -390,7 +390,7 @@ misc_is_ar71xx = false; else BUG(); -@@ -197,4 +280,6 @@ void __init arch_init_irq(void) +@@ -203,4 +286,6 @@ void __init arch_init_irq(void) qca953x_irq_init(); else if (soc_is_qca955x()) qca955x_irq_init(); diff --git a/target/linux/ar71xx/patches-4.14/630-MIPS-ath79-fix-chained-irq-disable.patch b/target/linux/ar71xx/patches-4.14/630-MIPS-ath79-fix-chained-irq-disable.patch index 2b92b88d03..a74eb4f43e 100644 --- a/target/linux/ar71xx/patches-4.14/630-MIPS-ath79-fix-chained-irq-disable.patch +++ b/target/linux/ar71xx/patches-4.14/630-MIPS-ath79-fix-chained-irq-disable.patch @@ -10,7 +10,7 @@ static void ar934x_ip2_irq_dispatch(struct irq_desc *desc) { u32 status; -@@ -50,8 +53,7 @@ static void ar934x_ip2_irq_init(void) +@@ -56,8 +59,7 @@ static void ar934x_ip2_irq_init(void) for (i = ATH79_IP2_IRQ_BASE; i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) @@ -20,7 +20,7 @@ irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch); } -@@ -79,7 +81,7 @@ static void qca953x_irq_init(void) +@@ -85,7 +87,7 @@ static void qca953x_irq_init(void) for (i = ATH79_IP2_IRQ_BASE; i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) @@ -29,7 +29,7 @@ irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch); } -@@ -143,15 +145,13 @@ static void qca955x_irq_init(void) +@@ -149,15 +151,13 @@ static void qca955x_irq_init(void) for (i = ATH79_IP2_IRQ_BASE; i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) @@ -47,7 +47,7 @@ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch); } -@@ -222,13 +222,13 @@ static void qca956x_irq_init(void) +@@ -228,13 +228,13 @@ static void qca956x_irq_init(void) for (i = ATH79_IP2_IRQ_BASE; i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++) @@ -63,7 +63,7 @@ irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch); -@@ -237,12 +237,40 @@ static void qca956x_irq_init(void) +@@ -243,12 +243,40 @@ static void qca956x_irq_init(void) late_time_init = &qca956x_enable_timer_cb; } diff --git a/target/linux/ar71xx/patches-4.14/952-qca955x-enable-ddr-wb-flush.patch b/target/linux/ar71xx/patches-4.14/952-qca955x-enable-ddr-wb-flush.patch index ef22edb319..16d17b8a0e 100644 --- a/target/linux/ar71xx/patches-4.14/952-qca955x-enable-ddr-wb-flush.patch +++ b/target/linux/ar71xx/patches-4.14/952-qca955x-enable-ddr-wb-flush.patch @@ -11,7 +11,7 @@ ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c; --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c -@@ -99,12 +99,12 @@ static void qca955x_ip2_irq_dispatch(str +@@ -105,12 +105,12 @@ static void qca955x_ip2_irq_dispatch(str } if (status & QCA955X_EXT_INT_PCIE_RC1_ALL) { @@ -26,7 +26,7 @@ generic_handle_irq(ATH79_IP2_IRQ(1)); } } -@@ -124,17 +124,17 @@ static void qca955x_ip3_irq_dispatch(str +@@ -130,17 +130,17 @@ static void qca955x_ip3_irq_dispatch(str } if (status & QCA955X_EXT_INT_USB1) { diff --git a/target/linux/generic/hack-4.14/204-module_strip.patch b/target/linux/generic/hack-4.14/204-module_strip.patch index dce9c48473..d847adf054 100644 --- a/target/linux/generic/hack-4.14/204-module_strip.patch +++ b/target/linux/generic/hack-4.14/204-module_strip.patch @@ -114,7 +114,7 @@ Signed-off-by: Felix Fietkau config MODULES_TREE_LOOKUP --- a/kernel/module.c +++ b/kernel/module.c -@@ -3008,9 +3008,11 @@ static struct module *setup_load_info(st +@@ -3020,9 +3020,11 @@ static struct module *setup_load_info(st static int check_modinfo(struct module *mod, struct load_info *info, int flags) { @@ -127,7 +127,7 @@ Signed-off-by: Felix Fietkau if (flags & MODULE_INIT_IGNORE_VERMAGIC) modmagic = NULL; -@@ -3031,6 +3033,7 @@ static int check_modinfo(struct module * +@@ -3043,6 +3045,7 @@ static int check_modinfo(struct module * mod->name); add_taint_module(mod, TAINT_OOT_MODULE, LOCKDEP_STILL_OK); } diff --git a/target/linux/layerscape/patches-4.14/816-pcie-support-layerscape.patch b/target/linux/layerscape/patches-4.14/816-pcie-support-layerscape.patch index 588be3ce7c..88f38df746 100644 --- a/target/linux/layerscape/patches-4.14/816-pcie-support-layerscape.patch +++ b/target/linux/layerscape/patches-4.14/816-pcie-support-layerscape.patch @@ -830,7 +830,7 @@ Signed-off-by: Yangbo Lu obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c -@@ -338,15 +338,6 @@ static irqreturn_t dra7xx_pcie_irq_handl +@@ -339,15 +339,6 @@ static irqreturn_t dra7xx_pcie_irq_handl return IRQ_HANDLED; } @@ -1125,49 +1125,13 @@ Signed-off-by: Yangbo Lu struct pci_epf_header *hdr) { struct dw_pcie_ep *ep = epc_get_drvdata(epc); -@@ -74,8 +106,7 @@ static int dw_pcie_ep_inbound_atu(struct - u32 free_win; - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - -- free_win = find_first_zero_bit(&ep->ib_window_map, -- sizeof(ep->ib_window_map)); -+ free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows); - if (free_win >= ep->num_ib_windows) { - dev_err(pci->dev, "no free inbound window\n"); - return -EINVAL; -@@ -89,7 +120,7 @@ static int dw_pcie_ep_inbound_atu(struct - } - - ep->bar_to_atu[bar] = free_win; -- set_bit(free_win, &ep->ib_window_map); -+ set_bit(free_win, ep->ib_window_map); - - return 0; - } -@@ -100,8 +131,7 @@ static int dw_pcie_ep_outbound_atu(struc - u32 free_win; - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); - -- free_win = find_first_zero_bit(&ep->ob_window_map, -- sizeof(ep->ob_window_map)); -+ free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows); - if (free_win >= ep->num_ob_windows) { - dev_err(pci->dev, "no free outbound window\n"); - return -EINVAL; -@@ -110,30 +140,35 @@ static int dw_pcie_ep_outbound_atu(struc - dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM, - phys_addr, pci_addr, size); - -- set_bit(free_win, &ep->ob_window_map); -+ set_bit(free_win, ep->ob_window_map); - ep->outbound_addr[free_win] = phys_addr; - +@@ -114,24 +146,29 @@ static int dw_pcie_ep_outbound_atu(struc return 0; } -static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar) +static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no, -+ struct pci_epf_bar *epf_bar) ++ struct pci_epf_bar *epf_bar) { struct dw_pcie_ep *ep = epc_get_drvdata(epc); struct dw_pcie *pci = to_dw_pcie_from_ep(ep); @@ -1178,14 +1142,13 @@ Signed-off-by: Yangbo Lu + __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags); dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND); -- clear_bit(atu_index, &ep->ib_window_map); -+ clear_bit(atu_index, ep->ib_window_map); + clear_bit(atu_index, ep->ib_window_map); } -static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar, - dma_addr_t bar_phys, size_t size, int flags) +static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, -+ struct pci_epf_bar *epf_bar) ++ struct pci_epf_bar *epf_bar) { int ret; struct dw_pcie_ep *ep = epc_get_drvdata(epc); @@ -1196,7 +1159,7 @@ Signed-off-by: Yangbo Lu enum dw_pcie_as_type as_type; u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar); -@@ -142,13 +177,20 @@ static int dw_pcie_ep_set_bar(struct pci +@@ -140,13 +177,20 @@ static int dw_pcie_ep_set_bar(struct pci else as_type = DW_PCIE_AS_IO; @@ -1219,7 +1182,7 @@ Signed-off-by: Yangbo Lu dw_pcie_dbi_ro_wr_dis(pci); return 0; -@@ -169,7 +211,8 @@ static int dw_pcie_find_index(struct dw_ +@@ -167,7 +211,8 @@ static int dw_pcie_find_index(struct dw_ return -EINVAL; } @@ -1229,101 +1192,96 @@ Signed-off-by: Yangbo Lu { int ret; u32 atu_index; -@@ -181,10 +224,11 @@ static void dw_pcie_ep_unmap_addr(struct - return; - - dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND); -- clear_bit(atu_index, &ep->ob_window_map); -+ clear_bit(atu_index, ep->ob_window_map); +@@ -182,8 +227,9 @@ static void dw_pcie_ep_unmap_addr(struct + clear_bit(atu_index, ep->ob_window_map); } -static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr, +- u64 pci_addr, size_t size) +static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, -+ phys_addr_t addr, - u64 pci_addr, size_t size) ++ phys_addr_t addr, ++ u64 pci_addr, size_t size) { int ret; -@@ -200,45 +244,93 @@ static int dw_pcie_ep_map_addr(struct pc + struct dw_pcie_ep *ep = epc_get_drvdata(epc); +@@ -198,45 +244,93 @@ static int dw_pcie_ep_map_addr(struct pc return 0; } -static int dw_pcie_ep_get_msi(struct pci_epc *epc) +static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no) - { -- int val; - struct dw_pcie_ep *ep = epc_get_drvdata(epc); - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); ++{ ++ struct dw_pcie_ep *ep = epc_get_drvdata(epc); ++ struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + u32 val, reg; + + if (!ep->msi_cap) + return -EINVAL; - -- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); -- if (!(val & MSI_CAP_MSI_EN_MASK)) ++ + reg = ep->msi_cap + PCI_MSI_FLAGS; + val = dw_pcie_readw_dbi(pci, reg); + if (!(val & PCI_MSI_FLAGS_ENABLE)) - return -EINVAL; - -- val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT; ++ return -EINVAL; ++ + val = (val & PCI_MSI_FLAGS_QSIZE) >> 4; + - return val; - } - --static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int) ++ return val; ++} ++ +static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts) - { -- int val; - struct dw_pcie_ep *ep = epc_get_drvdata(epc); - struct dw_pcie *pci = to_dw_pcie_from_ep(ep); ++{ ++ struct dw_pcie_ep *ep = epc_get_drvdata(epc); ++ struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + u32 val, reg; + + if (!ep->msi_cap) + return -EINVAL; - -- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); -- val &= ~MSI_CAP_MMC_MASK; -- val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; ++ + reg = ep->msi_cap + PCI_MSI_FLAGS; + val = dw_pcie_readw_dbi(pci, reg); + val &= ~PCI_MSI_FLAGS_QMASK; + val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK; - dw_pcie_dbi_ro_wr_en(pci); -- dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); ++ dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_writew_dbi(pci, reg, val); - dw_pcie_dbi_ro_wr_dis(pci); - - return 0; - } - --static int dw_pcie_ep_raise_irq(struct pci_epc *epc, -- enum pci_epc_irq_type type, u8 interrupt_num) ++ dw_pcie_dbi_ro_wr_dis(pci); ++ ++ return 0; ++} ++ +static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no) -+{ -+ struct dw_pcie_ep *ep = epc_get_drvdata(epc); -+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + { +- int val; + struct dw_pcie_ep *ep = epc_get_drvdata(epc); + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + u32 val, reg; + + if (!ep->msix_cap) + return -EINVAL; -+ + +- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); +- if (!(val & MSI_CAP_MSI_EN_MASK)) + reg = ep->msix_cap + PCI_MSIX_FLAGS; + val = dw_pcie_readw_dbi(pci, reg); + if (!(val & PCI_MSIX_FLAGS_ENABLE)) -+ return -EINVAL; -+ + return -EINVAL; + +- val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT; + val &= PCI_MSIX_FLAGS_QSIZE; + -+ return val; -+} -+ + return val; + } + +-static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int) +static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts) -+{ -+ struct dw_pcie_ep *ep = epc_get_drvdata(epc); -+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + { +- int val; + struct dw_pcie_ep *ep = epc_get_drvdata(epc); + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + u32 val, reg; -+ + +- val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL); +- val &= ~MSI_CAP_MMC_MASK; +- val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK; + if (!ep->msix_cap) + return -EINVAL; + @@ -1331,13 +1289,16 @@ Signed-off-by: Yangbo Lu + val = dw_pcie_readw_dbi(pci, reg); + val &= ~PCI_MSIX_FLAGS_QSIZE; + val |= interrupts; -+ dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_dbi_ro_wr_en(pci); +- dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val); + dw_pcie_writew_dbi(pci, reg, val); -+ dw_pcie_dbi_ro_wr_dis(pci); -+ -+ return 0; -+} -+ + dw_pcie_dbi_ro_wr_dis(pci); + + return 0; + } + +-static int dw_pcie_ep_raise_irq(struct pci_epc *epc, +- enum pci_epc_irq_type type, u8 interrupt_num) +static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no, + enum pci_epc_irq_type type, u16 interrupt_num) { @@ -1351,7 +1312,7 @@ Signed-off-by: Yangbo Lu } static void dw_pcie_ep_stop(struct pci_epc *epc) -@@ -271,15 +363,130 @@ static const struct pci_epc_ops epc_ops +@@ -269,15 +363,130 @@ static const struct pci_epc_ops epc_ops .unmap_addr = dw_pcie_ep_unmap_addr, .set_msi = dw_pcie_ep_set_msi, .get_msi = dw_pcie_ep_get_msi, @@ -1482,7 +1443,7 @@ Signed-off-by: Yangbo Lu pci_epc_mem_exit(epc); } -@@ -293,7 +500,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e +@@ -291,7 +500,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e struct device_node *np = dev->of_node; if (!pci->dbi_base || !pci->dbi_base2) { @@ -1491,40 +1452,7 @@ Signed-off-by: Yangbo Lu return -EINVAL; } -@@ -302,12 +509,32 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e - dev_err(dev, "unable to read *num-ib-windows* property\n"); - return ret; - } -+ if (ep->num_ib_windows > MAX_IATU_IN) { -+ dev_err(dev, "invalid *num-ib-windows*\n"); -+ return -EINVAL; -+ } - - ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows); - if (ret < 0) { - dev_err(dev, "unable to read *num-ob-windows* property\n"); - return ret; - } -+ if (ep->num_ob_windows > MAX_IATU_OUT) { -+ dev_err(dev, "invalid *num-ob-windows*\n"); -+ return -EINVAL; -+ } -+ -+ ep->ib_window_map = devm_kzalloc(dev, sizeof(long) * -+ BITS_TO_LONGS(ep->num_ib_windows), -+ GFP_KERNEL); -+ if (!ep->ib_window_map) -+ return -ENOMEM; -+ -+ ep->ob_window_map = devm_kzalloc(dev, sizeof(long) * -+ BITS_TO_LONGS(ep->num_ob_windows), -+ GFP_KERNEL); -+ if (!ep->ob_window_map) -+ return -ENOMEM; - - addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows, - GFP_KERNEL); -@@ -315,15 +542,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e +@@ -333,15 +542,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e return -ENOMEM; ep->outbound_addr = addr; @@ -1546,7 +1474,7 @@ Signed-off-by: Yangbo Lu ret = of_property_read_u8(np, "max-functions", &epc->max_functions); if (ret < 0) epc->max_functions = 1; -@@ -335,8 +565,16 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e +@@ -353,8 +565,16 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e return ret; } @@ -1873,9 +1801,9 @@ Signed-off-by: Yangbo Lu /* * Maximum number of MSI IRQs can be 256 per controller. But keep * it 32 as of now. Probably we will never need more than 32. If needed, -@@ -114,6 +102,10 @@ - #define MAX_MSI_IRQS 32 - #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32) +@@ -118,6 +106,10 @@ + #define MAX_IATU_IN 256 + #define MAX_IATU_OUT 256 +/* Maximum number of inbound/outbound iATUs */ +#define MAX_IATU_IN 256 @@ -1884,7 +1812,7 @@ Signed-off-by: Yangbo Lu struct pcie_port; struct dw_pcie; struct dw_pcie_ep; -@@ -181,8 +173,8 @@ enum dw_pcie_as_type { +@@ -185,8 +177,8 @@ enum dw_pcie_as_type { struct dw_pcie_ep_ops { void (*ep_init)(struct dw_pcie_ep *ep); @@ -1895,24 +1823,18 @@ Signed-off-by: Yangbo Lu }; struct dw_pcie_ep { -@@ -193,10 +185,14 @@ struct dw_pcie_ep { - size_t page_size; - u8 bar_to_atu[6]; - phys_addr_t *outbound_addr; -- unsigned long ib_window_map; -- unsigned long ob_window_map; -+ unsigned long *ib_window_map; -+ unsigned long *ob_window_map; +@@ -201,6 +193,10 @@ struct dw_pcie_ep { + unsigned long *ob_window_map; u32 num_ib_windows; u32 num_ob_windows; -+ void __iomem *msi_mem; -+ phys_addr_t msi_mem_phys; -+ u8 msi_cap; /* MSI capability offset */ -+ u8 msix_cap; /* MSI-X capability offset */ ++ void __iomem *msi_mem; ++ phys_addr_t msi_mem_phys; ++ u8 msi_cap; /* MSI capability offset */ ++ u8 msix_cap; /* MSI-X capability offset */ }; struct dw_pcie_ops { -@@ -335,6 +331,12 @@ static inline int dw_pcie_host_init(stru +@@ -339,6 +335,12 @@ static inline int dw_pcie_host_init(stru void dw_pcie_ep_linkup(struct dw_pcie_ep *ep); int dw_pcie_ep_init(struct dw_pcie_ep *ep); void dw_pcie_ep_exit(struct dw_pcie_ep *ep); @@ -1925,7 +1847,7 @@ Signed-off-by: Yangbo Lu #else static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) { -@@ -348,5 +350,26 @@ static inline int dw_pcie_ep_init(struct +@@ -352,5 +354,26 @@ static inline int dw_pcie_ep_init(struct static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep) { } -- 2.30.2