52fb3bab0a5aa7398d1d3a675ca849cc6db21578
[openwrt/openwrt.git] / openwrt / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.17/arch/mips/aruba/Makefile linux-2.6.17-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.17/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.17-owrt/arch/mips/aruba/Makefile 2006-06-18 12:44:28.000000000 +0200
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/Makefile linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.17/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile 2006-06-18 12:44:28.000000000 +0200
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.c linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c 2006-06-18 12:44:28.000000000 +0200
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.h linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h 2006-06-18 12:44:28.000000000 +0200
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.17/arch/mips/aruba/prom.c linux-2.6.17-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.17/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.17-owrt/arch/mips/aruba/prom.c 2006-06-18 12:44:28.000000000 +0200
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.17/arch/mips/aruba/serial.c linux-2.6.17-owrt/arch/mips/aruba/serial.c
686 --- linux-2.6.17/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.17-owrt/arch/mips/aruba/serial.c 2006-06-18 12:44:28.000000000 +0200
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.17/arch/mips/aruba/setup.c linux-2.6.17-owrt/arch/mips/aruba/setup.c
784 --- linux-2.6.17/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.17-owrt/arch/mips/aruba/setup.c 2006-06-18 12:44:28.000000000 +0200
786 @@ -0,0 +1,134 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/module.h>
827 +#include <linux/mm.h>
828 +#include <linux/sched.h>
829 +#include <linux/irq.h>
830 +#include <asm/bootinfo.h>
831 +#include <asm/io.h>
832 +#include <linux/ioport.h>
833 +#include <asm/mipsregs.h>
834 +#include <asm/pgtable.h>
835 +#include <asm/reboot.h>
836 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
837 +#include <asm/idt-boards/rc32434/rc32434.h>
838 +#include <linux/pm.h>
839 +
840 +extern char *__init prom_getcmdline(void);
841 +
842 +extern void (*board_time_init) (void);
843 +extern void (*board_timer_setup) (struct irqaction * irq);
844 +extern void aruba_time_init(void);
845 +extern void aruba_timer_setup(struct irqaction *irq);
846 +extern void aruba_reset(void);
847 +
848 +#define epldMask ((volatile unsigned char *)0xB900000d)
849 +
850 +static void aruba_machine_restart(char *command)
851 +{
852 + switch (mips_machtype) {
853 + case MACH_ARUBA_AP70:
854 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
855 + break;
856 + case MACH_ARUBA_AP65:
857 + case MACH_ARUBA_AP60:
858 + default:
859 + /* Reset*/
860 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
861 + udelay(100);
862 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
863 + udelay(100);
864 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
865 + break;
866 + }
867 +}
868 +
869 +static void aruba_machine_halt(void)
870 +{
871 + for (;;) continue;
872 +}
873 +
874 +extern char * getenv(char *e);
875 +extern void unlock_ap60_70_flash(void);
876 +
877 +void __init plat_setup(void)
878 +{
879 + board_time_init = aruba_time_init;
880 +
881 + board_timer_setup = aruba_timer_setup;
882 +
883 + _machine_restart = aruba_machine_restart;
884 + _machine_halt = aruba_machine_halt;
885 + pm_power_off = aruba_machine_halt;
886 +
887 + set_io_port_base(KSEG1);
888 +
889 + /* Enable PCI interrupts in EPLD Mask register */
890 + *epldMask = 0x0;
891 + *(epldMask + 1) = 0x0;
892 +
893 + write_c0_wired(0);
894 + unlock_ap60_70_flash();
895 +
896 + printk("BOARD - %s\n",getenv("boardname"));
897 +
898 + return 0;
899 +}
900 +
901 +int page_is_ram(unsigned long pagenr)
902 +{
903 + return 1;
904 +}
905 +
906 +const char *get_system_type(void)
907 +{
908 + switch (mips_machtype) {
909 + case MACH_ARUBA_AP70:
910 + return "Aruba AP70";
911 + case MACH_ARUBA_AP65:
912 + return "Aruba AP65";
913 + case MACH_ARUBA_AP60:
914 + return "Aruba AP60/AP61";
915 + default:
916 + return "Aruba UNKNOWN";
917 + }
918 +}
919 +
920 +EXPORT_SYMBOL(get_system_type);
921 diff -Nur linux-2.6.17/arch/mips/aruba/time.c linux-2.6.17-owrt/arch/mips/aruba/time.c
922 --- linux-2.6.17/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
923 +++ linux-2.6.17-owrt/arch/mips/aruba/time.c 2006-06-18 12:44:28.000000000 +0200
924 @@ -0,0 +1,108 @@
925 +/**************************************************************************
926 + *
927 + * BRIEF MODULE DESCRIPTION
928 + * timer routines for IDT EB434 boards
929 + *
930 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
931 + *
932 + * This program is free software; you can redistribute it and/or modify it
933 + * under the terms of the GNU General Public License as published by the
934 + * Free Software Foundation; either version 2 of the License, or (at your
935 + * option) any later version.
936 + *
937 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
938 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
939 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
940 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
941 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
942 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
943 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
944 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
945 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
946 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
947 + *
948 + * You should have received a copy of the GNU General Public License along
949 + * with this program; if not, write to the Free Software Foundation, Inc.,
950 + * 675 Mass Ave, Cambridge, MA 02139, USA.
951 + *
952 + *
953 + **************************************************************************
954 + * May 2004 rkt, neb
955 + *
956 + * Initial Release
957 + *
958 + *
959 + *
960 + **************************************************************************
961 + */
962 +
963 +#include <linux/config.h>
964 +#include <linux/init.h>
965 +#include <linux/kernel_stat.h>
966 +#include <linux/sched.h>
967 +#include <linux/spinlock.h>
968 +#include <linux/mc146818rtc.h>
969 +#include <linux/irq.h>
970 +#include <linux/timex.h>
971 +
972 +#include <linux/param.h>
973 +#include <asm/mipsregs.h>
974 +#include <asm/ptrace.h>
975 +#include <asm/time.h>
976 +#include <asm/hardirq.h>
977 +
978 +#include <asm/mipsregs.h>
979 +#include <asm/ptrace.h>
980 +#include <asm/debug.h>
981 +#include <asm/time.h>
982 +
983 +#include <asm/idt-boards/rc32434/rc32434.h>
984 +
985 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
986 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
987 +
988 +extern unsigned int idt_cpu_freq;
989 +
990 +static unsigned long __init cal_r4koff(void)
991 +{
992 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
993 + return (mips_hpt_frequency / HZ);
994 +}
995 +
996 +void __init aruba_time_init(void)
997 +{
998 + unsigned int est_freq, flags;
999 + local_irq_save(flags);
1000 +
1001 + printk("calculating r4koff... ");
1002 + r4k_offset = cal_r4koff();
1003 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
1004 +
1005 + est_freq = 2 * r4k_offset * HZ;
1006 + est_freq += 5000; /* round */
1007 + est_freq -= est_freq % 10000;
1008 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1009 + (est_freq % 1000000) * 100 / 1000000);
1010 + local_irq_restore(flags);
1011 +
1012 +}
1013 +
1014 +void __init aruba_timer_setup(struct irqaction *irq)
1015 +{
1016 + /* we are using the cpu counter for timer interrupts */
1017 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1018 +
1019 + /* to generate the first timer interrupt */
1020 + r4k_cur = (read_c0_count() + r4k_offset);
1021 + write_c0_compare(r4k_cur);
1022 +
1023 +}
1024 +
1025 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1026 +{
1027 + irq_enter();
1028 + kstat_this_cpu.irqs[irq]++;
1029 +
1030 + timer_interrupt(irq, NULL, regs);
1031 + irq_exit();
1032 +}
1033 diff -Nur linux-2.6.17/arch/mips/Kconfig linux-2.6.17-owrt/arch/mips/Kconfig
1034 --- linux-2.6.17/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
1035 +++ linux-2.6.17-owrt/arch/mips/Kconfig 2006-06-18 12:44:28.000000000 +0200
1036 @@ -227,6 +227,17 @@
1037 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1038 a kernel for this platform.
1039
1040 +config MACH_ARUBA
1041 + bool "Support for the ARUBA product line"
1042 + select DMA_NONCOHERENT
1043 + select CPU_HAS_PREFETCH
1044 + select HW_HAS_PCI
1045 + select SWAP_IO_SPACE
1046 + select SYS_SUPPORTS_32BIT_KERNEL
1047 + select SYS_HAS_CPU_MIPS32_R1
1048 + select SYS_SUPPORTS_BIG_ENDIAN
1049 +
1050 +
1051 config MACH_JAZZ
1052 bool "Jazz family of machines"
1053 select ARC
1054 diff -Nur linux-2.6.17/arch/mips/Makefile linux-2.6.17-owrt/arch/mips/Makefile
1055 --- linux-2.6.17/arch/mips/Makefile 2006-06-18 03:49:35.000000000 +0200
1056 +++ linux-2.6.17-owrt/arch/mips/Makefile 2006-06-18 12:44:28.000000000 +0200
1057 @@ -145,6 +145,14 @@
1058 #
1059
1060 #
1061 +# Aruba
1062 +#
1063 +
1064 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1065 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1066 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1067 +
1068 +#
1069 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1070 #
1071 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1072 diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
1073 --- linux-2.6.17/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200
1074 +++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c 2006-06-18 12:48:27.000000000 +0200
1075 @@ -876,7 +876,6 @@
1076 case CPU_R10000:
1077 case CPU_R12000:
1078 case CPU_R14000:
1079 - case CPU_4KC:
1080 case CPU_SB1:
1081 case CPU_SB1A:
1082 case CPU_4KSC:
1083 @@ -904,6 +903,7 @@
1084 tlbw(p);
1085 break;
1086
1087 + case CPU_4KC:
1088 case CPU_4KEC:
1089 case CPU_24K:
1090 case CPU_34K:
1091 diff -Nur linux-2.6.17/drivers/net/Kconfig linux-2.6.17-owrt/drivers/net/Kconfig
1092 --- linux-2.6.17/drivers/net/Kconfig 2006-06-18 03:49:35.000000000 +0200
1093 +++ linux-2.6.17-owrt/drivers/net/Kconfig 2006-06-18 12:44:28.000000000 +0200
1094 @@ -187,6 +187,13 @@
1095
1096 source "drivers/net/arm/Kconfig"
1097
1098 +config IDT_RC32434_ETH
1099 + tristate "IDT RC32434 Local Ethernet support"
1100 + depends on NET_ETHERNET
1101 + help
1102 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1103 + To compile this driver as a module, choose M here.
1104 +
1105 config MACE
1106 tristate "MACE (Power Mac ethernet) support"
1107 depends on NET_ETHERNET && PPC_PMAC && PPC32
1108 diff -Nur linux-2.6.17/drivers/net/Makefile linux-2.6.17-owrt/drivers/net/Makefile
1109 --- linux-2.6.17/drivers/net/Makefile 2006-06-18 03:49:35.000000000 +0200
1110 +++ linux-2.6.17-owrt/drivers/net/Makefile 2006-06-18 12:44:28.000000000 +0200
1111 @@ -38,6 +38,7 @@
1112
1113 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1114
1115 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1116 obj-$(CONFIG_DGRS) += dgrs.o
1117 obj-$(CONFIG_VORTEX) += 3c59x.o
1118 obj-$(CONFIG_TYPHOON) += typhoon.o
1119 diff -Nur linux-2.6.17/drivers/net/natsemi.c linux-2.6.17-owrt/drivers/net/natsemi.c
1120 --- linux-2.6.17/drivers/net/natsemi.c 2006-06-18 03:49:35.000000000 +0200
1121 +++ linux-2.6.17-owrt/drivers/net/natsemi.c 2006-06-18 12:44:28.000000000 +0200
1122 @@ -771,6 +771,49 @@
1123 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1124 static struct ethtool_ops ethtool_ops;
1125
1126 +#ifdef CONFIG_MACH_ARUBA
1127 +
1128 +#include <linux/ctype.h>
1129 +
1130 +#ifndef ERR
1131 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1132 +#endif
1133 +
1134 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1135 +{
1136 + int i, j;
1137 + unsigned char result, value;
1138 +
1139 + for (i=0; i<6; i++) {
1140 + result = 0;
1141 + if (i != 5 && *(macstr+2) != ':') {
1142 + ERR("invalid mac address format: %d %c\n",
1143 + i, *(macstr+2));
1144 + return -EINVAL;
1145 + }
1146 + for (j=0; j<2; j++) {
1147 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1148 + toupper(*macstr)-'A'+10) < 16) {
1149 + result = result*16 + value;
1150 + macstr++;
1151 + }
1152 + else {
1153 + ERR("invalid mac address "
1154 + "character: %c\n", *macstr);
1155 + return -EINVAL;
1156 + }
1157 + }
1158 +
1159 + macstr++;
1160 + dev->dev_addr[i] = result;
1161 + }
1162 +
1163 + dev->dev_addr[5]++;
1164 + return 0;
1165 +}
1166 +
1167 +#endif
1168 +
1169 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1170 {
1171 return (void __iomem *) dev->base_addr;
1172 @@ -871,6 +914,7 @@
1173 goto err_ioremap;
1174 }
1175
1176 +#ifndef CONFIG_MACH_ARUBA
1177 /* Work around the dropped serial bit. */
1178 prev_eedata = eeprom_read(ioaddr, 6);
1179 for (i = 0; i < 3; i++) {
1180 @@ -879,6 +923,19 @@
1181 dev->dev_addr[i*2+1] = eedata >> 7;
1182 prev_eedata = eedata;
1183 }
1184 +#else
1185 + {
1186 + char mac[32];
1187 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1188 + extern char *getenv(char *e);
1189 + memset(mac, 0, 32);
1190 + memcpy(mac, getenv("ethaddr"), 17);
1191 + if (parse_mac_addr(dev, mac)){
1192 + printk("%s: MAC address not found\n", __func__);
1193 + memcpy(dev->dev_addr, def_mac, 6);
1194 + }
1195 + }
1196 +#endif
1197
1198 dev->base_addr = (unsigned long __force) ioaddr;
1199 dev->irq = irq;
1200 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.c linux-2.6.17-owrt/drivers/net/rc32434_eth.c
1201 --- linux-2.6.17/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1202 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.c 2006-06-18 12:44:28.000000000 +0200
1203 @@ -0,0 +1,1268 @@
1204 +/**************************************************************************
1205 + *
1206 + * BRIEF MODULE DESCRIPTION
1207 + * Driver for the IDT RC32434 on-chip ethernet controller.
1208 + *
1209 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1210 + *
1211 + * This program is free software; you can redistribute it and/or modify it
1212 + * under the terms of the GNU General Public License as published by the
1213 + * Free Software Foundation; either version 2 of the License, or (at your
1214 + * option) any later version.
1215 + *
1216 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1217 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1218 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1219 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1220 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1221 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1222 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1223 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1224 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1225 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1226 + *
1227 + * You should have received a copy of the GNU General Public License along
1228 + * with this program; if not, write to the Free Software Foundation, Inc.,
1229 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1230 + *
1231 + *
1232 + **************************************************************************
1233 + * May 2004 rkt, neb
1234 + *
1235 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1236 + *
1237 + * Aug 2004 Sadik
1238 + *
1239 + * Added NAPI
1240 + *
1241 + **************************************************************************
1242 + */
1243 +
1244 +#include <linux/config.h>
1245 +#include <linux/module.h>
1246 +#include <linux/kernel.h>
1247 +#include <linux/moduleparam.h>
1248 +#include <linux/sched.h>
1249 +#include <linux/ctype.h>
1250 +#include <linux/types.h>
1251 +#include <linux/fcntl.h>
1252 +#include <linux/interrupt.h>
1253 +#include <linux/ptrace.h>
1254 +#include <linux/init.h>
1255 +#include <linux/ioport.h>
1256 +#include <linux/proc_fs.h>
1257 +#include <linux/in.h>
1258 +#include <linux/slab.h>
1259 +#include <linux/string.h>
1260 +#include <linux/delay.h>
1261 +#include <linux/netdevice.h>
1262 +#include <linux/etherdevice.h>
1263 +#include <linux/skbuff.h>
1264 +#include <linux/errno.h>
1265 +#include <asm/bootinfo.h>
1266 +#include <asm/system.h>
1267 +#include <asm/bitops.h>
1268 +#include <asm/pgtable.h>
1269 +#include <asm/segment.h>
1270 +#include <asm/io.h>
1271 +#include <asm/dma.h>
1272 +
1273 +#include "rc32434_eth.h"
1274 +
1275 +#define DRIVER_VERSION "(mar2904)"
1276 +
1277 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1278 +
1279 +
1280 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1281 + ((dev)->dev_addr[1]))
1282 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1283 + ((dev)->dev_addr[3] << 16) | \
1284 + ((dev)->dev_addr[4] << 8) | \
1285 + ((dev)->dev_addr[5]))
1286 +
1287 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1288 +static char mac0[18] = "08:00:06:05:40:01";
1289 +
1290 +MODULE_PARM(mac0, "c18");
1291 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1292 +
1293 +static struct rc32434_if_t {
1294 + char *name;
1295 + struct net_device *dev;
1296 + char* mac_str;
1297 + int weight;
1298 + u32 iobase;
1299 + u32 rxdmabase;
1300 + u32 txdmabase;
1301 + int rx_dma_irq;
1302 + int tx_dma_irq;
1303 + int rx_ovr_irq;
1304 + int tx_und_irq;
1305 +} rc32434_iflist[] =
1306 +{
1307 + {
1308 + "rc32434_eth0", NULL, mac0,
1309 + 64,
1310 + ETH0_PhysicalAddress,
1311 + ETH0_RX_DMA_ADDR,
1312 + ETH0_TX_DMA_ADDR,
1313 + ETH0_DMA_RX_IRQ,
1314 + ETH0_DMA_TX_IRQ,
1315 + ETH0_RX_OVR_IRQ,
1316 + ETH0_TX_UND_IRQ
1317 + }
1318 +};
1319 +
1320 +
1321 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1322 +{
1323 + int i, j;
1324 + unsigned char result, value;
1325 +
1326 + for (i=0; i<6; i++) {
1327 + result = 0;
1328 + if (i != 5 && *(macstr+2) != ':') {
1329 + ERR("invalid mac address format: %d %c\n",
1330 + i, *(macstr+2));
1331 + return -EINVAL;
1332 + }
1333 + for (j=0; j<2; j++) {
1334 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1335 + toupper(*macstr)-'A'+10) < 16) {
1336 + result = result*16 + value;
1337 + macstr++;
1338 + }
1339 + else {
1340 + ERR("invalid mac address "
1341 + "character: %c\n", *macstr);
1342 + return -EINVAL;
1343 + }
1344 + }
1345 +
1346 + macstr++;
1347 + dev->dev_addr[i] = result;
1348 + }
1349 +
1350 + return 0;
1351 +}
1352 +
1353 +
1354 +
1355 +static inline void rc32434_abort_tx(struct net_device *dev)
1356 +{
1357 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1358 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1359 +
1360 +}
1361 +
1362 +static inline void rc32434_abort_rx(struct net_device *dev)
1363 +{
1364 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1365 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1366 +
1367 +}
1368 +
1369 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1370 +{
1371 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1372 +}
1373 +
1374 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1375 +{
1376 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1377 +}
1378 +
1379 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1380 +{
1381 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1382 +}
1383 +
1384 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1385 +{
1386 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1387 +}
1388 +
1389 +#ifdef RC32434_PROC_DEBUG
1390 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1391 + int length, int *eof, void *data)
1392 +{
1393 + struct net_device *dev = (struct net_device *)data;
1394 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1395 + int len = 0;
1396 +
1397 + /* print out header */
1398 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1399 + len += sprintf (buf + len,
1400 + "DMA halt count = %10d, DMA run count = %10d\n",
1401 + lp->dma_halt_cnt, lp->dma_run_cnt);
1402 +
1403 + if (fpos >= len) {
1404 + *start = buf;
1405 + *eof = 1;
1406 + return 0;
1407 + }
1408 + *start = buf + fpos;
1409 +
1410 + if ((len -= fpos) > length)
1411 + return length;
1412 + *eof = 1;
1413 +
1414 + return len;
1415 +
1416 +}
1417 +#endif
1418 +
1419 +
1420 +/*
1421 + * Restart the RC32434 ethernet controller.
1422 + */
1423 +static int rc32434_restart(struct net_device *dev)
1424 +{
1425 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1426 +
1427 + /*
1428 + * Disable interrupts
1429 + */
1430 + disable_irq(lp->rx_irq);
1431 + disable_irq(lp->tx_irq);
1432 +#ifdef RC32434_REVISION
1433 + disable_irq(lp->ovr_irq);
1434 +#endif
1435 + disable_irq(lp->und_irq);
1436 +
1437 + /* Mask F E bit in Tx DMA */
1438 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1439 + /* Mask D H E bit in Rx DMA */
1440 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1441 +
1442 + rc32434_init(dev);
1443 + rc32434_multicast_list(dev);
1444 +
1445 + enable_irq(lp->und_irq);
1446 +#ifdef RC32434_REVISION
1447 + enable_irq(lp->ovr_irq);
1448 +#endif
1449 + enable_irq(lp->tx_irq);
1450 + enable_irq(lp->rx_irq);
1451 +
1452 + return 0;
1453 +}
1454 +
1455 +int rc32434_init_module(void)
1456 +{
1457 +#ifdef CONFIG_MACH_ARUBA
1458 + if (mips_machtype != MACH_ARUBA_AP70)
1459 + return 1;
1460 +#endif
1461 +
1462 + printk(KERN_INFO DRIVER_NAME " \n");
1463 + return rc32434_probe(0);
1464 +}
1465 +
1466 +static int rc32434_probe(int port_num)
1467 +{
1468 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1469 + struct rc32434_local *lp = NULL;
1470 + struct net_device *dev = NULL;
1471 + int i, retval,err;
1472 +
1473 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1474 + if(!dev) {
1475 + ERR("rc32434_eth: alloc_etherdev failed\n");
1476 + return -1;
1477 + }
1478 +
1479 + SET_MODULE_OWNER(dev);
1480 + bif->dev = dev;
1481 +
1482 +#ifdef CONFIG_MACH_ARUBA
1483 + {
1484 + extern char * getenv(char *e);
1485 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1486 + }
1487 +#endif
1488 +
1489 + printk("mac: %s\n", bif->mac_str);
1490 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1491 + ERR("MAC address parse failed\n");
1492 + free_netdev(dev);
1493 + return -1;
1494 + }
1495 +
1496 +
1497 + /* Initialize the device structure. */
1498 + if (dev->priv == NULL) {
1499 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1500 + memset(lp, 0, sizeof(struct rc32434_local));
1501 + }
1502 + else {
1503 + lp = (struct rc32434_local *)dev->priv;
1504 + }
1505 +
1506 + lp->rx_irq = bif->rx_dma_irq;
1507 + lp->tx_irq = bif->tx_dma_irq;
1508 + lp->ovr_irq = bif->rx_ovr_irq;
1509 + lp->und_irq = bif->tx_und_irq;
1510 +
1511 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1512 +
1513 + if (!lp->eth_regs) {
1514 + ERR("Can't remap eth registers\n");
1515 + retval = -ENXIO;
1516 + goto probe_err_out;
1517 + }
1518 +
1519 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1520 +
1521 + if (!lp->rx_dma_regs) {
1522 + ERR("Can't remap Rx DMA registers\n");
1523 + retval = -ENXIO;
1524 + goto probe_err_out;
1525 + }
1526 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1527 +
1528 + if (!lp->tx_dma_regs) {
1529 + ERR("Can't remap Tx DMA registers\n");
1530 + retval = -ENXIO;
1531 + goto probe_err_out;
1532 + }
1533 +
1534 +#ifdef RC32434_PROC_DEBUG
1535 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1536 + rc32434_read_proc, dev);
1537 +#endif
1538 +
1539 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1540 + if (!lp->td_ring) {
1541 + ERR("Can't allocate descriptors\n");
1542 + retval = -ENOMEM;
1543 + goto probe_err_out;
1544 + }
1545 +
1546 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1547 +
1548 + /* now convert TD_RING pointer to KSEG1 */
1549 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1550 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1551 +
1552 +
1553 + spin_lock_init(&lp->lock);
1554 +
1555 + dev->base_addr = bif->iobase;
1556 + /* just use the rx dma irq */
1557 + dev->irq = bif->rx_dma_irq;
1558 +
1559 + dev->priv = lp;
1560 +
1561 + dev->open = rc32434_open;
1562 + dev->stop = rc32434_close;
1563 + dev->hard_start_xmit = rc32434_send_packet;
1564 + dev->get_stats = rc32434_get_stats;
1565 + dev->set_multicast_list = &rc32434_multicast_list;
1566 + dev->tx_timeout = rc32434_tx_timeout;
1567 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1568 +
1569 +#ifdef CONFIG_IDT_USE_NAPI
1570 + dev->poll = rc32434_poll;
1571 + dev->weight = bif->weight;
1572 + printk("Using NAPI with weight %d\n",dev->weight);
1573 +#else
1574 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1575 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1576 +#endif
1577 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1578 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1579 +
1580 + if ((err = register_netdev(dev))) {
1581 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1582 + free_netdev(dev);
1583 + retval = -EINVAL;
1584 + goto probe_err_out;
1585 + }
1586 +
1587 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1588 + for (i = 0; i < 6; i++) {
1589 + printk("%2.2x", dev->dev_addr[i]);
1590 + if (i<5)
1591 + printk(":");
1592 + }
1593 + printk("\n");
1594 +
1595 + return 0;
1596 +
1597 + probe_err_out:
1598 + rc32434_cleanup_module();
1599 + ERR(" failed. Returns %d\n", retval);
1600 + return retval;
1601 +
1602 +}
1603 +
1604 +
1605 +static void rc32434_cleanup_module(void)
1606 +{
1607 + int i;
1608 +
1609 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1610 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1611 + if (bif->dev != NULL) {
1612 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1613 + if (lp != NULL) {
1614 + if (lp->eth_regs)
1615 + iounmap((void*)lp->eth_regs);
1616 + if (lp->rx_dma_regs)
1617 + iounmap((void*)lp->rx_dma_regs);
1618 + if (lp->tx_dma_regs)
1619 + iounmap((void*)lp->tx_dma_regs);
1620 + if (lp->td_ring)
1621 + kfree((void*)KSEG0ADDR(lp->td_ring));
1622 +
1623 +#ifdef RC32434_PROC_DEBUG
1624 + if (lp->ps) {
1625 + remove_proc_entry(bif->name, proc_net);
1626 + }
1627 +#endif
1628 + kfree(lp);
1629 + }
1630 +
1631 + unregister_netdev(bif->dev);
1632 + free_netdev(bif->dev);
1633 + kfree(bif->dev);
1634 + }
1635 + }
1636 +}
1637 +
1638 +
1639 +
1640 +static int rc32434_open(struct net_device *dev)
1641 +{
1642 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1643 +
1644 + /* Initialize */
1645 + if (rc32434_init(dev)) {
1646 + ERR("Error: cannot open the Ethernet device\n");
1647 + return -EAGAIN;
1648 + }
1649 +
1650 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1651 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1652 + SA_SHIRQ | SA_INTERRUPT,
1653 + "rc32434 ethernet Rx", dev)) {
1654 + ERR(": unable to get Rx DMA IRQ %d\n",
1655 + lp->rx_irq);
1656 + return -EAGAIN;
1657 + }
1658 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1659 + SA_SHIRQ | SA_INTERRUPT,
1660 + "rc32434 ethernet Tx", dev)) {
1661 + ERR(": unable to get Tx DMA IRQ %d\n",
1662 + lp->tx_irq);
1663 + free_irq(lp->rx_irq, dev);
1664 + return -EAGAIN;
1665 + }
1666 +
1667 +#ifdef RC32434_REVISION
1668 + /* Install handler for overrun error. */
1669 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1670 + SA_SHIRQ | SA_INTERRUPT,
1671 + "Ethernet Overflow", dev)) {
1672 + ERR(": unable to get OVR IRQ %d\n",
1673 + lp->ovr_irq);
1674 + free_irq(lp->rx_irq, dev);
1675 + free_irq(lp->tx_irq, dev);
1676 + return -EAGAIN;
1677 + }
1678 +#endif
1679 +
1680 + /* Install handler for underflow error. */
1681 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1682 + SA_SHIRQ | SA_INTERRUPT,
1683 + "Ethernet Underflow", dev)) {
1684 + ERR(": unable to get UND IRQ %d\n",
1685 + lp->und_irq);
1686 + free_irq(lp->rx_irq, dev);
1687 + free_irq(lp->tx_irq, dev);
1688 +#ifdef RC32434_REVISION
1689 + free_irq(lp->ovr_irq, dev);
1690 +#endif
1691 + return -EAGAIN;
1692 + }
1693 +
1694 +
1695 + return 0;
1696 +}
1697 +
1698 +
1699 +
1700 +
1701 +static int rc32434_close(struct net_device *dev)
1702 +{
1703 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1704 + u32 tmp;
1705 +
1706 + /* Disable interrupts */
1707 + disable_irq(lp->rx_irq);
1708 + disable_irq(lp->tx_irq);
1709 +#ifdef RC32434_REVISION
1710 + disable_irq(lp->ovr_irq);
1711 +#endif
1712 + disable_irq(lp->und_irq);
1713 +
1714 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1715 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1716 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1717 +
1718 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1719 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1720 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1721 +
1722 + free_irq(lp->rx_irq, dev);
1723 + free_irq(lp->tx_irq, dev);
1724 +#ifdef RC32434_REVISION
1725 + free_irq(lp->ovr_irq, dev);
1726 +#endif
1727 + free_irq(lp->und_irq, dev);
1728 + return 0;
1729 +}
1730 +
1731 +
1732 +/* transmit packet */
1733 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1734 +{
1735 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1736 + unsigned long flags;
1737 + u32 length;
1738 + DMAD_t td;
1739 +
1740 +
1741 + spin_lock_irqsave(&lp->lock, flags);
1742 +
1743 + td = &lp->td_ring[lp->tx_chain_tail];
1744 +
1745 + /* stop queue when full, drop pkts if queue already full */
1746 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1747 + lp->tx_full = 1;
1748 +
1749 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1750 + netif_stop_queue(dev);
1751 + }
1752 + else {
1753 + lp->stats.tx_dropped++;
1754 + dev_kfree_skb_any(skb);
1755 + spin_unlock_irqrestore(&lp->lock, flags);
1756 + return 1;
1757 + }
1758 + }
1759 +
1760 + lp->tx_count ++;
1761 +
1762 + lp->tx_skb[lp->tx_chain_tail] = skb;
1763 +
1764 + length = skb->len;
1765 +
1766 + /* Setup the transmit descriptor. */
1767 + td->ca = CPHYSADDR(skb->data);
1768 +
1769 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1770 + if( lp->tx_chain_status == empty ) {
1771 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1772 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1773 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1774 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1775 + }
1776 + else {
1777 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1778 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1779 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1780 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1781 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1782 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1783 + lp->tx_chain_status = empty;
1784 + }
1785 + }
1786 + else {
1787 + if( lp->tx_chain_status == empty ) {
1788 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1789 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1790 + lp->tx_chain_status = filled;
1791 + }
1792 + else {
1793 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1794 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1795 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1796 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1797 + }
1798 + }
1799 +
1800 + dev->trans_start = jiffies;
1801 +
1802 + spin_unlock_irqrestore(&lp->lock, flags);
1803 +
1804 + return 0;
1805 +}
1806 +
1807 +
1808 +/* Ethernet MII-PHY Handler */
1809 +static void rc32434_mii_handler(unsigned long data)
1810 +{
1811 + struct net_device *dev = (struct net_device *)data;
1812 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1813 + unsigned long flags;
1814 + unsigned long duplex_status;
1815 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1816 +
1817 + spin_lock_irqsave(&lp->lock, flags);
1818 +
1819 + /* Two ports are using the same MII, the difference is the PHY address */
1820 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1821 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1822 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1823 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1824 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1825 +
1826 + ERR("irq:%x port_addr:%x RDD:%x\n",
1827 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1828 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1829 + if(duplex_status != lp->duplex_mode) {
1830 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1831 + lp->duplex_mode = duplex_status;
1832 + rc32434_restart(dev);
1833 + }
1834 +
1835 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1836 + add_timer(&lp->mii_phy_timer);
1837 +
1838 + spin_unlock_irqrestore(&lp->lock, flags);
1839 +
1840 +}
1841 +
1842 +#ifdef RC32434_REVISION
1843 +/* Ethernet Rx Overflow interrupt */
1844 +static irqreturn_t
1845 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1846 +{
1847 + struct net_device *dev = (struct net_device *)dev_id;
1848 + struct rc32434_local *lp;
1849 + unsigned int ovr;
1850 + irqreturn_t retval = IRQ_NONE;
1851 +
1852 + ASSERT(dev != NULL);
1853 +
1854 + lp = (struct rc32434_local *)dev->priv;
1855 + spin_lock(&lp->lock);
1856 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1857 +
1858 + if(ovr & ETHINTFC_ovr_m) {
1859 + netif_stop_queue(dev);
1860 +
1861 + /* clear OVR bit */
1862 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1863 +
1864 + /* Restart interface */
1865 + rc32434_restart(dev);
1866 + retval = IRQ_HANDLED;
1867 + }
1868 + spin_unlock(&lp->lock);
1869 +
1870 + return retval;
1871 +}
1872 +
1873 +#endif
1874 +
1875 +
1876 +/* Ethernet Tx Underflow interrupt */
1877 +static irqreturn_t
1878 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1879 +{
1880 + struct net_device *dev = (struct net_device *)dev_id;
1881 + struct rc32434_local *lp;
1882 + unsigned int und;
1883 + irqreturn_t retval = IRQ_NONE;
1884 +
1885 + ASSERT(dev != NULL);
1886 +
1887 + lp = (struct rc32434_local *)dev->priv;
1888 +
1889 + spin_lock(&lp->lock);
1890 +
1891 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1892 +
1893 + if(und & ETHINTFC_und_m) {
1894 + netif_stop_queue(dev);
1895 +
1896 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1897 +
1898 + /* Restart interface */
1899 + rc32434_restart(dev);
1900 + retval = IRQ_HANDLED;
1901 + }
1902 +
1903 + spin_unlock(&lp->lock);
1904 +
1905 + return retval;
1906 +}
1907 +
1908 +
1909 +/* Ethernet Rx DMA interrupt */
1910 +static irqreturn_t
1911 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1912 +{
1913 + struct net_device *dev = (struct net_device *)dev_id;
1914 + struct rc32434_local* lp;
1915 + volatile u32 dmas,dmasm;
1916 + irqreturn_t retval;
1917 +
1918 + ASSERT(dev != NULL);
1919 +
1920 + lp = (struct rc32434_local *)dev->priv;
1921 +
1922 + spin_lock(&lp->lock);
1923 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1924 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1925 + /* Mask D H E bit in Rx DMA */
1926 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1927 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1928 +#ifdef CONFIG_IDT_USE_NAPI
1929 + if(netif_rx_schedule_prep(dev))
1930 + __netif_rx_schedule(dev);
1931 +#else
1932 + tasklet_hi_schedule(lp->rx_tasklet);
1933 +#endif
1934 +
1935 + if (dmas & DMAS_e_m)
1936 + ERR(": DMA error\n");
1937 +
1938 + retval = IRQ_HANDLED;
1939 + }
1940 + else
1941 + retval = IRQ_NONE;
1942 +
1943 + spin_unlock(&lp->lock);
1944 + return retval;
1945 +}
1946 +
1947 +#ifdef CONFIG_IDT_USE_NAPI
1948 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1949 +#else
1950 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1951 +#endif
1952 +{
1953 + struct net_device *dev = (struct net_device *)rx_data_dev;
1954 + struct rc32434_local* lp = netdev_priv(dev);
1955 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1956 + struct sk_buff *skb, *skb_new;
1957 + u8* pkt_buf;
1958 + u32 devcs, count, pkt_len, pktuncrc_len;
1959 + volatile u32 dmas;
1960 +#ifdef CONFIG_IDT_USE_NAPI
1961 + u32 received = 0;
1962 + int rx_work_limit = min(*budget,dev->quota);
1963 +#else
1964 + unsigned long flags;
1965 + spin_lock_irqsave(&lp->lock, flags);
1966 +#endif
1967 +
1968 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1969 +#ifdef CONFIG_IDT_USE_NAPI
1970 + if(--rx_work_limit <0)
1971 + {
1972 + break;
1973 + }
1974 +#endif
1975 + /* init the var. used for the later operations within the while loop */
1976 + skb_new = NULL;
1977 + devcs = rd->devcs;
1978 + pkt_len = RCVPKT_LENGTH(devcs);
1979 + skb = lp->rx_skb[lp->rx_next_done];
1980 +
1981 + if (count < 64) {
1982 + lp->stats.rx_errors++;
1983 + lp->stats.rx_dropped++;
1984 + }
1985 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1986 + /* check that this is a whole packet */
1987 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1988 + lp->stats.rx_errors++;
1989 + lp->stats.rx_dropped++;
1990 + }
1991 + else if ( (devcs & ETHRX_rok_m) ) {
1992 +
1993 + {
1994 + /* must be the (first and) last descriptor then */
1995 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
1996 +
1997 + pktuncrc_len = pkt_len - 4;
1998 + /* invalidate the cache */
1999 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
2000 +
2001 + /* Malloc up new buffer. */
2002 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
2003 +
2004 + if (skb_new != NULL){
2005 + /* Make room */
2006 + skb_put(skb, pktuncrc_len);
2007 +
2008 + skb->protocol = eth_type_trans(skb, dev);
2009 +
2010 + /* pass the packet to upper layers */
2011 +#ifdef CONFIG_IDT_USE_NAPI
2012 + netif_receive_skb(skb);
2013 +#else
2014 + netif_rx(skb);
2015 +#endif
2016 +
2017 + dev->last_rx = jiffies;
2018 + lp->stats.rx_packets++;
2019 + lp->stats.rx_bytes += pktuncrc_len;
2020 +
2021 + if (IS_RCV_MP(devcs))
2022 + lp->stats.multicast++;
2023 +
2024 + /* 16 bit align */
2025 + skb_reserve(skb_new, 2);
2026 +
2027 + skb_new->dev = dev;
2028 + lp->rx_skb[lp->rx_next_done] = skb_new;
2029 + }
2030 + else {
2031 + ERR("no memory, dropping rx packet.\n");
2032 + lp->stats.rx_errors++;
2033 + lp->stats.rx_dropped++;
2034 + }
2035 + }
2036 +
2037 + }
2038 + else {
2039 + /* This should only happen if we enable accepting broken packets */
2040 + lp->stats.rx_errors++;
2041 + lp->stats.rx_dropped++;
2042 +
2043 + /* add statistics counters */
2044 + if (IS_RCV_CRC_ERR(devcs)) {
2045 + DBG(2, "RX CRC error\n");
2046 + lp->stats.rx_crc_errors++;
2047 + }
2048 + else if (IS_RCV_LOR_ERR(devcs)) {
2049 + DBG(2, "RX LOR error\n");
2050 + lp->stats.rx_length_errors++;
2051 + }
2052 + else if (IS_RCV_LE_ERR(devcs)) {
2053 + DBG(2, "RX LE error\n");
2054 + lp->stats.rx_length_errors++;
2055 + }
2056 + else if (IS_RCV_OVR_ERR(devcs)) {
2057 + lp->stats.rx_over_errors++;
2058 + }
2059 + else if (IS_RCV_CV_ERR(devcs)) {
2060 + /* code violation */
2061 + DBG(2, "RX CV error\n");
2062 + lp->stats.rx_frame_errors++;
2063 + }
2064 + else if (IS_RCV_CES_ERR(devcs)) {
2065 + DBG(2, "RX Preamble error\n");
2066 + }
2067 + }
2068 +
2069 + rd->devcs = 0;
2070 +
2071 + /* restore descriptor's curr_addr */
2072 + if(skb_new)
2073 + rd->ca = CPHYSADDR(skb_new->data);
2074 + else
2075 + rd->ca = CPHYSADDR(skb->data);
2076 +
2077 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2078 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2079 +
2080 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2081 + rd = &lp->rd_ring[lp->rx_next_done];
2082 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2083 + }
2084 +#ifdef CONFIG_IDT_USE_NAPI
2085 + dev->quota -= received;
2086 + *budget =- received;
2087 + if(rx_work_limit < 0)
2088 + goto not_done;
2089 +#endif
2090 +
2091 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2092 +
2093 + if(dmas & DMAS_h_m) {
2094 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2095 +#ifdef RC32434_PROC_DEBUG
2096 + lp->dma_halt_cnt++;
2097 +#endif
2098 + rd->devcs = 0;
2099 + skb = lp->rx_skb[lp->rx_next_done];
2100 + rd->ca = CPHYSADDR(skb->data);
2101 + rc32434_chain_rx(lp,rd);
2102 + }
2103 +
2104 +#ifdef CONFIG_IDT_USE_NAPI
2105 + netif_rx_complete(dev);
2106 +#endif
2107 + /* Enable D H E bit in Rx DMA */
2108 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2109 +#ifdef CONFIG_IDT_USE_NAPI
2110 + return 0;
2111 + not_done:
2112 + return 1;
2113 +#else
2114 + spin_unlock_irqrestore(&lp->lock, flags);
2115 + return;
2116 +#endif
2117 +
2118 +
2119 +}
2120 +
2121 +
2122 +
2123 +/* Ethernet Tx DMA interrupt */
2124 +static irqreturn_t
2125 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2126 +{
2127 + struct net_device *dev = (struct net_device *)dev_id;
2128 + struct rc32434_local *lp;
2129 + volatile u32 dmas,dmasm;
2130 + irqreturn_t retval;
2131 +
2132 + ASSERT(dev != NULL);
2133 +
2134 + lp = (struct rc32434_local *)dev->priv;
2135 +
2136 + spin_lock(&lp->lock);
2137 +
2138 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2139 +
2140 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2141 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2142 + /* Mask F E bit in Tx DMA */
2143 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2144 +
2145 + tasklet_hi_schedule(lp->tx_tasklet);
2146 +
2147 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2148 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2149 + lp->tx_chain_status = empty;
2150 + lp->tx_chain_head = lp->tx_chain_tail;
2151 + dev->trans_start = jiffies;
2152 + }
2153 +
2154 + if (dmas & DMAS_e_m)
2155 + ERR(": DMA error\n");
2156 +
2157 + retval = IRQ_HANDLED;
2158 + }
2159 + else
2160 + retval = IRQ_NONE;
2161 +
2162 + spin_unlock(&lp->lock);
2163 +
2164 + return retval;
2165 +}
2166 +
2167 +
2168 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2169 +{
2170 + struct net_device *dev = (struct net_device *)tx_data_dev;
2171 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2172 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2173 + u32 devcs;
2174 + unsigned long flags;
2175 + volatile u32 dmas;
2176 +
2177 + spin_lock_irqsave(&lp->lock, flags);
2178 +
2179 + /* process all desc that are done */
2180 + while(IS_DMA_FINISHED(td->control)) {
2181 + if(lp->tx_full == 1) {
2182 + netif_wake_queue(dev);
2183 + lp->tx_full = 0;
2184 + }
2185 +
2186 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2187 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2188 + lp->stats.tx_errors++;
2189 + lp->stats.tx_dropped++;
2190 +
2191 + /* should never happen */
2192 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2193 + }
2194 + else if (IS_TX_TOK(devcs)) {
2195 + lp->stats.tx_packets++;
2196 + }
2197 + else {
2198 + lp->stats.tx_errors++;
2199 + lp->stats.tx_dropped++;
2200 +
2201 + /* underflow */
2202 + if (IS_TX_UND_ERR(devcs))
2203 + lp->stats.tx_fifo_errors++;
2204 +
2205 + /* oversized frame */
2206 + if (IS_TX_OF_ERR(devcs))
2207 + lp->stats.tx_aborted_errors++;
2208 +
2209 + /* excessive deferrals */
2210 + if (IS_TX_ED_ERR(devcs))
2211 + lp->stats.tx_carrier_errors++;
2212 +
2213 + /* collisions: medium busy */
2214 + if (IS_TX_EC_ERR(devcs))
2215 + lp->stats.collisions++;
2216 +
2217 + /* late collision */
2218 + if (IS_TX_LC_ERR(devcs))
2219 + lp->stats.tx_window_errors++;
2220 +
2221 + }
2222 +
2223 + /* We must always free the original skb */
2224 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2225 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2226 + lp->tx_skb[lp->tx_next_done] = NULL;
2227 + }
2228 +
2229 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2230 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2231 + lp->td_ring[lp->tx_next_done].link = 0;
2232 + lp->td_ring[lp->tx_next_done].ca = 0;
2233 + lp->tx_count --;
2234 +
2235 + /* go on to next transmission */
2236 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2237 + td = &lp->td_ring[lp->tx_next_done];
2238 +
2239 + }
2240 +
2241 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2242 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2243 +
2244 + /* Enable F E bit in Tx DMA */
2245 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2246 + spin_unlock_irqrestore(&lp->lock, flags);
2247 +
2248 +}
2249 +
2250 +
2251 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2252 +{
2253 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2254 + return &lp->stats;
2255 +}
2256 +
2257 +
2258 +/*
2259 + * Set or clear the multicast filter for this adaptor.
2260 + */
2261 +static void rc32434_multicast_list(struct net_device *dev)
2262 +{
2263 + /* listen to broadcasts always and to treat */
2264 + /* IFF bits independantly */
2265 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2266 + unsigned long flags;
2267 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2268 +
2269 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2270 + recognise |= ETHARC_pro_m;
2271 +
2272 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2273 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2274 + else if (dev->mc_count > 0) {
2275 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2276 + recognise |= ETHARC_am_m; /* for the time being */
2277 + }
2278 +
2279 + spin_lock_irqsave(&lp->lock, flags);
2280 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2281 + spin_unlock_irqrestore(&lp->lock, flags);
2282 +}
2283 +
2284 +
2285 +static void rc32434_tx_timeout(struct net_device *dev)
2286 +{
2287 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2288 + unsigned long flags;
2289 +
2290 + spin_lock_irqsave(&lp->lock, flags);
2291 + rc32434_restart(dev);
2292 + spin_unlock_irqrestore(&lp->lock, flags);
2293 +
2294 +}
2295 +
2296 +
2297 +/*
2298 + * Initialize the RC32434 ethernet controller.
2299 + */
2300 +static int rc32434_init(struct net_device *dev)
2301 +{
2302 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2303 + int i, j;
2304 +
2305 + /* Disable DMA */
2306 + rc32434_abort_tx(dev);
2307 + rc32434_abort_rx(dev);
2308 +
2309 + /* reset ethernet logic */
2310 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2311 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2312 + dev->trans_start = jiffies;
2313 +
2314 + /* Enable Ethernet Interface */
2315 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2316 +
2317 +#ifndef CONFIG_IDT_USE_NAPI
2318 + tasklet_disable(lp->rx_tasklet);
2319 +#endif
2320 + tasklet_disable(lp->tx_tasklet);
2321 +
2322 + /* Initialize the transmit Descriptors */
2323 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2324 + lp->td_ring[i].control = DMAD_iof_m;
2325 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2326 + lp->td_ring[i].ca = 0;
2327 + lp->td_ring[i].link = 0;
2328 + if (lp->tx_skb[i] != NULL) {
2329 + dev_kfree_skb_any(lp->tx_skb[i]);
2330 + lp->tx_skb[i] = NULL;
2331 + }
2332 + }
2333 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2334 + lp-> tx_chain_status = empty;
2335 +
2336 + /*
2337 + * Initialize the receive descriptors so that they
2338 + * become a circular linked list, ie. let the last
2339 + * descriptor point to the first again.
2340 + */
2341 + for (i=0; i<RC32434_NUM_RDS; i++) {
2342 + struct sk_buff *skb = lp->rx_skb[i];
2343 +
2344 + if (lp->rx_skb[i] == NULL) {
2345 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2346 + if (skb == NULL) {
2347 + ERR("No memory in the system\n");
2348 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2349 + if (lp->rx_skb[j] != NULL)
2350 + dev_kfree_skb_any(lp->rx_skb[j]);
2351 +
2352 + return 1;
2353 + }
2354 + else {
2355 + skb->dev = dev;
2356 + skb_reserve(skb, 2);
2357 + lp->rx_skb[i] = skb;
2358 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2359 +
2360 + }
2361 + }
2362 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2363 + lp->rd_ring[i].devcs = 0;
2364 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2365 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2366 +
2367 + }
2368 + /* loop back */
2369 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2370 + lp->rx_next_done = 0;
2371 +
2372 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2373 + lp->rx_chain_head = 0;
2374 + lp->rx_chain_tail = 0;
2375 + lp->rx_chain_status = empty;
2376 +
2377 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2378 + /* Start Rx DMA */
2379 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2380 +
2381 + /* Enable F E bit in Tx DMA */
2382 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2383 + /* Enable D H E bit in Rx DMA */
2384 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2385 +
2386 + /* Accept only packets destined for this Ethernet device address */
2387 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2388 +
2389 + /* Set all Ether station address registers to their initial values */
2390 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2391 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2392 +
2393 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2394 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2395 +
2396 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2397 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2398 +
2399 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2400 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2401 +
2402 +
2403 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2404 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2405 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2406 +
2407 + /* Back to back inter-packet-gap */
2408 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2409 + /* Non - Back to back inter-packet-gap */
2410 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2411 +
2412 + /* Management Clock Prescaler Divisor */
2413 + /* Clock independent setting */
2414 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2415 + &lp->eth_regs->ethmcp);
2416 +
2417 + /* don't transmit until fifo contains 48b */
2418 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2419 +
2420 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2421 +
2422 +#ifndef CONFIG_IDT_USE_NAPI
2423 + tasklet_enable(lp->rx_tasklet);
2424 +#endif
2425 + tasklet_enable(lp->tx_tasklet);
2426 +
2427 + netif_start_queue(dev);
2428 +
2429 +
2430 + return 0;
2431 +
2432 +}
2433 +
2434 +
2435 +#ifndef MODULE
2436 +
2437 +static int __init rc32434_setup(char *options)
2438 +{
2439 + /* no options yet */
2440 + return 1;
2441 +}
2442 +
2443 +static int __init rc32434_setup_ethaddr0(char *options)
2444 +{
2445 + memcpy(mac0, options, 17);
2446 + mac0[17]= '\0';
2447 + return 1;
2448 +}
2449 +
2450 +__setup("rc32434eth=", rc32434_setup);
2451 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2452 +
2453 +
2454 +#endif /* MODULE */
2455 +
2456 +module_init(rc32434_init_module);
2457 +module_exit(rc32434_cleanup_module);
2458 +
2459 +
2460 +
2461 +
2462 +
2463 +
2464 +
2465 +
2466 +
2467 +
2468 +
2469 +
2470 +
2471 +
2472 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.h linux-2.6.17-owrt/drivers/net/rc32434_eth.h
2473 --- linux-2.6.17/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2474 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
2475 @@ -0,0 +1,187 @@
2476 +/**************************************************************************
2477 + *
2478 + * BRIEF MODULE DESCRIPTION
2479 + * Definitions for IDT RC32434 on-chip ethernet controller.
2480 + *
2481 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2482 + *
2483 + * This program is free software; you can redistribute it and/or modify it
2484 + * under the terms of the GNU General Public License as published by the
2485 + * Free Software Foundation; either version 2 of the License, or (at your
2486 + * option) any later version.
2487 + *
2488 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2489 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2490 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2491 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2492 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2493 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2494 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2495 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2496 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2497 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2498 + *
2499 + * You should have received a copy of the GNU General Public License along
2500 + * with this program; if not, write to the Free Software Foundation, Inc.,
2501 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2502 + *
2503 + *
2504 + **************************************************************************
2505 + * May 2004 rkt, neb
2506 + *
2507 + * Initial Release
2508 + *
2509 + * Aug 2004
2510 + *
2511 + * Added NAPI
2512 + *
2513 + **************************************************************************
2514 + */
2515 +
2516 +
2517 +#include <asm/idt-boards/rc32434/rc32434.h>
2518 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2519 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2520 +
2521 +#define RC32434_DEBUG 2
2522 +//#define RC32434_PROC_DEBUG
2523 +#undef RC32434_DEBUG
2524 +
2525 +#ifdef RC32434_DEBUG
2526 +
2527 +/* use 0 for production, 1 for verification, >2 for debug */
2528 +static int rc32434_debug = RC32434_DEBUG;
2529 +#define ASSERT(expr) \
2530 + if(!(expr)) { \
2531 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2532 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2533 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2534 +#else
2535 +#define ASSERT(expr) do {} while (0)
2536 +#define DBG(lvl, format, arg...) do {} while (0)
2537 +#endif
2538 +
2539 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2540 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2541 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2542 +
2543 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2544 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2545 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2546 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2547 +
2548 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2549 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2550 +
2551 +/* the following must be powers of two */
2552 +#ifdef CONFIG_IDT_USE_NAPI
2553 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2554 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2555 +#else
2556 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2557 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2558 +#endif
2559 +
2560 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2561 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2562 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2563 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2564 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2565 +
2566 +#define RC32434_TX_TIMEOUT HZ * 100
2567 +
2568 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2569 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2570 +
2571 +enum status { filled, empty};
2572 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2573 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2574 +
2575 +
2576 +/* Information that need to be kept for each board. */
2577 +struct rc32434_local {
2578 + ETH_t eth_regs;
2579 + DMA_Chan_t rx_dma_regs;
2580 + DMA_Chan_t tx_dma_regs;
2581 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2582 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2583 +
2584 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2585 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2586 +
2587 +#ifndef CONFIG_IDT_USE_NAPI
2588 + struct tasklet_struct * rx_tasklet;
2589 +#endif
2590 + struct tasklet_struct * tx_tasklet;
2591 +
2592 + int rx_next_done;
2593 + int rx_chain_head;
2594 + int rx_chain_tail;
2595 + enum status rx_chain_status;
2596 +
2597 + int tx_next_done;
2598 + int tx_chain_head;
2599 + int tx_chain_tail;
2600 + enum status tx_chain_status;
2601 + int tx_count;
2602 + int tx_full;
2603 +
2604 + struct timer_list mii_phy_timer;
2605 + unsigned long duplex_mode;
2606 +
2607 + int rx_irq;
2608 + int tx_irq;
2609 + int ovr_irq;
2610 + int und_irq;
2611 +
2612 + struct net_device_stats stats;
2613 + spinlock_t lock;
2614 +
2615 + /* debug /proc entry */
2616 + struct proc_dir_entry *ps;
2617 + int dma_halt_cnt; int dma_run_cnt;
2618 +};
2619 +
2620 +extern unsigned int idt_cpu_freq;
2621 +
2622 +/* Index to functions, as function prototypes. */
2623 +static int rc32434_open(struct net_device *dev);
2624 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2625 +static void rc32434_mii_handler(unsigned long data);
2626 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2627 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2628 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2629 +#ifdef RC32434_REVISION
2630 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2631 +#endif
2632 +static int rc32434_close(struct net_device *dev);
2633 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2634 +static void rc32434_multicast_list(struct net_device *dev);
2635 +static int rc32434_init(struct net_device *dev);
2636 +static void rc32434_tx_timeout(struct net_device *dev);
2637 +
2638 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2639 +#ifdef CONFIG_IDT_USE_NAPI
2640 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2641 +#else
2642 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2643 +#endif
2644 +static void rc32434_cleanup_module(void);
2645 +static int rc32434_probe(int port_num);
2646 +int rc32434_init_module(void);
2647 +
2648 +
2649 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2650 +{
2651 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2652 + rc32434_writel(0x10, &ch->dmac);
2653 +
2654 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2655 + dev->trans_start = jiffies;
2656 +
2657 + rc32434_writel(0, &ch->dmas);
2658 + }
2659 +
2660 + rc32434_writel(0, &ch->dmadptr);
2661 + rc32434_writel(0, &ch->dmandptr);
2662 +}
2663 diff -Nur linux-2.6.17/include/asm-mips/bootinfo.h linux-2.6.17-owrt/include/asm-mips/bootinfo.h
2664 --- linux-2.6.17/include/asm-mips/bootinfo.h 2006-06-18 03:49:35.000000000 +0200
2665 +++ linux-2.6.17-owrt/include/asm-mips/bootinfo.h 2006-06-18 12:44:28.000000000 +0200
2666 @@ -218,6 +218,17 @@
2667 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2668 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2669
2670 +
2671 +/*
2672 + * Valid machtype for group ARUBA
2673 + */
2674 +#define MACH_GROUP_ARUBA 23
2675 +#define MACH_ARUBA_UNKNOWN 0
2676 +#define MACH_ARUBA_AP60 1
2677 +#define MACH_ARUBA_AP65 2
2678 +#define MACH_ARUBA_AP70 3
2679 +#define MACH_ARUBA_AP40 4
2680 +
2681 #define CL_SIZE COMMAND_LINE_SIZE
2682
2683 const char *get_system_type(void);
2684 diff -Nur linux-2.6.17/include/asm-mips/cpu.h linux-2.6.17-owrt/include/asm-mips/cpu.h
2685 --- linux-2.6.17/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
2686 +++ linux-2.6.17-owrt/include/asm-mips/cpu.h 2006-06-18 12:45:56.000000000 +0200
2687 @@ -54,6 +54,9 @@
2688 #define PRID_IMP_R14000 0x0f00
2689 #define PRID_IMP_R8000 0x1000
2690 #define PRID_IMP_PR4450 0x1200
2691 +#define PRID_IMP_RC32334 0x1800
2692 +#define PRID_IMP_RC32355 0x1900
2693 +#define PRID_IMP_RC32365 0x1900
2694 #define PRID_IMP_R4600 0x2000
2695 #define PRID_IMP_R4700 0x2100
2696 #define PRID_IMP_TX39 0x2200
2697 @@ -200,7 +203,8 @@
2698 #define CPU_SB1A 62
2699 #define CPU_74K 63
2700 #define CPU_R14000 64
2701 -#define CPU_LAST 64
2702 +#define CPU_RC32300 65
2703 +#define CPU_LAST 65
2704
2705 /*
2706 * ISA Level encodings
2707 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2708 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2709 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-06-18 12:44:28.000000000 +0200
2710 @@ -0,0 +1,142 @@
2711 +/**************************************************************************
2712 + *
2713 + * BRIEF MODULE DESCRIPTION
2714 + * RC32300 helper routines
2715 + *
2716 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2717 + *
2718 + * This program is free software; you can redistribute it and/or modify it
2719 + * under the terms of the GNU General Public License as published by the
2720 + * Free Software Foundation; either version 2 of the License, or (at your
2721 + * option) any later version.
2722 + *
2723 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2724 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2725 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2726 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2727 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2728 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2729 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2730 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2731 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2732 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2733 + *
2734 + * You should have received a copy of the GNU General Public License along
2735 + * with this program; if not, write to the Free Software Foundation, Inc.,
2736 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2737 + *
2738 + *
2739 + **************************************************************************
2740 + * May 2004 P. Sadik.
2741 + *
2742 + * Initial Release
2743 + *
2744 + *
2745 + *
2746 + **************************************************************************
2747 + */
2748 +
2749 +#ifndef __IDT_RC32300_H__
2750 +#define __IDT_RC32300_H__
2751 +
2752 +#include <linux/delay.h>
2753 +#include <asm/io.h>
2754 +
2755 +
2756 +/* cpu pipeline flush */
2757 +static inline void rc32300_sync(void)
2758 +{
2759 + __asm__ volatile ("sync");
2760 +}
2761 +
2762 +static inline void rc32300_sync_udelay(int us)
2763 +{
2764 + __asm__ volatile ("sync");
2765 + udelay(us);
2766 +}
2767 +
2768 +static inline void rc32300_sync_delay(int ms)
2769 +{
2770 + __asm__ volatile ("sync");
2771 + mdelay(ms);
2772 +}
2773 +
2774 +/*
2775 + * Macros to access internal RC32300 registers. No byte
2776 + * swapping should be done when accessing the internal
2777 + * registers.
2778 + */
2779 +
2780 +static inline u8 rc32300_readb(unsigned long pa)
2781 +{
2782 + return *((volatile u8 *)KSEG1ADDR(pa));
2783 +}
2784 +static inline u16 rc32300_readw(unsigned long pa)
2785 +{
2786 + return *((volatile u16 *)KSEG1ADDR(pa));
2787 +}
2788 +static inline u32 rc32300_readl(unsigned long pa)
2789 +{
2790 + return *((volatile u32 *)KSEG1ADDR(pa));
2791 +}
2792 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2793 +{
2794 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2795 +}
2796 +static inline void rc32300_writew(u16 val, unsigned long pa)
2797 +{
2798 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2799 +}
2800 +static inline void rc32300_writel(u32 val, unsigned long pa)
2801 +{
2802 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2803 +}
2804 +
2805 +
2806 +#define local_readb __raw_readb
2807 +#define local_readw __raw_readw
2808 +#define local_readl __raw_readl
2809 +
2810 +#define local_writeb __raw_writeb
2811 +#define local_writew __raw_writew
2812 +#define local_writel __raw_writel
2813 +
2814 +
2815 +/*
2816 + * C access to CLZ and CLO instructions
2817 + * (count leading zeroes/ones).
2818 + */
2819 +static inline int rc32300_clz(unsigned long val)
2820 +{
2821 + int ret;
2822 + __asm__ volatile (
2823 + ".set\tnoreorder\n\t"
2824 + ".set\tnoat\n\t"
2825 + ".set\tmips32\n\t"
2826 + "clz\t%0,%1\n\t"
2827 + ".set\tmips0\n\t"
2828 + ".set\tat\n\t"
2829 + ".set\treorder"
2830 + : "=r" (ret)
2831 + : "r" (val));
2832 +
2833 + return ret;
2834 +}
2835 +static inline int rc32300_clo(unsigned long val)
2836 +{
2837 + int ret;
2838 + __asm__ volatile (
2839 + ".set\tnoreorder\n\t"
2840 + ".set\tnoat\n\t"
2841 + ".set\tmips32\n\t"
2842 + "clo\t%0,%1\n\t"
2843 + ".set\tmips0\n\t"
2844 + ".set\tat\n\t"
2845 + ".set\treorder"
2846 + : "=r" (ret)
2847 + : "r" (val));
2848 +
2849 + return ret;
2850 +}
2851 +
2852 +#endif // __IDT_RC32300_H__
2853 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2854 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2855 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-06-18 12:44:28.000000000 +0200
2856 @@ -0,0 +1,207 @@
2857 +/**************************************************************************
2858 + *
2859 + * BRIEF MODULE DESCRIPTION
2860 + * Definitions for IDT RC32334 CPU.
2861 + *
2862 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2863 + *
2864 + * This program is free software; you can redistribute it and/or modify it
2865 + * under the terms of the GNU General Public License as published by the
2866 + * Free Software Foundation; either version 2 of the License, or (at your
2867 + * option) any later version.
2868 + *
2869 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2870 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2871 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2872 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2873 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2874 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2875 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2876 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2877 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2878 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2879 + *
2880 + * You should have received a copy of the GNU General Public License along
2881 + * with this program; if not, write to the Free Software Foundation, Inc.,
2882 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2883 + *
2884 + *
2885 + **************************************************************************
2886 + * May 2004 P. Sadik.
2887 + *
2888 + * Initial Release
2889 + *
2890 + *
2891 + *
2892 + **************************************************************************
2893 + */
2894 +
2895 +
2896 +#ifndef __IDT_RC32334_H__
2897 +#define __IDT_RC32334_H__
2898 +
2899 +#include <linux/delay.h>
2900 +#include <asm/io.h>
2901 +
2902 +/* Base address of internal registers */
2903 +#define RC32334_REG_BASE 0x18000000
2904 +
2905 +/* CPU and IP Bus Control */
2906 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2907 +#define CPU_BTA 0xffffe204 // virtual!
2908 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2909 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2910 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2911 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2912 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2913 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2914 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2915 +
2916 +/* Memory Controller */
2917 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2918 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2919 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2920 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2921 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2922 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2923 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2924 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2925 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2926 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2927 +
2928 +/* PCI Controller */
2929 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2930 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2931 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2932 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2933 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2934 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2935 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2936 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2937 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2938 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2939 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2940 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2941 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2942 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2943 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2944 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2945 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2946 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2947 +
2948 +/* Timers */
2949 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2950 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2951 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2952 +#define TIMER_REG_OFFSET 0x10
2953 +
2954 +/* Programmable I/O */
2955 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2956 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2957 +
2958 +/*
2959 + * DMA
2960 + *
2961 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2962 + *
2963 + * DMA0: 18001400
2964 + * DMA1: 18001440
2965 + * DMA2: 18001900
2966 + * DMA3: 18001940
2967 + * NB: dma number must be immediate value or variable.
2968 + * It MUST NOT be a function since it would get called twice!
2969 + */
2970 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2971 +
2972 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2973 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2974 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2975 +
2976 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2977 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2978 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2979 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2980 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2981 +
2982 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2983 +
2984 +/* Expansion Interrupt Controller */
2985 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2986 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2987 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2988 +#define IC_GROUP_OFFSET 0x10
2989 +
2990 +#define NUM_INTR_GROUPS 15
2991 +/*
2992 + * The IRQ mapping is as follows:
2993 + *
2994 + * IRQ Mapped To
2995 + * --- -------------------
2996 + * 0 SW0 (IP0) SW0 intr
2997 + * 1 SW1 (IP1) SW1 intr
2998 + * 2 Int0 (IP2) board-specific
2999 + * 3 Int1 (IP3) board-specific
3000 + * 4 Int2 (IP4) board-specific
3001 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
3002 + * 6 Int4 (IP6) board-specific
3003 + * 7 Int5 (IP7) CP0 Timer
3004 + *
3005 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
3006 + * internally on the RC32334 is routed to the Expansion
3007 + * Interrupt Controller.
3008 + */
3009 +#define MIPS_CPU_TIMER_IRQ 7
3010 +
3011 +#define GROUP1_IRQ_BASE 8 // bus error
3012 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3013 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3014 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3015 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3016 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3017 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3018 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3019 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3020 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3021 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3022 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3023 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3024 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3025 +
3026 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3027 +
3028 +/* 16550 UARTs */
3029 +#ifdef __MIPSEB__
3030 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3031 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3032 +#else
3033 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3034 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3035 +#endif
3036 +
3037 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3038 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3039 +
3040 +#define IDT_CLOCK_MULT 2
3041 +
3042 +/* NVRAM */
3043 +#define NVRAM_BASE 0x12000000
3044 +#define NVRAM_ENVSIZE_OFF 4
3045 +#define NVRAM_ENVSTART_OFF 0x40
3046 +
3047 +/* LCD 4-digit display */
3048 +#define LCD_CLEAR 0x14000400
3049 +#define LCD_DIGIT0 0x1400000f
3050 +#define LCD_DIGIT1 0x14000008
3051 +#define LCD_DIGIT2 0x14000007
3052 +#define LCD_DIGIT3 0x14000003
3053 +
3054 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3055 +#define RC32334_SCC8530_IRQ 2
3056 +#define RC32334_PCI_INTA_IRQ 3
3057 +#define RC32334_PCI_INTB_IRQ 4
3058 +#define RC32334_PCI_INTC_IRQ 6
3059 +#define RC32334_PCI_INTD_IRQ 7
3060 +
3061 +#define RAM_SIZE (32*1024*1024)
3062 +
3063 +#endif // __IDT_RC32334_H__
3064 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3065 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3066 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-06-18 12:44:28.000000000 +0200
3067 @@ -0,0 +1,206 @@
3068 +/**************************************************************************
3069 + *
3070 + * BRIEF MODULE DESCRIPTION
3071 + * DMA controller defines on IDT RC32355
3072 + *
3073 + * Copyright 2004 IDT Inc.
3074 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3075 + *
3076 + *
3077 + * This program is free software; you can redistribute it and/or modify it
3078 + * under the terms of the GNU General Public License as published by the
3079 + * Free Software Foundation; either version 2 of the License, or (at your
3080 + * option) any later version.
3081 + *
3082 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3083 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3084 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3085 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3086 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3087 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3088 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3089 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3090 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3091 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3092 + *
3093 + * You should have received a copy of the GNU General Public License along
3094 + * with this program; if not, write to the Free Software Foundation, Inc.,
3095 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3096 + *
3097 + *
3098 + * May 2004 rkt
3099 + * Initial Release
3100 + *
3101 + **************************************************************************
3102 + */
3103 +
3104 +#ifndef BANYAN_DMA_H
3105 +#define BANYAN_DMA_H
3106 +#include <asm/idt-boards/rc32300/rc32300.h>
3107 +
3108 +/*
3109 + * An image of one RC32355 dma channel registers
3110 + */
3111 +typedef struct {
3112 + u32 dmac;
3113 + u32 dmas;
3114 + u32 dmasm;
3115 + u32 dmadptr;
3116 + u32 dmandptr;
3117 +} rc32355_dma_ch_t;
3118 +
3119 +/*
3120 + * An image of all RC32355 dma channel registers
3121 + */
3122 +typedef struct {
3123 + rc32355_dma_ch_t ch[16];
3124 +} rc32355_dma_regs_t;
3125 +
3126 +
3127 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3128 +
3129 +
3130 +/* DMAC register layout */
3131 +
3132 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3133 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3134 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3135 +
3136 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3137 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3138 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3139 +
3140 +/* DMAS and DMASM register layout */
3141 +
3142 +#define DMAS_F 0x01 /* Finished */
3143 +#define DMAS_D 0x02 /* Done */
3144 +#define DMAS_C 0x04 /* Chain */
3145 +#define DMAS_E 0x08 /* Error */
3146 +#define DMAS_H 0x10 /* Halt */
3147 +
3148 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3149 +#define DMA_HALT_TIMEOUT 500
3150 +
3151 +
3152 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3153 +{
3154 + int timeout=1;
3155 +
3156 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3157 + local_writel(0, &ch->dmac);
3158 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3159 + if (local_readl(&ch->dmas) & DMAS_H) {
3160 + local_writel(0, &ch->dmas);
3161 + break;
3162 + }
3163 + }
3164 + }
3165 +
3166 + return timeout ? 0 : 1;
3167 +}
3168 +
3169 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3170 +{
3171 + local_writel(0, &ch->dmandptr);
3172 + local_writel(dma_addr, &ch->dmadptr);
3173 +}
3174 +
3175 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3176 +{
3177 + local_writel(dma_addr, &ch->dmandptr);
3178 +}
3179 +
3180 +
3181 +/* The following can be used to describe DMA channels 0 to 15, and the */
3182 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3183 +
3184 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3185 +
3186 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3187 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3188 +
3189 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3190 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3191 +
3192 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3193 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3194 +
3195 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3196 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3197 +
3198 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3199 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3200 +#define DMA_DEV_ATMVCC(entry) 0
3201 +
3202 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3203 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3204 +
3205 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3206 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3207 +
3208 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3209 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3210 +
3211 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3212 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3213 +
3214 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3215 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3216 +
3217 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3218 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3219 +
3220 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3221 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3222 +
3223 +#define DMA_CHAN_USBIN 13 /* USB input */
3224 +#define DMA_DEV_USBIN 0 /* USB input */
3225 +
3226 +#define DMA_CHAN_USBOUT 14 /* USB output */
3227 +#define DMA_DEV_USBOUT 0 /* USB output */
3228 +
3229 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3230 +#define DMA_DEV_EXTERN 0 /* External DMA */
3231 +
3232 +/*
3233 + * An RC32355 dma descriptor in system memory
3234 + */
3235 +typedef struct {
3236 + u32 cmdstat; /* control and status */
3237 + u32 curr_addr; /* current address of data */
3238 + u32 devcs; /* peripheral-specific control and status */
3239 + u32 link; /* link to next descriptor */
3240 +} rc32355_dma_desc_t;
3241 +
3242 +/* Values for the descriptor cmdstat word */
3243 +
3244 +#define DMADESC_F 0x80000000u /* Finished bit */
3245 +#define DMADESC_D 0x40000000u /* Done bit */
3246 +#define DMADESC_T 0x20000000u /* Terminated bit */
3247 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3248 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3249 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3250 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3251 +
3252 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3253 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3254 +
3255 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3256 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3257 +
3258 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3259 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3260 +
3261 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3262 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3263 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3264 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3265 +
3266 +#define DMA_DEVCMD(devcmd) \
3267 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3268 +#define DMA_DS(ds) \
3269 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3270 +#define DMA_COUNT(count) \
3271 + ((count) & DMADESC_COUNT_MASK)
3272 +
3273 +#endif /* RC32355_DMA_H */
3274 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3275 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3276 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-06-18 12:44:28.000000000 +0200
3277 @@ -0,0 +1,442 @@
3278 +/**************************************************************************
3279 + *
3280 + * BRIEF MODULE DESCRIPTION
3281 + * Ethernet registers on IDT RC32355
3282 + *
3283 + * Copyright 2004 IDT Inc.
3284 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3285 + *
3286 + *
3287 + * This program is free software; you can redistribute it and/or modify it
3288 + * under the terms of the GNU General Public License as published by the
3289 + * Free Software Foundation; either version 2 of the License, or (at your
3290 + * option) any later version.
3291 + *
3292 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3293 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3294 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3295 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3296 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3297 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3298 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3299 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3300 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3301 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3302 + *
3303 + * You should have received a copy of the GNU General Public License along
3304 + * with this program; if not, write to the Free Software Foundation, Inc.,
3305 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3306 + *
3307 + *
3308 + * May 2004 rkt
3309 + * Initial Release
3310 + *
3311 + **************************************************************************
3312 + */
3313 +
3314 +
3315 +#ifndef RC32355_ETHER_H
3316 +#define RC32355_ETHER_H
3317 +
3318 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3319 +
3320 +/*
3321 + * A partial image of the RC32355 ethernet registers
3322 + */
3323 +typedef struct {
3324 + u32 ethintfc;
3325 + u32 ethfifott;
3326 + u32 etharc;
3327 + u32 ethhash0;
3328 + u32 ethhash1;
3329 + u32 ethfifost;
3330 + u32 ethfifos;
3331 + u32 ethodeops;
3332 + u32 ethis;
3333 + u32 ethos;
3334 + u32 ethmcp;
3335 + u32 _u1;
3336 + u32 ethid;
3337 + u32 _u2;
3338 + u32 _u3;
3339 + u32 _u4;
3340 + u32 ethod;
3341 + u32 _u5;
3342 + u32 _u6;
3343 + u32 _u7;
3344 + u32 ethodeop;
3345 + u32 _u8[43];
3346 + u32 ethsal0;
3347 + u32 ethsah0;
3348 + u32 ethsal1;
3349 + u32 ethsah1;
3350 + u32 ethsal2;
3351 + u32 ethsah2;
3352 + u32 ethsal3;
3353 + u32 ethsah3;
3354 + u32 ethrbc;
3355 + u32 ethrpc;
3356 + u32 ethrupc;
3357 + u32 ethrfc;
3358 + u32 ethtbc;
3359 + u32 ethgpf;
3360 + u32 _u9[50];
3361 + u32 ethmac1;
3362 + u32 ethmac2;
3363 + u32 ethipgt;
3364 + u32 ethipgr;
3365 + u32 ethclrt;
3366 + u32 ethmaxf;
3367 + u32 _u10;
3368 + u32 ethmtest;
3369 + u32 miimcfg;
3370 + u32 miimcmd;
3371 + u32 miimaddr;
3372 + u32 miimwtd;
3373 + u32 miimrdd;
3374 + u32 miimind;
3375 + u32 _u11;
3376 + u32 _u12;
3377 + u32 ethcfsa0;
3378 + u32 ethcfsa1;
3379 + u32 ethcfsa2;
3380 +} rc32355_eth_regs_t;
3381 +
3382 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3383 +
3384 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3385 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3386 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3387 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3388 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3389 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3390 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3391 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3392 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3393 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3394 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3395 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3396 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3397 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3398 +
3399 +/* for n in { 0, 1, 2, 3 } */
3400 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3401 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3402 +
3403 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3404 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3405 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3406 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3407 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3408 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3409 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3410 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3411 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3412 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3413 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3414 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3415 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3416 +
3417 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3418 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3419 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3420 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3421 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3422 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3423 +
3424 +/* for n in { 0, 1, 2 } */
3425 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3426 +
3427 +
3428 +/*
3429 + * Register Interpretations follow
3430 + */
3431 +
3432 +/******************************************************************************
3433 + * ETHINTFC register
3434 + *****************************************************************************/
3435 +
3436 +#define ETHERINTFC_EN (1<<0)
3437 +#define ETHERINTFC_ITS (1<<1)
3438 +#define ETHERINTFC_RES (1<<2)
3439 +#define ETHERINTFC_RIP (1<<2)
3440 +#define ETHERINTFC_JAM (1<<3)
3441 +
3442 +/******************************************************************************
3443 + * ETHFIFOTT register
3444 + *****************************************************************************/
3445 +
3446 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3447 +
3448 +/******************************************************************************
3449 + * ETHARC register
3450 + *****************************************************************************/
3451 +
3452 +#define ETHERARC_PRO (1<<0)
3453 +#define ETHERARC_AM (1<<1)
3454 +#define ETHERARC_AFM (1<<2)
3455 +#define ETHERARC_AB (1<<3)
3456 +
3457 +/******************************************************************************
3458 + * ETHHASH registers
3459 + *****************************************************************************/
3460 +
3461 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3462 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3463 +
3464 +/******************************************************************************
3465 + * ETHSA registers
3466 + *****************************************************************************/
3467 +
3468 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3469 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3470 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3471 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3472 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3473 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3474 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3475 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3476 +
3477 +/******************************************************************************
3478 + * ETHFIFOST register
3479 + *****************************************************************************/
3480 +
3481 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3482 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3483 +
3484 +/******************************************************************************
3485 + * ETHFIFOS register
3486 + *****************************************************************************/
3487 +
3488 +#define ETHERFIFOS_IR (1<<0)
3489 +#define ETHERFIFOS_OR (1<<1)
3490 +#define ETHERFIFOS_OVR (1<<2)
3491 +#define ETHERFIFOS_UND (1<<3)
3492 +
3493 +/******************************************************************************
3494 + * DATA registers
3495 + *****************************************************************************/
3496 +
3497 +#define ETHERID(v) (((v)&0xffff)<<0)
3498 +#define ETHEROD(v) (((v)&0xffff)<<0)
3499 +
3500 +/******************************************************************************
3501 + * ETHODEOPS register
3502 + *****************************************************************************/
3503 +
3504 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3505 +
3506 +/******************************************************************************
3507 + * ETHODEOP register
3508 + *****************************************************************************/
3509 +
3510 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3511 +
3512 +/******************************************************************************
3513 + * ETHIS register
3514 + *****************************************************************************/
3515 +
3516 +#define ETHERIS_EOP (1<<0)
3517 +#define ETHERIS_ROK (1<<2)
3518 +#define ETHERIS_FM (1<<3)
3519 +#define ETHERIS_MP (1<<4)
3520 +#define ETHERIS_BP (1<<5)
3521 +#define ETHERIS_VLT (1<<6)
3522 +#define ETHERIS_CF (1<<7)
3523 +#define ETHERIS_OVR (1<<8)
3524 +#define ETHERIS_CRC (1<<9)
3525 +#define ETHERIS_CV (1<<10)
3526 +#define ETHERIS_DB (1<<11)
3527 +#define ETHERIS_LE (1<<12)
3528 +#define ETHERIS_LOR (1<<13)
3529 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3530 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3531 +
3532 +/******************************************************************************
3533 + * ETHOS register
3534 + *****************************************************************************/
3535 +
3536 +#define ETHEROS_T (1<<0)
3537 +#define ETHEROS_TOK (1<<6)
3538 +#define ETHEROS_MP (1<<7)
3539 +#define ETHEROS_BP (1<<8)
3540 +#define ETHEROS_UND (1<<9)
3541 +#define ETHEROS_OF (1<<10)
3542 +#define ETHEROS_ED (1<<11)
3543 +#define ETHEROS_EC (1<<12)
3544 +#define ETHEROS_LC (1<<13)
3545 +#define ETHEROS_TD (1<<14)
3546 +#define ETHEROS_CRC (1<<15)
3547 +#define ETHEROS_LE (1<<16)
3548 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3549 +#define ETHEROS_PFD (1<<21)
3550 +
3551 +/******************************************************************************
3552 + * Statistics registers
3553 + *****************************************************************************/
3554 +
3555 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3556 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3557 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3558 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3559 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3560 +
3561 +/******************************************************************************
3562 + * ETHGPF register
3563 + *****************************************************************************/
3564 +
3565 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3566 +
3567 +/******************************************************************************
3568 + * MAC registers
3569 + *****************************************************************************/
3570 +//ETHMAC1
3571 +#define ETHERMAC1_RE (1<<0)
3572 +#define ETHERMAC1_PAF (1<<1)
3573 +#define ETHERMAC1_RFC (1<<2)
3574 +#define ETHERMAC1_TFC (1<<3)
3575 +#define ETHERMAC1_LB (1<<4)
3576 +#define ETHERMAC1_MR (1<<15)
3577 +
3578 +//ETHMAC2
3579 +#define ETHERMAC2_FD (1<<0)
3580 +#define ETHERMAC2_FLC (1<<1)
3581 +#define ETHERMAC2_HFE (1<<2)
3582 +#define ETHERMAC2_DC (1<<3)
3583 +#define ETHERMAC2_CEN (1<<4)
3584 +#define ETHERMAC2_PE (1<<5)
3585 +#define ETHERMAC2_VPE (1<<6)
3586 +#define ETHERMAC2_APE (1<<7)
3587 +#define ETHERMAC2_PPE (1<<8)
3588 +#define ETHERMAC2_LPE (1<<9)
3589 +#define ETHERMAC2_NB (1<<12)
3590 +#define ETHERMAC2_BP (1<<13)
3591 +#define ETHERMAC2_ED (1<<14)
3592 +
3593 +//ETHIPGT
3594 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
3595 +
3596 +//ETHIPGR
3597 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
3598 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
3599 +
3600 +//ETHCLRT
3601 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
3602 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
3603 +
3604 +//ETHMAXF
3605 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
3606 +
3607 +//ETHMTEST
3608 +#define ETHERMTEST_TB (1<<2)
3609 +
3610 +//ETHMCP
3611 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
3612 +
3613 +//MIIMCFG
3614 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
3615 +#define ETHERMIIMCFG_R (1<<15)
3616 +
3617 +//MIIMCMD
3618 +#define ETHERMIIMCMD_RD (1<<0)
3619 +#define ETHERMIIMCMD_SCN (1<<1)
3620 +
3621 +//MIIMADDR
3622 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
3623 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
3624 +
3625 +//MIIMWTD
3626 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
3627 +
3628 +//MIIMRDD
3629 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
3630 +
3631 +//MIIMIND
3632 +#define ETHERMIIMIND_BSY (1<<0)
3633 +#define ETHERMIIMIND_SCN (1<<1)
3634 +#define ETHERMIIMIND_NV (1<<2)
3635 +
3636 +//DMA DEVCS IN
3637 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
3638 +#define ETHERDMA_IN_CES (1<<14)
3639 +#define ETHERDMA_IN_LOR (1<<13)
3640 +#define ETHERDMA_IN_LE (1<<12)
3641 +#define ETHERDMA_IN_DB (1<<11)
3642 +#define ETHERDMA_IN_CV (1<<10)
3643 +#define ETHERDMA_IN_CRC (1<<9)
3644 +#define ETHERDMA_IN_OVR (1<<8)
3645 +#define ETHERDMA_IN_CF (1<<7)
3646 +#define ETHERDMA_IN_VLT (1<<6)
3647 +#define ETHERDMA_IN_BP (1<<5)
3648 +#define ETHERDMA_IN_MP (1<<4)
3649 +#define ETHERDMA_IN_FM (1<<3)
3650 +#define ETHERDMA_IN_ROK (1<<2)
3651 +#define ETHERDMA_IN_LD (1<<1)
3652 +#define ETHERDMA_IN_FD (1<<0)
3653 +
3654 +//DMA DEVCS OUT
3655 +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
3656 +#define ETHERDMA_OUT_CNT 0x001e0000
3657 +#define ETHERDMA_OUT_SHFT 17
3658 +#define ETHERDMA_OUT_LE (1<<16)
3659 +
3660 +#define ETHERDMA_OUT_CRC (1<<15)
3661 +#define ETHERDMA_OUT_TD (1<<14)
3662 +#define ETHERDMA_OUT_LC (1<<13)
3663 +#define ETHERDMA_OUT_EC (1<<12)
3664 +#define ETHERDMA_OUT_ED (1<<11)
3665 +#define ETHERDMA_OUT_OF (1<<10)
3666 +#define ETHERDMA_OUT_UND (1<<9)
3667 +#define ETHERDMA_OUT_BP (1<<8)
3668 +#define ETHERDMA_OUT_MP (1<<7)
3669 +#define ETHERDMA_OUT_TOK (1<<6)
3670 +#define ETHERDMA_OUT_HEN (1<<5)
3671 +#define ETHERDMA_OUT_CEN (1<<4)
3672 +#define ETHERDMA_OUT_PEN (1<<3)
3673 +#define ETHERDMA_OUT_OEN (1<<2)
3674 +#define ETHERDMA_OUT_LD (1<<1)
3675 +#define ETHERDMA_OUT_FD (1<<0)
3676 +
3677 +#define RCV_ERRS \
3678 + (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3679 +#define TX_ERRS \
3680 + (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3681 + ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3682 +
3683 +#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
3684 +#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
3685 +#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
3686 +#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
3687 +#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
3688 +#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
3689 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
3690 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
3691 +#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
3692 +#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
3693 +#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
3694 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
3695 + Range */
3696 +#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
3697 +#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
3698 + received packet */
3699 +
3700 +#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
3701 +#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
3702 +
3703 +#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
3704 +#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
3705 + Underflow */
3706 +#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
3707 +#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
3708 + deferral */
3709 +#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
3710 + collisions */
3711 +#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
3712 +#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
3713 +#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
3714 +#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
3715 +
3716 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
3717 +
3718 +#endif /* RC32355_ETHER_H */
3719 +
3720 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3721 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h 1970-01-01 01:00:00.000000000 +0100
3722 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h 2006-06-18 12:44:28.000000000 +0200
3723 @@ -0,0 +1,177 @@
3724 +/**************************************************************************
3725 + *
3726 + * BRIEF MODULE DESCRIPTION
3727 + * Definitions for IDT RC32355 CPU.
3728 + *
3729 + * Copyright 2004 IDT Inc.
3730 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3731 + *
3732 + *
3733 + * This program is free software; you can redistribute it and/or modify it
3734 + * under the terms of the GNU General Public License as published by the
3735 + * Free Software Foundation; either version 2 of the License, or (at your
3736 + * option) any later version.
3737 + *
3738 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3739 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3740 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3741 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3742 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3743 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3744 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3745 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3746 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3747 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3748 + *
3749 + * You should have received a copy of the GNU General Public License along
3750 + * with this program; if not, write to the Free Software Foundation, Inc.,
3751 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3752 + *
3753 + *
3754 + * May 2004 rkt
3755 + * Initial Release
3756 + *
3757 + **************************************************************************
3758 + */
3759 +
3760 +
3761 +#ifndef _RC32355_H_
3762 +#define _RC32355_H_
3763 +
3764 +#include <linux/delay.h>
3765 +#include <asm/io.h>
3766 +
3767 +/* Base address of internal registers */
3768 +#define RC32355_REG_BASE 0x18000000
3769 +
3770 +/* System ID Registers */
3771 +#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
3772 +#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
3773 +#define CPU_REV (RC32355_REG_BASE + 0x0002c)
3774 +
3775 +/* Reset Controller */
3776 +#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
3777 +
3778 +/* Device Controller */
3779 +#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
3780 +#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
3781 +#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
3782 +#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
3783 +#define DEV_REG_OFFSET 0x10
3784 +
3785 +/* SDRAM Controller */
3786 +#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
3787 +#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
3788 +#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
3789 +#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
3790 +#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
3791 +
3792 +/* Bus Arbiter */
3793 +#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
3794 +#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
3795 +
3796 +/* Counters/Timers */
3797 +#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
3798 +#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
3799 +#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
3800 +#define TIMER_REG_OFFSET 0x0C
3801 +
3802 +/* System Integrity */
3803 +
3804 +/* Interrupt Controller */
3805 +#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
3806 +#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
3807 +#define IC_GROUP_OFFSET 0x08
3808 +
3809 +#define NUM_INTR_GROUPS 5
3810 +/*
3811 + * The IRQ mapping is as follows:
3812 + *
3813 + * IRQ Mapped To
3814 + * --- -------------------
3815 + * 0 SW0 (IP0) SW0 intr
3816 + * 1 SW1 (IP1) SW1 intr
3817 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
3818 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
3819 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
3820 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
3821 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
3822 + * 7 Int5 (IP7) CP0 Timer
3823 + *
3824 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3825 + * internally on the RC32355 is routed to the Expansion
3826 + * Interrupt Controller.
3827 + */
3828 +#define MIPS_CPU_TIMER_IRQ 7
3829 +
3830 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
3831 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
3832 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // ATM
3833 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3834 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
3835 +
3836 +#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
3837 +
3838 +/* DMA - see rc32355_dma.h for full list of registers */
3839 +
3840 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3841 +#define DMA_CHAN_OFFSET 0x14
3842 +
3843 +/* GPIO Controller */
3844 +
3845 +/* TDM Bus */
3846 +
3847 +/* 16550 UARTs */
3848 +#ifdef __MIPSEB__
3849 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3850 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3851 +#else
3852 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3853 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3854 +#endif
3855 +
3856 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 14)
3857 +#define RC32300_UART1_IRQ (GROUP3_IRQ_BASE + 17)
3858 +
3859 +/* ATM */
3860 +
3861 +/* Ethernet - see rc32355_eth.h for full list of registers */
3862 +
3863 +#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
3864 +
3865 +
3866 +#define IDT_CLOCK_MULT 2
3867 +
3868 +/* Memory map of 79EB355 board */
3869 +
3870 +/* DRAM */
3871 +#define RAM_BASE 0x00000000
3872 +#define RAM_SIZE (32*1024*1024)
3873 +
3874 +/* SRAM (device 1) */
3875 +#define SRAM_BASE 0x02000000
3876 +#define SRAM_SIZE 0x00100000
3877 +
3878 +/* FLASH (device 2) */
3879 +#define FLASH_BASE 0x0C000000
3880 +#define FLASH_SIZE 0x00C00000
3881 +
3882 +/* ATM PHY (device 4) */
3883 +#define ATM_PHY_BASE 0x14000000
3884 +
3885 +/* TDM switch (device 3) */
3886 +#define TDM_BASE 0x1A000000
3887 +
3888 +/* LCD panel (device 3) */
3889 +#define LCD_BASE 0x1A002000
3890 +
3891 +/* RTC (DS1511W) (device 3) */
3892 +#define RTC_BASE 0x1A004000
3893 +
3894 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3895 +#define NVRAM_ADDR RTC_BASE + 0x10
3896 +#define NVRAM_DATA RTC_BASE + 0x13
3897 +#define NVRAM_ENVSIZE_OFF 4
3898 +#define NVRAM_ENVSTART_OFF 32
3899 +
3900 +#endif /* _RC32355_H_ */
3901 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3902 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 1970-01-01 01:00:00.000000000 +0100
3903 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-06-18 12:44:28.000000000 +0200
3904 @@ -0,0 +1,226 @@
3905 +/**************************************************************************
3906 + *
3907 + * BRIEF MODULE DESCRIPTION
3908 + * RC32365/336 DMA hardware abstraction.
3909 + *
3910 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3911 + *
3912 + * This program is free software; you can redistribute it and/or modify it
3913 + * under the terms of the GNU General Public License as published by the
3914 + * Free Software Foundation; either version 2 of the License, or (at your
3915 + * option) any later version.
3916 + *
3917 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3918 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3919 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3920 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3921 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3922 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3923 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3924 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3925 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3926 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3927 + *
3928 + * You should have received a copy of the GNU General Public License along
3929 + * with this program; if not, write to the Free Software Foundation, Inc.,
3930 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3931 + *
3932 + *
3933 + **************************************************************************
3934 + * May 2004 P. Sadik.
3935 + *
3936 + * Initial Release
3937 + *
3938 + *
3939 + *
3940 + **************************************************************************
3941 + */
3942 +
3943 +#ifndef __IDT_RC32365_DMA_H__
3944 +#define __IDT_RC32365_DMA_H__
3945 +
3946 +enum
3947 +{
3948 + DMA0_PhysicalAddress = 0x18038000,
3949 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
3950 +
3951 + DMA0_VirtualAddress = 0xb8038000,
3952 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
3953 +} ;
3954 +
3955 +/*
3956 + * DMA descriptor (in physical memory).
3957 + */
3958 +
3959 +typedef struct DMAD_s
3960 +{
3961 + u32 control ; // Control. use DMAD_*
3962 + u32 ca ; // Current Address.
3963 + u32 devcs ; // Device control and status.
3964 + u32 link ; // Next descriptor in chain.
3965 +} volatile *DMAD_t ;
3966 +
3967 +enum
3968 +{
3969 + DMAD_size = sizeof (struct DMAD_s),
3970 + DMAD_count_b = 0, // in DMAD_t -> control
3971 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
3972 + DMAD_ds_b = 20, // in DMAD_t -> control
3973 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
3974 + DMAD_ds_extToMem0_v = 0,
3975 + DMAD_ds_memToExt0_v = 1,
3976 + DMAD_ds_extToMem1_v = 0,
3977 + DMAD_ds_memToExt1_v = 1,
3978 + DMAD_ds_ethRcv0_v = 0,
3979 + DMAD_ds_ethXmt0_v = 0,
3980 + DMAD_ds_ethRcv1_v = 0,
3981 + DMAD_ds_ethXmt2_v = 0,
3982 + DMAD_ds_memToFifo_v = 0,
3983 + DMAD_ds_fifoToMem_v = 0,
3984 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
3985 + DMAD_ds_pciToMem_v = 0,
3986 + DMAD_ds_memToPci_v = 0,
3987 + DMAD_ds_securityInput_v = 0,
3988 + DMAD_ds_securityOutput_v = 0,
3989 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
3990 +
3991 + DMAD_devcmd_b = 22, // in DMAD_t -> control
3992 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
3993 + DMAD_devcmd_byte_v = 0, //memory-to-memory
3994 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
3995 + DMAD_devcmd_word_v = 2, //memory-to-memory
3996 + DMAD_devcmd_2words_v = 3, //memory-to-memory
3997 + DMAD_devcmd_4words_v = 4, //memory-to-memory
3998 + DMAD_devcmd_6words_v = 5, //memory-to-memory
3999 + DMAD_devcmd_8words_v = 6, //memory-to-memory
4000 + DMAD_devcmd_16words_v = 7, //memory-to-memory
4001 + DMAD_cof_b = 25, // chain on finished
4002 + DMAD_cof_m = 0x02000000, //
4003 + DMAD_cod_b = 26, // chain on done
4004 + DMAD_cod_m = 0x04000000, //
4005 + DMAD_iof_b = 27, // interrupt on finished
4006 + DMAD_iof_m = 0x08000000, //
4007 + DMAD_iod_b = 28, // interrupt on done
4008 + DMAD_iod_m = 0x10000000, //
4009 + DMAD_t_b = 29, // terminated
4010 + DMAD_t_m = 0x20000000, //
4011 + DMAD_d_b = 30, // done
4012 + DMAD_d_m = 0x40000000, //
4013 + DMAD_f_b = 31, // finished
4014 + DMAD_f_m = 0x80000000, //
4015 +} ;
4016 +
4017 +/*
4018 + * DMA register (within Internal Register Map).
4019 + */
4020 +
4021 +struct DMA_Chan_s
4022 +{
4023 + u32 dmac ; // Control.
4024 + u32 dmas ; // Status.
4025 + u32 dmasm ; // Mask.
4026 + u32 dmadptr ; // Descriptor pointer.
4027 + u32 dmandptr ; // Next descriptor pointer.
4028 +};
4029 +
4030 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
4031 +
4032 +//DMA_Channels use DMACH_count instead
4033 +
4034 +enum
4035 +{
4036 + DMAC_run_b = 0, //
4037 + DMAC_run_m = 0x00000001, //
4038 + DMAC_dm_b = 1, // done mask
4039 + DMAC_dm_m = 0x00000002, //
4040 + DMAC_mode_b = 2, //
4041 + DMAC_mode_m = 0x0000000c, //
4042 + DMAC_mode_auto_v = 0,
4043 + DMAC_mode_burst_v = 1,
4044 + DMAC_mode_transfer_v = 2, //usually used
4045 + DMAC_mode_reserved_v = 3,
4046 + DMAC_a_b = 4, //
4047 + DMAC_a_m = 0x00000010, //
4048 +
4049 + DMAS_f_b = 0, // finished (sticky)
4050 + DMAS_f_m = 0x00000001, //
4051 + DMAS_d_b = 1, // done (sticky)
4052 + DMAS_d_m = 0x00000002, //
4053 + DMAS_c_b = 2, // chain (sticky)
4054 + DMAS_c_m = 0x00000004, //
4055 + DMAS_e_b = 3, // error (sticky)
4056 + DMAS_e_m = 0x00000008, //
4057 + DMAS_h_b = 4, // halt (sticky)
4058 + DMAS_h_m = 0x00000010, //
4059 +
4060 + DMASM_f_b = 0, // finished (1=mask)
4061 + DMASM_f_m = 0x00000001, //
4062 + DMASM_d_b = 1, // done (1=mask)
4063 + DMASM_d_m = 0x00000002, //
4064 + DMASM_c_b = 2, // chain (1=mask)
4065 + DMASM_c_m = 0x00000004, //
4066 + DMASM_e_b = 3, // error (1=mask)
4067 + DMASM_e_m = 0x00000008, //
4068 + DMASM_h_b = 4, // halt (1=mask)
4069 + DMASM_h_m = 0x00000010, //
4070 +} ;
4071 +
4072 +/*
4073 + * DMA channel definitions
4074 + */
4075 +
4076 +enum
4077 +{
4078 + DMACH_ethRcv0 = 0,
4079 + DMACH_ethXmt0 = 1,
4080 + DMACH_ethRcv1 = 2,
4081 + DMACH_ethXmt2 = 3,
4082 + DMACH_pciToMem = 4,
4083 + DMACH_memToPci = 5,
4084 + DMACH_securityInput = 6,
4085 + DMACH_securityOutput = 7,
4086 + DMACH_rng = 8,
4087 +
4088 + DMACH_count //must be last
4089 +};
4090 +
4091 +
4092 +typedef struct DMAC_s
4093 +{
4094 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4095 +} volatile *DMA_t ;
4096 +
4097 +
4098 +/*
4099 + * External DMA parameters
4100 +*/
4101 +
4102 +enum
4103 +{
4104 + DMADEVCMD_ts_b = 0, // ts field in devcmd
4105 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
4106 + DMADEVCMD_ts_byte_v = 0,
4107 + DMADEVCMD_ts_halfword_v = 1,
4108 + DMADEVCMD_ts_word_v = 2,
4109 + DMADEVCMD_ts_2word_v = 3,
4110 + DMADEVCMD_ts_4word_v = 4,
4111 + DMADEVCMD_ts_6word_v = 5,
4112 + DMADEVCMD_ts_8word_v = 6,
4113 + DMADEVCMD_ts_16word_v = 7
4114 +};
4115 +
4116 +
4117 +#if 1 // aws - Compatibility.
4118 +# define EXTDMA_ts_b DMADEVCMD_ts_b
4119 +# define EXTDMA_ts_m DMADEVCMD_ts_m
4120 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
4121 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
4122 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
4123 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
4124 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
4125 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
4126 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
4127 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
4128 +#endif // aws - Compatibility.
4129 +
4130 +#endif // __IDT_RC32365_DMA_H__
4131 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4132 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 1970-01-01 01:00:00.000000000 +0100
4133 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 2006-06-18 12:44:28.000000000 +0200
4134 @@ -0,0 +1,86 @@
4135 +/**************************************************************************
4136 + *
4137 + * BRIEF MODULE DESCRIPTION
4138 + * RC32365/336 DMA interface routines.
4139 + *
4140 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4141 + *
4142 + * This program is free software; you can redistribute it and/or modify it
4143 + * under the terms of the GNU General Public License as published by the
4144 + * Free Software Foundation; either version 2 of the License, or (at your
4145 + * option) any later version.
4146 + *
4147 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4148 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4149 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4150 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4151 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4152 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4153 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4154 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4155 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4156 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4157 + *
4158 + * You should have received a copy of the GNU General Public License along
4159 + * with this program; if not, write to the Free Software Foundation, Inc.,
4160 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4161 + *
4162 + *
4163 + **************************************************************************
4164 + * May 2004 P. Sadik.
4165 + *
4166 + * Initial Release
4167 + *
4168 + *
4169 + *
4170 + **************************************************************************
4171 + */
4172 +
4173 +#ifndef __IDT_RC32365_DMA_V_H__
4174 +#define __IDT_RC32365_DMA_V_H__
4175 +
4176 +
4177 +#include <asm/idt-boards/rc32300/rc32300.h>
4178 +#include <asm/idt-boards/rc32300/rc32365_dma.h>
4179 +#include <asm/idt-boards/rc32300/rc32365.h>
4180 +
4181 +#define DMA_CHAN_OFFSET 0x14
4182 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4183 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
4184 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
4185 +
4186 +#define DMA_COUNT(count) \
4187 + ((count) & DMAD_count_m)
4188 +
4189 +#define DMA_HALT_TIMEOUT 500
4190 +
4191 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4192 +{
4193 + int timeout=1;
4194 + if (local_readl(&ch->dmac) & DMAC_run_m) {
4195 + local_writel(0, &ch->dmac);
4196 +
4197 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4198 + if (local_readl(&ch->dmas) & DMAS_h_m) {
4199 + local_writel(0, &ch->dmas);
4200 + break;
4201 + }
4202 + }
4203 +
4204 + }
4205 +
4206 + return timeout ? 0 : 1;
4207 +}
4208 +
4209 +
4210 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
4211 +{
4212 + local_writel(0, &ch->dmandptr);
4213 + local_writel(dma_addr, &ch->dmadptr);
4214 +}
4215 +
4216 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
4217 +{
4218 + local_writel(dma_addr, &ch->dmandptr);
4219 +}
4220 +#endif //__IDT_RC32365_DMA_V_H__
4221 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
4222 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 1970-01-01 01:00:00.000000000 +0100
4223 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-06-18 12:44:28.000000000 +0200
4224 @@ -0,0 +1,344 @@
4225 +/**************************************************************************
4226 + *
4227 + * BRIEF MODULE DESCRIPTION
4228 + * RC32365/336 Ethernet hardware abstraction.
4229 + *
4230 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4231 + *
4232 + * This program is free software; you can redistribute it and/or modify it
4233 + * under the terms of the GNU General Public License as published by the
4234 + * Free Software Foundation; either version 2 of the License, or (at your
4235 + * option) any later version.
4236 + *
4237 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4238 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4239 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4240 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4241 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4242 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4243 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4244 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4245 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4246 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4247 + *
4248 + * You should have received a copy of the GNU General Public License along
4249 + * with this program; if not, write to the Free Software Foundation, Inc.,
4250 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4251 + *
4252 + *
4253 + **************************************************************************
4254 + * May 2004 P. Sadik.
4255 + *
4256 + * Initial Release
4257 + *
4258 + *
4259 + *
4260 + **************************************************************************
4261 + */
4262 +
4263 +#ifndef __IDT_RC32365_ETH_H__
4264 +#define __IDT_RC32365_ETH_H__
4265 +
4266 +enum
4267 +{
4268 + ETH0_PhysicalAddress = 0x18058000,
4269 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
4270 + ETH0_VirtualAddress = 0xb8058000,
4271 +
4272 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
4273 +
4274 + ETH1_PhysicalAddress = 0x18060000,
4275 + ETH1_VirtualAddress = 0xb8060000, // Default
4276 +} ;
4277 +
4278 +typedef struct
4279 +{
4280 + u32 ethintfc ;
4281 + u32 ethfifott ;
4282 + u32 etharc ;
4283 + u32 ethhash0 ;
4284 + u32 ethhash1 ;
4285 + u32 ethu0 [4] ; // Reserved.
4286 + u32 ethpfs ;
4287 + u32 ethmcp ;
4288 + u32 eth_u1 [10] ; // Reserved.
4289 + u32 ethspare ;
4290 + u32 eth_u2 [42] ; // Reserved.
4291 + u32 ethsal0 ;
4292 + u32 ethsah0 ;
4293 + u32 ethsal1 ;
4294 + u32 ethsah1 ;
4295 + u32 ethsal2 ;
4296 + u32 ethsah2 ;
4297 + u32 ethsal3 ;
4298 + u32 ethsah3 ;
4299 + u32 ethrbc ;
4300 + u32 ethrpc ;
4301 + u32 ethrupc ;
4302 + u32 ethrfc ;
4303 + u32 ethtbc ;
4304 + u32 ethgpf ;
4305 + u32 eth_u9 [50] ; // Reserved.
4306 + u32 ethmac1 ;
4307 + u32 ethmac2 ;
4308 + u32 ethipgt ;
4309 + u32 ethipgr ;
4310 + u32 ethclrt ;
4311 + u32 ethmaxf ;
4312 + u32 eth_u10 ; // Reserved.
4313 + u32 ethmtest ;
4314 + u32 miimcfg ;
4315 + u32 miimcmd ;
4316 + u32 miimaddr ;
4317 + u32 miimwtd ;
4318 + u32 miimrdd ;
4319 + u32 miimind ;
4320 + u32 eth_u11 ; // Reserved.
4321 + u32 eth_u12 ; // Reserved.
4322 + u32 ethcfsa0 ;
4323 + u32 ethcfsa1 ;
4324 + u32 ethcfsa2 ;
4325 +} volatile *ETH_t;
4326 +
4327 +enum
4328 +{
4329 + ETHINTFC_en_b = 0,