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fix compile error
[openwrt/openwrt.git] / openwrt / target / linux / rb532-2.6 / patches / 100-rb5xx_support.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
3 +++ linux.dev/arch/mips/Kconfig 2006-10-11 21:56:38.000000000 +0200
4 @@ -742,6 +742,19 @@
5 select SYS_SUPPORTS_BIG_ENDIAN
6 select TOSHIBA_BOARDS
7
8 +config MIKROTIK_RB500
9 + bool "Support for RB5xx boards"
10 + select HW_HAS_PCI
11 + select IRQ_CPU
12 + select SYS_HAS_CPU_MIPS32_R1
13 + select SYS_SUPPORTS_LITTLE_ENDIAN
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SWAP_IO_SPACE
16 + select DMA_NONCOHERENT
17 + help
18 + Support the Mikrotik(tm) Routerboard 500 series,
19 + such as the RB532.
20 +
21 config TOSHIBA_RBTX4927
22 bool "Toshiba TBTX49[23]7 board"
23 select DMA_NONCOHERENT
24 @@ -1028,7 +1041,7 @@
25
26 config MIPS_L1_CACHE_SHIFT
27 int
28 - default "4" if MACH_DECSTATION
29 + default "4" if MACH_DECSTATION || MIKROTIK_RB500
30 default "7" if SGI_IP27
31 default "5"
32
33 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
34 --- linux.old/arch/mips/Makefile 2006-10-11 21:55:59.000000000 +0200
35 +++ linux.dev/arch/mips/Makefile 2006-10-11 21:56:38.000000000 +0200
36 @@ -580,6 +580,13 @@
37 load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
38
39 #
40 +# Routerboard 532 board
41 +#
42 +core-$(CONFIG_MIKROTIK_RB500) += arch/mips/rb500/
43 +cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
44 +load-$(CONFIG_MIKROTIK_RB500) += 0xffffffff80101000
45 +
46 +#
47 # Toshiba RBTX4927 board or
48 # Toshiba RBTX4937 board
49 #
50 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
51 --- linux.old/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200
52 +++ linux.dev/arch/mips/mm/tlbex.c 2006-10-11 21:56:38.000000000 +0200
53 @@ -876,7 +876,6 @@
54 case CPU_R10000:
55 case CPU_R12000:
56 case CPU_R14000:
57 - case CPU_4KC:
58 case CPU_SB1:
59 case CPU_SB1A:
60 case CPU_4KSC:
61 @@ -904,6 +903,7 @@
62 tlbw(p);
63 break;
64
65 + case CPU_4KC:
66 case CPU_4KEC:
67 case CPU_24K:
68 case CPU_34K:
69 diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c
70 --- linux.old/arch/mips/pci/fixup-rb500.c 1970-01-01 01:00:00.000000000 +0100
71 +++ linux.dev/arch/mips/pci/fixup-rb500.c 2006-10-11 21:56:38.000000000 +0200
72 @@ -0,0 +1,49 @@
73 +/*
74 + * Copyright 2001 MontaVista Software Inc.
75 + * Author: MontaVista Software, Inc.
76 + * stevel@mvista.com or source@mvista.com
77 + *
78 + * This program is free software; you can redistribute it and/or modify it
79 + * under the terms of the GNU General Public License as published by the
80 + * Free Software Foundation; either version 2 of the License, or (at your
81 + * option) any later version.
82 + *
83 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
84 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
85 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
86 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
87 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
88 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
89 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
90 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
91 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
92 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
93 + *
94 + * You should have received a copy of the GNU General Public License along
95 + * with this program; if not, write to the Free Software Foundation, Inc.,
96 + * 675 Mass Ave, Cambridge, MA 02139, USA.
97 + */
98 +
99 +#include <linux/config.h>
100 +#include <linux/types.h>
101 +#include <linux/pci.h>
102 +#include <linux/kernel.h>
103 +#include <linux/init.h>
104 +
105 +#include <asm/rc32434/rc32434.h>
106 +
107 +static int __devinitdata irq_map[2][12] = {
108 + { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
109 + { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
110 +};
111 +
112 +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
113 +{
114 + int irq = 0;
115 +
116 + if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
117 + irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
118 + }
119 + return irq + GROUP4_IRQ_BASE + 4;
120 +}
121 +
122 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
123 --- linux.old/arch/mips/pci/Makefile 2006-06-18 03:49:35.000000000 +0200
124 +++ linux.dev/arch/mips/pci/Makefile 2006-10-11 21:56:38.000000000 +0200
125 @@ -57,3 +57,4 @@
126 obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o
127 obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
128 obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
129 +obj-$(CONFIG_MIKROTIK_RB500) += pci-rc32434.o ops-rc32434.o fixup-rb500.o
130 diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c
131 --- linux.old/arch/mips/pci/ops-rc32434.c 1970-01-01 01:00:00.000000000 +0100
132 +++ linux.dev/arch/mips/pci/ops-rc32434.c 2006-10-11 21:56:38.000000000 +0200
133 @@ -0,0 +1,195 @@
134 +/**************************************************************************
135 + *
136 + * BRIEF MODULE DESCRIPTION
137 + * pci_ops for IDT EB434 board
138 + *
139 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
140 + *
141 + * This program is free software; you can redistribute it and/or modify it
142 + * under the terms of the GNU General Public License as published by the
143 + * Free Software Foundation; either version 2 of the License, or (at your
144 + * option) any later version.
145 + *
146 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
147 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
148 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
149 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
150 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
151 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
152 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
153 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
154 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
155 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
156 + *
157 + * You should have received a copy of the GNU General Public License along
158 + * with this program; if not, write to the Free Software Foundation, Inc.,
159 + * 675 Mass Ave, Cambridge, MA 02139, USA.
160 + *
161 + *
162 + **************************************************************************
163 + * May 2004 rkt, neb
164 + *
165 + * Initial Release
166 + *
167 + *
168 + *
169 + **************************************************************************
170 + */
171 +
172 +#include <linux/config.h>
173 +#include <linux/init.h>
174 +#include <linux/pci.h>
175 +#include <linux/types.h>
176 +#include <linux/delay.h>
177 +
178 +#include <asm/cpu.h>
179 +#include <asm/io.h>
180 +
181 +#include <asm/rc32434/rc32434.h>
182 +#include <asm/rc32434/pci.h>
183 +
184 +#define PCI_ACCESS_READ 0
185 +#define PCI_ACCESS_WRITE 1
186 +
187 +
188 +#define PCI_CFG_SET(bus,slot,func,off) \
189 + (rc32434_pci->pcicfga = (0x80000000 | \
190 + ((bus) << 16) | ((slot)<<11) | \
191 + ((func)<<8) | (off)))
192 +
193 +static inline int config_access(unsigned char access_type, struct pci_bus *bus,
194 + unsigned int devfn, unsigned char where,
195 + u32 * data)
196 +{
197 + unsigned int slot = PCI_SLOT(devfn);
198 + u8 func = PCI_FUNC(devfn);
199 +
200 + /* Setup address */
201 + PCI_CFG_SET(bus->number, slot, func, where);
202 + rc32434_sync();
203 +
204 + if (access_type == PCI_ACCESS_WRITE)
205 + rc32434_pci->pcicfgd = *data;
206 + else
207 + *data = rc32434_pci->pcicfgd;
208 +
209 + rc32434_sync();
210 +
211 + return 0;
212 +}
213 +
214 +
215 +/*
216 + * We can't address 8 and 16 bit words directly. Instead we have to
217 + * read/write a 32bit word and mask/modify the data we actually want.
218 + */
219 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
220 + int where, u8 * val)
221 +{
222 + u32 data;
223 + int ret;
224 +
225 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
226 + *val = (data >> ((where & 3) << 3)) & 0xff;
227 + return ret;
228 +}
229 +
230 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
231 + int where, u16 * val)
232 +{
233 + u32 data;
234 + int ret;
235 +
236 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
237 + *val = (data >> ((where & 3) << 3)) & 0xffff;
238 + return ret;
239 +}
240 +
241 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
242 + int where, u32 * val)
243 +{
244 + int ret;
245 +
246 + ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
247 + return ret;
248 +}
249 +
250 +static int
251 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
252 + u8 val)
253 +{
254 + u32 data = 0;
255 +
256 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
257 + return -1;
258 +
259 + data = (data & ~(0xff << ((where & 3) << 3))) |
260 + (val << ((where & 3) << 3));
261 +
262 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
263 + return -1;
264 +
265 + return PCIBIOS_SUCCESSFUL;
266 +}
267 +
268 +
269 +static int
270 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
271 + u16 val)
272 +{
273 + u32 data = 0;
274 +
275 + if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
276 + return -1;
277 +
278 + data = (data & ~(0xffff << ((where & 3) << 3))) |
279 + (val << ((where & 3) << 3));
280 +
281 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
282 + return -1;
283 +
284 +
285 + return PCIBIOS_SUCCESSFUL;
286 +}
287 +
288 +
289 +static int
290 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
291 + u32 val)
292 +{
293 + if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
294 + return -1;
295 +
296 + return PCIBIOS_SUCCESSFUL;
297 +}
298 +
299 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
300 + int where, int size, u32 * val)
301 +{
302 + switch (size) {
303 + case 1:
304 + return read_config_byte(bus, devfn, where, (u8 *) val);
305 + case 2:
306 + return read_config_word(bus, devfn, where, (u16 *) val);
307 + default:
308 + return read_config_dword(bus, devfn, where, val);
309 + }
310 +}
311 +
312 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
313 + int where, int size, u32 val)
314 +{
315 + switch (size) {
316 + case 1:
317 + return write_config_byte(bus, devfn, where, (u8) val);
318 + case 2:
319 + return write_config_word(bus, devfn, where, (u16) val);
320 + default:
321 + return write_config_dword(bus, devfn, where, val);
322 + }
323 +}
324 +
325 +struct pci_ops rc32434_pci_ops = {
326 + .read = pci_config_read,
327 + .write = pci_config_write,
328 +};
329 diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c
330 --- linux.old/arch/mips/pci/pci-rc32434.c 1970-01-01 01:00:00.000000000 +0100
331 +++ linux.dev/arch/mips/pci/pci-rc32434.c 2006-10-11 21:56:38.000000000 +0200
332 @@ -0,0 +1,234 @@
333 +/**************************************************************************
334 + *
335 + * BRIEF MODULE DESCRIPTION
336 + * PCI initialization for IDT EB434 board
337 + *
338 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
339 + *
340 + * This program is free software; you can redistribute it and/or modify it
341 + * under the terms of the GNU General Public License as published by the
342 + * Free Software Foundation; either version 2 of the License, or (at your
343 + * option) any later version.
344 + *
345 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
346 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
347 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
348 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
349 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
350 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
351 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
352 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
353 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
354 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
355 + *
356 + * You should have received a copy of the GNU General Public License along
357 + * with this program; if not, write to the Free Software Foundation, Inc.,
358 + * 675 Mass Ave, Cambridge, MA 02139, USA.
359 + *
360 + *
361 + **************************************************************************
362 + * May 2004 rkt, neb
363 + *
364 + * Initial Release
365 + *
366 + *
367 + *
368 + **************************************************************************
369 + */
370 +
371 +#include <linux/config.h>
372 +#include <linux/types.h>
373 +#include <linux/pci.h>
374 +#include <linux/kernel.h>
375 +#include <linux/init.h>
376 +
377 +#include <asm/rc32434/rc32434.h>
378 +#include <asm/rc32434/pci.h>
379 +
380 +#define PCI_ACCESS_READ 0
381 +#define PCI_ACCESS_WRITE 1
382 +
383 +/* define an unsigned array for the PCI registers */
384 +unsigned int korinaCnfgRegs[25] = {
385 + KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4,
386 + KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8,
387 + KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
388 + KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
389 + KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
390 + KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
391 +};
392 +static struct resource rc32434_res_pci_mem1;
393 +static struct resource rc32434_res_pci_mem2;
394 +
395 +static struct resource rc32434_res_pci_mem1 = {
396 + .name = "PCI MEM1",
397 + .start = 0x50000000,
398 + .end = 0x5FFFFFFF,
399 + .flags = IORESOURCE_MEM,
400 + .parent = &rc32434_res_pci_mem1,
401 + .sibling = NULL,
402 + .child = &rc32434_res_pci_mem2
403 +};
404 +
405 +static struct resource rc32434_res_pci_mem2 = {
406 + .name = "PCI Mem2",
407 + .start = 0x60000000,
408 + .end = 0x6FFFFFFF,
409 + .flags = IORESOURCE_MEM,
410 + .parent = &rc32434_res_pci_mem1,
411 + .sibling = NULL,
412 + .child = NULL
413 +};
414 +
415 +static struct resource rc32434_res_pci_io1 = {
416 + .name = "PCI I/O1",
417 + .start = 0x18800000,
418 + .end = 0x188FFFFF,
419 + .flags = IORESOURCE_IO,
420 +};
421 +
422 +extern struct pci_ops rc32434_pci_ops;
423 +
424 +#define PCI_MEM1_START PCI_ADDR_START
425 +#define PCI_MEM1_END PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
426 +#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
427 +#define PCI_MEM2_END PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN) - 1
428 +#define PCI_IO1_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
429 +#define PCI_IO1_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
430 +#define PCI_IO2_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
431 +#define PCI_IO2_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
432 +
433 +
434 +struct pci_controller rc32434_controller2;
435 +
436 +struct pci_controller rc32434_controller = {
437 + .pci_ops = &rc32434_pci_ops,
438 + .mem_resource = &rc32434_res_pci_mem1,
439 + .io_resource = &rc32434_res_pci_io1,
440 + .mem_offset = 0,
441 + .io_offset = 0,
442 +
443 +};
444 +
445 +#ifdef __MIPSEB__
446 +#define PCI_ENDIAN_FLAG PCILBAC_sb_m
447 +#else
448 +#define PCI_ENDIAN_FLAG 0
449 +#endif
450 +
451 +static int __init rc32434_pcibridge_init(void)
452 +{
453 + unsigned int pcicValue, pcicData = 0;
454 + unsigned int dummyRead, pciCntlVal;
455 + int loopCount;
456 + unsigned int pciConfigAddr;
457 +
458 + pcicValue = rc32434_pci->pcic;
459 + pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
460 + if (!((pcicValue == PCIM_H_EA) ||
461 + (pcicValue == PCIM_H_IA_FIX) ||
462 + (pcicValue == PCIM_H_IA_RR))) {
463 + printk("PCI init error!!!\n");
464 + /* Not in Host Mode, return ERROR */
465 + return -1;
466 + }
467 + /* Enables the Idle Grant mode, Arbiter Parking */
468 + pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
469 + rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
470 + /* Zero out the PCI status & PCI Status Mask */
471 + for(;;)
472 + {
473 + pcicData = rc32434_pci->pcis;
474 + if (!(pcicData & PCIS_rip_m))
475 + break;
476 + }
477 +
478 + rc32434_pci->pcis = 0;
479 + rc32434_pci->pcism = 0xFFFFFFFF;
480 + /* Zero out the PCI decoupled registers */
481 + rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
482 + rc32434_pci->pcidas=0; /* clear the status */
483 + rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
484 + /* Mask PCI Messaging Interrupts */
485 + rc32434_pci_msg->pciiic = 0;
486 + rc32434_pci_msg->pciiim = 0xFFFFFFFF;
487 + rc32434_pci_msg->pciioic = 0;
488 + rc32434_pci_msg->pciioim = 0;
489 +
490 +
491 + /* Setup PCILB0 as Memory Window */
492 + rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
493 +
494 + /* setup the PCI map address as same as the local address */
495 +
496 + rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
497 +
498 +
499 + /* Setup PCILBA1 as MEM */
500 + rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
501 + dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
502 + rc32434_pci->pcilba[1].a = 0x60000000;
503 + rc32434_pci->pcilba[1].m = 0x60000000;
504 +
505 + /* setup PCILBA2 as IO Window*/
506 + rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
507 + dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
508 + rc32434_pci->pcilba[2].a = 0x18C00000;
509 + rc32434_pci->pcilba[2].m = 0x18FFFFFF;
510 +
511 + /* setup PCILBA2 as IO Window*/
512 + rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
513 + dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
514 +
515 + /* Setup PCILBA3 as IO Window */
516 + rc32434_pci->pcilba[3].a = 0x18800000;
517 + rc32434_pci->pcilba[3].m = 0x18800000;
518 + rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
519 + dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
520 +
521 + pciConfigAddr=(unsigned int)(0x80000004);
522 + for(loopCount=0;loopCount<24;loopCount++){
523 + rc32434_pci->pcicfga=pciConfigAddr;
524 + dummyRead=rc32434_pci->pcicfga;
525 + rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
526 + dummyRead=rc32434_pci->pcicfgd;
527 + pciConfigAddr += 4;
528 + }
529 + rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
530 + | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
531 +
532 + pciCntlVal=rc32434_pci->pcic;
533 + pciCntlVal &=~(PCIC_tnr_m);
534 + rc32434_pci->pcic = pciCntlVal;
535 + pciCntlVal=rc32434_pci->pcic;
536 + return 0;
537 +}
538 +
539 +/* Do platform specific device initialization at pci_enable_device() time */
540 +int pcibios_plat_dev_init(struct pci_dev *dev)
541 +{
542 + if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
543 + /* disable prefetched memory range */
544 + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
545 + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
546 +
547 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
548 + }
549 + return 0;
550 +}
551 +
552 +static int __init rc32434_pci_init(void)
553 +{
554 + printk("PCI: Initializing PCI\n");
555 +
556 + ioport_resource.start = rc32434_res_pci_io1.start;
557 + ioport_resource.end = rc32434_res_pci_io1.end;
558 +
559 + rc32434_pcibridge_init();
560 +
561 + register_pci_controller(&rc32434_controller);
562 + rc32434_sync();
563 +}
564 +
565 +arch_initcall(rc32434_pci_init);
566 +
567 diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c
568 --- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100
569 +++ linux.dev/arch/mips/rb500/devices.c 2006-10-11 21:56:38.000000000 +0200
570 @@ -0,0 +1,211 @@
571 +#include <linux/kernel.h>
572 +#include <linux/init.h>
573 +#include <linux/module.h>
574 +#include <linux/ctype.h>
575 +#include <linux/string.h>
576 +#include <linux/platform_device.h>
577 +#include <asm/unaligned.h>
578 +#include <asm/io.h>
579 +
580 +#include <asm/rc32434/rc32434.h>
581 +#include <asm/rc32434/dma.h>
582 +#include <asm/rc32434/dma_v.h>
583 +#include <asm/rc32434/eth.h>
584 +#include <asm/rc32434/rb.h>
585 +
586 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
587 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
588 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
589 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
590 +
591 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
592 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
593 +
594 +static struct resource korina_dev0_res[] = {
595 + {
596 + .name = "korina_regs",
597 + .start = ETH0_PhysicalAddress,
598 + .end = ETH0_PhysicalAddress + sizeof(ETH_t),
599 + .flags = IORESOURCE_MEM,
600 + },
601 + {
602 + .name = "korina_rx",
603 + .start = ETH0_DMA_RX_IRQ,
604 + .end = ETH0_DMA_RX_IRQ,
605 + .flags = IORESOURCE_IRQ
606 + },
607 + {
608 + .name = "korina_tx",
609 + .start = ETH0_DMA_TX_IRQ,
610 + .end = ETH0_DMA_TX_IRQ,
611 + .flags = IORESOURCE_IRQ
612 + },
613 + {
614 + .name = "korina_ovr",
615 + .start = ETH0_RX_OVR_IRQ,
616 + .end = ETH0_RX_OVR_IRQ,
617 + .flags = IORESOURCE_IRQ
618 + },
619 + {
620 + .name = "korina_und",
621 + .start = ETH0_TX_UND_IRQ,
622 + .end = ETH0_TX_UND_IRQ,
623 + .flags = IORESOURCE_IRQ
624 + },
625 + {
626 + .name = "korina_dma_rx",
627 + .start = ETH0_RX_DMA_ADDR,
628 + .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
629 + .flags = IORESOURCE_MEM,
630 + },
631 + {
632 + .name = "korina_dma_tx",
633 + .start = ETH0_TX_DMA_ADDR,
634 + .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
635 + .flags = IORESOURCE_MEM,
636 + }
637 +};
638 +
639 +static struct korina_device korina_dev0_data = {
640 + .name = "korina0",
641 + .mac = { 0xde, 0xca, 0xff, 0xc0, 0xff, 0xee }
642 +};
643 +
644 +static struct platform_device korina_dev0 = {
645 + .id = 0,
646 + .name = "korina",
647 + .dev.platform_data = &korina_dev0_data,
648 + .resource = korina_dev0_res,
649 + .num_resources = ARRAY_SIZE(korina_dev0_res),
650 +};
651 +
652 +
653 +#define CF_GPIO_NUM 13
654 +
655 +static struct resource cf_slot0_res[] = {
656 + {
657 + .name = "cf_membase",
658 + .flags = IORESOURCE_MEM
659 + },
660 + {
661 + .name = "cf_irq",
662 + .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
663 + .end = (8 + 4 * 32 + CF_GPIO_NUM),
664 + .flags = IORESOURCE_IRQ
665 + }
666 +};
667 +
668 +static struct cf_device cf_slot0_data = {
669 + .gpio_pin = 13
670 +};
671 +
672 +static struct platform_device cf_slot0 = {
673 + .id = 0,
674 + .name = "rb500-cf",
675 + .dev.platform_data = &cf_slot0_data,
676 + .resource = cf_slot0_res,
677 + .num_resources = ARRAY_SIZE(cf_slot0_res),
678 +};
679 +
680 +
681 +
682 +static struct platform_device *rb500_devs[] = {
683 + &korina_dev0,
684 + &cf_slot0
685 +};
686 +
687 +static void __init parse_mac_addr(char* macstr)
688 +{
689 + int i, j;
690 + unsigned char result, value;
691 +
692 + for (i=0; i<6; i++) {
693 + result = 0;
694 + if (i != 5 && *(macstr+2) != ':') {
695 + return;
696 + }
697 + for (j=0; j<2; j++) {
698 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
699 + toupper(*macstr)-'A'+10) < 16) {
700 + result = result*16 + value;
701 + macstr++;
702 + }
703 + else return;
704 + }
705 +
706 + macstr++;
707 + korina_dev0_data.mac[i] = result;
708 + }
709 +}
710 +
711 +
712 +/* DEVICE CONTROLLER 1 */
713 +#define CFG_DC_DEV1 (void*)0xb8010010
714 +#define CFG_DC_DEVBASE 0x0
715 +#define CFG_DC_DEVMASK 0x4
716 +#define CFG_DC_DEVC 0x8
717 +#define CFG_DC_DEVTC 0xC
718 +
719 +
720 +static int __init plat_setup_devices(void)
721 +{
722 + /* Look for the CF card reader */
723 + if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
724 + rb500_devs[1] = NULL;
725 + else {
726 + cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
727 + cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
728 + }
729 +
730 + return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
731 +}
732 +
733 +static int __init setup_kmac(char *s)
734 +{
735 + printk("korina mac = %s\n",s);
736 + parse_mac_addr(s);
737 + return 0;
738 +}
739 +
740 +__setup("kmac=", setup_kmac);
741 +arch_initcall(plat_setup_devices);
742 +
743 +
744 +#if defined(CONFIG_MTD_BLOCK2MTD) && defined(CONFIG_BLK_DEV_CF_MIPS)
745 +extern void block2mtd_setup(char *initstr);
746 +extern void mount_devfs_fs(void);
747 +
748 +static int __init setup_mtd(void)
749 +{
750 + struct hd_struct **part;
751 + int num = 0, i;
752 + char initstr[64];
753 +
754 + if (cf_slot0_data.gd == NULL)
755 + return 0;
756 +
757 + /* count partitions */
758 + part = cf_slot0_data.gd->part;
759 + while (part[num] != NULL) {
760 + num++;
761 + }
762 +
763 + if (num < 2)
764 + return 0;
765 +
766 + mount_devfs_fs();
767 + printk("Setting up block2mtd devices\n");
768 +
769 + block2mtd_setup("/dev/cf/card0/part1,131072,kernel");
770 + block2mtd_setup("/dev/cf/card0/part2,131072,rootfs");
771 +
772 + for (i = 2; part[i]; i++) {
773 + sprintf(initstr, "/dev/cf/card0/part%d,131072,part%d", i + 1, i + 1);
774 + block2mtd_setup(initstr);
775 + }
776 +
777 + return 0;
778 +}
779 +
780 +late_initcall(setup_mtd);
781 +#endif
782 diff -urN linux.old/arch/mips/rb500/early_serial.c linux.dev/arch/mips/rb500/early_serial.c
783 --- linux.old/arch/mips/rb500/early_serial.c 1970-01-01 01:00:00.000000000 +0100
784 +++ linux.dev/arch/mips/rb500/early_serial.c 2006-10-11 21:56:38.000000000 +0200
785 @@ -0,0 +1,199 @@
786 +/**************************************************************************
787 + *
788 + * BRIEF MODULE DESCRIPTION
789 + * EB434 specific polling driver for 16550 UART.
790 + *
791 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
792 + *
793 + * This program is free software; you can redistribute it and/or modify it
794 + * under the terms of the GNU General Public License as published by the
795 + * Free Software Foundation; either version 2 of the License, or (at your
796 + * option) any later version.
797 + *
798 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
799 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
800 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
801 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
802 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
803 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
804 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
805 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
806 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
807 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
808 + *
809 + * You should have received a copy of the GNU General Public License along
810 + * with this program; if not, write to the Free Software Foundation, Inc.,
811 + * 675 Mass Ave, Cambridge, MA 02139, USA.
812 + *
813 + *
814 + **************************************************************************
815 + * Copyright (C) 2000 by Lineo, Inc.
816 + * Written by Quinn Jensen (jensenq@lineo.com)
817 + **************************************************************************
818 + * P. Sadik Oct 20, 2003
819 + *
820 + * DIVISOR is made a function of idt_cpu_freq
821 + **************************************************************************
822 + * P. Sadik Oct 30, 2003
823 + *
824 + * added reset_cons_port
825 + **************************************************************************
826 + */
827 +
828 +#include <linux/serial_reg.h>
829 +
830 +/* turn this on to watch the debug protocol echoed on the console port */
831 +#define DEBUG_REMOTE_DEBUG
832 +
833 +#define CONS_BAUD 115200
834 +
835 +extern unsigned int idt_cpu_freq;
836 +
837 +#define EXT_FREQ 24000000
838 +#define INT_FREQ idt_cpu_freq
839 +
840 +#define EXT_PORT 0xb9800000u
841 +#define EXT_SHIFT 0
842 +
843 +#ifdef __MIPSEB__
844 +#define INT_PORT 0xb8058003u
845 +#else
846 +#define INT_PORT 0xb8058000u
847 +#endif
848 +#define INT_SHIFT 2
849 +
850 +#define INT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14
851 +#define EXT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT
852 +
853 +typedef struct
854 +{
855 + volatile unsigned char *base;
856 + unsigned int shift;
857 + unsigned int freq;
858 + unsigned int fcr;
859 +} ser_port;
860 +
861 +ser_port ports[2] =
862 +{
863 + { (volatile unsigned char *)INT_PORT, INT_SHIFT, 0, INT_FCR},
864 + { (volatile unsigned char *)EXT_PORT, EXT_SHIFT, EXT_FREQ, EXT_FCR}
865 +};
866 +
867 +#define CONS_PORT 0
868 +
869 +void cons_putc(char c);
870 +int port_getc(int port);
871 +void port_putc(int port, char c);
872 +
873 +int cons_getc(void)
874 +{
875 + return port_getc(CONS_PORT);
876 +}
877 +
878 +void cons_putc(char c)
879 +{
880 + port_putc(CONS_PORT, c);
881 +}
882 +
883 +void cons_puts(char *s)
884 +{
885 + while(*s) {
886 + if(*s == '\n') cons_putc('\r');
887 + cons_putc(*s);
888 + s++;
889 + }
890 +}
891 +
892 +void cons_do_putn(int n)
893 +{
894 + if(n) {
895 + cons_do_putn(n / 10);
896 + cons_putc(n % 10 + '0');
897 + }
898 +}
899 +
900 +void cons_putn(int n)
901 +{
902 + if(n < 0) {
903 + cons_putc('-');
904 + n = -n;
905 + }
906 +
907 + if (n == 0) {
908 + cons_putc('0');
909 + } else {
910 + cons_do_putn(n);
911 + }
912 +}
913 +
914 +int port_getc(int p)
915 +{
916 + volatile unsigned char *port = ports[p].base;
917 + int s = ports[p].shift;
918 + int c;
919 +
920 + while((*(port + (UART_LSR << s)) & UART_LSR_DR) == 0) {
921 + continue;
922 + }
923 +
924 + c = *(port + (UART_RX << s));
925 +
926 + return c;
927 +}
928 +
929 +int port_getc_ready(int p)
930 +{
931 + volatile unsigned char *port = ports[p].base;
932 + int s = ports[p].shift;
933 +
934 + return *(port + (UART_LSR << s)) & UART_LSR_DR;
935 +}
936 +
937 +#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE)
938 +
939 +void port_putc(int p, char c)
940 +{
941 + volatile unsigned char *port = ports[p].base;
942 + int s = ports[p].shift;
943 + volatile unsigned char *lsr = port + (UART_LSR << s);
944 +
945 + while((*lsr & OK_TO_XMT) != OK_TO_XMT) {
946 + continue;
947 + }
948 +
949 + *(port + (UART_TX << s)) = c;
950 +}
951 +
952 +void reset_cons_port(void)
953 +{
954 + volatile unsigned char *port = ports[CONS_PORT].base;
955 + unsigned int s = ports[CONS_PORT].shift;
956 + unsigned int DIVISOR;
957 +
958 + if (ports[CONS_PORT].freq)
959 + DIVISOR = (ports[CONS_PORT].freq / 16 / CONS_BAUD);
960 + else
961 + DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD);
962 +
963 + /* reset the port */
964 + *(port + (UART_CSR << s)) = 0;
965 +
966 + /* clear and enable the FIFOs */
967 + *(port + (UART_FCR << s)) = ports[CONS_PORT].fcr;
968 +
969 + /* set the baud rate */
970 + *(port + (UART_LCR << s)) = UART_LCR_DLAB; /* enable DLL, DLM registers */
971 +
972 + *(port + (UART_DLL << s)) = DIVISOR;
973 + *(port + (UART_DLM << s)) = DIVISOR >> 8;
974 + /* set the line control stuff and disable DLL, DLM regs */
975 +
976 + *(port + (UART_LCR << s)) = UART_LCR_STOP | /* 2 stop bits */
977 + UART_LCR_WLEN8; /* 8 bit word length */
978 +
979 + /* leave interrupts off */
980 + *(port + (UART_IER << s)) = 0;
981 +
982 + /* the modem controls don't leave the chip on this port, so leave them alone */
983 + *(port + (UART_MCR << s)) = 0;
984 +}
985 diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c
986 --- linux.old/arch/mips/rb500/irq.c 1970-01-01 01:00:00.000000000 +0100
987 +++ linux.dev/arch/mips/rb500/irq.c 2006-10-11 21:56:38.000000000 +0200
988 @@ -0,0 +1,264 @@
989 +/*
990 + * BRIEF MODULE DESCRIPTION
991 + * RC32434 interrupt routines.
992 + *
993 + * Copyright 2002 MontaVista Software Inc.
994 + * Author: MontaVista Software, Inc.
995 + * stevel@mvista.com or source@mvista.com
996 + *
997 + * This program is free software; you can redistribute it and/or modify it
998 + * under the terms of the GNU General Public License as published by the
999 + * Free Software Foundation; either version 2 of the License, or (at your
1000 + * option) any later version.
1001 + *
1002 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1003 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1004 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1005 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1006 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1007 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1008 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1009 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1010 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1011 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1012 + *
1013 + * You should have received a copy of the GNU General Public License along
1014 + * with this program; if not, write to the Free Software Foundation, Inc.,
1015 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1016 + */
1017 +
1018 +#include <linux/errno.h>
1019 +#include <linux/init.h>
1020 +#include <linux/kernel_stat.h>
1021 +#include <linux/module.h>
1022 +#include <linux/signal.h>
1023 +#include <linux/sched.h>
1024 +#include <linux/types.h>
1025 +#include <linux/interrupt.h>
1026 +#include <linux/ioport.h>
1027 +#include <linux/timex.h>
1028 +#include <linux/slab.h>
1029 +#include <linux/random.h>
1030 +#include <linux/delay.h>
1031 +
1032 +#include <asm/bitops.h>
1033 +#include <asm/bootinfo.h>
1034 +#include <asm/io.h>
1035 +#include <asm/irq.h>
1036 +#include <asm/time.h>
1037 +#include <asm/mipsregs.h>
1038 +#include <asm/system.h>
1039 +#include <asm/rc32434/rc32434.h>
1040 +#include <asm/rc32434/gpio.h>
1041 +
1042 +extern void set_debug_traps(void);
1043 +extern irq_cpustat_t irq_stat [NR_CPUS];
1044 +unsigned int local_bh_count[NR_CPUS];
1045 +unsigned int local_irq_count[NR_CPUS];
1046 +
1047 +static unsigned int startup_irq(unsigned int irq);
1048 +static void rb500_end_irq(unsigned int irq_nr);
1049 +static void mask_and_ack_irq(unsigned int irq_nr);
1050 +static void rb500_enable_irq(unsigned int irq_nr);
1051 +static void rb500_disable_irq(unsigned int irq_nr);
1052 +
1053 +extern void __init init_generic_irq(void);
1054 +
1055 +typedef struct {
1056 + u32 mask; /* mask of valid bits in pending/mask registers */
1057 + volatile u32 *base_addr;
1058 +} intr_group_t;
1059 +
1060 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
1061 +
1062 +#if (NR_IRQS < RC32434_NR_IRQS)
1063 +#error Too little irqs defined. Did you override <asm/irq.h> ?
1064 +#endif
1065 +
1066 +static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
1067 + { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
1068 + { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
1069 + { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
1070 + { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
1071 + { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
1072 +};
1073 +
1074 +#define READ_PEND(base) (*(base))
1075 +#define READ_MASK(base) (*(base + 2))
1076 +#define WRITE_MASK(base, val) (*(base + 2) = (val))
1077 +
1078 +static inline int irq_to_group(unsigned int irq_nr)
1079 +{
1080 + return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
1081 +}
1082 +
1083 +static inline int group_to_ip(unsigned int group)
1084 +{
1085 + return group + 2;
1086 +}
1087 +
1088 +static inline void enable_local_irq(unsigned int ip)
1089 +{
1090 + int ipnum = 0x100 << ip;
1091 + clear_c0_cause(ipnum);
1092 + set_c0_status(ipnum);
1093 +}
1094 +
1095 +static inline void disable_local_irq(unsigned int ip)
1096 +{
1097 + int ipnum = 0x100 << ip;
1098 + clear_c0_status(ipnum);
1099 +}
1100 +
1101 +static inline void ack_local_irq(unsigned int ip)
1102 +{
1103 + int ipnum = 0x100 << ip;
1104 + clear_c0_cause(ipnum);
1105 +}
1106 +
1107 +static void rb500_enable_irq(unsigned int irq_nr)
1108 +{
1109 + int ip = irq_nr - GROUP0_IRQ_BASE;
1110 + unsigned int group, intr_bit;
1111 + volatile unsigned int *addr;
1112 +
1113 +
1114 + if (ip < 0)
1115 + enable_local_irq(irq_nr);
1116 + else {
1117 + group = ip >> 5;
1118 +
1119 + ip &= (1<<5)-1;
1120 + intr_bit = 1 << ip;
1121 +
1122 + enable_local_irq(group_to_ip(group));
1123 +
1124 + addr = intr_group[group].base_addr;
1125 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1126 + }
1127 +}
1128 +
1129 +static void rb500_disable_irq(unsigned int irq_nr)
1130 +{
1131 + int ip = irq_nr - GROUP0_IRQ_BASE;
1132 + unsigned int group, intr_bit, mask;
1133 + volatile unsigned int *addr;
1134 +
1135 + if (ip < 0) {
1136 + disable_local_irq(irq_nr);
1137 + }else{
1138 + group = ip >> 5;
1139 +
1140 + ip &= (1<<5) -1;
1141 + intr_bit = 1 << ip;
1142 + addr = intr_group[group].base_addr;
1143 + mask = READ_MASK(addr);
1144 + mask |= intr_bit;
1145 + WRITE_MASK(addr,mask);
1146 +
1147 + /*
1148 + * if there are no more interrupts enabled in this
1149 + * group, disable corresponding IP
1150 + */
1151 + if (mask == intr_group[group].mask)
1152 + disable_local_irq(group_to_ip(group));
1153 + }
1154 +}
1155 +
1156 +static unsigned int startup_irq(unsigned int irq_nr)
1157 +{
1158 + rb500_enable_irq(irq_nr);
1159 + return 0;
1160 +}
1161 +
1162 +static void shutdown_irq(unsigned int irq_nr)
1163 +{
1164 + rb500_disable_irq(irq_nr);
1165 + return;
1166 +}
1167 +
1168 +static void mask_and_ack_irq(unsigned int irq_nr)
1169 +{
1170 + rb500_disable_irq(irq_nr);
1171 + ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
1172 +}
1173 +
1174 +static void rb500_end_irq(unsigned int irq_nr)
1175 +{
1176 +
1177 + int ip = irq_nr - GROUP0_IRQ_BASE;
1178 + unsigned int intr_bit, group;
1179 + volatile unsigned int *addr;
1180 +
1181 + if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
1182 + printk("warning: end_irq %d did not enable (%x)\n",
1183 + irq_nr, irq_desc[irq_nr].status);
1184 + return;
1185 + }
1186 +
1187 + if (ip < 0) {
1188 + enable_local_irq(irq_nr);
1189 + } else {
1190 + group = ip >> 5;
1191 +
1192 + ip &= (1 << 5) - 1;
1193 + intr_bit = 1 << ip;
1194 +
1195 + if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
1196 + gpio->gpioistat = gpio->gpioistat & ~intr_bit;
1197 + }
1198 +
1199 + enable_local_irq(group_to_ip(group));
1200 +
1201 + addr = intr_group[group].base_addr;
1202 + WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1203 + }
1204 +}
1205 +
1206 +static struct hw_interrupt_type rc32434_irq_type = {
1207 + .typename = "RB500",
1208 + .startup = startup_irq,
1209 + .shutdown = shutdown_irq,
1210 + .enable = rb500_enable_irq,
1211 + .disable = rb500_disable_irq,
1212 + .ack = mask_and_ack_irq,
1213 + .end = rb500_end_irq,
1214 +};
1215 +
1216 +
1217 +void __init arch_init_irq(void)
1218 +{
1219 + int i;
1220 +
1221 + printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
1222 + memset(irq_desc, 0, sizeof(irq_desc));
1223 +
1224 + for (i = 0; i < RC32434_NR_IRQS; i++) {
1225 + irq_desc[i].status = IRQ_DISABLED;
1226 + irq_desc[i].action = NULL;
1227 + irq_desc[i].depth = 1;
1228 + irq_desc[i].handler = &rc32434_irq_type;
1229 + spin_lock_init(&irq_desc[i].lock);
1230 + }
1231 +}
1232 +
1233 +/* Main Interrupt dispatcher */
1234 +asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
1235 +{
1236 + unsigned int ip, pend, group;
1237 + volatile unsigned int *addr;
1238 + unsigned int cp0_cause = read_c0_cause() & read_c0_status();
1239 +
1240 + if (cp0_cause & CAUSEF_IP7) {
1241 + ll_timer_interrupt(7, regs);
1242 + } else if ((ip = (cp0_cause & 0x7c00))) {
1243 + group = 21 - rc32434_clz(ip);
1244 +
1245 + addr = intr_group[group].base_addr;
1246 +
1247 + pend = READ_PEND(addr);
1248 + pend &= ~READ_MASK(addr); // only unmasked interrupts
1249 + pend = 39 - rc32434_clz(pend);
1250 + do_IRQ((group << 5) + pend, regs);
1251 + }
1252 +}
1253 diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile
1254 --- linux.old/arch/mips/rb500/Makefile 1970-01-01 01:00:00.000000000 +0100
1255 +++ linux.dev/arch/mips/rb500/Makefile 2006-10-11 21:56:38.000000000 +0200
1256 @@ -0,0 +1,5 @@
1257 +#
1258 +# Makefile for the RB500 board specific parts of the kernel
1259 +#
1260 +
1261 +obj-y += irq.o time.o setup.o serial.o early_serial.o prom.o misc.o devices.o
1262 diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c
1263 --- linux.old/arch/mips/rb500/misc.c 1970-01-01 01:00:00.000000000 +0100
1264 +++ linux.dev/arch/mips/rb500/misc.c 2006-10-11 21:56:38.000000000 +0200
1265 @@ -0,0 +1,54 @@
1266 +#include <linux/module.h>
1267 +#include <linux/kernel.h> /* printk() */
1268 +#include <linux/types.h> /* size_t */
1269 +#include <linux/pci.h>
1270 +#include <linux/spinlock.h>
1271 +#include <asm/rc32434/rb.h>
1272 +
1273 +#define GPIO_BADDR 0xb8050000
1274 +
1275 +
1276 +static unsigned char *devCtl3Base = (unsigned char *) KSEG1ADDR(0x18010030);
1277 +static unsigned char latchU5State = 0;
1278 +static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
1279 +
1280 +void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val) {
1281 + unsigned flags, data;
1282 + unsigned i = 0;
1283 + spin_lock_irqsave(&clu5Lock, flags);
1284 + data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
1285 + for (i = 0; i != len; ++i) {
1286 + if (val & (1 << i)) data |= (1 << (i + bit));
1287 + else data &= ~(1 << (i + bit));
1288 + }
1289 + *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
1290 + spin_unlock_irqrestore(&clu5Lock, flags);
1291 +}
1292 +
1293 +void changeLatchU5(unsigned char orMask, unsigned char nandMask) {
1294 + unsigned flags;
1295 + spin_lock_irqsave(&clu5Lock, flags);
1296 + latchU5State = (latchU5State | orMask) & ~nandMask;
1297 + *devCtl3Base = latchU5State;
1298 + spin_unlock_irqrestore(&clu5Lock, flags);
1299 +}
1300 +
1301 +u32 gpio_get(gpio_func func)
1302 +{
1303 + return readl((void *) GPIO_BADDR + func);
1304 +}
1305 +
1306 +void gpio_set(gpio_func func, u32 mask, u32 value)
1307 +{
1308 + u32 val = readl((void *) GPIO_BADDR + func);
1309 +
1310 + val &= ~mask;
1311 + val |= value & mask;
1312 +
1313 + writel(val, (void *) GPIO_BADDR + func);
1314 +}
1315 +
1316 +EXPORT_SYMBOL(gpio_set);
1317 +EXPORT_SYMBOL(gpio_get);
1318 +EXPORT_SYMBOL(set434Reg);
1319 +EXPORT_SYMBOL(changeLatchU5);
1320 diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c
1321 --- linux.old/arch/mips/rb500/prom.c 1970-01-01 01:00:00.000000000 +0100
1322 +++ linux.dev/arch/mips/rb500/prom.c 2006-10-11 21:56:38.000000000 +0200
1323 @@ -0,0 +1,181 @@
1324 +/*
1325 +* prom.c
1326 +**********************************************************************
1327 +* P . Sadik Oct 10, 2003
1328 +*
1329 +* Started change log
1330 +* idt_cpu_freq is make a kernel configuration parameter
1331 +* idt_cpu_freq is exported so that other modules can use it.
1332 +* Code cleanup
1333 +**********************************************************************
1334 +* P. Sadik Oct 20, 2003
1335 +*
1336 +* Removed NVRAM code from here, since they are already available under
1337 +* nvram directory.
1338 +* Added serial port initialisation.
1339 +**********************************************************************
1340 +**********************************************************************
1341 +* P. Sadik Oct 30, 2003
1342 +*
1343 +* Added reset_cons_port
1344 +**********************************************************************
1345 +
1346 + P.Christeas, 2005-2006
1347 + Port to 2.6, add 2.6 cmdline parsing
1348 +
1349 +*/
1350 +
1351 +#include <linux/config.h>
1352 +#include <linux/init.h>
1353 +#include <linux/mm.h>
1354 +#include <linux/module.h>
1355 +#include <linux/string.h>
1356 +#include <linux/console.h>
1357 +#include <asm/bootinfo.h>
1358 +#include <linux/bootmem.h>
1359 +#include <linux/ioport.h>
1360 +#include <linux/blkdev.h>
1361 +#include <asm/rc32434/ddr.h>
1362 +
1363 +#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
1364 +extern void __init setup_serial_port(void);
1365 +extern void cons_putc(char c);
1366 +extern void cons_puts(char *s);
1367 +
1368 +unsigned int idt_cpu_freq = 132000000;
1369 +EXPORT_SYMBOL(idt_cpu_freq);
1370 +unsigned int board_type = 500;
1371 +EXPORT_SYMBOL(board_type);
1372 +unsigned int gpio_bootup_state = 0;
1373 +EXPORT_SYMBOL(gpio_bootup_state);
1374 +
1375 +
1376 +char mips_mac_address[18] = "08:00:06:05:40:01";
1377 +EXPORT_SYMBOL(mips_mac_address);
1378 +
1379 +/* what to append to cmdline when button is [not] pressed */
1380 +#define GPIO_INIT_NOBUTTON ""
1381 +#define GPIO_INIT_BUTTON " 2"
1382 +
1383 +#ifdef CONFIG_MIKROTIK_RB500
1384 +unsigned soft_reboot = 0;
1385 +EXPORT_SYMBOL(soft_reboot);
1386 +#endif
1387 +
1388 +#define SR_NMI 0x00180000 /* NMI */
1389 +#define SERIAL_SPEED_ENTRY 0x00000001
1390 +
1391 +#ifdef CONFIG_REMOTE_DEBUG
1392 +extern int remote_debug;
1393 +#endif
1394 +
1395 +extern unsigned long mips_machgroup;
1396 +extern unsigned long mips_machtype;
1397 +
1398 +#define FREQ_TAG "HZ="
1399 +#define GPIO_TAG "gpio="
1400 +#define KMAC_TAG "kmac="
1401 +#define MEM_TAG "mem="
1402 +#define BOARD_TAG "board="
1403 +#define IGNORE_CMDLINE_MEM 1
1404 +#define DEBUG_DDR
1405 +
1406 +void parse_soft_settings(unsigned *ptr, unsigned size);
1407 +void parse_hard_settings(unsigned *ptr, unsigned size);
1408 +
1409 +void __init prom_setup_cmdline(void);
1410 +
1411 +#ifdef DEBUG_DDR
1412 +void cons_puthex4(u32 h){
1413 + h&=0x0f;
1414 + if (h>=10)
1415 + cons_putc((h-10)+'a');
1416 + else
1417 + cons_putc(h+'0');
1418 +}
1419 +
1420 +void cons_putreg32(u32 reg){
1421 + char c;
1422 + cons_putc('0');
1423 + cons_putc('x');
1424 + for (c=28;c>=0;c-=4)
1425 + cons_puthex4(reg>>c);
1426 +}
1427 +#endif
1428 +
1429 +void __init prom_init(void)
1430 +{
1431 + DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
1432 + phys_t memsize = 0-ddr->ddrmask;
1433 +
1434 + /* this should be the very first message, even before serial is properly initialized */
1435 + prom_setup_cmdline();
1436 + setup_serial_port();
1437 +
1438 + mips_machgroup = MACH_GROUP_MIKROTIK;
1439 + soft_reboot = read_c0_status() & SR_NMI;
1440 + pm_power_off = NULL;
1441 +
1442 + /*
1443 + * give all RAM to boot allocator,
1444 + * except for the first 0x400 and the last 0x200 bytes
1445 + */
1446 + add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
1447 +}
1448 +
1449 +void prom_free_prom_memory(void)
1450 +{
1451 + /* FIXME: STUB */
1452 +}
1453 +
1454 +void __init prom_setup_cmdline(void){
1455 + char cmd_line[CL_SIZE];
1456 + char *cp;
1457 + int prom_argc;
1458 + char **prom_argv, **prom_envp;
1459 + int i;
1460 +
1461 + prom_argc = fw_arg0;
1462 + prom_argv = (char **) fw_arg1;
1463 + prom_envp = (char **) fw_arg2;
1464 +
1465 + cp=cmd_line;
1466 + /* Note: it is common that parameters start at argv[1] and not argv[0],
1467 + however, our elf loader starts at [0] */
1468 + for(i=0;i<prom_argc;i++){
1469 + if (strncmp(prom_argv[i], FREQ_TAG, sizeof(FREQ_TAG) - 1) == 0) {
1470 + idt_cpu_freq = simple_strtoul(prom_argv[i] + sizeof(FREQ_TAG) - 1, 0, 10);
1471 + continue;
1472 + }
1473 +#ifdef IGNORE_CMDLINE_MEM
1474 + /* parses out the "mem=xx" arg */
1475 + if (strncmp(prom_argv[i], MEM_TAG, sizeof(MEM_TAG) - 1) == 0) {
1476 + continue;
1477 + }
1478 +#endif
1479 + if (i>0) *(cp++) = ' ';
1480 + if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) {
1481 + board_type = simple_strtoul(prom_argv[i] + sizeof(BOARD_TAG) - 1, 0, 10);
1482 + }
1483 + if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) {
1484 + gpio_bootup_state = simple_strtoul(prom_argv[i] + sizeof(GPIO_TAG) - 1, 0, 10);
1485 + }
1486 + strcpy(cp,prom_argv[i]);
1487 + cp+=strlen(prom_argv[i]);
1488 + }
1489 +
1490 + i=strlen(arcs_cmdline);
1491 + if (i>0){
1492 + *(cp++) = ' ';
1493 + strcpy(cp,arcs_cmdline);
1494 + cp+=strlen(arcs_cmdline);
1495 + }
1496 + if (gpio_bootup_state&0x02)
1497 + strcpy(cp,GPIO_INIT_NOBUTTON);
1498 + else
1499 + strcpy(cp,GPIO_INIT_BUTTON);
1500 + cmd_line[CL_SIZE-1] = '\0';
1501 +
1502 + strcpy(arcs_cmdline,cmd_line);
1503 +}
1504 +
1505 diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c
1506 --- linux.old/arch/mips/rb500/serial.c 1970-01-01 01:00:00.000000000 +0100
1507 +++ linux.dev/arch/mips/rb500/serial.c 2006-10-11 21:56:38.000000000 +0200
1508 @@ -0,0 +1,79 @@
1509 +/**************************************************************************
1510 + *
1511 + * BRIEF MODULE DESCRIPTION
1512 + * Serial port initialisation.
1513 + *
1514 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1515 + *
1516 + * This program is free software; you can redistribute it and/or modify it
1517 + * under the terms of the GNU General Public License as published by the
1518 + * Free Software Foundation; either version 2 of the License, or (at your
1519 + * option) any later version.
1520 + *
1521 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1522 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1523 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1524 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1525 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1526 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1527 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1528 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1529 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1530 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1531 + *
1532 + * You should have received a copy of the GNU General Public License along
1533 + * with this program; if not, write to the Free Software Foundation, Inc.,
1534 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1535 + *
1536 + *
1537 + **************************************************************************
1538 + * May 2004 rkt, neb
1539 + *
1540 + * Initial Release
1541 + *
1542 + *
1543 + *
1544 + **************************************************************************
1545 + */
1546 +
1547 +
1548 +#include <linux/config.h>
1549 +#include <linux/init.h>
1550 +#include <linux/sched.h>
1551 +#include <linux/pci.h>
1552 +#include <linux/interrupt.h>
1553 +#include <linux/tty.h>
1554 +#include <linux/serial.h>
1555 +#include <linux/serial_core.h>
1556 +
1557 +#include <asm/time.h>
1558 +#include <asm/cpu.h>
1559 +#include <asm/bootinfo.h>
1560 +#include <asm/irq.h>
1561 +#include <asm/serial.h>
1562 +#include <asm/rc32434/rc32434.h>
1563 +
1564 +extern unsigned int idt_cpu_freq;
1565 +
1566 +static struct uart_port serial_req = {
1567 + .type = PORT_16550A,
1568 + .line = 0,
1569 + .irq = RC32434_UART0_IRQ,
1570 + .flags = STD_COM_FLAGS,
1571 + .iotype = UPIO_MEM,
1572 + .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
1573 +// .fifosize = 14
1574 + .regshift = 2
1575 +};
1576 +
1577 +int __init setup_serial_port(void)
1578 +{
1579 + serial_req.uartclk = idt_cpu_freq;
1580 +
1581 + if (early_serial_setup(&serial_req)){
1582 + cons_puts("Serial setup failed!\n");
1583 + return -ENODEV;
1584 + }
1585 +
1586 + return(0);
1587 +}
1588 diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c
1589 --- linux.old/arch/mips/rb500/setup.c 1970-01-01 01:00:00.000000000 +0100
1590 +++ linux.dev/arch/mips/rb500/setup.c 2006-10-11 21:56:38.000000000 +0200
1591 @@ -0,0 +1,84 @@
1592 +/*
1593 + * setup.c - boot time setup code
1594 + */
1595 +
1596 +#include <linux/init.h>
1597 +#include <linux/mm.h>
1598 +#include <linux/sched.h>
1599 +#include <linux/irq.h>
1600 +#include <asm/bootinfo.h>
1601 +#include <asm/io.h>
1602 +#include <linux/ioport.h>
1603 +#include <asm/mipsregs.h>
1604 +#include <asm/pgtable.h>
1605 +#include <asm/reboot.h>
1606 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
1607 +#include <asm/rc32434/rc32434.h>
1608 +#include <linux/pm.h>
1609 +#include <asm/rc32434/pci.h>
1610 +
1611 +extern void (*board_time_init)(void);
1612 +extern void (*board_timer_setup)(struct irqaction *irq);
1613 +extern void rc32434_time_init(void);
1614 +extern void rc32434_timer_setup(struct irqaction *irq);
1615 +#ifdef CONFIG_PCI
1616 +extern int __init rc32434_pcibridge_init(void);
1617 +#endif
1618 +
1619 +#define epldMask ((volatile unsigned char *)0xB900000d)
1620 +
1621 +static void rb_machine_restart(char *command)
1622 +{
1623 + /* just jump to the reset vector */
1624 + * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
1625 + ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
1626 +}
1627 +
1628 +static void rb_machine_halt(void)
1629 +{
1630 + for(;;) continue;
1631 +}
1632 +
1633 +#ifdef CONFIG_CPU_HAS_WB
1634 +void (*__wbflush) (void);
1635 +
1636 +static void rb_write_buffer_flush(void)
1637 +{
1638 + __asm__ __volatile__
1639 + ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
1640 +}
1641 +#endif
1642 +
1643 +void __init plat_setup(void)
1644 +{
1645 + unsigned int pciCntlVal;
1646 +
1647 + board_time_init = rc32434_time_init;
1648 + board_timer_setup = rc32434_timer_setup;
1649 +
1650 +#ifdef CONFIG_CPU_HAS_WB
1651 + __wbflush = rb_write_buffer_flush;
1652 +#endif
1653 + _machine_restart = rb_machine_restart;
1654 + _machine_halt = rb_machine_halt;
1655 + /*_machine_power_off = rb_machine_power_halt;*/
1656 + pm_power_off = rb_machine_halt;
1657 +
1658 + set_io_port_base(KSEG1);
1659 +
1660 + pciCntlVal=rc32434_pci->pcic;
1661 + pciCntlVal &= 0xFFFFFF7;
1662 + rc32434_pci->pcic = pciCntlVal;
1663 +
1664 +#ifdef CONFIG_PCI
1665 + /* Enable PCI interrupts in EPLD Mask register */
1666 + *epldMask = 0x0;
1667 + *(epldMask + 1) = 0x0;
1668 +#endif
1669 + write_c0_wired(0);
1670 +}
1671 +
1672 +const char *get_system_type(void)
1673 +{
1674 + return "MIPS RB500";
1675 +}
1676 diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c
1677 --- linux.old/arch/mips/rb500/time.c 1970-01-01 01:00:00.000000000 +0100
1678 +++ linux.dev/arch/mips/rb500/time.c 2006-10-11 21:56:38.000000000 +0200
1679 @@ -0,0 +1,94 @@
1680 +/*
1681 +****************************************************************************
1682 +* Carsten Langgaard, carstenl@mips.com
1683 +* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1684 +*
1685 +***************************************************************************
1686 +*
1687 +* This program is free software; you can distribute it and/or modify it
1688 +* under the terms of the GNU General Public License (Version 2) as
1689 +* published by the Free Software Foundation.
1690 +*
1691 +* This program is distributed in the hope it will be useful, but WITHOUT
1692 +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1693 +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1694 +* for more details.
1695 +*
1696 +* You should have received a copy of the GNU General Public License along
1697 +* with this program; if not, write to the Free Software Foundation, Inc.,
1698 +* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1699 +*
1700 +****************************************************************************
1701 +*
1702 +* Setting up the clock on the MIPS boards.
1703 +*
1704 +****************************************************************************
1705 +* P. Sadik Oct 10, 2003
1706 +*
1707 +* Started change log.
1708 +* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
1709 +* Code cleanup
1710 +****************************************************************************
1711 +*/
1712 +
1713 +#include <linux/config.h>
1714 +#include <linux/init.h>
1715 +#include <linux/kernel_stat.h>
1716 +#include <linux/sched.h>
1717 +#include <linux/spinlock.h>
1718 +#include <linux/mc146818rtc.h>
1719 +#include <linux/irq.h>
1720 +#include <linux/timex.h>
1721 +
1722 +#include <asm/mipsregs.h>
1723 +#include <asm/ptrace.h>
1724 +#include <asm/debug.h>
1725 +#include <asm/rc32434/rc32434.h>
1726 +
1727 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
1728 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
1729 +extern void ll_timer_interrupt(int irq, struct pt_regs *regs);
1730 +extern unsigned int mips_hpt_frequency;
1731 +extern unsigned int idt_cpu_freq;
1732 +
1733 +/*
1734 + * Figure out the r4k offset, the amount to increment the compare
1735 + * register for each time tick. There is no RTC available.
1736 + *
1737 + * The RC32434 counts at half the CPU *core* speed.
1738 + */
1739 +static unsigned long __init cal_r4koff(void)
1740 +{
1741 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
1742 + return (mips_hpt_frequency / HZ);
1743 +}
1744 +
1745 +
1746 +void __init rc32434_time_init(void)
1747 +{
1748 + unsigned int est_freq, flags;
1749 +
1750 + local_irq_save(flags);
1751 +
1752 + printk("calculating r4koff... ");
1753 + r4k_offset = cal_r4koff();
1754 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1755 +
1756 + est_freq = 2*r4k_offset*HZ;
1757 + est_freq += 5000; /* round */
1758 + est_freq -= est_freq%10000;
1759 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1760 + (est_freq%1000000)*100/1000000);
1761 + local_irq_restore(flags);
1762 +}
1763 +
1764 +void __init rc32434_timer_setup(struct irqaction *irq)
1765 +{
1766 + /* we are using the cpu counter for timer interrupts */
1767 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1768 +
1769 + /* to generate the first timer interrupt */
1770 + r4k_cur = (read_c0_count() + r4k_offset);
1771 + write_c0_compare(r4k_cur);
1772 +}
1773 +
1774 diff -urN linux.old/drivers/mtd/devices/block2mtd.c linux.dev/drivers/mtd/devices/block2mtd.c
1775 --- linux.old/drivers/mtd/devices/block2mtd.c 2006-10-11 21:55:59.000000000 +0200
1776 +++ linux.dev/drivers/mtd/devices/block2mtd.c 2006-10-11 21:57:34.000000000 +0200
1777 @@ -26,7 +26,6 @@
1778 #define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args)
1779 #define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args)
1780
1781 -
1782 /* Info for the block device */
1783 struct block2mtd_dev {
1784 struct list_head list;
1785 @@ -104,7 +103,7 @@
1786
1787 while (pages) {
1788 page = page_readahead(mapping, index);
1789 - if (!page)
1790 + if (!page || !page_address(page))
1791 return -ENOMEM;
1792 if (IS_ERR(page))
1793 return PTR_ERR(page);
1794 @@ -285,7 +284,7 @@
1795
1796
1797 /* FIXME: ensure that mtd->size % erase_size == 0 */
1798 -static struct block2mtd_dev *add_device(char *devname, int erase_size)
1799 +static struct block2mtd_dev *add_device(char *devname, int erase_size, char *alias)
1800 {
1801 struct block_device *bdev;
1802 struct block2mtd_dev *dev;
1803 @@ -328,14 +327,15 @@
1804
1805 /* Setup the MTD structure */
1806 /* make the name contain the block device in */
1807 - dev->mtd.name = kmalloc(sizeof("block2mtd: ") + strlen(devname),
1808 + dev->mtd.name = kmalloc(strlen((alias ?: devname)),
1809 GFP_KERNEL);
1810 if (!dev->mtd.name)
1811 goto devinit_err;
1812
1813 - sprintf(dev->mtd.name, "block2mtd: %s", devname);
1814 + strcpy(dev->mtd.name, (alias ?: devname));
1815
1816 dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK;
1817 + dev->mtd.size -= dev->mtd.size % erase_size;
1818 dev->mtd.erasesize = erase_size;
1819 dev->mtd.type = MTD_RAM;
1820 dev->mtd.flags = MTD_CAP_RAM;
1821 @@ -353,7 +353,7 @@
1822 }
1823 list_add(&dev->list, &blkmtd_device_list);
1824 INFO("mtd%d: [%s] erase_size = %dKiB [%d]", dev->mtd.index,
1825 - dev->mtd.name + strlen("blkmtd: "),
1826 + dev->mtd.name,
1827 dev->mtd.erasesize >> 10, dev->mtd.erasesize);
1828 return dev;
1829
1830 @@ -425,11 +425,11 @@
1831 #endif
1832
1833
1834 -static int block2mtd_setup2(const char *val)
1835 +int block2mtd_setup2(const char *val)
1836 {
1837 char buf[80 + 12]; /* 80 for device, 12 for erase size */
1838 char *str = buf;
1839 - char *token[2];
1840 + char *token[3];
1841 char *name;
1842 size_t erase_size = PAGE_SIZE;
1843 int i, ret;
1844 @@ -440,7 +440,7 @@
1845 strcpy(str, val);
1846 kill_final_newline(str);
1847
1848 - for (i = 0; i < 2; i++)
1849 + for (i = 0; i < 3; i++)
1850 token[i] = strsep(&str, ",");
1851
1852 if (str)
1853 @@ -461,7 +461,7 @@
1854 }
1855 }
1856
1857 - add_device(name, erase_size);
1858 + add_device(name, erase_size, token[2]);
1859
1860 return 0;
1861 }
1862 @@ -496,6 +496,7 @@
1863
1864 module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200);
1865 MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>]\"");
1866 +EXPORT_SYMBOL(block2mtd_setup);
1867
1868 static int __init block2mtd_init(void)
1869 {
1870 diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile
1871 --- linux.old/drivers/pci/Makefile 2006-06-18 03:49:35.000000000 +0200
1872 +++ linux.dev/drivers/pci/Makefile 2006-10-11 21:56:38.000000000 +0200
1873 @@ -27,6 +27,7 @@
1874 obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o
1875 obj-$(CONFIG_X86_VISWS) += setup-irq.o
1876 obj-$(CONFIG_PCI_MSI) += msi.o
1877 +obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
1878
1879 #
1880 # ACPI Related PCI FW Functions
1881 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
1882 --- linux.old/include/asm-mips/bootinfo.h 2006-06-18 03:49:35.000000000 +0200
1883 +++ linux.dev/include/asm-mips/bootinfo.h 2006-10-11 21:56:38.000000000 +0200
1884 @@ -218,6 +218,8 @@
1885 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
1886 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
1887
1888 +#define MACH_GROUP_MIKROTIK 24 /* Mikrotik Boards */
1889 +
1890 #define CL_SIZE COMMAND_LINE_SIZE
1891
1892 const char *get_system_type(void);
1893 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
1894 --- linux.old/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
1895 +++ linux.dev/include/asm-mips/cpu.h 2006-10-11 21:56:38.000000000 +0200
1896 @@ -200,7 +200,8 @@
1897 #define CPU_SB1A 62
1898 #define CPU_74K 63
1899 #define CPU_R14000 64
1900 -#define CPU_LAST 64
1901 +#define CPU_RC32300 65
1902 +#define CPU_LAST 65
1903
1904 /*
1905 * ISA Level encodings
1906 diff -urN linux.old/include/asm-mips/rc32434/crom.h linux.dev/include/asm-mips/rc32434/crom.h
1907 --- linux.old/include/asm-mips/rc32434/crom.h 1970-01-01 01:00:00.000000000 +0100
1908 +++ linux.dev/include/asm-mips/rc32434/crom.h 2006-10-11 21:56:38.000000000 +0200
1909 @@ -0,0 +1,98 @@
1910 +#ifndef __IDT_CROM_H__
1911 +#define __IDT_CROM_H__
1912 +
1913 +/*******************************************************************************
1914 + *
1915 + * Copyright 2002 Integrated Device Technology, Inc.
1916 + * All rights reserved.
1917 + *
1918 + * Configuration ROM register definitions.
1919 + *
1920 + * File : $Id: crom.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1921 + *
1922 + * Author : Allen.Stichter@idt.com
1923 + * Date : 20020118
1924 + * Update :
1925 + * $Log: crom.h,v $
1926 + * Revision 1.2 2002/06/06 18:34:03 astichte
1927 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
1928 + *
1929 + * Revision 1.1 2002/05/29 17:33:21 sysarch
1930 + * jba File moved from vcode/include/idt/acacia
1931 + *
1932 + *
1933 + ******************************************************************************/
1934 +
1935 +#include <asm/rc32434/types.h>
1936 +
1937 +enum
1938 +{
1939 + CROM0_PhysicalAddress = 0x100b8000,
1940 + CROM_PhysicalAddress = CROM0_PhysicalAddress,
1941 +
1942 + CROM0_VirtualAddress = 0xb00b8000,
1943 + CROM_VirtualAddress = CROM0_VirtualAddress,
1944 +} ;
1945 +
1946 +typedef struct CROM_s
1947 +{
1948 + U32 cromw0 ; // use CROMW0_
1949 + U32 cromw1 ; // use CROMW1_
1950 + U32 cromw2 ; // use CROMW2_
1951 +} volatile * CROM_t ;
1952 +
1953 +enum
1954 +{
1955 + CROMW0_xloc_b = 0,
1956 + CROMW0_xloc_m = 0x0000003f,
1957 + CROMW0_yloc_b = 8,
1958 + CROMW0_yloc_m = 0x00003f00,
1959 + CROMW0_speed_b = 16,
1960 + CROMW0_speed_m = 0x01ff0000,
1961 + CROMW1_wafer_b = 0,
1962 + CROMW1_wafer_m = 0x0000001f,
1963 + CROMW1_lot_b = 8,
1964 + CROMW1_lot_m = 0x0fffff00,
1965 + CROMW1_fab_b = 28,
1966 + CROMW1_fab_m = 0xf0000000,
1967 + CROMW2_pci_b = 0,
1968 + CROMW2_pci_m = 0x00000001,
1969 + CROMW2_eth0_b = 1,
1970 + CROMW2_eth0_m = 0x00000002,
1971 + CROMW2_eth1_b = 2,
1972 + CROMW2_eth1_m = 0x00000004
1973 + CROMW2_i2c_b = 3,
1974 + CROMW2_i2c_m = 0x00000008,
1975 + CROMW2_rng_b = 4,
1976 + CROMW2_rng_m = 0x00000010,
1977 + CROMW2_se_b = 5,
1978 + CROMW2_se_m = 0x00000020,
1979 + CROMW2_des_b = 6,
1980 + CROMW2_des_m = 0x00000040,
1981 + CROMW2_tdes_b = 7,
1982 + CROMW2_tdes_m = 0x00000080,
1983 + CROMW2_a128_b = 8,
1984 + CROMW2_a128_m = 0x00000100,
1985 + CROMW2_a192_b = 9,
1986 + CROMW2_a192_m = 0x00000200,
1987 + CROMW2_a256_b = 10,
1988 + CROMW2_a256_m = 0x00000400,
1989 + CROMW2_md5_b = 11,
1990 + CROMW2_md5_m = 0x00000800,
1991 + CROMW2_s1_b = 12,
1992 + CROMW2_s1_m = 0x00001000,
1993 + CROMW2_s256_b = 13,
1994 + CROMW2_s256_m = 0x00002000,
1995 + CROMW2_pka_b = 14,
1996 + CROMW2_pka_m = 0x00004000,
1997 + CROMW2_exp_b = 15,
1998 + CROMW2_exp_m = 0x00018000,
1999 + CROMW2_exp_8192_v = 0,
2000 + CROMW2_exp_1536_v = 1,
2001 + CROMW2_exp_1024_v = 2,
2002 + CROMW2_exp_512_v = 3,
2003 + CROMW2_rocfg_b = 17,
2004 + CROMW2_rocfg_m = 0x000e0000,
2005 +} ;
2006 +
2007 +#endif // __IDT_CROM_H__
2008 diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h
2009 --- linux.old/include/asm-mips/rc32434/ddr.h 1970-01-01 01:00:00.000000000 +0100
2010 +++ linux.dev/include/asm-mips/rc32434/ddr.h 2006-10-11 21:56:38.000000000 +0200
2011 @@ -0,0 +1,175 @@
2012 +#ifndef __IDT_DDR_H__
2013 +#define __IDT_DDR_H__
2014 +
2015 +/*******************************************************************************
2016 + *
2017 + * Copyright 2002 Integrated Device Technology, Inc.
2018 + * All rights reserved.
2019 + *
2020 + * DDR register definition.
2021 + *
2022 + * File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2023 + *
2024 + * Author : ryan.holmQVist@idt.com
2025 + * Date : 20011005
2026 + * Update :
2027 + * $Log: ddr.h,v $
2028 + * Revision 1.2 2002/06/06 18:34:03 astichte
2029 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2030 + *
2031 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2032 + * jba File moved from vcode/include/idt/acacia
2033 + *
2034 + *
2035 + ******************************************************************************/
2036 +
2037 +#include <asm/rc32434/types.h>
2038 +
2039 +enum
2040 +{
2041 + DDR0_PhysicalAddress = 0x18018000,
2042 + DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default
2043 +
2044 + DDR0_VirtualAddress = 0xb8018000,
2045 + DDR_VirtualAddress = DDR0_VirtualAddress, // Default
2046 +} ;
2047 +
2048 +typedef struct DDR_s
2049 +{
2050 + U32 ddrbase ;
2051 + U32 ddrmask ;
2052 + U32 res1;
2053 + U32 res2;
2054 + U32 ddrc ;
2055 + U32 ddrabase ;
2056 + U32 ddramask ;
2057 + U32 ddramap ;
2058 + U32 ddrcust;
2059 + U32 ddrrdc;
2060 + U32 ddrspare;
2061 +} volatile *DDR_t ;
2062 +
2063 +enum
2064 +{
2065 + DDR0BASE_baseaddr_b = 16,
2066 + DDR0BASE_baseaddr_m = 0xffff0000,
2067 +
2068 + DDR0MASK_mask_b = 16,
2069 + DDR0MASK_mask_m = 0xffff0000,
2070 +
2071 + DDR1BASE_baseaddr_b = 16,
2072 + DDR1BASE_baseaddr_m = 0xffff0000,
2073 +
2074 + DDR1MASK_mask_b = 16,
2075 + DDR1MASK_mask_m = 0xffff0000,
2076 +
2077 + DDRC_ata_b = 5,
2078 + DDRC_ata_m = 0x000000E0,
2079 + DDRC_dbw_b = 8,
2080 + DDRC_dbw_m = 0x00000100,
2081 + DDRC_wr_b = 9,
2082 + DDRC_wr_m = 0x00000600,
2083 + DDRC_ps_b = 11,
2084 + DDRC_ps_m = 0x00001800,
2085 + DDRC_dtype_b = 13,
2086 + DDRC_dtype_m = 0x0000e000,
2087 + DDRC_rfc_b = 16,
2088 + DDRC_rfc_m = 0x000f0000,
2089 + DDRC_rp_b = 20,
2090 + DDRC_rp_m = 0x00300000,
2091 + DDRC_ap_b = 22,
2092 + DDRC_ap_m = 0x00400000,
2093 + DDRC_rcd_b = 23,
2094 + DDRC_rcd_m = 0x01800000,
2095 + DDRC_cl_b = 25,
2096 + DDRC_cl_m = 0x06000000,
2097 + DDRC_dbm_b = 27,
2098 + DDRC_dbm_m = 0x08000000,
2099 + DDRC_sds_b = 28,
2100 + DDRC_sds_m = 0x10000000,
2101 + DDRC_atp_b = 29,
2102 + DDRC_atp_m = 0x60000000,
2103 + DDRC_re_b = 31,
2104 + DDRC_re_m = 0x80000000,
2105 +
2106 + DDRRDC_ces_b = 0,
2107 + DDRRDC_ces_m = 0x00000001,
2108 + DDRRDC_ace_b = 1,
2109 + DDRRDC_ace_m = 0x00000002,
2110 +
2111 + DDRABASE_baseaddr_b = 16,
2112 + DDRABASE_baseaddr_m = 0xffff0000,
2113 +
2114 + DDRAMASK_mask_b = 16,
2115 + DDRAMASK_mask_m = 0xffff0000,
2116 +
2117 + DDRAMAP_map_b = 16,
2118 + DDRAMAP_map_m = 0xffff0000,
2119 +
2120 + DDRCUST_cs_b = 0,
2121 + DDRCUST_cs_m = 0x00000003,
2122 + DDRCUST_we_b = 2,
2123 + DDRCUST_we_m = 0x00000004,
2124 + DDRCUST_ras_b = 3,
2125 + DDRCUST_ras_m = 0x00000008,
2126 + DDRCUST_cas_b = 4,
2127 + DDRCUST_cas_m = 0x00000010,
2128 + DDRCUST_cke_b = 5,
2129 + DDRCUST_cke_m = 0x00000020,
2130 + DDRCUST_ba_b = 6,
2131 + DDRCUST_ba_m = 0x000000c0,
2132 +
2133 + RCOUNT_rcount_b = 0,
2134 + RCOUNT_rcount_m = 0x0000ffff,
2135 +
2136 + RCOMPARE_rcompare_b = 0,
2137 + RCOMPARE_rcompare_m = 0x0000ffff,
2138 +
2139 + RTC_ce_b = 0,
2140 + RTC_ce_m = 0x00000001,
2141 + RTC_to_b = 1,
2142 + RTC_to_m = 0x00000002,
2143 + RTC_rqe_b = 2,
2144 + RTC_rqe_m = 0x00000004,
2145 +
2146 + DDRDQSC_dm_b = 0,
2147 + DDRDQSC_dm_m = 0x00000003,
2148 + DDRDQSC_dqsbs_b = 2,
2149 + DDRDQSC_dqsbs_m = 0x000000fc,
2150 + DDRDQSC_db_b = 8,
2151 + DDRDQSC_db_m = 0x00000100,
2152 + DDRDQSC_dbsp_b = 9,
2153 + DDRDQSC_dbsp_m = 0x01fffe00,
2154 + DDRDQSC_bdp_b = 25,
2155 + DDRDQSC_bdp_m = 0x7e000000,
2156 +
2157 + DDRDLLC_eao_b = 0,
2158 + DDRDLLC_eao_m = 0x00000001,
2159 + DDRDLLC_eo_b = 1,
2160 + DDRDLLC_eo_m = 0x0000003e,
2161 + DDRDLLC_fs_b = 6,
2162 + DDRDLLC_fs_m = 0x000000c0,
2163 + DDRDLLC_as_b = 8,
2164 + DDRDLLC_as_m = 0x00000700,
2165 + DDRDLLC_sp_b = 11,
2166 + DDRDLLC_sp_m = 0x001ff800,
2167 +
2168 + DDRDLLFC_men_b = 0,
2169 + DDRDLLFC_men_m = 0x00000001,
2170 + DDRDLLFC_aen_b = 1,
2171 + DDRDLLFC_aen_m = 0x00000002,
2172 + DDRDLLFC_ff_b = 2,
2173 + DDRDLLFC_ff_m = 0x00000004,
2174 +
2175 + DDRDLLTA_addr_b = 2,
2176 + DDRDLLTA_addr_m = 0xfffffffc,
2177 +
2178 + DDRDLLED_dbe_b = 0,
2179 + DDRDLLED_dbe_m = 0x00000001,
2180 + DDRDLLED_dte_b = 1,
2181 + DDRDLLED_dte_m = 0x00000002,
2182 +
2183 +
2184 +} ;
2185 +
2186 +#endif // __IDT_DDR_H__
2187 diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc32434/dev.h
2188 --- linux.old/include/asm-mips/rc32434/dev.h 1970-01-01 01:00:00.000000000 +0100
2189 +++ linux.dev/include/asm-mips/rc32434/dev.h 2006-10-11 21:56:38.000000000 +0200
2190 @@ -0,0 +1,134 @@
2191 +#ifndef __IDT_DEV_H__
2192 +#define __IDT_DEV_H__
2193 +
2194 +/*******************************************************************************
2195 + *
2196 + * Copyright 2002 Integrated Device Technology, Inc.
2197 + * All rights reserved.
2198 + *
2199 + * Device Controller register definition.
2200 + *
2201 + * File : $Id: dev.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
2202 + *
2203 + * Author : John.Ahrens@idt.com
2204 + * Date : 200112013
2205 + * Update :
2206 + * $Log: dev.h,v $
2207 + * Revision 1.2 2002/06/06 18:34:03 astichte
2208 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2209 + *
2210 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2211 + * jba File moved from vcode/include/idt/acacia
2212 + *
2213 + *
2214 + ******************************************************************************/
2215 +
2216 +#include <asm/rc32434/types.h>
2217 +
2218 +enum
2219 +{
2220 + DEV0_PhysicalAddress = 0x18010000,
2221 + DEV_PhysicalAddress = DEV0_PhysicalAddress, // Default
2222 +
2223 + DEV0_VirtualAddress = 0xb8010000,
2224 + DEV_VirtualAddress = DEV0_VirtualAddress, // Default
2225 +} ;
2226 +
2227 +typedef struct DEVICE_s
2228 +{
2229 + U32 devbase ; // Device Base
2230 + U32 devmask ; // Device Mask
2231 + U32 devc ; // Device Control
2232 + U32 devtc ; // Device Timing Control
2233 +} volatile *DEVICE_t ;
2234 +
2235 +enum
2236 +{
2237 + DEV_Count = 3,
2238 +} ;
2239 +
2240 +typedef struct DEV_s
2241 +{
2242 + struct DEVICE_s dev [DEV_Count] ;
2243 + U32 btcs ; // Bus timeout control / status
2244 + U32 btcompare ; // Compare
2245 + U32 btaddr ; // Timeout address.
2246 + U32 devdacs ; // Decoupled access control.
2247 + U32 devdaa ; // Decoupled access address.
2248 + U32 devdad ; // Decoupled access address.
2249 + U32 devspare ; // spare.
2250 +} volatile *DEV_t ;
2251 +
2252 +enum
2253 +{
2254 + DEVBASE_baseaddr_b = 16,
2255 + DEVBASE_baseaddr_m = 0xffff0000,
2256 + DEVMASK_mask_b = 16,
2257 + DEVMASK_mask_m = 0xffff0000,
2258 +
2259 + DEVC_ds_b = 0,
2260 + DEVC_ds_m = 0x00000003,
2261 + DEVC_ds_8_v = 0, // 8-bit device.
2262 + DEVC_ds_16_v = 1, // reserved
2263 + DEVC_ds_res_v = 2, // reserved.
2264 + DEVC_ds_res2_v = 3, // reserved.
2265 + DEVC_be_b = 2,
2266 + DEVC_be_m = 0x00000004,
2267 + DEVC_wp_b = 3,
2268 + DEVC_wp_m = 0x00000008,
2269 + DEVC_csd_b = 4,
2270 + DEVC_csd_m = 0x000000f0,
2271 + DEVC_oed_b = 8,
2272 + DEVC_oed_m = 0x00000f00,
2273 + DEVC_bwd_b = 12,
2274 + DEVC_bwd_m = 0x0000f000,
2275 + DEVC_rws_b = 16,
2276 + DEVC_rws_m = 0x003f0000,
2277 + DEVC_wws_b = 22,
2278 + DEVC_wws_m = 0x0fc00000,
2279 + DEVC_bre_b = 28,
2280 + DEVC_bre_m = 0x10000000,
2281 + DEVC_bwe_b = 29,
2282 + DEVC_bwe_m = 0x20000000,
2283 + DEVC_wam_b = 30,
2284 + DEVC_wam_m = 0x40000000,
2285 +
2286 + DEVTC_prd_b = 0,
2287 + DEVTC_prd_m = 0x0000000f,
2288 + DEVTC_pwd_b = 4,
2289 + DEVTC_pwd_m = 0x000000f0,
2290 + DEVTC_wdh_b = 8,
2291 + DEVTC_wdh_m = 0x00000700,
2292 + DEVTC_csh_b = 11,
2293 + DEVTC_csh_m = 0x00001800,
2294 +
2295 + BTCS_tt_b = 0,
2296 + BTCS_tt_m = 0x00000001,
2297 + BTCS_tt_write = 0,
2298 + BTCS_tt_read = 1,
2299 + BTCS_bto_b = 1, // In btcs
2300 + BTCS_bto_m = 0x00000002, // In btcs
2301 + BTCS_bte_b = 2, // In btcs
2302 + BTCS_bte_m = 0x00000004, // In btcs
2303 +
2304 + BTCOMPARE_compare_b = 0, // In btcompare
2305 + BTCOMPARE_compare_m = 0x0000ffff, // In btcompare
2306 +
2307 + DEVDACS_op_b = 0, // In devdacs
2308 + DEVDACS_op_m = 0x00000001, // In devdacs
2309 + DEVDACS_op_write_v = 0,
2310 + DEVDACS_op_read_v = 1,
2311 + DEVDACS_size_b = 1, // In devdacs
2312 + DEVDACS_size_m = 0x00000006, // In devdacs
2313 + DEVDACS_size_byte_v = 0,
2314 + DEVDACS_size_halfword = 1,
2315 + DEVDACS_size_triplebyte = 2,
2316 + DEVDACS_size_word = 3,
2317 + DEVDACS_err_b = 3, // In devdacs
2318 + DEVDACS_err_m = 0x00000008, // In devdacs
2319 + DEVDACS_f_b = 4, // In devdacs
2320 + DEVDACS_f_m = 0x00000010, // In devdacs
2321 +} ;
2322 +
2323 +#endif //__IDT_DEV_H__
2324 +
2325 diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h
2326 --- linux.old/include/asm-mips/rc32434/dma.h 1970-01-01 01:00:00.000000000 +0100
2327 +++ linux.dev/include/asm-mips/rc32434/dma.h 2006-10-11 21:56:38.000000000 +0200
2328 @@ -0,0 +1,202 @@
2329 +#ifndef __IDT_DMA_H__
2330 +#define __IDT_DMA_H__
2331 +
2332 +/*******************************************************************************
2333 + *
2334 + * Copyright 2002 Integrated Device Technology, Inc.
2335 + * All rights reserved.
2336 + *
2337 + * DMA register definition.
2338 + *
2339 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2340 + *
2341 + * Author : ryan.holmQVist@idt.com
2342 + * Date : 20011005
2343 + * Update :
2344 + * $Log: dma.h,v $
2345 + * Revision 1.3 2002/06/06 18:34:03 astichte
2346 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2347 + *
2348 + * Revision 1.2 2002/06/05 18:30:46 astichte
2349 + * Removed IDTField
2350 + *
2351 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2352 + * jba File moved from vcode/include/idt/acacia
2353 + *
2354 + *
2355 + ******************************************************************************/
2356 +
2357 +#include <asm/rc32434/types.h>
2358 +enum
2359 +{
2360 + DMA0_PhysicalAddress = 0x18040000,
2361 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
2362 +
2363 + DMA0_VirtualAddress = 0xb8040000,
2364 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
2365 +} ;
2366 +
2367 +/*
2368 + * DMA descriptor (in physical memory).
2369 + */
2370 +
2371 +typedef struct DMAD_s
2372 +{
2373 + U32 control ; // Control. use DMAD_*
2374 + U32 ca ; // Current Address.
2375 + U32 devcs ; // Device control and status.
2376 + U32 link ; // Next descriptor in chain.
2377 +} volatile *DMAD_t ;
2378 +
2379 +enum
2380 +{
2381 + DMAD_size = sizeof (struct DMAD_s),
2382 + DMAD_count_b = 0, // in DMAD_t -> control
2383 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
2384 + DMAD_ds_b = 20, // in DMAD_t -> control
2385 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
2386 + DMAD_ds_ethRcv_v = 0,
2387 + DMAD_ds_ethXmt_v = 0,
2388 + DMAD_ds_memToFifo_v = 0,
2389 + DMAD_ds_fifoToMem_v = 0,
2390 + DMAD_ds_pciToMem_v = 0,
2391 + DMAD_ds_memToPci_v = 0,
2392 +
2393 + DMAD_devcmd_b = 22, // in DMAD_t -> control
2394 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
2395 + DMAD_devcmd_byte_v = 0, //memory-to-memory
2396 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
2397 + DMAD_devcmd_word_v = 2, //memory-to-memory
2398 + DMAD_devcmd_2words_v = 3, //memory-to-memory
2399 + DMAD_devcmd_4words_v = 4, //memory-to-memory
2400 + DMAD_devcmd_6words_v = 5, //memory-to-memory
2401 + DMAD_devcmd_8words_v = 6, //memory-to-memory
2402 + DMAD_devcmd_16words_v = 7, //memory-to-memory
2403 + DMAD_cof_b = 25, // chain on finished
2404 + DMAD_cof_m = 0x02000000, //
2405 + DMAD_cod_b = 26, // chain on done
2406 + DMAD_cod_m = 0x04000000, //
2407 + DMAD_iof_b = 27, // interrupt on finished
2408 + DMAD_iof_m = 0x08000000, //
2409 + DMAD_iod_b = 28, // interrupt on done
2410 + DMAD_iod_m = 0x10000000, //
2411 + DMAD_t_b = 29, // terminated
2412 + DMAD_t_m = 0x20000000, //
2413 + DMAD_d_b = 30, // done
2414 + DMAD_d_m = 0x40000000, //
2415 + DMAD_f_b = 31, // finished
2416 + DMAD_f_m = 0x80000000, //
2417 +} ;
2418 +
2419 +/*
2420 + * DMA register (within Internal Register Map).
2421 + */
2422 +
2423 +struct DMA_Chan_s
2424 +{
2425 + U32 dmac ; // Control.
2426 + U32 dmas ; // Status.
2427 + U32 dmasm ; // Mask.
2428 + U32 dmadptr ; // Descriptor pointer.
2429 + U32 dmandptr ; // Next descriptor pointer.
2430 +};
2431 +
2432 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
2433 +
2434 +//DMA_Channels use DMACH_count instead
2435 +
2436 +enum
2437 +{
2438 + DMAC_run_b = 0, //
2439 + DMAC_run_m = 0x00000001, //
2440 + DMAC_dm_b = 1, // done mask
2441 + DMAC_dm_m = 0x00000002, //
2442 + DMAC_mode_b = 2, //
2443 + DMAC_mode_m = 0x0000000c, //
2444 + DMAC_mode_auto_v = 0,
2445 + DMAC_mode_burst_v = 1,
2446 + DMAC_mode_transfer_v = 2, //usually used
2447 + DMAC_mode_reserved_v = 3,
2448 + DMAC_a_b = 4, //
2449 + DMAC_a_m = 0x00000010, //
2450 +
2451 + DMAS_f_b = 0, // finished (sticky)
2452 + DMAS_f_m = 0x00000001, //
2453 + DMAS_d_b = 1, // done (sticky)
2454 + DMAS_d_m = 0x00000002, //
2455 + DMAS_c_b = 2, // chain (sticky)
2456 + DMAS_c_m = 0x00000004, //
2457 + DMAS_e_b = 3, // error (sticky)
2458 + DMAS_e_m = 0x00000008, //
2459 + DMAS_h_b = 4, // halt (sticky)
2460 + DMAS_h_m = 0x00000010, //
2461 +
2462 + DMASM_f_b = 0, // finished (1=mask)
2463 + DMASM_f_m = 0x00000001, //
2464 + DMASM_d_b = 1, // done (1=mask)
2465 + DMASM_d_m = 0x00000002, //
2466 + DMASM_c_b = 2, // chain (1=mask)
2467 + DMASM_c_m = 0x00000004, //
2468 + DMASM_e_b = 3, // error (1=mask)
2469 + DMASM_e_m = 0x00000008, //
2470 + DMASM_h_b = 4, // halt (1=mask)
2471 + DMASM_h_m = 0x00000010, //
2472 +} ;
2473 +
2474 +/*
2475 + * DMA channel definitions
2476 + */
2477 +
2478 +enum
2479 +{
2480 + DMACH_ethRcv = 0,
2481 + DMACH_ethXmt = 1,
2482 + DMACH_memToFifo = 2,
2483 + DMACH_fifoToMem = 3,
2484 + DMACH_pciToMem = 4,
2485 + DMACH_memToPci = 5,
2486 +
2487 + DMACH_count //must be last
2488 +};
2489 +
2490 +
2491 +typedef struct DMAC_s
2492 +{
2493 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
2494 +} volatile *DMA_t ;
2495 +
2496 +
2497 +/*
2498 + * External DMA parameters
2499 +*/
2500 +#if 0
2501 +enum
2502 +{
2503 + DMADEVCMD_ts_b = 0, // ts field in devcmd
2504 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
2505 + DMADEVCMD_ts_byte_v = 0,
2506 + DMADEVCMD_ts_halfword_v = 1,
2507 + DMADEVCMD_ts_word_v = 2,
2508 + DMADEVCMD_ts_2word_v = 3,
2509 + DMADEVCMD_ts_4word_v = 4,
2510 + DMADEVCMD_ts_6word_v = 5,
2511 + DMADEVCMD_ts_8word_v = 6,
2512 + DMADEVCMD_ts_16word_v = 7
2513 +};
2514 +#endif
2515 +
2516 +#if 1 // aws - Compatibility.
2517 +# define EXTDMA_ts_b DMADEVCMD_ts_b
2518 +# define EXTDMA_ts_m DMADEVCMD_ts_m
2519 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
2520 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
2521 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
2522 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
2523 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
2524 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
2525 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
2526 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
2527 +#endif // aws - Compatibility.
2528 +
2529 +#endif // __IDT_DMA_H__
2530 +
2531 diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h
2532 --- linux.old/include/asm-mips/rc32434/dma_v.h 1970-01-01 01:00:00.000000000 +0100
2533 +++ linux.dev/include/asm-mips/rc32434/dma_v.h 2006-10-11 21:56:38.000000000 +0200
2534 @@ -0,0 +1,73 @@
2535 +#ifndef __IDT_DMA_V_H__
2536 +#define __IDT_DMA_V_H__
2537 +
2538 +/*******************************************************************************
2539 + *
2540 + * Copyright 2002 Integrated Device Technology, Inc.
2541 + * All rights reserved.
2542 + *
2543 + * DMA register definition.
2544 + *
2545 + * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
2546 + *
2547 + * Author : ryan.holmQVist@idt.com
2548 + * Date : 20011005
2549 + * Update :
2550 + * $Log: dma.h,v $
2551 + * Revision 1.3 2002/06/06 18:34:03 astichte
2552 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2553 + *
2554 + * Revision 1.2 2002/06/05 18:30:46 astichte
2555 + * Removed IDTField
2556 + *
2557 + * Revision 1.1 2002/05/29 17:33:21 sysarch
2558 + * jba File moved from vcode/include/idt/acacia
2559 + *
2560 + *
2561 + ******************************************************************************/
2562 +#include <asm/rc32434/types.h>
2563 +#include <asm/rc32434/dma.h>
2564 +#include <asm/rc32434/rc32434.h>
2565 +#define DMA_CHAN_OFFSET 0x14
2566 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
2567 +#define DMA_COUNT(count) \
2568 + ((count) & DMAD_count_m)
2569 +
2570 +#define DMA_HALT_TIMEOUT 500
2571 +
2572 +
2573 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
2574 +{
2575 + int timeout=1;
2576 + if (local_readl(&ch->dmac) & DMAC_run_m) {
2577 + local_writel(0, &ch->dmac);
2578 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
2579 + if (local_readl(&ch->dmas) & DMAS_h_m) {
2580 + local_writel(0, &ch->dmas);
2581 + break;
2582 + }
2583 + }
2584 + }
2585 +
2586 + return timeout ? 0 : 1;
2587 +}
2588 +
2589 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
2590 +{
2591 + local_writel(0, &ch->dmandptr);
2592 + local_writel(dma_addr, &ch->dmadptr);
2593 +}
2594 +
2595 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
2596 +{
2597 + local_writel(dma_addr, &ch->dmandptr);
2598 +}
2599 +
2600 +#endif // __IDT_DMA_V_H__
2601 +
2602 +
2603 +
2604 +
2605 +
2606 +
2607 +
2608 diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h
2609 --- linux.old/include/asm-mips/rc32434/eth.h 1970-01-01 01:00:00.000000000 +0100
2610 +++ linux.dev/include/asm-mips/rc32434/eth.h 2006-10-11 21:56:38.000000000 +0200
2611 @@ -0,0 +1,322 @@
2612 +#ifndef __IDT_ETH_H__
2613 +#define __IDT_ETH_H__
2614 +
2615 +/*******************************************************************************
2616 + *
2617 + * Copyright 2002 Integrated Device Technology, Inc.
2618 + * All rights reserved.
2619 + *
2620 + * Ethernet register definition.
2621 + *
2622 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2623 + *
2624 + * Author : Allen.Stichter@idt.com
2625 + * Date : 20020605
2626 + * Update :
2627 + * $Log: eth.h,v $
2628 + * Revision 1.3 2002/06/06 18:34:04 astichte
2629 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2630 + *
2631 + * Revision 1.2 2002/06/05 18:19:46 astichte
2632 + * Added
2633 + *
2634 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2635 + * jba File moved from vcode/include/idt/acacia
2636 + *
2637 + ******************************************************************************/
2638 +
2639 +#include <asm/rc32434/types.h>
2640 +
2641 +enum
2642 +{
2643 + ETH0_PhysicalAddress = 0x18060000,
2644 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
2645 +
2646 + ETH0_VirtualAddress = 0xb8060000,
2647 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
2648 +} ;
2649 +
2650 +typedef struct
2651 +{
2652 + U32 ethintfc ;
2653 + U32 ethfifott ;
2654 + U32 etharc ;
2655 + U32 ethhash0 ;
2656 + U32 ethhash1 ;
2657 + U32 ethu0 [4] ; // Reserved.
2658 + U32 ethpfs ;
2659 + U32 ethmcp ;
2660 + U32 eth_u1 [10] ; // Reserved.
2661 + U32 ethspare ;
2662 + U32 eth_u2 [42] ; // Reserved.
2663 + U32 ethsal0 ;
2664 + U32 ethsah0 ;
2665 + U32 ethsal1 ;
2666 + U32 ethsah1 ;
2667 + U32 ethsal2 ;
2668 + U32 ethsah2 ;
2669 + U32 ethsal3 ;
2670 + U32 ethsah3 ;
2671 + U32 ethrbc ;
2672 + U32 ethrpc ;
2673 + U32 ethrupc ;
2674 + U32 ethrfc ;
2675 + U32 ethtbc ;
2676 + U32 ethgpf ;
2677 + U32 eth_u9 [50] ; // Reserved.
2678 + U32 ethmac1 ;
2679 + U32 ethmac2 ;
2680 + U32 ethipgt ;
2681 + U32 ethipgr ;
2682 + U32 ethclrt ;
2683 + U32 ethmaxf ;
2684 + U32 eth_u10 ; // Reserved.
2685 + U32 ethmtest ;
2686 + U32 miimcfg ;
2687 + U32 miimcmd ;
2688 + U32 miimaddr ;
2689 + U32 miimwtd ;
2690 + U32 miimrdd ;
2691 + U32 miimind ;
2692 + U32 eth_u11 ; // Reserved.
2693 + U32 eth_u12 ; // Reserved.
2694 + U32 ethcfsa0 ;
2695 + U32 ethcfsa1 ;
2696 + U32 ethcfsa2 ;
2697 +} volatile *ETH_t;
2698 +
2699 +enum
2700 +{
2701 + ETHINTFC_en_b = 0,
2702 + ETHINTFC_en_m = 0x00000001,
2703 + ETHINTFC_its_b = 1,
2704 + ETHINTFC_its_m = 0x00000002,
2705 + ETHINTFC_rip_b = 2,
2706 + ETHINTFC_rip_m = 0x00000004,
2707 + ETHINTFC_jam_b = 3,
2708 + ETHINTFC_jam_m = 0x00000008,
2709 + ETHINTFC_ovr_b = 4,
2710 + ETHINTFC_ovr_m = 0x00000010,
2711 + ETHINTFC_und_b = 5,
2712 + ETHINTFC_und_m = 0x00000020,
2713 + ETHINTFC_iom_b = 6,
2714 + ETHINTFC_iom_m = 0x000000c0,
2715 +
2716 + ETHFIFOTT_tth_b = 0,
2717 + ETHFIFOTT_tth_m = 0x0000007f,
2718 +
2719 + ETHARC_pro_b = 0,
2720 + ETHARC_pro_m = 0x00000001,
2721 + ETHARC_am_b = 1,
2722 + ETHARC_am_m = 0x00000002,
2723 + ETHARC_afm_b = 2,
2724 + ETHARC_afm_m = 0x00000004,
2725 + ETHARC_ab_b = 3,
2726 + ETHARC_ab_m = 0x00000008,
2727 +
2728 + ETHSAL_byte5_b = 0,
2729 + ETHSAL_byte5_m = 0x000000ff,
2730 + ETHSAL_byte4_b = 8,
2731 + ETHSAL_byte4_m = 0x0000ff00,
2732 + ETHSAL_byte3_b = 16,
2733 + ETHSAL_byte3_m = 0x00ff0000,
2734 + ETHSAL_byte2_b = 24,
2735 + ETHSAL_byte2_m = 0xff000000,
2736 +
2737 + ETHSAH_byte1_b = 0,
2738 + ETHSAH_byte1_m = 0x000000ff,
2739 + ETHSAH_byte0_b = 8,
2740 + ETHSAH_byte0_m = 0x0000ff00,
2741 +
2742 + ETHGPF_ptv_b = 0,
2743 + ETHGPF_ptv_m = 0x0000ffff,
2744 +
2745 + ETHPFS_pfd_b = 0,
2746 + ETHPFS_pfd_m = 0x00000001,
2747 +
2748 + ETHCFSA0_cfsa4_b = 0,
2749 + ETHCFSA0_cfsa4_m = 0x000000ff,
2750 + ETHCFSA0_cfsa5_b = 8,
2751 + ETHCFSA0_cfsa5_m = 0x0000ff00,
2752 +
2753 + ETHCFSA1_cfsa2_b = 0,
2754 + ETHCFSA1_cfsa2_m = 0x000000ff,
2755 + ETHCFSA1_cfsa3_b = 8,
2756 + ETHCFSA1_cfsa3_m = 0x0000ff00,
2757 +
2758 + ETHCFSA2_cfsa0_b = 0,
2759 + ETHCFSA2_cfsa0_m = 0x000000ff,
2760 + ETHCFSA2_cfsa1_b = 8,
2761 + ETHCFSA2_cfsa1_m = 0x0000ff00,
2762 +
2763 + ETHMAC1_re_b = 0,
2764 + ETHMAC1_re_m = 0x00000001,
2765 + ETHMAC1_paf_b = 1,
2766 + ETHMAC1_paf_m = 0x00000002,
2767 + ETHMAC1_rfc_b = 2,
2768 + ETHMAC1_rfc_m = 0x00000004,
2769 + ETHMAC1_tfc_b = 3,
2770 + ETHMAC1_tfc_m = 0x00000008,
2771 + ETHMAC1_lb_b = 4,
2772 + ETHMAC1_lb_m = 0x00000010,
2773 + ETHMAC1_mr_b = 31,
2774 + ETHMAC1_mr_m = 0x80000000,
2775 +
2776 + ETHMAC2_fd_b = 0,
2777 + ETHMAC2_fd_m = 0x00000001,
2778 + ETHMAC2_flc_b = 1,
2779 + ETHMAC2_flc_m = 0x00000002,
2780 + ETHMAC2_hfe_b = 2,
2781 + ETHMAC2_hfe_m = 0x00000004,
2782 + ETHMAC2_dc_b = 3,
2783 + ETHMAC2_dc_m = 0x00000008,
2784 + ETHMAC2_cen_b = 4,
2785 + ETHMAC2_cen_m = 0x00000010,
2786 + ETHMAC2_pe_b = 5,
2787 + ETHMAC2_pe_m = 0x00000020,
2788 + ETHMAC2_vpe_b = 6,
2789 + ETHMAC2_vpe_m = 0x00000040,
2790 + ETHMAC2_ape_b = 7,
2791 + ETHMAC2_ape_m = 0x00000080,
2792 + ETHMAC2_ppe_b = 8,
2793 + ETHMAC2_ppe_m = 0x00000100,
2794 + ETHMAC2_lpe_b = 9,
2795 + ETHMAC2_lpe_m = 0x00000200,
2796 + ETHMAC2_nb_b = 12,
2797 + ETHMAC2_nb_m = 0x00001000,
2798 + ETHMAC2_bp_b = 13,
2799 + ETHMAC2_bp_m = 0x00002000,
2800 + ETHMAC2_ed_b = 14,
2801 + ETHMAC2_ed_m = 0x00004000,
2802 +
2803 + ETHIPGT_ipgt_b = 0,
2804 + ETHIPGT_ipgt_m = 0x0000007f,
2805 +
2806 + ETHIPGR_ipgr2_b = 0,
2807 + ETHIPGR_ipgr2_m = 0x0000007f,
2808 + ETHIPGR_ipgr1_b = 8,
2809 + ETHIPGR_ipgr1_m = 0x00007f00,
2810 +
2811 + ETHCLRT_maxret_b = 0,
2812 + ETHCLRT_maxret_m = 0x0000000f,
2813 + ETHCLRT_colwin_b = 8,
2814 + ETHCLRT_colwin_m = 0x00003f00,
2815 +
2816 + ETHMAXF_maxf_b = 0,
2817 + ETHMAXF_maxf_m = 0x0000ffff,
2818 +
2819 + ETHMTEST_tb_b = 2,
2820 + ETHMTEST_tb_m = 0x00000004,
2821 +
2822 + ETHMCP_div_b = 0,
2823 + ETHMCP_div_m = 0x000000ff,
2824 +
2825 + MIIMCFG_rsv_b = 0,
2826 + MIIMCFG_rsv_m = 0x0000000c,
2827 +
2828 + MIIMCMD_rd_b = 0,
2829 + MIIMCMD_rd_m = 0x00000001,
2830 + MIIMCMD_scn_b = 1,
2831 + MIIMCMD_scn_m = 0x00000002,
2832 +
2833 + MIIMADDR_regaddr_b = 0,
2834 + MIIMADDR_regaddr_m = 0x0000001f,
2835 + MIIMADDR_phyaddr_b = 8,
2836 + MIIMADDR_phyaddr_m = 0x00001f00,
2837 +
2838 + MIIMWTD_wdata_b = 0,
2839 + MIIMWTD_wdata_m = 0x0000ffff,
2840 +
2841 + MIIMRDD_rdata_b = 0,
2842 + MIIMRDD_rdata_m = 0x0000ffff,
2843 +
2844 + MIIMIND_bsy_b = 0,
2845 + MIIMIND_bsy_m = 0x00000001,
2846 + MIIMIND_scn_b = 1,
2847 + MIIMIND_scn_m = 0x00000002,
2848 + MIIMIND_nv_b = 2,
2849 + MIIMIND_nv_m = 0x00000004,
2850 +
2851 +} ;
2852 +
2853 +/*
2854 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
2855 + */
2856 +enum
2857 +{
2858 + ETHRX_fd_b = 0,
2859 + ETHRX_fd_m = 0x00000001,
2860 + ETHRX_ld_b = 1,
2861 + ETHRX_ld_m = 0x00000002,
2862 + ETHRX_rok_b = 2,
2863 + ETHRX_rok_m = 0x00000004,
2864 + ETHRX_fm_b = 3,
2865 + ETHRX_fm_m = 0x00000008,
2866 + ETHRX_mp_b = 4,
2867 + ETHRX_mp_m = 0x00000010,
2868 + ETHRX_bp_b = 5,
2869 + ETHRX_bp_m = 0x00000020,
2870 + ETHRX_vlt_b = 6,
2871 + ETHRX_vlt_m = 0x00000040,
2872 + ETHRX_cf_b = 7,
2873 + ETHRX_cf_m = 0x00000080,
2874 + ETHRX_ovr_b = 8,
2875 + ETHRX_ovr_m = 0x00000100,
2876 + ETHRX_crc_b = 9,
2877 + ETHRX_crc_m = 0x00000200,
2878 + ETHRX_cv_b = 10,
2879 + ETHRX_cv_m = 0x00000400,
2880 + ETHRX_db_b = 11,
2881 + ETHRX_db_m = 0x00000800,
2882 + ETHRX_le_b = 12,
2883 + ETHRX_le_m = 0x00001000,
2884 + ETHRX_lor_b = 13,
2885 + ETHRX_lor_m = 0x00002000,
2886 + ETHRX_ces_b = 14,
2887 + ETHRX_ces_m = 0x00004000,
2888 + ETHRX_length_b = 16,
2889 + ETHRX_length_m = 0xffff0000,
2890 +
2891 + ETHTX_fd_b = 0,
2892 + ETHTX_fd_m = 0x00000001,
2893 + ETHTX_ld_b = 1,
2894 + ETHTX_ld_m = 0x00000002,
2895 + ETHTX_oen_b = 2,
2896 + ETHTX_oen_m = 0x00000004,
2897 + ETHTX_pen_b = 3,
2898 + ETHTX_pen_m = 0x00000008,
2899 + ETHTX_cen_b = 4,
2900 + ETHTX_cen_m = 0x00000010,
2901 + ETHTX_hen_b = 5,
2902 + ETHTX_hen_m = 0x00000020,
2903 + ETHTX_tok_b = 6,
2904 + ETHTX_tok_m = 0x00000040,
2905 + ETHTX_mp_b = 7,
2906 + ETHTX_mp_m = 0x00000080,
2907 + ETHTX_bp_b = 8,
2908 + ETHTX_bp_m = 0x00000100,
2909 + ETHTX_und_b = 9,
2910 + ETHTX_und_m = 0x00000200,
2911 + ETHTX_of_b = 10,
2912 + ETHTX_of_m = 0x00000400,
2913 + ETHTX_ed_b = 11,
2914 + ETHTX_ed_m = 0x00000800,
2915 + ETHTX_ec_b = 12,
2916 + ETHTX_ec_m = 0x00001000,
2917 + ETHTX_lc_b = 13,
2918 + ETHTX_lc_m = 0x00002000,
2919 + ETHTX_td_b = 14,
2920 + ETHTX_td_m = 0x00004000,
2921 + ETHTX_crc_b = 15,
2922 + ETHTX_crc_m = 0x00008000,
2923 + ETHTX_le_b = 16,
2924 + ETHTX_le_m = 0x00010000,
2925 + ETHTX_cc_b = 17,
2926 + ETHTX_cc_m = 0x001E0000,
2927 +} ;
2928 +
2929 +#endif // __IDT_ETH_H__
2930 +
2931 +
2932 +
2933 +
2934 diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h
2935 --- linux.old/include/asm-mips/rc32434/eth_v.h 1970-01-01 01:00:00.000000000 +0100
2936 +++ linux.dev/include/asm-mips/rc32434/eth_v.h 2006-10-11 21:56:38.000000000 +0200
2937 @@ -0,0 +1,64 @@
2938 +#ifndef __IDT_ETH_V_H__
2939 +#define __IDT_ETH_V_H__
2940 +
2941 +/*******************************************************************************
2942 + *
2943 + * Copyright 2002 Integrated Device Technology, Inc.
2944 + * All rights reserved.
2945 + *
2946 + * Ethernet register definition.
2947 + *
2948 + * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2949 + *
2950 + * Author : Allen.Stichter@idt.com
2951 + * Date : 20020605
2952 + * Update :
2953 + * $Log: eth.h,v $
2954 + * Revision 1.3 2002/06/06 18:34:04 astichte
2955 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
2956 + *
2957 + * Revision 1.2 2002/06/05 18:19:46 astichte
2958 + * Added
2959 + *
2960 + * Revision 1.1 2002/05/29 17:33:22 sysarch
2961 + * jba File moved from vcode/include/idt/acacia
2962 + *
2963 + ******************************************************************************/
2964 +
2965 +#include <asm/rc32434/types.h>
2966 +#include <asm/rc32434/eth.h>
2967 +
2968 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
2969 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
2970 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
2971 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
2972 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
2973 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
2974 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
2975 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
2976 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
2977 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
2978 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
2979 +
2980 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
2981 +
2982 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
2983 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
2984 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
2985 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
2986 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
2987 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
2988 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
2989 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
2990 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
2991 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
2992 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
2993 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
2994 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
2995 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
2996 +#endif // __IDT_ETH_V_H__
2997 +
2998 +
2999 +
3000 +
3001 +
3002 diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h
3003 --- linux.old/include/asm-mips/rc32434/gpio.h 1970-01-01 01:00:00.000000000 +0100
3004 +++ linux.dev/include/asm-mips/rc32434/gpio.h 2006-10-11 21:56:38.000000000 +0200
3005 @@ -0,0 +1,182 @@
3006 +#ifndef __IDT_GPIO_H__
3007 +#define __IDT_GPIO_H__
3008 +
3009 +/*******************************************************************************
3010 + *
3011 + * Copyright 2002 Integrated Device Technology, Inc.
3012 + * All rights reserved.
3013 + *
3014 + * GPIO register definition.
3015 + *
3016 + * File : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3017 + *
3018 + * Author : ryan.holmQVist@idt.com
3019 + * Date : 20011005
3020 + * Update :
3021 + * $Log: gpio.h,v $
3022 + * Revision 1.2 2002/06/06 18:34:04 astichte
3023 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3024 + *
3025 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3026 + * jba File moved from vcode/include/idt/acacia
3027 + *
3028 + *
3029 + ******************************************************************************/
3030 +
3031 +#include <asm/rc32434/types.h>
3032 +enum
3033 +{
3034 + GPIO0_PhysicalAddress = 0x18050000,
3035 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
3036 +
3037 + GPIO0_VirtualAddress = 0xb8050000,
3038 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
3039 +} ;
3040 +
3041 +typedef struct
3042 +{
3043 + U32 gpiofunc; /* GPIO Function Register
3044 + * gpiofunc[x]==0 bit = gpio
3045 + * func[x]==1 bit = altfunc
3046 + */
3047 + U32 gpiocfg; /* GPIO Configuration Register
3048 + * gpiocfg[x]==0 bit = input
3049 + * gpiocfg[x]==1 bit = output
3050 + */
3051 + U32 gpiod; /* GPIO Data Register
3052 + * gpiod[x] read/write gpio pinX status
3053 + */
3054 + U32 gpioilevel; /* GPIO Interrupt Status Register
3055 + * interrupt level (see gpioistat)
3056 + */
3057 + U32 gpioistat; /* Gpio Interrupt Status Register
3058 + * istat[x] = (gpiod[x] == level[x])
3059 + * cleared in ISR (STICKY bits)
3060 + */
3061 + U32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
3062 +} volatile * GPIO_t ;
3063 +
3064 +typedef enum
3065 +{
3066 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
3067 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
3068 + GPIO_input_v = 0, // gpiocfg use pin as input.
3069 + GPIO_output_v = 1, // gpiocfg use pin as output.
3070 + GPIO_pin0_b = 0,
3071 + GPIO_pin0_m = 0x00000001,
3072 + GPIO_pin1_b = 1,
3073 + GPIO_pin1_m = 0x00000002,
3074 + GPIO_pin2_b = 2,
3075 + GPIO_pin2_m = 0x00000004,
3076 + GPIO_pin3_b = 3,
3077 + GPIO_pin3_m = 0x00000008,
3078 + GPIO_pin4_b = 4,
3079 + GPIO_pin4_m = 0x00000010,
3080 + GPIO_pin5_b = 5,
3081 + GPIO_pin5_m = 0x00000020,
3082 + GPIO_pin6_b = 6,
3083 + GPIO_pin6_m = 0x00000040,
3084 + GPIO_pin7_b = 7,
3085 + GPIO_pin7_m = 0x00000080,
3086 + GPIO_pin8_b = 8,
3087 + GPIO_pin8_m = 0x00000100,
3088 + GPIO_pin9_b = 9,
3089 + GPIO_pin9_m = 0x00000200,
3090 + GPIO_pin10_b = 10,
3091 + GPIO_pin10_m = 0x00000400,
3092 + GPIO_pin11_b = 11,
3093 + GPIO_pin11_m = 0x00000800,
3094 + GPIO_pin12_b = 12,
3095 + GPIO_pin12_m = 0x00001000,
3096 + GPIO_pin13_b = 13,
3097 + GPIO_pin13_m = 0x00002000,
3098 + GPIO_pin14_b = 14,
3099 + GPIO_pin14_m = 0x00004000,
3100 + GPIO_pin15_b = 15,
3101 + GPIO_pin15_m = 0x00008000,
3102 + GPIO_pin16_b = 16,
3103 + GPIO_pin16_m = 0x00010000,
3104 + GPIO_pin17_b = 17,
3105 + GPIO_pin17_m = 0x00020000,
3106 + GPIO_pin18_b = 18,
3107 + GPIO_pin18_m = 0x00040000,
3108 + GPIO_pin19_b = 19,
3109 + GPIO_pin19_m = 0x00080000,
3110 + GPIO_pin20_b = 20,
3111 + GPIO_pin20_m = 0x00100000,
3112 + GPIO_pin21_b = 21,
3113 + GPIO_pin21_m = 0x00200000,
3114 + GPIO_pin22_b = 22,
3115 + GPIO_pin22_m = 0x00400000,
3116 + GPIO_pin23_b = 23,
3117 + GPIO_pin23_m = 0x00800000,
3118 + GPIO_pin24_b = 24,
3119 + GPIO_pin24_m = 0x01000000,
3120 + GPIO_pin25_b = 25,
3121 + GPIO_pin25_m = 0x02000000,
3122 + GPIO_pin26_b = 26,
3123 + GPIO_pin26_m = 0x04000000,
3124 + GPIO_pin27_b = 27,
3125 + GPIO_pin27_m = 0x08000000,
3126 + GPIO_pin28_b = 28,
3127 + GPIO_pin28_m = 0x10000000,
3128 + GPIO_pin29_b = 29,
3129 + GPIO_pin29_m = 0x20000000,
3130 + GPIO_pin30_b = 30,
3131 + GPIO_pin30_m = 0x40000000,
3132 + GPIO_pin31_b = 31,
3133 + GPIO_pin31_m = 0x80000000,
3134 +
3135 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
3136 +
3137 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
3138 + GPIO_u0sout_m = GPIO_pin0_m,
3139 + GPIO_u0sout_cfg_v = GPIO_output_v,
3140 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
3141 + GPIO_u0sinp_m = GPIO_pin1_m,
3142 + GPIO_u0sinp_cfg_v = GPIO_input_v,
3143 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
3144 + GPIO_u0rtsn_m = GPIO_pin2_m,
3145 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
3146 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
3147 + GPIO_u0ctsn_m = GPIO_pin3_m,
3148 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
3149 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
3150 + GPIO_maddr22_m = GPIO_pin4_m,
3151 + GPIO_maddr22_cfg_v = GPIO_output_v,
3152 +
3153 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
3154 + GPIO_maddr23_m = GPIO_pin5_m,
3155 + GPIO_maddr23_cfg_v = GPIO_output_v,
3156 +
3157 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
3158 + GPIO_maddr24_m = GPIO_pin6_m,
3159 + GPIO_maddr24_cfg_v = GPIO_output_v,
3160 +
3161 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
3162 + GPIO_maddr25_m = GPIO_pin7_m,
3163 + GPIO_maddr25_cfg_v = GPIO_output_v,
3164 +
3165 + GPIO_cpu_b = GPIO_pin8_b, // M&P bus bit 25.
3166 + GPIO_cpu_m = GPIO_pin8_m,
3167 + GPIO_cpu_cfg_v = GPIO_output_v,
3168 + GPIO_afspare6_b = GPIO_pin9_b, // reserved.
3169 + GPIO_afspare6_m = GPIO_pin9_m,
3170 + GPIO_afspare6_cfg_v = GPIO_input_v,
3171 + GPIO_afspare4_b = GPIO_pin10_b, // reserved.
3172 + GPIO_afspare4_m = GPIO_pin10_m,
3173 + GPIO_afspare4_cfg_v = GPIO_input_v,
3174 + GPIO_afspare3_b = GPIO_pin11_b, // reserved.
3175 + GPIO_afspare3_m = GPIO_pin11_m,
3176 + GPIO_afspare3_cfg_v = GPIO_input_v,
3177 + GPIO_afspare2_b = GPIO_pin12_b, // reserved.
3178 + GPIO_afspare2_m = GPIO_pin12_m,
3179 + GPIO_afspare2_cfg_v = GPIO_input_v,
3180 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
3181 + GPIO_pcimuintn_m = GPIO_pin13_m,
3182 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
3183 +
3184 +} GPIO_DEFS_t;
3185 +
3186 +#endif // __IDT_GPIO_H__
3187 +
3188 diff -urN linux.old/include/asm-mips/rc32434/i2c.h linux.dev/include/asm-mips/rc32434/i2c.h
3189 --- linux.old/include/asm-mips/rc32434/i2c.h 1970-01-01 01:00:00.000000000 +0100
3190 +++ linux.dev/include/asm-mips/rc32434/i2c.h 2006-10-11 21:56:38.000000000 +0200
3191 @@ -0,0 +1,147 @@
3192 +#ifndef __IDT_I2C_H__
3193 +#define __IDT_I2C_H__
3194 +
3195 +/*******************************************************************************
3196 + *
3197 + * Copyright 2002 Integrated Device Technology, Inc.
3198 + * All rights reserved.
3199 + *
3200 + * I2C register definitions.
3201 + *
3202 + * File : $Id: i2c.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
3203 + *
3204 + * Author : Allen.Stichter@idt.com
3205 + * Date : 20020120
3206 + * Update :
3207 + * $Log: i2c.h,v $
3208 + * Revision 1.2 2002/06/06 18:34:04 astichte
3209 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3210 + *
3211 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3212 + * jba File moved from vcode/include/idt/acacia
3213 + *
3214 + *
3215 + ******************************************************************************/
3216 +
3217 +#include <asm/rc32434/types.h>
3218 +
3219 +enum
3220 +{
3221 + I2C0_PhysicalAddress = 0x18068000,
3222 + I2C_PhysicalAddress = I2C0_PhysicalAddress,
3223 +
3224 + I2C0_VirtualAddress = 0xb8068000,
3225 + I2C_VirtualAddress = I2C0_VirtualAddress,
3226 +} ;
3227 +
3228 +typedef struct
3229 +{
3230 + U32 i2cc ;
3231 + U32 i2cdi ;
3232 + U32 i2cdo ;
3233 + U32 i2ccp ; // I2C clk = ICLK / div / 8
3234 + U32 i2cmcmd ;
3235 + U32 i2cms ;
3236 + U32 i2cmsm ;
3237 + U32 i2css ;
3238 + U32 i2cssm ;
3239 + U32 i2csaddr ;
3240 + U32 i2csack ;
3241 +} volatile * I2C_t ;
3242 +enum
3243 +{
3244 + I2CC_men_b = 0, // In I2C-> i2cc
3245 + I2CC_men_m = 0x00000001,
3246 + I2CC_sen_b = 1, // In I2C-> i2cc
3247 + I2CC_sen_m = 0x00000002,
3248 + I2CC_iom_b = 2, // In I2C-> i2cc
3249 + I2CC_iom_m = 0x00000004,
3250 +
3251 + I2CDI_data_b = 0, // In I2C-> i2cdi
3252 + I2CDI_data_m = 0x000000ff,
3253 +
3254 + I2CDO_data_b = 0, // In I2C-> i2cdo
3255 + I2CDO_data_m = 0x000000ff,
3256 +
3257 + I2CCP_div_b = 0, // In I2C-> i2ccp
3258 + I2CCP_div_m = 0x0000ffff,
3259 +
3260 + I2CMCMD_cmd_b = 0, // In I2C-> i2cmcmd
3261 + I2CMCMD_cmd_m = 0x0000000f,
3262 + I2CMCMD_cmd_nop_v = 0,
3263 + I2CMCMD_cmd_start_v = 1,
3264 + I2CMCMD_cmd_stop_v = 2,
3265 + I2CMCMD_cmd_res3_v = 3,
3266 + I2CMCMD_cmd_rd_v = 4,
3267 + I2CMCMD_cmd_rdack_v = 5,
3268 + I2CMCMD_cmd_wd_v = 6,
3269 + I2CMCMD_cmd_wdack_v = 7,
3270 + I2CMCMD_cmd_res8_v = 8,
3271 + I2CMCMD_cmd_res9_v = 9,
3272 + I2CMCMD_cmd_res10_v = 10,
3273 + I2CMCMD_cmd_res11_v = 11,
3274 + I2CMCMD_cmd_res12_v = 12,
3275 + I2CMCMD_cmd_res13_v = 13,
3276 + I2CMCMD_cmd_res14_v = 14,
3277 + I2CMCMD_cmd_res15_v = 15,
3278 +
3279 + I2CMS_d_b = 0, // In I2C-> i2cms
3280 + I2CMS_d_m = 0x00000001,
3281 + I2CMS_na_b = 1, // In I2C-> i2cms
3282 + I2CMS_na_m = 0x00000002,
3283 + I2CMS_la_b = 2, // In I2C-> i2cms
3284 + I2CMS_la_m = 0x00000004,
3285 + I2CMS_err_b = 3, // In I2C-> i2cms
3286 + I2CMS_err_m = 0x00000008,
3287 +
3288 + I2CMSM_d_b = 0, // In I2C-> i2cmsm
3289 + I2CMSM_d_m = 0x00000001,
3290 + I2CMSM_na_b = 1, // In I2C-> i2cmsm
3291 + I2CMSM_na_m = 0x00000002,
3292 + I2CMSM_la_b = 2, // In I2C-> i2cmsm
3293 + I2CMSM_la_m = 0x00000004,
3294 + I2CMSM_err_b = 3, // In I2C-> i2cmsm
3295 + I2CMSM_err_m = 0x00000008,
3296 +
3297 + I2CSS_rr_b = 0, // In I2C-> i2css
3298 + I2CSS_rr_m = 0x00000001,
3299 + I2CSS_wr_b = 1, // In I2C-> i2css
3300 + I2CSS_wr_m = 0x00000002,
3301 + I2CSS_sa_b = 2, // In I2C-> i2css
3302 + I2CSS_sa_m = 0x00000004,
3303 + I2CSS_tf_b = 3, // In I2C-> i2css
3304 + I2CSS_tf_m = 0x00000008,
3305 + I2CSS_gc_b = 4, // In I2C-> i2css
3306 + I2CSS_gc_m = 0x00000010,
3307 + I2CSS_na_b = 5, // In I2C-> i2css
3308 + I2CSS_na_m = 0x00000020,
3309 + I2CSS_err_b = 6, // In I2C-> i2css
3310 + I2CSS_err_m = 0x00000040,
3311 +
3312 + I2CSSM_rr_b = 0, // In I2C-> i2cssm
3313 + I2CSSM_rr_m = 0x00000001,
3314 + I2CSSM_wr_b = 1, // In I2C-> i2cssm
3315 + I2CSSM_wr_m = 0x00000002,
3316 + I2CSSM_sa_b = 2, // In I2C-> i2cssm
3317 + I2CSSM_sa_m = 0x00000004,
3318 + I2CSSM_tf_b = 3, // In I2C-> i2cssm
3319 + I2CSSM_tf_m = 0x00000008,
3320 + I2CSSM_gc_b = 4, // In I2C-> i2cssm
3321 + I2CSSM_gc_m = 0x00000010,
3322 + I2CSSM_na_b = 5, // In I2C-> i2cssm
3323 + I2CSSM_na_m = 0x00000020,
3324 + I2CSSM_err_b = 6, // In I2C-> i2cssm
3325 + I2CSSM_err_m = 0x00000040,
3326 +
3327 + I2CSADDR_addr_b = 0, // In I2C-> i2csaddr
3328 + I2CSADDR_addr_m = 0x000003ff,
3329 + I2CSADDR_a_gc_b = 10, // In I2C-> i2csaddr
3330 + I2CSADDR_a_gc_m = 0x00000400,
3331 + I2CSADDR_a10_b = 11, // In I2C-> i2csaddr
3332 + I2CSADDR_a10_m = 0x00000800,
3333 +
3334 + I2CSACK_ack_b = 0, // In I2C-> i2csack
3335 + I2CSACK_ack_m = 0x00000001,
3336 +
3337 +} ;
3338 +#endif // __IDT_I2C_H__
3339 diff -urN linux.old/include/asm-mips/rc32434/integ.h linux.dev/include/asm-mips/rc32434/integ.h
3340 --- linux.old/include/asm-mips/rc32434/integ.h 1970-01-01 01:00:00.000000000 +0100
3341 +++ linux.dev/include/asm-mips/rc32434/integ.h 2006-10-11 21:56:38.000000000 +0200
3342 @@ -0,0 +1,78 @@
3343 +#ifndef __IDT_INTEG_H__
3344 +#define __IDT_INTEG_H__
3345 +
3346 +/*******************************************************************************
3347 + *
3348 + * Copyright 2002 Integrated Device Technology, Inc.
3349 + * All rights reserved.
3350 + *
3351 + * System Integrity register definition.
3352 + *
3353 + * File : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3354 + *
3355 + * Author : ryan.holmQVist@idt.com
3356 + * Date : 20011005
3357 + * Update :
3358 + * $Log: integ.h,v $
3359 + * Revision 1.3 2002/06/06 18:34:04 astichte
3360 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3361 + *
3362 + * Revision 1.2 2002/06/05 18:32:33 astichte
3363 + * Removed IDTField
3364 + *
3365 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3366 + * jba File moved from vcode/include/idt/acacia
3367 + *
3368 + ******************************************************************************/
3369 +
3370 +#include <asm/rc32434/types.h>
3371 +
3372 +enum
3373 +{
3374 + INTEG0_PhysicalAddress = 0x18030000,
3375 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
3376 +
3377 + INTEG0_VirtualAddress = 0xb8030000,
3378 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
3379 +} ;
3380 +
3381 +// if you are looing for CEA, try rst.h
3382 +typedef struct
3383 +{
3384 + U32 filler [0xc] ; // 0x30 bytes unused.
3385 + U32 errcs ; // sticky use ERRCS_
3386 + U32 wtcount ; // Watchdog timer count reg.
3387 + U32 wtcompare ; // Watchdog timer timeout value.
3388 + U32 wtc ; // Watchdog timer control. use WTC_
3389 +} volatile *INTEG_t ;
3390 +
3391 +enum
3392 +{
3393 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
3394 + ERRCS_wto_m = 0x00000001,
3395 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
3396 + ERRCS_wne_m = 0x00000002,
3397 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
3398 + ERRCS_ucw_m = 0x00000004,
3399 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
3400 + ERRCS_ucr_m = 0x00000008,
3401 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
3402 + ERRCS_upw_m = 0x00000010,
3403 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
3404 + ERRCS_upr_m = 0x00000020,
3405 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
3406 + ERRCS_udw_m = 0x00000040,
3407 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
3408 + ERRCS_udr_m = 0x00000080,
3409 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
3410 + ERRCS_sae_m = 0x00000100,
3411 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
3412 + ERRCS_wre_m = 0x00000200,
3413 +
3414 + WTC_en_b = 0, // In INTEG_t -> wtc
3415 + WTC_en_m = 0x00000001,
3416 + WTC_to_b = 1, // In INTEG_t -> wtc
3417 + WTC_to_m = 0x00000002,
3418 +} ;
3419 +
3420 +#endif // __IDT_INTEG_H__
3421 diff -urN linux.old/include/asm-mips/rc32434/int.h linux.dev/include/asm-mips/rc32434/int.h
3422 --- linux.old/include/asm-mips/rc32434/int.h 1970-01-01 01:00:00.000000000 +0100
3423 +++ linux.dev/include/asm-mips/rc32434/int.h 2006-10-11 21:56:38.000000000 +0200
3424 @@ -0,0 +1,167 @@
3425 +#ifndef __IDT_INT_H__
3426 +#define __IDT_INT_H__
3427 +
3428 +/*******************************************************************************
3429 + *
3430 + * Copyright 2002 Integrated Device Technology, Inc.
3431 + * All rights reserved.
3432 + *
3433 + * Interrupt Controller register definition.
3434 + *
3435 + * File : $Id: int.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3436 + *
3437 + * Author : ryan.holmqvist@idt.com
3438 + * Date : 20011005
3439 + * Update :
3440 + * $Log: int.h,v $
3441 + * Revision 1.3 2002/06/06 18:34:04 astichte
3442 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3443 + *
3444 + * Revision 1.2 2002/06/05 18:47:33 astichte
3445 + * Removed IDTField
3446 + *
3447 + * Revision 1.1 2002/05/29 17:33:22 sysarch
3448 + * jba File moved from vcode/include/idt/acacia
3449 + *
3450 + *
3451 + ******************************************************************************/
3452 +
3453 +#include <asm/rc32434/types.h>
3454 +
3455 +enum
3456 +{
3457 + INT0_PhysicalAddress = 0x18038000,
3458 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
3459 +
3460 + INT0_VirtualAddress = 0xb8038000,
3461 + INT_VirtualAddress = INT0_VirtualAddress, // Default
3462 +} ;
3463 +
3464 +struct INT_s
3465 +{
3466 + U32 ipend ; //Pending interrupts. use INT?_
3467 + U32 itest ; //Test bits. use INT?_
3468 + U32 imask ; //Interrupt disabled when set. use INT?_
3469 +} ;
3470 +
3471 +enum
3472 +{
3473 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
3474 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
3475 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
3476 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
3477 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
3478 +
3479 + IPEND_count, // must be last (used in loops)
3480 + IPEND_min = IPEND2 // min IPEND (used in loops)
3481 +};
3482 +
3483 +typedef struct INTC_s
3484 +{
3485 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
3486 + U32 nmips ; // use NMIPS_
3487 +} volatile *INT_t ;
3488 +
3489 +enum
3490 +{
3491 + INT2_timer0_b = 0,
3492 + INT2_timer0_m = 0x00000001,
3493 + INT2_timer1_b = 1,
3494 + INT2_timer1_m = 0x00000002,
3495 + INT2_timer2_b = 2,
3496 + INT2_timer2_m = 0x00000004,
3497 + INT2_refresh_b = 3,
3498 + INT2_refresh_m = 0x00000008,
3499 + INT2_watchdogTimeout_b = 4,
3500 + INT2_watchdogTimeout_m = 0x00000010,
3501 + INT2_undecodedCpuWrite_b = 5,
3502 + INT2_undecodedCpuWrite_m = 0x00000020,
3503 + INT2_undecodedCpuRead_b = 6,
3504 + INT2_undecodedCpuRead_m = 0x00000040,
3505 + INT2_undecodedPciWrite_b = 7,
3506 + INT2_undecodedPciWrite_m = 0x00000080,
3507 + INT2_undecodedPciRead_b = 8,
3508 + INT2_undecodedPciRead_m = 0x00000100,
3509 + INT2_undecodedDmaWrite_b = 9,
3510 + INT2_undecodedDmaWrite_m = 0x00000200,
3511 + INT2_undecodedDmaRead_b = 10,
3512 + INT2_undecodedDmaRead_m = 0x00000400,
3513 + INT2_ipBusSlaveAckError_b = 11,
3514 + INT2_ipBusSlaveAckError_m = 0x00000800,
3515 +
3516 + INT3_dmaChannel0_b = 0,
3517 + INT3_dmaChannel0_m = 0x00000001,
3518 + INT3_dmaChannel1_b = 1,
3519 + INT3_dmaChannel1_m = 0x00000002,
3520 + INT3_dmaChannel2_b = 2,
3521 + INT3_dmaChannel2_m = 0x00000004,
3522 + INT3_dmaChannel3_b = 3,
3523 + INT3_dmaChannel3_m = 0x00000008,
3524 + INT3_dmaChannel4_b = 4,
3525 + INT3_dmaChannel4_m = 0x00000010,
3526 + INT3_dmaChannel5_b = 5,
3527 + INT3_dmaChannel5_m = 0x00000020,
3528 +
3529 + INT5_uartGeneral0_b = 0,
3530 + INT5_uartGeneral0_m = 0x00000001,
3531 + INT5_uartTxrdy0_b = 1,
3532 + INT5_uartTxrdy0_m = 0x00000002,
3533 + INT5_uartRxrdy0_b = 2,
3534 + INT5_uartRxrdy0_m = 0x00000004,
3535 + INT5_pci_b = 3,
3536 + INT5_pci_m = 0x00000008,
3537 + INT5_pciDecoupled_b = 4,
3538 + INT5_pciDecoupled_m = 0x00000010,
3539 + INT5_spi_b = 5,
3540 + INT5_spi_m = 0x00000020,
3541 + INT5_deviceDecoupled_b = 6,
3542 + INT5_deviceDecoupled_m = 0x00000040,
3543 + INT5_i2cMaster_b = 7,
3544 + INT5_i2cMaster_m = 0x00000080,
3545 + INT5_i2cSlave_b = 8,
3546 + INT5_i2cSlave_m = 0x00000100,
3547 + INT5_ethOvr_b = 9,
3548 + INT5_ethOvr_m = 0x00000200,
3549 + INT5_ethUnd_b = 10,
3550 + INT5_ethUnd_m = 0x00000400,
3551 + INT5_ethPfd_b = 11,
3552 + INT5_ethPfd_m = 0x00000800,
3553 + INT5_nvram_b = 12,
3554 + INT5_nvram_m = 0x00001000,
3555 +
3556 + INT6_gpio0_b = 0,
3557 + INT6_gpio0_m = 0x00000001,
3558 + INT6_gpio1_b = 1,
3559 + INT6_gpio1_m = 0x00000002,
3560 + INT6_gpio2_b = 2,
3561 + INT6_gpio2_m = 0x00000004,
3562 + INT6_gpio3_b = 3,
3563 + INT6_gpio3_m = 0x00000008,
3564 + INT6_gpio4_b = 4,
3565 + INT6_gpio4_m = 0x00000010,
3566 + INT6_gpio5_b = 5,
3567 + INT6_gpio5_m = 0x00000020,
3568 + INT6_gpio6_b = 6,
3569 + INT6_gpio6_m = 0x00000040,
3570 + INT6_gpio7_b = 7,
3571 + INT6_gpio7_m = 0x00000080,
3572 + INT6_gpio8_b = 8,
3573 + INT6_gpio8_m = 0x00000100,
3574 + INT6_gpio9_b = 9,
3575 + INT6_gpio9_m = 0x00000200,
3576 + INT6_gpio10_b = 10,
3577 + INT6_gpio10_m = 0x00000400,
3578 + INT6_gpio11_b = 11,
3579 + INT6_gpio11_m = 0x00000800,
3580 + INT6_gpio12_b = 12,
3581 + INT6_gpio12_m = 0x00001000,
3582 + INT6_gpio13_b = 13,
3583 + INT6_gpio13_m = 0x00002000,
3584 +
3585 + NMIPS_gpio_b = 0,
3586 + NMIPS_gpio_m = 0x00000001,
3587 +} ;
3588 +
3589 +#endif // __IDT_INT_H__
3590 +
3591 +
3592 diff -urN linux.old/include/asm-mips/rc32434/iparb.h linux.dev/include/asm-mips/rc32434/iparb.h
3593 --- linux.old/include/asm-mips/rc32434/iparb.h 1970-01-01 01:00:00.000000000 +0100
3594 +++ linux.dev/include/asm-mips/rc32434/iparb.h 2006-10-11 21:56:38.000000000 +0200
3595 @@ -0,0 +1,95 @@
3596 +#ifndef __IDT_IPARB_H__
3597 +#define __IDT_IPARB_H__
3598 +
3599 +/*******************************************************************************
3600 + *
3601 + * Copyright 2002 Integrated Device Technology, Inc.
3602 + * All rights reserved.
3603 + *
3604 + * IP Arbiter register definitions.
3605 + *
3606 + * File : $Id: iparb.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
3607 + *
3608 + * Author : Allen.Stichter@idt.com
3609 + * Date : 20020120
3610 + * Update :
3611 + * $Log: iparb.h,v $
3612 + * Revision 1.3 2002/06/06 18:34:04 astichte
3613 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
3614 + *
3615 + * Revision 1.2 2002/06/05 19:01:42 astichte
3616 + * Removed IDTField
3617 + *
3618 + * Revision 1.1 2002/05/29 17:33:23 sysarch
3619 + * jba File moved from vcode/include/idt/acacia
3620 + *
3621 + ******************************************************************************/
3622 +
3623 +#include <asm/rc32434/types.h>
3624 +
3625 +enum
3626 +{
3627 + IPARB0_PhysicalAddress = 0x18048000,
3628 + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
3629 +
3630 + IPARB0_VirtualAddress = 0xb8048000,
3631 + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
3632 +} ;
3633 +
3634 +enum
3635 +{
3636 + IPABMXC_ethernetReceive = 0,
3637 + IPABMXC_ethernetTransmit = 1,
3638 + IPABMXC_memoryToHoldFifo = 2,
3639 + IPABMXC_holdFifoToMemory = 3,
3640 + IPABMXC_pciToMemory = 4,
3641 + IPABMXC_memoryToPci = 5,
3642 + IPABMXC_pciTarget = 6,
3643 + IPABMXC_pciTargetStart = 7,
3644 + IPABMXC_cpuToIpBus = 8,
3645 +
3646 + IPABMXC_Count, // Must be last in list !
3647 + IPABMXC_Min = IPABMXC_ethernetReceive,
3648 +
3649 + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
3650 +} ;
3651 +
3652 +typedef struct
3653 +{
3654 + U32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
3655 + U32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
3656 + U32 ipac ; // use IPAC_
3657 + U32 ipaitcc; // use IPAITCC_
3658 + U32 ipaspare ;
3659 +} volatile * IPARB_t ;
3660 +
3661 +enum
3662 +{
3663 + IPAC_dwm_b = 2,
3664 + IPAC_dwm_m = 0x00000004,
3665 + IPAC_drm_b = 3,
3666 + IPAC_drm_m = 0x00000008,
3667 + IPAC_msk_b = 4,
3668 + IPAC_msk_m = 0x00000010,
3669 +
3670 + IPAPC_ptc_b = 0,
3671 + IPAPC_ptc_m = 0x00003fff,
3672 + IPAPC_mf_b = 14,
3673 + IPAPC_mf_m = 0x00004000,
3674 + IPAPC_cptc_b = 16,
3675 + IPAPC_cptc_m = 0x3fff0000,
3676 +
3677 + IPAITCC_itcc = 0,
3678 + IPAITCC_itcc, = 0x000001ff,
3679 +
3680 + IPABMC_mtc_b = 0,
3681 + IPABMC_mtc_m = 0x00000fff,
3682 + IPABMC_p_b = 12,
3683 + IPABMC_p_m = 0x00003000,
3684 + IPABMC_msk_b = 14,
3685 + IPABMC_msk_m = 0x00004000,
3686 + IPABMC_cmtc_b = 16,
3687 + IPABMC_cmtc_m = 0x0fff0000,
3688 +};
3689 +
3690 +#endif // __IDT_IPARB_H__
3691 diff -urN linux.old/include/asm-mips/rc32434/irm.h linux.dev/include/asm-mips/rc32434/irm.h
3692 --- linux.old/include/asm-mips/rc32434/irm.h 1970-01-01 01:00:00.000000000 +0100
3693 +++ linux.dev/include/asm-mips/rc32434/irm.h 2006-10-11 21:56:38.000000000 +0200
3694 @@ -0,0 +1,55 @@
3695 +#ifndef __IDT_IRM_H__
3696 +#define __IDT_IRM_H__
3697 +
3698 +/*******************************************************************************
3699 + *
3700 + * Copyright 2002 Integrated Device Technology, Inc.
3701 + * All rights reserved.
3702 + *
3703 + * Internal Register Map
3704 + *
3705 + * File : $Id: irm.h,v 1.2 2002/06/05 14:51:06 astichte Exp $
3706 + *
3707 + * Author : Allen.Stichter@idt.com
3708 + * Date : 20020605
3709 + * Update :
3710 + * $Log: irm.h,v $
3711 + * Revision 1.2 2002/06/05 14:51:06 astichte
3712 + * *** empty log message ***
3713 + *
3714 + * Revision 1.1 2002/05/29 17:33:23 sysarch
3715 + * jba File moved from vcode/include/idt/acacia
3716 + *
3717 + ******************************************************************************/
3718 +
3719 +/*
3720 + * NOTE --
3721 + * This file is here for backwards compatibility.
3722 + * DO NOT USE !!!!
3723 + */
3724 +
3725 +typedef enum
3726 +{
3727 + IRM_Physical = 0x18000000, // Internal Reg. map physical.
3728 + RST_Offset = 0x00000000, // Includes sysid and RST.
3729 + DEV_Offset = 0x00010000, // Device Controller 0.
3730 + DDR_Offset = 0x00018000, // Double-Data-Rate mem. controller.
3731 + PMARB_Offset = 0x00020000, // PM bus arbiter.
3732 + TIM_Offset = 0x00028000, // Counter / timer.
3733 + INTEG_Offset = 0x00030000, // System Integrity.
3734 + INT_Offset = 0x00038000, // Interrupt controller.
3735 + DMA_Offset = 0x00040000, // DMA.
3736 + IPARB_Offset = 0x00044000, // IP bus arbiter.
3737 + GPIO_Offset = 0x00050000, // GPIO.
3738 + UART_Offset = 0x00058000, // UART
3739 + ETH_Offset = 0x00060000, // Ethernet 1.
3740 + I2C_Offset = 0x00068000, // I2C interface.
3741 + SPI_Offset = 0x00070000, // Serial Peripheral Interface.
3742 + NVRAM_Offset = 0x00078000, // NVRAM interface
3743 + AUTH_Offset = 0x0007c000, // Authorization unit
3744 + PCI_Offset = 0x00080000,
3745 + CROM_Offset = 0x000b8000, // Configuration ROM.
3746 + IRM_Size = 0x00200000, // Internal Reg. map size.
3747 +} IRM_Offset_t ;
3748 +
3749 +#endif // __IDT_IRM_H__
3750 diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h
3751 --- linux.old/include/asm-mips/rc32434/irq.h 1970-01-01 01:00:00.000000000 +0100
3752 +++ linux.dev/include/asm-mips/rc32434/irq.h 2006-10-11 21:56:38.000000000 +0200
3753 @@ -0,0 +1,8 @@
3754 +#ifndef __ASM_MACH_MIPS_IRQ_H
3755 +#define __ASM_MACH_MIPS_IRQ_H
3756 +
3757 +#include <linux/config.h>
3758 +
3759 +#define NR_IRQS 256
3760 +
3761 +#endif /* __ASM_MACH_MIPS_IRQ_H */
3762 diff -urN linux.old/include/asm-mips/rc32434/nvram.h linux.dev/include/asm-mips/rc32434/nvram.h
3763 --- linux.old/include/asm-mips/rc32434/nvram.h 1970-01-01 01:00:00.000000000 +0100
3764 +++ linux.dev/include/asm-mips/rc32434/nvram.h 2006-10-11 21:56:38.000000000 +0200
3765 @@ -0,0 +1,97 @@
3766 +#ifndef __IDT_NVRAM_H
3767 +#define __IDT_NVRAM_H
3768 +
3769 +/*******************************************************************************
3770 + *
3771 + * Copyright 2002 Integrated Device Technology, Inc.
3772 + * All rights reserved.
3773 + *
3774 + * IP Arbiter register definitions.
3775 + *
3776 + * File : $Id: nvram.h,v 1.3 2003/07/24 18:34:04 astichte Exp $
3777 + *
3778 + * Author : kiran.rao@idt.com
3779 + * Date : 20030724
3780 + * Update :
3781 + * $Log: nvram.h,v $
3782 + *
3783 + *
3784 + ******************************************************************************/
3785 +#include <asm/rc32434/tpes.h>
3786 +
3787 +
3788 +enum
3789 +{
3790 + NVRAM0_PhysicalAddress = 0xba000000,
3791 + NVRAM_PhysicalAddress = NVRAM0_PhysicalAddress, // Default
3792 +
3793 + NVRAM0_VirtualAddress = 0xba000000,
3794 + NVRAM_VirtualAddress = NVRAM0_VirtualAddress, // Default
3795 +} ;
3796 +
3797 +enum
3798 +{
3799 + NVRCMD_cmd_b = 0,
3800 + NVRCMD_cmd_m = 0x0000007f,
3801 +
3802 + NVRS_r_b = 0,
3803 + NVRS_r_m = 0x00000001,
3804 + NVRS_e_b = 1,
3805 + NVRS_e_m = 0x00000002,
3806 + NVRS_k_b = 2,
3807 + NVRS_k_m = 0x00000004,
3808 +
3809 + NVRSM_r_b = 0,
3810 + NVRSM_r_m = 0x00000001,
3811 + NVRSM_e_b = 1,
3812 + NVRSM_e_m = 0x00000002,
3813 + NVRSM_k_b = 2,
3814 + NVRSM_k_m = 0x00000004,
3815 +
3816 + NVRCFG0_pwidth_b = 0,
3817 + NVRCFG0_pwidth_m = 0x00000003,
3818 + NVRCFG0_nmax_b = 2,
3819 + NVRCFG0_nmax_m = 0x0000000C,
3820 + NVRCFG0_vppl_b = 4,
3821 + NVRCFG0_vppl_m = 0x000000f0,
3822 + NVRCFG0_vppm_b = 8,
3823 + NVRCFG0_vppm_m = 0x00000300,
3824 + NVRCFG0_dvpp_b = 10,
3825 + NVRCFG0_dvpp_m = 0x00000c00,
3826 + NVRCFG0_x_b = 12,
3827 + NVRCFG0_x_m = 0x00007000,
3828 +
3829 + NVRCFG1_t1tecc_b = 0,
3830 + NVRCFG1_t1tecc_m = 0x00000003,
3831 + NVRCFG1_t1mrcl_b = 2,
3832 + NVRCFG1_t1mrcl_m = 0x0000000c,
3833 + NVRCFG1_t1bias_b = 4,
3834 + NVRCFG1_t1bias_m = 0x00000030,
3835 + NVRCFG1_t2tecc_b = 6,
3836 + NVRCFG1_t2tecc_m = 0x000000c0,
3837 + NVRCFG1_t2mrcl_b = 8,
3838 + NVRCFG1_t2mrcl_m = 0x00000300,
3839 + NVRCFG1_t2bias_b = 10,
3840 + NVRCFG1_t2bias_m = 0x00000c00,
3841 + NVRCFG1_t3tecc_b = 12,
3842 + NVRCFG1_t3tecc_m = 0x00003000,
3843 + NVRCFG1_t3mrcl_b = 14,
3844 + NVRCFG1_t3mrcl_m = 0x0000c000,
3845 + NVRCFG1_t3bias_b = 16,
3846 + NVRCFG1_t3bias_m = 0x00030000,
3847 + NVRCFG1_t4tecc_b = 18,
3848 + NVRCFG1_t4tecc_m = 0x000c0000,
3849 + NVRCFG1_t4mrcl_b = 20,
3850 + NVRCFG1_t4mrcl_m = 0x00300000,
3851 + NVRCFG1_t4bias_b = 22,
3852 + NVRCFG1_t4bias_m = 0x00c00000,
3853 + NVRCFG1_t5tecc_b = 24,
3854 + NVRCFG1_t5tecc_m = 0x03000000,
3855 + NVRCFG1_t5mrcl_b = 26,
3856 + NVRCFG1_t5mrcl_m = 0x0c000000,
3857 + NVRCFG1_t5bias_b = 28,
3858 + NVRCFG1_t5bias_m = 0x30000000,
3859 +}
3860 +
3861 +#endif // __IDT_NVRAM_H__
3862 +
3863 diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h
3864 --- linux.old/include/asm-mips/rc32434/pci.h 1970-01-01 01:00:00.000000000 +0100
3865 +++ linux.dev/include/asm-mips/rc32434/pci.h 2006-10-11 21:56:38.000000000 +0200
3866 @@ -0,0 +1,695 @@
3867 +/**************************************************************************
3868 + *
3869 + * BRIEF MODULE DESCRIPTION
3870 + * PCI register definitio
3871 + *
3872 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3873 + *
3874 + * This program is free software; you can redistribute it and/or modify it
3875 + * under the terms of the GNU General Public License as published by the
3876 + * Free Software Foundation; either version 2 of the License, or (at your
3877 + * option) any later version.
3878 + *
3879 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3880 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3881 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3882 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3883 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3884 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3885 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3886 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3887 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3888 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3889 + *
3890 + * You should have received a copy of the GNU General Public License along
3891 + * with this program; if not, write to the Free Software Foundation, Inc.,
3892 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3893 + *
3894 + *
3895 + **************************************************************************
3896 + * May 2004 rkt, neb.
3897 + *
3898 + * Initial Release
3899 + *
3900 + *
3901 + *
3902 + **************************************************************************
3903 + */
3904 +
3905 +#ifndef __IDT_PCI_H__
3906 +#define __IDT_PCI_H__
3907 +
3908 +enum
3909 +{
3910 + PCI0_PhysicalAddress = 0x18080000,
3911 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
3912 +
3913 + PCI0_VirtualAddress = 0xB8080000,
3914 + PCI_VirtualAddress = PCI0_VirtualAddress,
3915 +} ;
3916 +
3917 +enum
3918 +{
3919 + PCI_LbaCount = 4, // Local base addresses.
3920 +} ;
3921 +
3922 +typedef struct
3923 +{
3924 + u32 a ; // Address.
3925 + u32 c ; // Control.
3926 + u32 m ; // mapping.
3927 +} PCI_Map_s ;
3928 +
3929 +typedef struct
3930 +{
3931 + u32 pcic ;
3932 + u32 pcis ;
3933 + u32 pcism ;
3934 + u32 pcicfga ;
3935 + u32 pcicfgd ;
3936 + PCI_Map_s pcilba [PCI_LbaCount] ;
3937 + u32 pcidac ;
3938 + u32 pcidas ;
3939 + u32 pcidasm ;
3940 + u32 pcidad ;
3941 + u32 pcidma8c ;
3942 + u32 pcidma9c ;
3943 + u32 pcitc ;
3944 +} volatile *PCI_t ;
3945 +
3946 +// PCI messaging unit.
3947 +enum
3948 +{
3949 + PCIM_Count = 2,
3950 +} ;
3951 +typedef struct
3952 +{
3953 + u32 pciim [PCIM_Count] ;
3954 + u32 pciom [PCIM_Count] ;
3955 + u32 pciid ;
3956 + u32 pciiic ;
3957 + u32 pciiim ;
3958 + u32 pciiod ;
3959 + u32 pciioic ;
3960 + u32 pciioim ;
3961 +} volatile *PCIM_t ;
3962 +
3963 +/*******************************************************************************
3964 + *
3965 + * PCI Control Register
3966 + *
3967 + ******************************************************************************/
3968 +enum
3969 +{
3970 + PCIC_en_b = 0,
3971 + PCIC_en_m = 0x00000001,
3972 + PCIC_tnr_b = 1,
3973 + PCIC_tnr_m = 0x00000002,
3974 + PCIC_sce_b = 2,
3975 + PCIC_sce_m = 0x00000004,
3976 + PCIC_ien_b = 3,
3977 + PCIC_ien_m = 0x00000008,
3978 + PCIC_aaa_b = 4,
3979 + PCIC_aaa_m = 0x00000010,
3980 + PCIC_eap_b = 5,
3981 + PCIC_eap_m = 0x00000020,
3982 + PCIC_pcim_b = 6,
3983 + PCIC_pcim_m = 0x000001c0,
3984 + PCIC_pcim_disabled_v = 0,
3985 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
3986 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
3987 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
3988 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
3989 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
3990 + PCIC_pcim_reserved6_v = 6,
3991 + PCIC_pcim_reserved7_v = 7,
3992 + PCIC_igm_b = 9,
3993 + PCIC_igm_m = 0x00000200,
3994 +} ;
3995 +
3996 +/*******************************************************************************
3997 + *
3998 + * PCI Status Register
3999 + *
4000 + ******************************************************************************/
4001 +enum {
4002 + PCIS_eed_b = 0,
4003 + PCIS_eed_m = 0x00000001,
4004 + PCIS_wr_b = 1,
4005 + PCIS_wr_m = 0x00000002,
4006 + PCIS_nmi_b = 2,
4007 + PCIS_nmi_m = 0x00000004,
4008 + PCIS_ii_b = 3,
4009 + PCIS_ii_m = 0x00000008,
4010 + PCIS_cwe_b = 4,
4011 + PCIS_cwe_m = 0x00000010,
4012 + PCIS_cre_b = 5,
4013 + PCIS_cre_m = 0x00000020,
4014 + PCIS_mdpe_b = 6,
4015 + PCIS_mdpe_m = 0x00000040,
4016 + PCIS_sta_b = 7,
4017 + PCIS_sta_m = 0x00000080,
4018 + PCIS_rta_b = 8,
4019 + PCIS_rta_m = 0x00000100,
4020 + PCIS_rma_b = 9,
4021 + PCIS_rma_m = 0x00000200,
4022 + PCIS_sse_b = 10,
4023 + PCIS_sse_m = 0x00000400,
4024 + PCIS_ose_b = 11,
4025 + PCIS_ose_m = 0x00000800,
4026 + PCIS_pe_b = 12,
4027 + PCIS_pe_m = 0x00001000,
4028 + PCIS_tae_b = 13,
4029 + PCIS_tae_m = 0x00002000,
4030 + PCIS_rle_b = 14,
4031 + PCIS_rle_m = 0x00004000,
4032 + PCIS_bme_b = 15,
4033 + PCIS_bme_m = 0x00008000,
4034 + PCIS_prd_b = 16,
4035 + PCIS_prd_m = 0x00010000,
4036 + PCIS_rip_b = 17,
4037 + PCIS_rip_m = 0x00020000,
4038 +} ;
4039 +
4040 +/*******************************************************************************
4041 + *
4042 + * PCI Status Mask Register
4043 + *
4044 + ******************************************************************************/
4045 +enum {
4046 + PCISM_eed_b = 0,
4047 + PCISM_eed_m = 0x00000001,
4048 + PCISM_wr_b = 1,
4049 + PCISM_wr_m = 0x00000002,
4050 + PCISM_nmi_b = 2,
4051 + PCISM_nmi_m = 0x00000004,
4052 + PCISM_ii_b = 3,
4053 + PCISM_ii_m = 0x00000008,
4054 + PCISM_cwe_b = 4,
4055 + PCISM_cwe_m = 0x00000010,
4056 + PCISM_cre_b = 5,
4057 + PCISM_cre_m = 0x00000020,
4058 + PCISM_mdpe_b = 6,
4059 + PCISM_mdpe_m = 0x00000040,
4060 + PCISM_sta_b = 7,
4061 + PCISM_sta_m = 0x00000080,
4062 + PCISM_rta_b = 8,
4063 + PCISM_rta_m = 0x00000100,
4064 + PCISM_rma_b = 9,
4065 + PCISM_rma_m = 0x00000200,
4066 + PCISM_sse_b = 10,
4067 + PCISM_sse_m = 0x00000400,
4068 + PCISM_ose_b = 11,
4069 + PCISM_ose_m = 0x00000800,
4070 + PCISM_pe_b = 12,
4071 + PCISM_pe_m = 0x00001000,
4072 + PCISM_tae_b = 13,
4073 + PCISM_tae_m = 0x00002000,
4074 + PCISM_rle_b = 14,
4075 + PCISM_rle_m = 0x00004000,
4076 + PCISM_bme_b = 15,
4077 + PCISM_bme_m = 0x00008000,
4078 + PCISM_prd_b = 16,
4079 + PCISM_prd_m = 0x00010000,
4080 + PCISM_rip_b = 17,
4081 + PCISM_rip_m = 0x00020000,
4082 +} ;
4083 +
4084 +/*******************************************************************************
4085 + *
4086 + * PCI Configuration Address Register
4087 + *
4088 + ******************************************************************************/
4089 +enum {
4090 + PCICFGA_reg_b = 2,
4091 + PCICFGA_reg_m = 0x000000fc,
4092 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
4093 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
4094 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
4095 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
4096 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
4097 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
4098 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
4099 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
4100 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
4101 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
4102 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
4103 + PCICFGA_reg_pba0m_v = 0x48>>2,
4104 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
4105 + PCICFGA_reg_pba1m_v = 0x50>>2,
4106 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
4107 + PCICFGA_reg_pba2m_v = 0x58>>2,
4108 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
4109 + PCICFGA_reg_pba3m_v = 0x60>>2,
4110 + PCICFGA_reg_pmgt_v = 0x64>>2,
4111 + PCICFGA_func_b = 8,
4112 + PCICFGA_func_m = 0x00000700,
4113 + PCICFGA_dev_b = 11,
4114 + PCICFGA_dev_m = 0x0000f800,
4115 + PCICFGA_dev_internal_v = 0,
4116 + PCICFGA_bus_b = 16,
4117 + PCICFGA_bus_m = 0x00ff0000,
4118 + PCICFGA_bus_type0_v = 0, //local bus
4119 + PCICFGA_en_b = 31, // read only
4120 + PCICFGA_en_m = 0x80000000,
4121 +} ;
4122 +
4123 +enum {
4124 + PCFGID_vendor_b = 0,
4125 + PCFGID_vendor_m = 0x0000ffff,
4126 + PCFGID_vendor_IDT_v = 0x111d,
4127 + PCFGID_device_b = 16,
4128 + PCFGID_device_m = 0xffff0000,
4129 + PCFGID_device_Korinade_v = 0x0214,
4130 +
4131 + PCFG04_command_ioena_b = 1,
4132 + PCFG04_command_ioena_m = 0x00000001,
4133 + PCFG04_command_memena_b = 2,
4134 + PCFG04_command_memena_m = 0x00000002,
4135 + PCFG04_command_bmena_b = 3,
4136 + PCFG04_command_bmena_m = 0x00000004,
4137 + PCFG04_command_mwinv_b = 5,
4138 + PCFG04_command_mwinv_m = 0x00000010,
4139 + PCFG04_command_parena_b = 7,
4140 + PCFG04_command_parena_m = 0x00000040,
4141 + PCFG04_command_serrena_b = 9,
4142 + PCFG04_command_serrena_m = 0x00000100,
4143 + PCFG04_command_fastbbena_b = 10,
4144 + PCFG04_command_fastbbena_m = 0x00000200,
4145 + PCFG04_status_b = 16,
4146 + PCFG04_status_m = 0xffff0000,
4147 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
4148 + PCFG04_status_66MHz_m = 0x00200000,
4149 + PCFG04_status_fbb_b = 23,
4150 + PCFG04_status_fbb_m = 0x00800000,
4151 + PCFG04_status_mdpe_b = 24,
4152 + PCFG04_status_mdpe_m = 0x01000000,
4153 + PCFG04_status_dst_b = 25,
4154 + PCFG04_status_dst_m = 0x06000000,
4155 + PCFG04_status_sta_b = 27,
4156 + PCFG04_status_sta_m = 0x08000000,
4157 + PCFG04_status_rta_b = 28,
4158 + PCFG04_status_rta_m = 0x10000000,
4159 + PCFG04_status_rma_b = 29,
4160 + PCFG04_status_rma_m = 0x20000000,
4161 + PCFG04_status_sse_b = 30,
4162 + PCFG04_status_sse_m = 0x40000000,
4163 + PCFG04_status_pe_b = 31,
4164 + PCFG04_status_pe_m = 0x40000000,
4165 +
4166 + PCFG08_revId_b = 0,
4167 + PCFG08_revId_m = 0x000000ff,
4168 + PCFG08_classCode_b = 0,
4169 + PCFG08_classCode_m = 0xffffff00,
4170 + PCFG08_classCode_bridge_v = 06,
4171 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
4172 + PCFG0C_cacheline_b = 0,
4173 + PCFG0C_cacheline_m = 0x000000ff,
4174 + PCFG0C_masterLatency_b = 8,
4175 + PCFG0C_masterLatency_m = 0x0000ff00,
4176 + PCFG0C_headerType_b = 16,
4177 + PCFG0C_headerType_m = 0x00ff0000,
4178 + PCFG0C_bist_b = 24,
4179 + PCFG0C_bist_m = 0xff000000,
4180 +
4181 + PCIPBA_msi_b = 0,
4182 + PCIPBA_msi_m = 0x00000001,
4183 + PCIPBA_p_b = 3,
4184 + PCIPBA_p_m = 0x00000004,
4185 + PCIPBA_baddr_b = 8,
4186 + PCIPBA_baddr_m = 0xffffff00,
4187 +
4188 + PCFGSS_vendorId_b = 0,
4189 + PCFGSS_vendorId_m = 0x0000ffff,
4190 + PCFGSS_id_b = 16,
4191 + PCFGSS_id_m = 0xffff0000,
4192 +
4193 + PCFG3C_interruptLine_b = 0,
4194 + PCFG3C_interruptLine_m = 0x000000ff,
4195 + PCFG3C_interruptPin_b = 8,
4196 + PCFG3C_interruptPin_m = 0x0000ff00,
4197 + PCFG3C_minGrant_b = 16,
4198 + PCFG3C_minGrant_m = 0x00ff0000,
4199 + PCFG3C_maxLat_b = 24,
4200 + PCFG3C_maxLat_m = 0xff000000,
4201 +
4202 + PCIPBAC_msi_b = 0,
4203 + PCIPBAC_msi_m = 0x00000001,
4204 + PCIPBAC_p_b = 1,
4205 + PCIPBAC_p_m = 0x00000002,
4206 + PCIPBAC_size_b = 2,
4207 + PCIPBAC_size_m = 0x0000007c,
4208 + PCIPBAC_sb_b = 7,
4209 + PCIPBAC_sb_m = 0x00000080,
4210 + PCIPBAC_pp_b = 8,
4211 + PCIPBAC_pp_m = 0x00000100,
4212 + PCIPBAC_mr_b = 9,
4213 + PCIPBAC_mr_m = 0x00000600,
4214 + PCIPBAC_mr_read_v =0, //no prefetching
4215 + PCIPBAC_mr_readLine_v =1,
4216 + PCIPBAC_mr_readMult_v =2,
4217 + PCIPBAC_mrl_b = 11,
4218 + PCIPBAC_mrl_m = 0x00000800,
4219 + PCIPBAC_mrm_b = 12,
4220 + PCIPBAC_mrm_m = 0x00001000,
4221 + PCIPBAC_trp_b = 13,
4222 + PCIPBAC_trp_m = 0x00002000,
4223 +
4224 + PCFG40_trdyTimeout_b = 0,
4225 + PCFG40_trdyTimeout_m = 0x000000ff,
4226 + PCFG40_retryLim_b = 8,
4227 + PCFG40_retryLim_m = 0x0000ff00,
4228 +};
4229 +
4230 +/*******************************************************************************
4231 + *
4232 + * PCI Local Base Address [0|1|2|3] Register
4233 + *
4234 + ******************************************************************************/
4235 +enum {
4236 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
4237 + PCILBA_baddr_m = 0xffffff00,
4238 +} ;
4239 +/*******************************************************************************
4240 + *
4241 + * PCI Local Base Address Control Register
4242 + *
4243 + ******************************************************************************/
4244 +enum {
4245 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
4246 + PCILBAC_msi_m = 0x00000001,
4247 + PCILBAC_msi_mem_v = 0,
4248 + PCILBAC_msi_io_v = 1,
4249 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
4250 + PCILBAC_size_m = 0x0000007c,
4251 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
4252 + PCILBAC_sb_m = 0x00000080,
4253 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
4254 + PCILBAC_rt_m = 0x00000100,
4255 + PCILBAC_rt_noprefetch_v = 0, // mem read
4256 + PCILBAC_rt_prefetch_v = 1, // mem readline
4257 +} ;
4258 +
4259 +/*******************************************************************************
4260 + *
4261 + * PCI Local Base Address [0|1|2|3] Mapping Register
4262 + *
4263 + ******************************************************************************/
4264 +enum {
4265 + PCILBAM_maddr_b = 8,
4266 + PCILBAM_maddr_m = 0xffffff00,
4267 +} ;
4268 +
4269 +/*******************************************************************************
4270 + *
4271 + * PCI Decoupled Access Control Register
4272 + *
4273 + ******************************************************************************/
4274 +enum {
4275 + PCIDAC_den_b = 0,
4276 + PCIDAC_den_m = 0x00000001,
4277 +} ;
4278 +
4279 +/*******************************************************************************
4280 + *
4281 + * PCI Decoupled Access Status Register
4282 + *
4283 + ******************************************************************************/
4284 +enum {
4285 + PCIDAS_d_b = 0,
4286 + PCIDAS_d_m = 0x00000001,
4287 + PCIDAS_b_b = 1,
4288 + PCIDAS_b_m = 0x00000002,
4289 + PCIDAS_e_b = 2,
4290 + PCIDAS_e_m = 0x00000004,
4291 + PCIDAS_ofe_b = 3,
4292 + PCIDAS_ofe_m = 0x00000008,
4293 + PCIDAS_off_b = 4,
4294 + PCIDAS_off_m = 0x00000010,
4295 + PCIDAS_ife_b = 5,
4296 + PCIDAS_ife_m = 0x00000020,
4297 + PCIDAS_iff_b = 6,
4298 + PCIDAS_iff_m = 0x00000040,
4299 +} ;
4300 +
4301 +/*******************************************************************************
4302 + *
4303 + * PCI DMA Channel 8 Configuration Register
4304 + *
4305 + ******************************************************************************/
4306 +enum
4307 +{
4308 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
4309 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
4310 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
4311 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
4312 +} ;
4313 +
4314 +/*******************************************************************************
4315 + *
4316 + * PCI DMA Channel 9 Configuration Register
4317 + *
4318 + ******************************************************************************/
4319 +enum
4320 +{
4321 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
4322 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
4323 +} ;
4324 +
4325 +/*******************************************************************************
4326 + *
4327 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
4328 + *
4329 + ******************************************************************************/
4330 +enum {
4331 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
4332 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
4333 + // These are for reads (DMA channel 8)
4334 + PCIDMAD_devcmd_mr_v = 0, //memory read
4335 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
4336 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
4337 + PCIDMAD_devcmd_ior_v = 3, //I/O read
4338 + // These are for writes (DMA channel 9)
4339 + PCIDMAD_devcmd_mw_v = 0, //memory write
4340 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
4341 + PCIDMAD_devcmd_iow_v = 3, //I/O write
4342 +
4343 + // Swap byte field applies to both DMA channel 8 and 9
4344 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
4345 + PCIDMAD_sb_m = 0x01000000, // swap byte field
4346 +} ;
4347 +
4348 +
4349 +/*******************************************************************************
4350 + *
4351 + * PCI Target Control Register
4352 + *
4353 + ******************************************************************************/
4354 +enum
4355 +{
4356 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
4357 + PCITC_rtimer_m = 0x000000ff,
4358 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
4359 + PCITC_dtimer_m = 0x0000ff00,
4360 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
4361 + PCITC_rdr_m = 0x00040000,
4362 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
4363 + PCITC_ddt_m = 0x00080000,
4364 +} ;
4365 +/*******************************************************************************
4366 + *
4367 + * PCI messaging unit [applies to both inbound and outbound registers ]
4368 + *
4369 + ******************************************************************************/
4370 +enum
4371 +{
4372 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4373 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
4374 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4375 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
4376 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
4377 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
4378 +};
4379 +
4380 +
4381 +
4382 +
4383 +
4384 +
4385 +#define PCI_MSG_VirtualAddress 0xB8088010
4386 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
4387 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
4388 +
4389 +#define PCIM_SHFT 0x6
4390 +#define PCIM_BIT_LEN 0x7
4391 +#define PCIM_H_EA 0x3
4392 +#define PCIM_H_IA_FIX 0x4
4393 +#define PCIM_H_IA_RR 0x5
4394 +#if 0
4395 +#define PCI_ADDR_START 0x13000000
4396 +#endif
4397 +
4398 +#define PCI_ADDR_START 0x50000000
4399 +
4400 +#define CPUTOPCI_MEM_WIN 0x02000000
4401 +#define CPUTOPCI_IO_WIN 0x00100000
4402 +#define PCILBA_SIZE_SHFT 2
4403 +#define PCILBA_SIZE_MASK 0x1F
4404 +#define SIZE_256MB 0x1C
4405 +#define SIZE_128MB 0x1B
4406 +#define SIZE_64MB 0x1A
4407 +#define SIZE_32MB 0x19
4408 +#define SIZE_16MB 0x18
4409 +#define SIZE_4MB 0x16
4410 +#define SIZE_2MB 0x15
4411 +#define SIZE_1MB 0x14
4412 +#define KORINA_CONFIG0_ADDR 0x80000000
4413 +#define KORINA_CONFIG1_ADDR 0x80000004
4414 +#define KORINA_CONFIG2_ADDR 0x80000008
4415 +#define KORINA_CONFIG3_ADDR 0x8000000C
4416 +#define KORINA_CONFIG4_ADDR 0x80000010
4417 +#define KORINA_CONFIG5_ADDR 0x80000014
4418 +#define KORINA_CONFIG6_ADDR 0x80000018
4419 +#define KORINA_CONFIG7_ADDR 0x8000001C
4420 +#define KORINA_CONFIG8_ADDR 0x80000020
4421 +#define KORINA_CONFIG9_ADDR 0x80000024
4422 +#define KORINA_CONFIG10_ADDR 0x80000028
4423 +#define KORINA_CONFIG11_ADDR 0x8000002C
4424 +#define KORINA_CONFIG12_ADDR 0x80000030
4425 +#define KORINA_CONFIG13_ADDR 0x80000034
4426 +#define KORINA_CONFIG14_ADDR 0x80000038
4427 +#define KORINA_CONFIG15_ADDR 0x8000003C
4428 +#define KORINA_CONFIG16_ADDR 0x80000040
4429 +#define KORINA_CONFIG17_ADDR 0x80000044
4430 +#define KORINA_CONFIG18_ADDR 0x80000048
4431 +#define KORINA_CONFIG19_ADDR 0x8000004C
4432 +#define KORINA_CONFIG20_ADDR 0x80000050
4433 +#define KORINA_CONFIG21_ADDR 0x80000054
4434 +#define KORINA_CONFIG22_ADDR 0x80000058
4435 +#define KORINA_CONFIG23_ADDR 0x8000005C
4436 +#define KORINA_CONFIG24_ADDR 0x80000060
4437 +#define KORINA_CONFIG25_ADDR 0x80000064
4438 +#define KORINA_CMD (PCFG04_command_ioena_m | \
4439 + PCFG04_command_memena_m | \
4440 + PCFG04_command_bmena_m | \
4441 + PCFG04_command_mwinv_m | \
4442 + PCFG04_command_parena_m | \
4443 + PCFG04_command_serrena_m )
4444 +
4445 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
4446 + PCFG04_status_sta_m | \
4447 + PCFG04_status_rta_m | \
4448 + PCFG04_status_rma_m | \
4449 + PCFG04_status_sse_m | \
4450 + PCFG04_status_pe_m)
4451 +
4452 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
4453 +
4454 +#define KORINA_REVID 0
4455 +#define KORINA_CLASS_CODE 0
4456 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
4457 + KORINA_REVID)
4458 +
4459 +#define KORINA_CACHE_LINE_SIZE 4
4460 +#define KORINA_MASTER_LAT 0x3c
4461 +#define KORINA_HEADER_TYPE 0
4462 +#define KORINA_BIST 0
4463 +
4464 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
4465 + (KORINA_HEADER_TYPE<<16) | \
4466 + (KORINA_MASTER_LAT<<8) | \
4467 + KORINA_CACHE_LINE_SIZE )
4468 +
4469 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
4470 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
4471 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
4472 + internal Registers */
4473 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
4474 +
4475 +#define KORINA_CNFG4 KORINA_BAR0
4476 +#define KORINA_CNFG5 KORINA_BAR1
4477 +#define KORINA_CNFG6 KORINA_BAR2
4478 +#define KORINA_CNFG7 KORINA_BAR3
4479 +
4480 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
4481 +#define KORINA_SUBSYSTEM_ID 0x0214
4482 +#define KORINA_CNFG8 0
4483 +#define KORINA_CNFG9 0
4484 +#define KORINA_CNFG10 0
4485 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
4486 + KORINA_SUBSYSTEM_ID)
4487 +#define KORINA_INT_LINE 1
4488 +#define KORINA_INT_PIN 1
4489 +#define KORINA_MIN_GNT 8
4490 +#define KORINA_MAX_LAT 0x38
4491 +#define KORINA_CNFG12 0
4492 +#define KORINA_CNFG13 0
4493 +#define KORINA_CNFG14 0
4494 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
4495 + (KORINA_MIN_GNT<<16) | \
4496 + (KORINA_INT_PIN<<8) | \
4497 + KORINA_INT_LINE)
4498 +#define KORINA_RETRY_LIMIT 0x80
4499 +#define KORINA_TRDY_LIMIT 0x80
4500 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
4501 + KORINA_TRDY_LIMIT)
4502 +#define PCI_PBAxC_R 0x0
4503 +#define PCI_PBAxC_RL 0x1
4504 +#define PCI_PBAxC_RM 0x2
4505 +#define SIZE_SHFT 2
4506 +
4507 +#if defined(__MIPSEB__)
4508 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
4509 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4510 + PCIPBAC_pp_m | \
4511 + (SIZE_128MB<<SIZE_SHFT) | \
4512 + PCIPBAC_p_m)
4513 +#else
4514 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
4515 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4516 + PCIPBAC_pp_m | \
4517 + (SIZE_128MB<<SIZE_SHFT) | \
4518 + PCIPBAC_p_m)
4519 +#endif
4520 +#define KORINA_CNFG17 KORINA_PBA0C
4521 +#define KORINA_PBA0M 0x0
4522 +#define KORINA_CNFG18 KORINA_PBA0M
4523 +
4524 +#if defined(__MIPSEB__)
4525 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4526 + PCIPBAC_msi_m)
4527 +#else
4528 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
4529 + PCIPBAC_msi_m)
4530 +#endif
4531 +#define KORINA_CNFG19 KORINA_PBA1C
4532 +#define KORINA_PBA1M 0x0
4533 +#define KORINA_CNFG20 KORINA_PBA1M
4534 +
4535 +#if defined(__MIPSEB__)
4536 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4537 + PCIPBAC_msi_m)
4538 +#else
4539 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
4540 + PCIPBAC_msi_m)
4541 +#endif
4542 +#define KORINA_CNFG21 KORINA_PBA2C
4543 +#define KORINA_PBA2M 0x18000000
4544 +#define KORINA_CNFG22 KORINA_PBA2M
4545 +#define KORINA_PBA3C 0
4546 +#define KORINA_CNFG23 KORINA_PBA3C
4547 +#define KORINA_PBA3M 0
4548 +#define KORINA_CNFG24 KORINA_PBA3M
4549 +
4550 +
4551 +
4552 +#define PCITC_DTIMER_VAL 8
4553 +#define PCITC_RTIMER_VAL 0x10
4554 +
4555 +
4556 +
4557 +
4558 +#endif // __IDT_PCI_H__
4559 +
4560 +
4561 +
4562 diff -urN linux.old/include/asm-mips/rc32434/pcikorina.h linux.dev/include/asm-mips/rc32434/pcikorina.h
4563 --- linux.old/include/asm-mips/rc32434/pcikorina.h 1970-01-01 01:00:00.000000000 +0100
4564 +++ linux.dev/include/asm-mips/rc32434/pcikorina.h 2006-10-11 21:56:38.000000000 +0200
4565 @@ -0,0 +1,209 @@
4566 +/* $Id: pciacacia.h,v 1.5 2001/05/01 10:09:17 carstenl Exp $
4567 + *
4568 + * This file is subject to the terms and conditions of the GNU General Public
4569 + * License. See the file "COPYING" in the main directory of this archive
4570 + * for more details.
4571 + */
4572 +#ifndef _PCIKORINA_H
4573 +#define _PCIKORINA_H
4574 +
4575 +
4576 +#define PCI_MSG_VirtualAddress 0xB8088010
4577 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
4578 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
4579 +
4580 +#define PCIM_SHFT 0x6
4581 +#define PCIM_BIT_LEN 0x7
4582 +#define PCIM_H_EA 0x3
4583 +#define PCIM_H_IA_FIX 0x4
4584 +#define PCIM_H_IA_RR 0x5
4585 +#if 0
4586 +#define PCI_ADDR_START 0x13000000
4587 +#endif
4588 +
4589 +#define PCI_ADDR_START 0x50000000
4590 +
4591 +#define CPUTOPCI_MEM_WIN 0x02000000
4592 +#define CPUTOPCI_IO_WIN 0x00100000
4593 +#define PCILBA_SIZE_SHFT 2
4594 +#define PCILBA_SIZE_MASK 0x1F
4595 +#define SIZE_256MB 0x1C
4596 +#define SIZE_128MB 0x1B
4597 +#define SIZE_64MB 0x1A
4598 +#define SIZE_32MB 0x19
4599 +#define SIZE_16MB 0x18
4600 +#define SIZE_4MB 0x16
4601 +#define SIZE_2MB 0x15
4602 +#define SIZE_1MB 0x14
4603 +#define KORINA_CONFIG0_ADDR 0x80000000
4604 +#define KORINA_CONFIG1_ADDR 0x80000004
4605 +#define KORINA_CONFIG2_ADDR 0x80000008
4606 +#define KORINA_CONFIG3_ADDR 0x8000000C
4607 +#define KORINA_CONFIG4_ADDR 0x80000010
4608 +#define KORINA_CONFIG5_ADDR 0x80000014
4609 +#define KORINA_CONFIG6_ADDR 0x80000018
4610 +#define KORINA_CONFIG7_ADDR 0x8000001C
4611 +#define KORINA_CONFIG8_ADDR 0x80000020
4612 +#define KORINA_CONFIG9_ADDR 0x80000024
4613 +#define KORINA_CONFIG10_ADDR 0x80000028
4614 +#define KORINA_CONFIG11_ADDR 0x8000002C
4615 +#define KORINA_CONFIG12_ADDR 0x80000030
4616 +#define KORINA_CONFIG13_ADDR 0x80000034
4617 +#define KORINA_CONFIG14_ADDR 0x80000038
4618 +#define KORINA_CONFIG15_ADDR 0x8000003C
4619 +#define KORINA_CONFIG16_ADDR 0x80000040
4620 +#define KORINA_CONFIG17_ADDR 0x80000044
4621 +#define KORINA_CONFIG18_ADDR 0x80000048
4622 +#define KORINA_CONFIG19_ADDR 0x8000004C
4623 +#define KORINA_CONFIG20_ADDR 0x80000050
4624 +#define KORINA_CONFIG21_ADDR 0x80000054
4625 +#define KORINA_CONFIG22_ADDR 0x80000058
4626 +#define KORINA_CONFIG23_ADDR 0x8000005C
4627 +#define KORINA_CONFIG24_ADDR 0x80000060
4628 +#define KORINA_CONFIG25_ADDR 0x80000064
4629 +#define KORINA_CMD (PCFG04_command_ioena_m | \
4630 + PCFG04_command_memena_m | \
4631 + PCFG04_command_bmena_m | \
4632 + PCFG04_command_mwinv_m | \
4633 + PCFG04_command_parena_m | \
4634 + PCFG04_command_serrena_m )
4635 +
4636 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
4637 + PCFG04_status_sta_m | \
4638 + PCFG04_status_rta_m | \
4639 + PCFG04_status_rma_m | \
4640 + PCFG04_status_sse_m | \
4641 + PCFG04_status_pe_m)
4642 +
4643 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
4644 +
4645 +#define KORINA_REVID 0
4646 +#define KORINA_CLASS_CODE 0
4647 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
4648 + KORINA_REVID)
4649 +
4650 +#define KORINA_CACHE_LINE_SIZE 4
4651 +#define KORINA_MASTER_LAT 0x3c
4652 +#define KORINA_HEADER_TYPE 0
4653 +#define KORINA_BIST 0
4654 +
4655 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
4656 + (KORINA_HEADER_TYPE<<16) | \
4657 + (KORINA_MASTER_LAT<<8) | \
4658 + KORINA_CACHE_LINE_SIZE )
4659 +
4660 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
4661 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
4662 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Acacia
4663 + internal Registers */
4664 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
4665 +
4666 +#define KORINA_CNFG4 KORINA_BAR0
4667 +#define KORINA_CNFG5 KORINA_BAR1
4668 +#define KORINA_CNFG6 KORINA_BAR2
4669 +#define KORINA_CNFG7 KORINA_BAR3
4670 +
4671 +#define KORINA_SUBSYS_VENDOR_ID 0
4672 +#define KORINA_SUBSYSTEM_ID 0
4673 +#define KORINA_CNFG8 0
4674 +#define KORINA_CNFG9 0
4675 +#define KORINA_CNFG10 0
4676 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
4677 + KORINA_SUBSYSTEM_ID)
4678 +#define KORINA_INT_LINE 1
4679 +#define KORINA_INT_PIN 1
4680 +#define KORINA_MIN_GNT 8
4681 +#define KORINA_MAX_LAT 0x38
4682 +#define KORINA_CNFG12 0
4683 +#define KORINA_CNFG13 0
4684 +#define KORINA_CNFG14 0
4685 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
4686 + (KORINA_MIN_GNT<<16) | \
4687 + (KORINA_INT_PIN<<8) | \
4688 + KORINA_INT_LINE)
4689 +#define KORINA_RETRY_LIMIT 0x80
4690 +#define KORINA_TRDY_LIMIT 0x80
4691 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
4692 + KORINA_TRDY_LIMIT)
4693 +#define PCI_PBAxC_R 0x0
4694 +#define PCI_PBAxC_RL 0x1
4695 +#define PCI_PBAxC_RM 0x2
4696 +#define SIZE_SHFT 2
4697 +
4698 +#ifdef __MIPSEB__
4699 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
4700 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4701 + PCIPBAC_pp_m | \
4702 + (SIZE_32MB<<SIZE_SHFT) | \
4703 + PCIPBAC_p_m)
4704 +#else
4705 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
4706 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
4707 + PCIPBAC_pp_m | \
4708 + (SIZE_32MB<<SIZE_SHFT) | \
4709 + PCIPBAC_p_m)
4710 +#endif
4711 +
4712 +#if 0
4713 +
4714 +#define KORINA_PBA0C ( PCIPBAC_sb_m | PCIPBAC_pp_m | \
4715 + ((PCI_PBAxC_R &0x3) << PCIPBAC_mr_b) | \
4716 + (SIZE_128MB<<SIZE_SHFT))
4717 +#endif
4718 +#define KORINA_CNFG17 KORINA_PBA0C
4719 +#define KORINA_PBA0M 0x0
4720 +#define KORINA_CNFG18 KORINA_PBA0M
4721 +
4722 +#ifdef __MIPSEB__
4723 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4724 + PCIPBAC_msi_m)
4725 +#else
4726 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
4727 + PCIPBAC_msi_m)
4728 +
4729 +#endif
4730 +
4731 +#define KORINA_CNFG19 KORINA_PBA1C
4732 +#define KORINA_PBA1M 0x0
4733 +#define KORINA_CNFG20 KORINA_PBA1M
4734 +
4735 +#ifdef __MIPSEB__
4736 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
4737 + PCIPBAC_msi_m)
4738 +#else
4739 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
4740 + PCIPBAC_msi_m)
4741 +
4742 +#endif
4743 +#define KORINA_CNFG21 KORINA_PBA2C
4744 +#define KORINA_PBA2M 0x18000000
4745 +#define KORINA_CNFG22 KORINA_PBA2M
4746 +#define KORINA_PBA3C 0
4747 +#define KORINA_CNFG23 KORINA_PBA3C
4748 +#define KORINA_PBA3M 0
4749 +#define KORINA_CNFG24 KORINA_PBA3M
4750 +
4751 +
4752 +
4753 +#define PCITC_DTIMER_VAL 8
4754 +#define PCITC_RTIMER_VAL 0x10
4755 +
4756 +
4757 +#endif /* _PCIKORINA_H */
4758 +
4759 +
4760 +
4761 +
4762 +
4763 +
4764 +
4765 +
4766 +
4767 +
4768 +
4769 +
4770 +
4771 +
4772 +
4773 +
4774 +
4775 diff -urN linux.old/include/asm-mips/rc32434/pci_regs.h linux.dev/include/asm-mips/rc32434/pci_regs.h
4776 --- linux.old/include/asm-mips/rc32434/pci_regs.h 1970-01-01 01:00:00.000000000 +0100
4777 +++ linux.dev/include/asm-mips/rc32434/pci_regs.h 2006-10-11 21:56:38.000000000 +0200
4778 @@ -0,0 +1,8 @@
4779 +/* Override the default address space for this arch
4780 +*/
4781 +
4782 +#include <linux/pci_regs.h>
4783 +
4784 +//#undef PCI_BASE_ADDRESS_SPACE
4785 +//#define PCI_BASE_ADDRESS_SPACE PCI_BASE_ADDRESS_SPACE_MEMORY
4786 +
4787 diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h
4788 --- linux.old/include/asm-mips/rc32434/rb.h 1970-01-01 01:00:00.000000000 +0100
4789 +++ linux.dev/include/asm-mips/rc32434/rb.h 2006-10-11 21:56:38.000000000 +0200
4790 @@ -0,0 +1,69 @@
4791 +#ifndef __MIPS_RB_H__
4792 +#define __MIPS_RB_H__
4793 +#include <linux/genhd.h>
4794 +
4795 +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
4796 +#define DEV0BASE 0x010000
4797 +#define DEV0MASK 0x010004
4798 +#define DEV0C 0x010008
4799 +#define DEV0TC 0x01000C
4800 +#define DEV1BASE 0x010010
4801 +#define DEV1MASK 0x010014
4802 +#define DEV1C 0x010018
4803 +#define DEV1TC 0x01001C
4804 +#define DEV2BASE 0x010020
4805 +#define DEV2MASK 0x010024
4806 +#define DEV2C 0x010028
4807 +#define DEV2TC 0x01002C
4808 +#define DEV3BASE 0x010030
4809 +#define DEV3MASK 0x010034
4810 +#define DEV3C 0x010038
4811 +#define DEV3TC 0x01003C
4812 +#define BTCS 0x010040
4813 +#define BTCOMPARE 0x010044
4814 +#define GPIOFUNC 0x050000
4815 +#define GPIOCFG 0x050004
4816 +#define GPIOD 0x050008
4817 +#define GPIOILEVEL 0x05000C
4818 +#define GPIOISTAT 0x050010
4819 +#define GPIONMIEN 0x050014
4820 +#define IMASK6 0x038038
4821 +
4822 +#define LO_WPX (1 << 0)
4823 +#define LO_ALE (1 << 1)
4824 +#define LO_CLE (1 << 2)
4825 +#define LO_CEX (1 << 3)
4826 +#define LO_FOFF (1 << 5)
4827 +#define LO_SPICS (1 << 6)
4828 +#define LO_ULED (1 << 7)
4829 +
4830 +typedef enum {
4831 + FUNC = 0x00,
4832 + CFG = 0x04,
4833 + DATA = 0x08,
4834 + ILEVEL = 0x0c,
4835 + ISTAT = 0x10,
4836 + NMIEN = 0x14
4837 +} gpio_func;
4838 +
4839 +extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
4840 +extern unsigned get434Reg(unsigned regOffs);
4841 +extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
4842 +extern void gpio_set(gpio_func func, u32 mask, u32 value);
4843 +extern u32 gpio_get(gpio_func func);
4844 +
4845 +#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
4846 +
4847 +struct korina_device {
4848 + char *name;
4849 + unsigned char mac[6];
4850 + struct net_device *dev;
4851 +};
4852 +
4853 +struct cf_device {
4854 + int gpio_pin;
4855 + void *dev;
4856 + struct gendisk *gd;
4857 +};
4858 +
4859 +#endif
4860 diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h
4861 --- linux.old/include/asm-mips/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
4862 +++ linux.dev/include/asm-mips/rc32434/rc32434.h 2006-10-11 21:56:38.000000000 +0200
4863 @@ -0,0 +1,126 @@
4864 +/*
4865 + ***************************************************************************
4866 + * Definitions for IDT RC323434 CPU.
4867 + *
4868 + ****************************************************************************
4869 + * Kiran Rao
4870 + *
4871 + * Original form
4872 + ****************************************************************************
4873 + * P. Sadik Oct 08, 2003
4874 + *
4875 + * Started revision history
4876 + * Made IDT_BUS_FREQ a kernel configuration parameter
4877 + ****************************************************************************
4878 + * P. Sadik Oct 10, 2003
4879 + *
4880 + * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
4881 + * idt_cpu_freq is used everywhere
4882 + ****************************************************************************
4883 + * P. Sadik Oct 20, 2003
4884 + *
4885 + * Removed RC32434_BASE_BAUD
4886 + ****************************************************************************
4887 +*/
4888 +#ifndef _RC32434_H_
4889 +#define _RC32434_H_
4890 +
4891 +#include <linux/config.h>
4892 +#include <linux/delay.h>
4893 +#include <asm/io.h>
4894 +#include <asm/rc32434/timer.h>
4895 +
4896 +#define RC32434_REG_BASE 0x18000000
4897 +
4898 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
4899 +#define timer ((volatile TIM_t) TIM0_VirtualAddress)
4900 +#define gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
4901 +
4902 +#define IDT_CLOCK_MULT 2
4903 +#define MIPS_CPU_TIMER_IRQ 7
4904 +/* Interrupt Controller */
4905 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
4906 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
4907 +#define IC_GROUP_OFFSET 0x0C
4908 +
4909 +#define NUM_INTR_GROUPS 5
4910 +/* 16550 UARTs */
4911 +
4912 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
4913 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
4914 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
4915 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
4916 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
4917 +
4918 +
4919 +#ifdef __MIPSEB__
4920 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
4921 +#else
4922 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
4923 +#endif
4924 +
4925 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
4926 +// #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
4927 +
4928 +#define local_readl(addr) __raw_readl(addr)
4929 +#define local_writel(l,addr) __raw_writel(l,addr)
4930 +
4931 +/* cpu pipeline flush */
4932 +static inline void rc32434_sync(void)
4933 +{
4934 + __asm__ volatile ("sync");
4935 +}
4936 +
4937 +static inline void rc32434_sync_udelay(int us)
4938 +{
4939 + __asm__ volatile ("sync");
4940 + udelay(us);
4941 +}
4942 +
4943 +static inline void rc32434_sync_delay(int ms)
4944 +{
4945 + __asm__ volatile ("sync");
4946 + mdelay(ms);
4947 +}
4948 +
4949 +/*
4950 + * C access to CLZ and CLO instructions
4951 + * (count leading zeroes/ones).
4952 + */
4953 +static inline int rc32434_clz(unsigned long val)
4954 +{
4955 + int ret;
4956 + __asm__ volatile (
4957 + ".set\tnoreorder\n\t"
4958 + ".set\tnoat\n\t"
4959 + ".set\tmips32\n\t"
4960 + "clz\t%0,%1\n\t"
4961 + ".set\tmips0\n\t"
4962 + ".set\tat\n\t"
4963 + ".set\treorder"
4964 + : "=r" (ret)
4965 + : "r" (val));
4966 +
4967 + return ret;
4968 +}
4969 +static inline int rc32434_clo(unsigned long val)
4970 +{
4971 + int ret;
4972 + __asm__ volatile (
4973 + ".set\tnoreorder\n\t"
4974 + ".set\tnoat\n\t"
4975 + ".set\tmips32\n\t"
4976 + "clo\t%0,%1\n\t"
4977 + ".set\tmips0\n\t"
4978 + ".set\tat\n\t"
4979 + ".set\treorder"
4980 + : "=r" (ret)
4981 + : "r" (val));
4982 +
4983 + return ret;
4984 +}
4985 +
4986 +extern void cons_putc(char c);
4987 +extern void cons_puts(char *s);
4988 +
4989 +#endif /* _RC32434_H_ */
4990 diff -urN linux.old/include/asm-mips/rc32434/rst.h linux.dev/include/asm-mips/rc32434/rst.h
4991 --- linux.old/include/asm-mips/rc32434/rst.h 1970-01-01 01:00:00.000000000 +0100
4992 +++ linux.dev/include/asm-mips/rc32434/rst.h 2006-10-11 21:56:38.000000000 +0200
4993 @@ -0,0 +1,105 @@
4994 +#ifndef __IDT_RST_H__
4995 +#define __IDT_RST_H__
4996 +
4997 +/*******************************************************************************
4998 + *
4999 + * Copyright 2002 Integrated Device Technology, Inc.
5000 + * All rights reserved.
5001 + *
5002 + * Reset register definitions.
5003 + *
5004 + * File : $Id: rst.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5005 + *
5006 + * Author : Allen.Stichter@idt.com
5007 + * Date : 20020118
5008 + * Update :
5009 + * $Log: rst.h,v $
5010 + * Revision 1.2 2002/06/06 18:34:05 astichte
5011 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5012 + *
5013 + * Revision 1.1 2002/05/29 17:33:24 sysarch
5014 + * jba File moved from vcode/include/idt/acacia
5015 + *
5016 + *
5017 + ******************************************************************************/
5018 +
5019 +#include <asm/rc32434/types.h>
5020 +
5021 +enum
5022 +{
5023 + RST0_PhysicalAddress = 0x18000000,
5024 + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
5025 +
5026 + RST0_VirtualAddress = 0xb8000000,
5027 + RST_VirtualAddress = RST0_VirtualAddress, // Default
5028 +} ;
5029 +
5030 +typedef struct RST_s
5031 +{
5032 + U32 filler [0x0006] ;
5033 + U32 sysid ;
5034 + U32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
5035 + U32 reset ;
5036 + U32 bcv ;
5037 + U32 cea ;
5038 +} volatile * RST_t ;
5039 +
5040 +enum
5041 +{
5042 + SYSID_rev_b = 0,
5043 + SYSID_rev_m = 0x000000ff,
5044 + SYSID_imp_b = 8,
5045 + SYSID_imp_m = 0x000fff00,
5046 + SYSID_vendor_b = 20,
5047 + SYSID_vendor_m = 0xfff00000,
5048 +
5049 + BCV_pll_b = 0,
5050 + BCV_pll_m = 0x0000000f,
5051 + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
5052 + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
5053 + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
5054 + BCV_pll_SlowMul5_v = 0x3, // PCLK=4*CLK.
5055 + BCV_pll_Mul5_v = 0x4, // PCLK=6*CLK.
5056 + BCV_pll_SlowMul6_v = 0x5, // PCLK=8*CLK.
5057 + BCV_pll_Mul6_v = 0x6, // PCLK=8*CLK.
5058 + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
5059 + BCV_pll_Mul10_v = 0x8, // PCLK=8*CLK.
5060 + BCV_pll_Res5_v = 0x9,
5061 + BCV_pll_Res6_v = 0xa,
5062 + BCV_pll_Res7_v = 0xb,
5063 + BCV_pll_Res8_v = 0xc,
5064 + BCV_pll_Res13_v = 0xd,
5065 + BCV_pll_Res14_v = 0xe,
5066 + BCV_pll_Res15_v = 0xf,
5067 + BCV_clkDiv_b = 4,
5068 + BCV_clkDiv_m = 0x00000030,
5069 + BCV_clkDiv_Div1_v = 0x0,
5070 + BCV_clkDiv_Div2_v = 0x1,
5071 + BCV_clkDiv_Div4_v = 0x2,
5072 + BCV_clkDiv_Res3_v = 0x3,
5073 + BCV_bigEndian_b = 6,
5074 + BCV_bigEndian_m = 0x00000040,
5075 + BCV_resetFast_b = 7,
5076 + BCV_resetFast_m = 0x00000080,
5077 + BCV_pciMode_b = 8,
5078 + BCV_pciMode_m = 0x00000100,
5079 + BCV_pciMode_disabled_v = 0, // PCI is disabled.
5080 + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
5081 + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
5082 + BCV_pciMode_external_v = 3, // host, external arbiter.
5083 + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
5084 + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
5085 + BCV_pciMode_res6_v = 6,
5086 + BCV_pciMode_res7_v = 7,
5087 + BCV_watchDisable_b = 11,
5088 + BCV_watchDisable_m = 0x00000800,
5089 + BCV_pllTest_b = 12,
5090 + BCV_pllTest_m = 0x00001000,
5091 + BCV_nvramInit_b = 13,
5092 + BCV_nvramInit_m = 0x00002000,
5093 + BCV_clksyncTstMd_b = 14,
5094 + BCV_clksyncTstMd_m = 0x00004000,
5095 + BCV_delayBypass_b = 15,
5096 + BCV_delayByPass_m = 0x00008000,
5097 +} ;
5098 +#endif // __IDT_RST_H__
5099 diff -urN linux.old/include/asm-mips/rc32434/spi.h linux.dev/include/asm-mips/rc32434/spi.h
5100 --- linux.old/include/asm-mips/rc32434/spi.h 1970-01-01 01:00:00.000000000 +0100
5101 +++ linux.dev/include/asm-mips/rc32434/spi.h 2006-10-11 21:56:38.000000000 +0200
5102 @@ -0,0 +1,100 @@
5103 +#ifndef __IDT_SPI_H__
5104 +#define __IDT_SPI_H__
5105 +
5106 +/*******************************************************************************
5107 + *
5108 + * Copyright 2002 Integrated Device Technology, Inc.
5109 + * All rights reserved.
5110 + *
5111 + * Serial Peripheral Interface register definitions.
5112 + *
5113 + * File : $Id: spi.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5114 + *
5115 + * Author : ryan.holmQVist@idt.com
5116 + * Date : 20011005
5117 + * Update :
5118 + * $Log: spi.h,v $
5119 + * Revision 1.2 2002/06/06 18:34:05 astichte
5120 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5121 + *
5122 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5123 + * jba File moved from vcode/include/idt/acacia
5124 + *
5125 + *
5126 + ******************************************************************************/
5127 +
5128 +#include <asm/rc32434/types.h>
5129 +
5130 +enum
5131 +{
5132 + SPI0_PhysicalAddress = 0x18070000,
5133 + SPI_PhysicalAddress = SPI0_PhysicalAddress,
5134 +
5135 + SPI0_VirtualAddress = 0xb8070000,
5136 + SPI_VirtualAddress = SPI0_VirtualAddress,
5137 +} ;
5138 +
5139 +typedef struct
5140 +{
5141 + U32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
5142 + U32 spc ; // spi control reg use SPC_
5143 + U32 sps ; // spi status reg use SPS_
5144 + U32 spd ; // spi data reg use SPD_
5145 + U32 siofunc ; // serial IO function use SIOFUNC_
5146 + U32 siocfg ; // serial IO config use SIOCFG_
5147 + U32 siod; // serial IO data use SIOD_
5148 +} volatile *SPI_t ;
5149 +
5150 +enum
5151 +{
5152 + SPCP_div_b = 0,
5153 + SPCP_div_m = 0x000000ff,
5154 + SPC_spr_b = 0,
5155 + SPC_spr_m = 0x00000003,
5156 + SPC_spr_div2_v = 0,
5157 + SPC_spr_div4_v = 1,
5158 + SPC_spr_div16_v = 2,
5159 + SPC_spr_div32_v = 3,
5160 + SPC_cpha_b = 2,
5161 + SPC_cpha_m = 0x00000004,
5162 + SPC_cpol_b = 3,
5163 + SPC_cpol_m = 0x00000008,
5164 + SPC_mstr_b = 4,
5165 + SPC_mstr_m = 0x00000010,
5166 + SPC_spe_b = 6,
5167 + SPC_spe_m = 0x00000040,
5168 + SPC_spie_b = 7,
5169 + SPC_spie_m = 0x00000080,
5170 +
5171 + SPS_modf_b = 4,
5172 + SPS_modf_m = 0x00000010,
5173 + SPS_wcol_b = 6,
5174 + SPS_wcol_m = 0x00000040,
5175 + SPS_spif_b = 7,
5176 + SPS_spif_m = 0x00000070,
5177 +
5178 + SPD_data_b = 0,
5179 + SPD_data_m = 0x000000ff,
5180 +
5181 + SIOFUNC_sdo_b = 0,
5182 + SIOFUNC_sdo_m = 0x00000001,
5183 + SIOFUNC_sdi_b = 1,
5184 + SIOFUNC_sdi_m = 0x00000002,
5185 + SIOFUNC_sck_b = 2,
5186 + SIOFUNC_sck_m = 0x00000004,
5187 +
5188 + SIOCFG_sdo_b = 0,
5189 + SIOCFG_sdo_m = 0x00000001,
5190 + SIOCFG_sdi_b = 1,
5191 + SIOCFG_sdi_m = 0x00000002,
5192 + SIOCFG_sck_b = 2,
5193 + SIOCFG_sck_m = 0x00000004,
5194 +
5195 + SIOD_sdo_b = 0,
5196 + SIOD_sdo_m = 0x00000001,
5197 + SIOD_sdi_b = 1,
5198 + SIOD_sdi_m = 0x00000002,
5199 + SIOD_sck_b = 2,
5200 + SIOD_sck_m = 0x00000004,
5201 +} ;
5202 +#endif // __IDT_SPI_H__
5203 diff -urN linux.old/include/asm-mips/rc32434/timer.h linux.dev/include/asm-mips/rc32434/timer.h
5204 --- linux.old/include/asm-mips/rc32434/timer.h 1970-01-01 01:00:00.000000000 +0100
5205 +++ linux.dev/include/asm-mips/rc32434/timer.h 2006-10-11 21:56:38.000000000 +0200
5206 @@ -0,0 +1,91 @@
5207 +/**************************************************************************
5208 + *
5209 + * BRIEF MODULE DESCRIPTION
5210 + * Definitions for timer registers
5211 + *
5212 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5213 + *
5214 + * This program is free software; you can redistribute it and/or modify it
5215 + * under the terms of the GNU General Public License as published by the
5216 + * Free Software Foundation; either version 2 of the License, or (at your
5217 + * option) any later version.
5218 + *
5219 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5220 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5221 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5222 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5223 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5224 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5225 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5226 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5227 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5228 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5229 + *
5230 + * You should have received a copy of the GNU General Public License along
5231 + * with this program; if not, write to the Free Software Foundation, Inc.,
5232 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5233 + *
5234 + *
5235 + **************************************************************************
5236 + * May 2004 rkt,neb.
5237 + *
5238 + * Initial Release
5239 + *
5240 + *
5241 + *
5242 + **************************************************************************
5243 + */
5244 +
5245 +#ifndef __IDT_TIM_H__
5246 +#define __IDT_TIM_H__
5247 +
5248 +enum
5249 +{
5250 + TIM0_PhysicalAddress = 0x18028000,
5251 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
5252 +
5253 + TIM0_VirtualAddress = 0xb8028000,
5254 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
5255 +} ;
5256 +
5257 +enum
5258 +{
5259 + TIM_Count = 3,
5260 +} ;
5261 +
5262 +struct TIM_CNTR_s
5263 +{
5264 + u32 count ;
5265 + u32 compare ;
5266 + u32 ctc ; //use CTC_
5267 +} ;
5268 +
5269 +typedef struct TIM_s
5270 +{
5271 + struct TIM_CNTR_s tim [TIM_Count] ;
5272 + u32 rcount ; //use RCOUNT_
5273 + u32 rcompare ; //use RCOMPARE_
5274 + u32 rtc ; //use RTC_
5275 +} volatile * TIM_t ;
5276 +
5277 +enum
5278 +{
5279 + CTC_en_b = 0,
5280 + CTC_en_m = 0x00000001,
5281 + CTC_to_b = 1,
5282 + CTC_to_m = 0x00000002,
5283 +
5284 + RCOUNT_count_b = 0,
5285 + RCOUNT_count_m = 0x0000ffff,
5286 + RCOMPARE_compare_b = 0,
5287 + RCOMPARE_compare_m = 0x0000ffff,
5288 + RTC_ce_b = 0,
5289 + RTC_ce_m = 0x00000001,
5290 + RTC_to_b = 1,
5291 + RTC_to_m = 0x00000002,
5292 + RTC_rqe_b = 2,
5293 + RTC_rqe_m = 0x00000004,
5294 +
5295 +} ;
5296 +#endif // __IDT_TIM_H__
5297 +
5298 diff -urN linux.old/include/asm-mips/rc32434/tim.h linux.dev/include/asm-mips/rc32434/tim.h
5299 --- linux.old/include/asm-mips/rc32434/tim.h 1970-01-01 01:00:00.000000000 +0100
5300 +++ linux.dev/include/asm-mips/rc32434/tim.h 2006-10-11 21:56:38.000000000 +0200
5301 @@ -0,0 +1,78 @@
5302 +#ifndef __IDT_TIM_H__
5303 +#define __IDT_TIM_H__
5304 +
5305 +/*******************************************************************************
5306 + *
5307 + * Copyright 2002 Integrated Device Technology, Inc.
5308 + * All rights reserved.
5309 + *
5310 + * Timer register definition.
5311 + *
5312 + * File : $Id: tim.h,v 1.2 2002/06/06 18:34:05 astichte Exp $
5313 + *
5314 + * Author : ryan.holmQVist@idt.com
5315 + * Date : 20011005
5316 + * Update :
5317 + * $Log: tim.h,v $
5318 + * Revision 1.2 2002/06/06 18:34:05 astichte
5319 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5320 + *
5321 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5322 + * jba File moved from vcode/include/idt/acacia
5323 + *
5324 + *
5325 + ******************************************************************************/
5326 +
5327 +
5328 +#include <asm/rc32434/types.h>
5329 +
5330 +enum
5331 +{
5332 + TIM0_PhysicalAddress = 0x18028000,
5333 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
5334 +
5335 + TIM0_VirtualAddress = 0xb8028000,
5336 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
5337 +} ;
5338 +
5339 +enum
5340 +{
5341 + TIM_Count = 3,
5342 +} ;
5343 +
5344 +struct TIM_CNTR_s
5345 +{
5346 + U32 count ;
5347 + U32 compare ;
5348 + U32 ctc ; //use CTC_
5349 +} ;
5350 +
5351 +typedef struct TIM_s
5352 +{
5353 + struct TIM_CNTR_s tim [TIM_Count] ;
5354 + U32 rcount ; //use RCOUNT_
5355 + U32 rcompare ; //use RCOMPARE_
5356 + U32 rtc ; //use RTC_
5357 +} volatile * TIM_t ;
5358 +
5359 +enum
5360 +{
5361 + CTC_en_b = 0,
5362 + CTC_en_m = 0x00000001,
5363 + CTC_to_b = 1,
5364 + CTC_to_m = 0x00000002,
5365 +
5366 + RCOUNT_count_b = 0,
5367 + RCOUNT_count_m = 0x0000ffff,
5368 + RCOMPARE_compare_b = 0,
5369 + RCOMPARE_compare_m = 0x0000ffff,
5370 + RTC_ce_b = 0,
5371 + RTC_ce_m = 0x00000001,
5372 + RTC_to_b = 1,
5373 + RTC_to_m = 0x00000002,
5374 + RTC_rqe_b = 2,
5375 + RTC_rqe_m = 0x00000004,
5376 +
5377 +} ;
5378 +#endif // __IDT_TIM_H__
5379 +
5380 diff -urN linux.old/include/asm-mips/rc32434/types.h linux.dev/include/asm-mips/rc32434/types.h
5381 --- linux.old/include/asm-mips/rc32434/types.h 1970-01-01 01:00:00.000000000 +0100
5382 +++ linux.dev/include/asm-mips/rc32434/types.h 2006-10-11 21:56:38.000000000 +0200
5383 @@ -0,0 +1,39 @@
5384 +#ifndef __IDT_TYPES_H__
5385 +#define __IDT_TYPES_H__
5386 +
5387 +/*******************************************************************************
5388 + *
5389 + * Copyright 2002 Integrated Device Technology, Inc.
5390 + * All rights reserved.
5391 + *
5392 + * Common typedefs used in IDT-generated code.
5393 + *
5394 + * File : $Id: types.h,v 1.1 2002/06/06 16:16:56 astichte Exp $
5395 + *
5396 + * Author : Allen.Stichter@idt.com
5397 + * Date : 20020606
5398 + * Update :
5399 + * $Log: types.h,v $
5400 + * Revision 1.1 2002/06/06 16:16:56 astichte
5401 + * Added
5402 + *
5403 + *
5404 + ******************************************************************************/
5405 +
5406 +typedef unsigned char U8 ;
5407 +typedef signed char S8 ;
5408 +
5409 +typedef unsigned short U16 ;
5410 +typedef signed short S16 ;
5411 +
5412 +typedef unsigned int U32 ;
5413 +typedef signed int S32 ;
5414 +
5415 +typedef unsigned long long U64 ;
5416 +typedef signed long long S64 ;
5417 +
5418 +#ifndef __cplusplus
5419 + typedef U32 bool ; // (false == 0), (true is != false)
5420 +#endif // __cplusplus
5421 +
5422 +#endif // __IDT_TYPES_H__
5423 diff -urN linux.old/include/asm-mips/rc32434/uart.h linux.dev/include/asm-mips/rc32434/uart.h
5424 --- linux.old/include/asm-mips/rc32434/uart.h 1970-01-01 01:00:00.000000000 +0100
5425 +++ linux.dev/include/asm-mips/rc32434/uart.h 2006-10-11 21:56:38.000000000 +0200
5426 @@ -0,0 +1,178 @@
5427 +#ifndef __IDT_UART_H__
5428 +#define __IDT_UART_H__
5429 +
5430 +/*******************************************************************************
5431 + *
5432 + * Copyright 2002 Integrated Device Technology, Inc.
5433 + * All rights reserved.
5434 + *
5435 + * UART register definitions.
5436 + *
5437 + * File : $Id: uart.h,v 1.3 2002/06/06 18:34:05 astichte Exp $
5438 + *
5439 + * Author : Allen.Stichter@idt.com
5440 + * Date : 20020118
5441 + * Update :
5442 + * $Log: uart.h,v $
5443 + * Revision 1.3 2002/06/06 18:34:05 astichte
5444 + * Added XXX_PhysicalAddress and XXX_VirtualAddress
5445 + *
5446 + * Revision 1.2 2002/06/04 17:37:52 astichte
5447 + * Updated register definitions.
5448 + *
5449 + * Revision 1.1 2002/05/29 17:33:25 sysarch
5450 + * jba File moved from vcode/include/idt/acacia
5451 + *
5452 + *
5453 + ******************************************************************************/
5454 +
5455 +#include <asm/rc32434/types.h>
5456 +
5457 +enum
5458 +{
5459 + UART_PhysicalAddress = 0x18058000,
5460 + UART_PhysicalAddress = UART_PhysicalAddress, // Default
5461 +
5462 + UART_VirtualAddress = 0xb8058000,
5463 + UART_VirtualAddress = UART_VirtualAddress, // Default
5464 +} ;
5465 +
5466 +/*
5467 + * Register definitions are in bytes so we can handle endian problems.
5468 + */
5469 +
5470 +typedef struct UART_s
5471 +{
5472 + union
5473 + {
5474 + U32 const uartrb ; // 0x00 - DLAB=0, read.
5475 + U32 uartth ; // 0x00 - DLAB=0, write.
5476 + U32 uartdll ; // 0x00 - DLAB=1, read/write.
5477 + } ;
5478 +
5479 + union
5480 + {
5481 + U32 uartie ; // 0x04 - DLAB=0, read/write.
5482 + U32 uartdlh ; // 0x04 - DLAB=1, read/write.
5483 + } ;
5484 + union
5485 + {
5486 + U32 const uartii ; // 0x08 - DLAB=0, read.
5487 + U32 uartfc ; // 0x08 - DLAB=0, write.
5488 + } ;
5489 +
5490 + U32 uartlc ; // 0x0c
5491 + U32 uartmc ; // 0x10
5492 + U32 uartls ; // 0x14
5493 + U32 uartms ; // 0x18
5494 + U32 uarts ; // 0x1c
5495 +} volatile *UART_t ;
5496 +
5497 +// Reset registers.
5498 +typedef U32 volatile *UARTRR_t ;
5499 +
5500 +enum
5501 +{
5502 + UARTIE_rda_b = 0,
5503 + UARTIE_rda_m = 0x00000001,
5504 + UARTIE_the_b = 1,
5505 + UARTIE_the_m = 0x00000002,
5506 + UARTIE_rls_b = 2,
5507 + UARTIE_rls_m = 0x00000004,
5508 + UARTIE_ems_b = 3,
5509 + UARTIE_ems_m = 0x00000008,
5510 +
5511 + UARTII_pi_b = 0,
5512 + UARTII_pi_m = 0x00000001,
5513 + UARTII_iid_b = 1,
5514 + UARTII_iid_m = 0x0000000e,
5515 + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
5516 + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
5517 + UARTII_iid_rda_v = 2, // Receive data available
5518 + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
5519 + UARTII_iid_res4_v = 4, // reserved.
5520 + UARTII_iid_res5_v = 5, // reserved.
5521 + UARTII_iid_cto_v = 6, // Character timeout.
5522 + UARTII_iid_res7_v = 7, // reserved.
5523 +
5524 + UARTFC_en_b = 0,
5525 + UARTFC_en_m = 0x00000001,
5526 + UARTFC_rr_b = 1,
5527 + UARTFC_rr_m = 0x00000002,
5528 + UARTFC_tr_b = 2,
5529 + UARTFC_tr_m = 0x00000004,
5530 + UARTFC_dms_b = 3,
5531 + UARTFC_dms_m = 0x00000008,
5532 + UARTFC_rt_b = 6,
5533 + UARTFC_rt_m = 0x000000c0,
5534 + UARTFC_rt_1Byte_v = 0,
5535 + UARTFC_rt_4Byte_v = 1,
5536 + UARTFC_rt_8Byte_v = 2,
5537 + UARTFC_rt_14Byte_v = 3,
5538 +
5539 + UARTLC_wls_b = 0,
5540 + UARTLC_wls_m = 0x00000003,
5541 + UARTLC_wls_5Bits_v = 0,
5542 + UARTLC_wls_6Bits_v = 1,
5543 + UARTLC_wls_7Bits_v = 2,
5544 + UARTLC_wls_8Bits_v = 3,
5545 + UARTLC_stb_b = 2,
5546 + UARTLC_stb_m = 0x00000004,
5547 + UARTLC_pen_b = 3,
5548 + UARTLC_pen_m = 0x00000008,
5549 + UARTLC_eps_b = 4,
5550 + UARTLC_eps_m = 0x00000010,
5551 + UARTLC_sp_b = 5,
5552 + UARTLC_sp_m = 0x00000020,
5553 + UARTLC_sb_b = 6,
5554 + UARTLC_sb_m = 0x00000040,
5555 + UARTLC_dlab_b = 7,
5556 + UARTLC_dlab_m = 0x00000080,
5557 +
5558 + UARTMC_dtr_b = 0,
5559 + UARTMC_dtr_m = 0x00000001,
5560 + UARTMC_rts_b = 1,
5561 + UARTMC_rts_m = 0x00000002,
5562 + UARTMC_o1_b = 2,
5563 + UARTMC_o1_m = 0x00000004,
5564 + UARTMC_o2_b = 3,
5565 + UARTMC_o2_m = 0x00000008,
5566 + UARTMC_lp_b = 4,
5567 + UARTMC_lp_m = 0x00000010,
5568 +
5569 + UARTLS_dr_b = 0,
5570 + UARTLS_dr_m = 0x00000001,
5571 + UARTLS_oe_b = 1,
5572 + UARTLS_oe_m = 0x00000002,
5573 + UARTLS_pe_b = 2,
5574 + UARTLS_pe_m = 0x00000004,
5575 + UARTLS_fe_b = 3,
5576 + UARTLS_fe_m = 0x00000008,
5577 + UARTLS_bi_b = 4,
5578 + UARTLS_bi_m = 0x00000010,
5579 + UARTLS_thr_b = 5,
5580 + UARTLS_thr_m = 0x00000020,
5581 + UARTLS_te_b = 6,
5582 + UARTLS_te_m = 0x00000040,
5583 + UARTLS_rfe_b = 7,
5584 + UARTLS_rfe_m = 0x00000080,
5585 +
5586 + UARTMS_dcts_b = 0,
5587 + UARTMS_dcts_m = 0x00000001,
5588 + UARTMS_ddsr_b = 1,
5589 + UARTMS_ddsr_m = 0x00000002,
5590 + UARTMS_teri_b = 2,
5591 + UARTMS_teri_m = 0x00000004,
5592 + UARTMS_ddcd_b = 3,
5593 + UARTMS_ddcd_m = 0x00000008,
5594 + UARTMS_cts_b = 4,
5595 + UARTMS_cts_m = 0x00000010,
5596 + UARTMS_dsr_b = 5,
5597 + UARTMS_dsr_m = 0x00000020,
5598 + UARTMS_ri_b = 6,
5599 + UARTMS_ri_m = 0x00000040,
5600 + UARTMS_dcd_b = 7,
5601 + UARTMS_dcd_m = 0x00000080,
5602 +} ;
5603 +
5604 +#endif // __IDT_UART_H__
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