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[openwrt/openwrt.git] / package / ath9k / src / drivers / net / wireless / ath9k / ath9k.h
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef ATH9K_H
18 #define ATH9K_H
19
20 #include <linux/io.h>
21
22 #define ATHEROS_VENDOR_ID 0x168c
23
24 #define AR5416_DEVID_PCI 0x0023
25 #define AR5416_DEVID_PCIE 0x0024
26 #define AR9160_DEVID_PCI 0x0027
27 #define AR9280_DEVID_PCI 0x0029
28 #define AR9280_DEVID_PCIE 0x002a
29
30 #define AR5416_AR9100_DEVID 0x000b
31
32 #define AR_SUBVENDOR_ID_NOG 0x0e11
33 #define AR_SUBVENDOR_ID_NEW_A 0x7065
34
35 #define HAL_TXERR_XRETRY 0x01
36 #define HAL_TXERR_FILT 0x02
37 #define HAL_TXERR_FIFO 0x04
38 #define HAL_TXERR_XTXOP 0x08
39 #define HAL_TXERR_TIMER_EXPIRED 0x10
40
41 #define HAL_TX_BA 0x01
42 #define HAL_TX_PWRMGMT 0x02
43 #define HAL_TX_DESC_CFG_ERR 0x04
44 #define HAL_TX_DATA_UNDERRUN 0x08
45 #define HAL_TX_DELIM_UNDERRUN 0x10
46 #define HAL_TX_SW_ABORTED 0x40
47 #define HAL_TX_SW_FILTERED 0x80
48
49 #define NBBY 8
50 #ifndef howmany
51 #define howmany(x, y) (((x)+((y)-1))/(y))
52 #endif
53
54 struct ath_tx_status {
55 u_int32_t ts_tstamp;
56 u_int16_t ts_seqnum;
57 u_int8_t ts_status;
58 u_int8_t ts_ratecode;
59 u_int8_t ts_rateindex;
60 int8_t ts_rssi;
61 u_int8_t ts_shortretry;
62 u_int8_t ts_longretry;
63 u_int8_t ts_virtcol;
64 u_int8_t ts_antenna;
65 u_int8_t ts_flags;
66 int8_t ts_rssi_ctl0;
67 int8_t ts_rssi_ctl1;
68 int8_t ts_rssi_ctl2;
69 int8_t ts_rssi_ext0;
70 int8_t ts_rssi_ext1;
71 int8_t ts_rssi_ext2;
72 u_int8_t pad[3];
73 u_int32_t ba_low;
74 u_int32_t ba_high;
75 u_int32_t evm0;
76 u_int32_t evm1;
77 u_int32_t evm2;
78 };
79
80 struct ath_rx_status {
81 u_int32_t rs_tstamp;
82 u_int16_t rs_datalen;
83 u_int8_t rs_status;
84 u_int8_t rs_phyerr;
85 int8_t rs_rssi;
86 u_int8_t rs_keyix;
87 u_int8_t rs_rate;
88 u_int8_t rs_antenna;
89 u_int8_t rs_more;
90 int8_t rs_rssi_ctl0;
91 int8_t rs_rssi_ctl1;
92 int8_t rs_rssi_ctl2;
93 int8_t rs_rssi_ext0;
94 int8_t rs_rssi_ext1;
95 int8_t rs_rssi_ext2;
96 u_int8_t rs_isaggr;
97 u_int8_t rs_moreaggr;
98 u_int8_t rs_num_delims;
99 u_int8_t rs_flags;
100 u_int32_t evm0;
101 u_int32_t evm1;
102 u_int32_t evm2;
103 };
104
105 #define HAL_RXERR_CRC 0x01
106 #define HAL_RXERR_PHY 0x02
107 #define HAL_RXERR_FIFO 0x04
108 #define HAL_RXERR_DECRYPT 0x08
109 #define HAL_RXERR_MIC 0x10
110
111 #define HAL_RX_MORE 0x01
112 #define HAL_RX_MORE_AGGR 0x02
113 #define HAL_RX_GI 0x04
114 #define HAL_RX_2040 0x08
115 #define HAL_RX_DELIM_CRC_PRE 0x10
116 #define HAL_RX_DELIM_CRC_POST 0x20
117 #define HAL_RX_DECRYPT_BUSY 0x40
118
119 enum hal_bool {
120 AH_FALSE = 0,
121 AH_TRUE = 1,
122 };
123
124 #define HAL_RXKEYIX_INVALID ((u_int8_t)-1)
125 #define HAL_TXKEYIX_INVALID ((u_int)-1)
126
127 struct ath_desc {
128 u_int32_t ds_link;
129 u_int32_t ds_data;
130 u_int32_t ds_ctl0;
131 u_int32_t ds_ctl1;
132 u_int32_t ds_hw[20];
133 union {
134 struct ath_tx_status tx;
135 struct ath_rx_status rx;
136 void *stats;
137 } ds_us;
138 void *ds_vdata;
139 } __packed;
140
141 #define ds_txstat ds_us.tx
142 #define ds_rxstat ds_us.rx
143 #define ds_stat ds_us.stats
144
145 #define HAL_TXDESC_CLRDMASK 0x0001
146 #define HAL_TXDESC_NOACK 0x0002
147 #define HAL_TXDESC_RTSENA 0x0004
148 #define HAL_TXDESC_CTSENA 0x0008
149 #define HAL_TXDESC_INTREQ 0x0010
150 #define HAL_TXDESC_VEOL 0x0020
151 #define HAL_TXDESC_EXT_ONLY 0x0040
152 #define HAL_TXDESC_EXT_AND_CTL 0x0080
153 #define HAL_TXDESC_VMF 0x0100
154 #define HAL_TXDESC_FRAG_IS_ON 0x0200
155
156 #define HAL_RXDESC_INTREQ 0x0020
157
158 enum hal_capability_type {
159 HAL_CAP_CIPHER = 0,
160 HAL_CAP_TKIP_MIC,
161 HAL_CAP_TKIP_SPLIT,
162 HAL_CAP_PHYCOUNTERS,
163 HAL_CAP_DIVERSITY,
164 HAL_CAP_PSPOLL,
165 HAL_CAP_TXPOW,
166 HAL_CAP_PHYDIAG,
167 HAL_CAP_MCAST_KEYSRCH,
168 HAL_CAP_TSF_ADJUST,
169 HAL_CAP_WME_TKIPMIC,
170 HAL_CAP_RFSILENT,
171 HAL_CAP_ANT_CFG_2GHZ,
172 HAL_CAP_ANT_CFG_5GHZ
173 };
174
175 struct hal_capabilities {
176 u_int halChanSpreadSupport:1,
177 halChapTuningSupport:1,
178 halMicAesCcmSupport:1,
179 halMicCkipSupport:1,
180 halMicTkipSupport:1,
181 halCipherAesCcmSupport:1,
182 halCipherCkipSupport:1,
183 halCipherTkipSupport:1,
184 halVEOLSupport:1,
185 halBssIdMaskSupport:1,
186 halMcastKeySrchSupport:1,
187 halTsfAddSupport:1,
188 halChanHalfRate:1,
189 halChanQuarterRate:1,
190 halHTSupport:1,
191 halGTTSupport:1,
192 halFastCCSupport:1,
193 halRfSilentSupport:1,
194 halWowSupport:1,
195 halCSTSupport:1,
196 halEnhancedPmSupport:1,
197 halAutoSleepSupport:1,
198 hal4kbSplitTransSupport:1,
199 halWowMatchPatternExact:1;
200 u_int32_t halWirelessModes;
201 u_int16_t halTotalQueues;
202 u_int16_t halKeyCacheSize;
203 u_int16_t halLow5GhzChan, halHigh5GhzChan;
204 u_int16_t halLow2GhzChan, halHigh2GhzChan;
205 u_int16_t halNumMRRetries;
206 u_int16_t halRtsAggrLimit;
207 u_int8_t halTxChainMask;
208 u_int8_t halRxChainMask;
209 u_int16_t halTxTrigLevelMax;
210 u_int16_t halRegCap;
211 u_int8_t halNumGpioPins;
212 u_int8_t halNumAntCfg2GHz;
213 u_int8_t halNumAntCfg5GHz;
214 };
215
216 struct hal_ops_config {
217 int ath_hal_dma_beacon_response_time;
218 int ath_hal_sw_beacon_response_time;
219 int ath_hal_additional_swba_backoff;
220 int ath_hal_6mb_ack;
221 int ath_hal_cwmIgnoreExtCCA;
222 u_int8_t ath_hal_pciePowerSaveEnable;
223 u_int8_t ath_hal_pcieL1SKPEnable;
224 u_int8_t ath_hal_pcieClockReq;
225 u_int32_t ath_hal_pcieWaen;
226 int ath_hal_pciePowerReset;
227 u_int8_t ath_hal_pcieRestore;
228 u_int8_t ath_hal_analogShiftReg;
229 u_int8_t ath_hal_htEnable;
230 u_int32_t ath_hal_ofdmTrigLow;
231 u_int32_t ath_hal_ofdmTrigHigh;
232 u_int32_t ath_hal_cckTrigHigh;
233 u_int32_t ath_hal_cckTrigLow;
234 u_int32_t ath_hal_enableANI;
235 u_int8_t ath_hal_noiseImmunityLvl;
236 u_int32_t ath_hal_ofdmWeakSigDet;
237 u_int32_t ath_hal_cckWeakSigThr;
238 u_int8_t ath_hal_spurImmunityLvl;
239 u_int8_t ath_hal_firStepLvl;
240 int8_t ath_hal_rssiThrHigh;
241 int8_t ath_hal_rssiThrLow;
242 u_int16_t ath_hal_diversityControl;
243 u_int16_t ath_hal_antennaSwitchSwap;
244 int ath_hal_serializeRegMode;
245 int ath_hal_intrMitigation;
246 int ath_hal_debug;
247 #define SPUR_DISABLE 0
248 #define SPUR_ENABLE_IOCTL 1
249 #define SPUR_ENABLE_EEPROM 2
250 #define AR_EEPROM_MODAL_SPURS 5
251 #define AR_SPUR_5413_1 1640
252 #define AR_SPUR_5413_2 1200
253 #define AR_NO_SPUR 0x8000
254 #define AR_BASE_FREQ_2GHZ 2300
255 #define AR_BASE_FREQ_5GHZ 4900
256 #define AR_SPUR_FEEQ_BOUND_HT40 19
257 #define AR_SPUR_FEEQ_BOUND_HT20 10
258 int ath_hal_spurMode;
259 u_int16_t ath_hal_spurChans[AR_EEPROM_MODAL_SPURS][2];
260 };
261
262 enum hal_tx_queue {
263 HAL_TX_QUEUE_INACTIVE = 0,
264 HAL_TX_QUEUE_DATA,
265 HAL_TX_QUEUE_BEACON,
266 HAL_TX_QUEUE_CAB,
267 HAL_TX_QUEUE_UAPSD,
268 HAL_TX_QUEUE_PSPOLL
269 };
270
271 #define HAL_NUM_TX_QUEUES 10
272
273 enum hal_tx_queue_subtype {
274 HAL_WME_AC_BK = 0,
275 HAL_WME_AC_BE,
276 HAL_WME_AC_VI,
277 HAL_WME_AC_VO,
278 HAL_WME_UPSD
279 };
280
281 enum hal_tx_queue_flags {
282 TXQ_FLAG_TXOKINT_ENABLE = 0x0001,
283 TXQ_FLAG_TXERRINT_ENABLE = 0x0001,
284 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002,
285 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004,
286 TXQ_FLAG_TXURNINT_ENABLE = 0x0008,
287 TXQ_FLAG_BACKOFF_DISABLE = 0x0010,
288 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020,
289 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040,
290 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
291 };
292
293 struct hal_txq_info {
294 u_int32_t tqi_ver;
295 enum hal_tx_queue_subtype tqi_subtype;
296 enum hal_tx_queue_flags tqi_qflags;
297 u_int32_t tqi_priority;
298 u_int32_t tqi_aifs;
299 u_int32_t tqi_cwmin;
300 u_int32_t tqi_cwmax;
301 u_int16_t tqi_shretry;
302 u_int16_t tqi_lgretry;
303 u_int32_t tqi_cbrPeriod;
304 u_int32_t tqi_cbrOverflowLimit;
305 u_int32_t tqi_burstTime;
306 u_int32_t tqi_readyTime;
307 u_int32_t tqi_compBuf;
308 };
309
310 #define HAL_TQI_NONVAL 0xffff
311
312 #define HAL_TXQ_USEDEFAULT ((u_int32_t) -1)
313
314 #define HAL_COMP_BUF_MAX_SIZE 9216
315 #define HAL_COMP_BUF_ALIGN_SIZE 512
316 #define HAL_DECOMP_MASK_SIZE 128
317
318 #define HAL_READY_TIME_LO_BOUND 50
319 #define HAL_READY_TIME_HI_BOUND 96
320
321 enum hal_pkt_type {
322 HAL_PKT_TYPE_NORMAL = 0,
323 HAL_PKT_TYPE_ATIM,
324 HAL_PKT_TYPE_PSPOLL,
325 HAL_PKT_TYPE_BEACON,
326 HAL_PKT_TYPE_PROBE_RESP,
327 HAL_PKT_TYPE_CHIRP,
328 HAL_PKT_TYPE_GRP_POLL,
329 };
330
331 struct hal_tx_queue_info {
332 u_int32_t tqi_ver;
333 enum hal_tx_queue tqi_type;
334 enum hal_tx_queue_subtype tqi_subtype;
335 enum hal_tx_queue_flags tqi_qflags;
336 u_int32_t tqi_priority;
337 u_int32_t tqi_aifs;
338 u_int32_t tqi_cwmin;
339 u_int32_t tqi_cwmax;
340 u_int16_t tqi_shretry;
341 u_int16_t tqi_lgretry;
342 u_int32_t tqi_cbrPeriod;
343 u_int32_t tqi_cbrOverflowLimit;
344 u_int32_t tqi_burstTime;
345 u_int32_t tqi_readyTime;
346 u_int32_t tqi_physCompBuf;
347 u_int32_t tqi_intFlags;
348 };
349
350 enum hal_rx_filter {
351 HAL_RX_FILTER_UCAST = 0x00000001,
352 HAL_RX_FILTER_MCAST = 0x00000002,
353 HAL_RX_FILTER_BCAST = 0x00000004,
354 HAL_RX_FILTER_CONTROL = 0x00000008,
355 HAL_RX_FILTER_BEACON = 0x00000010,
356 HAL_RX_FILTER_PROM = 0x00000020,
357 HAL_RX_FILTER_PROBEREQ = 0x00000080,
358 HAL_RX_FILTER_PSPOLL = 0x00004000,
359 HAL_RX_FILTER_PHYERR = 0x00000100,
360 HAL_RX_FILTER_PHYRADAR = 0x00002000,
361 };
362
363 enum hal_int {
364 HAL_INT_RX = 0x00000001,
365 HAL_INT_RXDESC = 0x00000002,
366 HAL_INT_RXNOFRM = 0x00000008,
367 HAL_INT_RXEOL = 0x00000010,
368 HAL_INT_RXORN = 0x00000020,
369 HAL_INT_TX = 0x00000040,
370 HAL_INT_TXDESC = 0x00000080,
371 HAL_INT_TIM_TIMER = 0x00000100,
372 HAL_INT_TXURN = 0x00000800,
373 HAL_INT_MIB = 0x00001000,
374 HAL_INT_RXPHY = 0x00004000,
375 HAL_INT_RXKCM = 0x00008000,
376 HAL_INT_SWBA = 0x00010000,
377 HAL_INT_BMISS = 0x00040000,
378 HAL_INT_BNR = 0x00100000,
379 HAL_INT_TIM = 0x00200000,
380 HAL_INT_DTIM = 0x00400000,
381 HAL_INT_DTIMSYNC = 0x00800000,
382 HAL_INT_GPIO = 0x01000000,
383 HAL_INT_CABEND = 0x02000000,
384 HAL_INT_CST = 0x10000000,
385 HAL_INT_GTT = 0x20000000,
386 HAL_INT_FATAL = 0x40000000,
387 HAL_INT_GLOBAL = 0x80000000,
388 HAL_INT_BMISC = HAL_INT_TIM
389 | HAL_INT_DTIM | HAL_INT_DTIMSYNC | HAL_INT_CABEND,
390 HAL_INT_COMMON = HAL_INT_RXNOFRM
391 | HAL_INT_RXDESC
392 | HAL_INT_RXEOL
393 | HAL_INT_RXORN
394 | HAL_INT_TXURN
395 | HAL_INT_TXDESC
396 | HAL_INT_MIB
397 | HAL_INT_RXPHY
398 | HAL_INT_RXKCM | HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_GPIO,
399 HAL_INT_NOCARD = 0xffffffff
400 };
401
402 struct hal_rate_table {
403 int rateCount;
404 u_int8_t rateCodeToIndex[256];
405 struct {
406 u_int8_t valid;
407 u_int8_t phy;
408 u_int32_t rateKbps;
409 u_int8_t rateCode;
410 u_int8_t shortPreamble;
411 u_int8_t dot11Rate;
412 u_int8_t controlRate;
413 u_int16_t lpAckDuration;
414 u_int16_t spAckDuration;
415 } info[32];
416 };
417
418 #define HAL_RATESERIES_RTS_CTS 0x0001
419 #define HAL_RATESERIES_2040 0x0002
420 #define HAL_RATESERIES_HALFGI 0x0004
421
422 struct hal_11n_rate_series {
423 u_int Tries;
424 u_int Rate;
425 u_int PktDuration;
426 u_int ChSel;
427 u_int RateFlags;
428 };
429
430 struct hal_channel {
431 u_int16_t channel;
432 u_int32_t channelFlags;
433 u_int8_t privFlags;
434 int8_t maxRegTxPower;
435 int8_t maxTxPower;
436 int8_t minTxPower;
437 };
438
439 #define CHANNEL_CW_INT 0x00002
440 #define CHANNEL_CCK 0x00020
441 #define CHANNEL_OFDM 0x00040
442 #define CHANNEL_2GHZ 0x00080
443 #define CHANNEL_5GHZ 0x00100
444 #define CHANNEL_PASSIVE 0x00200
445 #define CHANNEL_DYN 0x00400
446 #define CHANNEL_HALF 0x04000
447 #define CHANNEL_QUARTER 0x08000
448 #define CHANNEL_HT20 0x10000
449 #define CHANNEL_HT40PLUS 0x20000
450 #define CHANNEL_HT40MINUS 0x40000
451
452 #define CHANNEL_INTERFERENCE 0x01
453 #define CHANNEL_DFS 0x02
454 #define CHANNEL_4MS_LIMIT 0x04
455 #define CHANNEL_DFS_CLEAR 0x08
456 #define CHANNEL_DISALLOW_ADHOC 0x10
457 #define CHANNEL_PER_11D_ADHOC 0x20
458
459 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
460 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
461 #define CHANNEL_PUREG (CHANNEL_2GHZ|CHANNEL_OFDM)
462 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
463 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
464 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
465 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
466 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
467 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
468 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
469 #define CHANNEL_ALL \
470 (CHANNEL_OFDM| \
471 CHANNEL_CCK| \
472 CHANNEL_2GHZ | \
473 CHANNEL_5GHZ | \
474 CHANNEL_HT20 | \
475 CHANNEL_HT40PLUS | \
476 CHANNEL_HT40MINUS)
477
478 struct hal_channel_internal {
479 u_int16_t channel;
480 u_int32_t channelFlags;
481 u_int8_t privFlags;
482 int8_t maxRegTxPower;
483 int8_t maxTxPower;
484 int8_t minTxPower;
485 enum hal_bool bssSendHere;
486 u_int8_t gainI;
487 enum hal_bool iqCalValid;
488 int32_t CalValid;
489 enum hal_bool oneTimeCalsDone;
490 int8_t iCoff;
491 int8_t qCoff;
492 int16_t rawNoiseFloor;
493 int16_t noiseFloorAdjust;
494 int8_t antennaMax;
495 u_int32_t regDmnFlags;
496 u_int32_t conformanceTestLimit;
497 u_int64_t ah_tsf_last;
498 u_int64_t ah_channel_time;
499 u_int16_t mainSpur;
500 u_int64_t dfsTsf;
501 #ifdef ATH_NF_PER_CHAN
502 struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];
503 #endif
504 };
505
506 #define HAL_SPUR_VAL_MASK 0x3FFF
507 #define HAL_SPUR_CHAN_WIDTH 87
508 #define HAL_BIN_WIDTH_BASE_100HZ 3125
509 #define HAL_MAX_BINS_ALLOWED 28
510
511 #define IS_CHAN_A(_c) ((((_c)->channelFlags & CHANNEL_A) == CHANNEL_A) || \
512 (((_c)->channelFlags & CHANNEL_A_HT20) == CHANNEL_A_HT20) || \
513 (((_c)->channelFlags & CHANNEL_A_HT40PLUS) == CHANNEL_A_HT40PLUS) || \
514 (((_c)->channelFlags & CHANNEL_A_HT40MINUS) == CHANNEL_A_HT40MINUS))
515 #define IS_CHAN_B(_c) (((_c)->channelFlags & CHANNEL_B) == CHANNEL_B)
516 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
517 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
518 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
519 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
520 #define IS_CHAN_PUREG(_c) \
521 (((_c)->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG)
522 #define IS_CHAN_CCK(_c) (((_c)->channelFlags & CHANNEL_CCK) != 0)
523 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
524 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
525 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
526 #define IS_CHAN_PASSIVE(_c) (((_c)->channelFlags & CHANNEL_PASSIVE) != 0)
527 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
528 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
529 #define IS_CHAN_HT20(_c) (((_c)->channelFlags & CHANNEL_HT20) != 0)
530 #define IS_CHAN_HT40(_c) ((((_c)->channelFlags & CHANNEL_HT40PLUS) != 0) \
531 || (((_c)->channelFlags & CHANNEL_HT40MINUS) != 0))
532 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
533 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
534 #define IS_CHAN_A_5MHZ_SPACED(_c) \
535 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
536 (((_c)->channel % 20) != 0) && \
537 (((_c)->channel % 10) != 0))
538
539 struct hal_keyval {
540 u_int8_t kv_type;
541 u_int8_t kv_pad;
542 u_int16_t kv_len;
543 u_int8_t kv_val[16];
544 u_int8_t kv_mic[8];
545 u_int8_t kv_txmic[8];
546 };
547
548 enum hal_key_type {
549 HAL_KEY_TYPE_CLEAR,
550 HAL_KEY_TYPE_WEP,
551 HAL_KEY_TYPE_AES,
552 HAL_KEY_TYPE_TKIP,
553 };
554
555 enum hal_cipher {
556 HAL_CIPHER_WEP = 0,
557 HAL_CIPHER_AES_OCB = 1,
558 HAL_CIPHER_AES_CCM = 2,
559 HAL_CIPHER_CKIP = 3,
560 HAL_CIPHER_TKIP = 4,
561 HAL_CIPHER_CLR = 5,
562 HAL_CIPHER_MIC = 127
563 };
564
565 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
566 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
567 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
568 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
569 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
570 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
571 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
572 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
573 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
574
575 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
576 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
577 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
578 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
579 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
580 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
581
582 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
583 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
584
585 #define SD_NO_CTL 0xE0
586 #define NO_CTL 0xff
587 #define CTL_MODE_M 7
588 #define CTL_11A 0
589 #define CTL_11B 1
590 #define CTL_11G 2
591 #define CTL_2GHT20 5
592 #define CTL_5GHT20 6
593 #define CTL_2GHT40 7
594 #define CTL_5GHT40 8
595
596 #define AR_EEPROM_MAC(i) (0x1d+(i))
597 #define EEP_SCALE 100
598 #define EEP_DELTA 10
599
600 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
601 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
602 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
603 #define AR_EEPROM_RFSILENT_POLARITY_S 1
604
605 enum {
606 CTRY_DEBUG = 0x1ff,
607 CTRY_DEFAULT = 0
608 };
609
610 enum reg_ext_bitmap {
611 REG_EXT_JAPAN_MIDBAND = 1,
612 REG_EXT_FCC_DFS_HT40 = 2,
613 REG_EXT_JAPAN_NONDFS_HT40 = 3,
614 REG_EXT_JAPAN_DFS_HT40 = 4
615 };
616
617 struct hal_country_entry {
618 u_int16_t countryCode;
619 u_int16_t regDmnEnum;
620 u_int16_t regDmn5G;
621 u_int16_t regDmn2G;
622 u_int8_t isMultidomain;
623 u_int8_t iso[3];
624 };
625
626 #define HAL_DBG_RESET 0x00000001
627 #define HAL_DBG_PHY_IO 0x00000002
628 #define HAL_DBG_REG_IO 0x00000004
629 #define HAL_DBG_RF_PARAM 0x00000008
630 #define HAL_DBG_QUEUE 0x00000010
631 #define HAL_DBG_EEPROM_DUMP 0x00000020
632 #define HAL_DBG_EEPROM 0x00000040
633 #define HAL_DBG_NF_CAL 0x00000080
634 #define HAL_DBG_CALIBRATE 0x00000100
635 #define HAL_DBG_CHANNEL 0x00000200
636 #define HAL_DBG_INTERRUPT 0x00000400
637 #define HAL_DBG_DFS 0x00000800
638 #define HAL_DBG_DMA 0x00001000
639 #define HAL_DBG_REGULATORY 0x00002000
640 #define HAL_DBG_TX 0x00004000
641 #define HAL_DBG_TXDESC 0x00008000
642 #define HAL_DBG_RX 0x00010000
643 #define HAL_DBG_RXDESC 0x00020000
644 #define HAL_DBG_ANI 0x00040000
645 #define HAL_DBG_BEACON 0x00080000
646 #define HAL_DBG_KEYCACHE 0x00100000
647 #define HAL_DBG_POWER_MGMT 0x00200000
648 #define HAL_DBG_MALLOC 0x00400000
649 #define HAL_DBG_POWER_OVERRIDE 0x01000000
650 #define HAL_DBG_SPUR_MITIGATE 0x02000000
651 #define HAL_DBG_UNMASKABLE 0xFFFFFFFF
652
653 #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg)
654 #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg)
655
656 #define SM(_v, _f) (((_v) << _f##_S) & _f)
657 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
658 #define OS_REG_RMW(_a, _r, _set, _clr) \
659 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
660 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
661 REG_WRITE(_a, _r, \
662 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
663 #define OS_REG_SET_BIT(_a, _r, _f) \
664 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
665 #define OS_REG_CLR_BIT(_a, _r, _f) \
666 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
667 #define OS_REG_ath9k_regd_is_bit_set(_a, _r, _f) \
668 ((REG_READ(_a, _r) & _f) != 0)
669
670 #define HAL_COMP_BUF_MAX_SIZE 9216
671 #define HAL_COMP_BUF_ALIGN_SIZE 512
672
673 #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
674
675 #define INIT_AIFS 2
676 #define INIT_CWMIN 15
677 #define INIT_CWMIN_11B 31
678 #define INIT_CWMAX 1023
679 #define INIT_SH_RETRY 10
680 #define INIT_LG_RETRY 10
681 #define INIT_SSH_RETRY 32
682 #define INIT_SLG_RETRY 32
683
684 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4)
685
686 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
687 #define ATH_AMPDU_LIMIT_DEFAULT ATH_AMPDU_LIMIT_MAX
688
689 #define IEEE80211_WEP_IVLEN 3
690 #define IEEE80211_WEP_KIDLEN 1
691 #define IEEE80211_WEP_CRCLEN 4
692 #define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
693 (IEEE80211_WEP_IVLEN + \
694 IEEE80211_WEP_KIDLEN + \
695 IEEE80211_WEP_CRCLEN))
696 #define IEEE80211_MAX_LEN (2300 + FCS_LEN + \
697 (IEEE80211_WEP_IVLEN + \
698 IEEE80211_WEP_KIDLEN + \
699 IEEE80211_WEP_CRCLEN))
700
701 #define MAX_REG_ADD_COUNT 129
702 #define MAX_RATE_POWER 63
703
704 #define LE_READ_2(p) \
705 ((u_int16_t) \
706 ((((const u_int8_t *)(p))[0]) | \
707 (((const u_int8_t *)(p))[1] << 8)))
708
709 #define LE_READ_4(p) \
710 ((u_int32_t) \
711 ((((const u_int8_t *)(p))[0]) | \
712 (((const u_int8_t *)(p))[1] << 8) | \
713 (((const u_int8_t *)(p))[2] << 16) | \
714 (((const u_int8_t *)(p))[3] << 24)))
715
716 enum hal_status {
717 HAL_OK = 0,
718 HAL_ENXIO,
719 HAL_ENOMEM,
720 HAL_EIO,
721 HAL_EEMAGIC,
722 HAL_EEVERSION,
723 HAL_EELOCKED,
724 HAL_EEBADSUM,
725 HAL_EEREAD,
726 HAL_EEBADMAC,
727 HAL_EESIZE,
728 HAL_EEWRITE,
729 HAL_EINVAL,
730 HAL_ENOTSUPP,
731 HAL_ESELFTEST,
732 HAL_EINPROGRESS
733 };
734
735 enum hal_power_mode {
736 HAL_PM_AWAKE = 0,
737 HAL_PM_FULL_SLEEP,
738 HAL_PM_NETWORK_SLEEP,
739 HAL_PM_UNDEFINED
740 };
741
742 enum hal_rfgain {
743 HAL_RFGAIN_INACTIVE = 0,
744 HAL_RFGAIN_READ_REQUESTED,
745 HAL_RFGAIN_NEED_CHANGE
746 };
747
748 #define HAL_ANTENNA_MIN_MODE 0
749 #define HAL_ANTENNA_FIXED_A 1
750 #define HAL_ANTENNA_FIXED_B 2
751 #define HAL_ANTENNA_MAX_MODE 3
752
753 struct hal_mib_stats {
754 u_int32_t ackrcv_bad;
755 u_int32_t rts_bad;
756 u_int32_t rts_good;
757 u_int32_t fcs_bad;
758 u_int32_t beacons;
759 };
760
761 enum hal_ant_setting {
762 HAL_ANT_VARIABLE = 0,
763 HAL_ANT_FIXED_A,
764 HAL_ANT_FIXED_B
765 };
766
767 enum hal_opmode {
768 HAL_M_STA = 1,
769 HAL_M_IBSS = 0,
770 HAL_M_HOSTAP = 6,
771 HAL_M_MONITOR = 8
772 };
773
774 enum {
775 HAL_SLOT_TIME_6 = 6,
776 HAL_SLOT_TIME_9 = 9,
777 HAL_SLOT_TIME_20 = 20,
778 };
779
780
781 enum hal_ht_macmode {
782 HAL_HT_MACMODE_20 = 0,
783 HAL_HT_MACMODE_2040 = 1,
784 };
785
786 enum hal_ht_extprotspacing {
787 HAL_HT_EXTPROTSPACING_20 = 0,
788 HAL_HT_EXTPROTSPACING_25 = 1,
789 };
790
791 struct hal_ht_cwm {
792 enum hal_ht_macmode ht_macmode;
793 enum hal_ht_extprotspacing ht_extprotspacing;
794 };
795
796 enum hal_freq_band {
797 HAL_FREQ_BAND_5GHZ = 0,
798 HAL_FREQ_BAND_2GHZ = 1,
799 };
800
801 enum {
802 HAL_TRUE_CHIP = 1
803 };
804
805 enum hal_bus_type {
806 HAL_BUS_TYPE_PCI,
807 HAL_BUS_TYPE_AHB
808 };
809
810 enum hal_ani_cmd {
811 HAL_ANI_PRESENT = 0x1,
812 HAL_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
813 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4,
814 HAL_ANI_CCK_WEAK_SIGNAL_THR = 0x8,
815 HAL_ANI_FIRSTEP_LEVEL = 0x10,
816 HAL_ANI_SPUR_IMMUNITY_LEVEL = 0x20,
817 HAL_ANI_MODE = 0x40,
818 HAL_ANI_PHYERR_RESET = 0x80,
819 HAL_ANI_ALL = 0xff
820 };
821
822 enum phytype {
823 PHY_DS,
824 PHY_FH,
825 PHY_OFDM,
826 PHY_HT,
827 PHY_MAX
828 };
829 #define PHY_CCK PHY_DS
830
831 enum start_adhoc_option {
832 START_ADHOC_NO_11A,
833 START_ADHOC_PER_11D,
834 START_ADHOC_IN_11A,
835 START_ADHOC_IN_11B,
836 };
837
838 enum hal_tp_scale {
839 HAL_TP_SCALE_MAX = 0,
840 HAL_TP_SCALE_50,
841 HAL_TP_SCALE_25,
842 HAL_TP_SCALE_12,
843 HAL_TP_SCALE_MIN
844 };
845
846 enum ser_reg_mode {
847 SER_REG_MODE_OFF = 0,
848 SER_REG_MODE_ON = 1,
849 SER_REG_MODE_AUTO = 2,
850 };
851
852 #define AR_PHY_CCA_MAX_GOOD_VALUE -85
853 #define AR_PHY_CCA_MAX_HIGH_VALUE -62
854 #define AR_PHY_CCA_MIN_BAD_VALUE -121
855 #define AR_PHY_CCA_FILTERWINDOW_LENGTH_INIT 3
856 #define AR_PHY_CCA_FILTERWINDOW_LENGTH 5
857
858 #define HAL_NF_CAL_HIST_MAX 5
859 #define NUM_NF_READINGS 6
860
861 struct hal_nfcal_hist {
862 int16_t nfCalBuffer[HAL_NF_CAL_HIST_MAX];
863 u_int8_t currIndex;
864 int16_t privNF;
865 u_int8_t invalidNFcount;
866 };
867
868 struct hal_beacon_state {
869 u_int32_t bs_nexttbtt;
870 u_int32_t bs_nextdtim;
871 u_int32_t bs_intval;
872 #define HAL_BEACON_PERIOD 0x0000ffff
873 #define HAL_BEACON_ENA 0x00800000
874 #define HAL_BEACON_RESET_TSF 0x01000000
875 u_int32_t bs_dtimperiod;
876 u_int16_t bs_cfpperiod;
877 u_int16_t bs_cfpmaxduration;
878 u_int32_t bs_cfpnext;
879 u_int16_t bs_timoffset;
880 u_int16_t bs_bmissthreshold;
881 u_int32_t bs_sleepduration;
882 };
883
884 struct hal_node_stats {
885 u_int32_t ns_avgbrssi;
886 u_int32_t ns_avgrssi;
887 u_int32_t ns_avgtxrssi;
888 u_int32_t ns_avgtxrate;
889 };
890
891 #define HAL_RSSI_EP_MULTIPLIER (1<<7)
892 #define HAL_RATE_EP_MULTIPLIER (1<<7)
893
894 enum hal_gpio_output_mux_type {
895 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT,
896 HAL_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
897 HAL_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
898 HAL_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
899 HAL_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
900 HAL_GPIO_OUTPUT_MUX_NUM_ENTRIES
901 };
902
903 enum {
904 HAL_RESET_POWER_ON,
905 HAL_RESET_WARM,
906 HAL_RESET_COLD,
907 };
908
909 #define AH_USE_EEPROM 0x1
910 #define AH_IS_HB63 0x2
911
912 struct ath_hal {
913 u_int32_t ah_magic;
914 u_int16_t ah_devid;
915 u_int16_t ah_subvendorid;
916 void *ah_sc;
917 void __iomem *ah_sh;
918 u_int16_t ah_countryCode;
919 u_int32_t ah_macVersion;
920 u_int16_t ah_macRev;
921 u_int16_t ah_phyRev;
922 u_int16_t ah_analog5GhzRev;
923 u_int16_t ah_analog2GhzRev;
924 u_int8_t ah_decompMask[HAL_DECOMP_MASK_SIZE];
925 u_int32_t ah_flags;
926 enum hal_opmode ah_opmode;
927 struct hal_ops_config ah_config;
928 struct hal_capabilities ah_caps;
929 int16_t ah_powerLimit;
930 u_int16_t ah_maxPowerLevel;
931 u_int ah_tpScale;
932 u_int16_t ah_currentRD;
933 u_int16_t ah_currentRDExt;
934 u_int16_t ah_currentRDInUse;
935 u_int16_t ah_currentRD5G;
936 u_int16_t ah_currentRD2G;
937 char ah_iso[4];
938 enum start_adhoc_option ah_adHocMode;
939 enum hal_bool ah_commonMode;
940 struct hal_channel_internal ah_channels[150];
941 u_int ah_nchan;
942 struct hal_channel_internal *ah_curchan;
943 u_int16_t ah_rfsilent;
944 enum hal_bool ah_rfkillEnabled;
945 enum hal_bool ah_isPciExpress;
946 u_int16_t ah_txTrigLevel;
947 #ifndef ATH_NF_PER_CHAN
948 struct hal_nfcal_hist nfCalHist[NUM_NF_READINGS];
949 #endif
950 };
951
952 #define HDPRINTF(_ah, _m, _fmt, ...) do { \
953 if (((_ah) == NULL && _m == HAL_DBG_UNMASKABLE) || \
954 (((struct ath_hal *)(_ah))->ah_config.ath_hal_debug & _m)) \
955 printk(KERN_DEBUG _fmt , ##__VA_ARGS__); \
956 } while (0)
957
958 enum wireless_mode {
959 WIRELESS_MODE_11a = 0,
960 WIRELESS_MODE_11b = 2,
961 WIRELESS_MODE_11g = 3,
962 WIRELESS_MODE_11NA_HT20 = 6,
963 WIRELESS_MODE_11NG_HT20 = 7,
964 WIRELESS_MODE_11NA_HT40PLUS = 8,
965 WIRELESS_MODE_11NA_HT40MINUS = 9,
966 WIRELESS_MODE_11NG_HT40PLUS = 10,
967 WIRELESS_MODE_11NG_HT40MINUS = 11,
968 WIRELESS_MODE_MAX
969 };
970
971 enum {
972 ATH9K_MODE_SEL_11A = 0x00001,
973 ATH9K_MODE_SEL_11B = 0x00002,
974 ATH9K_MODE_SEL_11G = 0x00004,
975 ATH9K_MODE_SEL_11NG_HT20 = 0x00008,
976 ATH9K_MODE_SEL_11NA_HT20 = 0x00010,
977 ATH9K_MODE_SEL_11NG_HT40PLUS = 0x00020,
978 ATH9K_MODE_SEL_11NG_HT40MINUS = 0x00040,
979 ATH9K_MODE_SEL_11NA_HT40PLUS = 0x00080,
980 ATH9K_MODE_SEL_11NA_HT40MINUS = 0x00100,
981 ATH9K_MODE_SEL_2GHZ = (ATH9K_MODE_SEL_11B |
982 ATH9K_MODE_SEL_11G |
983 ATH9K_MODE_SEL_11NG_HT20),
984 ATH9K_MODE_SEL_5GHZ = (ATH9K_MODE_SEL_11A |
985 ATH9K_MODE_SEL_11NA_HT20),
986 ATH9K_MODE_SEL_ALL = 0xffffffff
987 };
988
989 struct chan_centers {
990 u_int16_t synth_center;
991 u_int16_t ctl_center;
992 u_int16_t ext_center;
993 };
994
995 enum hal_status ath_hal_getcapability(struct ath_hal *ah,
996 enum hal_capability_type type,
997 u_int32_t capability,
998 u_int32_t *result);
999 const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
1000 u_int mode);
1001 void ath9k_hw_detach(struct ath_hal *ah);
1002 struct ath_hal *ath9k_hw_attach(u_int16_t devid, void *sc, void __iomem *mem,
1003 enum hal_status *error);
1004 enum hal_bool ath9k_regd_init_channels(struct ath_hal *ah,
1005 struct hal_channel *chans,
1006 u_int maxchans, u_int *nchans,
1007 u_int8_t *regclassids,
1008 u_int maxregids, u_int *nregids,
1009 u_int16_t cc, u_int32_t modeSelect,
1010 enum hal_bool enableOutdoor,
1011 enum hal_bool
1012 enableExtendedChannels);
1013 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
1014 enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah,
1015 enum hal_int ints);
1016 enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
1017 struct hal_channel *chan,
1018 enum hal_ht_macmode macmode,
1019 u_int8_t txchainmask, u_int8_t rxchainmask,
1020 enum hal_ht_extprotspacing extprotspacing,
1021 enum hal_bool bChannelChange,
1022 enum hal_status *status);
1023 enum hal_bool ath9k_hw_phy_disable(struct ath_hal *ah);
1024 void ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
1025 enum hal_bool *isCalDone);
1026 void ath9k_hw_ani_monitor(struct ath_hal *ah,
1027 const struct hal_node_stats *stats,
1028 struct hal_channel *chan);
1029 enum hal_bool ath9k_hw_calibrate(struct ath_hal *ah,
1030 struct hal_channel *chan,
1031 u_int8_t rxchainmask,
1032 enum hal_bool longcal,
1033 enum hal_bool *isCalDone);
1034 int16_t ath9k_hw_getchan_noise(struct ath_hal *ah,
1035 struct hal_channel *chan);
1036 void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
1037 u_int16_t assocId);
1038 void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits);
1039 void ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
1040 u_int16_t assocId);
1041 enum hal_bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q);
1042 void ath9k_hw_reset_tsf(struct ath_hal *ah);
1043 enum hal_bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry);
1044 enum hal_bool ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
1045 const u_int8_t *mac);
1046 enum hal_bool ath9k_hw_set_keycache_entry(struct ath_hal *ah,
1047 u_int16_t entry,
1048 const struct hal_keyval *k,
1049 const u_int8_t *mac,
1050 int xorKey);
1051 enum hal_bool ath9k_hw_set_tsfadjust(struct ath_hal *ah,
1052 u_int32_t setting);
1053 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore);
1054 enum hal_bool ath9k_hw_intrpend(struct ath_hal *ah);
1055 enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked);
1056 enum hal_bool ath9k_hw_updatetxtriglevel(struct ath_hal *ah,
1057 enum hal_bool bIncTrigLevel);
1058 void ath9k_hw_procmibevent(struct ath_hal *ah,
1059 const struct hal_node_stats *stats);
1060 enum hal_bool ath9k_hw_setrxabort(struct ath_hal *ah, enum hal_bool set);
1061 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode);
1062 enum hal_bool ath9k_hw_setupxtxdesc(struct ath_hal *ah,
1063 struct ath_desc *ds,
1064 u_int txRate1, u_int txTries1,
1065 u_int txRate2, u_int txTries2,
1066 u_int txRate3, u_int txTries3);
1067 enum hal_bool ath9k_hw_phycounters(struct ath_hal *ah);
1068 enum hal_bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry);
1069 enum hal_bool ath9k_hw_getcapability(struct ath_hal *ah,
1070 enum hal_capability_type type,
1071 u_int32_t capability,
1072 u_int32_t *result);
1073 enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
1074 enum hal_capability_type type,
1075 u_int32_t capability,
1076 u_int32_t setting,
1077 enum hal_status *status);
1078 u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
1079 void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac);
1080 void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask);
1081 enum hal_bool ath9k_hw_setbssidmask(struct ath_hal *ah,
1082 const u_int8_t *mask);
1083 enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
1084 enum hal_power_mode mode);
1085 enum hal_int ath9k_hw_intrget(struct ath_hal *ah);
1086 u_int64_t ath9k_hw_gettsf64(struct ath_hal *ah);
1087 u_int ath9k_hw_getdefantenna(struct ath_hal *ah);
1088 enum hal_bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us);
1089 enum hal_bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
1090 enum hal_ant_setting settings,
1091 struct hal_channel *chan,
1092 u_int8_t *tx_chainmask,
1093 u_int8_t *rx_chainmask,
1094 u_int8_t *antenna_cfgd);
1095 void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna);
1096 enum hal_status ath9k_hw_select_antconfig(struct ath_hal *ah,
1097 u_int32_t cfg);
1098 enum hal_bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
1099 u_int32_t txdp);
1100 enum hal_bool ath9k_hw_txstart(struct ath_hal *ah, u_int q);
1101 u_int16_t ath9k_hw_computetxtime(struct ath_hal *ah,
1102 const struct hal_rate_table *rates,
1103 u_int32_t frameLen, u_int16_t rateix,
1104 enum hal_bool shortPreamble);
1105 void ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
1106 struct ath_desc *lastds,
1107 u_int durUpdateEn, u_int rtsctsRate,
1108 u_int rtsctsDuration,
1109 struct hal_11n_rate_series series[],
1110 u_int nseries, u_int flags);
1111 void ath9k_hw_set11n_burstduration(struct ath_hal *ah,
1112 struct ath_desc *ds,
1113 u_int burstDuration);
1114 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds);
1115 u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n);
1116 enum hal_bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q);
1117 u_int ath9k_regd_get_ctl(struct ath_hal *ah, struct hal_channel *chan);
1118 u_int ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
1119 struct hal_channel *chan);
1120 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags);
1121 enum hal_bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
1122 struct hal_txq_info *qInfo);
1123 enum hal_bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
1124 const struct hal_txq_info *qInfo);
1125 struct hal_channel_internal *ath9k_regd_check_channel(struct ath_hal *ah,
1126 const struct hal_channel *c);
1127 void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
1128 u_int pktLen, enum hal_pkt_type type,
1129 u_int txPower, u_int keyIx,
1130 enum hal_key_type keyType, u_int flags);
1131 enum hal_bool ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
1132 u_int segLen, enum hal_bool firstSeg,
1133 enum hal_bool lastSeg,
1134 const struct ath_desc *ds0);
1135 u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1136 u_int32_t *rxc_pcnt,
1137 u_int32_t *rxf_pcnt,
1138 u_int32_t *txf_pcnt);
1139 void ath9k_hw_dmaRegDump(struct ath_hal *ah);
1140 void ath9k_hw_beaconinit(struct ath_hal *ah,
1141 u_int32_t next_beacon, u_int32_t beacon_period);
1142 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
1143 const struct hal_beacon_state *bs);
1144 enum hal_bool ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
1145 u_int32_t size, u_int flags);
1146 void ath9k_hw_putrxbuf(struct ath_hal *ah, u_int32_t rxdp);
1147 void ath9k_hw_rxena(struct ath_hal *ah);
1148 void ath9k_hw_setopmode(struct ath_hal *ah);
1149 enum hal_bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac);
1150 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
1151 u_int32_t filter1);
1152 u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah);
1153 void ath9k_hw_startpcureceive(struct ath_hal *ah);
1154 void ath9k_hw_stoppcurecv(struct ath_hal *ah);
1155 enum hal_bool ath9k_hw_stopdmarecv(struct ath_hal *ah);
1156 enum hal_status ath9k_hw_rxprocdesc(struct ath_hal *ah,
1157 struct ath_desc *ds, u_int32_t pa,
1158 struct ath_desc *nds, u_int64_t tsf);
1159 u_int32_t ath9k_hw_gettxbuf(struct ath_hal *ah, u_int q);
1160 enum hal_status ath9k_hw_txprocdesc(struct ath_hal *ah,
1161 struct ath_desc *ds);
1162 void ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
1163 u_int numDelims);
1164 void ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
1165 u_int aggrLen);
1166 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds);
1167 enum hal_bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q);
1168 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs);
1169 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds);
1170 void ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah,
1171 struct ath_desc *ds, u_int vmf);
1172 enum hal_bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u_int32_t limit);
1173 enum hal_bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
1174 int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
1175 const struct hal_txq_info *qInfo);
1176 u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q);
1177 const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid);
1178 enum hal_bool ath9k_hw_disable(struct ath_hal *ah);
1179 void ath9k_hw_rfdetach(struct ath_hal *ah);
1180 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
1181 struct hal_channel_internal *chan,
1182 struct chan_centers *centers);
1183 enum hal_bool ath9k_get_channel_edges(struct ath_hal *ah,
1184 u_int16_t flags, u_int16_t *low,
1185 u_int16_t *high);
1186 enum hal_bool ath9k_hw_get_chip_power_limits(struct ath_hal *ah,
1187 struct hal_channel *chans,
1188 u_int32_t nchans);
1189 #endif
OpenWrt Source Repository