package/bcm43xx-mac80211/src/bcm43xx/bcm43xx.h

   1 #ifndef BCM43xx_H_
   2 #define BCM43xx_H_
   3
   4 #include <linux/hw_random.h>
   5 #include <linux/kernel.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/interrupt.h>
   8 #include <linux/stringify.h>
   9 #include <linux/netdevice.h>
  10 #include <linux/pci.h>
  11 #include <asm/atomic.h>
  12 #include <asm/io.h>
  13
  14 #include <linux/ssb/ssb.h>
  15 #include <linux/ssb/ssb_driver_chipcommon.h>
  16
  17 #include <linux/wireless.h>
  18 #include <net/mac80211.h>
  19
  20 #include "bcm43xx_debugfs.h"
  21 #include "bcm43xx_leds.h"
  22 #include "bcm43xx_lo.h"
  23 #include "bcm43xx_phy.h"
  24
  25
  26 #define PFX                             KBUILD_MODNAME ": "
  27
  28 #define BCM43xx_IRQWAIT_MAX_RETRIES     50
  29
  30 #define BCM43xx_IO_SIZE                 8192
  31
  32 #define BCM43xx_RX_MAX_SSI              60
  33
  34 /* MMIO offsets */
  35 #define BCM43xx_MMIO_DMA0_REASON        0x20
  36 #define BCM43xx_MMIO_DMA0_IRQ_MASK      0x24
  37 #define BCM43xx_MMIO_DMA1_REASON        0x28
  38 #define BCM43xx_MMIO_DMA1_IRQ_MASK      0x2C
  39 #define BCM43xx_MMIO_DMA2_REASON        0x30
  40 #define BCM43xx_MMIO_DMA2_IRQ_MASK      0x34
  41 #define BCM43xx_MMIO_DMA3_REASON        0x38
  42 #define BCM43xx_MMIO_DMA3_IRQ_MASK      0x3C
  43 #define BCM43xx_MMIO_DMA4_REASON        0x40
  44 #define BCM43xx_MMIO_DMA4_IRQ_MASK      0x44
  45 #define BCM43xx_MMIO_DMA5_REASON        0x48
  46 #define BCM43xx_MMIO_DMA5_IRQ_MASK      0x4C
  47 #define BCM43xx_MMIO_MACCTL             0x120
  48 #define BCM43xx_MMIO_STATUS_BITFIELD    0x120//TODO replace all instances by MACCTL
  49 #define BCM43xx_MMIO_STATUS2_BITFIELD   0x124
  50 #define BCM43xx_MMIO_GEN_IRQ_REASON     0x128
  51 #define BCM43xx_MMIO_GEN_IRQ_MASK       0x12C
  52 #define BCM43xx_MMIO_RAM_CONTROL        0x130
  53 #define BCM43xx_MMIO_RAM_DATA           0x134
  54 #define BCM43xx_MMIO_PS_STATUS          0x140
  55 #define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158
  56 #define BCM43xx_MMIO_SHM_CONTROL        0x160
  57 #define BCM43xx_MMIO_SHM_DATA           0x164
  58 #define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166
  59 #define BCM43xx_MMIO_XMITSTAT_0         0x170
  60 #define BCM43xx_MMIO_XMITSTAT_1         0x174
  61 #define BCM43xx_MMIO_REV3PLUS_TSF_LOW   0x180 /* core rev >= 3 only */
  62 #define BCM43xx_MMIO_REV3PLUS_TSF_HIGH  0x184 /* core rev >= 3 only */
  63
  64 /* 32-bit DMA */
  65 #define BCM43xx_MMIO_DMA32_BASE0        0x200
  66 #define BCM43xx_MMIO_DMA32_BASE1        0x220
  67 #define BCM43xx_MMIO_DMA32_BASE2        0x240
  68 #define BCM43xx_MMIO_DMA32_BASE3        0x260
  69 #define BCM43xx_MMIO_DMA32_BASE4        0x280
  70 #define BCM43xx_MMIO_DMA32_BASE5        0x2A0
  71 /* 64-bit DMA */
  72 #define BCM43xx_MMIO_DMA64_BASE0        0x200
  73 #define BCM43xx_MMIO_DMA64_BASE1        0x240
  74 #define BCM43xx_MMIO_DMA64_BASE2        0x280
  75 #define BCM43xx_MMIO_DMA64_BASE3        0x2C0
  76 #define BCM43xx_MMIO_DMA64_BASE4        0x300
  77 #define BCM43xx_MMIO_DMA64_BASE5        0x340
  78 /* PIO */
  79 #define BCM43xx_MMIO_PIO1_BASE          0x300
  80 #define BCM43xx_MMIO_PIO2_BASE          0x310
  81 #define BCM43xx_MMIO_PIO3_BASE          0x320
  82 #define BCM43xx_MMIO_PIO4_BASE          0x330
  83
  84 #define BCM43xx_MMIO_PHY_VER            0x3E0
  85 #define BCM43xx_MMIO_PHY_RADIO          0x3E2
  86 #define BCM43xx_MMIO_PHY0               0x3E6
  87 #define BCM43xx_MMIO_ANTENNA            0x3E8
  88 #define BCM43xx_MMIO_CHANNEL            0x3F0
  89 #define BCM43xx_MMIO_CHANNEL_EXT        0x3F4
  90 #define BCM43xx_MMIO_RADIO_CONTROL      0x3F6
  91 #define BCM43xx_MMIO_RADIO_DATA_HIGH    0x3F8
  92 #define BCM43xx_MMIO_RADIO_DATA_LOW     0x3FA
  93 #define BCM43xx_MMIO_PHY_CONTROL        0x3FC
  94 #define BCM43xx_MMIO_PHY_DATA           0x3FE
  95 #define BCM43xx_MMIO_MACFILTER_CONTROL  0x420
  96 #define BCM43xx_MMIO_MACFILTER_DATA     0x422
  97 #define BCM43xx_MMIO_RCMTA_COUNT        0x43C
  98 #define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A
  99 #define BCM43xx_MMIO_GPIO_CONTROL       0x49C
 100 #define BCM43xx_MMIO_GPIO_MASK          0x49E
 101 #define BCM43xx_MMIO_TSF_0              0x632 /* core rev < 3 only */
 102 #define BCM43xx_MMIO_TSF_1              0x634 /* core rev < 3 only */
 103 #define BCM43xx_MMIO_TSF_2              0x636 /* core rev < 3 only */
 104 #define BCM43xx_MMIO_TSF_3              0x638 /* core rev < 3 only */
 105 #define BCM43xx_MMIO_RNG                0x65A
 106 #define BCM43xx_MMIO_POWERUP_DELAY      0x6A8
 107
 108 /* SPROM boardflags_lo values */
 109 #define BCM43xx_BFL_BTCOEXIST           0x0001 /* implements Bluetooth coexistance */
 110 #define BCM43xx_BFL_PACTRL              0x0002 /* GPIO 9 controlling the PA */
 111 #define BCM43xx_BFL_AIRLINEMODE         0x0004 /* implements GPIO 13 radio disable indication */
 112 #define BCM43xx_BFL_RSSI                0x0008 /* software calculates nrssi slope. */
 113 #define BCM43xx_BFL_ENETSPI             0x0010 /* has ephy roboswitch spi */
 114 #define BCM43xx_BFL_XTAL_NOSLOW         0x0020 /* no slow clock available */
 115 #define BCM43xx_BFL_CCKHIPWR            0x0040 /* can do high power CCK transmission */
 116 #define BCM43xx_BFL_ENETADM             0x0080 /* has ADMtek switch */
 117 #define BCM43xx_BFL_ENETVLAN            0x0100 /* can do vlan */
 118 #define BCM43xx_BFL_AFTERBURNER         0x0200 /* supports Afterburner mode */
 119 #define BCM43xx_BFL_NOPCI               0x0400 /* leaves PCI floating */
 120 #define BCM43xx_BFL_FEM                 0x0800 /* supports the Front End Module */
 121 #define BCM43xx_BFL_EXTLNA              0x1000 /* has an external LNA */
 122 #define BCM43xx_BFL_HGPA                0x2000 /* had high gain PA */
 123 #define BCM43xx_BFL_BTCMOD              0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
 124 #define BCM43xx_BFL_ALTIQ               0x8000 /* alternate I/Q settings */
 125
 126 /* GPIO register offset, in both ChipCommon and PCI core. */
 127 #define BCM43xx_GPIO_CONTROL            0x6c
 128
 129 /* SHM Routing */
 130 enum {
 131         BCM43xx_SHM_UCODE,      /* Microcode memory */
 132         BCM43xx_SHM_SHARED,     /* Shared memory */
 133         BCM43xx_SHM_SCRATCH,    /* Scratch memory */
 134         BCM43xx_SHM_HW,         /* Internal hardware register */
 135         BCM43xx_SHM_RCMTA,      /* Receive match transmitter address (rev >= 5 only) */
 136 };
 137 /* SHM Routing modifiers */
 138 #define BCM43xx_SHM_AUTOINC_R           0x0200 /* Auto-increment address on read */
 139 #define BCM43xx_SHM_AUTOINC_W           0x0100 /* Auto-increment address on write */
 140 #define BCM43xx_SHM_AUTOINC_RW          (BCM43xx_SHM_AUTOINC_R | \
 141                                          BCM43xx_SHM_AUTOINC_W)
 142
 143 /* Misc SHM_SHARED offsets */
 144 #define BCM43xx_SHM_SH_WLCOREREV        0x0016 /* 802.11 core revision */
 145 #define BCM43xx_SHM_SH_PCTLWDPOS        0x0008
 146 #define BCM43xx_SHM_SH_RXPADOFF         0x0034 /* RX Padding data offset (PIO only) */
 147 #define BCM43xx_SHM_SH_PHYVER           0x0050 /* PHY version */
 148 #define BCM43xx_SHM_SH_PHYTYPE          0x0052 /* PHY type */
 149 #define BCM43xx_SHM_SH_ANTSWAP          0x005C /* Antenna swap threshold */
 150 #define BCM43xx_SHM_SH_HOSTFLO          0x005E /* Hostflags for ucode options (low) */
 151 #define BCM43xx_SHM_SH_HOSTFHI          0x0060 /* Hostflags for ucode options (high) */
 152 #define BCM43xx_SHM_SH_RFATT            0x0064 /* Current radio attenuation value */
 153 #define BCM43xx_SHM_SH_RADAR            0x0066 /* Radar register */
 154 #define BCM43xx_SHM_SH_PHYTXNOI         0x006E /* PHY noise directly after TX (lower 8bit only) */
 155 #define BCM43xx_SHM_SH_RFRXSP1          0x0072 /* RF RX SP Register 1 */
 156 #define BCM43xx_SHM_SH_CHAN             0x00A0 /* Current channel (low 8bit only) */
 157 #define  BCM43xx_SHM_SH_CHAN_5GHZ       0x0100 /* Bit set, if 5Ghz channel */
 158 #define BCM43xx_SHM_SH_BCMCFIFOID       0x0108 /* Last posted cookie to the bcast/mcast FIFO */
 159 /* SHM_SHARED TX FIFO variables */
 160 #define BCM43xx_SHM_SH_SIZE01           0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
 161 #define BCM43xx_SHM_SH_SIZE23           0x009A /* TX FIFO size for FIFO 2 and 3 */
 162 #define BCM43xx_SHM_SH_SIZE45           0x009C /* TX FIFO size for FIFO 4 and 5 */
 163 #define BCM43xx_SHM_SH_SIZE67           0x009E /* TX FIFO size for FIFO 6 and 7 */
 164 /* SHM_SHARED background noise */
 165 #define BCM43xx_SHM_SH_JSSI0            0x0088 /* Measure JSSI 0 */
 166 #define BCM43xx_SHM_SH_JSSI1            0x008A /* Measure JSSI 1 */
 167 #define BCM43xx_SHM_SH_JSSIAUX          0x008C /* Measure JSSI AUX */
 168 /* SHM_SHARED crypto engine */
 169 #define BCM43xx_SHM_SH_DEFAULTIV        0x003C /* Default IV location */
 170 #define BCM43xx_SHM_SH_NRRXTRANS        0x003E /* # of soft RX transmitter addresses (max 8) */
 171 #define BCM43xx_SHM_SH_KTP              0x0056 /* Key table pointer */
 172 #define BCM43xx_SHM_SH_TKIPTSCTTAK      0x0318
 173 #define BCM43xx_SHM_SH_KEYIDXBLOCK      0x05D4 /* Key index/algorithm block (v4 firmware) */
 174 #define BCM43xx_SHM_SH_PSM              0x05F4 /* PSM transmitter address match block (rev < 5) */
 175 /* SHM_SHARED WME variables */
 176 #define BCM43xx_SHM_SH_EDCFSTAT         0x000E /* EDCF status */
 177 #define BCM43xx_SHM_SH_TXFCUR           0x0030 /* TXF current index */
 178 #define BCM43xx_SHM_SH_EDCFQ            0x0240 /* EDCF Q info */
 179 /* SHM_SHARED powersave mode related */
 180 #define BCM43xx_SHM_SH_SLOTT            0x0010 /* Slot time */
 181 #define BCM43xx_SHM_SH_DTIMPER          0x0012 /* DTIM period */
 182 #define BCM43xx_SHM_SH_NOSLPZNATDTIM    0x004C /* NOSLPZNAT DTIM */
 183 /* SHM_SHARED beacon variables */
 184 #define BCM43xx_SHM_SH_BTL0             0x0018 /* Beacon template length 0 */
 185 #define BCM43xx_SHM_SH_BTL1             0x001A /* Beacon template length 1 */
 186 #define BCM43xx_SHM_SH_BTSFOFF          0x001C /* Beacon TSF offset */
 187 #define BCM43xx_SHM_SH_TIMBPOS          0x001E /* TIM B position in beacon */
 188 #define BCM43xx_SHM_SH_SFFBLIM          0x0044 /* Short frame fallback retry limit */
 189 #define BCM43xx_SHM_SH_LFFBLIM          0x0046 /* Long frame fallback retry limit */
 190 #define BCM43xx_SHM_SH_BEACPHYCTL       0x0054 /* Beacon PHY TX control word (see PHY TX control) */
 191 /* SHM_SHARED ACK/CTS control */
 192 #define BCM43xx_SHM_SH_ACKCTSPHYCTL     0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
 193 /* SHM_SHARED probe response variables */
 194 #define BCM43xx_SHM_SH_PRSSID           0x0160 /* Probe Response SSID */
 195 #define BCM43xx_SHM_SH_PRSSIDLEN        0x0048 /* Probe Response SSID length */
 196 #define BCM43xx_SHM_SH_PRTLEN           0x004A /* Probe Response template length */
 197 #define BCM43xx_SHM_SH_PRMAXTIME        0x0074 /* Probe Response max time */
 198 #define BCM43xx_SHM_SH_PRPHYCTL         0x0188 /* Probe Response PHY TX control word */
 199 /* SHM_SHARED rate tables */
 200 #define BCM43xx_SHM_SH_OFDMDIRECT       0x01C0 /* Pointer to OFDM direct map */
 201 #define BCM43xx_SHM_SH_OFDMBASIC        0x01E0 /* Pointer to OFDM basic rate map */
 202 #define BCM43xx_SHM_SH_CCKDIRECT        0x0200 /* Pointer to CCK direct map */
 203 #define BCM43xx_SHM_SH_CCKBASIC         0x0220 /* Pointer to CCK basic rate map */
 204 /* SHM_SHARED microcode soft registers */
 205 #define BCM43xx_SHM_SH_UCODEREV         0x0000 /* Microcode revision */
 206 #define BCM43xx_SHM_SH_UCODEPATCH       0x0002 /* Microcode patchlevel */
 207 #define BCM43xx_SHM_SH_UCODEDATE        0x0004 /* Microcode date */
 208 #define BCM43xx_SHM_SH_UCODETIME        0x0006 /* Microcode time */
 209 #define BCM43xx_SHM_SH_UCODESTAT        0x0040 /* Microcode debug status code */
 210 #define  BCM43xx_SHM_SH_UCODESTAT_INVALID       0
 211 #define  BCM43xx_SHM_SH_UCODESTAT_INIT          1
 212 #define  BCM43xx_SHM_SH_UCODESTAT_ACTIVE        2
 213 #define  BCM43xx_SHM_SH_UCODESTAT_SUSP          3 /* suspended */
 214 #define  BCM43xx_SHM_SH_UCODESTAT_SLEEP         4 /* asleep (PS) */
 215 #define BCM43xx_SHM_SH_MAXBFRAMES       0x0080 /* Maximum number of frames in a burst */
 216 #define BCM43xx_SHM_SH_SPUWKUP          0x0094 /* pre-wakeup for synth PU in us */
 217 #define BCM43xx_SHM_SH_PRETBTT          0x0096 /* pre-TBTT in us */
 218
 219 /* SHM_SCRATCH offsets */
 220 #define BCM43xx_SHM_SC_MINCONT          0x0003 /* Minimum contention window */
 221 #define BCM43xx_SHM_SC_MAXCONT          0x0004 /* Maximum contention window */
 222 #define BCM43xx_SHM_SC_CURCONT          0x0005 /* Current contention window */
 223 #define BCM43xx_SHM_SC_SRLIMIT          0x0006 /* Short retry count limit */
 224 #define BCM43xx_SHM_SC_LRLIMIT          0x0007 /* Long retry count limit */
 225 #define BCM43xx_SHM_SC_DTIMC            0x0008 /* Current DTIM count */
 226 #define BCM43xx_SHM_SC_BTL0LEN          0x0015 /* Beacon 0 template length */
 227 #define BCM43xx_SHM_SC_BTL1LEN          0x0016 /* Beacon 1 template length */
 228 #define BCM43xx_SHM_SC_SCFB             0x0017 /* Short frame transmit count threshold for rate fallback */
 229 #define BCM43xx_SHM_SC_LCFB             0x0018 /* Long frame transmit count threshold for rate fallback */
 230
 231
 232 /* Hardware Radio Enable masks */
 233 #define BCM43xx_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
 234 #define BCM43xx_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
 235
 236 /* HostFlags. See bcm43xx_hf_read/write() */
 237 #define BCM43xx_HF_ANTDIVHELP           0x00000001 /* ucode antenna div helper */
 238 #define BCM43xx_HF_SYMW                 0x00000002 /* G-PHY SYM workaround */
 239 #define BCM43xx_HF_RXPULLW              0x00000004 /* RX pullup workaround */
 240 #define BCM43xx_HF_CCKBOOST             0x00000008 /* 4dB CCK power boost (exclusive with OFDM boost) */
 241 #define BCM43xx_HF_BTCOEX               0x00000010 /* Bluetooth coexistance */
 242 #define BCM43xx_HF_GDCW                 0x00000020 /* G-PHY DV canceller filter bw workaround */
 243 #define BCM43xx_HF_OFDMPABOOST          0x00000040 /* Enable PA gain boost for OFDM */
 244 #define BCM43xx_HF_ACPR                 0x00000080 /* Disable for Japan, channel 14 */
 245 #define BCM43xx_HF_EDCF                 0x00000100 /* on if WME and MAC suspended */
 246 #define BCM43xx_HF_TSSIRPSMW            0x00000200 /* TSSI reset PSM ucode workaround */
 247 #define BCM43xx_HF_DSCRQ                0x00000400 /* Disable slow clock request in ucode */
 248 #define BCM43xx_HF_ACIW                 0x00000800 /* ACI workaround: shift bits by 2 on PHY CRS */
 249 #define BCM43xx_HF_2060W                0x00001000 /* 2060 radio workaround */
 250 #define BCM43xx_HF_RADARW               0x00002000 /* Radar workaround */
 251 #define BCM43xx_HF_USEDEFKEYS           0x00004000 /* Enable use of default keys */
 252 #define BCM43xx_HF_BT4PRIOCOEX          0x00010000 /* Bluetooth 2-priority coexistance */
 253 #define BCM43xx_HF_FWKUP                0x00020000 /* Fast wake-up ucode */
 254 #define BCM43xx_HF_VCORECALC            0x00040000 /* Force VCO recalculation when powering up synthpu */
 255 #define BCM43xx_HF_PCISCW               0x00080000 /* PCI slow clock workaround */
 256 #define BCM43xx_HF_4318TSSI             0x00200000 /* 4318 TSSI */
 257 #define BCM43xx_HF_FBCMCFIFO            0x00400000 /* Flush bcast/mcast FIFO immediately */
 258 #define BCM43xx_HF_HWPCTL               0x00800000 /* Enable hardwarre power control */
 259 #define BCM43xx_HF_BTCOEXALT            0x01000000 /* Bluetooth coexistance in alternate pins */
 260 #define BCM43xx_HF_TXBTCHECK            0x02000000 /* Bluetooth check during transmission */
 261 #define BCM43xx_HF_SKCFPUP              0x04000000 /* Skip CFP update */
 262
 263
 264 /* MacFilter offsets. */
 265 #define BCM43xx_MACFILTER_SELF          0x0000
 266 #define BCM43xx_MACFILTER_BSSID         0x0003
 267
 268 /* PowerControl */
 269 #define BCM43xx_PCTL_IN                 0xB0
 270 #define BCM43xx_PCTL_OUT                0xB4
 271 #define BCM43xx_PCTL_OUTENABLE          0xB8
 272 #define BCM43xx_PCTL_XTAL_POWERUP       0x40
 273 #define BCM43xx_PCTL_PLL_POWERDOWN      0x80
 274
 275 /* PowerControl Clock Modes */
 276 #define BCM43xx_PCTL_CLK_FAST           0x00
 277 #define BCM43xx_PCTL_CLK_SLOW           0x01
 278 #define BCM43xx_PCTL_CLK_DYNAMIC        0x02
 279
 280 #define BCM43xx_PCTL_FORCE_SLOW         0x0800
 281 #define BCM43xx_PCTL_FORCE_PLL          0x1000
 282 #define BCM43xx_PCTL_DYN_XTAL           0x2000
 283
 284 /* PHYVersioning */
 285 #define BCM43xx_PHYTYPE_A               0x00
 286 #define BCM43xx_PHYTYPE_B               0x01
 287 #define BCM43xx_PHYTYPE_G               0x02
 288
 289 /* PHYRegisters */
 290 #define BCM43xx_PHY_ILT_A_CTRL          0x0072
 291 #define BCM43xx_PHY_ILT_A_DATA1         0x0073
 292 #define BCM43xx_PHY_ILT_A_DATA2         0x0074
 293 #define BCM43xx_PHY_G_LO_CONTROL        0x0810
 294 #define BCM43xx_PHY_ILT_G_CTRL          0x0472
 295 #define BCM43xx_PHY_ILT_G_DATA1         0x0473
 296 #define BCM43xx_PHY_ILT_G_DATA2         0x0474
 297 #define BCM43xx_PHY_A_PCTL              0x007B
 298 #define BCM43xx_PHY_G_PCTL              0x0029
 299 #define BCM43xx_PHY_A_CRS               0x0029
 300 #define BCM43xx_PHY_RADIO_BITFIELD      0x0401
 301 #define BCM43xx_PHY_G_CRS               0x0429
 302 #define BCM43xx_PHY_NRSSILT_CTRL        0x0803
 303 #define BCM43xx_PHY_NRSSILT_DATA        0x0804
 304
 305 /* RadioRegisters */
 306 #define BCM43xx_RADIOCTL_ID             0x01
 307
 308 /* MAC Control bitfield */
 309 #define BCM43xx_MACCTL_ENABLED          0x00000001 /* MAC Enabled */
 310 #define BCM43xx_MACCTL_PSM_RUN          0x00000002 /* Run Microcode */
 311 #define BCM43xx_MACCTL_PSM_JMP0         0x00000004 /* Microcode jump to 0 */
 312 #define BCM43xx_MACCTL_SHM_ENABLED      0x00000100 /* SHM Enabled */
 313 #define BCM43xx_MACCTL_SHM_UPPER        0x00000200 /* SHM Upper */
 314 #define BCM43xx_MACCTL_IHR_ENABLED      0x00000400 /* IHR Region Enabled */
 315 #define BCM43xx_MACCTL_PSM_DBG          0x00002000 /* Microcode debugging enabled */
 316 #define BCM43xx_MACCTL_GPOUTSMSK        0x0000C000 /* GPOUT Select Mask */
 317 #define BCM43xx_MACCTL_BE               0x00010000 /* Big Endian mode */
 318 #define BCM43xx_MACCTL_INFRA            0x00020000 /* Infrastructure mode */
 319 #define BCM43xx_MACCTL_AP               0x00040000 /* AccessPoint mode */
 320 #define BCM43xx_MACCTL_RADIOLOCK        0x00080000 /* Radio lock */
 321 #define BCM43xx_MACCTL_BEACPROMISC      0x00100000 /* Beacon Promiscuous */
 322 #define BCM43xx_MACCTL_KEEP_BADPLCP     0x00200000 /* Keep frames with bad PLCP */
 323 #define BCM43xx_MACCTL_KEEP_CTL         0x00400000 /* Keep control frames */
 324 #define BCM43xx_MACCTL_KEEP_BAD         0x00800000 /* Keep bad frames (FCS) */
 325 #define BCM43xx_MACCTL_PROMISC          0x01000000 /* Promiscuous mode */
 326 #define BCM43xx_MACCTL_HWPS             0x02000000 /* Hardware Power Saving */
 327 #define BCM43xx_MACCTL_AWAKE            0x04000000 /* Device is awake */
 328 #define BCM43xx_MACCTL_CLOSEDNET        0x08000000 /* Closed net (no SSID bcast) */
 329 #define BCM43xx_MACCTL_TBTTHOLD         0x10000000 /* TBTT Hold */
 330 #define BCM43xx_MACCTL_DISCTXSTAT       0x20000000 /* Discard TX status */
 331 #define BCM43xx_MACCTL_DISCPMQ          0x40000000 /* Discard Power Management Queue */
 332 #define BCM43xx_MACCTL_GMODE            0x80000000 /* G Mode */
 333
 334 /* StatusBitField *///FIXME rename these all
 335 #define BCM43xx_SBF_MAC_ENABLED         0x00000001
 336 #define BCM43xx_SBF_2                   0x00000002 /*FIXME: fix name*/
 337 #define BCM43xx_SBF_CORE_READY          0x00000004
 338 #define BCM43xx_SBF_400                 0x00000400 /*FIXME: fix name*/
 339 #define BCM43xx_SBF_4000                0x00004000 /*FIXME: fix name*/
 340 #define BCM43xx_SBF_8000                0x00008000 /*FIXME: fix name*/
 341 #define BCM43xx_SBF_XFER_REG_BYTESWAP   0x00010000
 342 #define BCM43xx_SBF_MODE_NOTADHOC       0x00020000
 343 #define BCM43xx_SBF_MODE_AP             0x00040000
 344 #define BCM43xx_SBF_RADIOREG_LOCK       0x00080000
 345 #define BCM43xx_SBF_MODE_MONITOR        0x00400000
 346 #define BCM43xx_SBF_MODE_PROMISC        0x01000000
 347 #define BCM43xx_SBF_PS1                 0x02000000
 348 #define BCM43xx_SBF_PS2                 0x04000000
 349 #define BCM43xx_SBF_NO_SSID_BCAST       0x08000000
 350 #define BCM43xx_SBF_TIME_UPDATE         0x10000000
 351 #define BCM43xx_SBF_80000000            0x80000000 /*FIXME: fix name*/
 352
 353 /* 802.11 core specific TM State Low flags */
 354 #define BCM43xx_TMSLOW_GMODE            0x20000000 /* G Mode Enable */
 355 #define BCM43xx_TMSLOW_PLLREFSEL        0x00200000 /* PLL Frequency Reference Select */
 356 #define BCM43xx_TMSLOW_MACPHYCLKEN      0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
 357 #define BCM43xx_TMSLOW_PHYRESET         0x00080000 /* PHY Reset */
 358 #define BCM43xx_TMSLOW_PHYCLKEN         0x00040000 /* PHY Clock Enable */
 359
 360 /* 802.11 core specific TM State High flags */
 361 #define BCM43xx_TMSHIGH_FCLOCK          0x00040000 /* Fast Clock Available (rev >= 5)*/
 362 #define BCM43xx_TMSHIGH_APHY            0x00020000 /* A-PHY available (rev >= 5) */
 363 #define BCM43xx_TMSHIGH_GPHY            0x00010000 /* G-PHY available (rev >= 5) */
 364
 365 /* Generic-Interrupt reasons. */
 366 #define BCM43xx_IRQ_MAC_SUSPENDED       0x00000001
 367 #define BCM43xx_IRQ_BEACON              0x00000002
 368 #define BCM43xx_IRQ_TBTT_INDI           0x00000004
 369 #define BCM43xx_IRQ_BEACON_TX_OK        0x00000008
 370 #define BCM43xx_IRQ_BEACON_CANCEL       0x00000010
 371 #define BCM43xx_IRQ_ATIM_END            0x00000020
 372 #define BCM43xx_IRQ_PMQ                 0x00000040
 373 #define BCM43xx_IRQ_PIO_WORKAROUND      0x00000100
 374 #define BCM43xx_IRQ_MAC_TXERR           0x00000200
 375 #define BCM43xx_IRQ_PHY_TXERR           0x00000800
 376 #define BCM43xx_IRQ_PMEVENT             0x00001000
 377 #define BCM43xx_IRQ_TIMER0              0x00002000
 378 #define BCM43xx_IRQ_TIMER1              0x00004000
 379 #define BCM43xx_IRQ_DMA                 0x00008000
 380 #define BCM43xx_IRQ_TXFIFO_FLUSH_OK     0x00010000
 381 #define BCM43xx_IRQ_CCA_MEASURE_OK      0x00020000
 382 #define BCM43xx_IRQ_NOISESAMPLE_OK      0x00040000
 383 #define BCM43xx_IRQ_UCODE_DEBUG         0x08000000
 384 #define BCM43xx_IRQ_RFKILL              0x10000000
 385 #define BCM43xx_IRQ_TX_OK               0x20000000
 386 #define BCM43xx_IRQ_PHY_G_CHANGED       0x40000000
 387 #define BCM43xx_IRQ_TIMEOUT             0x80000000
 388
 389 #define BCM43xx_IRQ_ALL                 0xFFFFFFFF
 390 #define BCM43xx_IRQ_MASKTEMPLATE        (BCM43xx_IRQ_MAC_SUSPENDED |    \
 391                                          BCM43xx_IRQ_BEACON |           \
 392                                          BCM43xx_IRQ_TBTT_INDI |        \
 393                                          BCM43xx_IRQ_ATIM_END |         \
 394                                          BCM43xx_IRQ_PMQ |              \
 395                                          BCM43xx_IRQ_MAC_TXERR |        \
 396                                          BCM43xx_IRQ_PHY_TXERR |        \
 397                                          BCM43xx_IRQ_DMA |              \
 398                                          BCM43xx_IRQ_TXFIFO_FLUSH_OK |  \
 399                                          BCM43xx_IRQ_NOISESAMPLE_OK |   \
 400                                          BCM43xx_IRQ_UCODE_DEBUG |      \
 401                                          BCM43xx_IRQ_RFKILL |           \
 402                                          BCM43xx_IRQ_TX_OK)
 403
 404 /* Device specific rate values.
 405  * The actual values defined here are (rate_in_mbps * 2).
 406  * Some code depends on this. Don't change it. */
 407 #define BCM43xx_CCK_RATE_1MB            0x02
 408 #define BCM43xx_CCK_RATE_2MB            0x04
 409 #define BCM43xx_CCK_RATE_5MB            0x0B
 410 #define BCM43xx_CCK_RATE_11MB           0x16
 411 #define BCM43xx_OFDM_RATE_6MB           0x0C
 412 #define BCM43xx_OFDM_RATE_9MB           0x12
 413 #define BCM43xx_OFDM_RATE_12MB          0x18
 414 #define BCM43xx_OFDM_RATE_18MB          0x24
 415 #define BCM43xx_OFDM_RATE_24MB          0x30
 416 #define BCM43xx_OFDM_RATE_36MB          0x48
 417 #define BCM43xx_OFDM_RATE_48MB          0x60
 418 #define BCM43xx_OFDM_RATE_54MB          0x6C
 419 /* Convert a bcm43xx rate value to a rate in 100kbps */
 420 #define BCM43xx_RATE_TO_BASE100KBPS(rate)       (((rate) * 10) / 2)
 421
 422
 423 #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT       7
 424 #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT        4
 425
 426 /* Max size of a security key */
 427 #define BCM43xx_SEC_KEYSIZE                     16
 428 /* Security algorithms. */
 429 enum {
 430         BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
 431         BCM43xx_SEC_ALGO_WEP40,
 432         BCM43xx_SEC_ALGO_TKIP,
 433         BCM43xx_SEC_ALGO_AES,
 434         BCM43xx_SEC_ALGO_WEP104,
 435         BCM43xx_SEC_ALGO_AES_LEGACY,
 436 };
 437
 438
 439 #ifdef assert
 440 # undef assert
 441 #endif
 442 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
 443 # define assert(expr) \
 444         do {                                                                    \
 445                 if (unlikely(!(expr))) {                                        \
 446                 printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n",   \
 447                         #expr, __FILE__, __LINE__, __FUNCTION__);               \
 448                 }                                                               \
 449         } while (0)
 450 # define BCM43xx_DEBUG  1
 451 #else
 452 # define assert(expr)   do { /* nothing */ } while (0)
 453 # define BCM43xx_DEBUG  0
 454 #endif
 455
 456 /* rate limited printk(). */
 457 #ifdef printkl
 458 # undef printkl
 459 #endif
 460 #define printkl(f, x...)  do { if (printk_ratelimit()) printk(f ,##x); } while (0)
 461 /* rate limited printk() for debugging */
 462 #ifdef dprintkl
 463 # undef dprintkl
 464 #endif
 465 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
 466 # define dprintkl               printkl
 467 #else
 468 # define dprintkl(f, x...)      do { /* nothing */ } while (0)
 469 #endif
 470
 471 /* debugging printk() */
 472 #ifdef dprintk
 473 # undef dprintk
 474 #endif
 475 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
 476 # define dprintk(f, x...)  do { printk(f ,##x); } while (0)
 477 #else
 478 # define dprintk(f, x...)  do { /* nothing */ } while (0)
 479 #endif
 480
 481
 482 struct net_device;
 483 struct pci_dev;
 484 struct bcm43xx_dmaring;
 485 struct bcm43xx_pioqueue;
 486
 487 struct bcm43xx_initval {
 488         u16 offset;
 489         u16 size;
 490         u32 value;
 491 } __attribute__((__packed__));
 492
 493 #define BCM43xx_PHYMODE(phytype)        (1 << (phytype))
 494 #define BCM43xx_PHYMODE_A               BCM43xx_PHYMODE(BCM43xx_PHYTYPE_A)
 495 #define BCM43xx_PHYMODE_B               BCM43xx_PHYMODE(BCM43xx_PHYTYPE_B)
 496 #define BCM43xx_PHYMODE_G               BCM43xx_PHYMODE(BCM43xx_PHYTYPE_G)
 497
 498 struct bcm43xx_phy {
 499         /* Possible PHYMODEs on this PHY */
 500         u8 possible_phymodes;
 501         /* GMODE bit enabled? */
 502         u8 gmode;
 503         /* Possible ieee80211 subsystem hwmodes for this PHY.
 504          * Which mode is selected, depends on thr GMODE enabled bit */
 505 #define BCM43xx_MAX_PHYHWMODES  2
 506         struct ieee80211_hw_mode hwmodes[BCM43xx_MAX_PHYHWMODES];
 507
 508         /* Analog Type */
 509         u8 analog;
 510         /* BCM43xx_PHYTYPE_ */
 511         u8 type;
 512         /* PHY revision number. */
 513         u8 rev;
 514
 515         /* Radio versioning */
 516         u16 radio_manuf;        /* Radio manufacturer */
 517         u16 radio_ver;          /* Radio version */
 518         u8 radio_rev;           /* Radio revision */
 519
 520         u8 radio_on:1;          /* Radio switched on/off */
 521         u8 locked:1;            /* Only used in bcm43xx_phy_{un}lock() */
 522         u8 dyn_tssi_tbl:1;      /* tssi2dbm is kmalloc()ed. */
 523
 524         /* ACI (adjacent channel interference) flags. */
 525         u8 aci_enable:1;
 526         u8 aci_wlan_automatic:1;
 527         u8 aci_hw_rssi:1;
 528
 529         u16 minlowsig[2];
 530         u16 minlowsigpos[2];
 531
 532         /* TSSI to dBm table in use */
 533         const s8 *tssi2dbm;
 534         /* Target idle TSSI */
 535         int tgt_idle_tssi;
 536         /* Current idle TSSI */
 537         int cur_idle_tssi;
 538
 539         /* LocalOscillator control values. */
 540         struct bcm43xx_txpower_lo_control *lo_control;
 541         /* Values from bcm43xx_calc_loopback_gain() */
 542         s16 max_lb_gain;        /* Maximum Loopback gain in hdB */
 543         s16 trsw_rx_gain;       /* TRSW RX gain in hdB */
 544         s16 lna_lod_gain;       /* LNA lod */
 545         s16 lna_gain;           /* LNA */
 546         s16 pga_gain;           /* PGA */
 547
 548         /* PHY lock for core.rev < 3
 549          * This lock is only used by bcm43xx_phy_{un}lock()
 550          */
 551         spinlock_t lock;
 552
 553         /* Desired TX power level (in dBm).
 554          * This is set by the user and adjusted in bcm43xx_phy_xmitpower(). */
 555         u8 power_level;
 556         /* A-PHY TX Power control value. */
 557         u16 txpwr_offset;
 558
 559         /* Current TX power level attenuation control values */
 560         struct bcm43xx_bbatt bbatt;
 561         struct bcm43xx_rfatt rfatt;
 562         u8 tx_control; /* BCM43xx_TXCTL_XXX */
 563 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
 564         u8 manual_txpower_control; /* Manual TX-power control enabled? */
 565 #endif
 566
 567         /* Current Interference Mitigation mode */
 568         int interfmode;
 569         /* Stack of saved values from the Interference Mitigation code.
 570          * Each value in the stack is layed out as follows:
 571          * bit 0-11:  offset
 572          * bit 12-15: register ID
 573          * bit 16-32: value
 574          * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
 575          */
 576 #define BCM43xx_INTERFSTACK_SIZE        26
 577         u32 interfstack[BCM43xx_INTERFSTACK_SIZE];//FIXME: use a data structure
 578
 579         /* Saved values from the NRSSI Slope calculation */
 580         s16 nrssi[2];
 581         s32 nrssislope;
 582         /* In memory nrssi lookup table. */
 583         s8 nrssi_lt[64];
 584
 585         /* current channel */
 586         u8 channel;
 587
 588         u16 lofcal;
 589
 590         u16 initval;//FIXME rename?
 591 };
 592
 593 /* Data structures for DMA transmission, per 80211 core. */
 594 struct bcm43xx_dma {
 595         struct bcm43xx_dmaring *tx_ring0;
 596         struct bcm43xx_dmaring *tx_ring1;
 597         struct bcm43xx_dmaring *tx_ring2;
 598         struct bcm43xx_dmaring *tx_ring3;
 599         struct bcm43xx_dmaring *tx_ring4;
 600         struct bcm43xx_dmaring *tx_ring5;
 601
 602         struct bcm43xx_dmaring *rx_ring0;
 603         struct bcm43xx_dmaring *rx_ring3; /* only available on core.rev < 5 */
 604 };
 605
 606 /* Data structures for PIO transmission, per 80211 core. */
 607 struct bcm43xx_pio {
 608         struct bcm43xx_pioqueue *queue0;
 609         struct bcm43xx_pioqueue *queue1;
 610         struct bcm43xx_pioqueue *queue2;
 611         struct bcm43xx_pioqueue *queue3;
 612 };
 613
 614 /* Context information for a noise calculation (Link Quality). */
 615 struct bcm43xx_noise_calculation {
 616         u8 channel_at_start;
 617         u8 calculation_running:1;
 618         u8 nr_samples;
 619         s8 samples[8][4];
 620 };
 621
 622 struct bcm43xx_stats {
 623         u8 link_noise;
 624         /* Store the last TX/RX times here for updating the leds. */
 625         unsigned long last_tx;
 626         unsigned long last_rx;
 627 };
 628
 629 struct bcm43xx_key {
 630         u8 enabled;
 631         u8 algorithm;
 632         u8 address[6];
 633 };
 634
 635 struct bcm43xx_wldev;
 636
 637 /* Data structure for the WLAN parts (802.11 cores) of the bcm43xx chip. */
 638 struct bcm43xx_wl {
 639         /* Pointer to the active wireless device on this chip */
 640         struct bcm43xx_wldev *current_dev;
 641         /* Pointer to the ieee80211 hardware data structure */
 642         struct ieee80211_hw *hw;
 643
 644         spinlock_t irq_lock;
 645         struct mutex mutex;
 646         spinlock_t leds_lock;
 647
 648         /* We can only have one operating interface (802.11 core)
 649          * at a time. General information about this interface follows.
 650          */
 651
 652         /* Opaque ID of the operating interface (!= monitor
 653          * interface) from the ieee80211 subsystem.
 654          * Do not modify.
 655          */
 656         int if_id;
 657         /* MAC address (can be NULL). */
 658         const u8 *mac_addr;
 659         /* Current BSSID (can be NULL). */
 660         const u8 *bssid;
 661         /* Interface type. (IEEE80211_IF_TYPE_XXX) */
 662         int if_type;
 663         /* Counter of active monitor interfaces. */
 664         int monitor;
 665         /* Is the card operating in AP, STA or IBSS mode? */
 666         unsigned int operating:1;
 667         /* Promisc mode active?
 668          * Note that (monitor != 0) implies promisc.
 669          */
 670         unsigned int promisc:1;
 671         /* Stats about the wireless interface */
 672         struct ieee80211_low_level_stats ieee_stats;
 673
 674         struct hwrng rng;
 675         u8 rng_initialized;
 676         char rng_name[30 + 1];
 677
 678         /* List of all wireless devices on this chip */
 679         struct list_head devlist;
 680         u8 nr_devs;
 681 };
 682
 683 /* Pointers to the firmware data and meta information about it. */
 684 struct bcm43xx_firmware {
 685         /* Microcode */
 686         const struct firmware *ucode;
 687         /* PCM code */
 688         const struct firmware *pcm;
 689         /* Initial MMIO values 0 */
 690         const struct firmware *initvals0;
 691         /* Initial MMIO values 1 */
 692         const struct firmware *initvals1;
 693         /* Firmware revision */
 694         u16 rev;
 695         /* Firmware patchlevel */
 696         u16 patch;
 697 };
 698
 699 /* Device (802.11 core) initialization status. */
 700 enum {
 701         BCM43xx_STAT_UNINIT,            /* Uninitialized. */
 702         BCM43xx_STAT_INITIALIZING,      /* bcm43xx_wireless_core_init() in progress. */
 703         BCM43xx_STAT_INITIALIZED,       /* Initialized. Note that this doesn't mean it's started. */
 704 };
 705 #define bcm43xx_status(bcm)             atomic_read(&(bcm)->init_status)
 706 #define bcm43xx_set_status(bcm, stat)   do {                    \
 707                 atomic_set(&(bcm)->init_status, (stat));        \
 708                 smp_wmb();                                      \
 709                                         } while (0)
 710
 711 /* XXX---   HOW LOCKING WORKS IN BCM43xx   ---XXX
 712  *
 713  * You should always acquire both, wl->mutex and wl->irq_lock unless:
 714  * - You don't need to acquire wl->irq_lock, if the interface is stopped.
 715  * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
 716  *   and packet TX path (and _ONLY_ there.)
 717  */
 718
 719 /* Data structure for one wireless device (802.11 core) */
 720 struct bcm43xx_wldev {
 721         struct ssb_device *dev;
 722         struct bcm43xx_wl *wl;
 723
 724         /* Driver initialization status BCM43xx_STAT_*** */
 725         atomic_t init_status;
 726         /* Interface started? (bcm43xx_wireless_core_start()) */
 727         u8 started;
 728
 729         u16 was_initialized:1,          /* for suspend/resume. */
 730             was_started:1,              /* for suspend/resume. */
 731             __using_pio:1,              /* Internal, use bcm43xx_using_pio(). */
 732             bad_frames_preempt:1,       /* Use "Bad Frames Preemption" (default off) */
 733             reg124_set_0x4:1,           /* Some variable to keep track of IRQ stuff. */
 734             short_preamble:1,           /* TRUE, if short preamble is enabled. */
 735             short_slot:1,               /* TRUE, if short slot timing is enabled. */
 736             radio_hw_enable:1;          /* saved state of radio hardware enabled state */
 737
 738         /* PHY/Radio device. */
 739         struct bcm43xx_phy phy;
 740         union {
 741                 /* DMA engines. */
 742                 struct bcm43xx_dma dma;
 743                 /* PIO engines. */
 744                 struct bcm43xx_pio pio;
 745         };
 746
 747         /* Various statistics about the physical device. */
 748         struct bcm43xx_stats stats;
 749
 750 #define BCM43xx_NR_LEDS         4
 751         struct bcm43xx_led leds[BCM43xx_NR_LEDS];
 752
 753         /* Reason code of the last interrupt. */
 754         u32 irq_reason;
 755         u32 dma_reason[6];
 756         /* saved irq enable/disable state bitfield. */
 757         u32 irq_savedstate;
 758         /* Link Quality calculation context. */
 759         struct bcm43xx_noise_calculation noisecalc;
 760         /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
 761         int mac_suspended;
 762
 763         /* Interrupt Service Routine tasklet (bottom-half) */
 764         struct tasklet_struct isr_tasklet;
 765
 766         /* Periodic tasks */
 767         struct delayed_work periodic_work;
 768         unsigned int periodic_state;
 769
 770         struct work_struct restart_work;
 771
 772         /* encryption/decryption */
 773         u16 ktp; /* Key table pointer */
 774         u8 max_nr_keys;
 775         struct bcm43xx_key key[58];
 776
 777         /* Cached beacon template while uploading the template. */
 778         struct sk_buff *cached_beacon;
 779
 780         /* Firmware data */
 781         struct bcm43xx_firmware fw;
 782
 783         /* Devicelist in struct bcm43xx_wl (all 802.11 cores) */
 784         struct list_head list;
 785
 786         /* Debugging stuff follows. */
 787 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
 788         struct bcm43xx_dfsentry *dfsentry;
 789 #endif
 790 };
 791
 792
 793 static inline
 794 struct bcm43xx_wl * hw_to_bcm43xx_wl(struct ieee80211_hw *hw)
 795 {
 796         return hw->priv;
 797 }
 798
 799 /* Helper function, which returns a boolean.
 800  * TRUE, if PIO is used; FALSE, if DMA is used.
 801  */
 802 #if defined(CONFIG_BCM43XX_MAC80211_DMA) && defined(CONFIG_BCM43XX_MAC80211_PIO)
 803 static inline
 804 int bcm43xx_using_pio(struct bcm43xx_wldev *dev)
 805 {
 806         return dev->__using_pio;
 807 }
 808 #elif defined(CONFIG_BCM43XX_MAC80211_DMA)
 809 static inline
 810 int bcm43xx_using_pio(struct bcm43xx_wldev *dev)
 811 {
 812         return 0;
 813 }
 814 #elif defined(CONFIG_BCM43XX_MAC80211_PIO)
 815 static inline
 816 int bcm43xx_using_pio(struct bcm43xx_wldev *dev)
 817 {
 818         return 1;
 819 }
 820 #else
 821 # error "Using neither DMA nor PIO? Confused..."
 822 #endif
 823
 824
 825 static inline
 826 struct bcm43xx_wldev * dev_to_bcm43xx_wldev(struct device *dev)
 827 {
 828         struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
 829         return ssb_get_drvdata(ssb_dev);
 830 }
 831
 832 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
 833 static inline
 834 int bcm43xx_is_mode(struct bcm43xx_wl *wl, int type)
 835 {
 836         if (type == IEEE80211_IF_TYPE_MNTR)
 837                 return !!(wl->monitor);
 838         return (wl->operating &&
 839                 wl->if_type == type);
 840 }
 841
 842 static inline
 843 u16 bcm43xx_read16(struct bcm43xx_wldev *dev, u16 offset)
 844 {
 845         return ssb_read16(dev->dev, offset);
 846 }
 847
 848 static inline
 849 void bcm43xx_write16(struct bcm43xx_wldev *dev, u16 offset, u16 value)
 850 {
 851         ssb_write16(dev->dev, offset, value);
 852 }
 853
 854 static inline
 855 u32 bcm43xx_read32(struct bcm43xx_wldev *dev, u16 offset)
 856 {
 857         return ssb_read32(dev->dev, offset);
 858 }
 859
 860 static inline
 861 void bcm43xx_write32(struct bcm43xx_wldev *dev, u16 offset, u32 value)
 862 {
 863         ssb_write32(dev->dev, offset, value);
 864 }
 865
 866 /** Limit a value between two limits */
 867 #ifdef limit_value
 868 # undef limit_value
 869 #endif
 870 #define limit_value(value, min, max)  \
 871         ({                                              \
 872                 typeof(value) __value = (value);        \
 873                 typeof(value) __min = (min);            \
 874                 typeof(value) __max = (max);            \
 875                 if (__value < __min)                    \
 876                         __value = __min;                \
 877                 else if (__value > __max)               \
 878                         __value = __max;                \
 879                 __value;                                \
 880         })
 881
 882 /* Macros for printing a value in Q5.2 format */
 883 #define Q52_FMT         "%u.%u"
 884 #define Q52_ARG(q52)    ((q52) / 4), ((((q52) & 3) * 100) / 4)
 885
 886 #endif /* BCM43xx_H_ */