package/boot/uboot-kirkwood/patches/701-phy-mv88e61xx-add-support-for-RGMII-TX-RX-delay.patch

   1 From 940e9a5828480e4185c9a276ad7f35a4069a2393 Mon Sep 17 00:00:00 2001
   2 From: Pawel Dembicki <paweldembicki@gmail.com>
   3 Date: Thu, 23 Jan 2020 22:04:15 +0100
   4 Subject: [PATCH 1/2] phy: mv88e61xx: add support for RGMII TX/RX delay
   5
   6 Clock delay in RGMII is required for some boards.
   7 This patch introduce CONFIG_MV88E61XX_CPU_PORT_TX_DELAY and
   8 CONFIG_MV88E61XX_CPU_PORT_RX_DELAY defines, which are setting
   9 proper bits in PORT_REG_PHYS_CTRL register.
  10
  11 Cc: Chris Packham <judge.packham@gmail.com>
  12 Cc: Joe Hershberger <joe.hershberger@ni.com>
  13 Cc: Anatolij Gustschin <agust@denx.de>
  14 Cc: Tim Harvey <tharvey@gateworks.com>
  15 Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
  16 ---
  17  drivers/net/phy/mv88e61xx.c | 11 ++++++++++-
  18  1 file changed, 10 insertions(+), 1 deletion(-)
  19
  20 diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c
  21 index 5aff7ed397..889327639d 100644
  22 --- a/drivers/net/phy/mv88e61xx.c
  23 +++ b/drivers/net/phy/mv88e61xx.c
  24 @@ -94,6 +94,8 @@
  25  #define PORT_REG_STATUS_CMODE_1000BASE_X       0x9
  26  #define PORT_REG_STATUS_CMODE_SGMII            0xa
  27
  28 +#define PORT_REG_PHYS_CTRL_RGMII_RX_DELAY      BIT(15)
  29 +#define PORT_REG_PHYS_CTRL_RGMII_TX_DELAY      BIT(14)
  30  #define PORT_REG_PHYS_CTRL_PCS_AN_EN   BIT(10)
  31  #define PORT_REG_PHYS_CTRL_PCS_AN_RST  BIT(9)
  32  #define PORT_REG_PHYS_CTRL_FC_VALUE    BIT(7)
  33 @@ -747,9 +749,16 @@ static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
  34                        PORT_REG_PHYS_CTRL_SPD1000;
  35         }
  36
  37 -       if (port == CONFIG_MV88E61XX_CPU_PORT)
  38 +       if (port == CONFIG_MV88E61XX_CPU_PORT) {
  39                 val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
  40                        PORT_REG_PHYS_CTRL_LINK_FORCE;
  41 +#if defined(CONFIG_MV88E61XX_CPU_PORT_RX_DELAY)
  42 +               val |= PORT_REG_PHYS_CTRL_RGMII_RX_DELAY;
  43 +#endif
  44 +#if defined(CONFIG_MV88E61XX_CPU_PORT_TX_DELAY)
  45 +               val |= PORT_REG_PHYS_CTRL_RGMII_TX_DELAY;
  46 +#endif
  47 +       }
  48
  49         return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
  50                                    val);
  51 --
  52 2.20.1
  53