uboot-lantiq: Support newer versions of the PEF7071 ethernet
[openwrt/openwrt.git] / package / boot / uboot-lantiq / patches / 0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch
1 From 11553b0de8992ded6240d034bd49f561d17bea53 Mon Sep 17 00:00:00 2001
2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 Date: Thu, 13 Jun 2013 01:18:02 +0200
4 Subject: MIPS: add support for Lantiq XWAY SoCs
5
6 Signed-off-by: Luka Perkov <luka@openwrt.org>
7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8
9 --- a/.gitignore
10 +++ b/.gitignore
11 @@ -49,6 +49,13 @@
12 /u-boot.sb
13 /u-boot.bd
14 /u-boot.geany
15 +/u-boot.bin.lzma
16 +/u-boot.bin.lzo
17 +/u-boot.ltq.lzma.norspl
18 +/u-boot.ltq.lzo.norspl
19 +/u-boot.ltq.norspl
20 +/u-boot.lzma.img
21 +/u-boot.lzo.img
22
23 #
24 # Generated files
25 --- a/Makefile
26 +++ b/Makefile
27 @@ -435,6 +435,12 @@ $(obj)u-boot.bin: $(obj)u-boot
28 $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
29 $(BOARD_SIZE_CHECK)
30
31 +$(obj)u-boot.bin.lzma: $(obj)u-boot.bin
32 + cat $< | lzma -9 -f - > $@
33 +
34 +$(obj)u-boot.bin.lzo: $(obj)u-boot.bin
35 + cat $< | lzop -9 -f - > $@
36 +
37 $(obj)u-boot.ldr: $(obj)u-boot
38 $(CREATE_LDR_ENV)
39 $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
40 @@ -454,13 +460,23 @@ ifndef CONFIG_SYS_UBOOT_START
41 CONFIG_SYS_UBOOT_START := 0
42 endif
43
44 -$(obj)u-boot.img: $(obj)u-boot.bin
45 - $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
46 +define GEN_UBOOT_IMAGE
47 + $(obj)tools/mkimage -A $(ARCH) -T firmware -C $(1) \
48 -O u-boot -a $(CONFIG_SYS_TEXT_BASE) \
49 -e $(CONFIG_SYS_UBOOT_START) \
50 -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
51 sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
52 -d $< $@
53 +endef
54 +
55 +$(obj)u-boot.img: $(obj)u-boot.bin
56 + $(call GEN_UBOOT_IMAGE,none)
57 +
58 +$(obj)u-boot.lzma.img: $(obj)u-boot.bin.lzma
59 + $(call GEN_UBOOT_IMAGE,lzma)
60 +
61 +$(obj)u-boot.lzo.img: $(obj)u-boot.bin.lzo
62 + $(call GEN_UBOOT_IMAGE,lzo)
63
64 $(obj)u-boot.imx: $(obj)u-boot.bin depend
65 $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx
66 @@ -571,6 +587,27 @@ $(obj)u-boot-img-spl-at-end.bin: $(obj)s
67 conv=notrunc 2>/dev/null
68 cat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@
69
70 +$(obj)u-boot.ltq.sfspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
71 + $(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \
72 + -s $(obj)spl/u-boot-spl.bin -u $< -o $@
73 +
74 +$(obj)u-boot.ltq.lzo.sfspl: $(obj)u-boot.lzo.img $(obj)spl/u-boot-spl.bin
75 + $(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \
76 + -s $(obj)spl/u-boot-spl.bin -u $< -o $@
77 +
78 +$(obj)u-boot.ltq.lzma.sfspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin
79 + $(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \
80 + -s $(obj)spl/u-boot-spl.bin -u $< -o $@
81 +
82 +$(obj)u-boot.ltq.norspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
83 + cat $(obj)spl/u-boot-spl.bin $< > $@
84 +
85 +$(obj)u-boot.ltq.lzo.norspl: $(obj)u-boot.lzo.img $(obj)spl/u-boot-spl.bin
86 + cat $(obj)spl/u-boot-spl.bin $< > $@
87 +
88 +$(obj)u-boot.ltq.lzma.norspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin
89 + cat $(obj)spl/u-boot-spl.bin $< > $@
90 +
91 ifeq ($(CONFIG_SANDBOX),y)
92 GEN_UBOOT = \
93 cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
94 --- a/README
95 +++ b/README
96 @@ -468,6 +468,11 @@ The following options need to be configu
97 CONF_CM_CACHABLE_CUW
98 CONF_CM_CACHABLE_ACCELERATED
99
100 + CONFIG_SYS_MIPS_CACHE_EXT_INIT
101 +
102 + Enable this to use extended cache initialization for recent
103 + MIPS CPU cores.
104 +
105 CONFIG_SYS_XWAY_EBU_BOOTCFG
106
107 Special option for Lantiq XWAY SoCs for booting from NOR flash.
108 --- a/arch/mips/config.mk
109 +++ b/arch/mips/config.mk
110 @@ -45,9 +45,13 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__M
111 # On the other hand, we want PIC in the U-Boot code to relocate it from ROM
112 # to RAM. $28 is always used as gp.
113 #
114 -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS)
115 +PF_ABICALLS ?= -mabicalls
116 +PF_PIC ?= -fpic
117 +PF_PIE ?= -pie
118 +
119 +PLATFORM_CPPFLAGS += -G 0 $(PF_ABICALLS) $(PF_PIC) $(ENDIANNESS)
120 PLATFORM_CPPFLAGS += -msoft-float
121 PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS)
122 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
123 -LDFLAGS_FINAL += --gc-sections -pie
124 +LDFLAGS_FINAL += --gc-sections $(PF_PIE)
125 OBJCFLAGS += --remove-section=.dynsym
126 --- a/arch/mips/cpu/mips32/cache.S
127 +++ b/arch/mips/cpu/mips32/cache.S
128 @@ -29,7 +29,11 @@
129 */
130 #define MIPS_MAX_CACHE_SIZE 0x10000
131
132 +#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
133 +#define INDEX_BASE 0x9fc00000
134 +#else
135 #define INDEX_BASE CKSEG0
136 +#endif
137
138 .macro cache_op op addr
139 .set push
140 @@ -65,7 +69,11 @@
141 */
142 LEAF(mips_init_icache)
143 blez a1, 9f
144 +#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
145 + mtc0 zero, CP0_ITAGLO
146 +#else
147 mtc0 zero, CP0_TAGLO
148 +#endif
149 /* clear tag to invalidate */
150 PTR_LI t0, INDEX_BASE
151 PTR_ADDU t1, t0, a1
152 @@ -90,7 +98,11 @@ LEAF(mips_init_icache)
153 */
154 LEAF(mips_init_dcache)
155 blez a1, 9f
156 +#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
157 + mtc0 zero, CP0_DTAGLO
158 +#else
159 mtc0 zero, CP0_TAGLO
160 +#endif
161 /* clear all tags */
162 PTR_LI t0, INDEX_BASE
163 PTR_ADDU t1, t0, a1
164 --- /dev/null
165 +++ b/arch/mips/cpu/mips32/danube/Makefile
166 @@ -0,0 +1,31 @@
167 +#
168 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
169 +#
170 +# SPDX-License-Identifier: GPL-2.0+
171 +#
172 +
173 +include $(TOPDIR)/config.mk
174 +
175 +LIB = $(obj)lib$(SOC).o
176 +
177 +COBJS-y += cgu.o chipid.o ebu.o mem.o pmu.o rcu.o
178 +SOBJS-y += cgu_init.o mem_init.o
179 +
180 +COBJS := $(COBJS-y)
181 +SOBJS := $(SOBJS-y)
182 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
183 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
184 +
185 +all: $(LIB)
186 +
187 +$(LIB): $(obj).depend $(OBJS)
188 + $(call cmd_link_o_target, $(OBJS))
189 +
190 +#########################################################################
191 +
192 +# defines $(obj).depend target
193 +include $(SRCTREE)/rules.mk
194 +
195 +sinclude $(obj).depend
196 +
197 +#########################################################################
198 --- /dev/null
199 +++ b/arch/mips/cpu/mips32/danube/cgu.c
200 @@ -0,0 +1,117 @@
201 +/*
202 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
203 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
204 + *
205 + * SPDX-License-Identifier: GPL-2.0+
206 + */
207 +
208 +#include <common.h>
209 +#include <asm/arch/soc.h>
210 +#include <asm/lantiq/clk.h>
211 +#include <asm/lantiq/io.h>
212 +
213 +#define LTQ_CGU_SYS_DDR_MASK 0x0003
214 +#define LTQ_CGU_SYS_DDR_SHIFT 0
215 +#define LTQ_CGU_SYS_CPU0_MASK 0x000C
216 +#define LTQ_CGU_SYS_CPU0_SHIFT 2
217 +#define LTQ_CGU_SYS_FPI_MASK 0x0040
218 +#define LTQ_CGU_SYS_FPI_SHIFT 6
219 +
220 +struct ltq_cgu_regs {
221 + u32 rsvd0;
222 + u32 pll0_cfg; /* PLL0 config */
223 + u32 pll1_cfg; /* PLL1 config */
224 + u32 pll2_cfg; /* PLL2 config */
225 + u32 sys; /* System clock */
226 + u32 update; /* CGU update control */
227 + u32 if_clk; /* Interface clock */
228 + u32 osc_con; /* Update OSC Control */
229 + u32 smd; /* SDRAM Memory Control */
230 + u32 rsvd1[3];
231 + u32 pcm_cr; /* PCM control */
232 + u32 pci_cr; /* PCI clock control */
233 +};
234 +
235 +static struct ltq_cgu_regs *ltq_cgu_regs =
236 + (struct ltq_cgu_regs *) CKSEG1ADDR(LTQ_CGU_BASE);
237 +
238 +static inline u32 ltq_cgu_sys_readl(u32 mask, u32 shift)
239 +{
240 + return (ltq_readl(&ltq_cgu_regs->sys) & mask) >> shift;
241 +}
242 +
243 +unsigned long ltq_get_io_region_clock(void)
244 +{
245 + u32 ddr_sel;
246 + unsigned long clk;
247 +
248 + ddr_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_DDR_MASK,
249 + LTQ_CGU_SYS_DDR_SHIFT);
250 +
251 + switch (ddr_sel) {
252 + case 0:
253 + clk = CLOCK_166_MHZ;
254 + break;
255 + case 1:
256 + clk = CLOCK_133_MHZ;
257 + break;
258 + case 2:
259 + clk = CLOCK_111_MHZ;
260 + break;
261 + case 3:
262 + clk = CLOCK_83_MHZ;
263 + break;
264 + default:
265 + clk = 0;
266 + break;
267 + }
268 +
269 + return clk;
270 +}
271 +
272 +unsigned long ltq_get_cpu_clock(void)
273 +{
274 + u32 cpu0_sel;
275 + unsigned long clk;
276 +
277 + cpu0_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_CPU0_MASK,
278 + LTQ_CGU_SYS_CPU0_SHIFT);
279 +
280 + switch (cpu0_sel) {
281 + /* Same as PLL0 output (333,33 MHz) */
282 + case 0:
283 + clk = CLOCK_333_MHZ;
284 + break;
285 + /* 1/1 fixed ratio to DDR clock */
286 + case 1:
287 + clk = ltq_get_io_region_clock();
288 + break;
289 + /* 1/2 fixed ratio to DDR clock */
290 + case 2:
291 + clk = ltq_get_io_region_clock() << 1;
292 + break;
293 + default:
294 + clk = 0;
295 + break;
296 + }
297 +
298 + return clk;
299 +}
300 +
301 +unsigned long ltq_get_bus_clock(void)
302 +{
303 + u32 fpi_sel;
304 + unsigned long clk;
305 +
306 + fpi_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_FPI_MASK,
307 + LTQ_CGU_SYS_FPI_SHIFT);
308 +
309 + if (fpi_sel)
310 + /* Half the DDR clock */
311 + clk = ltq_get_io_region_clock() >> 1;
312 + else
313 + /* Same as DDR clock */
314 + clk = ltq_get_io_region_clock();
315 +
316 + return clk;
317 +}
318 --- /dev/null
319 +++ b/arch/mips/cpu/mips32/danube/cgu_init.S
320 @@ -0,0 +1,142 @@
321 +/*
322 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
323 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
324 + *
325 + * SPDX-License-Identifier: GPL-2.0+
326 + */
327 +
328 +#include <config.h>
329 +#include <asm/asm.h>
330 +#include <asm/regdef.h>
331 +#include <asm/addrspace.h>
332 +#include <asm/arch/soc.h>
333 +
334 +/* RCU module register */
335 +#define LTQ_RCU_RST_REQ 0x0010
336 +#define LTQ_RCU_RST_STAT 0x0014
337 +#define LTQ_RCU_RST_REQ_VALUE 0x40000008
338 +#define LTQ_RCU_RST_STAT_XTAL_F 0x20000
339 +
340 +/* CGU module register */
341 +#define LTQ_CGU_PLL0_CFG 0x0004 /* PLL0 config */
342 +#define LTQ_CGU_PLL1_CFG 0x0008 /* PLL1 config */
343 +#define LTQ_CGU_PLL2_CFG 0x000C /* PLL2 config */
344 +#define LTQ_CGU_SYS 0x0010 /* System clock */
345 +
346 +/* Valid SYS.CPU0/1 values */
347 +#define LTQ_CGU_SYS_CPU0_SHIFT 2
348 +#define LTQ_CGU_SYS_CPU1_SHIFT 4
349 +#define LTQ_CGU_SYS_CPU_PLL0 0x0
350 +#define LTQ_CGU_SYS_CPU_DDR_EQUAL 0x1
351 +#define LTQ_CGU_SYS_CPU_DDR_TWICE 0x2
352 +
353 +/* Valid SYS.DDR values */
354 +#define LTQ_CGU_SYS_DDR_SHIFT 0
355 +#define LTQ_CGU_SYS_DDR_167_MHZ 0x0
356 +#define LTQ_CGU_SYS_DDR_133_MHZ 0x1
357 +#define LTQ_CGU_SYS_DDR_111_MHZ 0x2
358 +#define LTQ_CGU_SYS_DDR_83_MHZ 0x3
359 +
360 +/* Valid SYS.FPI values */
361 +#define LTQ_CGU_SYS_FPI_SHIFT 6
362 +#define LTQ_CGU_SYS_FPI_DDR_EQUAL 0x0
363 +#define LTQ_CGU_SYS_FPI_DDR_HALF 0x1
364 +
365 +/* Valid SYS.PPE values */
366 +#define LTQ_CGU_SYS_PPE_SHIFT 7
367 +#define LTQ_CGU_SYS_PPE_266_MHZ 0x0
368 +#define LTQ_CGU_SYS_PPE_240_MHZ 0x1
369 +#define LTQ_CGU_SYS_PPE_222_MHZ 0x2
370 +#define LTQ_CGU_SYS_PPE_133_MHZ 0x3
371 +
372 +#if (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_333_DDR_167)
373 +#define LTQ_CGU_SYS_CPU_CONFIG LTQ_CGU_SYS_CPU_DDR_TWICE
374 +#define LTQ_CGU_SYS_DDR_CONFIG LTQ_CGU_SYS_DDR_167_MHZ
375 +#define LTQ_CGU_SYS_FPI_CONFIG LTQ_CGU_SYS_FPI_DDR_HALF
376 +#define LTQ_CGU_SYS_PPE_CONFIG LTQ_CGU_SYS_PPE_266_MHZ
377 +#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_111_DDR_111)
378 +#define LTQ_CGU_SYS_CPU_CONFIG LTQ_CGU_SYS_CPU_DDR_EQUAL
379 +#define LTQ_CGU_SYS_DDR_CONFIG LTQ_CGU_SYS_DDR_111_MHZ
380 +#define LTQ_CGU_SYS_FPI_CONFIG LTQ_CGU_SYS_FPI_DDR_HALF
381 +#define LTQ_CGU_SYS_PPE_CONFIG LTQ_CGU_SYS_PPE_133_MHZ
382 +#else
383 +#error "Invalid system clock configuration!"
384 +#endif
385 +
386 +/* Build register values */
387 +#define LTQ_CGU_SYS_VALUE ((LTQ_CGU_SYS_PPE_CONFIG << \
388 + LTQ_CGU_SYS_PPE_SHIFT) | \
389 + (LTQ_CGU_SYS_FPI_CONFIG << \
390 + LTQ_CGU_SYS_FPI_SHIFT) | \
391 + (LTQ_CGU_SYS_CPU_CONFIG << \
392 + LTQ_CGU_SYS_CPU1_SHIFT) | \
393 + (LTQ_CGU_SYS_CPU_CONFIG << \
394 + LTQ_CGU_SYS_CPU0_SHIFT) | \
395 + LTQ_CGU_SYS_DDR_CONFIG)
396 +
397 +/* Reset values for PLL registers for usage with 35.328 MHz crystal */
398 +#define PLL0_35MHZ_CONFIG 0x9D861059
399 +#define PLL1_35MHZ_CONFIG 0x1A260CD9
400 +#define PLL2_35MHZ_CONFIG 0x8000f1e5
401 +
402 +/* Reset values for PLL registers for usage with 36 MHz crystal */
403 +#define PLL0_36MHZ_CONFIG 0x1000125D
404 +#define PLL1_36MHZ_CONFIG 0x1B1E0C99
405 +#define PLL2_36MHZ_CONFIG 0x8002f2a1
406 +
407 +LEAF(ltq_cgu_init)
408 + /* Load current CGU register value */
409 + li t0, (LTQ_CGU_BASE | KSEG1)
410 + lw t1, LTQ_CGU_SYS(t0)
411 +
412 + /* Load target CGU register values */
413 + li t3, LTQ_CGU_SYS_VALUE
414 +
415 + /* Only update registers if values differ */
416 + beq t1, t3, finished
417 +
418 + /*
419 + * Check whether the XTAL_F bit in RST_STAT register is set or not.
420 + * This bit is latched in via pin strapping. If bit is set then
421 + * clock source is a 36 MHz crystal. Otherwise a 35.328 MHz crystal.
422 + */
423 + li t1, (LTQ_RCU_BASE | KSEG1)
424 + lw t2, LTQ_RCU_RST_STAT(t1)
425 + and t2, t2, LTQ_RCU_RST_STAT_XTAL_F
426 + beq t2, LTQ_RCU_RST_STAT_XTAL_F, boot_36mhz
427 +
428 +boot_35mhz:
429 + /* Configure PLL for 35.328 MHz */
430 + li t2, PLL0_35MHZ_CONFIG
431 + sw t2, LTQ_CGU_PLL0_CFG(t0)
432 + li t2, PLL1_35MHZ_CONFIG
433 + sw t2, LTQ_CGU_PLL1_CFG(t0)
434 + li t2, PLL2_35MHZ_CONFIG
435 + sw t2, LTQ_CGU_PLL2_CFG(t0)
436 +
437 + b do_reset
438 +
439 +boot_36mhz:
440 + /* Configure PLL for 36 MHz */
441 + li t2, PLL0_36MHZ_CONFIG
442 + sw t2, LTQ_CGU_PLL0_CFG(t0)
443 + li t2, PLL1_36MHZ_CONFIG
444 + sw t2, LTQ_CGU_PLL1_CFG(t0)
445 + li t2, PLL2_36MHZ_CONFIG
446 + sw t2, LTQ_CGU_PLL2_CFG(t0)
447 +
448 +do_reset:
449 + /* Store new clock config */
450 + sw t3, LTQ_CGU_SYS(t0)
451 +
452 + /* Perform software reset to activate new clock config */
453 + li t2, LTQ_RCU_RST_REQ_VALUE
454 + sw t2, LTQ_RCU_RST_REQ(t1)
455 +
456 +wait_reset:
457 + b wait_reset
458 +
459 +finished:
460 + jr ra
461 +
462 + END(ltq_cgu_init)
463 --- /dev/null
464 +++ b/arch/mips/cpu/mips32/danube/chipid.c
465 @@ -0,0 +1,59 @@
466 +/*
467 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
468 + *
469 + * SPDX-License-Identifier: GPL-2.0+
470 + */
471 +
472 +#include <common.h>
473 +#include <asm/lantiq/io.h>
474 +#include <asm/lantiq/chipid.h>
475 +#include <asm/arch/soc.h>
476 +
477 +#define LTQ_CHIPID_VERSION_SHIFT 28
478 +#define LTQ_CHIPID_VERSION_MASK (0xF << LTQ_CHIPID_VERSION_SHIFT)
479 +#define LTQ_CHIPID_PNUM_SHIFT 12
480 +#define LTQ_CHIPID_PNUM_MASK (0xFFFF << LTQ_CHIPID_PNUM_SHIFT)
481 +
482 +struct ltq_chipid_regs {
483 + u32 manid; /* Manufacturer identification */
484 + u32 chipid; /* Chip identification */
485 +};
486 +
487 +static struct ltq_chipid_regs *ltq_chipid_regs =
488 + (struct ltq_chipid_regs *) CKSEG1ADDR(LTQ_CHIPID_BASE);
489 +
490 +unsigned int ltq_chip_version_get(void)
491 +{
492 + u32 chipid;
493 +
494 + chipid = ltq_readl(&ltq_chipid_regs->chipid);
495 +
496 + return (chipid & LTQ_CHIPID_VERSION_MASK) >> LTQ_CHIPID_VERSION_SHIFT;
497 +}
498 +
499 +unsigned int ltq_chip_partnum_get(void)
500 +{
501 + u32 chipid;
502 +
503 + chipid = ltq_readl(&ltq_chipid_regs->chipid);
504 +
505 + return (chipid & LTQ_CHIPID_PNUM_MASK) >> LTQ_CHIPID_PNUM_SHIFT;
506 +}
507 +
508 +const char *ltq_chip_partnum_str(void)
509 +{
510 + enum ltq_chip_partnum partnum = ltq_chip_partnum_get();
511 +
512 + switch (partnum) {
513 + case LTQ_SOC_DANUBE:
514 + return "Danube";
515 + case LTQ_SOC_DANUBE_S:
516 + return "Danube-S";
517 + case LTQ_SOC_TWINPASS:
518 + return "Twinpass";
519 + default:
520 + printf("Unknown partnum: %x\n", partnum);
521 + }
522 +
523 + return "";
524 +}
525 --- /dev/null
526 +++ b/arch/mips/cpu/mips32/danube/config.mk
527 @@ -0,0 +1,25 @@
528 +#
529 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
530 +#
531 +# SPDX-License-Identifier: GPL-2.0+
532 +#
533 +
534 +PF_CPPFLAGS_DANUBE := $(call cc-option,-mtune=24kec,)
535 +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_DANUBE)
536 +
537 +ifdef CONFIG_SPL_BUILD
538 +PF_ABICALLS := -mno-abicalls
539 +PF_PIC := -fno-pic
540 +PF_PIE :=
541 +USE_PRIVATE_LIBGCC := yes
542 +endif
543 +
544 +LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o
545 +
546 +ifndef CONFIG_SPL_BUILD
547 +ifdef CONFIG_SYS_BOOT_NORSPL
548 +ALL-y += $(obj)u-boot.ltq.norspl
549 +ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl
550 +ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl
551 +endif
552 +endif
553 --- /dev/null
554 +++ b/arch/mips/cpu/mips32/danube/ebu.c
555 @@ -0,0 +1,105 @@
556 +/*
557 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
558 + *
559 + * SPDX-License-Identifier: GPL-2.0+
560 + */
561 +
562 +#include <common.h>
563 +#include <asm/arch/soc.h>
564 +#include <asm/lantiq/io.h>
565 +
566 +#define EBU_ADDRSEL_MASK(mask) ((mask & 0xf) << 4)
567 +#define EBU_ADDRSEL_REGEN (1 << 0)
568 +
569 +#define EBU_CON_WRDIS (1 << 31)
570 +#define EBU_CON_AGEN_DEMUX (0x0 << 24)
571 +#define EBU_CON_AGEN_MUX (0x2 << 24)
572 +#define EBU_CON_SETUP (1 << 22)
573 +#define EBU_CON_WAIT_DIS (0x0 << 20)
574 +#define EBU_CON_WAIT_ASYNC (0x1 << 20)
575 +#define EBU_CON_WAIT_SYNC (0x2 << 20)
576 +#define EBU_CON_WINV (1 << 19)
577 +#define EBU_CON_PW_8BIT (0x0 << 16)
578 +#define EBU_CON_PW_16BIT (0x1 << 16)
579 +#define EBU_CON_ALEC(cycles) ((cycles & 0x3) << 14)
580 +#define EBU_CON_BCGEN_CS (0x0 << 12)
581 +#define EBU_CON_BCGEN_INTEL (0x1 << 12)
582 +#define EBU_CON_BCGEN_MOTOROLA (0x2 << 12)
583 +#define EBU_CON_WAITWRC(cycles) ((cycles & 0x7) << 8)
584 +#define EBU_CON_WAITRDC(cycles) ((cycles & 0x3) << 6)
585 +#define EBU_CON_HOLDC(cycles) ((cycles & 0x3) << 4)
586 +#define EBU_CON_RECOVC(cycles) ((cycles & 0x3) << 2)
587 +#define EBU_CON_CMULT_1 0x0
588 +#define EBU_CON_CMULT_4 0x1
589 +#define EBU_CON_CMULT_8 0x2
590 +#define EBU_CON_CMULT_16 0x3
591 +
592 +#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
593 +#define ebu_region0_enable 1
594 +#else
595 +#define ebu_region0_enable 0
596 +#endif
597 +
598 +#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
599 +#define ebu_region1_enable 1
600 +#else
601 +#define ebu_region1_enable 0
602 +#endif
603 +
604 +struct ltq_ebu_regs {
605 + u32 clc;
606 + u32 rsvd0[3];
607 + u32 con;
608 + u32 rsvd1[3];
609 + u32 addr_sel_0;
610 + u32 addr_sel_1;
611 + u32 rsvd2[14];
612 + u32 con_0;
613 + u32 con_1;
614 +};
615 +
616 +static struct ltq_ebu_regs *ltq_ebu_regs =
617 + (struct ltq_ebu_regs *) CKSEG1ADDR(LTQ_EBU_BASE);
618 +
619 +void ltq_ebu_init(void)
620 +{
621 + if (ebu_region0_enable) {
622 + /*
623 + * Map EBU region 0 to range 0x10000000-0x13ffffff and enable
624 + * region control. This supports up to 32 MiB NOR flash in
625 + * bank 0.
626 + */
627 + ltq_writel(&ltq_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE |
628 + EBU_ADDRSEL_MASK(1) | EBU_ADDRSEL_REGEN);
629 +
630 + ltq_writel(&ltq_ebu_regs->con_0, EBU_CON_AGEN_DEMUX |
631 + EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |
632 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
633 + EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |
634 + EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |
635 + EBU_CON_CMULT_16);
636 + } else
637 + ltq_clrbits(&ltq_ebu_regs->addr_sel_0, EBU_ADDRSEL_REGEN);
638 +
639 + if (ebu_region1_enable) {
640 + /*
641 + * Map EBU region 1 to range 0x14000000-0x13ffffff and enable
642 + * region control. This supports NAND flash in bank 1.
643 + */
644 + ltq_writel(&ltq_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE |
645 + EBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN);
646 +
647 + ltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |
648 + EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT |
649 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
650 + EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) |
651 + EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) |
652 + EBU_CON_CMULT_4);
653 + } else
654 + ltq_clrbits(&ltq_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN);
655 +}
656 +
657 +void *flash_swap_addr(unsigned long addr)
658 +{
659 + return (void *)(addr ^ 2);
660 +}
661 --- /dev/null
662 +++ b/arch/mips/cpu/mips32/danube/mem.c
663 @@ -0,0 +1,30 @@
664 +/*
665 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
666 + *
667 + * SPDX-License-Identifier: GPL-2.0+
668 + */
669 +
670 +#include <common.h>
671 +#include <asm/arch/soc.h>
672 +#include <asm/lantiq/io.h>
673 +
674 +static void *ltq_mc_ddr_base = (void *) CKSEG1ADDR(LTQ_MC_DDR_BASE);
675 +
676 +static inline u32 ltq_mc_dc_read(u32 index)
677 +{
678 + return ltq_readl(ltq_mc_ddr_base + LTQ_MC_DDR_DC_OFFSET(index));
679 +}
680 +
681 +phys_size_t initdram(int board_type)
682 +{
683 + u32 col, row, dc04, dc19, dc20;
684 +
685 + dc04 = ltq_mc_dc_read(4);
686 + dc19 = ltq_mc_dc_read(19);
687 + dc20 = ltq_mc_dc_read(20);
688 +
689 + row = (dc04 & 0xF) - ((dc19 & 0x700) >> 8);
690 + col = ((dc04 & 0xF00) >> 8) - (dc20 & 0x7);
691 +
692 + return (1 << (row + col)) * 4 * 2;
693 +}
694 --- /dev/null
695 +++ b/arch/mips/cpu/mips32/danube/mem_init.S
696 @@ -0,0 +1,114 @@
697 +/*
698 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
699 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
700 + *
701 + * SPDX-License-Identifier: GPL-2.0+
702 + */
703 +
704 +#include <config.h>
705 +#include <asm/asm.h>
706 +#include <asm/regdef.h>
707 +#include <asm/addrspace.h>
708 +#include <asm/arch/soc.h>
709 +
710 +/* Must be configured in BOARDDIR */
711 +#include <ddr_settings.h>
712 +
713 +#define LTQ_MC_GEN_ERRCAUSE 0x0010
714 +#define LTQ_MC_GEN_ERRADDR 0x0020
715 +#define LTQ_MC_GEN_CON 0x0060
716 +#define LTQ_MC_GEN_STAT 0x0070
717 +#define LTQ_MC_GEN_CON_SRAM_DDR_ENABLE 0x5
718 +#define LTQ_MC_GEN_STAT_DLCK_PWRON 0xC
719 +
720 +#define LTQ_MC_DDR_DC03_MC_START 0x100
721 +
722 + /* Store given value in MC DDR CCRx register */
723 + .macro dc_sw num, val
724 + li t2, \val
725 + sw t2, LTQ_MC_DDR_DC_OFFSET(\num)(t1)
726 + .endm
727 +
728 +LEAF(ltq_mem_init)
729 + /* Load MC General and MC DDR module base */
730 + li t0, (LTQ_MC_GEN_BASE | KSEG1)
731 + li t1, (LTQ_MC_DDR_BASE | KSEG1)
732 +
733 + /* Clear access error log registers */
734 + sw zero, LTQ_MC_GEN_ERRCAUSE(t0)
735 + sw zero, LTQ_MC_GEN_ERRADDR(t0)
736 +
737 + /* Enable DDR and SRAM module in memory controller */
738 + li t2, LTQ_MC_GEN_CON_SRAM_DDR_ENABLE
739 + sw t2, LTQ_MC_GEN_CON(t0)
740 +
741 + /* Clear start bit of DDR memory controller */
742 + sw zero, LTQ_MC_DDR_DC_OFFSET(3)(t1)
743 +
744 + /* Init memory controller registers with values ddr_settings.h */
745 + dc_sw 0, MC_DC00_VALUE
746 + dc_sw 1, MC_DC01_VALUE
747 + dc_sw 2, MC_DC02_VALUE
748 + dc_sw 4, MC_DC04_VALUE
749 + dc_sw 5, MC_DC05_VALUE
750 + dc_sw 6, MC_DC06_VALUE
751 + dc_sw 7, MC_DC07_VALUE
752 + dc_sw 8, MC_DC08_VALUE
753 + dc_sw 9, MC_DC09_VALUE
754 +
755 + dc_sw 10, MC_DC10_VALUE
756 + dc_sw 11, MC_DC11_VALUE
757 + dc_sw 12, MC_DC12_VALUE
758 + dc_sw 13, MC_DC13_VALUE
759 + dc_sw 14, MC_DC14_VALUE
760 + dc_sw 15, MC_DC15_VALUE
761 + dc_sw 16, MC_DC16_VALUE
762 + dc_sw 17, MC_DC17_VALUE
763 + dc_sw 18, MC_DC18_VALUE
764 + dc_sw 19, MC_DC19_VALUE
765 +
766 + dc_sw 20, MC_DC20_VALUE
767 + dc_sw 21, MC_DC21_VALUE
768 + dc_sw 22, MC_DC22_VALUE
769 + dc_sw 23, MC_DC23_VALUE
770 + dc_sw 24, MC_DC24_VALUE
771 + dc_sw 25, MC_DC25_VALUE
772 + dc_sw 26, MC_DC26_VALUE
773 + dc_sw 27, MC_DC27_VALUE
774 + dc_sw 28, MC_DC28_VALUE
775 + dc_sw 29, MC_DC29_VALUE
776 +
777 + dc_sw 30, MC_DC30_VALUE
778 + dc_sw 31, MC_DC31_VALUE
779 + dc_sw 32, MC_DC32_VALUE
780 + dc_sw 33, MC_DC33_VALUE
781 + dc_sw 34, MC_DC34_VALUE
782 + dc_sw 35, MC_DC35_VALUE
783 + dc_sw 36, MC_DC36_VALUE
784 + dc_sw 37, MC_DC37_VALUE
785 + dc_sw 38, MC_DC38_VALUE
786 + dc_sw 39, MC_DC39_VALUE
787 +
788 + dc_sw 40, MC_DC40_VALUE
789 + dc_sw 41, MC_DC41_VALUE
790 + dc_sw 42, MC_DC42_VALUE
791 + dc_sw 43, MC_DC43_VALUE
792 + dc_sw 44, MC_DC44_VALUE
793 + dc_sw 45, MC_DC45_VALUE
794 + dc_sw 46, MC_DC46_VALUE
795 +
796 + /* Set start bit of DDR memory controller */
797 + li t2, LTQ_MC_DDR_DC03_MC_START
798 + sw t2, LTQ_MC_DDR_DC_OFFSET(3)(t1)
799 +
800 + /* Wait until DLL has locked and core is ready for data transfers */
801 +wait_ready:
802 + lw t2, LTQ_MC_GEN_STAT(t0)
803 + li t3, LTQ_MC_GEN_STAT_DLCK_PWRON
804 + and t2, t3
805 + bne t2, t3, wait_ready
806 +
807 +finished:
808 + jr ra
809 +
810 + END(ltq_mem_init)
811 --- /dev/null
812 +++ b/arch/mips/cpu/mips32/danube/pmu.c
813 @@ -0,0 +1,117 @@
814 +/*
815 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
816 + *
817 + * SPDX-License-Identifier: GPL-2.0+
818 + */
819 +
820 +#include <common.h>
821 +#include <asm/lantiq/io.h>
822 +#include <asm/lantiq/pm.h>
823 +#include <asm/arch/soc.h>
824 +
825 +#define LTQ_PMU_PWDCR_RESERVED 0xFD0C001C
826 +
827 +#define LTQ_PMU_PWDCR_TDM (1 << 25)
828 +#define LTQ_PMU_PWDCR_PPE_ENET0 (1 << 23)
829 +#define LTQ_PMU_PWDCR_PPE_ENET1 (1 << 22)
830 +#define LTQ_PMU_PWDCR_PPE_TC (1 << 21)
831 +#define LTQ_PMU_PWDCR_DEU (1 << 20)
832 +#define LTQ_PMU_PWDCR_UART1 (1 << 17)
833 +#define LTQ_PMU_PWDCR_SDIO (1 << 16)
834 +#define LTQ_PMU_PWDCR_AHB (1 << 15)
835 +#define LTQ_PMU_PWDCR_FPI0 (1 << 14)
836 +#define LTQ_PMU_PWDCR_PPE (1 << 13)
837 +#define LTQ_PMU_PWDCR_GPTC (1 << 12)
838 +#define LTQ_PMU_PWDCR_LEDC (1 << 11)
839 +#define LTQ_PMU_PWDCR_EBU (1 << 10)
840 +#define LTQ_PMU_PWDCR_DSL (1 << 9)
841 +#define LTQ_PMU_PWDCR_SPI (1 << 8)
842 +#define LTQ_PMU_PWDCR_UART0 (1 << 7)
843 +#define LTQ_PMU_PWDCR_USB (1 << 6)
844 +#define LTQ_PMU_PWDCR_DMA (1 << 5)
845 +#define LTQ_PMU_PWDCR_FPI1 (1 << 1)
846 +#define LTQ_PMU_PWDCR_USB_PHY (1 << 0)
847 +
848 +struct ltq_pmu_regs {
849 + u32 rsvd0[7];
850 + u32 pwdcr;
851 + u32 sr;
852 + u32 pwdcr1;
853 + u32 sr1;
854 +};
855 +
856 +static struct ltq_pmu_regs *ltq_pmu_regs =
857 + (struct ltq_pmu_regs *) CKSEG1ADDR(LTQ_PMU_BASE);
858 +
859 +u32 ltq_pm_map(enum ltq_pm_modules module)
860 +{
861 + u32 val;
862 +
863 + switch (module) {
864 + case LTQ_PM_CORE:
865 + val = LTQ_PMU_PWDCR_UART1 | LTQ_PMU_PWDCR_FPI0 |
866 + LTQ_PMU_PWDCR_LEDC | LTQ_PMU_PWDCR_EBU;
867 + break;
868 + case LTQ_PM_DMA:
869 + val = LTQ_PMU_PWDCR_DMA;
870 + break;
871 + case LTQ_PM_ETH:
872 + val = LTQ_PMU_PWDCR_PPE_ENET0 | LTQ_PMU_PWDCR_PPE_TC |
873 + LTQ_PMU_PWDCR_PPE;
874 + break;
875 + case LTQ_PM_SPI:
876 + val = LTQ_PMU_PWDCR_SPI;
877 + break;
878 + default:
879 + val = 0;
880 + break;
881 + }
882 +
883 + return val;
884 +}
885 +
886 +int ltq_pm_enable(enum ltq_pm_modules module)
887 +{
888 + const unsigned long timeout = 1000;
889 + unsigned long timebase;
890 + u32 sr, val;
891 +
892 + val = ltq_pm_map(module);
893 + if (unlikely(!val))
894 + return 1;
895 +
896 + ltq_clrbits(&ltq_pmu_regs->pwdcr, val);
897 +
898 + timebase = get_timer(0);
899 +
900 + do {
901 + sr = ltq_readl(&ltq_pmu_regs->sr);
902 + if (~sr & val)
903 + return 0;
904 + } while (get_timer(timebase) < timeout);
905 +
906 + return 1;
907 +}
908 +
909 +int ltq_pm_disable(enum ltq_pm_modules module)
910 +{
911 + u32 val;
912 +
913 + val = ltq_pm_map(module);
914 + if (unlikely(!val))
915 + return 1;
916 +
917 + ltq_setbits(&ltq_pmu_regs->pwdcr, val);
918 +
919 + return 0;
920 +}
921 +
922 +void ltq_pmu_init(void)
923 +{
924 + u32 set, clr;
925 +
926 + clr = ltq_pm_map(LTQ_PM_CORE);
927 + set = ~(LTQ_PMU_PWDCR_RESERVED | clr);
928 +
929 + ltq_clrsetbits(&ltq_pmu_regs->pwdcr, clr, set);
930 +}
931 --- /dev/null
932 +++ b/arch/mips/cpu/mips32/danube/rcu.c
933 @@ -0,0 +1,125 @@
934 +/*
935 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
936 + *
937 + * SPDX-License-Identifier: GPL-2.0+
938 + */
939 +
940 +#include <common.h>
941 +#include <asm/lantiq/io.h>
942 +#include <asm/lantiq/reset.h>
943 +#include <asm/lantiq/cpu.h>
944 +#include <asm/arch/soc.h>
945 +
946 +#define LTQ_RCU_RD_SRST (1 << 30) /* Global SW Reset */
947 +#define LTQ_RCU_RD_MC (1 << 14) /* Memory Controller */
948 +#define LTQ_RCU_RD_PCI (1 << 13) /* PCI core */
949 +#define LTQ_RCU_RD_DFE_AFE (1 << 12) /* Voice DFE/AFE */
950 +#define LTQ_RCU_RD_DSL_AFE (1 << 11) /* DSL AFE */
951 +#define LTQ_RCU_RD_SDIO (1 << 10) /* SDIO core */
952 +#define LTQ_RCU_RD_DMA (1 << 9) /* DMA core */
953 +#define LTQ_RCU_RD_PPE (1 << 8) /* PPE core */
954 +#define LTQ_RCU_RD_ARC_DFE (1 << 7) /* ARC/DFE core */
955 +#define LTQ_RCU_RD_AHB (1 << 6) /* AHB bus */
956 +#define LTQ_RCU_RD_ENET_MAC1 (1 << 5) /* Ethernet MAC1 */
957 +#define LTQ_RCU_RD_USB (1 << 4) /* USB and Phy core */
958 +#define LTQ_RCU_RD_CPU1 (1 << 3) /* CPU1 subsystem */
959 +#define LTQ_RCU_RD_FPI (1 << 2) /* FPI bus */
960 +#define LTQ_RCU_RD_CPU0 (1 << 1) /* CPU0 subsystem */
961 +#define LTQ_RCU_RD_HRST (1 << 0) /* HW reset via HRST pin */
962 +
963 +#define LTQ_RCU_STAT_BOOT_SHIFT 18
964 +#define LTQ_RCU_STAT_BOOT_MASK (0x7 << LTQ_RCU_STAT_BOOT_SHIFT)
965 +
966 +struct ltq_rcu_regs {
967 + u32 rsvd0[4];
968 + u32 req; /* Reset request */
969 + u32 stat; /* Reset status */
970 + u32 usb_cfg; /* USB configure */
971 + u32 rsvd1[2];
972 + u32 pci_rdy; /* PCI boot ready */
973 +};
974 +
975 +static struct ltq_rcu_regs *ltq_rcu_regs =
976 + (struct ltq_rcu_regs *) CKSEG1ADDR(LTQ_RCU_BASE);
977 +
978 +u32 ltq_reset_map(enum ltq_reset_modules module)
979 +{
980 + u32 val;
981 +
982 + switch (module) {
983 + case LTQ_RESET_CORE:
984 + case LTQ_RESET_SOFT:
985 + val = LTQ_RCU_RD_SRST | LTQ_RCU_RD_CPU1;
986 + break;
987 + case LTQ_RESET_DMA:
988 + val = LTQ_RCU_RD_DMA;
989 + break;
990 + case LTQ_RESET_ETH:
991 + val = LTQ_RCU_RD_PPE;
992 + break;
993 + case LTQ_RESET_HARD:
994 + val = LTQ_RCU_RD_HRST;
995 + break;
996 + default:
997 + val = 0;
998 + break;
999 + }
1000 +
1001 + return val;
1002 +}
1003 +
1004 +int ltq_reset_activate(enum ltq_reset_modules module)
1005 +{
1006 + u32 val;
1007 +
1008 + val = ltq_reset_map(module);
1009 + if (unlikely(!val))
1010 + return 1;
1011 +
1012 + ltq_setbits(&ltq_rcu_regs->req, val);
1013 +
1014 + return 0;
1015 +}
1016 +
1017 +int ltq_reset_deactivate(enum ltq_reset_modules module)
1018 +{
1019 + u32 val;
1020 +
1021 + val = ltq_reset_map(module);
1022 + if (unlikely(!val))
1023 + return 1;
1024 +
1025 + ltq_clrbits(&ltq_rcu_regs->req, val);
1026 +
1027 + return 0;
1028 +}
1029 +
1030 +enum ltq_boot_select ltq_boot_select(void)
1031 +{
1032 + u32 stat;
1033 + unsigned int bootstrap;
1034 +
1035 + stat = ltq_readl(&ltq_rcu_regs->stat);
1036 + bootstrap = (stat & LTQ_RCU_STAT_BOOT_MASK) >> LTQ_RCU_STAT_BOOT_SHIFT;
1037 +
1038 + switch (bootstrap) {
1039 + case 0:
1040 + return BOOT_NOR_NO_BOOTROM;
1041 + case 1:
1042 + return BOOT_NOR;
1043 + case 2:
1044 + return BOOT_MII0;
1045 + case 3:
1046 + return BOOT_PCI;
1047 + case 4:
1048 + return BOOT_UART;
1049 + case 5:
1050 + return BOOT_SPI;
1051 + case 6:
1052 + return BOOT_NAND;
1053 + case 7:
1054 + return BOOT_RMII0;
1055 + default:
1056 + return BOOT_UNKNOWN;
1057 + }
1058 +}
1059 --- /dev/null
1060 +++ b/arch/mips/cpu/mips32/lantiq-common/Makefile
1061 @@ -0,0 +1,34 @@
1062 +#
1063 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
1064 +#
1065 +# SPDX-License-Identifier: GPL-2.0+
1066 +#
1067 +
1068 +include $(TOPDIR)/config.mk
1069 +
1070 +LIB = $(obj)liblantiq-common.o
1071 +
1072 +START = start.o
1073 +COBJS-y = cpu.o pmu.o
1074 +COBJS-$(CONFIG_SPL_BUILD) += spl.o
1075 +SOBJS-y = lowlevel_init.o
1076 +
1077 +COBJS := $(COBJS-y)
1078 +SOBJS := $(SOBJS-y)
1079 +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
1080 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
1081 +START := $(addprefix $(obj),$(START))
1082 +
1083 +all: $(LIB)
1084 +
1085 +$(LIB): $(obj).depend $(OBJS)
1086 + $(call cmd_link_o_target, $(OBJS))
1087 +
1088 +#########################################################################
1089 +
1090 +# defines $(obj).depend target
1091 +include $(SRCTREE)/rules.mk
1092 +
1093 +sinclude $(obj).depend
1094 +
1095 +#########################################################################
1096 --- /dev/null
1097 +++ b/arch/mips/cpu/mips32/lantiq-common/cpu.c
1098 @@ -0,0 +1,59 @@
1099 +/*
1100 + * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1101 + *
1102 + * SPDX-License-Identifier: GPL-2.0+
1103 + */
1104 +
1105 +#include <common.h>
1106 +#include <asm/lantiq/chipid.h>
1107 +#include <asm/lantiq/clk.h>
1108 +#include <asm/lantiq/reset.h>
1109 +#include <asm/lantiq/cpu.h>
1110 +
1111 +static const char ltq_bootsel_strings[][16] = {
1112 + "NOR",
1113 + "NOR w/o BootROM",
1114 + "UART",
1115 + "UART w/o EEPROM",
1116 + "SPI",
1117 + "NAND",
1118 + "PCI",
1119 + "MII0",
1120 + "RMII0",
1121 + "RGMII1",
1122 + "unknown",
1123 +};
1124 +
1125 +const char *ltq_boot_select_str(void)
1126 +{ enum ltq_boot_select bootsel = ltq_boot_select();
1127 +
1128 + if (bootsel > BOOT_UNKNOWN)
1129 + bootsel = BOOT_UNKNOWN;
1130 +
1131 + return ltq_bootsel_strings[bootsel];
1132 +}
1133 +
1134 +void ltq_chip_print_info(void)
1135 +{
1136 + char buf[32];
1137 +
1138 + printf("SoC: Lantiq %s v1.%u\n", ltq_chip_partnum_str(),
1139 + ltq_chip_version_get());
1140 + printf("CPU: %s MHz\n", strmhz(buf, ltq_get_cpu_clock()));
1141 + printf("IO: %s MHz\n", strmhz(buf, ltq_get_io_region_clock()));
1142 + printf("BUS: %s MHz\n", strmhz(buf, ltq_get_bus_clock()));
1143 + printf("BOOT: %s\n", ltq_boot_select_str());
1144 +}
1145 +
1146 +int arch_cpu_init(void)
1147 +{
1148 + ltq_pmu_init();
1149 + ltq_ebu_init();
1150 +
1151 + return 0;
1152 +}
1153 +
1154 +void _machine_restart(void)
1155 +{
1156 + ltq_reset_activate(LTQ_RESET_CORE);
1157 +}
1158 --- /dev/null
1159 +++ b/arch/mips/cpu/mips32/lantiq-common/lowlevel_init.S
1160 @@ -0,0 +1,20 @@
1161 +/*
1162 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1163 + *
1164 + * SPDX-License-Identifier: GPL-2.0+
1165 + */
1166 +
1167 +#include <asm/asm.h>
1168 +#include <asm/regdef.h>
1169 +
1170 +NESTED(lowlevel_init, 0, ra)
1171 + move t8, ra
1172 +
1173 + la t7, ltq_cgu_init
1174 + jalr t7
1175 +
1176 + la t7, ltq_mem_init
1177 + jalr t7
1178 +
1179 + jr t8
1180 + END(lowlevel_init)
1181 --- /dev/null
1182 +++ b/arch/mips/cpu/mips32/lantiq-common/pmu.c
1183 @@ -0,0 +1,9 @@
1184 +/*
1185 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1186 + *
1187 + * SPDX-License-Identifier: GPL-2.0+
1188 + */
1189 +
1190 +#include <common.h>
1191 +#include <asm/lantiq/pm.h>
1192 +
1193 --- /dev/null
1194 +++ b/arch/mips/cpu/mips32/lantiq-common/spl.c
1195 @@ -0,0 +1,403 @@
1196 +/*
1197 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1198 + *
1199 + * SPDX-License-Identifier: GPL-2.0+
1200 + */
1201 +
1202 +#include <common.h>
1203 +#include <image.h>
1204 +#include <version.h>
1205 +#include <spi_flash.h>
1206 +#include <linux/compiler.h>
1207 +#include <lzma/LzmaDec.h>
1208 +#include <linux/lzo.h>
1209 +#include <asm/mipsregs.h>
1210 +
1211 +#if defined(CONFIG_LTQ_SPL_CONSOLE)
1212 +#define spl_has_console 1
1213 +
1214 +#if defined(CONFIG_LTQ_SPL_DEBUG)
1215 +#define spl_has_debug 1
1216 +#else
1217 +#define spl_has_debug 0
1218 +#endif
1219 +
1220 +#else
1221 +#define spl_has_console 0
1222 +#define spl_has_debug 0
1223 +#endif
1224 +
1225 +#define spl_debug(fmt, args...) \
1226 + do { \
1227 + if (spl_has_debug) \
1228 + printf(fmt, ##args); \
1229 + } while (0)
1230 +
1231 +#define spl_puts(msg) \
1232 + do { \
1233 + if (spl_has_console) \
1234 + puts(msg); \
1235 + } while (0)
1236 +
1237 +#if defined(CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH) && defined(CONFIG_SYS_BOOT_SFSPL)
1238 +#define spl_boot_spi_flash 1
1239 +#else
1240 +#define spl_boot_spi_flash 0
1241 +#ifndef CONFIG_SPL_SPI_BUS
1242 +#define CONFIG_SPL_SPI_BUS 0
1243 +#endif
1244 +#ifndef CONFIG_SPL_SPI_CS
1245 +#define CONFIG_SPL_SPI_CS 0
1246 +#endif
1247 +#ifndef CONFIG_SPL_SPI_MAX_HZ
1248 +#define CONFIG_SPL_SPI_MAX_HZ 0
1249 +#endif
1250 +#ifndef CONFIG_SPL_SPI_MODE
1251 +#define CONFIG_SPL_SPI_MODE 0
1252 +#endif
1253 +#endif
1254 +
1255 +#if defined(CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH) && defined(CONFIG_SYS_BOOT_NORSPL)
1256 +#define spl_boot_nor_flash 1
1257 +#else
1258 +#define spl_boot_nor_flash 0
1259 +#endif
1260 +
1261 +#define spl_sync() __asm__ __volatile__("sync");
1262 +
1263 +struct spl_image {
1264 + ulong data_addr;
1265 + ulong entry_addr;
1266 + ulong data_size;
1267 + ulong entry_size;
1268 + ulong data_crc;
1269 + u8 comp;
1270 +};
1271 +
1272 +DECLARE_GLOBAL_DATA_PTR;
1273 +
1274 +/* Emulated malloc area needed for LZMA allocator in BSS */
1275 +static u8 *spl_mem_ptr __maybe_unused;
1276 +static size_t spl_mem_size __maybe_unused;
1277 +
1278 +static int spl_is_comp_lzma(const struct spl_image *spl)
1279 +{
1280 +#if defined(CONFIG_LTQ_SPL_COMP_LZMA)
1281 + return spl->comp == IH_COMP_LZMA;
1282 +#else
1283 + return 0;
1284 +#endif
1285 +}
1286 +
1287 +static int spl_is_comp_lzo(const struct spl_image *spl)
1288 +{
1289 +#if defined(CONFIG_LTQ_SPL_COMP_LZO)
1290 + return spl->comp == IH_COMP_LZO;
1291 +#else
1292 + return 0;
1293 +#endif
1294 +}
1295 +
1296 +static int spl_is_compressed(const struct spl_image *spl)
1297 +{
1298 + if (spl_is_comp_lzma(spl))
1299 + return 1;
1300 +
1301 + if (spl_is_comp_lzo(spl))
1302 + return 1;
1303 +
1304 + return 0;
1305 +}
1306 +
1307 +static void spl_console_init(void)
1308 +{
1309 + if (!spl_has_console)
1310 + return;
1311 +
1312 + gd->flags |= GD_FLG_RELOC;
1313 + gd->baudrate = CONFIG_BAUDRATE;
1314 +
1315 + serial_init();
1316 +
1317 + gd->have_console = 1;
1318 +
1319 + spl_puts("\nU-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
1320 + U_BOOT_TIME ")\n");
1321 +}
1322 +
1323 +static int spl_parse_image(const image_header_t *hdr, struct spl_image *spl)
1324 +{
1325 + spl_puts("SPL: checking U-Boot image\n");
1326 +
1327 + if (!image_check_magic(hdr)) {
1328 + spl_puts("SPL: invalid magic\n");
1329 + return -1;
1330 + }
1331 +
1332 + if (!image_check_hcrc(hdr)) {
1333 + spl_puts("SPL: invalid header CRC\n");
1334 + return -1;
1335 + }
1336 +
1337 + spl->data_addr += image_get_header_size();
1338 + spl->entry_addr = image_get_load(hdr);
1339 + spl->data_size = image_get_data_size(hdr);
1340 + spl->data_crc = image_get_dcrc(hdr);
1341 + spl->comp = image_get_comp(hdr);
1342 +
1343 + spl_debug("SPL: data %08lx, size %lu, entry %08lx, comp %u\n",
1344 + spl->data_addr, spl->data_size, spl->entry_addr, spl->comp);
1345 +
1346 + return 0;
1347 +}
1348 +
1349 +static int spl_check_data(const struct spl_image *spl, ulong loadaddr)
1350 +{
1351 + ulong dcrc = crc32(0, (unsigned char *)loadaddr, spl->data_size);
1352 +
1353 + if (dcrc != spl->data_crc) {
1354 + spl_puts("SPL: invalid data CRC\n");
1355 + return 0;
1356 + }
1357 +
1358 + return 1;
1359 +}
1360 +
1361 +static void *spl_lzma_alloc(void *p, size_t size)
1362 +{
1363 + u8 *ret;
1364 +
1365 + if (size > spl_mem_size)
1366 + return NULL;
1367 +
1368 + ret = spl_mem_ptr;
1369 + spl_mem_ptr += size;
1370 + spl_mem_size -= size;
1371 +
1372 + return ret;
1373 +}
1374 +
1375 +static void spl_lzma_free(void *p, void *addr)
1376 +{
1377 +}
1378 +
1379 +static int spl_copy_image(struct spl_image *spl)
1380 +{
1381 + spl_puts("SPL: copying U-Boot to RAM\n");
1382 +
1383 + memcpy((void *) spl->entry_addr, (const void *) spl->data_addr,
1384 + spl->data_size);
1385 +
1386 + spl->entry_size = spl->data_size;
1387 +
1388 + return 0;
1389 +}
1390 +
1391 +static int spl_uncompress_lzma(struct spl_image *spl, unsigned long loadaddr)
1392 +{
1393 + SRes res;
1394 + const Byte *prop = (const Byte *) loadaddr;
1395 + const Byte *src = (const Byte *) loadaddr + LZMA_PROPS_SIZE +
1396 + sizeof(uint64_t);
1397 + Byte *dest = (Byte *) spl->entry_addr;
1398 + SizeT dest_len = 0xFFFFFFFF;
1399 + SizeT src_len = spl->data_size - LZMA_PROPS_SIZE;
1400 + ELzmaStatus status = 0;
1401 + ISzAlloc alloc;
1402 +
1403 + spl_puts("SPL: decompressing U-Boot with LZMA\n");
1404 +
1405 + alloc.Alloc = spl_lzma_alloc;
1406 + alloc.Free = spl_lzma_free;
1407 + spl_mem_ptr = (u8 *) CONFIG_SPL_MALLOC_BASE;
1408 + spl_mem_size = CONFIG_SPL_MALLOC_MAX_SIZE;
1409 +
1410 + res = LzmaDecode(dest, &dest_len, src, &src_len, prop, LZMA_PROPS_SIZE,
1411 + LZMA_FINISH_ANY, &status, &alloc);
1412 + if (res != SZ_OK)
1413 + return 1;
1414 +
1415 + spl->entry_size = dest_len;
1416 +
1417 + return 0;
1418 +}
1419 +
1420 +static int spl_uncompress_lzo(struct spl_image *spl, unsigned long loadaddr)
1421 +{
1422 + size_t len;
1423 + int ret;
1424 +
1425 + spl_puts("SPL: decompressing U-Boot with LZO\n");
1426 +
1427 + ret = lzop_decompress(
1428 + (const unsigned char*) loadaddr, spl->data_size,
1429 + (unsigned char *) spl->entry_addr, &len);
1430 +
1431 + spl->entry_size = len;
1432 +
1433 + return ret;
1434 +}
1435 +
1436 +static int spl_uncompress(struct spl_image *spl, unsigned long loadaddr)
1437 +{
1438 + int ret;
1439 +
1440 + if (spl_is_comp_lzma(spl))
1441 + ret = spl_uncompress_lzma(spl, loadaddr);
1442 + else if (spl_is_comp_lzo(spl))
1443 + ret = spl_uncompress_lzo(spl, loadaddr);
1444 + else
1445 + ret = 1;
1446 +
1447 + return ret;
1448 +}
1449 +
1450 +static int spl_load_spi_flash(struct spl_image *spl)
1451 +{
1452 + struct spi_flash sf = { 0 };
1453 + image_header_t hdr;
1454 + int ret;
1455 + unsigned long loadaddr;
1456 +
1457 + /*
1458 + * Image format:
1459 + *
1460 + * - 12 byte non-volatile bootstrap header
1461 + * - SPL binary
1462 + * - 12 byte non-volatile bootstrap header
1463 + * - 64 byte U-Boot mkimage header
1464 + * - U-Boot binary
1465 + */
1466 + spl->data_addr = image_copy_end() - CONFIG_SPL_TEXT_BASE + 24;
1467 +
1468 + spl_puts("SPL: probing SPI flash\n");
1469 +
1470 + spi_init();
1471 + ret = spl_spi_flash_probe(&sf);
1472 + if (ret)
1473 + return ret;
1474 +
1475 + spl_debug("SPL: reading image header at offset %lx\n", spl->data_addr);
1476 +
1477 + ret = spi_flash_read(&sf, spl->data_addr, sizeof(hdr), &hdr);
1478 + if (ret)
1479 + return ret;
1480 +
1481 + spl_debug("SPL: checking image header at offset %lx\n", spl->data_addr);
1482 +
1483 + ret = spl_parse_image(&hdr, spl);
1484 + if (ret)
1485 + return ret;
1486 +
1487 + if (spl_is_compressed(spl))
1488 + loadaddr = CONFIG_LOADADDR;
1489 + else
1490 + loadaddr = spl->entry_addr;
1491 +
1492 + spl_puts("SPL: loading U-Boot to RAM\n");
1493 +
1494 + ret = spi_flash_read(&sf, spl->data_addr, spl->data_size,
1495 + (void *) loadaddr);
1496 +
1497 + if (!spl_check_data(spl, loadaddr))
1498 + return -1;
1499 +
1500 + if (spl_is_compressed(spl))
1501 + ret = spl_uncompress(spl, loadaddr);
1502 +
1503 + return ret;
1504 +}
1505 +
1506 +static int spl_load_nor_flash(struct spl_image *spl)
1507 +{
1508 + const image_header_t *hdr;
1509 + int ret;
1510 +
1511 + /*
1512 + * Image format:
1513 + *
1514 + * - SPL binary
1515 + * - 64 byte U-Boot mkimage header
1516 + * - U-Boot binary
1517 + */
1518 + spl->data_addr = image_copy_end();
1519 + hdr = (const image_header_t *) image_copy_end();
1520 +
1521 + spl_debug("SPL: checking image header at address %p\n", hdr);
1522 +
1523 + ret = spl_parse_image(hdr, spl);
1524 + if (ret)
1525 + return ret;
1526 +
1527 + if (spl_is_compressed(spl))
1528 + ret = spl_uncompress(spl, spl->data_addr);
1529 + else
1530 + ret = spl_copy_image(spl);
1531 +
1532 + return ret;
1533 +}
1534 +
1535 +static int spl_load(struct spl_image *spl)
1536 +{
1537 + int ret;
1538 +
1539 + if (spl_boot_spi_flash)
1540 + ret = spl_load_spi_flash(spl);
1541 + else if (spl_boot_nor_flash)
1542 + ret = spl_load_nor_flash(spl);
1543 + else
1544 + ret = 1;
1545 +
1546 + return ret;
1547 +}
1548 +
1549 +void __noreturn spl_lantiq_init(void)
1550 +{
1551 + void (*uboot)(void) __noreturn;
1552 + struct spl_image spl;
1553 + gd_t gd_data;
1554 + int ret;
1555 +
1556 + gd = &gd_data;
1557 + barrier();
1558 + memset((void *)gd, 0, sizeof(gd_t));
1559 +
1560 + spl_console_init();
1561 +
1562 + spl_debug("SPL: initializing\n");
1563 +
1564 +#if 0
1565 + spl_debug("CP0_CONFIG: %08x\n", read_c0_config());
1566 + spl_debug("CP0_CONFIG1: %08x\n", read_c0_config1());
1567 + spl_debug("CP0_CONFIG2: %08x\n", read_c0_config2());
1568 + spl_debug("CP0_CONFIG3: %08x\n", read_c0_config3());
1569 + spl_debug("CP0_CONFIG6: %08x\n", read_c0_config6());
1570 + spl_debug("CP0_CONFIG7: %08x\n", read_c0_config7());
1571 + spl_debug("CP0_STATUS: %08x\n", read_c0_status());
1572 + spl_debug("CP0_PRID: %08x\n", read_c0_prid());
1573 +#endif
1574 +
1575 + board_early_init_f();
1576 + timer_init();
1577 +
1578 + memset(&spl, 0, sizeof(spl));
1579 +
1580 + ret = spl_load(&spl);
1581 + if (ret)
1582 + goto hang;
1583 +
1584 + spl_debug("SPL: U-Boot entry %08lx\n", spl.entry_addr);
1585 + spl_puts("SPL: jumping to U-Boot\n");
1586 +
1587 + flush_cache(spl.entry_addr, spl.entry_size);
1588 + spl_sync();
1589 +
1590 + uboot = (void *) spl.entry_addr;
1591 + uboot();
1592 +
1593 +hang:
1594 + spl_puts("SPL: cannot start U-Boot\n");
1595 +
1596 + for (;;)
1597 + ;
1598 +}
1599 --- /dev/null
1600 +++ b/arch/mips/cpu/mips32/lantiq-common/start.S
1601 @@ -0,0 +1,143 @@
1602 +/*
1603 + * Copyright (C) 2010 Lantiq Deutschland GmbH
1604 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1605 + *
1606 + * SPDX-License-Identifier: GPL-2.0+
1607 + */
1608 +
1609 +#include <config.h>
1610 +#include <asm/regdef.h>
1611 +#include <asm/mipsregs.h>
1612 +
1613 +#define S_PRIdCoID 16 /* Company ID (R) */
1614 +#define M_PRIdCoID (0xff << S_PRIdCoID)
1615 +#define S_PRIdImp 8 /* Implementation ID (R) */
1616 +#define M_PRIdImp (0xff << S_PRIdImp)
1617 +
1618 +#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */
1619 +#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */
1620 +#define K_CacheAttrU 2 /* Uncached */
1621 +#define K_CacheAttrC 3 /* Cacheable */
1622 +#define K_CacheAttrCN 3 /* Cacheable, non-coherent */
1623 +#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */
1624 +#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */
1625 +#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */
1626 +#define K_CacheAttrUA 7 /* Uncached accelerated */
1627 +
1628 +#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */
1629 +#define M_ConfigK23 (0x7 << S_ConfigK23)
1630 +#define W_ConfigK23 3
1631 +#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */
1632 +#define M_ConfigKU (0x7 << S_ConfigKU)
1633 +#define W_ConfigKU 3
1634 +
1635 +#define S_ConfigMM 18 /* Merge mode (implementation specific) */
1636 +#define M_ConfigMM (0x1 << S_ConfigMM)
1637 +
1638 +#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */
1639 +#define M_StatusBEV (0x1 << S_StatusBEV)
1640 +
1641 +#define S_StatusFR 26 /* Enable 64-bit FPRs (R/W) */
1642 +#define M_StatusFR (0x1 << S_StatusFR)
1643 +
1644 +#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */
1645 +#define M_ConfigK0 (0x7 << S_ConfigK0)
1646 +
1647 +#define CONFIG0_MIPS32_64_MSK 0x8000ffff
1648 +#define STATUS_MIPS32_64_MSK 0xfffcffff
1649 +
1650 +#define STATUS_MIPS24K 0
1651 +#define CONFIG0_MIPS24K ((K_CacheAttrCN << S_ConfigK23) |\
1652 + (K_CacheAttrCN << S_ConfigKU) |\
1653 + (M_ConfigMM))
1654 +
1655 +#define STATUS_MIPS34K 0
1656 +#define CONFIG0_MIPS34K ((K_CacheAttrCN << S_ConfigK23) |\
1657 + (K_CacheAttrCN << S_ConfigKU) |\
1658 + (M_ConfigMM))
1659 +
1660 +#define STATUS_MIPS32_64 (M_StatusBEV | M_StatusFR)
1661 +#define CONFIG0_MIPS32_64 (K_CacheAttrCN << S_ConfigK0)
1662 +
1663 +#ifdef CONFIG_SOC_XWAY_DANUBE
1664 +#define CONFIG0_LANTIQ (CONFIG0_MIPS24K | CONFIG0_MIPS32_64)
1665 +#define STATUS_LANTIQ (STATUS_MIPS24K | STATUS_MIPS32_64)
1666 +#endif
1667 +
1668 +#ifdef CONFIG_SOC_XWAY_VRX200
1669 +#define CONFIG0_LANTIQ (CONFIG0_MIPS34K | CONFIG0_MIPS32_64)
1670 +#define STATUS_LANTIQ (STATUS_MIPS34K | STATUS_MIPS32_64)
1671 +#endif
1672 +
1673 +
1674 + .set noreorder
1675 +
1676 + .globl _start
1677 + .text
1678 +_start:
1679 + /* Entry point */
1680 + b main
1681 + nop
1682 +
1683 + /* Lantiq SoC Boot config word */
1684 + .org 0x10
1685 +#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
1686 + .word CONFIG_SYS_XWAY_EBU_BOOTCFG
1687 +#else
1688 + .word 0
1689 +#endif
1690 + .word 0
1691 +
1692 + .align 4
1693 +main:
1694 +
1695 + /* Init Timer */
1696 + mtc0 zero, CP0_COUNT
1697 + mtc0 zero, CP0_COMPARE
1698 +
1699 + /* Setup MIPS24K/MIPS34K specifics (implementation dependent fields) */
1700 + mfc0 t0, CP0_CONFIG
1701 + li t1, CONFIG0_MIPS32_64_MSK
1702 + and t0, t1
1703 + li t1, CONFIG0_LANTIQ
1704 + or t0, t1
1705 + mtc0 t0, CP0_CONFIG
1706 +
1707 + mfc0 t0, CP0_STATUS
1708 + li t1, STATUS_MIPS32_64_MSK
1709 + and t0, t1
1710 + li t1, STATUS_LANTIQ
1711 + or t0, t1
1712 + mtc0 t0, CP0_STATUS
1713 +
1714 + /* Initialize CGU */
1715 + la t9, ltq_cgu_init
1716 + jalr t9
1717 + nop
1718 +
1719 + /* Initialize memory controller */
1720 + la t9, ltq_mem_init
1721 + jalr t9
1722 + nop
1723 +
1724 + /* Initialize caches... */
1725 + la t9, mips_cache_reset
1726 + jalr t9
1727 + nop
1728 +
1729 + /* Clear BSS */
1730 + la t1, __bss_start
1731 + la t2, __bss_end
1732 + sub t1, 4
1733 +1:
1734 + addi t1, 4
1735 + bltl t1, t2, 1b
1736 + sw zero, 0(t1)
1737 +
1738 + /* Setup stack pointer and force alignment on a 16 byte boundary */
1739 + li t0, (CONFIG_SPL_STACK_BASE & ~0xF)
1740 + la sp, 0(t0)
1741 +
1742 + la t9, spl_lantiq_init
1743 + jr t9
1744 + nop
1745 --- /dev/null
1746 +++ b/arch/mips/cpu/mips32/lantiq-common/u-boot-spl.lds
1747 @@ -0,0 +1,48 @@
1748 +/*
1749 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1750 + *
1751 + * SPDX-License-Identifier: GPL-2.0+
1752 + */
1753 +
1754 +MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \
1755 + LENGTH = CONFIG_SPL_MAX_SIZE }
1756 +MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_BASE, \
1757 + LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
1758 +
1759 +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
1760 +OUTPUT_ARCH(mips)
1761 +ENTRY(_start)
1762 +SECTIONS
1763 +{
1764 + . = ALIGN(4);
1765 + .text : {
1766 + *(.text*)
1767 + } > .spl_mem
1768 +
1769 + . = ALIGN(4);
1770 + .rodata : {
1771 + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
1772 + } > .spl_mem
1773 +
1774 + . = ALIGN(4);
1775 + .data : {
1776 + *(SORT_BY_ALIGNMENT(.data*))
1777 + *(SORT_BY_ALIGNMENT(.sdata*))
1778 + } > .spl_mem
1779 +
1780 + . = ALIGN(4);
1781 + __image_copy_end = .;
1782 + uboot_end_data = .;
1783 +
1784 + .bss : {
1785 + __bss_start = .;
1786 + *(.bss*)
1787 + *(.sbss*)
1788 + . = ALIGN(4);
1789 + __bss_end = .;
1790 + } > .bss_mem
1791 +
1792 + . = ALIGN(4);
1793 + __end = .;
1794 + uboot_end = .;
1795 +}
1796 --- a/arch/mips/cpu/mips32/start.S
1797 +++ b/arch/mips/cpu/mips32/start.S
1798 @@ -105,7 +105,7 @@ reset:
1799 mtc0 zero, CP0_COUNT
1800 mtc0 zero, CP0_COMPARE
1801
1802 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT
1803 +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_SYS_DISABLE_CACHE)
1804 /* CONFIG0 register */
1805 li t0, CONF_CM_UNCACHED
1806 mtc0 t0, CP0_CONFIG
1807 --- /dev/null
1808 +++ b/arch/mips/cpu/mips32/vrx200/Makefile
1809 @@ -0,0 +1,32 @@
1810 +#
1811 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
1812 +#
1813 +# SPDX-License-Identifier: GPL-2.0+
1814 +#
1815 +
1816 +include $(TOPDIR)/config.mk
1817 +
1818 +LIB = $(obj)lib$(SOC).o
1819 +
1820 +COBJS-y += cgu.o chipid.o dcdc.o ebu.o gphy.o mem.o pmu.o rcu.o
1821 +SOBJS-y += cgu_init.o mem_init.o
1822 +SOBJS-y += gphy_fw.o
1823 +
1824 +COBJS := $(COBJS-y)
1825 +SOBJS := $(SOBJS-y)
1826 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
1827 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
1828 +
1829 +all: $(LIB)
1830 +
1831 +$(LIB): $(obj).depend $(OBJS)
1832 + $(call cmd_link_o_target, $(OBJS))
1833 +
1834 +#########################################################################
1835 +
1836 +# defines $(obj).depend target
1837 +include $(SRCTREE)/rules.mk
1838 +
1839 +sinclude $(obj).depend
1840 +
1841 +#########################################################################
1842 --- /dev/null
1843 +++ b/arch/mips/cpu/mips32/vrx200/cgu.c
1844 @@ -0,0 +1,208 @@
1845 +/*
1846 + * Copyright (C) 2010 Lantiq Deutschland GmbH
1847 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1848 + *
1849 + * SPDX-License-Identifier: GPL-2.0+
1850 + */
1851 +
1852 +#include <common.h>
1853 +#include <asm/arch/soc.h>
1854 +#include <asm/arch/gphy.h>
1855 +#include <asm/lantiq/clk.h>
1856 +#include <asm/lantiq/io.h>
1857 +
1858 +#define LTQ_CGU_PLL1_PLLN_SHIFT 6
1859 +#define LTQ_CGU_PLL1_PLLN_MASK (0x3F << LTQ_CGU_PLL1_PLLN_SHIFT)
1860 +#define LTQ_CGU_PLL1_PLLM_SHIFT 2
1861 +#define LTQ_CGU_PLL1_PLLM_MASK (0xF << LTQ_CGU_PLL1_PLLM_SHIFT)
1862 +#define LTQ_CGU_PLL1_PLLL (1 << 1)
1863 +#define LTQ_CGU_PLL1_PLL_EN 1
1864 +
1865 +#define LTQ_CGU_SYS_OCP_SHIFT 0
1866 +#define LTQ_CGU_SYS_OCP_MASK (0x3 << LTQ_CGU_SYS_OCP_SHIFT)
1867 +#define LTQ_CGU_SYS_CPU_SHIFT 4
1868 +#define LTQ_CGU_SYS_CPU_MASK (0xF << LTQ_CGU_SYS_CPU_SHIFT)
1869 +
1870 +#define LTQ_CGU_UPDATE 1
1871 +
1872 +#define LTQ_CGU_IFCLK_GPHY_SEL_SHIFT 2
1873 +#define LTQ_CGU_IFCLK_GPHY_SEL_MASK (0x7 << LTQ_CGU_IFCLK_GPHY_SEL_SHIFT)
1874 +
1875 +struct ltq_cgu_regs {
1876 + u32 rsvd0;
1877 + u32 pll0_cfg; /* PLL0 config */
1878 + u32 pll1_cfg; /* PLL1 config */
1879 + u32 sys; /* System clock */
1880 + u32 clk_fsr; /* Clock frequency select */
1881 + u32 clk_gsr; /* Clock gating status */
1882 + u32 clk_gcr0; /* Clock gating control 0 */
1883 + u32 clk_gcr1; /* Clock gating control 1 */
1884 + u32 update; /* CGU update control */
1885 + u32 if_clk; /* Interface clock */
1886 + u32 ddr; /* DDR memory control */
1887 + u32 ct1_sr; /* CT status 1 */
1888 + u32 ct_kval; /* CT K value */
1889 + u32 pcm_cr; /* PCM control */
1890 + u32 pci_cr; /* PCI clock control */
1891 + u32 rsvd1;
1892 + u32 gphy1_cfg; /* GPHY1 config */
1893 + u32 gphy0_cfg; /* GPHY0 config */
1894 + u32 rsvd2[6];
1895 + u32 pll2_cfg; /* PLL2 config */
1896 +};
1897 +
1898 +static struct ltq_cgu_regs *ltq_cgu_regs =
1899 + (struct ltq_cgu_regs *) CKSEG1ADDR(LTQ_CGU_BASE);
1900 +
1901 +static inline u32 ltq_cgu_sys_readl(u32 mask, u32 shift)
1902 +{
1903 + return (ltq_readl(&ltq_cgu_regs->sys) & mask) >> shift;
1904 +}
1905 +
1906 +unsigned long ltq_get_io_region_clock(void)
1907 +{
1908 + unsigned int ocp_sel;
1909 + unsigned long clk, cpu_clk;
1910 +
1911 + cpu_clk = ltq_get_cpu_clock();
1912 +
1913 + ocp_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_OCP_MASK,
1914 + LTQ_CGU_SYS_OCP_SHIFT);
1915 +
1916 + switch (ocp_sel) {
1917 + case 0:
1918 + /* OCP ratio 1 */
1919 + clk = cpu_clk;
1920 + break;
1921 + case 2:
1922 + /* OCP ratio 2 */
1923 + clk = cpu_clk / 2;
1924 + break;
1925 + case 3:
1926 + /* OCP ratio 2.5 */
1927 + clk = (cpu_clk * 2) / 5;
1928 + break;
1929 + case 4:
1930 + /* OCP ratio 3 */
1931 + clk = cpu_clk / 3;
1932 + break;
1933 + default:
1934 + clk = 0;
1935 + break;
1936 + }
1937 +
1938 + return clk;
1939 +}
1940 +
1941 +unsigned long ltq_get_cpu_clock(void)
1942 +{
1943 + unsigned int cpu_sel;
1944 + unsigned long clk;
1945 +
1946 + cpu_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_CPU_MASK,
1947 + LTQ_CGU_SYS_CPU_SHIFT);
1948 +
1949 + switch (cpu_sel) {
1950 + case 0:
1951 + clk = CLOCK_600_MHZ;
1952 + break;
1953 + case 1:
1954 + clk = CLOCK_500_MHZ;
1955 + break;
1956 + case 2:
1957 + clk = CLOCK_393_MHZ;
1958 + break;
1959 + case 3:
1960 + clk = CLOCK_333_MHZ;
1961 + break;
1962 + case 5:
1963 + case 6:
1964 + clk = CLOCK_197_MHZ;
1965 + break;
1966 + case 7:
1967 + clk = CLOCK_166_MHZ;
1968 + break;
1969 + case 4:
1970 + case 8:
1971 + case 9:
1972 + clk = CLOCK_125_MHZ;
1973 + break;
1974 + default:
1975 + clk = 0;
1976 + break;
1977 + }
1978 +
1979 + return clk;
1980 +}
1981 +
1982 +unsigned long ltq_get_bus_clock(void)
1983 +{
1984 + return ltq_get_io_region_clock();
1985 +}
1986 +
1987 +void ltq_cgu_gphy_clk_src(enum ltq_gphy_clk clk)
1988 +{
1989 + ltq_clrbits(&ltq_cgu_regs->if_clk, LTQ_CGU_IFCLK_GPHY_SEL_MASK);
1990 + ltq_setbits(&ltq_cgu_regs->if_clk, clk << LTQ_CGU_IFCLK_GPHY_SEL_SHIFT);
1991 +}
1992 +
1993 +static inline int ltq_cgu_pll1_locked(void)
1994 +{
1995 + u32 pll1_cfg = ltq_readl(&ltq_cgu_regs->pll1_cfg);
1996 +
1997 + return pll1_cfg & LTQ_CGU_PLL1_PLLL;
1998 +}
1999 +
2000 +static inline void ltq_cgu_pll1_restart(unsigned m, unsigned n)
2001 +{
2002 + u32 pll1_cfg;
2003 +
2004 + ltq_clrbits(&ltq_cgu_regs->pll1_cfg, LTQ_CGU_PLL1_PLL_EN);
2005 + ltq_setbits(&ltq_cgu_regs->update, LTQ_CGU_UPDATE);
2006 +
2007 + pll1_cfg = ltq_readl(&ltq_cgu_regs->pll1_cfg);
2008 + pll1_cfg &= ~(LTQ_CGU_PLL1_PLLN_MASK | LTQ_CGU_PLL1_PLLM_MASK);
2009 + pll1_cfg |= n << LTQ_CGU_PLL1_PLLN_SHIFT;
2010 + pll1_cfg |= m << LTQ_CGU_PLL1_PLLM_SHIFT;
2011 + pll1_cfg |= LTQ_CGU_PLL1_PLL_EN;
2012 + ltq_writel(&ltq_cgu_regs->pll1_cfg, pll1_cfg);
2013 + ltq_setbits(&ltq_cgu_regs->update, LTQ_CGU_UPDATE);
2014 +
2015 + __udelay(1000);
2016 +}
2017 +
2018 +/*
2019 + * From chapter 9 in errata sheet:
2020 + *
2021 + * Under certain condition, the PLL1 may failed to enter into lock
2022 + * status by hardware default N, M setting.
2023 + *
2024 + * Since system always starts from PLL0, the system software can run
2025 + * and re-program the PLL1 settings.
2026 + */
2027 +static void ltq_cgu_pll1_init(void)
2028 +{
2029 + unsigned i;
2030 + const unsigned pll1_m[] = { 1, 2, 3, 4 };
2031 + const unsigned pll1_n[] = { 21, 32, 43, 54 };
2032 +
2033 + /* Check if PLL1 has locked with hardware default settings */
2034 + if (ltq_cgu_pll1_locked())
2035 + return;
2036 +
2037 + for (i = 0; i < 4; i++) {
2038 + ltq_cgu_pll1_restart(pll1_m[i], pll1_n[i]);
2039 +
2040 + if (ltq_cgu_pll1_locked())
2041 + goto done;
2042 + }
2043 +
2044 +done:
2045 + /* Restart with hardware default values M=5, N=64 */
2046 + ltq_cgu_pll1_restart(5, 64);
2047 +}
2048 +
2049 +void ltq_pll_init(void)
2050 +{
2051 + ltq_cgu_pll1_init();
2052 +}
2053 --- /dev/null
2054 +++ b/arch/mips/cpu/mips32/vrx200/cgu_init.S
2055 @@ -0,0 +1,119 @@
2056 +/*
2057 + * Copyright (C) 2010 Lantiq Deutschland GmbH
2058 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2059 + *
2060 + * SPDX-License-Identifier: GPL-2.0+
2061 + */
2062 +
2063 +#include <config.h>
2064 +#include <asm/asm.h>
2065 +#include <asm/regdef.h>
2066 +#include <asm/addrspace.h>
2067 +#include <asm/arch/soc.h>
2068 +
2069 +/* RCU module register */
2070 +#define LTQ_RCU_RST_REQ 0x0010 /* Reset request */
2071 +#define LTQ_RCU_RST_REQ_VALUE ((1 << 14) | (1 << 1))
2072 +
2073 +/* CGU module register */
2074 +#define LTQ_CGU_PLL0_CFG 0x0004 /* PLL0 config */
2075 +#define LTQ_CGU_PLL1_CFG 0x0008 /* PLL1 config */
2076 +#define LTQ_CGU_PLL2_CFG 0x0060 /* PLL2 config */
2077 +#define LTQ_CGU_SYS 0x000C /* System clock */
2078 +#define LTQ_CGU_CLK_FSR 0x0010 /* Clock frequency select */
2079 +#define LTQ_CGU_UPDATE 0x0020 /* Clock update control */
2080 +
2081 +/* Valid SYS.CPU values */
2082 +#define LTQ_CGU_SYS_CPU_SHIFT 4
2083 +#define LTQ_CGU_SYS_CPU_600_MHZ 0x0
2084 +#define LTQ_CGU_SYS_CPU_500_MHZ 0x1
2085 +#define LTQ_CGU_SYS_CPU_393_MHZ 0x2
2086 +#define LTQ_CGU_SYS_CPU_333_MHZ 0x3
2087 +#define LTQ_CGU_SYS_CPU_197_MHZ 0x5
2088 +#define LTQ_CGU_SYS_CPU_166_MHZ 0x7
2089 +#define LTQ_CGU_SYS_CPU_125_MHZ 0x9
2090 +
2091 +/* Valid SYS.OCP values */
2092 +#define LTQ_CGU_SYS_OCP_SHIFT 0
2093 +#define LTQ_CGU_SYS_OCP_1 0x0
2094 +#define LTQ_CGU_SYS_OCP_2 0x2
2095 +#define LTQ_CGU_SYS_OCP_2_5 0x3
2096 +#define LTQ_CGU_SYS_OCP_3 0x4
2097 +
2098 +/* Valid CLK_FSR.ETH values */
2099 +#define LTQ_CGU_CLK_FSR_ETH_SHIFT 24
2100 +#define LTQ_CGU_CLK_FSR_ETH_50_MHZ 0x0
2101 +#define LTQ_CGU_CLK_FSR_ETH_25_MHZ 0x1
2102 +#define LTQ_CGU_CLK_FSR_ETH_2_5_MHZ 0x2
2103 +#define LTQ_CGU_CLK_FSR_ETH_125_MHZ 0x3
2104 +
2105 +/* Valid CLK_FSR.PPE values */
2106 +#define LTQ_CGU_CLK_FSR_PPE_SHIFT 16
2107 +#define LTQ_CGU_CLK_FSR_PPE_500_MHZ 0x0 /* Overclock frequency */
2108 +#define LTQ_CGU_CLK_FSR_PPE_450_MHZ 0x1 /* High frequency */
2109 +#define LTQ_CGU_CLK_FSR_PPE_400_MHZ 0x2 /* Low frequency */
2110 +
2111 +#if (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_500_DDR_250)
2112 +#define LTQ_CGU_SYS_CPU_CONFIG LTQ_CGU_SYS_CPU_500_MHZ
2113 +#define LTQ_CGU_SYS_OCP_CONFIG LTQ_CGU_SYS_OCP_2
2114 +#define LTQ_CGU_CLK_FSR_ETH_CONFIG LTQ_CGU_CLK_FSR_ETH_125_MHZ
2115 +#define LTQ_CGU_CLK_FSR_PPE_CONFIG LTQ_CGU_CLK_FSR_PPE_450_MHZ
2116 +#else
2117 +#error "Invalid system clock configuration!"
2118 +#endif
2119 +
2120 +/* Build register values */
2121 +#define LTQ_CGU_SYS_VALUE ((LTQ_CGU_SYS_CPU_CONFIG << \
2122 + LTQ_CGU_SYS_CPU_SHIFT) | \
2123 + LTQ_CGU_SYS_OCP_CONFIG)
2124 +
2125 +#define LTQ_CGU_CLK_FSR_VALUE ((LTQ_CGU_CLK_FSR_ETH_CONFIG << \
2126 + LTQ_CGU_CLK_FSR_ETH_SHIFT) | \
2127 + (LTQ_CGU_CLK_FSR_PPE_CONFIG << \
2128 + LTQ_CGU_CLK_FSR_PPE_SHIFT))
2129 +
2130 + .set noreorder
2131 +
2132 +LEAF(ltq_cgu_init)
2133 + /* Load current CGU register values */
2134 + li t0, (LTQ_CGU_BASE | KSEG1)
2135 + lw t1, LTQ_CGU_SYS(t0)
2136 + lw t2, LTQ_CGU_CLK_FSR(t0)
2137 +
2138 + /* Load target CGU register values */
2139 + li t3, LTQ_CGU_SYS_VALUE
2140 + li t4, LTQ_CGU_CLK_FSR_VALUE
2141 +
2142 + /* Only update registers if values differ */
2143 + bne t1, t3, update
2144 + nop
2145 + beq t2, t4, finished
2146 + nop
2147 +
2148 +update:
2149 + /* Store target register values */
2150 + sw t3, LTQ_CGU_SYS(t0)
2151 + sw t4, LTQ_CGU_CLK_FSR(t0)
2152 +
2153 + /* Perform software reset to activate new clock config */
2154 +#if 0
2155 + li t0, (LTQ_RCU_BASE | KSEG1)
2156 + lw t1, LTQ_RCU_RST_REQ(t0)
2157 + or t1, LTQ_RCU_RST_REQ_VALUE
2158 + sw t1, LTQ_RCU_RST_REQ(t0)
2159 +#else
2160 + li t1, 1
2161 + sw t1, LTQ_CGU_UPDATE(t0)
2162 +#endif
2163 +
2164 +#if 0
2165 +wait_reset:
2166 + b wait_reset
2167 + nop
2168 +#endif
2169 +
2170 +finished:
2171 + jr ra
2172 + nop
2173 +
2174 + END(ltq_cgu_init)
2175 --- /dev/null
2176 +++ b/arch/mips/cpu/mips32/vrx200/chipid.c
2177 @@ -0,0 +1,62 @@
2178 +/*
2179 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2180 + *
2181 + * SPDX-License-Identifier: GPL-2.0+
2182 + */
2183 +
2184 +#include <common.h>
2185 +#include <asm/lantiq/io.h>
2186 +#include <asm/lantiq/chipid.h>
2187 +#include <asm/arch/soc.h>
2188 +
2189 +#define LTQ_CHIPID_VERSION_SHIFT 28
2190 +#define LTQ_CHIPID_VERSION_MASK (0x7 << LTQ_CHIPID_VERSION_SHIFT)
2191 +#define LTQ_CHIPID_PNUM_SHIFT 12
2192 +#define LTQ_CHIPID_PNUM_MASK (0xFFFF << LTQ_CHIPID_PNUM_SHIFT)
2193 +
2194 +struct ltq_chipid_regs {
2195 + u32 manid; /* Manufacturer identification */
2196 + u32 chipid; /* Chip identification */
2197 +};
2198 +
2199 +static struct ltq_chipid_regs *ltq_chipid_regs =
2200 + (struct ltq_chipid_regs *) CKSEG1ADDR(LTQ_CHIPID_BASE);
2201 +
2202 +unsigned int ltq_chip_version_get(void)
2203 +{
2204 + u32 chipid;
2205 +
2206 + chipid = ltq_readl(&ltq_chipid_regs->chipid);
2207 +
2208 + return (chipid & LTQ_CHIPID_VERSION_MASK) >> LTQ_CHIPID_VERSION_SHIFT;
2209 +}
2210 +
2211 +unsigned int ltq_chip_partnum_get(void)
2212 +{
2213 + u32 chipid;
2214 +
2215 + chipid = ltq_readl(&ltq_chipid_regs->chipid);
2216 +
2217 + return (chipid & LTQ_CHIPID_PNUM_MASK) >> LTQ_CHIPID_PNUM_SHIFT;
2218 +}
2219 +
2220 +const char *ltq_chip_partnum_str(void)
2221 +{
2222 + enum ltq_chip_partnum partnum = ltq_chip_partnum_get();
2223 +
2224 + switch (partnum) {
2225 + case LTQ_SOC_VRX268:
2226 + case LTQ_SOC_VRX268_2:
2227 + return "VRX268";
2228 + case LTQ_SOC_VRX288:
2229 + case LTQ_SOC_VRX288_2:
2230 + return "VRX288";
2231 + case LTQ_SOC_GRX288:
2232 + case LTQ_SOC_GRX288_2:
2233 + return "GRX288";
2234 + default:
2235 + printf("Unknown partnum: %x\n", partnum);
2236 + }
2237 +
2238 + return "";
2239 +}
2240 --- /dev/null
2241 +++ b/arch/mips/cpu/mips32/vrx200/config.mk
2242 @@ -0,0 +1,30 @@
2243 +#
2244 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2245 +#
2246 +# SPDX-License-Identifier: GPL-2.0+
2247 +#
2248 +
2249 +PF_CPPFLAGS_XRX := $(call cc-option,-mtune=34kc,)
2250 +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_XRX)
2251 +
2252 +ifdef CONFIG_SPL_BUILD
2253 +PF_ABICALLS := -mno-abicalls
2254 +PF_PIC := -fno-pic
2255 +PF_PIE :=
2256 +USE_PRIVATE_LIBGCC := yes
2257 +endif
2258 +
2259 +LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o
2260 +
2261 +ifndef CONFIG_SPL_BUILD
2262 +ifdef CONFIG_SYS_BOOT_SFSPL
2263 +ALL-y += $(obj)u-boot.ltq.sfspl
2264 +ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.sfspl
2265 +ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.sfspl
2266 +endif
2267 +ifdef CONFIG_SYS_BOOT_NORSPL
2268 +ALL-y += $(obj)u-boot.ltq.norspl
2269 +ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl
2270 +ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl
2271 +endif
2272 +endif
2273 --- /dev/null
2274 +++ b/arch/mips/cpu/mips32/vrx200/dcdc.c
2275 @@ -0,0 +1,106 @@
2276 +/*
2277 + * Copyright (C) 2010 Lantiq Deutschland GmbH
2278 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2279 + *
2280 + * SPDX-License-Identifier: GPL-2.0+
2281 + */
2282 +
2283 +#include <common.h>
2284 +#include <asm/arch/soc.h>
2285 +#include <asm/lantiq/io.h>
2286 +
2287 +#define LTQ_DCDC_CLK_SET0_CLK_SEL_P (1 << 6)
2288 +#define LTQ_DCDC_CLK_SET1_SEL_DIV25 (1 << 5)
2289 +#define LTQ_DCDC_CONF_TEST_DIG_PID_FREEZE (1 << 5)
2290 +
2291 +struct ltq_dcdc_regs {
2292 + u8 b0_coeh; /* Coefficient b0 */
2293 + u8 b0_coel; /* Coefficient b0 */
2294 + u8 b1_coeh; /* Coefficient b1 */
2295 + u8 b1_coel; /* Coefficient b1 */
2296 + u8 b2_coeh; /* Coefficient b2 */
2297 + u8 b2_coel; /* Coefficient b2 */
2298 + u8 clk_set0; /* Clock setup */
2299 + u8 clk_set1; /* Clock setup */
2300 + u8 pwm_confh; /* Configure PWM */
2301 + u8 pwm_confl; /* Configure PWM */
2302 + u8 bias_vreg0; /* Bias and regulator setup */
2303 + u8 bias_vreg1; /* Bias and regulator setup */
2304 + u8 adc_gen0; /* ADC and general control */
2305 + u8 adc_gen1; /* ADC and general control */
2306 + u8 adc_con0; /* ADC and general config */
2307 + u8 adc_con1; /* ADC and general config */
2308 + u8 conf_test_ana; /* not documented */
2309 + u8 conf_test_dig; /* not documented */
2310 + u8 dcdc_status; /* not documented */
2311 + u8 pid_status; /* not documented */
2312 + u8 duty_cycle; /* not documented */
2313 + u8 non_ov_delay; /* not documented */
2314 + u8 analog_gain; /* not documented */
2315 + u8 duty_cycle_max_sat; /* not documented */
2316 + u8 duty_cycle_min_sat; /* not documented */
2317 + u8 duty_cycle_max; /* not documented */
2318 + u8 duty_cycle_min; /* not documented */
2319 + u8 error_max; /* not documented */
2320 + u8 error_read; /* not documented */
2321 + u8 delay_deglitch; /* not documented */
2322 + u8 latch_control; /* not documented */
2323 + u8 rsvd[240];
2324 + u8 osc_conf; /* OSC general config */
2325 + u8 osc_stat; /* OSC general status */
2326 +};
2327 +
2328 +static struct ltq_dcdc_regs *ltq_dcdc_regs =
2329 + (struct ltq_dcdc_regs *) CKSEG1ADDR(LTQ_DCDC_BASE);
2330 +
2331 +void ltq_dcdc_init(unsigned int dig_ref)
2332 +{
2333 + u8 dig_ref_cur, val;
2334 +
2335 + /* Set duty cycle max sat. to 70/90, enable PID freeze */
2336 + ltq_writeb(&ltq_dcdc_regs->duty_cycle_max_sat, 0x5A);
2337 + ltq_writeb(&ltq_dcdc_regs->duty_cycle_min_sat, 0x46);
2338 + val = ltq_readb(&ltq_dcdc_regs->conf_test_dig);
2339 + val |= LTQ_DCDC_CONF_TEST_DIG_PID_FREEZE;
2340 + ltq_writeb(&ltq_dcdc_regs->conf_test_dig, val);
2341 +
2342 + /* Program new coefficients */
2343 + ltq_writeb(&ltq_dcdc_regs->b0_coeh, 0x00);
2344 + ltq_writeb(&ltq_dcdc_regs->b0_coel, 0x00);
2345 + ltq_writeb(&ltq_dcdc_regs->b1_coeh, 0xFF);
2346 + ltq_writeb(&ltq_dcdc_regs->b1_coel, 0xE6);
2347 + ltq_writeb(&ltq_dcdc_regs->b2_coeh, 0x00);
2348 + ltq_writeb(&ltq_dcdc_regs->b2_coel, 0x1B);
2349 + ltq_writeb(&ltq_dcdc_regs->non_ov_delay, 0x8B);
2350 +
2351 + /* Set duty cycle max sat. to 60/108, disable PID freeze */
2352 + ltq_writeb(&ltq_dcdc_regs->duty_cycle_max_sat, 0x6C);
2353 + ltq_writeb(&ltq_dcdc_regs->duty_cycle_min_sat, 0x3C);
2354 + val = ltq_readb(&ltq_dcdc_regs->conf_test_dig);
2355 + val &= ~LTQ_DCDC_CONF_TEST_DIG_PID_FREEZE;
2356 + ltq_writeb(&ltq_dcdc_regs->conf_test_dig, val);
2357 +
2358 + /* Init clock and DLL settings */
2359 + val = ltq_readb(&ltq_dcdc_regs->clk_set0);
2360 + val |= LTQ_DCDC_CLK_SET0_CLK_SEL_P;
2361 + ltq_writeb(&ltq_dcdc_regs->clk_set0, val);
2362 + val = ltq_readb(&ltq_dcdc_regs->clk_set1);
2363 + val |= LTQ_DCDC_CLK_SET1_SEL_DIV25;
2364 + ltq_writeb(&ltq_dcdc_regs->clk_set1, val);
2365 + ltq_writeb(&ltq_dcdc_regs->pwm_confh, 0xF9);
2366 +
2367 + wmb();
2368 +
2369 + /* Adapt value of digital reference of DCDC converter */
2370 + dig_ref_cur = ltq_readb(&ltq_dcdc_regs->bias_vreg1);
2371 +
2372 + while (dig_ref_cur != dig_ref) {
2373 + if (dig_ref >= dig_ref_cur)
2374 + dig_ref_cur++;
2375 + else if (dig_ref < dig_ref_cur)
2376 + dig_ref_cur--;
2377 +
2378 + ltq_writeb(&ltq_dcdc_regs->bias_vreg1, dig_ref_cur);
2379 + __udelay(1000);
2380 + }
2381 +}
2382 --- /dev/null
2383 +++ b/arch/mips/cpu/mips32/vrx200/ebu.c
2384 @@ -0,0 +1,126 @@
2385 +/*
2386 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2387 + *
2388 + * SPDX-License-Identifier: GPL-2.0+
2389 + */
2390 +
2391 +#include <common.h>
2392 +#include <asm/arch/soc.h>
2393 +#include <asm/lantiq/io.h>
2394 +
2395 +#define EBU_ADDRSEL_MASK(mask) ((mask & 0xf) << 4)
2396 +#define EBU_ADDRSEL_REGEN (1 << 0)
2397 +
2398 +#define EBU_CON_WRDIS (1 << 31)
2399 +#define EBU_CON_AGEN_DEMUX (0x0 << 24)
2400 +#define EBU_CON_AGEN_MUX (0x2 << 24)
2401 +#define EBU_CON_SETUP (1 << 22)
2402 +#define EBU_CON_WAIT_DIS (0x0 << 20)
2403 +#define EBU_CON_WAIT_ASYNC (0x1 << 20)
2404 +#define EBU_CON_WAIT_SYNC (0x2 << 20)
2405 +#define EBU_CON_WINV (1 << 19)
2406 +#define EBU_CON_PW_8BIT (0x0 << 16)
2407 +#define EBU_CON_PW_16BIT (0x1 << 16)
2408 +#define EBU_CON_ALEC(cycles) ((cycles & 0x3) << 14)
2409 +#define EBU_CON_BCGEN_CS (0x0 << 12)
2410 +#define EBU_CON_BCGEN_INTEL (0x1 << 12)
2411 +#define EBU_CON_BCGEN_MOTOROLA (0x2 << 12)
2412 +#define EBU_CON_WAITWRC(cycles) ((cycles & 0x7) << 8)
2413 +#define EBU_CON_WAITRDC(cycles) ((cycles & 0x3) << 6)
2414 +#define EBU_CON_HOLDC(cycles) ((cycles & 0x3) << 4)
2415 +#define EBU_CON_RECOVC(cycles) ((cycles & 0x3) << 2)
2416 +#define EBU_CON_CMULT_1 0x0
2417 +#define EBU_CON_CMULT_4 0x1
2418 +#define EBU_CON_CMULT_8 0x2
2419 +#define EBU_CON_CMULT_16 0x3
2420 +
2421 +#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
2422 +#define ebu_region0_enable 1
2423 +#else
2424 +#define ebu_region0_enable 0
2425 +#endif
2426 +
2427 +#if ((CONFIG_SYS_MAX_FLASH_BANKS == 2) && defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) )
2428 +#define ebu_region0_addrsel_mask 3
2429 +#else
2430 +#define ebu_region0_addrsel_mask 1
2431 +#endif
2432 +
2433 +#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) || ((CONFIG_SYS_MAX_FLASH_BANKS == 2) && defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) )
2434 +#define ebu_region1_enable 1
2435 +#else
2436 +#define ebu_region1_enable 0
2437 +#endif
2438 +
2439 +struct ltq_ebu_regs {
2440 + u32 clc;
2441 + u32 rsvd0;
2442 + u32 id;
2443 + u32 rsvd1;
2444 + u32 con;
2445 + u32 rsvd2[3];
2446 + u32 addr_sel_0;
2447 + u32 addr_sel_1;
2448 + u32 addr_sel_2;
2449 + u32 addr_sel_3;
2450 + u32 rsvd3[12];
2451 + u32 con_0;
2452 + u32 con_1;
2453 + u32 con_2;
2454 + u32 con_3;
2455 +};
2456 +
2457 +static struct ltq_ebu_regs *ltq_ebu_regs =
2458 + (struct ltq_ebu_regs *) CKSEG1ADDR(LTQ_EBU_BASE);
2459 +
2460 +void ltq_ebu_init(void)
2461 +{
2462 + if (ebu_region0_enable) {
2463 + /*
2464 + * Map EBU region 0 to range 0x10000000-0x13ffffff and enable
2465 + * region control. This supports up to 32 MiB NOR flash in
2466 + * bank 0.
2467 + */
2468 + ltq_writel(&ltq_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE |
2469 + EBU_ADDRSEL_MASK(ebu_region0_addrsel_mask) | EBU_ADDRSEL_REGEN);
2470 +
2471 + ltq_writel(&ltq_ebu_regs->con_0, EBU_CON_AGEN_DEMUX |
2472 + EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |
2473 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
2474 + EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |
2475 + EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |
2476 + EBU_CON_CMULT_16);
2477 + } else
2478 + ltq_clrbits(&ltq_ebu_regs->addr_sel_0, EBU_ADDRSEL_REGEN);
2479 +
2480 + if (ebu_region1_enable) {
2481 + /*
2482 + * Map EBU region 1 to range 0x14000000-0x13ffffff and enable
2483 + * region control. This supports NAND flash in bank 1. (and NOR flash in bank 2)
2484 + */
2485 + ltq_writel(&ltq_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE |
2486 + EBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN);
2487 +
2488 + if (ebu_region0_addrsel_mask == 1)
2489 + ltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |
2490 + EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT |
2491 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
2492 + EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) |
2493 + EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) |
2494 + EBU_CON_CMULT_4);
2495 +
2496 + if (ebu_region0_addrsel_mask == 3)
2497 + ltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |
2498 + EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |
2499 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
2500 + EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |
2501 + EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |
2502 + EBU_CON_CMULT_16);
2503 + } else
2504 + ltq_clrbits(&ltq_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN);
2505 +}
2506 +
2507 +void *flash_swap_addr(unsigned long addr)
2508 +{
2509 + return (void *)(addr ^ 2);
2510 +}
2511 --- /dev/null
2512 +++ b/arch/mips/cpu/mips32/vrx200/gphy.c
2513 @@ -0,0 +1,68 @@
2514 +/*
2515 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2516 + *
2517 + * SPDX-License-Identifier: GPL-2.0+
2518 + */
2519 +
2520 +#include <common.h>
2521 +#include <asm/lantiq/io.h>
2522 +#include <asm/arch/soc.h>
2523 +#include <asm/arch/gphy.h>
2524 +#include <lzma/LzmaTypes.h>
2525 +#include <lzma/LzmaDec.h>
2526 +#include <lzma/LzmaTools.h>
2527 +
2528 +static inline void ltq_gphy_decompress(const void *fw_start, const void *fw_end,
2529 + ulong dst_addr)
2530 +{
2531 + const ulong fw_len = (ulong) fw_end - (ulong) fw_start;
2532 + const ulong addr = CKSEG1ADDR(dst_addr);
2533 +
2534 + debug("ltq_gphy_decompress: addr %08lx, fw_start %p, fw_end %p\n",
2535 + addr, fw_start, fw_end);
2536 +
2537 + SizeT lzma_len = 65536;
2538 + int ret = lzmaBuffToBuffDecompress(
2539 + (unsigned char *)addr, &lzma_len,
2540 + (unsigned char *)fw_start, fw_len);
2541 +}
2542 +
2543 +void ltq_gphy_phy11g_a1x_load(ulong addr)
2544 +{
2545 + extern ulong __ltq_fw_phy11g_a1x_start;
2546 + extern ulong __ltq_fw_phy11g_a1x_end;
2547 +
2548 + ltq_gphy_decompress(&__ltq_fw_phy11g_a1x_start,
2549 + &__ltq_fw_phy11g_a1x_end,
2550 + addr);
2551 +}
2552 +
2553 +void ltq_gphy_phy11g_a2x_load(ulong addr)
2554 +{
2555 + extern ulong __ltq_fw_phy11g_a2x_start;
2556 + extern ulong __ltq_fw_phy11g_a2x_end;
2557 +
2558 + ltq_gphy_decompress(&__ltq_fw_phy11g_a2x_start,
2559 + &__ltq_fw_phy11g_a2x_end,
2560 + addr);
2561 +}
2562 +
2563 +void ltq_gphy_phy22f_a1x_load(ulong addr)
2564 +{
2565 + extern ulong __ltq_fw_phy22f_a1x_start;
2566 + extern ulong __ltq_fw_phy22f_a1x_end;
2567 +
2568 + ltq_gphy_decompress(&__ltq_fw_phy22f_a1x_start,
2569 + &__ltq_fw_phy22f_a1x_end,
2570 + addr);
2571 +}
2572 +
2573 +void ltq_gphy_phy22f_a2x_load(ulong addr)
2574 +{
2575 + extern ulong __ltq_fw_phy22f_a2x_start;
2576 + extern ulong __ltq_fw_phy22f_a2x_end;
2577 +
2578 + ltq_gphy_decompress(&__ltq_fw_phy22f_a2x_start,
2579 + &__ltq_fw_phy22f_a2x_end,
2580 + addr);
2581 +}
2582 --- /dev/null
2583 +++ b/arch/mips/cpu/mips32/vrx200/gphy_fw.S
2584 @@ -0,0 +1,27 @@
2585 +/*
2586 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2587 + *
2588 + * SPDX-License-Identifier: GPL-2.0+
2589 + */
2590 +
2591 +#include <asm/asm.h>
2592 +
2593 + .section .rodata.__ltq_fw_phy11g_a1x
2594 +EXPORT(__ltq_fw_phy11g_a1x_start)
2595 + .incbin "fw_phy11g_a1x.blob"
2596 +EXPORT(__ltq_fw_phy11g_a1x_end)
2597 +
2598 + .section .rodata.__ltq_fw_phy11g_a2x
2599 +EXPORT(__ltq_fw_phy11g_a2x_start)
2600 + .incbin "fw_phy11g_a2x.blob"
2601 +EXPORT(__ltq_fw_phy11g_a2x_end)
2602 +
2603 + .section .rodata.__ltq_fw_phy22f_a1x
2604 +EXPORT(__ltq_fw_phy22f_a1x_start)
2605 + .incbin "fw_phy22f_a1x.blob"
2606 +EXPORT(__ltq_fw_phy22f_a1x_end)
2607 +
2608 + .section .rodata.__ltq_fw_phy22f_a2x
2609 +EXPORT(__ltq_fw_phy22f_a2x_start)
2610 + .incbin "fw_phy22f_a2x.blob"
2611 +EXPORT(__ltq_fw_phy22f_a2x_end)
2612 --- /dev/null
2613 +++ b/arch/mips/cpu/mips32/vrx200/mem.c
2614 @@ -0,0 +1,57 @@
2615 +/*
2616 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2617 + *
2618 + * SPDX-License-Identifier: GPL-2.0+
2619 + */
2620 +
2621 +#include <common.h>
2622 +#include <asm/arch/soc.h>
2623 +#include <asm/lantiq/io.h>
2624 +
2625 +#define LTQ_CCR03_EIGHT_BANK_MODE (1 << 0)
2626 +#define LTQ_CCR08_CS_MAP_SHIFT 24
2627 +#define LTQ_CCR08_CS_MAP_MASK (0x3 << LTQ_CCR08_CS_MAP_SHIFT)
2628 +#define LTQ_CCR11_COLUMN_SIZE_SHIFT 24
2629 +#define LTQ_CCR11_COLUMN_SIZE_MASK (0x7 << LTQ_CCR11_COLUMN_SIZE_SHIFT)
2630 +#define LTQ_CCR11_ADDR_PINS_MASK 0x7
2631 +#define LTQ_CCR15_MAX_COL_REG_SHIFT 24
2632 +#define LTQ_CCR15_MAX_COL_REG_MASK (0xF << LTQ_CCR15_MAX_COL_REG_SHIFT)
2633 +#define LTQ_CCR16_MAX_ROW_REG_MASK 0xF
2634 +
2635 +static void *ltq_mc_ddr_base = (void *) CKSEG1ADDR(LTQ_MC_DDR_BASE);
2636 +
2637 +static inline u32 ltq_mc_ccr_read(u32 index)
2638 +{
2639 + return ltq_readl(ltq_mc_ddr_base + LTQ_MC_DDR_CCR_OFFSET(index));
2640 +}
2641 +
2642 +phys_size_t initdram(int board_type)
2643 +{
2644 + u32 max_col_reg, max_row_reg, column_size, addr_pins;
2645 + u32 banks, cs_map;
2646 + phys_size_t size;
2647 +
2648 + banks = (ltq_mc_ccr_read(3) & LTQ_CCR03_EIGHT_BANK_MODE) ? 8 : 4;
2649 +
2650 + cs_map = (ltq_mc_ccr_read(8) & LTQ_CCR08_CS_MAP_MASK) >>
2651 + LTQ_CCR08_CS_MAP_SHIFT;
2652 +
2653 + column_size = (ltq_mc_ccr_read(11) & LTQ_CCR11_COLUMN_SIZE_MASK) >>
2654 + LTQ_CCR11_COLUMN_SIZE_SHIFT;
2655 +
2656 + addr_pins = ltq_mc_ccr_read(11) & LTQ_CCR11_ADDR_PINS_MASK;
2657 +
2658 + max_col_reg = (ltq_mc_ccr_read(15) & LTQ_CCR15_MAX_COL_REG_MASK) >>
2659 + LTQ_CCR15_MAX_COL_REG_SHIFT;
2660 +
2661 + max_row_reg = ltq_mc_ccr_read(16) & LTQ_CCR16_MAX_ROW_REG_MASK;
2662 +
2663 + /*
2664 + * size (bytes) = 2 ^ rowsize * 2 ^ colsize * banks * chipselects
2665 + * * datawidth (bytes)
2666 + */
2667 + size = (2 << (max_col_reg - column_size - 1)) *
2668 + (2 << (max_row_reg - addr_pins - 1)) * banks * cs_map * 2;
2669 +
2670 + return size;
2671 +}
2672 --- /dev/null
2673 +++ b/arch/mips/cpu/mips32/vrx200/mem_init.S
2674 @@ -0,0 +1,233 @@
2675 +/*
2676 + * Copyright (C) 2010 Lantiq Deutschland GmbH
2677 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2678 + *
2679 + * SPDX-License-Identifier: GPL-2.0+
2680 + */
2681 +
2682 +#include <config.h>
2683 +#include <asm/asm.h>
2684 +#include <asm/regdef.h>
2685 +#include <asm/addrspace.h>
2686 +#include <asm/arch/soc.h>
2687 +
2688 +/* Must be configured in BOARDDIR */
2689 +#include <ddr_settings.h>
2690 +
2691 +#define LTQ_MC_DDR_START (1 << 8)
2692 +#define LTQ_MC_DDR_DLL_LOCK_IND 1
2693 +
2694 +#define CCS_ALWAYS_LAST 0x0430
2695 +#define CCS_AHBM_CR_BURST_EN (1 << 2)
2696 +#define CCS_FPIM_CR_BURST_EN (1 << 1)
2697 +
2698 +#define CCR03_EIGHT_BANK_MODE (1 << 0)
2699 +
2700 + /* Store given value in MC DDR CCRx register */
2701 + .macro ccr_sw num, val
2702 + li t1, \val
2703 + sw t1, LTQ_MC_DDR_CCR_OFFSET(\num)(t0)
2704 + .endm
2705 +
2706 +LEAF(ltq_mem_init)
2707 + /* Load MC DDR module base */
2708 + li t0, (LTQ_MC_DDR_BASE | KSEG1)
2709 +
2710 + /* Put memory controller in inactive mode */
2711 + sw zero, LTQ_MC_DDR_CCR_OFFSET(7)(t0)
2712 +
2713 + /* Init MC DDR CCR registers with values from ddr_settings.h */
2714 + ccr_sw 0, MC_CCR00_VALUE
2715 + ccr_sw 1, MC_CCR01_VALUE
2716 + ccr_sw 2, MC_CCR02_VALUE
2717 + ccr_sw 3, MC_CCR03_VALUE
2718 + ccr_sw 4, MC_CCR04_VALUE
2719 + ccr_sw 5, MC_CCR05_VALUE
2720 + ccr_sw 6, MC_CCR06_VALUE
2721 + ccr_sw 7, MC_CCR07_VALUE
2722 + ccr_sw 8, MC_CCR08_VALUE
2723 + ccr_sw 9, MC_CCR09_VALUE
2724 +
2725 + ccr_sw 10, MC_CCR10_VALUE
2726 + ccr_sw 11, MC_CCR11_VALUE
2727 + ccr_sw 12, MC_CCR12_VALUE
2728 + ccr_sw 13, MC_CCR13_VALUE
2729 + ccr_sw 14, MC_CCR14_VALUE
2730 + ccr_sw 15, MC_CCR15_VALUE
2731 + ccr_sw 16, MC_CCR16_VALUE
2732 + ccr_sw 17, MC_CCR17_VALUE
2733 + ccr_sw 18, MC_CCR18_VALUE
2734 + ccr_sw 19, MC_CCR19_VALUE
2735 +
2736 + ccr_sw 20, MC_CCR20_VALUE
2737 + ccr_sw 21, MC_CCR21_VALUE
2738 + ccr_sw 22, MC_CCR22_VALUE
2739 + ccr_sw 23, MC_CCR23_VALUE
2740 + ccr_sw 24, MC_CCR24_VALUE
2741 + ccr_sw 25, MC_CCR25_VALUE
2742 + ccr_sw 26, MC_CCR26_VALUE
2743 + ccr_sw 27, MC_CCR27_VALUE
2744 + ccr_sw 28, MC_CCR28_VALUE
2745 + ccr_sw 29, MC_CCR29_VALUE
2746 +
2747 + ccr_sw 30, MC_CCR30_VALUE
2748 + ccr_sw 31, MC_CCR31_VALUE
2749 + ccr_sw 32, MC_CCR32_VALUE
2750 + ccr_sw 33, MC_CCR33_VALUE
2751 + ccr_sw 34, MC_CCR34_VALUE
2752 + ccr_sw 35, MC_CCR35_VALUE
2753 + ccr_sw 36, MC_CCR36_VALUE
2754 + ccr_sw 37, MC_CCR37_VALUE
2755 + ccr_sw 38, MC_CCR38_VALUE
2756 + ccr_sw 39, MC_CCR39_VALUE
2757 +
2758 + ccr_sw 40, MC_CCR40_VALUE
2759 + ccr_sw 41, MC_CCR41_VALUE
2760 + ccr_sw 42, MC_CCR42_VALUE
2761 + ccr_sw 43, MC_CCR43_VALUE
2762 + ccr_sw 44, MC_CCR44_VALUE
2763 + ccr_sw 45, MC_CCR45_VALUE
2764 + ccr_sw 46, MC_CCR46_VALUE
2765 +
2766 + ccr_sw 52, MC_CCR52_VALUE
2767 + ccr_sw 53, MC_CCR53_VALUE
2768 + ccr_sw 54, MC_CCR54_VALUE
2769 + ccr_sw 55, MC_CCR55_VALUE
2770 + ccr_sw 56, MC_CCR56_VALUE
2771 + ccr_sw 57, MC_CCR57_VALUE
2772 + ccr_sw 58, MC_CCR58_VALUE
2773 + ccr_sw 59, MC_CCR59_VALUE
2774 +
2775 + ccr_sw 60, MC_CCR60_VALUE
2776 + ccr_sw 61, MC_CCR61_VALUE
2777 +
2778 + /* Disable bursts between FPI Master bus and XBAR bus */
2779 + li t4, (LTQ_MC_GLOBAL_BASE | KSEG1)
2780 + li t5, CCS_AHBM_CR_BURST_EN
2781 + sw t5, CCS_ALWAYS_LAST(t4)
2782 +
2783 + /* Init abort condition for DRAM probe */
2784 + move t4, zero
2785 +
2786 + /*
2787 + * Put memory controller in active mode and start initialitation
2788 + * sequence for connected DDR-SDRAM device
2789 + */
2790 +mc_start:
2791 + lw t1, LTQ_MC_DDR_CCR_OFFSET(7)(t0)
2792 + li t2, LTQ_MC_DDR_START
2793 + or t1, t1, t2
2794 + sw t1, LTQ_MC_DDR_CCR_OFFSET(7)(t0)
2795 +
2796 + /*
2797 + * Wait until DLL has locked and core is ready for data transfers.
2798 + * DLL lock indication is in register CCR47 and CCR48
2799 + */
2800 +wait_ready:
2801 + li t1, LTQ_MC_DDR_DLL_LOCK_IND
2802 + lw t2, LTQ_MC_DDR_CCR_OFFSET(47)(t0)
2803 + and t2, t2, t1
2804 + bne t1, t2, wait_ready
2805 +
2806 + lw t2, LTQ_MC_DDR_CCR_OFFSET(48)(t0)
2807 + and t2, t2, t1
2808 + bne t1, t2, wait_ready
2809 +
2810 +#ifdef CONFIG_SYS_DRAM_PROBE
2811 +dram_probe:
2812 + /* Initialization is finished after the second MC start */
2813 + bnez t4, mc_finished
2814 +
2815 + /*
2816 + * Preload register values for CCR03 and CCR11. Initial settings
2817 + * are 8-bank mode enabled, 14 use address row bits, 10 used
2818 + * column address bits.
2819 + */
2820 + li t1, CONFIG_SYS_SDRAM_BASE_UC
2821 + li t5, MC_CCR03_VALUE
2822 + li t6, MC_CCR11_VALUE
2823 + addi t4, t4, 1
2824 +
2825 + /*
2826 + * Store test values to DRAM at offsets 0 and 2^13 (bit 2 in bank select
2827 + * address BA[3]) and read back the value at offset 0. If the resulting
2828 + * value is equal to 1 we can skip to the next test. Otherwise
2829 + * the 8-bank mode does not work with the current DRAM device,
2830 + * thus we need to clear the according bit in register CCR03.
2831 + */
2832 + li t2, 1
2833 + sw t2, 0x0(t1)
2834 + li t3, (1 << 13)
2835 + add t3, t3, t1
2836 + sw zero, 0(t3)
2837 + lw t3, 0(t1)
2838 + bnez t3, row_col_test
2839 +
2840 + /* Clear CCR03.EIGHT_BANK_MODE */
2841 + li t3, ~CCR03_EIGHT_BANK_MODE
2842 + and t5, t5, t3
2843 +
2844 +row_col_test:
2845 + /*
2846 + * Store test values to DRAM at offsets 0, 2^27 (bit 13 of row address
2847 + * RA[14]) and 2^26 (bit 12 of RA[14]). The chosen test values
2848 + * represent the difference between max. row address bits (14) and used
2849 + * row address bits. Then the read back value at offset 0 indicates
2850 + * the useable row address bits with the current DRAM device. This
2851 + * value must be set in the CCR11 register.
2852 + */
2853 + sw zero, 0(t1)
2854 +
2855 + li t2, 1
2856 + li t3, (1 << 27)
2857 + add t3, t3, t1
2858 + sw t2, 0(t3)
2859 +
2860 + li t2, 2
2861 + li t3, (1 << 26)
2862 + add t3, t3, t1
2863 + sw t2, 0(t3)
2864 +
2865 + /* Update CCR11.ADDR_PINS */
2866 + lw t3, 0(t1)
2867 + add t6, t6, t3
2868 +
2869 + /*
2870 + * Store test values to DRAM at offsets 0, 2^10 (bit 9 of column address
2871 + * CA[10]) and 2^9 (bit 8 of CA[10]). The chosen test values represent
2872 + * the difference between max. column address bits (12) and used
2873 + * column address bits. Then the read back value at offset 0 indicates
2874 + * the useable column address bits with the current DRAM device. This
2875 + * value must be set in the CCR11 register.
2876 + */
2877 + sw zero, 0(t1)
2878 +
2879 + li t2, 1
2880 + li t3, (1 << 10)
2881 + add t3, t3, t1
2882 + sw t2, 0(t3)
2883 +
2884 + li t2, 2
2885 + li t3, (1 << 9)
2886 + add t3, t3, t1
2887 + sw t2, 0(t3)
2888 +
2889 + /* Update CCR11.COLUMN_SIZE */
2890 + lw t3, 0(t1)
2891 + sll t3, t3, 24
2892 + add t6, t6, t3
2893 +
2894 + /* Put memory controller in inactive mode */
2895 + sw zero, LTQ_MC_DDR_CCR_OFFSET(7)(t0)
2896 +
2897 + /* Update CCR03 and CCR11 and restart memory controller initialiation */
2898 + sw t5, LTQ_MC_DDR_CCR_OFFSET(3)(t0)
2899 + sw t6, LTQ_MC_DDR_CCR_OFFSET(11)(t0)
2900 + b mc_start
2901 +
2902 +mc_finished:
2903 +#endif /* CONFIG_SYS_DRAM_PROBE */
2904 +
2905 + jr ra
2906 +
2907 + END(ltq_mem_init)
2908 --- /dev/null
2909 +++ b/arch/mips/cpu/mips32/vrx200/pmu.c
2910 @@ -0,0 +1,130 @@
2911 +/*
2912 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2913 + *
2914 + * SPDX-License-Identifier: GPL-2.0+
2915 + */
2916 +
2917 +#include <common.h>
2918 +#include <asm/lantiq/io.h>
2919 +#include <asm/lantiq/pm.h>
2920 +#include <asm/arch/soc.h>
2921 +
2922 +#define LTQ_PMU_PWDCR_RESERVED ((1 << 13) | (1 << 4))
2923 +
2924 +#define LTQ_PMU_PWDCR_PCIELOC_EN (1 << 31)
2925 +#define LTQ_PMU_PWDCR_GPHY (1 << 30)
2926 +#define LTQ_PMU_PWDCR_PPE_TOP (1 << 29)
2927 +#define LTQ_PMU_PWDCR_SWITCH (1 << 28)
2928 +#define LTQ_PMU_PWDCR_USB1 (1 << 27)
2929 +#define LTQ_PMU_PWDCR_USB1_PHY (1 << 26)
2930 +#define LTQ_PMU_PWDCR_TDM (1 << 25)
2931 +#define LTQ_PMU_PWDCR_PPE_DPLUS (1 << 24)
2932 +#define LTQ_PMU_PWDCR_PPE_DPLUM (1 << 23)
2933 +#define LTQ_PMU_PWDCR_PPE_EMA (1 << 22)
2934 +#define LTQ_PMU_PWDCR_PPE_TC (1 << 21)
2935 +#define LTQ_PMU_PWDCR_DEU (1 << 20)
2936 +#define LTQ_PMU_PWDCR_PPE_SLL01 (1 << 19)
2937 +#define LTQ_PMU_PWDCR_PPE_QSB (1 << 18)
2938 +#define LTQ_PMU_PWDCR_UART1 (1 << 17)
2939 +#define LTQ_PMU_PWDCR_SDIO (1 << 16)
2940 +#define LTQ_PMU_PWDCR_AHBM (1 << 15)
2941 +#define LTQ_PMU_PWDCR_FPIM (1 << 14)
2942 +#define LTQ_PMU_PWDCR_GPTC (1 << 12)
2943 +#define LTQ_PMU_PWDCR_LEDC (1 << 11)
2944 +#define LTQ_PMU_PWDCR_EBU (1 << 10)
2945 +#define LTQ_PMU_PWDCR_DSL (1 << 9)
2946 +#define LTQ_PMU_PWDCR_SPI (1 << 8)
2947 +#define LTQ_PMU_PWDCR_USIF (1 << 7)
2948 +#define LTQ_PMU_PWDCR_USB0 (1 << 6)
2949 +#define LTQ_PMU_PWDCR_DMA (1 << 5)
2950 +#define LTQ_PMU_PWDCR_DFEV1 (1 << 3)
2951 +#define LTQ_PMU_PWDCR_DFEV0 (1 << 2)
2952 +#define LTQ_PMU_PWDCR_FPIS (1 << 1)
2953 +#define LTQ_PMU_PWDCR_USB0_PHY (1 << 0)
2954 +
2955 +struct ltq_pmu_regs {
2956 + u32 rsvd0[7];
2957 + u32 pwdcr; /* Power down control */
2958 + u32 sr; /* Power down status */
2959 + u32 pwdcr1; /* Power down control 1 */
2960 + u32 sr1; /* Power down status 1 */
2961 +};
2962 +
2963 +static struct ltq_pmu_regs *ltq_pmu_regs =
2964 + (struct ltq_pmu_regs *) CKSEG1ADDR(LTQ_PMU_BASE);
2965 +
2966 +u32 ltq_pm_map(enum ltq_pm_modules module)
2967 +{
2968 + u32 val;
2969 +
2970 + switch (module) {
2971 + case LTQ_PM_CORE:
2972 + val = LTQ_PMU_PWDCR_UART1 | LTQ_PMU_PWDCR_FPIM |
2973 + LTQ_PMU_PWDCR_LEDC | LTQ_PMU_PWDCR_EBU;
2974 + break;
2975 + case LTQ_PM_DMA:
2976 + val = LTQ_PMU_PWDCR_DMA;
2977 + break;
2978 + case LTQ_PM_ETH:
2979 + val = LTQ_PMU_PWDCR_GPHY | LTQ_PMU_PWDCR_PPE_TOP |
2980 + LTQ_PMU_PWDCR_SWITCH | LTQ_PMU_PWDCR_PPE_DPLUS |
2981 + LTQ_PMU_PWDCR_PPE_DPLUM | LTQ_PMU_PWDCR_PPE_EMA |
2982 + LTQ_PMU_PWDCR_PPE_TC | LTQ_PMU_PWDCR_PPE_SLL01 |
2983 + LTQ_PMU_PWDCR_PPE_QSB;
2984 + break;
2985 + case LTQ_PM_SPI:
2986 + val = LTQ_PMU_PWDCR_SPI;
2987 + break;
2988 + default:
2989 + val = 0;
2990 + break;
2991 + }
2992 +
2993 + return val;
2994 +}
2995 +
2996 +int ltq_pm_enable(enum ltq_pm_modules module)
2997 +{
2998 + const unsigned long timeout = 1000;
2999 + unsigned long timebase;
3000 + u32 sr, val;
3001 +
3002 + val = ltq_pm_map(module);
3003 + if (unlikely(!val))
3004 + return 1;
3005 +
3006 + ltq_clrbits(&ltq_pmu_regs->pwdcr, val);
3007 +
3008 + timebase = get_timer(0);
3009 +
3010 + do {
3011 + sr = ltq_readl(&ltq_pmu_regs->sr);
3012 + if (~sr & val)
3013 + return 0;
3014 + } while (get_timer(timebase) < timeout);
3015 +
3016 + return 1;
3017 +}
3018 +
3019 +int ltq_pm_disable(enum ltq_pm_modules module)
3020 +{
3021 + u32 val;
3022 +
3023 + val = ltq_pm_map(module);
3024 + if (unlikely(!val))
3025 + return 1;
3026 +
3027 + ltq_setbits(&ltq_pmu_regs->pwdcr, val);
3028 +
3029 + return 0;
3030 +}
3031 +
3032 +void ltq_pmu_init(void)
3033 +{
3034 + u32 set, clr;
3035 +
3036 + clr = ltq_pm_map(LTQ_PM_CORE);
3037 + set = ~(LTQ_PMU_PWDCR_RESERVED | clr);
3038 +
3039 + ltq_clrsetbits(&ltq_pmu_regs->pwdcr, clr, set);
3040 +}
3041 --- /dev/null
3042 +++ b/arch/mips/cpu/mips32/vrx200/rcu.c
3043 @@ -0,0 +1,194 @@
3044 +/*
3045 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3046 + *
3047 + * SPDX-License-Identifier: GPL-2.0+
3048 + */
3049 +
3050 +#include <common.h>
3051 +#include <asm/lantiq/io.h>
3052 +#include <asm/lantiq/reset.h>
3053 +#include <asm/lantiq/cpu.h>
3054 +#include <asm/arch/soc.h>
3055 +
3056 +#define LTQ_RCU_RD_GPHY0 (1 << 31) /* GPHY0 */
3057 +#define LTQ_RCU_RD_SRST (1 << 30) /* Global SW Reset */
3058 +#define LTQ_RCU_RD_GPHY1 (1 << 29) /* GPHY1 */
3059 +#define LTQ_RCU_RD_ENMIP2 (1 << 28) /* Enable NMI of PLL2 */
3060 +#define LTQ_RCU_RD_REG25_PD (1 << 26) /* Power down 2.5V regulator */
3061 +#define LTQ_RCU_RD_ENDINIT (1 << 25) /* FPI slave bus access */
3062 +#define LTQ_RCU_RD_PPE_ATM_TC (1 << 23) /* PPE ATM TC */
3063 +#define LTQ_RCU_RD_PCIE (1 << 22) /* PCI-E core */
3064 +#define LTQ_RCU_RD_ETHSW (1 << 21) /* Ethernet switch */
3065 +#define LTQ_RCU_RD_DSP_DEN (1 << 20) /* Enable DSP JTAG */
3066 +#define LTQ_RCU_RD_TDM (1 << 19) /* TDM module interface */
3067 +#define LTQ_RCU_RD_ENMIP1 (1 << 18) /* Enable NMI of PLL1 */
3068 +#define LTQ_RCU_RD_SWBCK (1 << 17) /* Switch backward compat */
3069 +#define LTQ_RCU_RD_HSNAND (1 << 16) /* HSNAND controller */
3070 +#define LTQ_RCU_RD_ENMIP0 (1 << 15) /* Enable NMI of PLL0 */
3071 +#define LTQ_RCU_RD_MC (1 << 14) /* Memory Controller */
3072 +#define LTQ_RCU_RD_PCI (1 << 13) /* PCI core */
3073 +#define LTQ_RCU_RD_PCIE_PHY (1 << 12) /* PCI-E Phy */
3074 +#define LTQ_RCU_RD_DFE_CORE (1 << 11) /* DFE core */
3075 +#define LTQ_RCU_RD_SDIO (1 << 10) /* SDIO core */
3076 +#define LTQ_RCU_RD_DMA (1 << 9) /* DMA core */
3077 +#define LTQ_RCU_RD_PPE (1 << 8) /* PPE core */
3078 +#define LTQ_RCU_RD_DFE (1 << 7) /* DFE core */
3079 +#define LTQ_RCU_RD_AHB (1 << 6) /* AHB bus */
3080 +#define LTQ_RCU_RD_HRST_CFG (1 << 5) /* HW reset configuration */
3081 +#define LTQ_RCU_RD_USB (1 << 4) /* USB and Phy core */
3082 +#define LTQ_RCU_RD_PPE_DSP (1 << 3) /* PPE DSP interface */
3083 +#define LTQ_RCU_RD_FPI (1 << 2) /* FPI bus */
3084 +#define LTQ_RCU_RD_CPU (1 << 1) /* CPU subsystem */
3085 +#define LTQ_RCU_RD_HRST (1 << 0) /* HW reset via HRST pin */
3086 +
3087 +#define LTQ_RCU_STAT_BOOT_SHIFT 17
3088 +#define LTQ_RCU_STAT_BOOT_MASK (0xF << LTQ_RCU_STAT_BOOT_SHIFT)
3089 +#define LTQ_RCU_STAT_BOOT_H (1 << 12)
3090 +
3091 +#define LTQ_RCU_GP_STRAP_CLOCKSOURCE (1 << 15)
3092 +
3093 +struct ltq_rcu_regs {
3094 + u32 rsvd0[4];
3095 + u32 req; /* Reset request */
3096 + u32 stat; /* Reset status */
3097 + u32 usb0_cfg; /* USB0 configure */
3098 + u32 gp_strap; /* GPIO strapping */
3099 + u32 gfs_add0; /* GPHY0 firmware base addr */
3100 + u32 stat2; /* SLIC and USB reset status */
3101 + u32 pci_rdy; /* PCI boot ready */
3102 + u32 ppe_conf; /* PPE ethernet config */
3103 + u32 pcie_phy_con; /* PCIE PHY config/status */
3104 + u32 usb1_cfg; /* USB1 configure */
3105 + u32 usb_ana_cfg1a; /* USB analog config 1a */
3106 + u32 usb_ana_cfg1b; /* USB analog config 1b */
3107 + u32 rsvd1;
3108 + u32 gf_mdio_add; /* GPHY0/1 MDIO address */
3109 + u32 req2; /* SLIC and USB reset request */
3110 + u32 ahb_endian; /* AHB bus endianess */
3111 + u32 rsvd2[4];
3112 + u32 gcc; /* General CPU config */
3113 + u32 rsvd3;
3114 + u32 gfs_add1; /* GPHY1 firmware base addr */
3115 +};
3116 +
3117 +static struct ltq_rcu_regs *ltq_rcu_regs =
3118 + (struct ltq_rcu_regs *) CKSEG1ADDR(LTQ_RCU_BASE);
3119 +
3120 +u32 ltq_reset_map(enum ltq_reset_modules module)
3121 +{
3122 + u32 val;
3123 +
3124 + switch (module) {
3125 + case LTQ_RESET_CORE:
3126 + case LTQ_RESET_SOFT:
3127 + val = LTQ_RCU_RD_SRST | LTQ_RCU_RD_CPU | LTQ_RCU_RD_ENMIP2 |
3128 + LTQ_RCU_RD_GPHY1 | LTQ_RCU_RD_GPHY0;
3129 + break;
3130 + case LTQ_RESET_DMA:
3131 + val = LTQ_RCU_RD_DMA;
3132 + break;
3133 + case LTQ_RESET_ETH:
3134 + val = LTQ_RCU_RD_PPE | LTQ_RCU_RD_ETHSW;
3135 + break;
3136 + case LTQ_RESET_PHY:
3137 + val = LTQ_RCU_RD_GPHY1 | LTQ_RCU_RD_GPHY0;
3138 + break;
3139 + case LTQ_RESET_HARD:
3140 + val = LTQ_RCU_RD_HRST;
3141 + break;
3142 + default:
3143 + val = 0;
3144 + break;
3145 + }
3146 +
3147 + return val;
3148 +}
3149 +
3150 +int ltq_reset_activate(enum ltq_reset_modules module)
3151 +{
3152 + u32 val;
3153 +
3154 + val = ltq_reset_map(module);
3155 + if (unlikely(!val))
3156 + return 1;
3157 +
3158 + ltq_setbits(&ltq_rcu_regs->req, val);
3159 +
3160 + return 0;
3161 +}
3162 +
3163 +int ltq_reset_deactivate(enum ltq_reset_modules module)
3164 +{
3165 + u32 val;
3166 +
3167 + val = ltq_reset_map(module);
3168 + if (unlikely(!val))
3169 + return 1;
3170 +
3171 + ltq_clrbits(&ltq_rcu_regs->req, val);
3172 +
3173 + return 0;
3174 +}
3175 +
3176 +enum ltq_boot_select ltq_boot_select(void)
3177 +{
3178 + u32 stat;
3179 + unsigned int bootstrap;
3180 +
3181 + /*
3182 + * Boot select value is built from bits 20-17 and bit 12.
3183 + * The bit sequence is read as 4-2-1-0-3.
3184 + */
3185 + stat = ltq_readl(&ltq_rcu_regs->stat);
3186 + bootstrap = ((stat & LTQ_RCU_STAT_BOOT_H) << 4) |
3187 + ((stat & LTQ_RCU_STAT_BOOT_MASK) >> LTQ_RCU_STAT_BOOT_SHIFT);
3188 +
3189 + switch (bootstrap) {
3190 + case 0:
3191 + return BOOT_NOR_NO_BOOTROM;
3192 + case 1:
3193 + return BOOT_RGMII1;
3194 + case 2:
3195 + return BOOT_NOR;
3196 + case 4:
3197 + return BOOT_UART_NO_EEPROM;
3198 + case 6:
3199 + return BOOT_PCI;
3200 + case 8:
3201 + return BOOT_UART;
3202 + case 10:
3203 + return BOOT_SPI;
3204 + case 12:
3205 + return BOOT_NAND;
3206 + default:
3207 + return BOOT_UNKNOWN;
3208 + }
3209 +}
3210 +
3211 +void ltq_rcu_gphy_boot(unsigned int id, ulong addr)
3212 +{
3213 + u32 module;
3214 + void *gfs_add;
3215 +
3216 + switch (id) {
3217 + case 0:
3218 + module = LTQ_RCU_RD_GPHY0;
3219 + gfs_add = &ltq_rcu_regs->gfs_add0;
3220 + break;
3221 + case 1:
3222 + module = LTQ_RCU_RD_GPHY1;
3223 + gfs_add = &ltq_rcu_regs->gfs_add1;
3224 + break;
3225 + default:
3226 + BUG();
3227 + }
3228 +
3229 + /* Stop and reset GPHY */
3230 + ltq_setbits(&ltq_rcu_regs->req, module);
3231 +
3232 + /* Configure firmware and boot address */
3233 + ltq_writel(gfs_add, CPHYSADDR(addr & 0xFFFFC000));
3234 +
3235 + /* Start GPHY by releasing reset */
3236 + ltq_clrbits(&ltq_rcu_regs->req, module);
3237 +}
3238 --- /dev/null
3239 +++ b/arch/mips/include/asm/arch-danube/config.h
3240 @@ -0,0 +1,163 @@
3241 +/*
3242 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
3243 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3244 + *
3245 + * SPDX-License-Identifier: GPL-2.0+
3246 + *
3247 + * Common board configuration for Lantiq XWAY Danube family
3248 + *
3249 + * Use following defines in your board config to enable specific features
3250 + * and drivers for this SoC:
3251 + *
3252 + * CONFIG_LTQ_SUPPORT_UART
3253 + * - support the Danube ASC/UART interface and console
3254 + *
3255 + * CONFIG_LTQ_SUPPORT_NOR_FLASH
3256 + * - support a parallel NOR flash via the CFI interface in flash bank 0
3257 + *
3258 + * CONFIG_LTQ_SUPPORT_ETHERNET
3259 + * - support the Danube ETOP and MAC interface
3260 + *
3261 + * CONFIG_LTQ_SUPPORT_SPI_FLASH
3262 + * - support the Danube SPI interface and serial flash drivers
3263 + * - specific SPI flash drivers must be configured separately
3264 + */
3265 +
3266 +#ifndef __DANUBE_CONFIG_H__
3267 +#define __DANUBE_CONFIG_H__
3268 +
3269 +/* CPU and SoC type */
3270 +#define CONFIG_SOC_LANTIQ
3271 +#define CONFIG_SOC_XWAY_DANUBE
3272 +
3273 +/* Cache configuration */
3274 +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
3275 +#define CONFIG_SYS_DCACHE_SIZE (16 * 1024)
3276 +#define CONFIG_SYS_ICACHE_SIZE (16 * 1024)
3277 +#define CONFIG_SYS_CACHELINE_SIZE 32
3278 +#define CONFIG_SYS_MIPS_CACHE_EXT_INIT
3279 +
3280 +/*
3281 + * Supported clock modes
3282 + * PLL0 clock output is 333 MHz
3283 + * PLL1 clock output is 262.144 MHz
3284 + */
3285 +#define LTQ_CLK_CPU_333_DDR_167 0 /* Base PLL0, OCP 2 */
3286 +#define LTQ_CLK_CPU_111_DDR_111 1 /* Base PLL0, OCP 1 */
3287 +
3288 +/* CPU speed */
3289 +#define CONFIG_SYS_CLOCK_MODE LTQ_CLK_CPU_333_DDR_167
3290 +#define CONFIG_SYS_MIPS_TIMER_FREQ 166666667
3291 +#define CONFIG_SYS_HZ 1000
3292 +
3293 +/* RAM */
3294 +#define CONFIG_NR_DRAM_BANKS 1
3295 +#define CONFIG_SYS_SDRAM_BASE 0x80000000
3296 +#define CONFIG_SYS_MEMTEST_START 0x81000000
3297 +#define CONFIG_SYS_MEMTEST_END 0x82000000
3298 +#define CONFIG_SYS_LOAD_ADDR 0x81000000
3299 +#define CONFIG_SYS_INIT_SP_OFFSET 0x4000
3300 +
3301 +/* SRAM */
3302 +#define CONFIG_SYS_SRAM_BASE 0xBE1A0000
3303 +#define CONFIG_SYS_SRAM_SIZE 0x10000
3304 +
3305 +/* ASC/UART driver and console */
3306 +#define CONFIG_LANTIQ_SERIAL
3307 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
3308 +
3309 +/* GPIO */
3310 +#define CONFIG_LANTIQ_GPIO
3311 +#define CONFIG_LTQ_GPIO_MAX_BANKS 2
3312 +
3313 +/* FLASH driver */
3314 +#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
3315 +#define CONFIG_SYS_MAX_FLASH_BANKS 1
3316 +#define CONFIG_SYS_MAX_FLASH_SECT 256
3317 +#define CONFIG_SYS_FLASH_BASE 0xB0000000
3318 +#define CONFIG_FLASH_16BIT
3319 +#define CONFIG_SYS_FLASH_CFI
3320 +#define CONFIG_FLASH_CFI_DRIVER
3321 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
3322 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
3323 +#define CONFIG_FLASH_SHOW_PROGRESS 50
3324 +#define CONFIG_SYS_FLASH_PROTECTION
3325 +#define CONFIG_CFI_FLASH_USE_WEAK_ADDR_SWAP
3326 +
3327 +#define CONFIG_CMD_FLASH
3328 +#else
3329 +#define CONFIG_SYS_NO_FLASH
3330 +#endif /* CONFIG_NOR_FLASH */
3331 +
3332 +#if defined(CONFIG_LTQ_SUPPORT_SPI_FLASH)
3333 +#define CONFIG_LANTIQ_SPI
3334 +#define CONFIG_SPI_FLASH
3335 +
3336 +#define CONFIG_CMD_SF
3337 +#define CONFIG_CMD_SPI
3338 +#endif
3339 +
3340 +#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
3341 +#define CONFIG_NAND_LANTIQ
3342 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
3343 +#define CONFIG_SYS_NAND_BASE 0xB4000000
3344 +
3345 +#define CONFIG_CMD_NAND
3346 +#endif
3347 +
3348 +#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)
3349 +#define CONFIG_LANTIQ_DMA
3350 +#define CONFIG_LANTIQ_DANUBE_ETOP
3351 +
3352 +#define CONFIG_PHYLIB
3353 +#define CONFIG_MII
3354 +
3355 +#define CONFIG_CMD_MII
3356 +#define CONFIG_CMD_NET
3357 +#endif
3358 +
3359 +#define CONFIG_SPL_MAX_SIZE (32 * 1024)
3360 +#define CONFIG_SPL_BSS_MAX_SIZE (8 * 1024)
3361 +#define CONFIG_SPL_STACK_MAX_SIZE (8 * 1024)
3362 +#define CONFIG_SPL_MALLOC_MAX_SIZE (32 * 1024)
3363 +/*#define CONFIG_SPL_STACK_BSS_IN_SRAM*/
3364 +
3365 +#if defined(CONFIG_SPL_STACK_BSS_IN_SRAM)
3366 +#define CONFIG_SPL_STACK_BASE (CONFIG_SYS_SRAM_BASE + \
3367 + CONFIG_SPL_MAX_SIZE + \
3368 + CONFIG_SPL_STACK_MAX_SIZE - 1)
3369 +#define CONFIG_SPL_BSS_BASE (CONFIG_SPL_STACK_BASE + 1)
3370 +#define CONFIG_SPL_MALLOC_BASE (CONFIG_SYS_SDRAM_BASE + \
3371 + CONFIG_SYS_INIT_SP_OFFSET)
3372 +#else
3373 +#define CONFIG_SPL_STACK_BASE (CONFIG_SYS_SDRAM_BASE + \
3374 + CONFIG_SYS_INIT_SP_OFFSET + \
3375 + CONFIG_SPL_STACK_MAX_SIZE - 1)
3376 +#define CONFIG_SPL_BSS_BASE (CONFIG_SPL_STACK_BASE + 1)
3377 +#define CONFIG_SPL_MALLOC_BASE (CONFIG_SPL_BSS_BASE + \
3378 + CONFIG_SPL_BSS_MAX_SIZE)
3379 +#endif
3380 +
3381 +#if defined(CONFIG_SYS_BOOT_RAM)
3382 +#define CONFIG_SYS_TEXT_BASE 0xa0100000
3383 +#define CONFIG_SKIP_LOWLEVEL_INIT
3384 +#define CONFIG_SYS_DISABLE_CACHE
3385 +#endif
3386 +
3387 +#if defined(CONFIG_SYS_BOOT_NOR)
3388 +#define CONFIG_SYS_TEXT_BASE 0xB0000000
3389 +#endif