projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
uboot-lantiq: Add SoC version 1.2 support for Arcadyan VGV7510KW22
[openwrt/openwrt.git] / package / boot / uboot-lantiq / patches / 0043-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch
1 --- /dev/null
2 +++ b/board/arcadyan/vgv7510kw22/Makefile
3 @@ -0,0 +1,27 @@
4 +#
5 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
6 +#
7 +# SPDX-License-Identifier: GPL-2.0+
8 +#
9 +
10 +include $(TOPDIR)/config.mk
11 +
12 +LIB = $(obj)lib$(BOARD).o
13 +
14 +COBJS = $(BOARD).o
15 +
16 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
17 +OBJS := $(addprefix $(obj),$(COBJS))
18 +SOBJS := $(addprefix $(obj),$(SOBJS))
19 +
20 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
21 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
22 +
23 +#########################################################################
24 +
25 +# defines $(obj).depend target
26 +include $(SRCTREE)/rules.mk
27 +
28 +sinclude $(obj).depend
29 +
30 +#########################################################################
31 --- /dev/null
32 +++ b/board/arcadyan/vgv7510kw22/vgv7510kw22.c
33 @@ -0,0 +1,136 @@
34 +/*
35 + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
36 + *
37 + * SPDX-License-Identifier: GPL-2.0+
38 + */
39 +
40 +#include <common.h>
41 +#include <spi.h>
42 +#include <asm/gpio.h>
43 +#include <asm/lantiq/eth.h>
44 +#include <asm/lantiq/chipid.h>
45 +#include <asm/lantiq/cpu.h>
46 +#include <asm/arch/gphy.h>
47 +
48 +#if defined(CONFIG_SPL_BUILD)
49 +#define do_gpio_init 1
50 +#define do_pll_init 1
51 +#define do_dcdc_init 0
52 +#elif defined(CONFIG_SYS_BOOT_RAM)
53 +#define do_gpio_init 1
54 +#define do_pll_init 0
55 +#define do_dcdc_init 1
56 +#elif defined(CONFIG_SYS_BOOT_NOR)
57 +#define do_gpio_init 1
58 +#define do_pll_init 1
59 +#define do_dcdc_init 1
60 +#else
61 +#define do_gpio_init 0
62 +#define do_pll_init 0
63 +#define do_dcdc_init 1
64 +#endif
65 +
66 +#define GPIO_POWER_GREEN 14
67 +
68 +static void gpio_init(void)
69 +{
70 + /* SPI CS 0.4 to serial flash */
71 + gpio_direction_output(10, 1);
72 +
73 + /* Turn on the green power LED */
74 + gpio_direction_output(GPIO_POWER_GREEN, 0);
75 + gpio_set_value(GPIO_POWER_GREEN, 0);
76 +}
77 +
78 +int board_early_init_f(void)
79 +{
80 + if (do_gpio_init)
81 + gpio_init();
82 +
83 + if (do_pll_init)
84 + ltq_pll_init();
85 +
86 + if (do_dcdc_init)
87 + ltq_dcdc_init(0x7F);
88 +
89 + return 0;
90 +}
91 +
92 +int checkboard(void)
93 +{
94 + puts("Board: " CONFIG_BOARD_NAME "\n");
95 + ltq_chip_print_info();
96 +
97 + return 0;
98 +}
99 +
100 +static const struct ltq_eth_port_config eth_port_config[] = {
101 + /* unused */
102 + { 0, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
103 + /* unused */
104 + { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
105 + /* Internal GPHY0 with 10/100 firmware for LAN port 2 */
106 + { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
107 + /* Internal GPHY0 with 10/100 firmware for LAN port 1 */
108 + { 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
109 + /* Internal GPHY1 with 10/100 firmware for LAN port 4 */
110 + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
111 + /* Internal GPHY1 with 10/100 firmware for LAN port 3 */
112 + { 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
113 +};
114 +
115 +static const struct ltq_eth_board_config eth_board_config = {
116 + .ports = eth_port_config,
117 + .num_ports = ARRAY_SIZE(eth_port_config),
118 +};
119 +
120 +int board_eth_init(bd_t * bis)
121 +{
122 + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
123 + const ulong fw_addr = 0x80FF0000;
124 +
125 + if (ltq_chip_version_get() == 1)
126 + ltq_gphy_phy22f_a1x_load(fw_addr);
127 + else
128 + ltq_gphy_phy22f_a2x_load(fw_addr);
129 +
130 + ltq_cgu_gphy_clk_src(clk);
131 +
132 + ltq_rcu_gphy_boot(0, fw_addr);
133 + ltq_rcu_gphy_boot(1, fw_addr);
134 +
135 + return ltq_eth_initialize(&eth_board_config);
136 +}
137 +
138 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
139 +{
140 + if (bus)
141 + return 0;
142 +
143 + if (cs == 4)
144 + return 1;
145 +
146 + return 0;
147 +}
148 +
149 +void spi_cs_activate(struct spi_slave *slave)
150 +{
151 + switch (slave->cs) {
152 + case 4:
153 + gpio_set_value(10, 0);
154 + break;
155 + default:
156 + break;
157 + }
158 +}
159 +
160 +void spi_cs_deactivate(struct spi_slave *slave)
161 +{
162 + switch (slave->cs) {
163 + case 4:
164 + gpio_set_value(10, 1);
165 + break;
166 + default:
167 + break;
168 + }
169 +}
170 --- /dev/null
171 +++ b/board/arcadyan/vgv7510kw22/config.mk
172 @@ -0,0 +1,7 @@
173 +#
174 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
175 +#
176 +# SPDX-License-Identifier: GPL-2.0+
177 +#
178 +
179 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
180 --- /dev/null
181 +++ b/board/arcadyan/vgv7510kw22/ddr_settings.h
182 @@ -0,0 +1,71 @@
183 +/*
184 + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
185 + * Based on code by:
186 + * Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
187 + * and Lantiq Deutschland GmbH
188 + *
189 + * SPDX-License-Identifier: GPL-2.0+
190 + */
191 +
192 +#define MC_CCR00_VALUE 0x101
193 +#define MC_CCR01_VALUE 0x1000100
194 +#define MC_CCR02_VALUE 0x1010000
195 +#define MC_CCR03_VALUE 0x100
196 +#define MC_CCR04_VALUE 0x1000000
197 +#define MC_CCR05_VALUE 0x1000101
198 +#define MC_CCR06_VALUE 0x1000100
199 +#define MC_CCR07_VALUE 0x1010000
200 +#define MC_CCR08_VALUE 0x1000101
201 +#define MC_CCR09_VALUE 0x0
202 +#define MC_CCR10_VALUE 0x2000100
203 +#define MC_CCR11_VALUE 0x2000401
204 +#define MC_CCR12_VALUE 0x30000
205 +#define MC_CCR13_VALUE 0x202
206 +#define MC_CCR14_VALUE 0x7080A0F
207 +#define MC_CCR15_VALUE 0x2040F
208 +#define MC_CCR16_VALUE 0x40000
209 +#define MC_CCR17_VALUE 0x70102
210 +#define MC_CCR18_VALUE 0x4020002
211 +#define MC_CCR19_VALUE 0x30302
212 +#define MC_CCR20_VALUE 0x8000700
213 +#define MC_CCR21_VALUE 0x40F020A
214 +#define MC_CCR22_VALUE 0x0
215 +#define MC_CCR23_VALUE 0xC020000
216 +#define MC_CCR24_VALUE 0x4401B04
217 +#define MC_CCR25_VALUE 0x0
218 +#define MC_CCR26_VALUE 0x0
219 +#define MC_CCR27_VALUE 0x6420000
220 +#define MC_CCR28_VALUE 0x0
221 +#define MC_CCR29_VALUE 0x0
222 +#define MC_CCR30_VALUE 0x798
223 +#define MC_CCR31_VALUE 0x0
224 +#define MC_CCR32_VALUE 0x0
225 +#define MC_CCR33_VALUE 0x650000
226 +#define MC_CCR34_VALUE 0x200C8
227 +#define MC_CCR35_VALUE 0x1D445D
228 +#define MC_CCR36_VALUE 0xC8
229 +#define MC_CCR37_VALUE 0xC351
230 +#define MC_CCR38_VALUE 0x0
231 +#define MC_CCR39_VALUE 0x141F04
232 +#define MC_CCR40_VALUE 0x142704
233 +#define MC_CCR41_VALUE 0x141B42
234 +#define MC_CCR42_VALUE 0x141B42
235 +#define MC_CCR43_VALUE 0x566504
236 +#define MC_CCR44_VALUE 0x566504
237 +#define MC_CCR45_VALUE 0x565F17
238 +#define MC_CCR46_VALUE 0x565F17
239 +#define MC_CCR47_VALUE 0x0
240 +#define MC_CCR48_VALUE 0x0
241 +#define MC_CCR49_VALUE 0x0
242 +#define MC_CCR50_VALUE 0x0
243 +#define MC_CCR51_VALUE 0x0
244 +#define MC_CCR52_VALUE 0x133
245 +#define MC_CCR53_VALUE 0xF3014B27
246 +#define MC_CCR54_VALUE 0xF3014B27
247 +#define MC_CCR55_VALUE 0xF3014B27
248 +#define MC_CCR56_VALUE 0xF3014B27
249 +#define MC_CCR57_VALUE 0x7800301
250 +#define MC_CCR58_VALUE 0x7800301
251 +#define MC_CCR59_VALUE 0x7800301
252 +#define MC_CCR60_VALUE 0x7800301
253 +#define MC_CCR61_VALUE 0x4
254 --- a/boards.cfg
255 +++ b/boards.cfg
256 @@ -542,6 +542,9 @@
257 Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
258 Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
259 Active mips mips32 vrx200 arcadyan easybox904 easybox904_ram easybox904:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
260 +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_brn vgv7510kw22:SYS_BOOT_BRN Martin Blumenstingl <martin.blumenstingl@googlemail.com>
261 +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_nor vgv7510kw22:SYS_BOOT_NOR Martin Blumenstingl <martin.blumenstingl@googlemail.com>
262 +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_ram vgv7510kw22:SYS_BOOT_RAM Martin Blumenstingl <martin.blumenstingl@googlemail.com>
263 Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
264 Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
265 Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
266 --- /dev/null
267 +++ b/include/configs/vgv7510kw22.h
268 @@ -0,0 +1,78 @@
269 +/*
270 + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
271 + *
272 + * SPDX-License-Identifier: GPL-2.0+
273 + */
274 +
275 +#ifndef __CONFIG_H
276 +#define __CONFIG_H
277 +
278 +#define CONFIG_MACH_TYPE "VGV7510KW22"
279 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
280 +#define CONFIG_BOARD_NAME "Arcadyan VGV7510KW22"
281 +
282 +/* Configure SoC */
283 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
284 +
285 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
286 +
287 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
288 +
289 +#define CONFIG_LTQ_SUPPORT_SPI_FLASH
290 +#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29GL128EL parallel flash */
291 +
292 +#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
293 +#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */
294 +#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */
295 +
296 +#define CONFIG_SPL_SPI_BUS 0
297 +#define CONFIG_SPL_SPI_CS 4
298 +#define CONFIG_SPL_SPI_MAX_HZ 25000000
299 +#define CONFIG_SPL_SPI_MODE 0
300 +
301 +#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
302 +
303 +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
304 +
305 +/* Environment */
306 +#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
307 +#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
308 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
309 +#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
310 +
311 +#if defined(CONFIG_SYS_BOOT_BRN)
312 +#define CONFIG_SYS_TEXT_BASE 0x80002000
313 +#define CONFIG_SKIP_LOWLEVEL_INIT
314 +#define CONFIG_SYS_DISABLE_CACHE
315 +#define CONFIG_ENV_IS_NOWHERE
316 +#elif defined(CONFIG_SYS_BOOT_NOR)
317 +#define CONFIG_ENV_IS_IN_FLASH
318 +#define CONFIG_ENV_OVERWRITE
319 +#define CONFIG_ENV_OFFSET (384 * 1024)
320 +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
321 +#else
322 +#define CONFIG_ENV_IS_NOWHERE
323 +#endif
324 +
325 +#define CONFIG_ENV_SIZE (128 * 1024)
326 +
327 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
328 +
329 +/* Console */
330 +#define CONFIG_LTQ_ADVANCED_CONSOLE
331 +#define CONFIG_BAUDRATE 115200
332 +#define CONFIG_CONSOLE_ASC 1
333 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
334 +
335 +/* Pull in default board configs for Lantiq XWAY VRX200 */
336 +#include <asm/lantiq/config.h>
337 +#include <asm/arch/config.h>
338 +
339 +/* Pull in default OpenWrt configs for Lantiq SoC */
340 +#include "openwrt-lantiq-common.h"
341 +
342 +#define CONFIG_EXTRA_ENV_SETTINGS \
343 + CONFIG_ENV_LANTIQ_DEFAULTS \
344 + "kernel_addr=0xB0080000\0"
345 +
346 +#endif /* __CONFIG_H */
OpenWrt Source Repository