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[openwrt/openwrt.git] / package / boot / uboot-lantiq / patches / 0109-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch
1 From 09f411b4d10f10a62f147264121bb853b4649c3e Mon Sep 17 00:00:00 2001
2 From: Oliver Muth <dr.o.muth@gmx.de>
3 Date: Sat, 12 Oct 2013 16:49:53 +0200
4 Subject: MIPS: add board support for Arcadyan ARV752DPW22
5
6 Signed-off-by: Oliver Muth <dr.o.muth@gmx.de>
7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8
9 --- /dev/null
10 +++ b/board/arcadyan/arv752dpw22/Makefile
11 @@ -0,0 +1,27 @@
12 +#
13 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
14 +#
15 +# SPDX-License-Identifier: GPL-2.0+
16 +#
17 +
18 +include $(TOPDIR)/config.mk
19 +
20 +LIB = $(obj)lib$(BOARD).o
21 +
22 +COBJS = $(BOARD).o
23 +
24 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
25 +OBJS := $(addprefix $(obj),$(COBJS))
26 +SOBJS := $(addprefix $(obj),$(SOBJS))
27 +
28 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
29 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
30 +
31 +#########################################################################
32 +
33 +# defines $(obj).depend target
34 +include $(SRCTREE)/rules.mk
35 +
36 +sinclude $(obj).depend
37 +
38 +#########################################################################
39 --- /dev/null
40 +++ b/board/arcadyan/arv752dpw22/arv752dpw22.c
41 @@ -0,0 +1,52 @@
42 +/*
43 + * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
44 + * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de>
45 + *
46 + * SPDX-License-Identifier: GPL-2.0+
47 + */
48 +
49 +#include <common.h>
50 +#include <switch.h>
51 +#include <asm/gpio.h>
52 +#include <asm/lantiq/eth.h>
53 +#include <asm/lantiq/reset.h>
54 +#include <asm/lantiq/chipid.h>
55 +
56 +int board_early_init_f(void)
57 +{
58 + return 0;
59 +}
60 +
61 +int checkboard(void)
62 +{
63 + puts("Board: " CONFIG_BOARD_NAME "\n");
64 + ltq_chip_print_info();
65 +
66 + return 0;
67 +}
68 +
69 +static const struct ltq_eth_port_config eth_port_config[] = {
70 + /* MAC0: Atheros ar8216 switch */
71 + { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII },
72 +};
73 +
74 +static const struct ltq_eth_board_config eth_board_config = {
75 + .ports = eth_port_config,
76 + .num_ports = ARRAY_SIZE(eth_port_config),
77 +};
78 +
79 +int board_eth_init(bd_t *bis)
80 +{
81 + return ltq_eth_initialize(&eth_board_config);
82 +}
83 +
84 +static struct switch_device ar8216_dev = {
85 + .name = "ar8216",
86 + .cpu_port = 0,
87 + .port_mask = 0xF,
88 +};
89 +
90 +int board_switch_init(void)
91 +{
92 + return switch_device_register(&ar8216_dev);
93 +}
94 --- /dev/null
95 +++ b/board/arcadyan/arv752dpw22/config.mk
96 @@ -0,0 +1,7 @@
97 +#
98 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
99 +#
100 +# SPDX-License-Identifier: GPL-2.0+
101 +#
102 +
103 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
104 --- /dev/null
105 +++ b/board/arcadyan/arv752dpw22/ddr_settings.h
106 @@ -0,0 +1,55 @@
107 +/*
108 + * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
109 + *
110 + * This file has been generated with lantiq_ram_extract_magic.awk script.
111 + *
112 + * SPDX-License-Identifier: GPL-2.0+
113 + */
114 +
115 +#define MC_DC00_VALUE 0x1B1B
116 +#define MC_DC01_VALUE 0x0
117 +#define MC_DC02_VALUE 0x0
118 +#define MC_DC03_VALUE 0x0
119 +#define MC_DC04_VALUE 0x0
120 +#define MC_DC05_VALUE 0x200
121 +#define MC_DC06_VALUE 0x605
122 +#define MC_DC07_VALUE 0x303
123 +#define MC_DC08_VALUE 0x102
124 +#define MC_DC09_VALUE 0x70A
125 +#define MC_DC10_VALUE 0x203
126 +#define MC_DC11_VALUE 0xC02
127 +#define MC_DC12_VALUE 0x1C8
128 +#define MC_DC13_VALUE 0x1
129 +#define MC_DC14_VALUE 0x0
130 +#define MC_DC15_VALUE 0x134
131 +#define MC_DC16_VALUE 0xC800
132 +#define MC_DC17_VALUE 0xD
133 +#define MC_DC18_VALUE 0x301
134 +#define MC_DC19_VALUE 0x200
135 +#define MC_DC20_VALUE 0xA03
136 +#define MC_DC21_VALUE 0x1400
137 +#define MC_DC22_VALUE 0x1414
138 +#define MC_DC23_VALUE 0x0
139 +#define MC_DC24_VALUE 0x5B
140 +#define MC_DC25_VALUE 0x0
141 +#define MC_DC26_VALUE 0x0
142 +#define MC_DC27_VALUE 0x0
143 +#define MC_DC28_VALUE 0x510
144 +#define MC_DC29_VALUE 0x4E20
145 +#define MC_DC30_VALUE 0x8235
146 +#define MC_DC31_VALUE 0x0
147 +#define MC_DC32_VALUE 0x0
148 +#define MC_DC33_VALUE 0x0
149 +#define MC_DC34_VALUE 0x0
150 +#define MC_DC35_VALUE 0x0
151 +#define MC_DC36_VALUE 0x0
152 +#define MC_DC37_VALUE 0x0
153 +#define MC_DC38_VALUE 0x0
154 +#define MC_DC39_VALUE 0x0
155 +#define MC_DC40_VALUE 0x0
156 +#define MC_DC41_VALUE 0x0
157 +#define MC_DC42_VALUE 0x0
158 +#define MC_DC43_VALUE 0x0
159 +#define MC_DC44_VALUE 0x0
160 +#define MC_DC45_VALUE 0x500
161 +#define MC_DC46_VALUE 0x0
162 --- a/boards.cfg
163 +++ b/boards.cfg
164 @@ -511,6 +511,9 @@ Active mips mips32 danub
165 Active mips mips32 danube arcadyan arv752dpw arv752dpw_brn arv752dpw:SYS_BOOT_BRN -
166 Active mips mips32 danube arcadyan arv752dpw arv752dpw_nor arv752dpw:SYS_BOOT_NOR -
167 Active mips mips32 danube arcadyan arv752dpw arv752dpw_ram arv752dpw:SYS_BOOT_RAM -
168 +Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_brn arv752dpw22:SYS_BOOT_BRN -
169 +Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_nor arv752dpw22:SYS_BOOT_NOR -
170 +Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_ram arv752dpw22:SYS_BOOT_RAM -
171 Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle <daniel.golle@gmail.com>
172 Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle <daniel.golle@gmail.com>
173 Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
174 --- /dev/null
175 +++ b/include/configs/arv752dpw22.h
176 @@ -0,0 +1,68 @@
177 +/*
178 + * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
179 + *
180 + * SPDX-License-Identifier: GPL-2.0+
181 + */
182 +
183 +#ifndef __CONFIG_H
184 +#define __CONFIG_H
185 +
186 +#define CONFIG_MACH_TYPE "ARV752DPW22"
187 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
188 +#define CONFIG_BOARD_NAME "Arcadyan ARV752DPW22"
189 +
190 +/* Configure SoC */
191 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
192 +
193 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
194 +
195 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
196 +
197 +/* Switch devices */
198 +#define CONFIG_SWITCH_MULTI
199 +#define CONFIG_SWITCH_AR8216
200 +
201 +/* Environment */
202 +#if defined(CONFIG_SYS_BOOT_NOR)
203 +#define CONFIG_ENV_IS_IN_FLASH
204 +#define CONFIG_ENV_OVERWRITE
205 +#define CONFIG_ENV_OFFSET (192 * 1024)
206 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
207 +#else
208 +#define CONFIG_ENV_IS_NOWHERE
209 +#endif
210 +
211 +#define CONFIG_ENV_SIZE (8 * 1024)
212 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
213 +
214 +/* Burnboot loadable image */
215 +#if defined(CONFIG_SYS_BOOT_BRN)
216 +#define CONFIG_SYS_TEXT_BASE 0x80002000
217 +#define CONFIG_SKIP_LOWLEVEL_INIT
218 +#define CONFIG_SYS_DISABLE_CACHE
219 +#define CONFIG_ENV_OVERWRITE 1
220 +#endif
221 +
222 +
223 +/* Console */
224 +#define CONFIG_LTQ_ADVANCED_CONSOLE
225 +#define CONFIG_BAUDRATE 115200
226 +#define CONFIG_CONSOLE_ASC 1
227 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
228 +
229 +/* Pull in default board configs for Lantiq XWAY Danube */
230 +#include <asm/lantiq/config.h>
231 +#include <asm/arch/config.h>
232 +
233 +/* Pull in default OpenWrt configs for Lantiq SoC */
234 +#include "openwrt-lantiq-common.h"
235 +
236 +#define CONFIG_ENV_UPDATE_UBOOT_NOR \
237 + "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
238 +
239 +#define CONFIG_EXTRA_ENV_SETTINGS \
240 + CONFIG_ENV_LANTIQ_DEFAULTS \
241 + CONFIG_ENV_UPDATE_UBOOT_NOR \
242 + "kernel_addr=0xB0040000\0"
243 +
244 +#endif /* __CONFIG_H */
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