ccc3505a968edec70d334d68bc46802afd696da6
[openwrt/openwrt.git] / package / boot / uboot-lantiq / patches / 0112-MIPS-add-board-support-for-Arcadyan-VGV7510KW22.patch
1 --- /dev/null
2 +++ b/board/arcadyan/vgv7510kw22/Makefile
3 @@ -0,0 +1,27 @@
4 +#
5 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
6 +#
7 +# SPDX-License-Identifier: GPL-2.0+
8 +#
9 +
10 +include $(TOPDIR)/config.mk
11 +
12 +LIB = $(obj)lib$(BOARD).o
13 +
14 +COBJS = $(BOARD).o
15 +
16 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
17 +OBJS := $(addprefix $(obj),$(COBJS))
18 +SOBJS := $(addprefix $(obj),$(SOBJS))
19 +
20 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
21 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
22 +
23 +#########################################################################
24 +
25 +# defines $(obj).depend target
26 +include $(SRCTREE)/rules.mk
27 +
28 +sinclude $(obj).depend
29 +
30 +#########################################################################
31 --- /dev/null
32 +++ b/board/arcadyan/vgv7510kw22/vgv7510kw22.c
33 @@ -0,0 +1,120 @@
34 +/*
35 + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
36 + *
37 + * SPDX-License-Identifier: GPL-2.0+
38 + */
39 +
40 +#include <common.h>
41 +#include <asm/gpio.h>
42 +#include <asm/lantiq/eth.h>
43 +#include <asm/lantiq/chipid.h>
44 +#include <asm/lantiq/cpu.h>
45 +#include <asm/arch/gphy.h>
46 +
47 +#if defined(CONFIG_SPL_BUILD)
48 +#define do_gpio_init 1
49 +#define do_pll_init 1
50 +#define do_dcdc_init 0
51 +#elif defined(CONFIG_SYS_BOOT_RAM)
52 +#define do_gpio_init 1
53 +#define do_pll_init 0
54 +#define do_dcdc_init 1
55 +#elif defined(CONFIG_SYS_BOOT_NOR)
56 +#define do_gpio_init 1
57 +#define do_pll_init 1
58 +#define do_dcdc_init 1
59 +#else
60 +#define do_gpio_init 0
61 +#define do_pll_init 0
62 +#define do_dcdc_init 1
63 +#endif
64 +
65 +#define GPIO_POWER_GREEN 14
66 +#define GPIO_POWER_RED 28
67 +
68 +static void gpio_init(void)
69 +{
70 + /* Turn on the green power LED */
71 + gpio_direction_output(GPIO_POWER_GREEN, 0);
72 +
73 + /* Turn off the red power LED */
74 + gpio_direction_output(GPIO_POWER_RED, 1);
75 +}
76 +
77 +int board_early_init_f(void)
78 +{
79 + if (do_gpio_init)
80 + gpio_init();
81 +
82 + if (do_pll_init)
83 + ltq_pll_init();
84 +
85 + if (do_dcdc_init)
86 + ltq_dcdc_init(0x7F);
87 +
88 + return 0;
89 +}
90 +
91 +int checkboard(void)
92 +{
93 + puts("Board: " CONFIG_BOARD_NAME "\n");
94 + ltq_chip_print_info();
95 +
96 + return 0;
97 +}
98 +
99 +void show_boot_progress(int arg)
100 +{
101 + if (!do_gpio_init)
102 + return 0;
103 +
104 + if (arg >= 0) {
105 + /* Success - turn off the red power LED and turn on the green power LED */
106 + gpio_set_value(GPIO_POWER_RED, 1);
107 + gpio_set_value(GPIO_POWER_GREEN, 0);
108 + } else {
109 + /* Failure - turn off green power LED and turn on red power LED */
110 + gpio_set_value(GPIO_POWER_GREEN, 1);
111 + gpio_set_value(GPIO_POWER_RED, 0);
112 + }
113 +
114 + return 0;
115 +}
116 +
117 +static const struct ltq_eth_port_config eth_port_config[] = {
118 + /* unused */
119 + { 0, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
120 + /* unused */
121 + { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
122 + /* Internal GPHY0 with 10/100 firmware for LAN port 2 */
123 + { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
124 + /* Internal GPHY0 with 10/100 firmware for LAN port 1 */
125 + { 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
126 + /* Internal GPHY1 with 10/100 firmware for LAN port 4 */
127 + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
128 + /* Internal GPHY1 with 10/100 firmware for LAN port 3 */
129 + { 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII },
130 +};
131 +
132 +static const struct ltq_eth_board_config eth_board_config = {
133 + .ports = eth_port_config,
134 + .num_ports = ARRAY_SIZE(eth_port_config),
135 +};
136 +
137 +int board_eth_init(bd_t * bis)
138 +{
139 + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
140 + const ulong fw_addr = 0x80FF0000;
141 +
142 + if (ltq_chip_version_get() == 1)
143 + ltq_gphy_phy22f_a1x_load(fw_addr);
144 + else
145 + ltq_gphy_phy22f_a2x_load(fw_addr);
146 +
147 + ltq_cgu_gphy_clk_src(clk);
148 +
149 + ltq_rcu_gphy_boot(0, fw_addr);
150 + ltq_rcu_gphy_boot(1, fw_addr);
151 +
152 + return ltq_eth_initialize(&eth_board_config);
153 +}
154 --- /dev/null
155 +++ b/board/arcadyan/vgv7510kw22/config.mk
156 @@ -0,0 +1,7 @@
157 +#
158 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
159 +#
160 +# SPDX-License-Identifier: GPL-2.0+
161 +#
162 +
163 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
164 --- /dev/null
165 +++ b/board/arcadyan/vgv7510kw22/ddr_settings.h
166 @@ -0,0 +1,71 @@
167 +/*
168 + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
169 + * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>
170 + *
171 + * The values have been extracted from original brnboot.
172 + *
173 + * SPDX-License-Identifier: GPL-2.0+
174 + */
175 +
176 +#define MC_CCR00_VALUE 0x101
177 +#define MC_CCR01_VALUE 0x1000100
178 +#define MC_CCR02_VALUE 0x1010000
179 +#define MC_CCR03_VALUE 0x100
180 +#define MC_CCR04_VALUE 0x1000000
181 +#define MC_CCR05_VALUE 0x1000101
182 +#define MC_CCR06_VALUE 0x1000100
183 +#define MC_CCR07_VALUE 0x1010000
184 +#define MC_CCR08_VALUE 0x1000101
185 +#define MC_CCR09_VALUE 0x0
186 +#define MC_CCR10_VALUE 0x2000100
187 +#define MC_CCR11_VALUE 0x2000401
188 +#define MC_CCR12_VALUE 0x30000
189 +#define MC_CCR13_VALUE 0x202
190 +#define MC_CCR14_VALUE 0x7080A0F
191 +#define MC_CCR15_VALUE 0x2040F
192 +#define MC_CCR16_VALUE 0x40000
193 +#define MC_CCR17_VALUE 0x70102
194 +#define MC_CCR18_VALUE 0x4020002
195 +#define MC_CCR19_VALUE 0x30302
196 +#define MC_CCR20_VALUE 0x8000700
197 +#define MC_CCR21_VALUE 0x40F020A
198 +#define MC_CCR22_VALUE 0x0
199 +#define MC_CCR23_VALUE 0xC020000
200 +#define MC_CCR24_VALUE 0x4401B04
201 +#define MC_CCR25_VALUE 0x0
202 +#define MC_CCR26_VALUE 0x0
203 +#define MC_CCR27_VALUE 0x6420000
204 +#define MC_CCR28_VALUE 0x0
205 +#define MC_CCR29_VALUE 0x0
206 +#define MC_CCR30_VALUE 0x798
207 +#define MC_CCR31_VALUE 0x2040F
208 +#define MC_CCR32_VALUE 0x0
209 +#define MC_CCR33_VALUE 0x650000
210 +#define MC_CCR34_VALUE 0x200C8
211 +#define MC_CCR35_VALUE 0x1D445D
212 +#define MC_CCR36_VALUE 0xC8
213 +#define MC_CCR37_VALUE 0xC351
214 +#define MC_CCR38_VALUE 0x0
215 +#define MC_CCR39_VALUE 0x141F04
216 +#define MC_CCR40_VALUE 0x142704
217 +#define MC_CCR41_VALUE 0x141B42
218 +#define MC_CCR42_VALUE 0x141B42
219 +#define MC_CCR43_VALUE 0x566504
220 +#define MC_CCR44_VALUE 0x566504
221 +#define MC_CCR45_VALUE 0x565F17
222 +#define MC_CCR46_VALUE 0x565F17
223 +#define MC_CCR47_VALUE 0x2040F
224 +#define MC_CCR48_VALUE 0x0
225 +#define MC_CCR49_VALUE 0x0
226 +#define MC_CCR50_VALUE 0x0
227 +#define MC_CCR51_VALUE 0x0
228 +#define MC_CCR52_VALUE 0x133
229 +#define MC_CCR53_VALUE 0xF3014B27
230 +#define MC_CCR54_VALUE 0xF3014B27
231 +#define MC_CCR55_VALUE 0xF3014B27
232 +#define MC_CCR56_VALUE 0xF3014B27
233 +#define MC_CCR57_VALUE 0x7800301
234 +#define MC_CCR58_VALUE 0x7800301
235 +#define MC_CCR59_VALUE 0x7800301
236 +#define MC_CCR60_VALUE 0x7800301
237 +#define MC_CCR61_VALUE 0x4
238 --- a/boards.cfg
239 +++ b/boards.cfg
240 @@ -531,6 +531,9 @@ Active mips mips32 incai
241 Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
242 Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
243 Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
244 +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_brn vgv7510kw22:SYS_BOOT_BRN Martin Blumenstingl <martin.blumenstingl@googlemail.com>
245 +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_nor vgv7510kw22:SYS_BOOT_NOR Martin Blumenstingl <martin.blumenstingl@googlemail.com>
246 +Active mips mips32 vrx200 arcadyan vgv7510kw22 vgv7510kw22_ram vgv7510kw22:SYS_BOOT_RAM Martin Blumenstingl <martin.blumenstingl@googlemail.com>
247 Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
248 Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
249 Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
250 --- /dev/null
251 +++ b/include/configs/vgv7510kw22.h
252 @@ -0,0 +1,59 @@
253 +/*
254 + * Copyright (C) 2015 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
255 + *
256 + * SPDX-License-Identifier: GPL-2.0+
257 + */
258 +
259 +#ifndef __CONFIG_H
260 +#define __CONFIG_H
261 +
262 +#define CONFIG_MACH_TYPE "VGV7510KW22"
263 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
264 +#define CONFIG_BOARD_NAME "Arcadyan VGV7510KW22"
265 +
266 +/* Configure SoC */
267 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
268 +
269 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
270 +
271 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
272 +
273 +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
274 +
275 +#if defined(CONFIG_SYS_BOOT_BRN)
276 +#define CONFIG_SYS_TEXT_BASE 0x80002000
277 +#define CONFIG_SKIP_LOWLEVEL_INIT
278 +#define CONFIG_SYS_DISABLE_CACHE
279 +#define CONFIG_ENV_IS_NOWHERE
280 +#define CONFIG_ENV_OVERWRITE 1
281 +#elif defined(CONFIG_SYS_BOOT_NOR)
282 +#define CONFIG_ENV_IS_IN_FLASH
283 +#define CONFIG_ENV_OVERWRITE
284 +#define CONFIG_ENV_OFFSET (384 * 1024)
285 +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
286 +#else
287 +#define CONFIG_ENV_IS_NOWHERE
288 +#endif
289 +
290 +#define CONFIG_ENV_SIZE (128 * 1024)
291 +
292 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
293 +
294 +/* Console */
295 +#define CONFIG_LTQ_ADVANCED_CONSOLE
296 +#define CONFIG_BAUDRATE 115200
297 +#define CONFIG_CONSOLE_ASC 1
298 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
299 +
300 +/* Pull in default board configs for Lantiq XWAY VRX200 */
301 +#include <asm/lantiq/config.h>
302 +#include <asm/arch/config.h>
303 +
304 +/* Pull in default OpenWrt configs for Lantiq SoC */
305 +#include "openwrt-lantiq-common.h"
306 +
307 +#define CONFIG_EXTRA_ENV_SETTINGS \
308 + CONFIG_ENV_LANTIQ_DEFAULTS \
309 + "kernel_addr=0xB0080000\0"
310 +
311 +#endif /* __CONFIG_H */