package/boot/uboot-layerscape/patches/0006-armv8-fsl-layerscape-Put-SMMU-config-code-in-SMMU_BA.patch

   1 From be06181f45695ce71536ecb461615ebf6f18011e Mon Sep 17 00:00:00 2001
   2 From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
   3 Date: Tue, 15 Mar 2016 13:40:07 +0530
   4 Subject: [PATCH 06/93] armv8: fsl-layerscape: Put SMMU config code in
   5  SMMU_BASE
   6
   7 It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
   8 LS1012A are layerscape SoC without SMMU IP.
   9
  10 So put SMMU configuration code under SMMU_BASE.
  11
  12 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
  13 ---
  14  arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S |    2 ++
  15  1 file changed, 2 insertions(+)
  16
  17 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
  18 index 93f4a65..5f5bfb9 100644
  19 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
  20 +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
  21 @@ -95,11 +95,13 @@ ENTRY(lowlevel_init)
  22         bl      ccn504_set_qos
  23  #endif
  24
  25 +#ifdef SMMU_BASE
  26         /* Set the SMMU page size in the sACR register */
  27         ldr     x1, =SMMU_BASE
  28         ldr     w0, [x1, #0x10]
  29         orr     w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
  30         str     w0, [x1, #0x10]
  31 +#endif
  32
  33         /* Initialize GIC Secure Bank Status */
  34  #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
  35 --
  36 1.7.9.5
  37