package/boot/uboot-layerscape/patches/0020-armv8-ls1012a-Update-DDR-init-sequence.patch

   1 From e8703a5bba4bc0e9fa6aefe0eae7caf9141b8bdc Mon Sep 17 00:00:00 2001
   2 From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
   3 Date: Mon, 2 May 2016 18:28:16 +0530
   4 Subject: [PATCH 20/93] armv8: ls1012a: Update DDR init sequence
   5
   6 Current DDR init code uses lots of delay.
   7
   8 Use wait for bit clear instead of delays.
   9
  10 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
  11 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
  12 ---
  13  board/freescale/ls1012aqds/ls1012aqds.c |   67 +++++++++++++++++--------------
  14  board/freescale/ls1012ardb/ls1012ardb.c |   54 +++++++++++--------------
  15  2 files changed, 60 insertions(+), 61 deletions(-)
  16
  17 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
  18 index 6d5fef8..5cb225f 100644
  19 --- a/board/freescale/ls1012aqds/ls1012aqds.c
  20 +++ b/board/freescale/ls1012aqds/ls1012aqds.c
  21 @@ -28,6 +28,20 @@
  22
  23  DECLARE_GLOBAL_DATA_PTR;
  24
  25 +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
  26 +{
  27 +       int timeout = 1000;
  28 +
  29 +       out_be32(ptr, value);
  30 +
  31 +       while (in_be32(ptr) & bits) {
  32 +               udelay(100);
  33 +               timeout--;
  34 +       }
  35 +       if (timeout <= 0)
  36 +               puts("Error: wait for clear timeout.\n");
  37 +}
  38 +
  39  int checkboard(void)
  40  {
  41         puts("Board: LS1012AQDS\n");
  42 @@ -44,7 +58,7 @@ void mmdc_init(void)
  43         out_be32(&mmdc->mdscr, 0x00008000);
  44
  45         /* configure timing parms */
  46 -       out_be32(&mmdc->mdotc, 0x12554000);
  47 +       out_be32(&mmdc->mdotc,  0x12554000);
  48         out_be32(&mmdc->mdcfg0, 0xbabf7954);
  49         out_be32(&mmdc->mdcfg1, 0xff328f64);
  50         out_be32(&mmdc->mdcfg2, 0x01ff00db);
  51 @@ -56,7 +70,7 @@ void mmdc_init(void)
  52         out_be32(&mmdc->mpodtctrl, 0x0000022a);
  53
  54         /* out of reset delays */
  55 -       out_be32(&mmdc->mdor, 0x00bf1023);
  56 +       out_be32(&mmdc->mdor,  0x00bf1023);
  57
  58         /* physical parms */
  59         out_be32(&mmdc->mdctl, 0x05180000);
  60 @@ -73,69 +87,60 @@ void mmdc_init(void)
  61
  62         /* dram init sequence: ZQCL */
  63         out_be32(&mmdc->mdscr,      0x04008040);
  64 -       out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
  65 -
  66 -       mdelay(100);
  67 +       set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
  68
  69         /* Calibrations now: wr lvl */
  70         out_be32(&mmdc->mdscr,   0x00848031);
  71         out_be32(&mmdc->mdscr,   0x00008200);
  72 -       out_be32(&mmdc->mpwlgcr, 0x00000001);
  73 +       set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
  74
  75 -       mdelay(100);
  76 +       mdelay(1);
  77
  78         out_be32(&mmdc->mdscr, 0x00048031);
  79         out_be32(&mmdc->mdscr, 0x00008000);
  80
  81 -       /*    manual_refresh */
  82 -       out_be32(&mmdc->mdscr, 0x00008020);
  83 -
  84 -       mdelay(100);
  85 +       mdelay(1);
  86
  87         /* Calibrations now: Read DQS gating calibration */
  88         out_be32(&mmdc->mdscr,     0x04008050);
  89         out_be32(&mmdc->mdscr,     0x00048033);
  90         out_be32(&mmdc->mppdcmpr2, 0x00000001);
  91         out_be32(&mmdc->mprddlctl, 0x40404040);
  92 -       out_be32(&mmdc->mpdgctrl0, 0x10000000);
  93 -
  94 -       mdelay(100);
  95 +       set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
  96
  97         out_be32(&mmdc->mdscr, 0x00008033);
  98
  99 -       /*   manual_refresh */
 100 -       out_be32(&mmdc->mdscr, 0x00008020);
 101 -
 102 -       mdelay(100);
 103
 104         /* Calibrations now: Read calibration */
 105         out_be32(&mmdc->mdscr,       0x04008050);
 106         out_be32(&mmdc->mdscr,       0x00048033);
 107         out_be32(&mmdc->mppdcmpr2,   0x00000001);
 108 -       out_be32(&mmdc->mprddlhwctl, 0x00000010);
 109 -
 110 -       mdelay(400);
 111 +       set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
 112
 113         out_be32(&mmdc->mdscr, 0x00008033);
 114
 115 -       /* manual_refresh */
 116 -       out_be32(&mmdc->mdscr, 0x00008020);
 117 -
 118 -       mdelay(100);
 119 -
 120         /* PD, SR */
 121         out_be32(&mmdc->mdpdc, 0x00030035);
 122         out_be32(&mmdc->mapsr, 0x00001067);
 123
 124         /* refresh scheme */
 125 -       out_be32(&mmdc->mdref, 0x103e8000);
 126 -
 127 -       mdelay(400);
 128 +       set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
 129
 130         /* disable CON_REQ */
 131         out_be32(&mmdc->mdscr, 0x0);
 132 +}
 133
 134 -       mdelay(50);
 135 +int select_i2c_ch_pca9547(u8 ch)
 136 +{
 137 +       int ret;
 138 +
 139 +       ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
 140 +       if (ret) {
 141 +               puts("PCA: failed to select proper channel\n");
 142 +               return ret;
 143 +       }
 144 +
 145 +       return 0;
 146  }
 147
 148  int dram_init(void)
 149 @@ -183,6 +188,8 @@ int board_init(void)
 150  #ifdef CONFIG_ENV_IS_NOWHERE
 151         gd->env_addr = (ulong)&default_environment[0];
 152  #endif
 153 +       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 154 +
 155         return 0;
 156  }
 157
 158 diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
 159 index 4a7aaaa..f7b9bce 100644
 160 --- a/board/freescale/ls1012ardb/ls1012ardb.c
 161 +++ b/board/freescale/ls1012ardb/ls1012ardb.c
 162 @@ -23,6 +23,20 @@
 163
 164  DECLARE_GLOBAL_DATA_PTR;
 165
 166 +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
 167 +{
 168 +       int timeout = 1000;
 169 +
 170 +       out_be32(ptr, value);
 171 +
 172 +       while (in_be32(ptr) & bits) {
 173 +               udelay(100);
 174 +               timeout--;
 175 +       }
 176 +       if (timeout <= 0)
 177 +               puts("Error: wait for clear timeout.\n");
 178 +}
 179 +
 180  int checkboard(void)
 181  {
 182         u8 in1;
 183 @@ -67,7 +81,7 @@ void mmdc_init(void)
 184         out_be32(&mmdc->mdscr, 0x00008000);
 185
 186         /* configure timing parms */
 187 -       out_be32(&mmdc->mdotc, 0x12554000);
 188 +       out_be32(&mmdc->mdotc,  0x12554000);
 189         out_be32(&mmdc->mdcfg0, 0xbabf7954);
 190         out_be32(&mmdc->mdcfg1, 0xff328f64);
 191         out_be32(&mmdc->mdcfg2, 0x01ff00db);
 192 @@ -79,7 +93,7 @@ void mmdc_init(void)
 193         out_be32(&mmdc->mpodtctrl, 0x0000022a);
 194
 195         /* out of reset delays */
 196 -       out_be32(&mmdc->mdor, 0x00bf1023);
 197 +       out_be32(&mmdc->mdor,  0x00bf1023);
 198
 199         /* physical parms */
 200         out_be32(&mmdc->mdctl, 0x05180000);
 201 @@ -96,69 +110,47 @@ void mmdc_init(void)
 202
 203         /* dram init sequence: ZQCL */
 204         out_be32(&mmdc->mdscr,      0x04008040);
 205 -       out_be32(&mmdc->mpzqhwctrl, 0xa1390003);
 206 -
 207 -       mdelay(100);
 208 +       set_wait_for_bits_clear(&mmdc->mpzqhwctrl, 0xa1390003, 0x00010000);
 209
 210         /* Calibrations now: wr lvl */
 211         out_be32(&mmdc->mdscr,   0x00848031);
 212         out_be32(&mmdc->mdscr,   0x00008200);
 213 -       out_be32(&mmdc->mpwlgcr, 0x00000001);
 214 +       set_wait_for_bits_clear(&mmdc->mpwlgcr, 0x00000001, 0x00000001);
 215
 216 -       mdelay(100);
 217 +       mdelay(1);
 218
 219         out_be32(&mmdc->mdscr, 0x00048031);
 220         out_be32(&mmdc->mdscr, 0x00008000);
 221
 222 -       /*    manual_refresh */
 223 -       out_be32(&mmdc->mdscr, 0x00008020);
 224 -
 225 -       mdelay(100);
 226 +       mdelay(1);
 227
 228         /* Calibrations now: Read DQS gating calibration */
 229         out_be32(&mmdc->mdscr,     0x04008050);
 230         out_be32(&mmdc->mdscr,     0x00048033);
 231         out_be32(&mmdc->mppdcmpr2, 0x00000001);
 232         out_be32(&mmdc->mprddlctl, 0x40404040);
 233 -       out_be32(&mmdc->mpdgctrl0, 0x10000000);
 234 -
 235 -       mdelay(100);
 236 +       set_wait_for_bits_clear(&mmdc->mpdgctrl0, 0x10000000, 0x10000000);
 237
 238         out_be32(&mmdc->mdscr, 0x00008033);
 239
 240 -       /*   manual_refresh */
 241 -       out_be32(&mmdc->mdscr, 0x00008020);
 242 -
 243 -       mdelay(100);
 244
 245         /* Calibrations now: Read calibration */
 246         out_be32(&mmdc->mdscr,       0x04008050);
 247         out_be32(&mmdc->mdscr,       0x00048033);
 248         out_be32(&mmdc->mppdcmpr2,   0x00000001);
 249 -       out_be32(&mmdc->mprddlhwctl, 0x00000010);
 250 -
 251 -       mdelay(400);
 252 +       set_wait_for_bits_clear(&mmdc->mprddlhwctl, 0x00000010, 0x00000010);
 253
 254         out_be32(&mmdc->mdscr, 0x00008033);
 255
 256 -       /* manual_refresh */
 257 -       out_be32(&mmdc->mdscr, 0x00008020);
 258 -
 259 -       mdelay(100);
 260 -
 261         /* PD, SR */
 262         out_be32(&mmdc->mdpdc, 0x00030035);
 263         out_be32(&mmdc->mapsr, 0x00001067);
 264
 265         /* refresh scheme */
 266 -       out_be32(&mmdc->mdref, 0x103e8000);
 267 -
 268 -       mdelay(400);
 269 +       set_wait_for_bits_clear(&mmdc->mdref, 0x103e8000, 0x00000001);
 270
 271         /* disable CON_REQ */
 272         out_be32(&mmdc->mdscr, 0x0);
 273 -
 274 -       mdelay(50);
 275  }
 276
 277  int dram_init(void)
 278 --
 279 1.7.9.5
 280