layerscape: add 64b/32b target for ls1012ardb device
[openwrt/openwrt.git] / package / boot / uboot-layerscape / patches / 0047-Enable-second-SGMII-1G-interface.patch
1 From 61bb1dceefdb4c08ff69e7e40a766a404421206f Mon Sep 17 00:00:00 2001
2 From: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
3 Date: Fri, 27 May 2016 13:16:43 +0530
4 Subject: [PATCH 47/93] Enable second SGMII 1G interface
5
6 Enable second SGMII 1G interface on LS1012A Freedom Board
7
8 Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
9 ---
10 board/freescale/ls1012afrdm/eth.c | 14 ++++++++++++++
11 drivers/net/pfe_eth/pfe_eth.c | 2 +-
12 2 files changed, 15 insertions(+), 1 deletion(-)
13
14 diff --git a/board/freescale/ls1012afrdm/eth.c b/board/freescale/ls1012afrdm/eth.c
15 index 8ae3f45..90ed66b 100644
16 --- a/board/freescale/ls1012afrdm/eth.c
17 +++ b/board/freescale/ls1012afrdm/eth.c
18 @@ -19,6 +19,7 @@
19 #include <asm/arch-fsl-layerscape/immap_lsch2.h>
20
21 #define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
22 +#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1"
23
24 #define MASK_ETH_PHY_RST 0x00000100
25
26 @@ -71,6 +72,19 @@ int board_eth_init(bd_t *bis)
27 return -1;
28 }
29
30 + /*We don't really need this MDIO bus,
31 + * this is called just to initialize EMAC2 MDIO interface*/
32 + mac1_mdio_info.reg_base = (void *)0x04220000; /*EMAC2_BASE_ADDR*/
33 + mac1_mdio_info.name = DEFAULT_PFE_MDIO1_NAME;
34 +
35 + bus = ls1012a_mdio_init(&mac1_mdio_info);
36 + if(!bus)
37 + {
38 + printf("Failed to register mdio \n");
39 + return -1;
40 + }
41 +
42 +
43 /*MAC1 */
44 ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
45 ls1012a_set_phy_address_mode(0, EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
46 diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
47 index 40f2c39..4aa318d 100644
48 --- a/drivers/net/pfe_eth/pfe_eth.c
49 +++ b/drivers/net/pfe_eth/pfe_eth.c
50 @@ -348,7 +348,7 @@ static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv)
51
52 printf("%s %d\n", __func__, priv->gemac_port);
53 /* PCS configuration done with corresponding GEMAC */
54 - bus.priv = priv->gem->gemac_base;
55 + bus.priv = gem_info[priv->gemac_port].gemac_base;
56
57 ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
58 ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
59 --
60 1.7.9.5
61