package/boot/uboot-layerscape/patches/0060-ls1012-sata-add-sata-support.patch

   1 From 4733ade3cdc2b2fcc960d72b6ad9009a3ada38cf Mon Sep 17 00:00:00 2001
   2 From: Tang Yuantian <Yuantian.Tang@nxp.com>
   3 Date: Fri, 24 Jun 2016 10:59:46 +0800
   4 Subject: [PATCH 60/93] ls1012: sata: add sata support
   5
   6 So add sata configuation for ls1012 soc.
   7
   8 Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
   9 ---
  10  arch/arm/cpu/armv8/fsl-layerscape/soc.c        |    9 +++++++++
  11  arch/arm/include/asm/arch-fsl-layerscape/soc.h |    7 +++++++
  12  2 files changed, 16 insertions(+)
  13
  14 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
  15 index 0a170eb..ab902ce 100644
  16 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
  17 +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
  18 @@ -328,10 +328,19 @@ int sata_init(void)
  19  {
  20         struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA;
  21
  22 +#if defined(CONFIG_LS1043A)
  23         out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
  24         out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
  25         out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
  26         out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
  27 +#elif defined(CONFIG_LS1012A)
  28 +       out_le32(&ccsr_ahci->ppcfg, LS1012A_PORT_PHY1);
  29 +       out_le32(&ccsr_ahci->pp2c, LS1012A_PORT_PHY2);
  30 +       out_le32(&ccsr_ahci->pp3c, LS1012A_PORT_PHY3);
  31 +       out_le32(&ccsr_ahci->pp4c, LS1012A_PORT_PHY4);
  32 +       out_le32(&ccsr_ahci->pp5c, LS1012A_PORT_PHY5);
  33 +       out_le32(&ccsr_ahci->ptc, LS1012A_PORT_TRANS);
  34 +#endif
  35
  36         ahci_init((void __iomem *)CONFIG_SYS_SATA);
  37         scsi_scan(0);
  38 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
  39 index 0822b49..8071114 100644
  40 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
  41 +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
  42 @@ -60,6 +60,13 @@ struct cpu_type {
  43  #define AHCI_PORT_PHY_3_CFG    0x0e081509
  44  #define AHCI_PORT_TRANS_CFG    0x08000029
  45
  46 +#define LS1012A_PORT_PHY1      0xa003fffe
  47 +#define LS1012A_PORT_PHY2      0x28184d1b
  48 +#define LS1012A_PORT_PHY3      0x0e081906
  49 +#define LS1012A_PORT_PHY4      0x064a0813
  50 +#define LS1012A_PORT_PHY5      0x3ffc96a4
  51 +#define LS1012A_PORT_TRANS     0x08000029
  52 +
  53  /* AHCI (sata) register map */
  54  struct ccsr_ahci {
  55         u32 res1[0xa4/4];       /* 0x0 - 0xa4 */
  56 --
  57 1.7.9.5
  58