4954353611b03c8c9c15722a2050f94c24edf44a
[openwrt/openwrt.git] / package / boot / uboot-mvebu / patches / 200-clearfog-reset-usom-onboard-1512-phy.patch
1 From 98848106b9558244ae36a85229caabcdb57d0f7b Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Fri, 23 Sep 2016 13:58:14 +0200
4 Subject: [PATCH] clearfog: reset usom onboard 1512 phy
5
6 Use GPIO19 which is wired to the uSOM phy reset signal in order to reset
7 the uSOM's 88E81512 gigabit Ethernet phy.
8
9 This GPIO is valid on ClearFog rev 2.1 and newer.
10
11 Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
12 [jonas.gorski: adapted to upstream u-boot code]
13 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
14 ---
15 board/solidrun/clearfog/clearfog.c | 4 ++++
16 1 file changed, 4 insertions(+)
17
18 diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
19 index 2773f5957e..3a8257cac3 100644
20 --- a/board/solidrun/clearfog/clearfog.c
21 +++ b/board/solidrun/clearfog/clearfog.c
22 @@ -131,8 +131,12 @@ int board_init(void)
23 /* Toggle GPIO41 to reset onboard switch and phy */
24 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
25 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
26 + /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
27 + clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
28 + clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
29 mdelay(1);
30 setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
31 + setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
32 mdelay(10);
33
34 /* Init I2C IO expanders */
35 --
36 2.12.2
37