package/boot/uboot-oxnas/src/board/ox820/ddr.h

   1 /*******************************************************************
   2 *
   3 * File:                 ddr_oxsemi.h
   4 *
   5 * Description:          Declarations for DDR routines and data objects
   6 *
   7 * Author:               Julien Margetts
   8 *
   9 * Copyright:            Oxford Semiconductor Ltd, 2009
  10 */
  11
  12 void ddr_oxsemi_setup(int mhz);
  13
  14 /* define to refresh in bursts of 8 */
  15 #define BURST_REFRESH_ENABLE
  16
  17 #define DDR_BASE                        0x44700000
  18
  19 #define C_DDR_CFG_REG                   (DDR_BASE + 0x00)
  20 #define C_CFG_DDR                       0x80000000
  21 #define C_CFG_SDR                       0x00000000
  22 #define C_CFG_WIDTH8                    0x00200000
  23 #define C_CFG_WIDTH16                   0x00100000
  24 #define C_CFG_WIDTH32                   0x00000000
  25 #define C_CFG_SIZE_FACTOR               0x00020000
  26 #define C_CFG_REFRESH_ENABLE            0x00010000
  27 #define C_CFG_BURST_REFRESH_ENABLE      0x01000000
  28 #define C_CFG_SIZE(x)                   (x << 17)
  29 #define CFG_SIZE_2MB                    1
  30 #define CFG_SIZE_4MB                    2
  31 #define CFG_SIZE_8MB                    3
  32 #define CFG_SIZE_16MB                   4
  33 #define CFG_SIZE_32MB                   5
  34 #define CFG_SIZE_64MB                   6
  35 #define CFG_SIZE_128MB                  7
  36
  37 #define C_DDR_BLKEN_REG                 (DDR_BASE + 0x04)
  38 #define C_BLKEN_DDR_ON                  0x80000000
  39
  40 #define C_DDR_STAT_REG                  (DDR_BASE + 0x08)
  41
  42 #define C_DDR_CMD_REG                   (DDR_BASE + 0x0C)
  43 #define C_CMD_SEND_COMMAND              (1UL << 31) | (1 << 21) // RAS/CAS/WE/CS all low(active), CKE High, indicates
  44 #define C_CMD_WAKE_UP                   0x80FC0000 // Asserts CKE
  45 #define C_CMD_MODE_SDR                  0x80200022 // Sets CL=2 BL=4
  46 #define C_CMD_MODE_DDR                  0x80200063 // Sets CL=2.5 BL=8
  47 #define C_CMD_RESET_DLL                 0x00000100 // A8=1 Use in conjunction with C_CMD_MODE_DDR
  48 #define C_CMD_PRECHARGE_ALL             0x80280400
  49 #define C_CMD_AUTO_REFRESH              0x80240000
  50 #define C_CMD_SELF_REFRESH              0x80040000 // As AUTO-REFRESH but with CKE low
  51 #define C_CMD_NOP                       0x803C0000 // NOP just to insert guaranteed delay
  52 #define C_CMD_DDR2_EMR1                 0x80210000 // Load extended mode register 1 with zeros (for init), CKE still set
  53 //#define C_CMD_DDR2_EMR1               0x80210400 // Load extended mode register 1 with zeros (for init), CKE still set
  54 #define C_CMD_ENABLE_DLL                0x00000000 // Values used in conjuction with C_CMD_DDR2_EMR1
  55 #define C_CMD_DISABLE_DLL               0x00000001
  56 #define C_CMD_REDUCED_DRIVE             0x00000002
  57 #define C_CMD_ODT_DISABLED              0x00000000
  58 #define C_CMD_ODT_50                    0x00000044
  59 #define C_CMD_ODT_75                    0x00000004
  60 #define C_CMD_ODT_150                   0x00000040
  61 #define C_CMD_MODE_DDR2_OCD_DFLT        0x00000380
  62 #define C_CMD_MODE_DDR2_OCD_EXIT        0x00000000
  63
  64 #define C_CMD_DDR2_EMR2                 0x80220000 // Load extended mode register 2 with zeros (for init), CKE still set
  65 #define C_CMD_DDR2_EMR3                 0x80230000 // Load extended mode register 3 with zeros (for init), CKE still set
  66
  67 #define C_DDR_AHB_REG                   (DDR_BASE + 0x10)
  68 #define C_AHB_NO_RCACHES                0xFFFF0000
  69 #define C_AHB_FLUSH_ALL_RCACHES         0x0000FFFF
  70 #define C_AHB_FLUSH_AHB0_RCACHE         0x00000001
  71 #define C_AHB_FLUSH_AHB1_RCACHE         0x00000002
  72
  73 #define C_DDR_DLL_REG                   (DDR_BASE + 0x14)
  74 #define C_DLL_DISABLED                  0x00000000
  75 #define C_DLL_MANUAL                    0x80000000
  76 #define C_DLL_AUTO_OFFSET               0xA0000000
  77 #define C_DLL_AUTO_IN_REFRESH           0xC0000000
  78 #define C_DLL_AUTOMATIC                 0xE0000000
  79
  80 #define C_DDR_MON_REG                   (DDR_BASE + 0x18)
  81 #define C_MON_ALL                       0x00000010
  82 #define C_MON_CLIENT                    0x00000000
  83
  84 #define C_DDR_DIAG_REG                  (DDR_BASE + 0x1C)
  85 #define C_DDR_DIAG2_REG                 (DDR_BASE + 0x20)
  86
  87 #define C_DDR_IOC_REG                   (DDR_BASE + 0x24)
  88 #define C_DDR_IOC_PWR_DWN               (1 << 10)
  89 #define C_DDR_IOC_SEL_SSTL              (1 << 9)
  90 #define C_DDR_IOC_CK_DRIVE(x)           ((x) << 6)
  91 #define C_DDR_IOC_DQ_DRIVE(x)           ((x) << 3)
  92 #define C_DDR_IOC_XX_DRIVE(x)           ((x) << 0)
  93
  94 #define C_DDR_ARB_REG                   (DDR_BASE + 0x28)
  95 #define C_DDR_ARB_MIDBUF                (1 << 4)
  96 #define C_DDR_ARB_LRUBANK               (1 << 3)
  97 #define C_DDR_ARB_REQAGE                (1 << 2)
  98 #define C_DDR_ARB_DATDIR                (1 << 1)
  99 #define C_DDR_ARB_DATDIR_NC             (1 << 0)
 100
 101 #define C_TOP_ADDRESS_BIT_TEST          22
 102 #define C_MEM_BASE                      C_SDRAM_BASE
 103
 104 #define C_MEM_TEST_BASE                 0
 105 #define C_MEM_TEST_LEN                  1920
 106 #define C_MAX_RAND_ACCESS_LEN           16
 107
 108 #define C_DDR_REG_IGNORE                (DDR_BASE + 0x2C)
 109 #define C_DDR_AHB4_REG                  (DDR_BASE + 0x44)
 110
 111 #define C_DDR_REG_TIMING0               (DDR_BASE + 0x34)
 112 #define C_DDR_REG_TIMING1               (DDR_BASE + 0x38)
 113 #define C_DDR_REG_TIMING2               (DDR_BASE + 0x3C)
 114
 115 #define C_DDR_REG_PHY0                  (DDR_BASE + 0x48)
 116 #define C_DDR_REG_PHY1                  (DDR_BASE + 0x4C)
 117 #define C_DDR_REG_PHY2                  (DDR_BASE + 0x50)
 118 #define C_DDR_REG_PHY3                  (DDR_BASE + 0x54)
 119
 120 #define C_DDR_REG_GENERIC               (DDR_BASE + 0x60)
 121
 122 #define C_OXSEMI_DDRC_SIGNATURE         0x054415AA
 123
 124 #define DDR_PHY_BASE                    (DDR_BASE + 0x80000)
 125 #define DDR_PHY_TIMING                  (DDR_PHY_BASE + 0x48)
 126 #define DDR_PHY_TIMING_CK               (1 << 12)
 127 #define DDR_PHY_TIMING_INC              (1 << 13)
 128 #define DDR_PHY_TIMING_W_CE             (1 << 14)
 129 #define DDR_PHY_TIMING_W_RST            (1 << 15)
 130 #define DDR_PHY_TIMING_I_CE             (1 << 16)
 131 #define DDR_PHY_TIMING_I_RST            (1 << 17)
 132
 133 #define C_DDR_REG_PHY_TIMING            (DDR_PHY_BASE + 0x50)
 134 #define C_DDR_REG_PHY_WR_RATIO          (DDR_PHY_BASE + 0x74)
 135 #define C_DDR_REG_PHY_RD_RATIO          (DDR_PHY_BASE + 0x78)
 136
 137 #define C_DDR_TRANSACTION_ROUTING       (DDR_PHY_BASE + 0xC8)
 138 #define DDR_ROUTE_CPU0_INSTR_SHIFT      0
 139 #define DDR_ROUTE_CPU0_RDDATA_SHIFT     4
 140 #define DDR_ROUTE_CPU0_WRDATA_SHIFT     6
 141 #define DDR_ROUTE_CPU1_INSTR_SHIFT      8
 142 #define DDR_ROUTE_CPU1_RDDATA_SHIFT     12
 143 #define DDR_ROUTE_CPU1_WRDATA_SHIFT     14
 144
 145 unsigned int ddrc_signature(void);
 146 void set_ddr_timing(unsigned int w, unsigned int i);
 147 int pause(unsigned int us);
 148 void set_ddr_sel(int val);