package/boot/uboot-rockchip/patches/100-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch

   1 From 4189a8db90ca7edc16cf9509576ca2e74f028c1c Mon Sep 17 00:00:00 2001
   2 From: David Bauer <mail@david-bauer.net>
   3 Date: Thu, 7 Jan 2021 00:05:46 +0100
   4 Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S
   5
   6 This adds support for the NanoPi R2S from FriendlyArm.
   7
   8 Rockchip RK3328 SoC
   9 1GB DDR4 RAM
  10 Gigabit Ethernet (WAN)
  11 Gigabit Ethernet (USB3) (LAN)
  12 USB 2.0 Host Port
  13 MicroSD slot
  14 Reset button
  15 WAN - LAN - SYS LED
  16
  17 Signed-off-by: David Bauer <mail@david-bauer.net>
  18 ---
  19  arch/arm/dts/Makefile                      |   1 +
  20  arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi |  40 +++
  21  arch/arm/dts/rk3328-nanopi-r2s.dts         | 370 +++++++++++++++++++++
  22  board/rockchip/evb_rk3328/MAINTAINERS      |   7 +
  23  configs/nanopi-r2s-rk3328_defconfig        |  98 ++++++
  24  5 files changed, 516 insertions(+)
  25  create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
  26  create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts
  27  create mode 100644 configs/nanopi-r2s-rk3328_defconfig
  28
  29 --- a/arch/arm/dts/Makefile
  30 +++ b/arch/arm/dts/Makefile
  31 @@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
  32
  33  dtb-$(CONFIG_ROCKCHIP_RK3328) += \
  34         rk3328-evb.dtb \
  35 +       rk3328-nanopi-r2s.dtb \
  36         rk3328-roc-cc.dtb \
  37         rk3328-rock64.dtb \
  38         rk3328-rock-pi-e.dtb
  39 --- /dev/null
  40 +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
  41 @@ -0,0 +1,40 @@
  42 +// SPDX-License-Identifier: GPL-2.0+
  43 +/*
  44 + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
  45 + * (C) Copyright 2020 David Bauer
  46 + */
  47 +
  48 +#include "rk3328-u-boot.dtsi"
  49 +#include "rk3328-sdram-ddr4-666.dtsi"
  50 +/ {
  51 +       chosen {
  52 +               u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
  53 +       };
  54 +};
  55 +
  56 +&gpio0 {
  57 +       u-boot,dm-spl;
  58 +};
  59 +
  60 +&pinctrl {
  61 +       u-boot,dm-spl;
  62 +};
  63 +
  64 +&sdmmc0m1_gpio {
  65 +       u-boot,dm-spl;
  66 +};
  67 +
  68 +&pcfg_pull_up_4ma {
  69 +       u-boot,dm-spl;
  70 +};
  71 +
  72 +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
  73 +&vcc_sd {
  74 +       u-boot,dm-spl;
  75 +};
  76 +
  77 +&gmac2io {
  78 +       snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
  79 +       snps,reset-active-low;
  80 +       snps,reset-delays-us = <0 10000 50000>;
  81 +};
  82 --- /dev/null
  83 +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts
  84 @@ -0,0 +1,370 @@
  85 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  86 +/*
  87 + * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
  88 + */
  89 +
  90 +/dts-v1/;
  91 +
  92 +#include <dt-bindings/input/input.h>
  93 +#include <dt-bindings/gpio/gpio.h>
  94 +#include "rk3328.dtsi"
  95 +
  96 +/ {
  97 +       model = "FriendlyElec NanoPi R2S";
  98 +       compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
  99 +
 100 +       chosen {
 101 +               stdout-path = "serial2:1500000n8";
 102 +       };
 103 +
 104 +       gmac_clk: gmac-clock {
 105 +               compatible = "fixed-clock";
 106 +               clock-frequency = <125000000>;
 107 +               clock-output-names = "gmac_clkin";
 108 +               #clock-cells = <0>;
 109 +       };
 110 +
 111 +       keys {
 112 +               compatible = "gpio-keys";
 113 +               pinctrl-0 = <&reset_button_pin>;
 114 +               pinctrl-names = "default";
 115 +
 116 +               reset {
 117 +                       label = "reset";
 118 +                       gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
 119 +                       linux,code = <KEY_RESTART>;
 120 +                       debounce-interval = <50>;
 121 +               };
 122 +       };
 123 +
 124 +       leds {
 125 +               compatible = "gpio-leds";
 126 +               pinctrl-0 = <&lan_led_pin>,  <&sys_led_pin>, <&wan_led_pin>;
 127 +               pinctrl-names = "default";
 128 +
 129 +               lan_led: led-0 {
 130 +                       gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
 131 +                       label = "nanopi-r2s:green:lan";
 132 +               };
 133 +
 134 +               sys_led: led-1 {
 135 +                       gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
 136 +                       label = "nanopi-r2s:red:sys";
 137 +               };
 138 +
 139 +               wan_led: led-2 {
 140 +                       gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
 141 +                       label = "nanopi-r2s:green:wan";
 142 +               };
 143 +       };
 144 +
 145 +       vcc_io_sdio: sdmmcio-regulator {
 146 +               compatible = "regulator-gpio";
 147 +               enable-active-high;
 148 +               gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
 149 +               pinctrl-0 = <&sdio_vcc_pin>;
 150 +               pinctrl-names = "default";
 151 +               regulator-name = "vcc_io_sdio";
 152 +               regulator-always-on;
 153 +               regulator-min-microvolt = <1800000>;
 154 +               regulator-max-microvolt = <3300000>;
 155 +               regulator-settling-time-us = <5000>;
 156 +               regulator-type = "voltage";
 157 +               startup-delay-us = <2000>;
 158 +               states = <1800000 0x1
 159 +                         3300000 0x0>;
 160 +               vin-supply = <&vcc_io_33>;
 161 +       };
 162 +
 163 +       vcc_sd: sdmmc-regulator {
 164 +               compatible = "regulator-fixed";
 165 +               gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
 166 +               pinctrl-0 = <&sdmmc0m1_gpio>;
 167 +               pinctrl-names = "default";
 168 +               regulator-name = "vcc_sd";
 169 +               regulator-boot-on;
 170 +               regulator-min-microvolt = <3300000>;
 171 +               regulator-max-microvolt = <3300000>;
 172 +               vin-supply = <&vcc_io_33>;
 173 +       };
 174 +
 175 +       vdd_5v: vdd-5v {
 176 +               compatible = "regulator-fixed";
 177 +               regulator-name = "vdd_5v";
 178 +               regulator-always-on;
 179 +               regulator-boot-on;
 180 +               regulator-min-microvolt = <5000000>;
 181 +               regulator-max-microvolt = <5000000>;
 182 +       };
 183 +};
 184 +
 185 +&cpu0 {
 186 +       cpu-supply = <&vdd_arm>;
 187 +};
 188 +
 189 +&cpu1 {
 190 +       cpu-supply = <&vdd_arm>;
 191 +};
 192 +
 193 +&cpu2 {
 194 +       cpu-supply = <&vdd_arm>;
 195 +};
 196 +
 197 +&cpu3 {
 198 +       cpu-supply = <&vdd_arm>;
 199 +};
 200 +
 201 +&gmac2io {
 202 +       assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
 203 +       assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
 204 +       clock_in_out = "input";
 205 +       phy-handle = <&rtl8211e>;
 206 +       phy-mode = "rgmii";
 207 +       phy-supply = <&vcc_io_33>;
 208 +       pinctrl-0 = <&rgmiim1_pins>;
 209 +       pinctrl-names = "default";
 210 +       rx_delay = <0x18>;
 211 +       snps,aal;
 212 +       tx_delay = <0x24>;
 213 +       status = "okay";
 214 +
 215 +       mdio {
 216 +               compatible = "snps,dwmac-mdio";
 217 +               #address-cells = <1>;
 218 +               #size-cells = <0>;
 219 +
 220 +               rtl8211e: ethernet-phy@1 {
 221 +                       compatible = "ethernet-phy-id001c.c915",
 222 +                                    "ethernet-phy-ieee802.3-c22";
 223 +                       reg = <1>;
 224 +                       pinctrl-0 = <&eth_phy_reset_pin>;
 225 +                       pinctrl-names = "default";
 226 +                       reset-assert-us = <10000>;
 227 +                       reset-deassert-us = <50000>;
 228 +                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
 229 +               };
 230 +       };
 231 +};
 232 +
 233 +&i2c1 {
 234 +       status = "okay";
 235 +
 236 +       rk805: pmic@18 {
 237 +               compatible = "rockchip,rk805";
 238 +               reg = <0x18>;
 239 +               interrupt-parent = <&gpio1>;
 240 +               interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
 241 +               #clock-cells = <1>;
 242 +               clock-output-names = "xin32k", "rk805-clkout2";
 243 +               gpio-controller;
 244 +               #gpio-cells = <2>;
 245 +               pinctrl-0 = <&pmic_int_l>;
 246 +               pinctrl-names = "default";
 247 +               rockchip,system-power-controller;
 248 +               wakeup-source;
 249 +
 250 +               vcc1-supply = <&vdd_5v>;
 251 +               vcc2-supply = <&vdd_5v>;
 252 +               vcc3-supply = <&vdd_5v>;
 253 +               vcc4-supply = <&vdd_5v>;
 254 +               vcc5-supply = <&vcc_io_33>;
 255 +               vcc6-supply = <&vdd_5v>;
 256 +
 257 +               regulators {
 258 +                       vdd_log: DCDC_REG1 {
 259 +                               regulator-name = "vdd_log";
 260 +                               regulator-always-on;
 261 +                               regulator-boot-on;
 262 +                               regulator-min-microvolt = <712500>;
 263 +                               regulator-max-microvolt = <1450000>;
 264 +                               regulator-ramp-delay = <12500>;
 265 +
 266 +                               regulator-state-mem {
 267 +                                       regulator-on-in-suspend;
 268 +                                       regulator-suspend-microvolt = <1000000>;
 269 +                               };
 270 +                       };
 271 +
 272 +                       vdd_arm: DCDC_REG2 {
 273 +                               regulator-name = "vdd_arm";
 274 +                               regulator-always-on;
 275 +                               regulator-boot-on;
 276 +                               regulator-min-microvolt = <712500>;
 277 +                               regulator-max-microvolt = <1450000>;
 278 +                               regulator-ramp-delay = <12500>;
 279 +
 280 +                               regulator-state-mem {
 281 +                                       regulator-on-in-suspend;
 282 +                                       regulator-suspend-microvolt = <950000>;
 283 +                               };
 284 +                       };
 285 +
 286 +                       vcc_ddr: DCDC_REG3 {
 287 +                               regulator-name = "vcc_ddr";
 288 +                               regulator-always-on;
 289 +                               regulator-boot-on;
 290 +
 291 +                               regulator-state-mem {
 292 +                                       regulator-on-in-suspend;
 293 +                               };
 294 +                       };
 295 +
 296 +                       vcc_io_33: DCDC_REG4 {
 297 +                               regulator-name = "vcc_io_33";
 298 +                               regulator-always-on;
 299 +                               regulator-boot-on;
 300 +                               regulator-min-microvolt = <3300000>;
 301 +                               regulator-max-microvolt = <3300000>;
 302 +
 303 +                               regulator-state-mem {
 304 +                                       regulator-on-in-suspend;
 305 +                                       regulator-suspend-microvolt = <3300000>;
 306 +                               };
 307 +                       };
 308 +
 309 +                       vcc_18: LDO_REG1 {
 310 +                               regulator-name = "vcc_18";
 311 +                               regulator-always-on;
 312 +                               regulator-boot-on;
 313 +                               regulator-min-microvolt = <1800000>;
 314 +                               regulator-max-microvolt = <1800000>;
 315 +
 316 +                               regulator-state-mem {
 317 +                                       regulator-on-in-suspend;
 318 +                                       regulator-suspend-microvolt = <1800000>;
 319 +                               };
 320 +                       };
 321 +
 322 +                       vcc18_emmc: LDO_REG2 {
 323 +                               regulator-name = "vcc18_emmc";
 324 +                               regulator-always-on;
 325 +                               regulator-boot-on;
 326 +                               regulator-min-microvolt = <1800000>;
 327 +                               regulator-max-microvolt = <1800000>;
 328 +
 329 +                               regulator-state-mem {
 330 +                                       regulator-on-in-suspend;
 331 +                                       regulator-suspend-microvolt = <1800000>;
 332 +                               };
 333 +                       };
 334 +
 335 +                       vdd_10: LDO_REG3 {
 336 +                               regulator-name = "vdd_10";
 337 +                               regulator-always-on;
 338 +                               regulator-boot-on;
 339 +                               regulator-min-microvolt = <1000000>;
 340 +                               regulator-max-microvolt = <1000000>;
 341 +
 342 +                               regulator-state-mem {
 343 +                                       regulator-on-in-suspend;
 344 +                                       regulator-suspend-microvolt = <1000000>;
 345 +                               };
 346 +                       };
 347 +               };
 348 +       };
 349 +};
 350 +
 351 +&io_domains {
 352 +       pmuio-supply = <&vcc_io_33>;
 353 +       vccio1-supply = <&vcc_io_33>;
 354 +       vccio2-supply = <&vcc18_emmc>;
 355 +       vccio3-supply = <&vcc_io_sdio>;
 356 +       vccio4-supply = <&vcc_18>;
 357 +       vccio5-supply = <&vcc_io_33>;
 358 +       vccio6-supply = <&vcc_io_33>;
 359 +       status = "okay";
 360 +};
 361 +
 362 +&pinctrl {
 363 +       button {
 364 +               reset_button_pin: reset-button-pin {
 365 +                       rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
 366 +               };
 367 +       };
 368 +
 369 +       ethernet-phy {
 370 +               eth_phy_reset_pin: eth-phy-reset-pin {
 371 +                       rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
 372 +               };
 373 +       };
 374 +
 375 +       leds {
 376 +               lan_led_pin: lan-led-pin {
 377 +                       rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
 378 +               };
 379 +
 380 +               sys_led_pin: sys-led-pin {
 381 +                       rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 382 +               };
 383 +
 384 +               wan_led_pin: wan-led-pin {
 385 +                       rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
 386 +               };
 387 +       };
 388 +
 389 +       pmic {
 390 +               pmic_int_l: pmic-int-l {
 391 +                       rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
 392 +               };
 393 +       };
 394 +
 395 +       sd {
 396 +               sdio_vcc_pin: sdio-vcc-pin {
 397 +                       rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
 398 +               };
 399 +       };
 400 +};
 401 +
 402 +&pwm2 {
 403 +       status = "okay";
 404 +};
 405 +
 406 +&sdmmc {
 407 +       bus-width = <4>;
 408 +       cap-sd-highspeed;
 409 +       disable-wp;
 410 +       pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
 411 +       pinctrl-names = "default";
 412 +       sd-uhs-sdr12;
 413 +       sd-uhs-sdr25;
 414 +       sd-uhs-sdr50;
 415 +       sd-uhs-sdr104;
 416 +       vmmc-supply = <&vcc_sd>;
 417 +       vqmmc-supply = <&vcc_io_sdio>;
 418 +       status = "okay";
 419 +};
 420 +
 421 +&tsadc {
 422 +       rockchip,hw-tshut-mode = <0>;
 423 +       rockchip,hw-tshut-polarity = <0>;
 424 +       status = "okay";
 425 +};
 426 +
 427 +&u2phy {
 428 +       status = "okay";
 429 +};
 430 +
 431 +&u2phy_host {
 432 +       status = "okay";
 433 +};
 434 +
 435 +&u2phy_otg {
 436 +       status = "okay";
 437 +};
 438 +
 439 +&uart2 {
 440 +       status = "okay";
 441 +};
 442 +
 443 +&usb20_otg {
 444 +       status = "okay";
 445 +       dr_mode = "host";
 446 +};
 447 +
 448 +&usb_host0_ehci {
 449 +       status = "okay";
 450 +};
 451 +
 452 +&usb_host0_ohci {
 453 +       status = "okay";
 454 +};
 455 --- a/board/rockchip/evb_rk3328/MAINTAINERS
 456 +++ b/board/rockchip/evb_rk3328/MAINTAINERS
 457 @@ -5,6 +5,13 @@ F:      board/rockchip/evb_rk3328
 458  F:      include/configs/evb_rk3328.h
 459  F:      configs/evb-rk3328_defconfig
 460
 461 +NANOPI-R2S-RK3328
 462 +M:      David Bauer <mail@david-bauer.net>
 463 +S:      Maintained
 464 +F:      configs/nanopi-r2s-rk3328_defconfig
 465 +F:      arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
 466 +F:      arch/arm/dts/rk3328-nanopi-r2s.dts
 467 +
 468  ROC-RK3328-CC
 469  M:      Loic Devulder <ldevulder@suse.com>
 470  M:      Chen-Yu Tsai <wens@csie.org>
 471 --- /dev/null
 472 +++ b/configs/nanopi-r2s-rk3328_defconfig
 473 @@ -0,0 +1,98 @@
 474 +CONFIG_ARM=y
 475 +CONFIG_ARCH_ROCKCHIP=y
 476 +CONFIG_SYS_TEXT_BASE=0x00200000
 477 +CONFIG_SPL_GPIO_SUPPORT=y
 478 +CONFIG_ENV_OFFSET=0x3F8000
 479 +CONFIG_ROCKCHIP_RK3328=y
 480 +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
 481 +CONFIG_TPL_LIBCOMMON_SUPPORT=y
 482 +CONFIG_TPL_LIBGENERIC_SUPPORT=y
 483 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
 484 +CONFIG_SPL_STACK_R_ADDR=0x600000
 485 +CONFIG_NR_DRAM_BANKS=1
 486 +CONFIG_DEBUG_UART_BASE=0xFF130000
 487 +CONFIG_DEBUG_UART_CLOCK=24000000
 488 +CONFIG_SYSINFO=y
 489 +CONFIG_DEBUG_UART=y
 490 +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
 491 +# CONFIG_ANDROID_BOOT_IMAGE is not set
 492 +CONFIG_FIT=y
 493 +CONFIG_FIT_VERBOSE=y
 494 +CONFIG_SPL_LOAD_FIT=y
 495 +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
 496 +CONFIG_MISC_INIT_R=y
 497 +# CONFIG_DISPLAY_CPUINFO is not set
 498 +CONFIG_DISPLAY_BOARDINFO_LATE=y
 499 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 500 +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 501 +CONFIG_SPL_STACK_R=y
 502 +CONFIG_SPL_I2C_SUPPORT=y
 503 +CONFIG_SPL_POWER_SUPPORT=y
 504 +CONFIG_SPL_ATF=y
 505 +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 506 +CONFIG_CMD_BOOTZ=y
 507 +CONFIG_CMD_GPT=y
 508 +CONFIG_CMD_MMC=y
 509 +CONFIG_CMD_USB=y
 510 +# CONFIG_CMD_SETEXPR is not set
 511 +CONFIG_CMD_TIME=y
 512 +CONFIG_SPL_OF_CONTROL=y
 513 +CONFIG_TPL_OF_CONTROL=y
 514 +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
 515 +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 516 +CONFIG_TPL_OF_PLATDATA=y
 517 +CONFIG_ENV_IS_IN_MMC=y
 518 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 519 +CONFIG_NET_RANDOM_ETHADDR=y
 520 +CONFIG_TPL_DM=y
 521 +CONFIG_REGMAP=y
 522 +CONFIG_SPL_REGMAP=y
 523 +CONFIG_TPL_REGMAP=y
 524 +CONFIG_SYSCON=y
 525 +CONFIG_SPL_SYSCON=y
 526 +CONFIG_TPL_SYSCON=y
 527 +CONFIG_CLK=y
 528 +CONFIG_SPL_CLK=y
 529 +CONFIG_FASTBOOT_BUF_ADDR=0x800800
 530 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 531 +CONFIG_ROCKCHIP_GPIO=y
 532 +CONFIG_SYS_I2C_ROCKCHIP=y
 533 +CONFIG_MMC_DW=y
 534 +CONFIG_MMC_DW_ROCKCHIP=y
 535 +CONFIG_SF_DEFAULT_SPEED=20000000
 536 +CONFIG_DM_ETH=y
 537 +CONFIG_ETH_DESIGNWARE=y
 538 +CONFIG_GMAC_ROCKCHIP=y
 539 +CONFIG_PINCTRL=y
 540 +CONFIG_SPL_PINCTRL=y
 541 +CONFIG_DM_PMIC=y
 542 +CONFIG_PMIC_RK8XX=y
 543 +CONFIG_SPL_DM_REGULATOR=y
 544 +CONFIG_REGULATOR_PWM=y
 545 +CONFIG_DM_REGULATOR_FIXED=y
 546 +CONFIG_SPL_DM_REGULATOR_FIXED=y
 547 +CONFIG_REGULATOR_RK8XX=y
 548 +CONFIG_PWM_ROCKCHIP=y
 549 +CONFIG_RAM=y
 550 +CONFIG_SPL_RAM=y
 551 +CONFIG_TPL_RAM=y
 552 +CONFIG_DM_RESET=y
 553 +CONFIG_BAUDRATE=1500000
 554 +CONFIG_DEBUG_UART_SHIFT=2
 555 +CONFIG_SYSRESET=y
 556 +# CONFIG_TPL_SYSRESET is not set
 557 +CONFIG_USB=y
 558 +CONFIG_USB_XHCI_HCD=y
 559 +CONFIG_USB_XHCI_DWC3=y
 560 +CONFIG_USB_EHCI_HCD=y
 561 +CONFIG_USB_EHCI_GENERIC=y
 562 +CONFIG_USB_OHCI_HCD=y
 563 +CONFIG_USB_OHCI_GENERIC=y
 564 +CONFIG_USB_DWC2=y
 565 +CONFIG_USB_DWC3=y
 566 +# CONFIG_USB_DWC3_GADGET is not set
 567 +CONFIG_USB_GADGET=y
 568 +CONFIG_USB_GADGET_DWC2_OTG=y
 569 +CONFIG_SPL_TINY_MEMSET=y
 570 +CONFIG_TPL_TINY_MEMSET=y
 571 +CONFIG_ERRNO_STR=y