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fc99523e8e68bf75b8321a9e09b60f2bc62bf041
[openwrt/openwrt.git] / package / boot / uboot-sunxi / patches / 001-u-boot-trunk-3e1ded1fff32d8af8cc5eec22c56797621ea6649.patch
1 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
2 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c 2014-12-08 22:35:08.000000000 +0100
3 +++ u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c 2015-01-01 17:34:32.005507318 +0100
4 @@ -209,6 +209,10 @@
5 .gate = SW_ONLY_GATE(0x0360, 20, 4),
6 };
7
8 +static struct bus_clk_data usb_otg_ahb_data = {
9 + .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
10 +};
11 +
12 static struct bus_clk_data sdio1_ahb_data = {
13 .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
14 };
15 @@ -331,6 +335,17 @@
16 */
17
18 /* KPM bus clocks */
19 +static struct bus_clock usb_otg_ahb_clk = {
20 + .clk = {
21 + .name = "usb_otg_ahb_clk",
22 + .parent = &kpm_ccu_clk.clk,
23 + .ops = &bus_clk_ops,
24 + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
25 + },
26 + .freq_tbl = master_ahb_freq_tbl,
27 + .data = &usb_otg_ahb_data,
28 +};
29 +
30 static struct bus_clock sdio1_ahb_clk = {
31 .clk = {
32 .name = "sdio1_ahb_clk",
33 @@ -541,6 +556,7 @@
34 CLK_LK(bsc2),
35 CLK_LK(bsc3),
36 /* Bus clocks */
37 + CLK_LK(usb_otg_ahb),
38 CLK_LK(sdio1_ahb),
39 CLK_LK(sdio2_ahb),
40 CLK_LK(sdio3_ahb),
41 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c u-boot/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
42 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c 1970-01-01 01:00:00.000000000 +0100
43 +++ u-boot/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c 2015-01-01 17:34:32.005507318 +0100
44 @@ -0,0 +1,27 @@
45 +/*
46 + * Copyright 2014 Broadcom Corporation.
47 + *
48 + * SPDX-License-Identifier: GPL-2.0+
49 + */
50 +
51 +#include <common.h>
52 +#include <asm/errno.h>
53 +#include <asm/arch/sysmap.h>
54 +#include "clk-core.h"
55 +
56 +/* Enable appropriate clocks for the USB OTG port */
57 +int clk_usb_otg_enable(void *base)
58 +{
59 + char *ahbstr;
60 +
61 + switch ((u32) base) {
62 + case HSOTG_BASE_ADDR:
63 + ahbstr = "usb_otg_ahb_clk";
64 + break;
65 + default:
66 + printf("%s: base 0x%p not found\n", __func__, base);
67 + return -EINVAL;
68 + }
69 +
70 + return clk_get_and_enable(ahbstr);
71 +}
72 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/Makefile u-boot/arch/arm/cpu/armv7/bcm281xx/Makefile
73 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/Makefile 2014-12-08 22:35:08.000000000 +0100
74 +++ u-boot/arch/arm/cpu/armv7/bcm281xx/Makefile 2015-01-01 17:34:32.005507318 +0100
75 @@ -10,3 +10,4 @@
76 obj-y += clk-sdio.o
77 obj-y += clk-bsc.o
78 obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
79 +obj-y += clk-usb-otg.o
80 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/kona-common/clk-stubs.c u-boot/arch/arm/cpu/armv7/kona-common/clk-stubs.c
81 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/kona-common/clk-stubs.c 2014-12-08 22:35:08.000000000 +0100
82 +++ u-boot/arch/arm/cpu/armv7/kona-common/clk-stubs.c 2015-01-01 17:34:32.009507252 +0100
83 @@ -19,3 +19,8 @@
84 {
85 return 0;
86 }
87 +
88 +int __weak clk_usb_otg_enable(void *base)
89 +{
90 + return 0;
91 +}
92 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/cpu.c u-boot/arch/arm/cpu/armv7/ls102xa/cpu.c
93 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/cpu.c 2014-12-08 22:35:08.000000000 +0100
94 +++ u-boot/arch/arm/cpu/armv7/ls102xa/cpu.c 2015-01-01 17:34:32.009507252 +0100
95 @@ -12,6 +12,8 @@
96 #include <netdev.h>
97 #include <fsl_esdhc.h>
98
99 +#include "fsl_epu.h"
100 +
101 DECLARE_GLOBAL_DATA_PTR;
102
103 #if defined(CONFIG_DISPLAY_CPUINFO)
104 @@ -101,3 +103,35 @@
105
106 return 0;
107 }
108 +
109 +int arch_cpu_init(void)
110 +{
111 + void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
112 +
113 + /*
114 + * After wakeup from deep sleep, Clear EPU registers
115 + * as early as possible to prevent from possible issue.
116 + * It's also safe to clear at normal boot.
117 + */
118 + fsl_epu_clean(epu_base);
119 +
120 + return 0;
121 +}
122 +
123 +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
124 +/* Set the address at which the secondary core starts from.*/
125 +void smp_set_core_boot_addr(unsigned long addr, int corenr)
126 +{
127 + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
128 +
129 + out_be32(&gur->scratchrw[0], addr);
130 +}
131 +
132 +/* Release the secondary core from holdoff state and kick it */
133 +void smp_kick_all_cpus(void)
134 +{
135 + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
136 +
137 + out_be32(&gur->brrl, 0x2);
138 +}
139 +#endif
140 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fdt.c u-boot/arch/arm/cpu/armv7/ls102xa/fdt.c
141 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fdt.c 2014-12-08 22:35:08.000000000 +0100
142 +++ u-boot/arch/arm/cpu/armv7/ls102xa/fdt.c 2015-01-01 17:34:32.009507252 +0100
143 @@ -91,7 +91,7 @@
144 }
145
146 do_fixup_by_prop_u32(blob, "device_type", "soc",
147 - 4, "bus-frequency", busclk / 2, 1);
148 + 4, "bus-frequency", busclk, 1);
149
150 ft_fixup_enet_phy_connect_type(blob);
151
152 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.c u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
153 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.c 1970-01-01 01:00:00.000000000 +0100
154 +++ u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.c 2015-01-01 17:34:32.009507252 +0100
155 @@ -0,0 +1,57 @@
156 +/*
157 + * Copyright 2014 Freescale Semiconductor, Inc.
158 + *
159 + * SPDX-License-Identifier: GPL-2.0+
160 + */
161 +
162 +#include <common.h>
163 +#include <asm/io.h>
164 +
165 +#include "fsl_epu.h"
166 +
167 +/**
168 + * fsl_epu_clean - Clear EPU registers
169 + */
170 +void fsl_epu_clean(void *epu_base)
171 +{
172 + u32 offset;
173 +
174 + /* follow the exact sequence to clear the registers */
175 + /* Clear EPACRn */
176 + for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
177 + out_be32(epu_base + offset, 0);
178 +
179 + /* Clear EPEVTCRn */
180 + for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
181 + out_be32(epu_base + offset, 0);
182 +
183 + /* Clear EPGCR */
184 + out_be32(epu_base + EPGCR, 0);
185 +
186 + /* Clear EPSMCRn */
187 + for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
188 + out_be32(epu_base + offset, 0);
189 +
190 + /* Clear EPCCRn */
191 + for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
192 + out_be32(epu_base + offset, 0);
193 +
194 + /* Clear EPCMPRn */
195 + for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
196 + out_be32(epu_base + offset, 0);
197 +
198 + /* Clear EPCTRn */
199 + for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
200 + out_be32(epu_base + offset, 0);
201 +
202 + /* Clear EPIMCRn */
203 + for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
204 + out_be32(epu_base + offset, 0);
205 +
206 + /* Clear EPXTRIGCRn */
207 + out_be32(epu_base + EPXTRIGCR, 0);
208 +
209 + /* Clear EPECRn */
210 + for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
211 + out_be32(epu_base + offset, 0);
212 +}
213 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.h u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
214 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.h 1970-01-01 01:00:00.000000000 +0100
215 +++ u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.h 2015-01-01 17:34:32.009507252 +0100
216 @@ -0,0 +1,68 @@
217 +/*
218 + * Copyright 2014 Freescale Semiconductor, Inc.
219 + *
220 + * SPDX-License-Identifier: GPL-2.0+
221 + */
222 +
223 +#ifndef __FSL_EPU_H
224 +#define __FSL_EPU_H
225 +
226 +#include <asm/types.h>
227 +
228 +#define FSL_STRIDE_4B 4
229 +#define FSL_STRIDE_8B 8
230 +
231 +/* Block offsets */
232 +#define EPU_BLOCK_OFFSET 0x00000000
233 +
234 +/* EPGCR (Event Processor Global Control Register) */
235 +#define EPGCR 0x000
236 +
237 +/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
238 +#define EPEVTCR0 0x050
239 +#define EPEVTCR9 0x074
240 +#define EPEVTCR_STRIDE FSL_STRIDE_4B
241 +
242 +/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
243 +#define EPXTRIGCR 0x090
244 +
245 +/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
246 +#define EPIMCR0 0x100
247 +#define EPIMCR31 0x17C
248 +#define EPIMCR_STRIDE FSL_STRIDE_4B
249 +
250 +/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
251 +#define EPSMCR0 0x200
252 +#define EPSMCR15 0x278
253 +#define EPSMCR_STRIDE FSL_STRIDE_8B
254 +
255 +/* EPECR0-15 (Event Processor Event Control Registers) */
256 +#define EPECR0 0x300
257 +#define EPECR15 0x33C
258 +#define EPECR_STRIDE FSL_STRIDE_4B
259 +
260 +/* EPACR0-15 (Event Processor Action Control Registers) */
261 +#define EPACR0 0x400
262 +#define EPACR15 0x43C
263 +#define EPACR_STRIDE FSL_STRIDE_4B
264 +
265 +/* EPCCRi0-15 (Event Processor Counter Control Registers) */
266 +#define EPCCR0 0x800
267 +#define EPCCR15 0x83C
268 +#define EPCCR31 0x87C
269 +#define EPCCR_STRIDE FSL_STRIDE_4B
270 +
271 +/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
272 +#define EPCMPR0 0x900
273 +#define EPCMPR15 0x93C
274 +#define EPCMPR31 0x97C
275 +#define EPCMPR_STRIDE FSL_STRIDE_4B
276 +
277 +/* EPCTR0-31 (Event Processor Counter Register) */
278 +#define EPCTR0 0xA00
279 +#define EPCTR31 0xA7C
280 +#define EPCTR_STRIDE FSL_STRIDE_4B
281 +
282 +void fsl_epu_clean(void *epu_base);
283 +
284 +#endif
285 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/Makefile u-boot/arch/arm/cpu/armv7/ls102xa/Makefile
286 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/Makefile 2014-12-08 22:35:08.000000000 +0100
287 +++ u-boot/arch/arm/cpu/armv7/ls102xa/Makefile 2015-01-01 17:34:32.009507252 +0100
288 @@ -7,6 +7,8 @@
289 obj-y += cpu.o
290 obj-y += clock.o
291 obj-y += timer.o
292 +obj-y += fsl_epu.o
293
294 obj-$(CONFIG_OF_LIBFDT) += fdt.o
295 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
296 +obj-$(CONFIG_SPL) += spl.o
297 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/spl.c u-boot/arch/arm/cpu/armv7/ls102xa/spl.c
298 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/spl.c 1970-01-01 01:00:00.000000000 +0100
299 +++ u-boot/arch/arm/cpu/armv7/ls102xa/spl.c 2015-01-01 17:34:32.009507252 +0100
300 @@ -0,0 +1,33 @@
301 +/*
302 + * Copyright 2014 Freescale Semiconductor, Inc.
303 + *
304 + * SPDX-License-Identifier: GPL-2.0+
305 + */
306 +
307 +#include <common.h>
308 +#include <spl.h>
309 +
310 +u32 spl_boot_device(void)
311 +{
312 +#ifdef CONFIG_SPL_MMC_SUPPORT
313 + return BOOT_DEVICE_MMC1;
314 +#endif
315 + return BOOT_DEVICE_NAND;
316 +}
317 +
318 +u32 spl_boot_mode(void)
319 +{
320 + switch (spl_boot_device()) {
321 + case BOOT_DEVICE_MMC1:
322 +#ifdef CONFIG_SPL_FAT_SUPPORT
323 + return MMCSD_MODE_FAT;
324 +#else
325 + return MMCSD_MODE_RAW;
326 +#endif
327 + case BOOT_DEVICE_NAND:
328 + return 0;
329 + default:
330 + puts("spl: error: unsupported device\n");
331 + hang();
332 + }
333 +}
334 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/Makefile u-boot/arch/arm/cpu/armv7/Makefile
335 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/Makefile 2014-12-08 22:35:08.000000000 +0100
336 +++ u-boot/arch/arm/cpu/armv7/Makefile 2015-01-01 17:34:32.001507383 +0100
337 @@ -56,6 +56,7 @@
338 obj-$(CONFIG_RMOBILE) += rmobile/
339 obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
340 obj-$(CONFIG_SOCFPGA) += socfpga/
341 +obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
342 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
343 obj-$(CONFIG_TEGRA20) += tegra20/
344 obj-$(CONFIG_U8500) += u8500/
345 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/mx6/clock.c u-boot/arch/arm/cpu/armv7/mx6/clock.c
346 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/mx6/clock.c 2014-12-08 22:35:08.000000000 +0100
347 +++ u-boot/arch/arm/cpu/armv7/mx6/clock.c 2015-01-01 17:34:32.009507252 +0100
348 @@ -443,7 +443,7 @@
349 struct anatop_regs __iomem *anatop =
350 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
351
352 - if (freq < ENET_25MHz || freq > ENET_125MHz)
353 + if (freq < ENET_25MHZ || freq > ENET_125MHZ)
354 return -EINVAL;
355
356 reg = readl(&anatop->pll_enet);
357 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/nonsec_virt.S u-boot/arch/arm/cpu/armv7/nonsec_virt.S
358 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/nonsec_virt.S 2014-12-08 22:35:08.000000000 +0100
359 +++ u-boot/arch/arm/cpu/armv7/nonsec_virt.S 2015-01-01 17:34:32.013507186 +0100
360 @@ -169,11 +169,11 @@
361 * we do this here instead.
362 * But first check if we have the generic timer.
363 */
364 -#ifdef CONFIG_SYS_CLK_FREQ
365 +#ifdef CONFIG_TIMER_CLK_FREQ
366 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
367 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
368 cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
369 - ldreq r1, =CONFIG_SYS_CLK_FREQ
370 + ldreq r1, =CONFIG_TIMER_CLK_FREQ
371 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
372 #endif
373
374 @@ -191,6 +191,9 @@
375 wfi
376 ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
377 ldr r1, [r1]
378 +#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
379 + rev r1, r1
380 +#endif
381 cmp r0, r1 @ make sure we dont execute this code
382 beq smp_waitloop @ again (due to a spurious wakeup)
383 mov r0, r1
384 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/freeze_controller.c u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c
385 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/freeze_controller.c 2014-12-08 22:35:08.000000000 +0100
386 +++ u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c 2015-01-01 17:34:32.021507054 +0100
387 @@ -38,8 +38,7 @@
388 /* Freeze channel 0 to 2 */
389 for (channel_id = 0; channel_id <= 2; channel_id++) {
390 ioctrl_reg_offset = (u32)(
391 - &freeze_controller_base->vioctrl +
392 - (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
393 + &freeze_controller_base->vioctrl + channel_id);
394
395 /*
396 * Assert active low enrnsl, plniotri
397 @@ -120,8 +119,7 @@
398 /* Thaw channel 0 to 2 */
399 for (channel_id = 0; channel_id <= 2; channel_id++) {
400 ioctrl_reg_offset
401 - = (u32)(&freeze_controller_base->vioctrl
402 - + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
403 + = (u32)(&freeze_controller_base->vioctrl + channel_id);
404
405 /*
406 * Assert active low bhniotri signal and
407 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/reset_manager.c u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c
408 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/reset_manager.c 2014-12-08 22:35:08.000000000 +0100
409 +++ u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c 2015-01-01 17:34:32.021507054 +0100
410 @@ -110,6 +110,6 @@
411 {
412 const void *reset = &reset_manager_base->per_mod_reset;
413
414 - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
415 - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
416 + clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
417 + (1 << RSTMGR_PERMODRST_SPIM1_LSB));
418 }
419 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/clock.c u-boot/arch/arm/cpu/armv7/stv0991/clock.c
420 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/clock.c 1970-01-01 01:00:00.000000000 +0100
421 +++ u-boot/arch/arm/cpu/armv7/stv0991/clock.c 2015-01-01 17:34:32.025506990 +0100
422 @@ -0,0 +1,41 @@
423 +/*
424 + * (C) Copyright 2014
425 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
426 + *
427 + * SPDX-License-Identifier: GPL-2.0+
428 + */
429 +
430 +#include <asm/io.h>
431 +#include <asm/arch/hardware.h>
432 +#include <asm/arch/stv0991_cgu.h>
433 +#include<asm/arch/stv0991_periph.h>
434 +
435 +static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
436 + (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
437 +
438 +void enable_pll1(void)
439 +{
440 + /* pll1 already configured for 1000Mhz, just need to enable it */
441 + writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
442 + &stv0991_cgu_regs->pll1_ctrl);
443 +}
444 +
445 +void clock_setup(int peripheral)
446 +{
447 + switch (peripheral) {
448 + case UART_CLOCK_CFG:
449 + writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
450 + break;
451 + case ETH_CLOCK_CFG:
452 + enable_pll1();
453 + writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
454 +
455 + /* Clock selection for ethernet tx_clk & rx_clk*/
456 + writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
457 + | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
458 +
459 + break;
460 + default:
461 + break;
462 + }
463 +}
464 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/lowlevel.S u-boot/arch/arm/cpu/armv7/stv0991/lowlevel.S
465 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/lowlevel.S 1970-01-01 01:00:00.000000000 +0100
466 +++ u-boot/arch/arm/cpu/armv7/stv0991/lowlevel.S 2015-01-01 17:34:32.025506990 +0100
467 @@ -0,0 +1,12 @@
468 +/*
469 + * (C) Copyright 2014 stmicroelectronics
470 + *
471 + * SPDX-License-Identifier: GPL-2.0+
472 + */
473 +
474 +#include <config.h>
475 +#include <linux/linkage.h>
476 +
477 +ENTRY(lowlevel_init)
478 + mov pc, lr
479 +ENDPROC(lowlevel_init)
480 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/Makefile u-boot/arch/arm/cpu/armv7/stv0991/Makefile
481 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/Makefile 1970-01-01 01:00:00.000000000 +0100
482 +++ u-boot/arch/arm/cpu/armv7/stv0991/Makefile 2015-01-01 17:34:32.025506990 +0100
483 @@ -0,0 +1,9 @@
484 +#
485 +# (C) Copyright 2014
486 +# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
487 +#
488 +# SPDX-License-Identifier: GPL-2.0+
489 +#
490 +
491 +obj-y := timer.o clock.o pinmux.o reset.o
492 +obj-y += lowlevel.o
493 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/pinmux.c u-boot/arch/arm/cpu/armv7/stv0991/pinmux.c
494 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/pinmux.c 1970-01-01 01:00:00.000000000 +0100
495 +++ u-boot/arch/arm/cpu/armv7/stv0991/pinmux.c 2015-01-01 17:34:32.025506990 +0100
496 @@ -0,0 +1,62 @@
497 +/*
498 + * (C) Copyright 2014
499 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
500 + *
501 + * SPDX-License-Identifier: GPL-2.0+
502 + */
503 +
504 +#include <asm/io.h>
505 +#include <asm/arch/stv0991_creg.h>
506 +#include <asm/arch/stv0991_periph.h>
507 +#include <asm/arch/hardware.h>
508 +
509 +static struct stv0991_creg *const stv0991_creg = \
510 + (struct stv0991_creg *)CREG_BASE_ADDR;
511 +
512 +int stv0991_pinmux_config(int peripheral)
513 +{
514 + switch (peripheral) {
515 + case UART_GPIOC_30_31:
516 + /* SSDA/SSCL pad muxing to UART Rx/Dx */
517 + writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
518 + CFG_GPIOC_31_UART_RX,
519 + &stv0991_creg->mux12);
520 + writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
521 + CFG_GPIOC_30_UART_TX,
522 + &stv0991_creg->mux12);
523 + /* SSDA/SSCL pad config to push pull*/
524 + writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
525 + CFG_GPIOC_31_MODE_PP,
526 + &stv0991_creg->cfg_pad6);
527 + writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
528 + CFG_GPIOC_30_MODE_HIGH,
529 + &stv0991_creg->cfg_pad6);
530 + break;
531 + case UART_GPIOB_16_17:
532 + /* ethernet rx_6/7 to UART Rx/Dx */
533 + writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
534 + CFG_GPIOB_17_UART_RX,
535 + &stv0991_creg->mux7);
536 + writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
537 + CFG_GPIOB_16_UART_TX,
538 + &stv0991_creg->mux7);
539 + break;
540 + case ETH_GPIOB_10_31_C_0_4:
541 + writel(readl(&stv0991_creg->mux6) & 0x000000FF,
542 + &stv0991_creg->mux6);
543 + writel(0x00000000, &stv0991_creg->mux7);
544 + writel(0x00000000, &stv0991_creg->mux8);
545 + writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
546 + &stv0991_creg->mux9);
547 + /* Ethernet Voltage configuration to 1.8V*/
548 + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
549 + ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
550 + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
551 + ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
552 +
553 + break;
554 + default:
555 + break;
556 + }
557 + return 0;
558 +}
559 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/reset.c u-boot/arch/arm/cpu/armv7/stv0991/reset.c
560 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/reset.c 1970-01-01 01:00:00.000000000 +0100
561 +++ u-boot/arch/arm/cpu/armv7/stv0991/reset.c 2015-01-01 17:34:32.025506990 +0100
562 @@ -0,0 +1,26 @@
563 +/*
564 + * (C) Copyright 2014
565 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
566 + *
567 + * SPDX-License-Identifier: GPL-2.0+
568 + */
569 +
570 +#include <common.h>
571 +#include <asm/io.h>
572 +#include <asm/arch/stv0991_wdru.h>
573 +void reset_cpu(ulong ignored)
574 +{
575 + puts("System is going to reboot ...\n");
576 + /*
577 + * This 1 second delay will allow the above message
578 + * to be printed before reset
579 + */
580 + udelay((1000 * 1000));
581 +
582 + /* Setting bit 1 of the WDRU unit will reset the SoC */
583 + writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1);
584 +
585 + /* system will restart */
586 + while (1)
587 + ;
588 +}
589 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/timer.c u-boot/arch/arm/cpu/armv7/stv0991/timer.c
590 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/timer.c 1970-01-01 01:00:00.000000000 +0100
591 +++ u-boot/arch/arm/cpu/armv7/stv0991/timer.c 2015-01-01 17:34:32.025506990 +0100
592 @@ -0,0 +1,114 @@
593 +/*
594 + * (C) Copyright 2014
595 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
596 + *
597 + * SPDX-License-Identifier: GPL-2.0+
598 + */
599 +
600 +#include <common.h>
601 +#include <asm/io.h>
602 +#include <asm/arch-stv0991/hardware.h>
603 +#include <asm/arch-stv0991/stv0991_cgu.h>
604 +#include <asm/arch-stv0991/stv0991_gpt.h>
605 +
606 +static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
607 + (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
608 +
609 +#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
610 +#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ)
611 +
612 +DECLARE_GLOBAL_DATA_PTR;
613 +
614 +#define timestamp gd->arch.tbl
615 +#define lastdec gd->arch.lastinc
616 +
617 +int timer_init(void)
618 +{
619 + /* Timer1 clock configuration */
620 + writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq);
621 + writel(readl(&stv0991_cgu_regs->cgu_enable_2) |
622 + TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2);
623 +
624 + /* Stop the timer */
625 + writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
626 + writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc);
627 + /* Configure timer for auto-reload */
628 + writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
629 + &gpt1_regs_ptr->cr1);
630 +
631 + /* load value for free running */
632 + writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
633 +
634 + /* start timer */
635 + writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN,
636 + &gpt1_regs_ptr->cr1);
637 +
638 + /* Reset the timer */
639 + lastdec = READ_TIMER();
640 + timestamp = 0;
641 +
642 + return 0;
643 +}
644 +
645 +/*
646 + * timer without interrupts
647 + */
648 +ulong get_timer(ulong base)
649 +{
650 + return (get_timer_masked() / GPT_RESOLUTION) - base;
651 +}
652 +
653 +void __udelay(unsigned long usec)
654 +{
655 + ulong tmo;
656 + ulong start = get_timer_masked();
657 + ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100);
658 + ulong rndoff;
659 +
660 + rndoff = (usec % 10) ? 1 : 0;
661 +
662 + /* tenudelcnt timer tick gives 10 microsecconds delay */
663 + tmo = ((usec / 10) + rndoff) * tenudelcnt;
664 +
665 + while ((ulong) (get_timer_masked() - start) < tmo)
666 + ;
667 +}
668 +
669 +ulong get_timer_masked(void)
670 +{
671 + ulong now = READ_TIMER();
672 +
673 + if (now >= lastdec) {
674 + /* normal mode */
675 + timestamp += now - lastdec;
676 + } else {
677 + /* we have an overflow ... */
678 + timestamp += now + GPT_FREE_RUNNING - lastdec;
679 + }
680 + lastdec = now;
681 +
682 + return timestamp;
683 +}
684 +
685 +void udelay_masked(unsigned long usec)
686 +{
687 + return udelay(usec);
688 +}
689 +
690 +/*
691 + * This function is derived from PowerPC code (read timebase as long long).
692 + * On ARM it just returns the timer value.
693 + */
694 +unsigned long long get_ticks(void)
695 +{
696 + return get_timer(0);
697 +}
698 +
699 +/*
700 + * This function is derived from PowerPC code (timebase clock frequency).
701 + * On ARM it returns the number of timer ticks per second.
702 + */
703 +ulong get_tbclk(void)
704 +{
705 + return CONFIG_STV0991_HZ;
706 +}
707 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/tegra124/Kconfig u-boot/arch/arm/cpu/armv7/tegra124/Kconfig
708 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/tegra124/Kconfig 2014-12-08 22:35:08.000000000 +0100
709 +++ u-boot/arch/arm/cpu/armv7/tegra124/Kconfig 2015-01-01 17:34:32.025506990 +0100
710 @@ -6,6 +6,15 @@
711 config TARGET_JETSON_TK1
712 bool "NVIDIA Tegra124 Jetson TK1 board"
713
714 +config TARGET_NYAN_BIG
715 + bool "Google/NVIDIA Nyan-big Chrombook"
716 + help
717 + Nyan Big is a Tegra124 clamshell board that is very similar
718 + to venice2, but it has a different panel, the sdcard CD and WP
719 + sense are flipped, and it has a different revision of the AS3722
720 + PMIC. The retail name is the Acer Chromebook 13 CB5-311-T7NN
721 + (13.3-inch HD, NVIDIA Tegra K1, 2GB).
722 +
723 config TARGET_VENICE2
724 bool "NVIDIA Tegra124 Venice2"
725
726 @@ -15,6 +24,7 @@
727 default "tegra124"
728
729 source "board/nvidia/jetson-tk1/Kconfig"
730 +source "board/nvidia/nyan-big/Kconfig"
731 source "board/nvidia/venice2/Kconfig"
732
733 endif
734 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/uniphier/init_page_table.c u-boot/arch/arm/cpu/armv7/uniphier/init_page_table.c
735 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/uniphier/init_page_table.c 2014-12-08 22:35:08.000000000 +0100
736 +++ u-boot/arch/arm/cpu/armv7/uniphier/init_page_table.c 2015-01-01 17:34:32.029506924 +0100
737 @@ -17,11 +17,7 @@
738 #define REG DEVICE /* IO Register: Device */
739 #define DDR DEVICE /* DDR SDRAM: Device */
740
741 -#ifdef CONFIG_SPL_BUILD
742 #define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SPL_TEXT_BASE) >> 20))
743 -#else
744 -#define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SYS_TEXT_BASE) >> 20))
745 -#endif
746
747 #define IS_INIT_STACK_AREA(x) ((x) == ((CONFIG_SYS_INIT_SP_ADDR) >> 20))
748
749 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/vf610/generic.c u-boot/arch/arm/cpu/armv7/vf610/generic.c
750 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/vf610/generic.c 2014-12-08 22:35:08.000000000 +0100
751 +++ u-boot/arch/arm/cpu/armv7/vf610/generic.c 2015-01-01 17:34:32.029506924 +0100
752 @@ -265,20 +265,21 @@
753
754 cause = readl(&src_regs->srsr);
755 writel(cause, &src_regs->srsr);
756 - cause &= 0xff;
757
758 - switch (cause) {
759 - case 0x08:
760 - return "WDOG";
761 - case 0x20:
762 + if (cause & SRC_SRSR_POR_RST)
763 + return "POWER ON RESET";
764 + else if (cause & SRC_SRSR_WDOG_A5)
765 + return "WDOG A5";
766 + else if (cause & SRC_SRSR_WDOG_M4)
767 + return "WDOG M4";
768 + else if (cause & SRC_SRSR_JTAG_RST)
769 return "JTAG HIGH-Z";
770 - case 0x80:
771 + else if (cause & SRC_SRSR_SW_RST)
772 + return "SW RESET";
773 + else if (cause & SRC_SRSR_RESETB)
774 return "EXTERNAL RESET";
775 - case 0xfd:
776 - return "POR";
777 - default:
778 + else
779 return "unknown reset";
780 - }
781 }
782
783 int print_cpuinfo(void)
784 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/tegra20-common/pmu.c u-boot/arch/arm/cpu/tegra20-common/pmu.c
785 --- u-boot-2015.01-rc3/arch/arm/cpu/tegra20-common/pmu.c 2014-12-08 22:35:08.000000000 +0100
786 +++ u-boot/arch/arm/cpu/tegra20-common/pmu.c 2015-01-01 17:34:32.037506793 +0100
787 @@ -6,6 +6,7 @@
788 */
789
790 #include <common.h>
791 +#include <i2c.h>
792 #include <tps6586x.h>
793 #include <asm/io.h>
794 #include <asm/arch/tegra.h>
795 @@ -23,9 +24,13 @@
796 #define VDD_TRANSITION_STEP 0x06 /* 150mv */
797 #define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */
798
799 +#define PMI_I2C_ADDRESS 0x34 /* chip requires this address */
800 +
801 int pmu_set_nominal(void)
802 {
803 - int core, cpu, bus;
804 + struct udevice *bus, *dev;
805 + int core, cpu;
806 + int ret;
807
808 /* by default, the table has been filled with T25 settings */
809 switch (tegra_get_chip_sku()) {
810 @@ -42,12 +47,18 @@
811 return -1;
812 }
813
814 - bus = tegra_i2c_get_dvc_bus_num();
815 - if (bus == -1) {
816 + ret = tegra_i2c_get_dvc_bus(&bus);
817 + if (ret) {
818 debug("%s: Cannot find DVC I2C bus\n", __func__);
819 - return -1;
820 + return ret;
821 }
822 - tps6586x_init(bus);
823 + ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, &dev);
824 + if (ret) {
825 + debug("%s: Cannot find DVC I2C chip\n", __func__);
826 + return ret;
827 + }
828 +
829 + tps6586x_init(dev);
830 tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
831 return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
832 VDD_TRANSITION_RATE, VDD_RELATION);
833 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/u-boot-spl.lds u-boot/arch/arm/cpu/u-boot-spl.lds
834 --- u-boot-2015.01-rc3/arch/arm/cpu/u-boot-spl.lds 2014-12-08 22:35:08.000000000 +0100
835 +++ u-boot/arch/arm/cpu/u-boot-spl.lds 2015-01-01 17:34:32.037506793 +0100
836 @@ -32,6 +32,9 @@
837 }
838
839 . = ALIGN(4);
840 + .u_boot_list : {
841 + KEEP(*(SORT(.u_boot_list*_i2c_*)));
842 + }
843
844 . = .;
845 #ifdef CONFIG_SPL_DM
846 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/cros-ec-keyboard.dtsi u-boot/arch/arm/dts/cros-ec-keyboard.dtsi
847 --- u-boot-2015.01-rc3/arch/arm/dts/cros-ec-keyboard.dtsi 1970-01-01 01:00:00.000000000 +0100
848 +++ u-boot/arch/arm/dts/cros-ec-keyboard.dtsi 2015-01-01 17:34:32.037506793 +0100
849 @@ -0,0 +1,105 @@
850 +/*
851 + * Keyboard dts fragment for devices that use cros-ec-keyboard
852 + *
853 + * Copyright (c) 2014 Google, Inc
854 + *
855 + * This program is free software; you can redistribute it and/or modify
856 + * it under the terms of the GNU General Public License version 2 as
857 + * published by the Free Software Foundation.
858 +*/
859 +
860 +#include <dt-bindings/input/input.h>
861 +
862 +&cros_ec {
863 + keyboard-controller {
864 + compatible = "google,cros-ec-keyb";
865 + keypad,num-rows = <8>;
866 + keypad,num-columns = <13>;
867 + google,needs-ghost-filter;
868 +
869 + linux,keymap = <
870 + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
871 + MATRIX_KEY(0x00, 0x02, KEY_F1)
872 + MATRIX_KEY(0x00, 0x03, KEY_B)
873 + MATRIX_KEY(0x00, 0x04, KEY_F10)
874 + MATRIX_KEY(0x00, 0x06, KEY_N)
875 + MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
876 + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
877 +
878 + MATRIX_KEY(0x01, 0x01, KEY_ESC)
879 + MATRIX_KEY(0x01, 0x02, KEY_F4)
880 + MATRIX_KEY(0x01, 0x03, KEY_G)
881 + MATRIX_KEY(0x01, 0x04, KEY_F7)
882 + MATRIX_KEY(0x01, 0x06, KEY_H)
883 + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
884 + MATRIX_KEY(0x01, 0x09, KEY_F9)
885 + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
886 +
887 + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
888 + MATRIX_KEY(0x02, 0x01, KEY_TAB)
889 + MATRIX_KEY(0x02, 0x02, KEY_F3)
890 + MATRIX_KEY(0x02, 0x03, KEY_T)
891 + MATRIX_KEY(0x02, 0x04, KEY_F6)
892 + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
893 + MATRIX_KEY(0x02, 0x06, KEY_Y)
894 + MATRIX_KEY(0x02, 0x07, KEY_102ND)
895 + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
896 + MATRIX_KEY(0x02, 0x09, KEY_F8)
897 +
898 + MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
899 + MATRIX_KEY(0x03, 0x02, KEY_F2)
900 + MATRIX_KEY(0x03, 0x03, KEY_5)
901 + MATRIX_KEY(0x03, 0x04, KEY_F5)
902 + MATRIX_KEY(0x03, 0x06, KEY_6)
903 + MATRIX_KEY(0x03, 0x08, KEY_MINUS)
904 + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
905 +
906 + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
907 + MATRIX_KEY(0x04, 0x01, KEY_A)
908 + MATRIX_KEY(0x04, 0x02, KEY_D)
909 + MATRIX_KEY(0x04, 0x03, KEY_F)
910 + MATRIX_KEY(0x04, 0x04, KEY_S)
911 + MATRIX_KEY(0x04, 0x05, KEY_K)
912 + MATRIX_KEY(0x04, 0x06, KEY_J)
913 + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
914 + MATRIX_KEY(0x04, 0x09, KEY_L)
915 + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
916 + MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
917 +
918 + MATRIX_KEY(0x05, 0x01, KEY_Z)
919 + MATRIX_KEY(0x05, 0x02, KEY_C)
920 + MATRIX_KEY(0x05, 0x03, KEY_V)
921 + MATRIX_KEY(0x05, 0x04, KEY_X)
922 + MATRIX_KEY(0x05, 0x05, KEY_COMMA)
923 + MATRIX_KEY(0x05, 0x06, KEY_M)
924 + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
925 + MATRIX_KEY(0x05, 0x08, KEY_SLASH)
926 + MATRIX_KEY(0x05, 0x09, KEY_DOT)
927 + MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
928 +
929 + MATRIX_KEY(0x06, 0x01, KEY_1)
930 + MATRIX_KEY(0x06, 0x02, KEY_3)
931 + MATRIX_KEY(0x06, 0x03, KEY_4)
932 + MATRIX_KEY(0x06, 0x04, KEY_2)
933 + MATRIX_KEY(0x06, 0x05, KEY_8)
934 + MATRIX_KEY(0x06, 0x06, KEY_7)
935 + MATRIX_KEY(0x06, 0x08, KEY_0)
936 + MATRIX_KEY(0x06, 0x09, KEY_9)
937 + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
938 + MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
939 + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
940 +
941 + MATRIX_KEY(0x07, 0x01, KEY_Q)
942 + MATRIX_KEY(0x07, 0x02, KEY_E)
943 + MATRIX_KEY(0x07, 0x03, KEY_R)
944 + MATRIX_KEY(0x07, 0x04, KEY_W)
945 + MATRIX_KEY(0x07, 0x05, KEY_I)
946 + MATRIX_KEY(0x07, 0x06, KEY_U)
947 + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
948 + MATRIX_KEY(0x07, 0x08, KEY_P)
949 + MATRIX_KEY(0x07, 0x09, KEY_O)
950 + MATRIX_KEY(0x07, 0x0b, KEY_UP)
951 + MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
952 + >;
953 + };
954 +};
955 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h u-boot/arch/arm/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h
956 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/include/dt-bindings/reset/altr,rst-mgr.h u-boot/arch/arm/dts/include/dt-bindings/reset/altr,rst-mgr.h
957 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/Makefile u-boot/arch/arm/dts/Makefile
958 --- u-boot-2015.01-rc3/arch/arm/dts/Makefile 2014-12-08 22:35:08.000000000 +0100
959 +++ u-boot/arch/arm/dts/Makefile 2015-01-01 17:34:32.037506793 +0100
960 @@ -31,6 +31,7 @@
961 tegra30-tec-ng.dtb \
962 tegra114-dalmore.dtb \
963 tegra124-jetson-tk1.dtb \
964 + tegra124-nyan-big.dtb \
965 tegra124-venice2.dtb
966 dtb-$(CONFIG_ARCH_UNIPHIER) += \
967 uniphier-ph1-sld3-ref.dtb \
968 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5.dtsi u-boot/arch/arm/dts/socfpga_cyclone5.dtsi
969 --- u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5.dtsi 2014-12-08 22:35:08.000000000 +0100
970 +++ u-boot/arch/arm/dts/socfpga_cyclone5.dtsi 2015-01-01 17:34:32.041506727 +0100
971 @@ -1,18 +1,7 @@
972 /*
973 * Copyright (C) 2012 Altera Corporation <www.altera.com>
974 *
975 - * This program is free software; you can redistribute it and/or modify
976 - * it under the terms of the GNU General Public License as published by
977 - * the Free Software Foundation; either version 2 of the License, or
978 - * (at your option) any later version.
979 - *
980 - * This program is distributed in the hope that it will be useful,
981 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
982 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
983 - * GNU General Public License for more details.
984 - *
985 - * You should have received a copy of the GNU General Public License
986 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
987 + * SPDX-License-Identifier: GPL-2.0+
988 */
989
990 /dts-v1/;
991 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5_socrates.dts u-boot/arch/arm/dts/socfpga_cyclone5_socrates.dts
992 --- u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5_socrates.dts 2014-12-08 22:35:08.000000000 +0100
993 +++ u-boot/arch/arm/dts/socfpga_cyclone5_socrates.dts 2015-01-01 17:34:32.041506727 +0100
994 @@ -1,18 +1,7 @@
995 /*
996 * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
997 *
998 - * This program is free software; you can redistribute it and/or modify
999 - * it under the terms of the GNU General Public License as published by
1000 - * the Free Software Foundation; either version 2 of the License, or
1001 - * (at your option) any later version.
1002 - *
1003 - * This program is distributed in the hope that it will be useful,
1004 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1005 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1006 - * GNU General Public License for more details.
1007 - *
1008 - * You should have received a copy of the GNU General Public License
1009 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
1010 + * SPDX-License-Identifier: GPL-2.0+
1011 */
1012
1013 #include "socfpga_cyclone5.dtsi"
1014 @@ -25,6 +14,12 @@
1015 bootargs = "console=ttyS0,115200";
1016 };
1017
1018 + aliases {
1019 + spi0 = "/spi@ff705000"; /* QSPI */
1020 + spi1 = "/spi@fff00000";
1021 + spi2 = "/spi@fff01000";
1022 + };
1023 +
1024 memory {
1025 name = "memory";
1026 device_type = "memory";
1027 @@ -48,3 +43,23 @@
1028 &mmc {
1029 status = "okay";
1030 };
1031 +
1032 +&qspi {
1033 + status = "okay";
1034 +
1035 + flash0: n25q00@0 {
1036 + #address-cells = <1>;
1037 + #size-cells = <1>;
1038 + compatible = "n25q00";
1039 + reg = <0>; /* chip select */
1040 + spi-max-frequency = <50000000>;
1041 + m25p,fast-read;
1042 + page-size = <256>;
1043 + block-size = <16>; /* 2^16, 64KB */
1044 + read-delay = <4>; /* delay value in read data capture register */
1045 + tshsl-ns = <50>;
1046 + tsd2d-ns = <50>;
1047 + tchsh-ns = <4>;
1048 + tslch-ns = <4>;
1049 + };
1050 +};
1051 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/socfpga.dtsi u-boot/arch/arm/dts/socfpga.dtsi
1052 --- u-boot-2015.01-rc3/arch/arm/dts/socfpga.dtsi 2014-12-08 22:35:08.000000000 +0100
1053 +++ u-boot/arch/arm/dts/socfpga.dtsi 2015-01-01 17:34:32.041506727 +0100
1054 @@ -1,18 +1,7 @@
1055 /*
1056 * Copyright (C) 2012 Altera <www.altera.com>
1057 *
1058 - * This program is free software; you can redistribute it and/or modify
1059 - * it under the terms of the GNU General Public License as published by
1060 - * the Free Software Foundation; either version 2 of the License, or
1061 - * (at your option) any later version.
1062 - *
1063 - * This program is distributed in the hope that it will be useful,
1064 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1065 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1066 - * GNU General Public License for more details.
1067 - *
1068 - * You should have received a copy of the GNU General Public License
1069 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
1070 + * SPDX-License-Identifier: GPL-2.0+
1071 */
1072
1073 #include "skeleton.dtsi"
1074 @@ -639,6 +628,49 @@
1075 clock-names = "biu", "ciu";
1076 };
1077
1078 + qspi: spi@ff705000 {
1079 + compatible = "cadence,qspi";
1080 + #address-cells = <1>;
1081 + #size-cells = <0>;
1082 + reg = <0xff705000 0x1000>,
1083 + <0xffa00000 0x1000>;
1084 + interrupts = <0 151 4>;
1085 + clocks = <&qspi_clk>;
1086 + ext-decoder = <0>; /* external decoder */
1087 + num-chipselect = <4>;
1088 + fifo-depth = <128>;
1089 + bus-num = <2>;
1090 + status = "disabled";
1091 + };
1092 +
1093 + spi0: spi@fff00000 {
1094 + compatible = "snps,dw-spi-mmio";
1095 + #address-cells = <1>;
1096 + #size-cells = <0>;
1097 + reg = <0xfff00000 0x1000>;
1098 + interrupts = <0 154 4>;
1099 + num-chipselect = <4>;
1100 + bus-num = <0>;
1101 + tx-dma-channel = <&pdma 16>;
1102 + rx-dma-channel = <&pdma 17>;
1103 + clocks = <&per_base_clk>;
1104 + status = "disabled";
1105 + };
1106 +
1107 + spi1: spi@fff01000 {
1108 + compatible = "snps,dw-spi-mmio";
1109 + #address-cells = <1>;
1110 + #size-cells = <0>;
1111 + reg = <0xfff01000 0x1000>;
1112 + interrupts = <0 156 4>;
1113 + num-chipselect = <4>;
1114 + bus-num = <1>;
1115 + tx-dma-channel = <&pdma 20>;
1116 + rx-dma-channel = <&pdma 21>;
1117 + clocks = <&per_base_clk>;
1118 + status = "disabled";
1119 + };
1120 +
1121 /* Local timer */
1122 timer@fffec600 {
1123 compatible = "arm,cortex-a9-twd-timer";
1124 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra124.dtsi u-boot/arch/arm/dts/tegra124.dtsi
1125 --- u-boot-2015.01-rc3/arch/arm/dts/tegra124.dtsi 2014-12-08 22:35:08.000000000 +0100
1126 +++ u-boot/arch/arm/dts/tegra124.dtsi 2015-01-01 17:34:32.041506727 +0100
1127 @@ -1,5 +1,6 @@
1128 #include <dt-bindings/clock/tegra124-car.h>
1129 #include <dt-bindings/gpio/tegra-gpio.h>
1130 +#include <dt-bindings/pinctrl/pinctrl-tegra.h>
1131 #include <dt-bindings/interrupt-controller/arm-gic.h>
1132
1133 #include "skeleton.dtsi"
1134 @@ -192,6 +193,16 @@
1135 status = "disabled";
1136 };
1137
1138 + pwm: pwm@7000a000 {
1139 + compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
1140 + reg = <0x7000a000 0x100>;
1141 + #pwm-cells = <2>;
1142 + clocks = <&tegra_car TEGRA124_CLK_PWM>;
1143 + resets = <&tegra_car 17>;
1144 + reset-names = "pwm";
1145 + status = "disabled";
1146 + };
1147 +
1148 spi@7000d400 {
1149 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
1150 reg = <0x7000d400 0x200>;
1151 @@ -290,6 +301,109 @@
1152 status = "disabled";
1153 };
1154
1155 + ahub@70300000 {
1156 + compatible = "nvidia,tegra124-ahub";
1157 + reg = <0x70300000 0x200>,
1158 + <0x70300800 0x800>,
1159 + <0x70300200 0x600>;
1160 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1161 + clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
1162 + <&tegra_car TEGRA124_CLK_APBIF>;
1163 + clock-names = "d_audio", "apbif";
1164 + resets = <&tegra_car 106>, /* d_audio */
1165 + <&tegra_car 107>, /* apbif */
1166 + <&tegra_car 30>, /* i2s0 */
1167 + <&tegra_car 11>, /* i2s1 */
1168 + <&tegra_car 18>, /* i2s2 */
1169 + <&tegra_car 101>, /* i2s3 */
1170 + <&tegra_car 102>, /* i2s4 */
1171 + <&tegra_car 108>, /* dam0 */
1172 + <&tegra_car 109>, /* dam1 */
1173 + <&tegra_car 110>, /* dam2 */
1174 + <&tegra_car 10>, /* spdif */
1175 + <&tegra_car 153>, /* amx */
1176 + <&tegra_car 185>, /* amx1 */
1177 + <&tegra_car 154>, /* adx */
1178 + <&tegra_car 180>, /* adx1 */
1179 + <&tegra_car 186>, /* afc0 */
1180 + <&tegra_car 187>, /* afc1 */
1181 + <&tegra_car 188>, /* afc2 */
1182 + <&tegra_car 189>, /* afc3 */
1183 + <&tegra_car 190>, /* afc4 */
1184 + <&tegra_car 191>; /* afc5 */
1185 + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
1186 + "i2s3", "i2s4", "dam0", "dam1", "dam2",
1187 + "spdif", "amx", "amx1", "adx", "adx1",
1188 + "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
1189 + dmas = <&apbdma 1>, <&apbdma 1>,
1190 + <&apbdma 2>, <&apbdma 2>,
1191 + <&apbdma 3>, <&apbdma 3>,
1192 + <&apbdma 4>, <&apbdma 4>,
1193 + <&apbdma 6>, <&apbdma 6>,
1194 + <&apbdma 7>, <&apbdma 7>,
1195 + <&apbdma 12>, <&apbdma 12>,
1196 + <&apbdma 13>, <&apbdma 13>,
1197 + <&apbdma 14>, <&apbdma 14>,
1198 + <&apbdma 29>, <&apbdma 29>;
1199 + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
1200 + "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
1201 + "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
1202 + "rx9", "tx9";
1203 + ranges;
1204 + #address-cells = <1>;
1205 + #size-cells = <1>;
1206 +
1207 + tegra_i2s0: i2s@70301000 {
1208 + compatible = "nvidia,tegra124-i2s";
1209 + reg = <0x70301000 0x100>;
1210 + nvidia,ahub-cif-ids = <4 4>;
1211 + clocks = <&tegra_car TEGRA124_CLK_I2S0>;
1212 + resets = <&tegra_car 30>;
1213 + reset-names = "i2s";
1214 + status = "disabled";
1215 + };
1216 +
1217 + tegra_i2s1: i2s@70301100 {
1218 + compatible = "nvidia,tegra124-i2s";
1219 + reg = <0x70301100 0x100>;
1220 + nvidia,ahub-cif-ids = <5 5>;
1221 + clocks = <&tegra_car TEGRA124_CLK_I2S1>;
1222 + resets = <&tegra_car 11>;
1223 + reset-names = "i2s";
1224 + status = "disabled";
1225 + };
1226 +
1227 + tegra_i2s2: i2s@70301200 {
1228 + compatible = "nvidia,tegra124-i2s";
1229 + reg = <0x70301200 0x100>;
1230 + nvidia,ahub-cif-ids = <6 6>;
1231 + clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1232 + resets = <&tegra_car 18>;
1233 + reset-names = "i2s";
1234 + status = "disabled";
1235 + };
1236 +
1237 + tegra_i2s3: i2s@70301300 {
1238 + compatible = "nvidia,tegra124-i2s";
1239 + reg = <0x70301300 0x100>;
1240 + nvidia,ahub-cif-ids = <7 7>;
1241 + clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1242 + resets = <&tegra_car 101>;
1243 + reset-names = "i2s";
1244 + status = "disabled";
1245 + };
1246 +
1247 + tegra_i2s4: i2s@70301400 {
1248 + compatible = "nvidia,tegra124-i2s";
1249 + reg = <0x70301400 0x100>;
1250 + nvidia,ahub-cif-ids = <8 8>;
1251 + clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1252 + resets = <&tegra_car 102>;
1253 + reset-names = "i2s";
1254 + status = "disabled";
1255 + };
1256 + };
1257 +
1258 usb@7d000000 {
1259 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1260 reg = <0x7d000000 0x4000>;
1261 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra124-jetson-tk1.dts u-boot/arch/arm/dts/tegra124-jetson-tk1.dts
1262 --- u-boot-2015.01-rc3/arch/arm/dts/tegra124-jetson-tk1.dts 2014-12-08 22:35:08.000000000 +0100
1263 +++ u-boot/arch/arm/dts/tegra124-jetson-tk1.dts 2015-01-01 17:34:32.041506727 +0100
1264 @@ -16,7 +16,6 @@
1265 i2c2 = "/i2c@7000c400";
1266 i2c3 = "/i2c@7000c500";
1267 i2c4 = "/i2c@7000c700";
1268 - i2c5 = "/i2c@7000d100";
1269 sdhci0 = "/sdhci@700b0600";
1270 sdhci1 = "/sdhci@700b0400";
1271 spi0 = "/spi@7000d400";
1272 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra124-nyan-big.dts u-boot/arch/arm/dts/tegra124-nyan-big.dts
1273 --- u-boot-2015.01-rc3/arch/arm/dts/tegra124-nyan-big.dts 1970-01-01 01:00:00.000000000 +0100
1274 +++ u-boot/arch/arm/dts/tegra124-nyan-big.dts 2015-01-01 17:34:32.041506727 +0100
1275 @@ -0,0 +1,365 @@
1276 +/dts-v1/;
1277 +
1278 +#include <dt-bindings/input/input.h>
1279 +#include "tegra124.dtsi"
1280 +
1281 +/ {
1282 + model = "Acer Chromebook 13 CB5-311";
1283 + compatible = "google,nyan-big", "nvidia,tegra124";
1284 +
1285 + aliases {
1286 + console = &uarta;
1287 + i2c0 = "/i2c@7000d000";
1288 + i2c1 = "/i2c@7000c000";
1289 + i2c2 = "/i2c@7000c400";
1290 + i2c3 = "/i2c@7000c500";
1291 + i2c4 = "/i2c@7000c700";
1292 + i2c5 = "/i2c@7000d100";
1293 + rtc0 = "/i2c@0,7000d000/pmic@40";
1294 + rtc1 = "/rtc@0,7000e000";
1295 + sdhci0 = "/sdhci@700b0600";
1296 + sdhci1 = "/sdhci@700b0400";
1297 + spi0 = "/spi@7000d400";
1298 + spi1 = "/spi@7000da00";
1299 + usb0 = "/usb@7d000000";
1300 + usb1 = "/usb@7d008000";
1301 + };
1302 +
1303 + memory {
1304 + reg = <0x80000000 0x80000000>;
1305 + };
1306 +
1307 + serial@70006000 {
1308 + /* Debug connector on the bottom of the board near SD card. */
1309 + status = "okay";
1310 + };
1311 +
1312 + pwm@7000a000 {
1313 + status = "okay";
1314 + };
1315 +
1316 + i2c@7000c000 {
1317 + status = "okay";
1318 + clock-frequency = <100000>;
1319 +
1320 + acodec: audio-codec@10 {
1321 + compatible = "maxim,max98090";
1322 + reg = <0x10>;
1323 + interrupt-parent = <&gpio>;
1324 + interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
1325 + };
1326 +
1327 + temperature-sensor@4c {
1328 + compatible = "ti,tmp451";
1329 + reg = <0x4c>;
1330 + interrupt-parent = <&gpio>;
1331 + interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1332 +
1333 + #thermal-sensor-cells = <1>;
1334 + };
1335 + };
1336 +
1337 + i2c@7000c400 {
1338 + status = "okay";
1339 + clock-frequency = <100000>;
1340 + };
1341 +
1342 + i2c@7000c500 {
1343 + status = "okay";
1344 + clock-frequency = <400000>;
1345 +
1346 + tpm@20 {
1347 + compatible = "infineon,slb9645tt";
1348 + reg = <0x20>;
1349 + };
1350 + };
1351 +
1352 + hdmi_ddc: i2c@7000c700 {
1353 + status = "okay";
1354 + clock-frequency = <100000>;
1355 + };
1356 +
1357 + i2c@7000d000 {
1358 + status = "okay";
1359 + clock-frequency = <400000>;
1360 +
1361 + pmic: pmic@40 {
1362 + compatible = "ams,as3722";
1363 + reg = <0x40>;
1364 + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1365 +
1366 + ams,system-power-controller;
1367 +
1368 + #interrupt-cells = <2>;
1369 + interrupt-controller;
1370 +
1371 + gpio-controller;
1372 + #gpio-cells = <2>;
1373 +
1374 + pinctrl-names = "default";
1375 + pinctrl-0 = <&as3722_default>;
1376 +
1377 + as3722_default: pinmux {
1378 + gpio0 {
1379 + pins = "gpio0";
1380 + function = "gpio";
1381 + bias-pull-down;
1382 + };
1383 +
1384 + gpio1 {
1385 + pins = "gpio1";
1386 + function = "gpio";
1387 + bias-pull-up;
1388 + };
1389 +
1390 + gpio2_4_7 {
1391 + pins = "gpio2", "gpio4", "gpio7";
1392 + function = "gpio";
1393 + bias-pull-up;
1394 + };
1395 +
1396 + gpio3_6 {
1397 + pins = "gpio3", "gpio6";
1398 + bias-high-impedance;
1399 + };
1400 +
1401 + gpio5 {
1402 + pins = "gpio5";
1403 + function = "clk32k-out";
1404 + bias-pull-down;
1405 + };
1406 + };
1407 + };
1408 + };
1409 +
1410 + spi@7000d400 {
1411 + status = "okay";
1412 +
1413 + cros_ec: cros-ec@0 {
1414 + compatible = "google,cros-ec-spi";
1415 + spi-max-frequency = <3000000>;
1416 + interrupt-parent = <&gpio>;
1417 + interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
1418 + reg = <0>;
1419 +
1420 + google,cros-ec-spi-msg-delay = <2000>;
1421 +
1422 + i2c-tunnel {
1423 + compatible = "google,cros-ec-i2c-tunnel";
1424 + #address-cells = <1>;
1425 + #size-cells = <0>;
1426 +
1427 + google,remote-bus = <0>;
1428 +
1429 + charger: bq24735@9 {
1430 + compatible = "ti,bq24735";
1431 + reg = <0x9>;
1432 + interrupt-parent = <&gpio>;
1433 + interrupts = <TEGRA_GPIO(J, 0)
1434 + GPIO_ACTIVE_HIGH>;
1435 + ti,ac-detect-gpios = <&gpio
1436 + TEGRA_GPIO(J, 0)
1437 + GPIO_ACTIVE_HIGH>;
1438 + };
1439 +
1440 + battery: sbs-battery@b {
1441 + compatible = "sbs,sbs-battery";
1442 + reg = <0xb>;
1443 + sbs,i2c-retry-count = <2>;
1444 + sbs,poll-retry-count = <10>;
1445 + power-supplies = <&charger>;
1446 + };
1447 + };
1448 + };
1449 + };
1450 +
1451 + spi@7000da00 {
1452 + status = "okay";
1453 + spi-max-frequency = <25000000>;
1454 +
1455 + flash@0 {
1456 + compatible = "winbond,w25q32dw";
1457 + reg = <0>;
1458 + };
1459 + };
1460 +
1461 + pmc@7000e400 {
1462 + nvidia,invert-interrupt;
1463 + nvidia,suspend-mode = <0>;
1464 + nvidia,cpu-pwr-good-time = <500>;
1465 + nvidia,cpu-pwr-off-time = <300>;
1466 + nvidia,core-pwr-good-time = <641 3845>;
1467 + nvidia,core-pwr-off-time = <61036>;
1468 + nvidia,core-power-req-active-high;
1469 + nvidia,sys-clock-req-active-high;
1470 + };
1471 +
1472 + hda@70030000 {
1473 + status = "okay";
1474 + };
1475 +
1476 + sdhci@700b0000 { /* WiFi/BT on this bus */
1477 + status = "okay";
1478 + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
1479 + bus-width = <4>;
1480 + no-1-8-v;
1481 + non-removable;
1482 + };
1483 +
1484 + sdhci@700b0400 { /* SD Card on this bus */
1485 + status = "okay";
1486 + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
1487 + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
1488 + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
1489 + bus-width = <4>;
1490 + no-1-8-v;
1491 + };
1492 +
1493 + sdhci@700b0600 { /* eMMC on this bus */
1494 + status = "okay";
1495 + bus-width = <8>;
1496 + no-1-8-v;
1497 + non-removable;
1498 + };
1499 +
1500 + ahub@70300000 {
1501 + i2s@70301100 {
1502 + status = "okay";
1503 + };
1504 + };
1505 +
1506 + usb@7d000000 { /* Rear external USB port. */
1507 + status = "okay";
1508 + };
1509 +
1510 + usb-phy@7d000000 {
1511 + status = "okay";
1512 + };
1513 +
1514 + usb@7d004000 { /* Internal webcam. */
1515 + status = "okay";
1516 + };
1517 +
1518 + usb-phy@7d004000 {
1519 + status = "okay";
1520 + };
1521 +
1522 + usb@7d008000 { /* Left external USB port. */
1523 + status = "okay";
1524 + };
1525 +
1526 + usb-phy@7d008000 {
1527 + status = "okay";
1528 + };
1529 +
1530 + backlight: backlight {
1531 + compatible = "pwm-backlight";
1532 +
1533 + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1534 + pwms = <&pwm 1 1000000>;
1535 +
1536 + default-brightness-level = <224>;
1537 + brightness-levels =
1538 + < 0 1 2 3 4 5 6 7
1539 + 8 9 10 11 12 13 14 15
1540 + 16 17 18 19 20 21 22 23
1541 + 24 25 26 27 28 29 30 31
1542 + 32 33 34 35 36 37 38 39
1543 + 40 41 42 43 44 45 46 47
1544 + 48 49 50 51 52 53 54 55
1545 + 56 57 58 59 60 61 62 63
1546 + 64 65 66 67 68 69 70 71
1547 + 72 73 74 75 76 77 78 79
1548 + 80 81 82 83 84 85 86 87
1549 + 88 89 90 91 92 93 94 95
1550 + 96 97 98 99 100 101 102 103
1551 + 104 105 106 107 108 109 110 111
1552 + 112 113 114 115 116 117 118 119
1553 + 120 121 122 123 124 125 126 127
1554 + 128 129 130 131 132 133 134 135
1555 + 136 137 138 139 140 141 142 143
1556 + 144 145 146 147 148 149 150 151
1557 + 152 153 154 155 156 157 158 159
1558 + 160 161 162 163 164 165 166 167
1559 + 168 169 170 171 172 173 174 175
1560 + 176 177 178 179 180 181 182 183
1561 + 184 185 186 187 188 189 190 191
1562 + 192 193 194 195 196 197 198 199
1563 + 200 201 202 203 204 205 206 207
1564 + 208 209 210 211 212 213 214 215
1565 + 216 217 218 219 220 221 222 223
1566 + 224 225 226 227 228 229 230 231
1567 + 232 233 234 235 236 237 238 239
1568 + 240 241 242 243 244 245 246 247
1569 + 248 249 250 251 252 253 254 255
1570 + 256>;
1571 + };
1572 +
1573 + clocks {
1574 + compatible = "simple-bus";
1575 + #address-cells = <1>;
1576 + #size-cells = <0>;
1577 +
1578 + clk32k_in: clock@0 {
1579 + compatible = "fixed-clock";
1580 + reg = <0>;
1581 + #clock-cells = <0>;
1582 + clock-frequency = <32768>;
1583 + };
1584 + };
1585 +
1586 + gpio-keys {
1587 + compatible = "gpio-keys";
1588 +
1589 + lid {
1590 + label = "Lid";
1591 + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
1592 + linux,input-type = <5>;
1593 + linux,code = <KEY_RESERVED>;
1594 + debounce-interval = <1>;
1595 + gpio-key,wakeup;
1596 + };
1597 +
1598 + power {
1599 + label = "Power";
1600 + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1601 + linux,code = <KEY_POWER>;
1602 + debounce-interval = <30>;
1603 + gpio-key,wakeup;
1604 + };
1605 + };
1606 +
1607 + panel: panel {
1608 + compatible = "auo,b133xtn01";
1609 +
1610 + backlight = <&backlight>;
1611 + };
1612 +
1613 + sound {
1614 + compatible = "nvidia,tegra-audio-max98090-nyan-big",
1615 + "nvidia,tegra-audio-max98090";
1616 + nvidia,model = "Acer Chromebook 13";
1617 +
1618 + nvidia,audio-routing =
1619 + "Headphones", "HPR",
1620 + "Headphones", "HPL",
1621 + "Speakers", "SPKR",
1622 + "Speakers", "SPKL",
1623 + "Mic Jack", "MICBIAS",
1624 + "DMICL", "Int Mic",
1625 + "DMICR", "Int Mic",
1626 + "IN34", "Mic Jack";
1627 +
1628 + nvidia,i2s-controller = <&tegra_i2s1>;
1629 + nvidia,audio-codec = <&acodec>;
1630 +
1631 + clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1632 + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1633 + <&tegra_car TEGRA124_CLK_EXTERN1>;
1634 + clock-names = "pll_a", "pll_a_out0", "mclk";
1635 +
1636 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
1637 + };
1638 +};
1639 +
1640 +#include "cros-ec-keyboard.dtsi"
1641 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra30-tec-ng.dts u-boot/arch/arm/dts/tegra30-tec-ng.dts
1642 --- u-boot-2015.01-rc3/arch/arm/dts/tegra30-tec-ng.dts 2014-12-08 22:35:08.000000000 +0100
1643 +++ u-boot/arch/arm/dts/tegra30-tec-ng.dts 2015-01-01 17:34:32.045506662 +0100
1644 @@ -6,6 +6,10 @@
1645 model = "Avionic Design Tamonten™ NG Evaluation Carrier";
1646 compatible = "ad,tec-ng", "nvidia,tegra30";
1647
1648 + aliases {
1649 + i2c0 = "/i2c@7000c400";
1650 + };
1651 +
1652 /* GEN2 */
1653 i2c@7000c400 {
1654 status = "okay";
1655 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-ld4-ref.dts u-boot/arch/arm/dts/uniphier-ph1-ld4-ref.dts
1656 --- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-ld4-ref.dts 2014-12-08 22:35:08.000000000 +0100
1657 +++ u-boot/arch/arm/dts/uniphier-ph1-ld4-ref.dts 2015-01-01 17:34:32.045506662 +0100
1658 @@ -25,10 +25,10 @@
1659 };
1660
1661 aliases {
1662 - uart0 = &uart0;
1663 - uart1 = &uart1;
1664 - uart2 = &uart2;
1665 - uart3 = &uart3;
1666 + serial0 = &uart0;
1667 + serial1 = &uart1;
1668 + serial2 = &uart2;
1669 + serial3 = &uart3;
1670 i2c0 = &i2c0;
1671 i2c1 = &i2c1;
1672 i2c2 = &i2c2;
1673 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-pro4-ref.dts u-boot/arch/arm/dts/uniphier-ph1-pro4-ref.dts
1674 --- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-pro4-ref.dts 2014-12-08 22:35:08.000000000 +0100
1675 +++ u-boot/arch/arm/dts/uniphier-ph1-pro4-ref.dts 2015-01-01 17:34:32.045506662 +0100
1676 @@ -25,10 +25,10 @@
1677 };
1678
1679 aliases {
1680 - uart0 = &uart0;
1681 - uart1 = &uart1;
1682 - uart2 = &uart2;
1683 - uart3 = &uart3;
1684 + serial0 = &uart0;
1685 + serial1 = &uart1;
1686 + serial2 = &uart2;
1687 + serial3 = &uart3;
1688 i2c0 = &i2c0;
1689 i2c1 = &i2c1;
1690 i2c2 = &i2c2;
1691 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld3-ref.dts u-boot/arch/arm/dts/uniphier-ph1-sld3-ref.dts
1692 --- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld3-ref.dts 2014-12-08 22:35:08.000000000 +0100
1693 +++ u-boot/arch/arm/dts/uniphier-ph1-sld3-ref.dts 2015-01-01 17:34:32.045506662 +0100
1694 @@ -25,9 +25,9 @@
1695 };
1696
1697 aliases {
1698 - uart0 = &uart0;
1699 - uart1 = &uart1;
1700 - uart2 = &uart2;
1701 + serial0 = &uart0;
1702 + serial1 = &uart1;
1703 + serial2 = &uart2;
1704 i2c0 = &i2c0;
1705 i2c1 = &i2c1;
1706 i2c2 = &i2c2;
1707 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld8-ref.dts u-boot/arch/arm/dts/uniphier-ph1-sld8-ref.dts
1708 --- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld8-ref.dts 2014-12-08 22:35:08.000000000 +0100
1709 +++ u-boot/arch/arm/dts/uniphier-ph1-sld8-ref.dts 2015-01-01 17:34:32.045506662 +0100
1710 @@ -25,10 +25,10 @@
1711 };
1712
1713 aliases {
1714 - uart0 = &uart0;
1715 - uart1 = &uart1;
1716 - uart2 = &uart2;
1717 - uart3 = &uart3;
1718 + serial0 = &uart0;
1719 + serial1 = &uart1;
1720 + serial2 = &uart2;
1721 + serial3 = &uart3;
1722 i2c0 = &i2c0;
1723 i2c1 = &i2c1;
1724 i2c2 = &i2c2;
1725 diff -ruN u-boot-2015.01-rc3/arch/arm/imx-common/cpu.c u-boot/arch/arm/imx-common/cpu.c
1726 --- u-boot-2015.01-rc3/arch/arm/imx-common/cpu.c 2014-12-08 22:35:08.000000000 +0100
1727 +++ u-boot/arch/arm/imx-common/cpu.c 2015-01-01 17:34:32.045506662 +0100
1728 @@ -206,6 +206,9 @@
1729 {
1730 #if defined(CONFIG_CMD_SATA)
1731 sata_stop();
1732 +#if defined(CONFIG_MX6)
1733 + disable_sata_clock();
1734 +#endif
1735 #endif
1736 #if defined(CONFIG_VIDEO_IPUV3)
1737 /* disable video before launching O/S */
1738 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm281xx/sysmap.h u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h
1739 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm281xx/sysmap.h 2014-12-08 22:35:08.000000000 +0100
1740 +++ u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h 2015-01-01 17:34:32.053506531 +0100
1741 @@ -13,6 +13,8 @@
1742 #define ESUB_CLK_BASE_ADDR 0x38000000
1743 #define ESW_CONTRL_BASE_ADDR 0x38200000
1744 #define GPIO2_BASE_ADDR 0x35003000
1745 +#define HSOTG_BASE_ADDR 0x3f120000
1746 +#define HSOTG_CTRL_BASE_ADDR 0x3f130000
1747 #define KONA_MST_CLK_BASE_ADDR 0x3f001000
1748 #define KONA_SLV_CLK_BASE_ADDR 0x3e011000
1749 #define PMU_BSC_BASE_ADDR 0x3500d000
1750 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm2835/mbox.h u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h
1751 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm2835/mbox.h 2014-12-08 22:35:08.000000000 +0100
1752 +++ u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h 2015-01-01 17:34:32.053506531 +0100
1753 @@ -140,6 +140,7 @@
1754 #define BCM2835_BOARD_REV_B_REV2_f 0xf
1755 #define BCM2835_BOARD_REV_B_PLUS 0x10
1756 #define BCM2835_BOARD_REV_CM 0x11
1757 +#define BCM2835_BOARD_REV_A_PLUS 0x12
1758
1759 struct bcm2835_mbox_tag_get_board_rev {
1760 struct bcm2835_mbox_tag_hdr tag_hdr;
1761 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/config.h u-boot/arch/arm/include/asm/arch-ls102xa/config.h
1762 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/config.h 2014-12-08 22:35:08.000000000 +0100
1763 +++ u-boot/arch/arm/include/asm/arch-ls102xa/config.h 2015-01-01 17:34:32.065506333 +0100
1764 @@ -11,11 +11,17 @@
1765
1766 #define OCRAM_BASE_ADDR 0x10000000
1767 #define OCRAM_SIZE 0x00020000
1768 +#define OCRAM_BASE_S_ADDR 0x10010000
1769 +#define OCRAM_S_SIZE 0x00010000
1770
1771 #define CONFIG_SYS_IMMR 0x01000000
1772 +#define CONFIG_SYS_DCSRBAR 0x20000000
1773 +
1774 +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
1775
1776 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
1777 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
1778 +#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
1779 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
1780 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
1781 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
1782 @@ -52,6 +58,9 @@
1783
1784 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
1785
1786 +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
1787 +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
1788 +
1789 #ifdef CONFIG_DDR_SPD
1790 #define CONFIG_SYS_FSL_DDR_BE
1791 #define CONFIG_VERY_BIG_RAM
1792 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
1793 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 2014-12-08 22:35:08.000000000 +0100
1794 +++ u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 2015-01-01 17:34:32.065506333 +0100
1795 @@ -17,6 +17,9 @@
1796 #define SOC_VER_LS1021 0x11
1797 #define SOC_VER_LS1022 0x12
1798
1799 +#define CCSR_BRR_OFFSET 0xe4
1800 +#define CCSR_SCRATCHRW1_OFFSET 0x200
1801 +
1802 #define RCWSR0_SYS_PLL_RAT_SHIFT 25
1803 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f
1804 #define RCWSR0_MEM_PLL_RAT_SHIFT 16
1805 @@ -29,6 +32,11 @@
1806 #define ARCH_TIMER_CTRL_ENABLE (1 << 0)
1807 #define SYS_COUNTER_CTRL_ENABLE (1 << 24)
1808
1809 +#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000
1810 +#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000
1811 +
1812 +#define DCFG_DCSR_PORCR1 0
1813 +
1814 struct sys_info {
1815 unsigned long freq_processor[CONFIG_MAX_CPUS];
1816 unsigned long freq_systembus;
1817 @@ -98,6 +106,7 @@
1818 #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
1819 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
1820 #define SCFG_PIXCLKCR_PXCKEN 0x80000000
1821 +#define SCFG_QSPI_CLKSEL 0xc0100000
1822
1823 /* Supplemental Configuration Unit */
1824 struct ccsr_scfg {
1825 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
1826 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h 1970-01-01 01:00:00.000000000 +0100
1827 +++ u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h 2015-01-01 17:34:32.065506333 +0100
1828 @@ -0,0 +1,17 @@
1829 +/*
1830 + * Copyright 2014 Freescale Semiconductor, Inc.
1831 + *
1832 + * SPDX-License-Identifier: GPL-2.0+
1833 + */
1834 +
1835 +#ifndef __FSL_LS102XA_STREAM_ID_H_
1836 +#define __FSL_LS102XA_STREAM_ID_H_
1837 +
1838 +struct smmu_stream_id {
1839 + uint16_t offset;
1840 + uint16_t stream_id;
1841 + char dev_name[32];
1842 +};
1843 +
1844 +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
1845 +#endif
1846 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ns_access.h u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h
1847 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ns_access.h 1970-01-01 01:00:00.000000000 +0100
1848 +++ u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h 2015-01-01 17:34:32.065506333 +0100
1849 @@ -0,0 +1,118 @@
1850 +/*
1851 + * Copyright 2014 Freescale Semiconductor, Inc.
1852 + *
1853 + * SPDX-License-Identifier: GPL-2.0+
1854 + */
1855 +
1856 +#ifndef __FSL_NS_ACCESS_H_
1857 +#define __FSL_NS_ACCESS_H_
1858 +
1859 +enum csu_cslx_access {
1860 + CSU_NS_SUP_R = 0x08,
1861 + CSU_NS_SUP_W = 0x80,
1862 + CSU_NS_SUP_RW = 0x88,
1863 + CSU_NS_USER_R = 0x04,
1864 + CSU_NS_USER_W = 0x40,
1865 + CSU_NS_USER_RW = 0x44,
1866 + CSU_S_SUP_R = 0x02,
1867 + CSU_S_SUP_W = 0x20,
1868 + CSU_S_SUP_RW = 0x22,
1869 + CSU_S_USER_R = 0x01,
1870 + CSU_S_USER_W = 0x10,
1871 + CSU_S_USER_RW = 0x11,
1872 + CSU_ALL_RW = 0xff,
1873 +};
1874 +
1875 +enum csu_cslx_ind {
1876 + CSU_CSLX_PCIE2_IO = 0,
1877 + CSU_CSLX_PCIE1_IO,
1878 + CSU_CSLX_MG2TPR_IP,
1879 + CSU_CSLX_IFC_MEM,
1880 + CSU_CSLX_OCRAM,
1881 + CSU_CSLX_GIC,
1882 + CSU_CSLX_PCIE1,
1883 + CSU_CSLX_OCRAM2,
1884 + CSU_CSLX_QSPI_MEM,
1885 + CSU_CSLX_PCIE2,
1886 + CSU_CSLX_SATA,
1887 + CSU_CSLX_USB3,
1888 + CSU_CSLX_SERDES = 32,
1889 + CSU_CSLX_QDMA,
1890 + CSU_CSLX_LPUART2,
1891 + CSU_CSLX_LPUART1,
1892 + CSU_CSLX_LPUART4,
1893 + CSU_CSLX_LPUART3,
1894 + CSU_CSLX_LPUART6,
1895 + CSU_CSLX_LPUART5,
1896 + CSU_CSLX_DSPI2 = 40,
1897 + CSU_CSLX_DSPI1,
1898 + CSU_CSLX_QSPI,
1899 + CSU_CSLX_ESDHC,
1900 + CSU_CSLX_2D_ACE,
1901 + CSU_CSLX_IFC,
1902 + CSU_CSLX_I2C1,
1903 + CSU_CSLX_USB2,
1904 + CSU_CSLX_I2C3,
1905 + CSU_CSLX_I2C2,
1906 + CSU_CSLX_DUART2 = 50,
1907 + CSU_CSLX_DUART1,
1908 + CSU_CSLX_WDT2,
1909 + CSU_CSLX_WDT1,
1910 + CSU_CSLX_EDMA,
1911 + CSU_CSLX_SYS_CNT,
1912 + CSU_CSLX_DMA_MUX2,
1913 + CSU_CSLX_DMA_MUX1,
1914 + CSU_CSLX_DDR,
1915 + CSU_CSLX_QUICC,
1916 + CSU_CSLX_DCFG_CCU_RCPM = 60,
1917 + CSU_CSLX_SECURE_BOOTROM,
1918 + CSU_CSLX_SFP,
1919 + CSU_CSLX_TMU,
1920 + CSU_CSLX_SECURE_MONITOR,
1921 + CSU_CSLX_RESERVED0,
1922 + CSU_CSLX_ETSEC1,
1923 + CSU_CSLX_SEC5_5,
1924 + CSU_CSLX_ETSEC3,
1925 + CSU_CSLX_ETSEC2,
1926 + CSU_CSLX_GPIO2 = 70,
1927 + CSU_CSLX_GPIO1,
1928 + CSU_CSLX_GPIO4,
1929 + CSU_CSLX_GPIO3,
1930 + CSU_CSLX_PLATFORM_CONT,
1931 + CSU_CSLX_CSU,
1932 + CSU_CSLX_ASRC,
1933 + CSU_CSLX_SPDIF,
1934 + CSU_CSLX_FLEXCAN2,
1935 + CSU_CSLX_FLEXCAN1,
1936 + CSU_CSLX_FLEXCAN4 = 80,
1937 + CSU_CSLX_FLEXCAN3,
1938 + CSU_CSLX_SAI2,
1939 + CSU_CSLX_SAI1,
1940 + CSU_CSLX_SAI4,
1941 + CSU_CSLX_SAI3,
1942 + CSU_CSLX_FTM2,
1943 + CSU_CSLX_FTM1,
1944 + CSU_CSLX_FTM4,
1945 + CSU_CSLX_FTM3,
1946 + CSU_CSLX_FTM6 = 90,
1947 + CSU_CSLX_FTM5,
1948 + CSU_CSLX_FTM8,
1949 + CSU_CSLX_FTM7,
1950 + CSU_CSLX_COP_DCSR,
1951 + CSU_CSLX_EPU,
1952 + CSU_CSLX_GDI,
1953 + CSU_CSLX_DDI,
1954 + CSU_CSLX_RESERVED1,
1955 + CSU_CSLX_USB3_PHY = 117,
1956 + CSU_CSLX_RESERVED2,
1957 + CSU_CSLX_MAX,
1958 +};
1959 +
1960 +struct csu_ns_dev {
1961 + unsigned long ind;
1962 + uint32_t val;
1963 +};
1964 +
1965 +void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
1966 +
1967 +#endif
1968 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/spl.h u-boot/arch/arm/include/asm/arch-ls102xa/spl.h
1969 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/spl.h 1970-01-01 01:00:00.000000000 +0100
1970 +++ u-boot/arch/arm/include/asm/arch-ls102xa/spl.h 2015-01-01 17:34:32.065506333 +0100
1971 @@ -0,0 +1,20 @@
1972 +/*
1973 + * Copyright 2014 Freescale Semiconductor, Inc.
1974 + *
1975 + * SPDX-License-Identifier: GPL-2.0+
1976 + */
1977 +
1978 +#ifndef __ASM_ARCH_SPL_H__
1979 +#define __ASM_ARCH_SPL_H__
1980 +
1981 +#define BOOT_DEVICE_NONE 0
1982 +#define BOOT_DEVICE_XIP 1
1983 +#define BOOT_DEVICE_XIPWAIT 2
1984 +#define BOOT_DEVICE_NAND 3
1985 +#define BOOT_DEVICE_ONENAND 4
1986 +#define BOOT_DEVICE_MMC1 5
1987 +#define BOOT_DEVICE_MMC2 6
1988 +#define BOOT_DEVICE_MMC2_2 7
1989 +#define BOOT_DEVICE_SPI 10
1990 +
1991 +#endif /* __ASM_ARCH_SPL_H__ */
1992 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/clock.h u-boot/arch/arm/include/asm/arch-mx6/clock.h
1993 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/clock.h 2014-12-08 22:35:08.000000000 +0100
1994 +++ u-boot/arch/arm/include/asm/arch-mx6/clock.h 2015-01-01 17:34:32.073506203 +0100
1995 @@ -43,10 +43,10 @@
1996 };
1997
1998 enum enet_freq {
1999 - ENET_25MHz,
2000 - ENET_50MHz,
2001 - ENET_100MHz,
2002 - ENET_125MHz,
2003 + ENET_25MHZ,
2004 + ENET_50MHZ,
2005 + ENET_100MHZ,
2006 + ENET_125MHZ,
2007 };
2008
2009 u32 imx_get_uartclk(void);
2010 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/mx6sl_pins.h u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
2011 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/mx6sl_pins.h 2014-12-08 22:35:08.000000000 +0100
2012 +++ u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h 2015-01-01 17:34:32.073506203 +0100
2013 @@ -53,5 +53,10 @@
2014 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
2015 MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
2016 MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
2017 +
2018 + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
2019 +
2020 + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
2021 + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
2022 };
2023 #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
2024 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/mmc.h u-boot/arch/arm/include/asm/arch-rmobile/mmc.h
2025 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/mmc.h 1970-01-01 01:00:00.000000000 +0100
2026 +++ u-boot/arch/arm/include/asm/arch-rmobile/mmc.h 2015-01-01 17:34:32.085506005 +0100
2027 @@ -0,0 +1,14 @@
2028 +/*
2029 + * Renesas SuperH MMCIF driver.
2030 + *
2031 + * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2032 + * Copyright (C) 2014 Renesas Electronics Corporation
2033 + *
2034 + * SPDX-License-Identifier: GPL-2.0
2035 + */
2036 +#ifndef _RMOBILE_MMC_H_
2037 +#define _RMOBILE_MMC_H_
2038 +
2039 +int mmcif_mmc_init(void);
2040 +
2041 +#endif /* _RMOBILE_MMC_H_ */
2042 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7790.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h
2043 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7790.h 2014-12-08 22:35:08.000000000 +0100
2044 +++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h 2015-01-01 17:34:32.085506005 +0100
2045 @@ -15,6 +15,19 @@
2046 #define CONFIG_SYS_I2C_SH_BASE2 0xE6520000
2047 #define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000
2048
2049 +/* Module stop control/status register bits */
2050 +#define MSTP0_BITS 0x00640801
2051 +#define MSTP1_BITS 0xDB6E9BDF
2052 +#define MSTP2_BITS 0x300DA1FC
2053 +#define MSTP3_BITS 0xF08CF831
2054 +#define MSTP4_BITS 0x80000184
2055 +#define MSTP5_BITS 0x44C00046
2056 +#define MSTP7_BITS 0x07F30718
2057 +#define MSTP8_BITS 0x01F0FF84
2058 +#define MSTP9_BITS 0xF5979FCF
2059 +#define MSTP10_BITS 0xFFFEFFE0
2060 +#define MSTP11_BITS 0x00000000
2061 +
2062 #define R8A7790_CUT_ES2X 2
2063 #define IS_R8A7790_ES2() \
2064 (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
2065 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7791.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h
2066 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7791.h 2014-12-08 22:35:08.000000000 +0100
2067 +++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h 2015-01-01 17:34:32.089505941 +0100
2068 @@ -51,6 +51,19 @@
2069 #define DBSC3_1_QOS_W15_BASE 0xE67A2F00
2070 #define DBSC3_1_DBADJ2 0xE67A00C8
2071
2072 +/* Module stop control/status register bits */
2073 +#define MSTP0_BITS 0x00640801
2074 +#define MSTP1_BITS 0x9B6C9B5A
2075 +#define MSTP2_BITS 0x100D21FC
2076 +#define MSTP3_BITS 0xF08CD810
2077 +#define MSTP4_BITS 0x800001C4
2078 +#define MSTP5_BITS 0x44C00046
2079 +#define MSTP7_BITS 0x05BFE618
2080 +#define MSTP8_BITS 0x40C0FE85
2081 +#define MSTP9_BITS 0xFF979FFF
2082 +#define MSTP10_BITS 0xFFFEFFE0
2083 +#define MSTP11_BITS 0x000001C0
2084 +
2085 #define R8A7791_CUT_ES2X 2
2086 #define IS_R8A7791_ES2() \
2087 (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
2088 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7793.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7793.h
2089 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7793.h 2014-12-08 22:35:08.000000000 +0100
2090 +++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7793.h 2015-01-01 17:34:32.089505941 +0100
2091 @@ -56,6 +56,20 @@
2092 /*
2093 * R8A7793 I/O Product Information
2094 */
2095 +
2096 +/* Module stop control/status register bits */
2097 +#define MSTP0_BITS 0x00640801
2098 +#define MSTP1_BITS 0x9B6C9B5A
2099 +#define MSTP2_BITS 0x100D21FC
2100 +#define MSTP3_BITS 0xF08CD810
2101 +#define MSTP4_BITS 0x800001C4
2102 +#define MSTP5_BITS 0x44C00046
2103 +#define MSTP7_BITS 0x05BFE618
2104 +#define MSTP8_BITS 0x40C0FE85
2105 +#define MSTP9_BITS 0xFF979FFF
2106 +#define MSTP10_BITS 0xFFFEFFE0
2107 +#define MSTP11_BITS 0x000001C0
2108 +
2109 #define R8A7793_CUT_ES2X 2
2110 #define IS_R8A7793_ES2() \
2111 (rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
2112 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7794.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7794.h
2113 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7794.h 2014-12-08 22:35:08.000000000 +0100
2114 +++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7794.h 2015-01-01 17:34:32.089505941 +0100
2115 @@ -14,4 +14,17 @@
2116 /* SH-I2C */
2117 #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
2118
2119 +/* Module stop control/status register bits */
2120 +#define MSTP0_BITS 0x00440801
2121 +#define MSTP1_BITS 0x936899DA
2122 +#define MSTP2_BITS 0x100D21FC
2123 +#define MSTP3_BITS 0xE084D810
2124 +#define MSTP4_BITS 0x800001C4
2125 +#define MSTP5_BITS 0x40C00044
2126 +#define MSTP7_BITS 0x013FE618
2127 +#define MSTP8_BITS 0x40803C05
2128 +#define MSTP9_BITS 0xFB879FEE
2129 +#define MSTP10_BITS 0xFFFEFFE0
2130 +#define MSTP11_BITS 0x000001C0
2131 +
2132 #endif /* __ASM_ARCH_R8A7794_H */
2133 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-base.h u-boot/arch/arm/include/asm/arch-rmobile/rcar-base.h
2134 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-base.h 2014-12-08 22:35:08.000000000 +0100
2135 +++ u-boot/arch/arm/include/asm/arch-rmobile/rcar-base.h 2015-01-01 17:34:32.089505941 +0100
2136 @@ -29,6 +29,45 @@
2137 #define SCIF4_BASE 0xE6EE0000
2138 #define SCIF5_BASE 0xE6EE8000
2139
2140 +/* Module stop status register */
2141 +#define MSTPSR0 0xE6150030
2142 +#define MSTPSR1 0xE6150038
2143 +#define MSTPSR2 0xE6150040
2144 +#define MSTPSR3 0xE6150048
2145 +#define MSTPSR4 0xE615004C
2146 +#define MSTPSR5 0xE615003C
2147 +#define MSTPSR7 0xE61501C4
2148 +#define MSTPSR8 0xE61509A0
2149 +#define MSTPSR9 0xE61509A4
2150 +#define MSTPSR10 0xE61509A8
2151 +#define MSTPSR11 0xE61509AC
2152 +
2153 +/* Realtime module stop control register */
2154 +#define RMSTPCR0 0xE6150110
2155 +#define RMSTPCR1 0xE6150114
2156 +#define RMSTPCR2 0xE6150118
2157 +#define RMSTPCR3 0xE615011C
2158 +#define RMSTPCR4 0xE6150120
2159 +#define RMSTPCR5 0xE6150124
2160 +#define RMSTPCR7 0xE615012C
2161 +#define RMSTPCR8 0xE6150980
2162 +#define RMSTPCR9 0xE6150984
2163 +#define RMSTPCR10 0xE6150988
2164 +#define RMSTPCR11 0xE615098C
2165 +
2166 +/* System module stop control register */
2167 +#define SMSTPCR0 0xE6150130
2168 +#define SMSTPCR1 0xE6150134
2169 +#define SMSTPCR2 0xE6150138
2170 +#define SMSTPCR3 0xE615013C
2171 +#define SMSTPCR4 0xE6150140
2172 +#define SMSTPCR5 0xE6150144
2173 +#define SMSTPCR7 0xE615014C
2174 +#define SMSTPCR8 0xE6150990
2175 +#define SMSTPCR9 0xE6150994
2176 +#define SMSTPCR10 0xE6150998
2177 +#define SMSTPCR11 0xE615099C
2178 +
2179 /*
2180 * SH-I2C
2181 * Ch2 and ch3 are different address. These are defined
2182 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-mstp.h u-boot/arch/arm/include/asm/arch-rmobile/rcar-mstp.h
2183 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-mstp.h 1970-01-01 01:00:00.000000000 +0100
2184 +++ u-boot/arch/arm/include/asm/arch-rmobile/rcar-mstp.h 2015-01-01 17:34:32.089505941 +0100
2185 @@ -0,0 +1,109 @@
2186 +/*
2187 + * arch/arm/include/asm/arch-rmobile/rcar-mstp.h
2188 + *
2189 + * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2190 + * Copyright (C) 2013, 2014 Renesas Electronics Corporation
2191 + *
2192 + * SPDX-License-Identifier: GPL-2.0
2193 + */
2194 +
2195 +#ifndef __ASM_ARCH_RCAR_MSTP_H
2196 +#define __ASM_ARCH_RCAR_MSTP_H
2197 +
2198 +#define mstp_setbits(type, addr, saddr, set) \
2199 + out_##type((saddr), in_##type(addr) | (set))
2200 +#define mstp_clrbits(type, addr, saddr, clear) \
2201 + out_##type((saddr), in_##type(addr) & ~(clear))
2202 +#define mstp_setclrbits(type, addr, set, clear) \
2203 + out_##type((addr), (in_##type(addr) | (set)) & ~(clear))
2204 +#define mstp_setbits_le32(addr, saddr, set) \
2205 + mstp_setbits(le32, addr, saddr, set)
2206 +#define mstp_clrbits_le32(addr, saddr, clear) \
2207 + mstp_clrbits(le32, addr, saddr, clear)
2208 +#define mstp_setclrbits_le32(addr, set, clear) \
2209 + mstp_setclrbits(le32, addr, set, clear)
2210 +
2211 +#ifndef CONFIG_SMSTP0_ENA
2212 +#define CONFIG_SMSTP0_ENA 0x00
2213 +#endif
2214 +#ifndef CONFIG_SMSTP1_ENA
2215 +#define CONFIG_SMSTP1_ENA 0x00
2216 +#endif
2217 +#ifndef CONFIG_SMSTP2_ENA
2218 +#define CONFIG_SMSTP2_ENA 0x00
2219 +#endif
2220 +#ifndef CONFIG_SMSTP3_ENA
2221 +#define CONFIG_SMSTP3_ENA 0x00
2222 +#endif
2223 +#ifndef CONFIG_SMSTP4_ENA
2224 +#define CONFIG_SMSTP4_ENA 0x00
2225 +#endif
2226 +#ifndef CONFIG_SMSTP5_ENA
2227 +#define CONFIG_SMSTP5_ENA 0x00
2228 +#endif
2229 +#ifndef CONFIG_SMSTP6_ENA
2230 +#define CONFIG_SMSTP6_ENA 0x00
2231 +#endif
2232 +#ifndef CONFIG_SMSTP7_ENA
2233 +#define CONFIG_SMSTP7_ENA 0x00
2234 +#endif
2235 +#ifndef CONFIG_SMSTP8_ENA
2236 +#define CONFIG_SMSTP8_ENA 0x00
2237 +#endif
2238 +#ifndef CONFIG_SMSTP9_ENA
2239 +#define CONFIG_SMSTP9_ENA 0x00
2240 +#endif
2241 +#ifndef CONFIG_SMSTP10_ENA
2242 +#define CONFIG_SMSTP10_ENA 0x00
2243 +#endif
2244 +#ifndef CONFIG_SMSTP11_ENA
2245 +#define CONFIG_SMSTP11_ENA 0x00
2246 +#endif
2247 +
2248 +#ifndef CONFIG_RMSTP0_ENA
2249 +#define CONFIG_RMSTP0_ENA 0x00
2250 +#endif
2251 +#ifndef CONFIG_RMSTP1_ENA
2252 +#define CONFIG_RMSTP1_ENA 0x00
2253 +#endif
2254 +#ifndef CONFIG_RMSTP2_ENA
2255 +#define CONFIG_RMSTP2_ENA 0x00
2256 +#endif
2257 +#ifndef CONFIG_RMSTP3_ENA
2258 +#define CONFIG_RMSTP3_ENA 0x00
2259 +#endif
2260 +#ifndef CONFIG_RMSTP4_ENA
2261 +#define CONFIG_RMSTP4_ENA 0x00
2262 +#endif
2263 +#ifndef CONFIG_RMSTP5_ENA
2264 +#define CONFIG_RMSTP5_ENA 0x00
2265 +#endif
2266 +#ifndef CONFIG_RMSTP6_ENA
2267 +#define CONFIG_RMSTP6_ENA 0x00
2268 +#endif
2269 +#ifndef CONFIG_RMSTP7_ENA
2270 +#define CONFIG_RMSTP7_ENA 0x00
2271 +#endif
2272 +#ifndef CONFIG_RMSTP8_ENA
2273 +#define CONFIG_RMSTP8_ENA 0x00
2274 +#endif
2275 +#ifndef CONFIG_RMSTP9_ENA
2276 +#define CONFIG_RMSTP9_ENA 0x00
2277 +#endif
2278 +#ifndef CONFIG_RMSTP10_ENA
2279 +#define CONFIG_RMSTP10_ENA 0x00
2280 +#endif
2281 +#ifndef CONFIG_RMSTP11_ENA
2282 +#define CONFIG_RMSTP11_ENA 0x00
2283 +#endif
2284 +
2285 +struct mstp_ctl {
2286 + u32 s_addr;
2287 + u32 s_dis;
2288 + u32 s_ena;
2289 + u32 r_addr;
2290 + u32 r_dis;
2291 + u32 r_ena;
2292 +};
2293 +
2294 +#endif /* __ASM_ARCH_RCAR_MSTP_H */
2295 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/clock_manager.h u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h
2296 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/clock_manager.h 2014-12-08 22:35:08.000000000 +0100
2297 +++ u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h 2015-01-01 17:34:32.089505941 +0100
2298 @@ -14,6 +14,7 @@
2299 unsigned int cm_get_l4_sp_clk_hz(void);
2300 unsigned int cm_get_mmc_controller_clk_hz(void);
2301 unsigned int cm_get_qspi_controller_clk_hz(void);
2302 +unsigned int cm_get_spi_controller_clk_hz(void);
2303 #endif
2304
2305 typedef struct {
2306 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/freeze_controller.h u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h
2307 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/freeze_controller.h 2014-12-08 22:35:08.000000000 +0100
2308 +++ u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h 2015-01-01 17:34:32.089505941 +0100
2309 @@ -42,7 +42,6 @@
2310 #define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
2311 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
2312 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
2313 -#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
2314
2315 void sys_mgr_frzctrl_freeze_req(void);
2316 void sys_mgr_frzctrl_thaw_req(void);
2317 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/scan_manager.h u-boot/arch/arm/include/asm/arch-socfpga/scan_manager.h
2318 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/scan_manager.h 2014-12-08 22:35:08.000000000 +0100
2319 +++ u-boot/arch/arm/include/asm/arch-socfpga/scan_manager.h 2015-01-01 17:34:32.089505941 +0100
2320 @@ -13,6 +13,7 @@
2321 u32 padding[2];
2322 u32 fifo_single_byte;
2323 u32 fifo_double_byte;
2324 + u32 fifo_triple_byte;
2325 u32 fifo_quad_byte;
2326 };
2327
2328 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/gpio.h u-boot/arch/arm/include/asm/arch-stv0991/gpio.h
2329 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/gpio.h 1970-01-01 01:00:00.000000000 +0100
2330 +++ u-boot/arch/arm/include/asm/arch-stv0991/gpio.h 2015-01-01 17:34:32.093505875 +0100
2331 @@ -0,0 +1,22 @@
2332 +/*
2333 + * (C) Copyright 2014
2334 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
2335 + *
2336 + * SPDX-License-Identifier: GPL-2.0+
2337 + */
2338 +
2339 +#ifndef __ASM_ARCH_STV0991_GPIO_H
2340 +#define __ASM_ARCH_STV0991_GPIO_H
2341 +
2342 +enum gpio_direction {
2343 + GPIO_DIRECTION_IN,
2344 + GPIO_DIRECTION_OUT,
2345 +};
2346 +
2347 +struct gpio_regs {
2348 + u32 data; /* offset 0x0 */
2349 + u32 reserved[0xff]; /* 0x4--0x3fc */
2350 + u32 dir; /* offset 0x400 */
2351 +};
2352 +
2353 +#endif /* __ASM_ARCH_STV0991_GPIO_H */
2354 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/hardware.h u-boot/arch/arm/include/asm/arch-stv0991/hardware.h
2355 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/hardware.h 1970-01-01 01:00:00.000000000 +0100
2356 +++ u-boot/arch/arm/include/asm/arch-stv0991/hardware.h 2015-01-01 17:34:32.093505875 +0100
2357 @@ -0,0 +1,73 @@
2358 +/*
2359 + * (C) Copyright 2014
2360 + * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
2361 + *
2362 + * SPDX-License-Identifier: GPL-2.0+
2363 + */
2364 +
2365 +#ifndef _ASM_ARCH_HARDWARE_H
2366 +#define _ASM_ARCH_HARDWARE_H
2367 +
2368 +/* STV0991 */
2369 +#define SRAM0_BASE_ADDR 0x00000000UL
2370 +#define SRAM1_BASE_ADDR 0x00068000UL
2371 +#define SRAM2_BASE_ADDR 0x000D0000UL
2372 +#define SRAM3_BASE_ADDR 0x00138000UL
2373 +#define CFS_SRAM0_BASE_ADDR 0x00198000UL
2374 +#define CFS_SRAM1_BASE_ADDR 0x001B8000UL
2375 +#define FAST_SRAM_BASE_ADDR 0x001D8000UL
2376 +#define FLASH_BASE_ADDR 0x40000000UL
2377 +#define PL310_BASE_ADDR 0x70000000UL
2378 +#define HSAXIM_BASE_ADDR 0x70100000UL
2379 +#define IMGSS_BASE_ADDR 0x70200000UL
2380 +#define ADC_BASE_ADDR 0x80000000UL
2381 +#define GPIOA_BASE_ADDR 0x80001000UL
2382 +#define GPIOB_BASE_ADDR 0x80002000UL
2383 +#define GPIOC_BASE_ADDR 0x80003000UL
2384 +#define HDM_BASE_ADDR 0x80004000UL
2385 +#define THSENS_BASE_ADDR 0x80200000UL
2386 +#define GPTIMER2_BASE_ADDR 0x80201000UL
2387 +#define GPTIMER1_BASE_ADDR 0x80202000UL
2388 +#define QSPI_BASE_ADDR 0x80203000UL
2389 +#define CGU_BASE_ADDR 0x80204000UL
2390 +#define CREG_BASE_ADDR 0x80205000UL
2391 +#define PEC_BASE_ADDR 0x80206000UL
2392 +#define WDRU_BASE_ADDR 0x80207000UL
2393 +#define BSEC_BASE_ADDR 0x80208000UL
2394 +#define DAP_ROM_BASE_ADDR 0x80210000UL
2395 +#define SOC_CTI_BASE_ADDR 0x80211000UL
2396 +#define TPIU_BASE_ADDR 0x80212000UL
2397 +#define TMC_ETF_BASE_ADDR 0x80213000UL
2398 +#define R4_ETM_BASE_ADDR 0x80214000UL
2399 +#define R4_CTI_BASE_ADDR 0x80215000UL
2400 +#define R4_DBG_BASE_ADDR 0x80216000UL
2401 +#define GMAC_BASE_ADDR 0x80300000UL
2402 +#define RNSS_BASE_ADDR 0x80302000UL
2403 +#define CRYP_BASE_ADDR 0x80303000UL
2404 +#define HASH_BASE_ADDR 0x80304000UL
2405 +#define GPDMA_BASE_ADDR 0x80305000UL
2406 +#define ISA_BASE_ADDR 0x8032A000UL
2407 +#define HCI_BASE_ADDR 0x80400000UL
2408 +#define I2C1_BASE_ADDR 0x80401000UL
2409 +#define I2C2_BASE_ADDR 0x80402000UL
2410 +#define SAI_BASE_ADDR 0x80403000UL
2411 +#define USI_BASE_ADDR 0x80404000UL
2412 +#define SPI1_BASE_ADDR 0x80405000UL
2413 +#define UART_BASE_ADDR 0x80406000UL
2414 +#define SPI2_BASE_ADDR 0x80500000UL
2415 +#define CAN_BASE_ADDR 0x80501000UL
2416 +#define USART1_BASE_ADDR 0x80502000UL
2417 +#define USART2_BASE_ADDR 0x80503000UL
2418 +#define USART3_BASE_ADDR 0x80504000UL
2419 +#define USART4_BASE_ADDR 0x80505000UL
2420 +#define USART5_BASE_ADDR 0x80506000UL
2421 +#define USART6_BASE_ADDR 0x80507000UL
2422 +#define SDI2_BASE_ADDR 0x80600000UL
2423 +#define SDI1_BASE_ADDR 0x80601000UL
2424 +#define VICA_BASE_ADDR 0x81000000UL
2425 +#define VICB_BASE_ADDR 0x81001000UL
2426 +#define STM_CHANNELS_BASE_ADDR 0x81100000UL
2427 +#define STM_BASE_ADDR 0x81110000UL
2428 +#define SROM_BASE_ADDR 0xFFFF0000UL
2429 +
2430 +#endif /* _ASM_ARCH_HARDWARE_H */
2431 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
2432 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h 1970-01-01 01:00:00.000000000 +0100
2433 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h 2015-01-01 17:34:32.093505875 +0100
2434 @@ -0,0 +1,116 @@
2435 +/*
2436 + * (C) Copyright 2014
2437 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
2438 + *
2439 + * SPDX-License-Identifier: GPL-2.0+
2440 + */
2441 +
2442 +#ifndef _STV0991_CGU_H
2443 +#define _STV0991_CGU_H
2444 +
2445 +struct stv0991_cgu_regs {
2446 + u32 cpu_freq; /* offset 0x0 */
2447 + u32 icn2_freq; /* offset 0x4 */
2448 + u32 dma_freq; /* offset 0x8 */
2449 + u32 isp_freq; /* offset 0xc */
2450 + u32 h264_freq; /* offset 0x10 */
2451 + u32 osif_freq; /* offset 0x14 */
2452 + u32 ren_freq; /* offset 0x18 */
2453 + u32 tim_freq; /* offset 0x1c */
2454 + u32 sai_freq; /* offset 0x20 */
2455 + u32 eth_freq; /* offset 0x24 */
2456 + u32 i2c_freq; /* offset 0x28 */
2457 + u32 spi_freq; /* offset 0x2c */
2458 + u32 uart_freq; /* offset 0x30 */
2459 + u32 qspi_freq; /* offset 0x34 */
2460 + u32 sdio_freq; /* offset 0x38 */
2461 + u32 usi_freq; /* offset 0x3c */
2462 + u32 can_line_freq; /* offset 0x40 */
2463 + u32 debug_freq; /* offset 0x44 */
2464 + u32 trace_freq; /* offset 0x48 */
2465 + u32 stm_freq; /* offset 0x4c */
2466 + u32 eth_ctrl; /* offset 0x50 */
2467 + u32 reserved[3]; /* offset 0x54 */
2468 + u32 osc_ctrl; /* offset 0x60 */
2469 + u32 pll1_ctrl; /* offset 0x64 */
2470 + u32 pll1_freq; /* offset 0x68 */
2471 + u32 pll1_fract; /* offset 0x6c */
2472 + u32 pll1_spread; /* offset 0x70 */
2473 + u32 pll1_status; /* offset 0x74 */
2474 + u32 pll2_ctrl; /* offset 0x78 */
2475 + u32 pll2_freq; /* offset 0x7c */
2476 + u32 pll2_fract; /* offset 0x80 */
2477 + u32 pll2_spread; /* offset 0x84 */
2478 + u32 pll2_status; /* offset 0x88 */
2479 + u32 cgu_enable_1; /* offset 0x8c */
2480 + u32 cgu_enable_2; /* offset 0x90 */
2481 + u32 cgu_isp_pulse; /* offset 0x94 */
2482 + u32 cgu_h264_pulse; /* offset 0x98 */
2483 + u32 cgu_osif_pulse; /* offset 0x9c */
2484 + u32 cgu_ren_pulse; /* offset 0xa0 */
2485 +
2486 +};
2487 +
2488 +/* CGU Timer */
2489 +#define CLK_TMR_OSC 0
2490 +#define CLK_TMR_MCLK 1
2491 +#define CLK_TMR_PLL1 2
2492 +#define CLK_TMR_PLL2 3
2493 +#define MDIV_SHIFT_TMR 3
2494 +#define DIV_SHIFT_TMR 6
2495 +
2496 +#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \
2497 + | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
2498 +
2499 +/* Clock Enable/Disable */
2500 +
2501 +#define TIMER1_CLK_EN (1 << 15)
2502 +
2503 +/* CGU Uart config */
2504 +#define CLK_UART_MCLK 0
2505 +#define CLK_UART_PLL1 1
2506 +#define CLK_UART_PLL2 2
2507 +
2508 +#define MDIV_SHIFT_UART 3
2509 +#define DIV_SHIFT_UART 6
2510 +
2511 +#define UART_CLK_CFG (4 << DIV_SHIFT_UART \
2512 + | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
2513 +
2514 +/* CGU Ethernet clock config */
2515 +#define CLK_ETH_MCLK 0
2516 +#define CLK_ETH_PLL1 1
2517 +#define CLK_ETH_PLL2 2
2518 +
2519 +#define MDIV_SHIFT_ETH 3
2520 +#define DIV_SHIFT_ETH 6
2521 +#define DIV_ETH_125 9
2522 +#define DIV_ETH_50 12
2523 +#define DIV_ETH_P2P 15
2524 +
2525 +#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
2526 + | 1 << DIV_ETH_125 \
2527 + | 0 << DIV_SHIFT_ETH \
2528 + | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
2529 + /* CGU Ethernet control */
2530 +
2531 +#define ETH_CLK_TX_EXT_PHY 0
2532 +#define ETH_CLK_TX_125M 1
2533 +#define ETH_CLK_TX_25M 2
2534 +#define ETH_CLK_TX_2M5 3
2535 +#define ETH_CLK_TX_DIS 7
2536 +
2537 +#define ETH_CLK_RX_EXT_PHY 0
2538 +#define ETH_CLK_RX_25M 1
2539 +#define ETH_CLK_RX_2M5 2
2540 +#define ETH_CLK_RX_DIS 3
2541 +#define RX_CLK_SHIFT 3
2542 +#define ETH_CLK_MASK ~(0x1F)
2543 +
2544 +#define ETH_PHY_MODE_GMII 0
2545 +#define ETH_PHY_MODE_RMII 1
2546 +#define ETH_PHY_CLK_DIS 1
2547 +
2548 +#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
2549 + | ETH_CLK_TX_EXT_PHY)
2550 +#endif
2551 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_creg.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
2552 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_creg.h 1970-01-01 01:00:00.000000000 +0100
2553 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_creg.h 2015-01-01 17:34:32.093505875 +0100
2554 @@ -0,0 +1,95 @@
2555 +/*
2556 + * (C) Copyright 2014
2557 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
2558 + *
2559 + * SPDX-License-Identifier: GPL-2.0+
2560 + */
2561 +
2562 +#ifndef _STV0991_CREG_H
2563 +#define _STV0991_CREG_H
2564 +
2565 +struct stv0991_creg {
2566 + u32 version; /* offset 0x0 */
2567 + u32 hdpctl; /* offset 0x4 */
2568 + u32 hdpval; /* offset 0x8 */
2569 + u32 hdpgposet; /* offset 0xc */
2570 + u32 hdpgpoclr; /* offset 0x10 */
2571 + u32 hdpgpoval; /* offset 0x14 */
2572 + u32 stm_mux; /* offset 0x18 */
2573 + u32 sysctrl_1; /* offset 0x1c */
2574 + u32 sysctrl_2; /* offset 0x20 */
2575 + u32 sysctrl_3; /* offset 0x24 */
2576 + u32 sysctrl_4; /* offset 0x28 */
2577 + u32 reserved_1[0x35]; /* offset 0x2C-0xFC */
2578 + u32 mux1; /* offset 0x100 */
2579 + u32 mux2; /* offset 0x104 */
2580 + u32 mux3; /* offset 0x108 */
2581 + u32 mux4; /* offset 0x10c */
2582 + u32 mux5; /* offset 0x110 */
2583 + u32 mux6; /* offset 0x114 */
2584 + u32 mux7; /* offset 0x118 */
2585 + u32 mux8; /* offset 0x11c */
2586 + u32 mux9; /* offset 0x120 */
2587 + u32 mux10; /* offset 0x124 */
2588 + u32 mux11; /* offset 0x128 */
2589 + u32 mux12; /* offset 0x12c */
2590 + u32 mux13; /* offset 0x130 */
2591 + u32 reserved_2[0x33]; /* offset 0x134-0x1FC */
2592 + u32 cfg_pad1; /* offset 0x200 */
2593 + u32 cfg_pad2; /* offset 0x204 */
2594 + u32 cfg_pad3; /* offset 0x208 */
2595 + u32 cfg_pad4; /* offset 0x20c */
2596 + u32 cfg_pad5; /* offset 0x210 */
2597 + u32 cfg_pad6; /* offset 0x214 */
2598 + u32 cfg_pad7; /* offset 0x218 */
2599 + u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */
2600 + u32 vdd_pad1; /* offset 0x300 */
2601 + u32 vdd_pad2; /* offset 0x304 */
2602 + u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */
2603 + u32 vdd_comp1; /* offset 0x400 */
2604 +};
2605 +
2606 +/* CREG MUX 12 register */
2607 +#define GPIOC_30_MUX_SHIFT 24
2608 +#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT)
2609 +#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT)
2610 +
2611 +#define GPIOC_31_MUX_SHIFT 28
2612 +#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT)
2613 +#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT)
2614 +
2615 +/* CREG MUX 7 register */
2616 +#define GPIOB_16_MUX_SHIFT 0
2617 +#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT)
2618 +#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT)
2619 +
2620 +#define GPIOB_17_MUX_SHIFT 4
2621 +#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT)
2622 +#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT)
2623 +
2624 +/* CREG CFG_PAD6 register */
2625 +
2626 +#define GPIOC_31_MODE_SHIFT 30
2627 +#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT)
2628 +#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT)
2629 +#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT)
2630 +
2631 +#define GPIOC_30_MODE_SHIFT 28
2632 +#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT)
2633 +#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT)
2634 +#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT)
2635 +
2636 +/* CREG Ethernet pad config */
2637 +
2638 +#define VDD_ETH_PS_1V8 0
2639 +#define VDD_ETH_PS_2V5 2
2640 +#define VDD_ETH_PS_3V3 3
2641 +#define VDD_ETH_PS_MASK 0x3
2642 +
2643 +#define VDD_ETH_PS_SHIFT 12
2644 +#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT)
2645 +
2646 +#define VDD_ETH_M_PS_SHIFT 28
2647 +#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT)
2648 +
2649 +#endif
2650 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_defs.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_defs.h
2651 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_defs.h 1970-01-01 01:00:00.000000000 +0100
2652 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_defs.h 2015-01-01 17:34:32.093505875 +0100
2653 @@ -0,0 +1,16 @@
2654 +/*
2655 + * (C) Copyright 2014
2656 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
2657 + *
2658 + * SPDX-License-Identifier: GPL-2.0+
2659 + */
2660 +
2661 +#ifndef __STV0991_DEFS_H__
2662 +#define __STV0991_DEFS_H__
2663 +#include <asm/arch/stv0991_periph.h>
2664 +
2665 +extern int stv0991_pinmux_config(enum periph_id);
2666 +extern int clock_setup(enum periph_clock);
2667 +
2668 +#endif
2669 +
2670 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
2671 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h 1970-01-01 01:00:00.000000000 +0100
2672 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h 2015-01-01 17:34:32.093505875 +0100
2673 @@ -0,0 +1,43 @@
2674 +/*
2675 + * (C) Copyright 2014
2676 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
2677 + *
2678 + * SPDX-License-Identifier: GPL-2.0+
2679 + */
2680 +
2681 +#ifndef _STV0991_GPT_H
2682 +#define _STV0991_GPT_H
2683 +
2684 +#include <asm/arch-stv0991/hardware.h>
2685 +
2686 +struct gpt_regs {
2687 + u32 cr1;
2688 + u32 cr2;
2689 + u32 reserved_1;
2690 + u32 dier; /* dma_int_en */
2691 + u32 sr; /* status reg */
2692 + u32 egr; /* event gen */
2693 + u32 reserved_2[3]; /* offset 0x18--0x20*/
2694 + u32 cnt;
2695 + u32 psc;
2696 + u32 arr;
2697 +};
2698 +
2699 +struct gpt_regs *const gpt1_regs_ptr =
2700 + (struct gpt_regs *) GPTIMER1_BASE_ADDR;
2701 +
2702 +/* Timer control1 register */
2703 +#define GPT_CR1_CEN 0x0001
2704 +#define GPT_MODE_AUTO_RELOAD (1 << 7)
2705 +
2706 +/* Timer prescalar reg */
2707 +#define GPT_PRESCALER_128 0x128
2708 +
2709 +/* Auto reload register for free running config */
2710 +#define GPT_FREE_RUNNING 0xFFFF
2711 +
2712 +/* Timer, HZ specific defines */
2713 +#define CONFIG_STV0991_HZ 1000
2714 +#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128
2715 +
2716 +#endif
2717 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_periph.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
2718 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_periph.h 1970-01-01 01:00:00.000000000 +0100
2719 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_periph.h 2015-01-01 17:34:32.093505875 +0100
2720 @@ -0,0 +1,44 @@
2721 +/*
2722 + * (C) Copyright 2014
2723 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
2724 + *
2725 + * SPDX-License-Identifier: GPL-2.0+
2726 + */
2727 +
2728 +#ifndef __ASM_ARM_ARCH_PERIPH_H
2729 +#define __ASM_ARM_ARCH_PERIPH_H
2730 +
2731 +/*
2732 + * Peripherals required for pinmux configuration. List will
2733 + * grow with support for more devices getting added.
2734 + * Numbering based on interrupt table.
2735 + *
2736 + */
2737 +enum periph_id {
2738 + UART_GPIOC_30_31 = 0,
2739 + UART_GPIOB_16_17,
2740 + ETH_GPIOB_10_31_C_0_4,
2741 + PERIPH_ID_I2C0,
2742 + PERIPH_ID_I2C1,
2743 + PERIPH_ID_I2C2,
2744 + PERIPH_ID_I2C3,
2745 + PERIPH_ID_I2C4,
2746 + PERIPH_ID_I2C5,
2747 + PERIPH_ID_I2C6,
2748 + PERIPH_ID_I2C7,
2749 + PERIPH_ID_SPI0,
2750 + PERIPH_ID_SPI1,
2751 + PERIPH_ID_SPI2,
2752 + PERIPH_ID_SDMMC0,
2753 + PERIPH_ID_SDMMC1,
2754 + PERIPH_ID_SDMMC2,
2755 + PERIPH_ID_SDMMC3,
2756 + PERIPH_ID_I2S1,
2757 +};
2758 +
2759 +enum periph_clock {
2760 + UART_CLOCK_CFG = 0,
2761 + ETH_CLOCK_CFG,
2762 +};
2763 +
2764 +#endif /* __ASM_ARM_ARCH_PERIPH_H */
2765 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
2766 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h 1970-01-01 01:00:00.000000000 +0100
2767 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h 2015-01-01 17:34:32.093505875 +0100
2768 @@ -0,0 +1,28 @@
2769 +/*
2770 + * (C) Copyright 2014
2771 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
2772 + *
2773 + * SPDX-License-Identifier: GPL-2.0+
2774 + */
2775 +
2776 +#ifndef _STV0991_WD_RST_H
2777 +#define _STV0991_WD_RST_H
2778 +#include <asm/arch-stv0991/hardware.h>
2779 +
2780 +struct stv0991_wd_ru {
2781 + u32 wdru_config;
2782 + u32 wdru_ctrl1;
2783 + u32 wdru_ctrl2;
2784 + u32 wdru_tim;
2785 + u32 wdru_count;
2786 + u32 wdru_stat;
2787 + u32 wdru_wrlock;
2788 +};
2789 +
2790 +struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \
2791 + (struct stv0991_wd_ru *)WDRU_BASE_ADDR;
2792 +
2793 +/* Watchdog control register */
2794 +#define WDRU_RST_SYS 0x1
2795 +
2796 +#endif
2797 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-tegra/tegra_i2c.h u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h
2798 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-tegra/tegra_i2c.h 2014-12-08 22:35:08.000000000 +0100
2799 +++ u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h 2015-01-01 17:34:32.097505809 +0100
2800 @@ -167,6 +167,6 @@
2801 *
2802 * @return number of bus, or -1 if there is no DVC active
2803 */
2804 -int tegra_i2c_get_dvc_bus_num(void);
2805 +int tegra_i2c_get_dvc_bus(struct udevice **busp);
2806
2807 #endif /* _TEGRA_I2C_H_ */
2808 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-vf610/imx-regs.h u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h
2809 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-vf610/imx-regs.h 2014-12-08 22:35:08.000000000 +0100
2810 +++ u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h 2015-01-01 17:34:32.109505612 +0100
2811 @@ -256,6 +256,14 @@
2812 #define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8)
2813 #define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf)
2814
2815 +/* System Reset Controller (SRC) */
2816 +#define SRC_SRSR_SW_RST (0x1 << 18)
2817 +#define SRC_SRSR_RESETB (0x1 << 7)
2818 +#define SRC_SRSR_JTAG_RST (0x1 << 5)
2819 +#define SRC_SRSR_WDOG_M4 (0x1 << 4)
2820 +#define SRC_SRSR_WDOG_A5 (0x1 << 3)
2821 +#define SRC_SRSR_POR_RST (0x1 << 0)
2822 +
2823 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
2824 #include <asm/types.h>
2825
2826 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/kona-common/clk.h u-boot/arch/arm/include/asm/kona-common/clk.h
2827 --- u-boot-2015.01-rc3/arch/arm/include/asm/kona-common/clk.h 2014-12-08 22:35:08.000000000 +0100
2828 +++ u-boot/arch/arm/include/asm/kona-common/clk.h 2015-01-01 17:34:32.113505547 +0100
2829 @@ -25,5 +25,6 @@
2830 struct clk *clk_get_parent(struct clk *clk);
2831 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
2832 int clk_bsc_enable(void *base);
2833 +int clk_usb_otg_enable(void *base);
2834
2835 #endif
2836 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/pcie_layerscape.h u-boot/arch/arm/include/asm/pcie_layerscape.h
2837 --- u-boot-2015.01-rc3/arch/arm/include/asm/pcie_layerscape.h 1970-01-01 01:00:00.000000000 +0100
2838 +++ u-boot/arch/arm/include/asm/pcie_layerscape.h 2015-01-01 17:34:32.125505350 +0100
2839 @@ -0,0 +1,13 @@
2840 +/*
2841 + * Copyright 2014 Freescale Semiconductor, Inc.
2842 + *
2843 + * SPDX-License-Identifier: GPL-2.0+
2844 + */
2845 +
2846 +#ifndef __PCIE_LAYERSCAPE_H_
2847 +#define __PCIE_LAYERSCAPE_H_
2848 +
2849 +void pci_init_board(void);
2850 +void ft_pcie_setup(void *blob, bd_t *bd);
2851 +
2852 +#endif
2853 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/semihosting.h u-boot/arch/arm/include/asm/semihosting.h
2854 --- u-boot-2015.01-rc3/arch/arm/include/asm/semihosting.h 2014-12-08 22:35:08.000000000 +0100
2855 +++ u-boot/arch/arm/include/asm/semihosting.h 2015-01-01 17:34:32.125505350 +0100
2856 @@ -12,10 +12,6 @@
2857 * code for more information.
2858 */
2859 int smh_load(const char *fname, void *memp, int avail, int verbose);
2860 -int smh_read(int fd, void *memp, int len);
2861 -int smh_open(const char *fname, char *modestr);
2862 -int smh_close(int fd);
2863 -int smh_len_fd(int fd);
2864 -int smh_len(const char *fname);
2865 +long smh_len(const char *fname);
2866
2867 #endif /* __SEMIHOSTING_H__ */
2868 diff -ruN u-boot-2015.01-rc3/arch/arm/Kconfig u-boot/arch/arm/Kconfig
2869 --- u-boot-2015.01-rc3/arch/arm/Kconfig 2014-12-08 22:35:08.000000000 +0100
2870 +++ u-boot/arch/arm/Kconfig 2015-01-01 17:34:31.989507580 +0100
2871 @@ -341,6 +341,10 @@
2872 bool "Support spear600"
2873 select CPU_ARM926EJS
2874
2875 +config TARGET_STV0991
2876 + bool "Support stv0991"
2877 + select CPU_V7
2878 +
2879 config TARGET_X600
2880 bool "Support x600"
2881 select CPU_ARM926EJS
2882 @@ -650,6 +654,7 @@
2883
2884 config TARGET_TBS2910
2885 bool "Support tbs2910"
2886 + select CPU_V7
2887
2888 config TARGET_TQMA6
2889 bool "TQ Systems TQMa6 board"
2890 @@ -728,12 +733,14 @@
2891 select ARM64
2892
2893 config TARGET_LS1021AQDS
2894 - bool "Support ls1021aqds_nor"
2895 + bool "Support ls1021aqds"
2896 select CPU_V7
2897 + select SUPPORT_SPL
2898
2899 config TARGET_LS1021ATWR
2900 - bool "Support ls1021atwr_nor"
2901 + bool "Support ls1021atwr"
2902 select CPU_V7
2903 + select SUPPORT_SPL
2904
2905 config TARGET_BALLOON3
2906 bool "Support balloon3"
2907 @@ -793,6 +800,7 @@
2908 bool "Panasonic UniPhier platform"
2909 select CPU_V7
2910 select SUPPORT_SPL
2911 + select SPL
2912 select OF_CONTROL if !SPL_BUILD
2913
2914 endchoice
2915 @@ -953,6 +961,7 @@
2916 source "board/spear/x600/Kconfig"
2917 source "board/st-ericsson/snowball/Kconfig"
2918 source "board/st-ericsson/u8500/Kconfig"
2919 +source "board/st/stv0991/Kconfig"
2920 source "board/sunxi/Kconfig"
2921 source "board/syteco/jadecpu/Kconfig"
2922 source "board/syteco/zmx25/Kconfig"
2923 diff -ruN u-boot-2015.01-rc3/arch/arm/lib/semihosting.c u-boot/arch/arm/lib/semihosting.c
2924 --- u-boot-2015.01-rc3/arch/arm/lib/semihosting.c 2014-12-08 22:35:08.000000000 +0100
2925 +++ u-boot/arch/arm/lib/semihosting.c 2015-01-01 17:34:32.133505219 +0100
2926 @@ -26,9 +26,9 @@
2927 /*
2928 * Call the handler
2929 */
2930 -static int smh_trap(unsigned int sysnum, void *addr)
2931 +static long smh_trap(unsigned int sysnum, void *addr)
2932 {
2933 - register int result asm("r0");
2934 + register long result asm("r0");
2935 #if defined(CONFIG_ARM64)
2936 asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
2937 #else
2938 @@ -39,167 +39,164 @@
2939 }
2940
2941 /*
2942 - * Open, load a file into memory, and close it. Check that the available space
2943 - * is sufficient to store the entire file. Return the bytes actually read from
2944 - * the file as seen by the read function. The verbose flag enables some extra
2945 - * printing of successful read status.
2946 + * Open a file on the host. Mode is "r" or "rb" currently. Returns a file
2947 + * descriptor or -1 on error.
2948 */
2949 -int smh_load(const char *fname, void *memp, int avail, int verbose)
2950 +static long smh_open(const char *fname, char *modestr)
2951 {
2952 - int ret, fd, len;
2953 -
2954 - ret = -1;
2955 -
2956 - debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname,
2957 - avail, memp);
2958 -
2959 - /* Open the file */
2960 - fd = smh_open(fname, "rb");
2961 - if (fd == -1)
2962 - return ret;
2963 + long fd;
2964 + unsigned long mode;
2965 + struct smh_open_s {
2966 + const char *fname;
2967 + unsigned long mode;
2968 + size_t len;
2969 + } open;
2970
2971 - /* Get the file length */
2972 - ret = smh_len_fd(fd);
2973 - if (ret == -1) {
2974 - smh_close(fd);
2975 - return ret;
2976 - }
2977 + debug("%s: file \'%s\', mode \'%s\'\n", __func__, fname, modestr);
2978
2979 - /* Check that the file will fit in the supplied buffer */
2980 - if (ret > avail) {
2981 - printf("%s: ERROR ret %d, avail %u\n", __func__, ret,
2982 - avail);
2983 - smh_close(fd);
2984 - return ret;
2985 + /* Check the file mode */
2986 + if (!(strcmp(modestr, "r"))) {
2987 + mode = MODE_READ;
2988 + } else if (!(strcmp(modestr, "rb"))) {
2989 + mode = MODE_READBIN;
2990 + } else {
2991 + printf("%s: ERROR mode \'%s\' not supported\n", __func__,
2992 + modestr);
2993 + return -1;
2994 }
2995
2996 - len = ret;
2997 -
2998 - /* Read the file into the buffer */
2999 - ret = smh_read(fd, memp, len);
3000 - if (ret == 0) {
3001 - /* Print successful load information if requested */
3002 - if (verbose) {
3003 - printf("\n%s\n", fname);
3004 - printf(" 0x%8p dest\n", memp);
3005 - printf(" 0x%08x size\n", len);
3006 - printf(" 0x%08x avail\n", avail);
3007 - }
3008 - }
3009 + open.fname = fname;
3010 + open.len = strlen(fname);
3011 + open.mode = mode;
3012
3013 - /* Close the file */
3014 - smh_close(fd);
3015 + /* Open the file on the host */
3016 + fd = smh_trap(SYSOPEN, &open);
3017 + if (fd == -1)
3018 + printf("%s: ERROR fd %ld for file \'%s\'\n", __func__, fd,
3019 + fname);
3020
3021 - return ret;
3022 + return fd;
3023 }
3024
3025 /*
3026 * Read 'len' bytes of file into 'memp'. Returns 0 on success, else failure
3027 */
3028 -int smh_read(int fd, void *memp, int len)
3029 +static long smh_read(long fd, void *memp, size_t len)
3030 {
3031 - int ret;
3032 + long ret;
3033 struct smh_read_s {
3034 - int fd;
3035 + long fd;
3036 void *memp;
3037 - int len;
3038 + size_t len;
3039 } read;
3040
3041 - debug("%s: fd %d, memp %p, len %d\n", __func__, fd, memp, len);
3042 + debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len);
3043
3044 read.fd = fd;
3045 read.memp = memp;
3046 read.len = len;
3047
3048 ret = smh_trap(SYSREAD, &read);
3049 - if (ret == 0) {
3050 - return 0;
3051 - } else {
3052 + if (ret < 0) {
3053 /*
3054 * The ARM handler allows for returning partial lengths,
3055 * but in practice this never happens so rather than create
3056 * hard to maintain partial read loops and such, just fail
3057 * with an error message.
3058 */
3059 - printf("%s: ERROR ret %d, fd %d, len %u memp %p\n",
3060 + printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n",
3061 __func__, ret, fd, len, memp);
3062 + return -1;
3063 }
3064 - return ret;
3065 +
3066 + return 0;
3067 }
3068
3069 /*
3070 - * Open a file on the host. Mode is "r" or "rb" currently. Returns a file
3071 - * descriptor or -1 on error.
3072 + * Close the file using the file descriptor
3073 */
3074 -int smh_open(const char *fname, char *modestr)
3075 +static long smh_close(long fd)
3076 {
3077 - int ret, fd, mode;
3078 - struct smh_open_s {
3079 - const char *fname;
3080 - unsigned int mode;
3081 - unsigned int len;
3082 - } open;
3083 + long ret;
3084
3085 - debug("%s: file \'%s\', mode \'%s\'\n", __func__, fname, modestr);
3086 -
3087 - ret = -1;
3088 + debug("%s: fd %ld\n", __func__, fd);
3089
3090 - /* Check the file mode */
3091 - if (!(strcmp(modestr, "r"))) {
3092 - mode = MODE_READ;
3093 - } else if (!(strcmp(modestr, "rb"))) {
3094 - mode = MODE_READBIN;
3095 - } else {
3096 - printf("%s: ERROR mode \'%s\' not supported\n", __func__,
3097 - modestr);
3098 - return ret;
3099 - }
3100 -
3101 - open.fname = fname;
3102 - open.len = strlen(fname);
3103 - open.mode = mode;
3104 -
3105 - /* Open the file on the host */
3106 - fd = smh_trap(SYSOPEN, &open);
3107 - if (fd == -1)
3108 - printf("%s: ERROR fd %d for file \'%s\'\n", __func__, fd,
3109 - fname);
3110 + ret = smh_trap(SYSCLOSE, &fd);
3111 + if (ret == -1)
3112 + printf("%s: ERROR fd %ld\n", __func__, fd);
3113
3114 - return fd;
3115 + return ret;
3116 }
3117
3118 /*
3119 - * Close the file using the file descriptor
3120 + * Get the file length from the file descriptor
3121 */
3122 -int smh_close(int fd)
3123 +static long smh_len_fd(long fd)
3124 {
3125 - int ret;
3126 - long fdlong;
3127 + long ret;
3128
3129 - debug("%s: fd %d\n", __func__, fd);
3130 + debug("%s: fd %ld\n", __func__, fd);
3131
3132 - fdlong = (long)fd;
3133 - ret = smh_trap(SYSCLOSE, &fdlong);
3134 + ret = smh_trap(SYSFLEN, &fd);
3135 if (ret == -1)
3136 - printf("%s: ERROR fd %d\n", __func__, fd);
3137 + printf("%s: ERROR ret %ld, fd %ld\n", __func__, ret, fd);
3138
3139 return ret;
3140 }
3141
3142 /*
3143 - * Get the file length from the file descriptor
3144 + * Open, load a file into memory, and close it. Check that the available space
3145 + * is sufficient to store the entire file. Return the bytes actually read from
3146 + * the file as seen by the read function. The verbose flag enables some extra
3147 + * printing of successful read status.
3148 */
3149 -int smh_len_fd(int fd)
3150 +int smh_load(const char *fname, void *memp, int avail, int verbose)
3151 {
3152 - int ret;
3153 - long fdlong;
3154 + long ret;
3155 + long fd;
3156 + size_t len;
3157
3158 - debug("%s: fd %d\n", __func__, fd);
3159 + ret = -1;
3160
3161 - fdlong = (long)fd;
3162 - ret = smh_trap(SYSFLEN, &fdlong);
3163 - if (ret == -1)
3164 - printf("%s: ERROR ret %d\n", __func__, ret);
3165 + debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname,
3166 + avail, memp);
3167 +
3168 + /* Open the file */
3169 + fd = smh_open(fname, "rb");
3170 + if (fd == -1)
3171 + return -1;
3172 +
3173 + /* Get the file length */
3174 + ret = smh_len_fd(fd);
3175 + if (ret == -1) {
3176 + smh_close(fd);
3177 + return -1;
3178 + }
3179 +
3180 + /* Check that the file will fit in the supplied buffer */
3181 + if (ret > avail) {
3182 + printf("%s: ERROR ret %ld, avail %u\n", __func__, ret,
3183 + avail);
3184 + smh_close(fd);
3185 + return -1;
3186 + }
3187 +
3188 + len = ret;
3189 +
3190 + /* Read the file into the buffer */
3191 + ret = smh_read(fd, memp, len);
3192 + if (ret == 0) {
3193 + /* Print successful load information if requested */
3194 + if (verbose) {
3195 + printf("\n%s\n", fname);
3196 + printf(" 0x%8p dest\n", memp);
3197 + printf(" 0x%08lx size\n", len);
3198 + printf(" 0x%08x avail\n", avail);
3199 + }
3200 + }
3201 +
3202 + /* Close the file */
3203 + smh_close(fd);
3204
3205 return ret;
3206 }
3207 @@ -207,26 +204,32 @@
3208 /*
3209 * Get the file length from the filename
3210 */
3211 -int smh_len(const char *fname)
3212 +long smh_len(const char *fname)
3213 {
3214 - int ret, fd, len;
3215 + long ret;
3216 + long fd;
3217 + long len;
3218
3219 debug("%s: file \'%s\'\n", __func__, fname);
3220
3221 /* Open the file */
3222 fd = smh_open(fname, "rb");
3223 - if (fd == -1)
3224 + if (fd < 0)
3225 return fd;
3226
3227 /* Get the file length */
3228 len = smh_len_fd(fd);
3229 + if (len < 0) {
3230 + smh_close(fd);
3231 + return len;
3232 + }
3233
3234 /* Close the file */
3235 ret = smh_close(fd);
3236 - if (ret == -1)
3237 + if (ret < 0)
3238 return ret;
3239
3240 - debug("%s: returning len %d\n", __func__, len);
3241 + debug("%s: returning len %ld\n", __func__, len);
3242
3243 /* Return the file length (or -1 error indication) */
3244 return len;
3245 diff -ruN u-boot-2015.01-rc3/arch/microblaze/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h u-boot/arch/microblaze/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h
3246 diff -ruN u-boot-2015.01-rc3/arch/microblaze/dts/include/dt-bindings/reset/altr,rst-mgr.h u-boot/arch/microblaze/dts/include/dt-bindings/reset/altr,rst-mgr.h
3247 diff -ruN u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/p5040_ids.c u-boot/arch/powerpc/cpu/mpc85xx/p5040_ids.c
3248 --- u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/p5040_ids.c 2014-12-08 22:35:08.000000000 +0100
3249 +++ u-boot/arch/powerpc/cpu/mpc85xx/p5040_ids.c 2015-01-01 17:34:32.221503777 +0100
3250 @@ -49,23 +49,23 @@
3251
3252 #ifdef CONFIG_SYS_DPAA_FMAN
3253 struct liodn_id_table fman1_liodn_tbl[] = {
3254 - SET_FMAN_RX_1G_LIODN(1, 0, 6),
3255 - SET_FMAN_RX_1G_LIODN(1, 1, 7),
3256 - SET_FMAN_RX_1G_LIODN(1, 2, 8),
3257 - SET_FMAN_RX_1G_LIODN(1, 3, 9),
3258 - SET_FMAN_RX_1G_LIODN(1, 4, 10),
3259 - SET_FMAN_RX_10G_LIODN(1, 0, 11),
3260 + SET_FMAN_RX_1G_LIODN(1, 0, 11),
3261 + SET_FMAN_RX_1G_LIODN(1, 1, 12),
3262 + SET_FMAN_RX_1G_LIODN(1, 2, 13),
3263 + SET_FMAN_RX_1G_LIODN(1, 3, 14),
3264 + SET_FMAN_RX_1G_LIODN(1, 4, 15),
3265 + SET_FMAN_RX_10G_LIODN(1, 0, 16),
3266 };
3267 int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
3268
3269 #if (CONFIG_SYS_NUM_FMAN == 2)
3270 struct liodn_id_table fman2_liodn_tbl[] = {
3271 - SET_FMAN_RX_1G_LIODN(2, 0, 12),
3272 - SET_FMAN_RX_1G_LIODN(2, 1, 13),
3273 - SET_FMAN_RX_1G_LIODN(2, 2, 14),
3274 - SET_FMAN_RX_1G_LIODN(2, 3, 15),
3275 - SET_FMAN_RX_1G_LIODN(2, 4, 16),
3276 - SET_FMAN_RX_10G_LIODN(2, 0, 17),
3277 + SET_FMAN_RX_1G_LIODN(2, 0, 17),
3278 + SET_FMAN_RX_1G_LIODN(2, 1, 18),
3279 + SET_FMAN_RX_1G_LIODN(2, 2, 19),
3280 + SET_FMAN_RX_1G_LIODN(2, 3, 20),
3281 + SET_FMAN_RX_1G_LIODN(2, 4, 21),
3282 + SET_FMAN_RX_10G_LIODN(2, 0, 22),
3283 };
3284 int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
3285 #endif
3286 diff -ruN u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/portals.c u-boot/arch/powerpc/cpu/mpc85xx/portals.c
3287 --- u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/portals.c 2014-12-08 22:35:08.000000000 +0100
3288 +++ u-boot/arch/powerpc/cpu/mpc85xx/portals.c 2015-01-01 17:34:32.221503777 +0100
3289 @@ -14,9 +14,46 @@
3290 #include <asm/fsl_portals.h>
3291 #include <asm/fsl_liodn.h>
3292
3293 +#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
3294 +#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
3295 +static void inhibit_portals(void __iomem *addr, int max_portals,
3296 + int arch_max_portals, int portal_cinh_size)
3297 +{
3298 + uint32_t val;
3299 + int i;
3300 +
3301 + /* arch_max_portals is the maximum based on memory size. This includes
3302 + * the reserved memory in the SoC. max_portals the number of physical
3303 + * portals in the SoC */
3304 + if (max_portals > arch_max_portals) {
3305 + printf("ERROR: portal config error\n");
3306 + max_portals = arch_max_portals;
3307 + }
3308 +
3309 + for (i = 0; i < max_portals; i++) {
3310 + out_be32(addr, -1);
3311 + val = in_be32(addr);
3312 + if (!val) {
3313 + printf("ERROR: Stopped after %d portals\n", i);
3314 + goto done;
3315 + }
3316 + addr += portal_cinh_size;
3317 + }
3318 +#ifdef DEBUG
3319 + printf("Cleared %d portals\n", i);
3320 +#endif
3321 +done:
3322 +
3323 + return;
3324 +}
3325 +
3326 void setup_portals(void)
3327 {
3328 ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
3329 + void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
3330 + CONFIG_SYS_BMAN_SWP_ISDR_REG;
3331 + void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
3332 + CONFIG_SYS_QMAN_SWP_ISDR_REG;
3333 #ifdef CONFIG_FSL_CORENET
3334 int i;
3335
3336 @@ -38,6 +75,12 @@
3337 out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
3338 #endif
3339 out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
3340 +
3341 + /* Change default state of BMan ISDR portals to all 1s */
3342 + inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
3343 + CONFIG_SYS_BMAN_SP_CINH_SIZE);
3344 + inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
3345 + CONFIG_SYS_QMAN_SP_CINH_SIZE);
3346 }
3347
3348 /* Update portal containter to match LAW setup of portal in phy map */
3349 diff -ruN u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/tlb.c u-boot/arch/powerpc/cpu/mpc85xx/tlb.c
3350 --- u-boot-2015.01-rc3/arch/powerpc/cpu/mpc85xx/tlb.c 2014-12-08 22:35:08.000000000 +0100
3351 +++ u-boot/arch/powerpc/cpu/mpc85xx/tlb.c 2015-01-01 17:34:32.221503777 +0100
3352 @@ -299,12 +299,16 @@
3353 {
3354 unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
3355 u64 memsize = (u64)memsize_in_meg << 20;
3356 + u64 size;
3357
3358 - memsize = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
3359 - memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
3360 + size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
3361 + size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM);
3362
3363 - if (memsize)
3364 - print_size(memsize, " left unmapped\n");
3365 + if (size || memsize > CONFIG_MAX_MEM_MAPPED) {
3366 + print_size(memsize > CONFIG_MAX_MEM_MAPPED ?
3367 + memsize - CONFIG_MAX_MEM_MAPPED + size : size,
3368 + " left unmapped\n");
3369 + }
3370
3371 return memsize_in_meg;
3372 }
3373 diff -ruN u-boot-2015.01-rc3/arch/powerpc/cpu/mpc8xxx/fdt.c u-boot/arch/powerpc/cpu/mpc8xxx/fdt.c
3374 --- u-boot-2015.01-rc3/arch/powerpc/cpu/mpc8xxx/fdt.c 2014-12-08 22:35:08.000000000 +0100
3375 +++ u-boot/arch/powerpc/cpu/mpc8xxx/fdt.c 2015-01-01 17:34:32.225503711 +0100
3376 @@ -73,110 +73,6 @@
3377 }
3378 #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */
3379
3380 -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
3381 -static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
3382 - const char *phy_type, int start_offset)
3383 -{
3384 - const char *compat_dr = "fsl-usb2-dr";
3385 - const char *compat_mph = "fsl-usb2-mph";
3386 - const char *prop_mode = "dr_mode";
3387 - const char *prop_type = "phy_type";
3388 - const char *node_type = NULL;
3389 - int node_offset;
3390 - int err;
3391 -
3392 - node_offset = fdt_node_offset_by_compatible(blob,
3393 - start_offset, compat_mph);
3394 - if (node_offset < 0) {
3395 - node_offset = fdt_node_offset_by_compatible(blob,
3396 - start_offset, compat_dr);
3397 - if (node_offset < 0) {
3398 - printf("WARNING: could not find compatible"
3399 - " node %s or %s: %s.\n", compat_mph,
3400 - compat_dr, fdt_strerror(node_offset));
3401 - return -1;
3402 - } else
3403 - node_type = compat_dr;
3404 - } else
3405 - node_type = compat_mph;
3406 -
3407 - if (mode) {
3408 - err = fdt_setprop(blob, node_offset, prop_mode, mode,
3409 - strlen(mode) + 1);
3410 - if (err < 0)
3411 - printf("WARNING: could not set %s for %s: %s.\n",
3412 - prop_mode, node_type, fdt_strerror(err));
3413 - }
3414 -
3415 - if (phy_type) {
3416 - err = fdt_setprop(blob, node_offset, prop_type, phy_type,
3417 - strlen(phy_type) + 1);
3418 - if (err < 0)
3419 - printf("WARNING: could not set %s for %s: %s.\n",
3420 - prop_type, node_type, fdt_strerror(err));
3421 - }
3422 -
3423 - return node_offset;
3424 -}
3425 -
3426 -void fdt_fixup_dr_usb(void *blob, bd_t *bd)
3427 -{
3428 - const char *modes[] = { "host", "peripheral", "otg" };
3429 - const char *phys[] = { "ulpi", "utmi" };
3430 - int usb_mode_off = -1;
3431 - int usb_phy_off = -1;
3432 - char str[5];
3433 - int i, j;
3434 -
3435 - for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
3436 - const char *dr_mode_type = NULL;
3437 - const char *dr_phy_type = NULL;
3438 - int mode_idx = -1, phy_idx = -1;
3439 - snprintf(str, 5, "%s%d", "usb", i);
3440 - if (hwconfig(str)) {
3441 - for (j = 0; j < ARRAY_SIZE(modes); j++) {
3442 - if (hwconfig_subarg_cmp(str, "dr_mode",
3443 - modes[j])) {
3444 - mode_idx = j;
3445 - break;
3446 - }
3447 - }
3448 -
3449 - for (j = 0; j < ARRAY_SIZE(phys); j++) {
3450 - if (hwconfig_subarg_cmp(str, "phy_type",
3451 - phys[j])) {
3452 - phy_idx = j;
3453 - break;
3454 - }
3455 - }
3456 -
3457 - if (mode_idx < 0 && phy_idx < 0) {
3458 - printf("WARNING: invalid phy or mode\n");
3459 - return;
3460 - }
3461 -
3462 - if (mode_idx > -1)
3463 - dr_mode_type = modes[mode_idx];
3464 -
3465 - if (phy_idx > -1)
3466 - dr_phy_type = phys[phy_idx];
3467 - }
3468 -
3469 - usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
3470 - dr_mode_type, NULL, usb_mode_off);
3471 -
3472 - if (usb_mode_off < 0)
3473 - return;
3474 -
3475 - usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
3476 - NULL, dr_phy_type, usb_phy_off);
3477 -
3478 - if (usb_phy_off < 0)
3479 - return;
3480 - }
3481 -}
3482 -#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
3483 -
3484 /*
3485 * update crypto node properties to a specified revision of the SEC
3486 * called with sec_rev == 0 if not on an E processor
3487 diff -ruN u-boot-2015.01-rc3/arch/sandbox/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h u-boot/arch/sandbox/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h
3488 diff -ruN u-boot-2015.01-rc3/arch/sandbox/dts/include/dt-bindings/reset/altr,rst-mgr.h u-boot/arch/sandbox/dts/include/dt-bindings/reset/altr,rst-mgr.h
3489 diff -ruN u-boot-2015.01-rc3/arch/sandbox/dts/sandbox.dts u-boot/arch/sandbox/dts/sandbox.dts
3490 --- u-boot-2015.01-rc3/arch/sandbox/dts/sandbox.dts 2014-12-08 22:35:08.000000000 +0100
3491 +++ u-boot/arch/sandbox/dts/sandbox.dts 2015-01-01 17:34:32.241503449 +0100
3492 @@ -134,6 +134,23 @@
3493 num-gpios = <20>;
3494 };
3495
3496 + i2c@0 {
3497 + #address-cells = <1>;
3498 + #size-cells = <0>;
3499 + reg = <0>;
3500 + compatible = "sandbox,i2c";
3501 + clock-frequency = <400000>;
3502 + eeprom@2c {
3503 + reg = <0x2c>;
3504 + compatible = "i2c-eeprom";
3505 + emul {
3506 + compatible = "sandbox,i2c-eeprom";
3507 + sandbox,filename = "i2c.bin";
3508 + sandbox,size = <128>;
3509 + };
3510 + };
3511 + };
3512 +
3513 spi@0 {
3514 #address-cells = <1>;
3515 #size-cells = <0>;
3516 diff -ruN u-boot-2015.01-rc3/arch/sandbox/include/asm/test.h u-boot/arch/sandbox/include/asm/test.h
3517 --- u-boot-2015.01-rc3/arch/sandbox/include/asm/test.h 1970-01-01 01:00:00.000000000 +0100
3518 +++ u-boot/arch/sandbox/include/asm/test.h 2015-01-01 17:34:32.241503449 +0100
3519 @@ -0,0 +1,26 @@
3520 +/*
3521 + * Test-related constants for sandbox
3522 + *
3523 + * Copyright (c) 2014 Google, Inc
3524 + *
3525 + * SPDX-License-Identifier: GPL-2.0+
3526 + */
3527 +
3528 +#ifndef __ASM_TEST_H
3529 +#define __ASM_TEST_H
3530 +
3531 +/* The sandbox driver always permits an I2C device with this address */
3532 +#define SANDBOX_I2C_TEST_ADDR 0x59
3533 +
3534 +enum sandbox_i2c_eeprom_test_mode {
3535 + SIE_TEST_MODE_NONE,
3536 + /* Permits read/write of only one byte per I2C transaction */
3537 + SIE_TEST_MODE_SINGLE_BYTE,
3538 +};
3539 +
3540 +void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
3541 + enum sandbox_i2c_eeprom_test_mode mode);
3542 +
3543 +void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len);
3544 +
3545 +#endif
3546 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/cpu.c u-boot/arch/x86/cpu/ivybridge/cpu.c
3547 --- u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/cpu.c 2014-12-08 22:35:08.000000000 +0100
3548 +++ u-boot/arch/x86/cpu/ivybridge/cpu.c 2015-01-01 17:34:32.249503317 +0100
3549 @@ -263,6 +263,7 @@
3550 static int report_bist_failure(void)
3551 {
3552 if (gd->arch.bist != 0) {
3553 + post_code(POST_BIST_FAILURE);
3554 printf("BIST failed: %08x\n", gd->arch.bist);
3555 return -EFAULT;
3556 }
3557 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/microcode_intel.c u-boot/arch/x86/cpu/ivybridge/microcode_intel.c
3558 --- u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/microcode_intel.c 2014-12-08 22:35:08.000000000 +0100
3559 +++ u-boot/arch/x86/cpu/ivybridge/microcode_intel.c 2015-01-01 17:34:32.249503317 +0100
3560 @@ -40,6 +40,8 @@
3561 update->data = fdt_getprop(blob, node, "data", &update->size);
3562 if (!update->data)
3563 return -EINVAL;
3564 + update->data += 48;
3565 + update->size -= 48;
3566
3567 update->header_version = fdtdec_get_int(blob, node,
3568 "intel,header-version", 0);
3569 @@ -48,17 +50,17 @@
3570 update->date_code = fdtdec_get_int(blob, node,
3571 "intel,date-code", 0);
3572 update->processor_signature = fdtdec_get_int(blob, node,
3573 - "intel.processor-signature", 0);
3574 + "intel,processor-signature", 0);
3575 update->checksum = fdtdec_get_int(blob, node, "intel,checksum", 0);
3576 update->loader_revision = fdtdec_get_int(blob, node,
3577 - "loader-revision", 0);
3578 + "intel,loader-revision", 0);
3579 update->processor_flags = fdtdec_get_int(blob, node,
3580 - "processor-flags", 0);
3581 + "intel,processor-flags", 0);
3582
3583 return 0;
3584 }
3585
3586 -static uint32_t microcode_read_rev(void)
3587 +static inline uint32_t microcode_read_rev(void)
3588 {
3589 /*
3590 * Some Intel CPUs can be very finicky about the CPUID sequence used.
3591 @@ -114,6 +116,7 @@
3592 {
3593 struct microcode_update cpu, update;
3594 const void *blob = gd->fdt_blob;
3595 + int skipped;
3596 int count;
3597 int node;
3598 int ret;
3599 @@ -121,12 +124,13 @@
3600 microcode_read_cpu(&cpu);
3601 node = 0;
3602 count = 0;
3603 + skipped = 0;
3604 do {
3605 node = fdtdec_next_compatible(blob, node,
3606 COMPAT_INTEL_MICROCODE);
3607 if (node < 0) {
3608 debug("%s: Found %d updates\n", __func__, count);
3609 - return count ? 0 : -ENOENT;
3610 + return count ? 0 : skipped ? -EEXIST : -ENOENT;
3611 }
3612
3613 ret = microcode_decode_node(blob, node, &update);
3614 @@ -135,12 +139,15 @@
3615 ret);
3616 return ret;
3617 }
3618 - if (update.processor_signature == cpu.processor_signature &&
3619 - (update.processor_flags & cpu.processor_flags)) {
3620 - debug("%s: Update already exists\n", __func__);
3621 - return -EEXIST;
3622 + if (!(update.processor_signature == cpu.processor_signature &&
3623 + (update.processor_flags & cpu.processor_flags))) {
3624 + debug("%s: Skipping non-matching update, sig=%x, pf=%x\n",
3625 + __func__, update.processor_signature,
3626 + update.processor_flags);
3627 + skipped++;
3628 + continue;
3629 }
3630 -
3631 + ret = microcode_read_rev();
3632 wrmsr(0x79, (ulong)update.data, 0);
3633 debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n",
3634 microcode_read_rev(), update.date_code & 0xffff,
3635 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/sdram.c u-boot/arch/x86/cpu/ivybridge/sdram.c
3636 --- u-boot-2015.01-rc3/arch/x86/cpu/ivybridge/sdram.c 2014-12-08 22:35:08.000000000 +0100
3637 +++ u-boot/arch/x86/cpu/ivybridge/sdram.c 2015-01-01 17:34:32.253503252 +0100
3638 @@ -177,7 +177,7 @@
3639
3640 debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
3641
3642 - data = (char *)CONFIG_X86_MRC_START;
3643 + data = (char *)CONFIG_X86_MRC_ADDR;
3644 if (data) {
3645 int rv;
3646 int (*func)(struct pei_data *);
3647 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/Makefile u-boot/arch/x86/cpu/Makefile
3648 --- u-boot-2015.01-rc3/arch/x86/cpu/Makefile 2014-12-08 22:35:08.000000000 +0100
3649 +++ u-boot/arch/x86/cpu/Makefile 2015-01-01 17:34:32.249503317 +0100
3650 @@ -15,6 +15,7 @@
3651 obj-$(CONFIG_SYS_COREBOOT) += coreboot/
3652 obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
3653 obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
3654 +obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
3655 obj-y += lapic.o
3656 obj-$(CONFIG_PCI) += pci.o
3657 obj-y += turbo.o
3658 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/fsp_configs.c u-boot/arch/x86/cpu/queensbay/fsp_configs.c
3659 --- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/fsp_configs.c 1970-01-01 01:00:00.000000000 +0100
3660 +++ u-boot/arch/x86/cpu/queensbay/fsp_configs.c 2015-01-01 17:34:32.253503252 +0100
3661 @@ -0,0 +1,20 @@
3662 +/*
3663 + * Copyright (C) 2013, Intel Corporation
3664 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3665 + *
3666 + * SPDX-License-Identifier: Intel
3667 + */
3668 +
3669 +#include <common.h>
3670 +#include <asm/arch/fsp/fsp_support.h>
3671 +
3672 +void update_fsp_upd(struct upd_region *fsp_upd)
3673 +{
3674 + /* Override any UPD setting if required */
3675 +
3676 + /* Uncomment the line below to enable DEBUG message */
3677 + /* fsp_upd->serial_dbgport_type = 1; */
3678 +
3679 + /* Examples on how to initialize the pointers in UPD region */
3680 + /* fsp_upd->pcd_example = (EXAMPLE_DATA *)&example; */
3681 +}
3682 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/fsp_support.c u-boot/arch/x86/cpu/queensbay/fsp_support.c
3683 --- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/fsp_support.c 1970-01-01 01:00:00.000000000 +0100
3684 +++ u-boot/arch/x86/cpu/queensbay/fsp_support.c 2015-01-01 17:34:32.253503252 +0100
3685 @@ -0,0 +1,401 @@
3686 +/*
3687 + * Copyright (C) 2013, Intel Corporation
3688 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3689 + *
3690 + * SPDX-License-Identifier: Intel
3691 + */
3692 +
3693 +#include <common.h>
3694 +#include <asm/arch/fsp/fsp_support.h>
3695 +#include <asm/post.h>
3696 +
3697 +/**
3698 + * Compares two GUIDs
3699 + *
3700 + * If the GUIDs are identical then true is returned.
3701 + * If there are any bit differences in the two GUIDs, then false is returned.
3702 + *
3703 + * @guid1: A pointer to a 128 bit GUID.
3704 + * @guid2: A pointer to a 128 bit GUID.
3705 + *
3706 + * @retval true: guid1 and guid2 are identical.
3707 + * @retval false: guid1 and guid2 are not identical.
3708 + */
3709 +static bool compare_guid(const struct efi_guid *guid1,
3710 + const struct efi_guid *guid2)
3711 +{
3712 + if (memcmp(guid1, guid2, sizeof(struct efi_guid)) == 0)
3713 + return true;
3714 + else
3715 + return false;
3716 +}
3717 +
3718 +u32 __attribute__((optimize("O0"))) find_fsp_header(void)
3719 +{
3720 + /*
3721 + * This function may be called before the a stack is established,
3722 + * so special care must be taken. First, it cannot declare any local
3723 + * variable using stack. Only register variable can be used here.
3724 + * Secondly, some compiler version will add prolog or epilog code
3725 + * for the C function. If so the function call may not work before
3726 + * stack is ready.
3727 + *
3728 + * GCC 4.8.1 has been verified to be working for the following codes.
3729 + */
3730 + volatile register u8 *fsp asm("eax");
3731 +
3732 + /* Initalize the FSP base */
3733 + fsp = (u8 *)CONFIG_FSP_ADDR;
3734 +
3735 + /* Check the FV signature, _FVH */
3736 + if (((struct fv_header *)fsp)->sign == EFI_FVH_SIGNATURE) {
3737 + /* Go to the end of the FV header and align the address */
3738 + fsp += ((struct fv_header *)fsp)->ext_hdr_off;
3739 + fsp += ((struct fv_ext_header *)fsp)->ext_hdr_size;
3740 + fsp = (u8 *)(((u32)fsp + 7) & 0xFFFFFFF8);
3741 + } else {
3742 + fsp = 0;
3743 + }
3744 +
3745 + /* Check the FFS GUID */
3746 + if (fsp &&
3747 + ((struct ffs_file_header *)fsp)->name.data1 == FSP_GUID_DATA1 &&
3748 + ((struct ffs_file_header *)fsp)->name.data2 == FSP_GUID_DATA2 &&
3749 + ((struct ffs_file_header *)fsp)->name.data3 == FSP_GUID_DATA3 &&
3750 + ((struct ffs_file_header *)fsp)->name.data4[0] == FSP_GUID_DATA4_0 &&
3751 + ((struct ffs_file_header *)fsp)->name.data4[1] == FSP_GUID_DATA4_1 &&
3752 + ((struct ffs_file_header *)fsp)->name.data4[2] == FSP_GUID_DATA4_2 &&
3753 + ((struct ffs_file_header *)fsp)->name.data4[3] == FSP_GUID_DATA4_3 &&
3754 + ((struct ffs_file_header *)fsp)->name.data4[4] == FSP_GUID_DATA4_4 &&
3755 + ((struct ffs_file_header *)fsp)->name.data4[5] == FSP_GUID_DATA4_5 &&
3756 + ((struct ffs_file_header *)fsp)->name.data4[6] == FSP_GUID_DATA4_6 &&
3757 + ((struct ffs_file_header *)fsp)->name.data4[7] == FSP_GUID_DATA4_7) {
3758 + /* Add the FFS header size to find the raw section header */
3759 + fsp += sizeof(struct ffs_file_header);
3760 + } else {
3761 + fsp = 0;
3762 + }
3763 +
3764 + if (fsp &&
3765 + ((struct raw_section *)fsp)->type == EFI_SECTION_RAW) {
3766 + /* Add the raw section header size to find the FSP header */
3767 + fsp += sizeof(struct raw_section);
3768 + } else {
3769 + fsp = 0;
3770 + }
3771 +
3772 + return (u32)fsp;
3773 +}
3774 +
3775 +void fsp_continue(struct shared_data *shared_data, u32 status, void *hob_list)
3776 +{
3777 + u32 stack_len;
3778 + u32 stack_base;
3779 + u32 stack_top;
3780 +
3781 + post_code(POST_MRC);
3782 +
3783 + assert(status == 0);
3784 +
3785 + /* Get the migrated stack in normal memory */
3786 + stack_base = (u32)fsp_get_bootloader_tmp_mem(hob_list, &stack_len);
3787 + assert(stack_base != 0);
3788 + stack_top = stack_base + stack_len - sizeof(u32);
3789 +
3790 + /*
3791 + * Old stack base is stored at the very end of the stack top,
3792 + * use it to calculate the migrated shared data base
3793 + */
3794 + shared_data = (struct shared_data *)(stack_base +
3795 + ((u32)shared_data - *(u32 *)stack_top));
3796 +
3797 + /* The boot loader main function entry */
3798 + fsp_init_done(hob_list);
3799 +}
3800 +
3801 +void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf)
3802 +{
3803 + struct shared_data shared_data;
3804 + fsp_init_f init;
3805 + struct fsp_init_params params;
3806 + struct fspinit_rtbuf rt_buf;
3807 + struct vpd_region *fsp_vpd;
3808 + struct fsp_header *fsp_hdr;
3809 + struct fsp_init_params *params_ptr;
3810 + struct upd_region *fsp_upd;
3811 +
3812 + fsp_hdr = (struct fsp_header *)find_fsp_header();
3813 + if (fsp_hdr == NULL) {
3814 + /* No valid FSP info header was found */
3815 + panic("Invalid FSP header");
3816 + }
3817 +
3818 + fsp_upd = (struct upd_region *)&shared_data.fsp_upd;
3819 + memset(&rt_buf, 0, sizeof(struct fspinit_rtbuf));
3820 +
3821 + /* Reserve a gap in stack top */
3822 + rt_buf.common.stack_top = (u32 *)stack_top - 32;
3823 + rt_buf.common.boot_mode = boot_mode;
3824 + rt_buf.common.upd_data = (struct upd_region *)fsp_upd;
3825 +
3826 + /* Get VPD region start */
3827 + fsp_vpd = (struct vpd_region *)(fsp_hdr->img_base +
3828 + fsp_hdr->cfg_region_off);
3829 +
3830 + /* Verifify the VPD data region is valid */
3831 + assert((fsp_vpd->img_rev == VPD_IMAGE_REV) &&
3832 + (fsp_vpd->sign == VPD_IMAGE_ID));
3833 +
3834 + /* Copy default data from Flash */
3835 + memcpy(fsp_upd, (void *)(fsp_hdr->img_base + fsp_vpd->upd_offset),
3836 + sizeof(struct upd_region));
3837 +
3838 + /* Verifify the UPD data region is valid */
3839 + assert(fsp_upd->terminator == UPD_TERMINATOR);
3840 +
3841 + /* Override any UPD setting if required */
3842 + update_fsp_upd(fsp_upd);
3843 +
3844 + memset(&params, 0, sizeof(struct fsp_init_params));
3845 + params.nvs_buf = nvs_buf;
3846 + params.rt_buf = (struct fspinit_rtbuf *)&rt_buf;
3847 + params.continuation = (fsp_continuation_f)asm_continuation;
3848 +
3849 + init = (fsp_init_f)(fsp_hdr->img_base + fsp_hdr->fsp_init);
3850 + params_ptr = &params;
3851 +
3852 + shared_data.fsp_hdr = fsp_hdr;
3853 + shared_data.stack_top = (u32 *)stack_top;
3854 +
3855 + post_code(POST_PRE_MRC);
3856 +
3857 + /*
3858 + * Use ASM code to ensure the register value in EAX & ECX
3859 + * will be passed into BlContinuationFunc
3860 + */
3861 + asm volatile (
3862 + "pushl %0;"
3863 + "call *%%eax;"
3864 + ".global asm_continuation;"
3865 + "asm_continuation:;"
3866 + "movl %%ebx, %%eax;" /* shared_data */
3867 + "movl 4(%%esp), %%edx;" /* status */
3868 + "movl 8(%%esp), %%ecx;" /* hob_list */
3869 + "jmp fsp_continue;"
3870 + : : "m"(params_ptr), "a"(init), "b"(&shared_data)
3871 + );
3872 +
3873 + /*
3874 + * Should never get here.
3875 + * Control will continue from fsp_continue.
3876 + * This line below is to prevent the compiler from optimizing
3877 + * structure intialization.
3878 + *
3879 + * DO NOT REMOVE!
3880 + */
3881 + init(&params);
3882 +}
3883 +
3884 +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase)
3885 +{
3886 + fsp_notify_f notify;
3887 + struct fsp_notify_params params;
3888 + struct fsp_notify_params *params_ptr;
3889 + u32 status;
3890 +
3891 + if (!fsp_hdr)
3892 + fsp_hdr = (struct fsp_header *)find_fsp_header();
3893 +
3894 + if (fsp_hdr == NULL) {
3895 + /* No valid FSP info header */
3896 + panic("Invalid FSP header");
3897 + }
3898 +
3899 + notify = (fsp_notify_f)(fsp_hdr->img_base + fsp_hdr->fsp_notify);
3900 + params.phase = phase;
3901 + params_ptr = &params;
3902 +
3903 + /*
3904 + * Use ASM code to ensure correct parameter is on the stack for
3905 + * FspNotify as U-Boot is using different ABI from FSP
3906 + */
3907 + asm volatile (
3908 + "pushl %1;" /* push notify phase */
3909 + "call *%%eax;" /* call FspNotify */
3910 + "addl $4, %%esp;" /* clean up the stack */
3911 + : "=a"(status) : "m"(params_ptr), "a"(notify), "m"(*params_ptr)
3912 + );
3913 +
3914 + return status;
3915 +}
3916 +
3917 +u32 fsp_get_usable_lowmem_top(const void *hob_list)
3918 +{
3919 + union hob_pointers hob;
3920 + phys_addr_t phys_start;
3921 + u32 top;
3922 +
3923 + /* Get the HOB list for processing */
3924 + hob.raw = (void *)hob_list;
3925 +
3926 + /* * Collect memory ranges */
3927 + top = FSP_LOWMEM_BASE;
3928 + while (!end_of_hob(hob)) {
3929 + if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
3930 + if (hob.res_desc->type == RES_SYS_MEM) {
3931 + phys_start = hob.res_desc->phys_start;
3932 + /* Need memory above 1MB to be collected here */
3933 + if (phys_start >= FSP_LOWMEM_BASE &&
3934 + phys_start < (phys_addr_t)FSP_HIGHMEM_BASE)
3935 + top += (u32)(hob.res_desc->len);
3936 + }
3937 + }
3938 + hob.raw = get_next_hob(hob);
3939 + }
3940 +
3941 + return top;
3942 +}
3943 +
3944 +u64 fsp_get_usable_highmem_top(const void *hob_list)
3945 +{
3946 + union hob_pointers hob;
3947 + phys_addr_t phys_start;
3948 + u64 top;
3949 +
3950 + /* Get the HOB list for processing */
3951 + hob.raw = (void *)hob_list;
3952 +
3953 + /* Collect memory ranges */
3954 + top = FSP_HIGHMEM_BASE;
3955 + while (!end_of_hob(hob)) {
3956 + if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
3957 + if (hob.res_desc->type == RES_SYS_MEM) {
3958 + phys_start = hob.res_desc->phys_start;
3959 + /* Need memory above 1MB to be collected here */
3960 + if (phys_start >= (phys_addr_t)FSP_HIGHMEM_BASE)
3961 + top += (u32)(hob.res_desc->len);
3962 + }
3963 + }
3964 + hob.raw = get_next_hob(hob);
3965 + }
3966 +
3967 + return top;
3968 +}
3969 +
3970 +u64 fsp_get_reserved_mem_from_guid(const void *hob_list, u64 *len,
3971 + struct efi_guid *guid)
3972 +{
3973 + union hob_pointers hob;
3974 +
3975 + /* Get the HOB list for processing */
3976 + hob.raw = (void *)hob_list;
3977 +
3978 + /* Collect memory ranges */
3979 + while (!end_of_hob(hob)) {
3980 + if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
3981 + if (hob.res_desc->type == RES_MEM_RESERVED) {
3982 + if (compare_guid(&hob.res_desc->owner, guid)) {
3983 + if (len)
3984 + *len = (u32)(hob.res_desc->len);
3985 +
3986 + return (u64)(hob.res_desc->phys_start);
3987 + }
3988 + }
3989 + }
3990 + hob.raw = get_next_hob(hob);
3991 + }
3992 +
3993 + return 0;
3994 +}
3995 +
3996 +u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len)
3997 +{
3998 + const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
3999 + u64 length;
4000 + u32 base;
4001 +
4002 + base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
4003 + &length, (struct efi_guid *)&guid);
4004 + if ((len != 0) && (base != 0))
4005 + *len = (u32)length;
4006 +
4007 + return base;
4008 +}
4009 +
4010 +u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len)
4011 +{
4012 + const struct efi_guid guid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID;
4013 + u64 length;
4014 + u32 base;
4015 +
4016 + base = (u32)fsp_get_reserved_mem_from_guid(hob_list,
4017 + &length, (struct efi_guid *)&guid);
4018 + if ((len != 0) && (base != 0))
4019 + *len = (u32)length;
4020 +
4021 + return base;
4022 +}
4023 +
4024 +void *fsp_get_next_hob(u16 type, const void *hob_list)
4025 +{
4026 + union hob_pointers hob;
4027 +
4028 + assert(hob_list != NULL);
4029 +
4030 + hob.raw = (u8 *)hob_list;
4031 +
4032 + /* Parse the HOB list until end of list or matching type is found */
4033 + while (!end_of_hob(hob)) {
4034 + if (get_hob_type(hob) == type)
4035 + return hob.raw;
4036 +
4037 + hob.raw = get_next_hob(hob);
4038 + }
4039 +
4040 + return NULL;
4041 +}
4042 +
4043 +void *fsp_get_next_guid_hob(const struct efi_guid *guid, const void *hob_list)
4044 +{
4045 + union hob_pointers hob;
4046 +
4047 + hob.raw = (u8 *)hob_list;
4048 + while ((hob.raw = fsp_get_next_hob(HOB_TYPE_GUID_EXT,
4049 + hob.raw)) != NULL) {
4050 + if (compare_guid(guid, &hob.guid->name))
4051 + break;
4052 + hob.raw = get_next_hob(hob);
4053 + }
4054 +
4055 + return hob.raw;
4056 +}
4057 +
4058 +void *fsp_get_guid_hob_data(const void *hob_list, u32 *len,
4059 + struct efi_guid *guid)
4060 +{
4061 + u8 *guid_hob;
4062 +
4063 + guid_hob = fsp_get_next_guid_hob(guid, hob_list);
4064 + if (guid_hob == NULL) {
4065 + return NULL;
4066 + } else {
4067 + if (len)
4068 + *len = get_guid_hob_data_size(guid_hob);
4069 +
4070 + return get_guid_hob_data(guid_hob);
4071 + }
4072 +}
4073 +
4074 +void *fsp_get_nvs_data(const void *hob_list, u32 *len)
4075 +{
4076 + const struct efi_guid guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
4077 +
4078 + return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
4079 +}
4080 +
4081 +void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len)
4082 +{
4083 + const struct efi_guid guid = FSP_BOOTLOADER_TEMP_MEM_HOB_GUID;
4084 +
4085 + return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid);
4086 +}
4087 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/Kconfig u-boot/arch/x86/cpu/queensbay/Kconfig
4088 --- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/Kconfig 1970-01-01 01:00:00.000000000 +0100
4089 +++ u-boot/arch/x86/cpu/queensbay/Kconfig 2015-01-01 17:34:32.253503252 +0100
4090 @@ -0,0 +1,79 @@
4091 +#
4092 +# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4093 +#
4094 +# SPDX-License-Identifier: GPL-2.0+
4095 +#
4096 +
4097 +config INTEL_QUEENSBAY
4098 + bool
4099 + select HAVE_FSP
4100 + select HAVE_CMC
4101 +
4102 +if INTEL_QUEENSBAY
4103 +
4104 +config HAVE_FSP
4105 + bool "Add an Firmware Support Package binary"
4106 + help
4107 + Select this option to add an Firmware Support Package binary to
4108 + the resulting U-Boot image. It is a binary blob which U-Boot uses
4109 + to set up SDRAM and other chipset specific initialization.
4110 +
4111 + Note: Without this binary U-Boot will not be able to set up its
4112 + SDRAM so will not boot.
4113 +
4114 +config FSP_FILE
4115 + string "Firmware Support Package binary filename"
4116 + depends on HAVE_FSP
4117 + default "fsp.bin"
4118 + help
4119 + The filename of the file to use as Firmware Support Package binary
4120 + in the board directory.
4121 +
4122 +config FSP_ADDR
4123 + hex "Firmware Support Package binary location"
4124 + depends on HAVE_FSP
4125 + default 0xfffc0000
4126 + help
4127 + FSP is not Position Independent Code (PIC) and the whole FSP has to
4128 + be rebased if it is placed at a location which is different from the
4129 + perferred base address specified during the FSP build. Use Intel's
4130 + Binary Configuration Tool (BCT) to do the rebase.
4131 +
4132 + The default base address of 0xfffc0000 indicates that the binary must
4133 + be located at offset 0xc0000 from the beginning of a 1MB flash device.
4134 +
4135 +config FSP_TEMP_RAM_ADDR
4136 + hex
4137 + default 0x2000000
4138 + help
4139 + Stack top address which is used in FspInit after DRAM is ready and
4140 + CAR is disabled.
4141 +
4142 +config HAVE_CMC
4143 + bool "Add a Chipset Micro Code state machine binary"
4144 + help
4145 + Select this option to add a Chipset Micro Code state machine binary
4146 + to the resulting U-Boot image. It is a 64K data block of machine
4147 + specific code which must be put in the flash for the processor to
4148 + access when powered up before system BIOS is executed.
4149 +
4150 +config CMC_FILE
4151 + string "Chipset Micro Code state machine filename"
4152 + depends on HAVE_CMC
4153 + default "cmc.bin"
4154 + help
4155 + The filename of the file to use as Chipset Micro Code state machine
4156 + binary in the board directory.
4157 +
4158 +config CMC_ADDR
4159 + hex "Chipset Micro Code state machine binary location"
4160 + depends on HAVE_CMC
4161 + default 0xfffb0000
4162 + help
4163 + The location of the CMC binary is determined by a strap. It must be
4164 + put in flash at a location matching the strap-determined base address.
4165 +
4166 + The default base address of 0xfffb0000 indicates that the binary must
4167 + be located at offset 0xb0000 from the beginning of a 1MB flash device.
4168 +
4169 +endif
4170 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/Makefile u-boot/arch/x86/cpu/queensbay/Makefile
4171 --- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/Makefile 1970-01-01 01:00:00.000000000 +0100
4172 +++ u-boot/arch/x86/cpu/queensbay/Makefile 2015-01-01 17:34:32.253503252 +0100
4173 @@ -0,0 +1,9 @@
4174 +#
4175 +# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4176 +#
4177 +# SPDX-License-Identifier: GPL-2.0+
4178 +#
4179 +
4180 +obj-y += tnc_car.o tnc_dram.o tnc.o topcliff.o
4181 +obj-y += fsp_configs.o fsp_support.o
4182 +obj-$(CONFIG_PCI) += tnc_pci.o
4183 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc.c u-boot/arch/x86/cpu/queensbay/tnc.c
4184 --- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc.c 1970-01-01 01:00:00.000000000 +0100
4185 +++ u-boot/arch/x86/cpu/queensbay/tnc.c 2015-01-01 17:34:32.253503252 +0100
4186 @@ -0,0 +1,72 @@
4187 +/*
4188 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4189 + *
4190 + * SPDX-License-Identifier: GPL-2.0+
4191 + */
4192 +
4193 +#include <common.h>
4194 +#include <asm/io.h>
4195 +#include <asm/pci.h>
4196 +#include <asm/post.h>
4197 +#include <asm/arch/tnc.h>
4198 +#include <asm/arch/fsp/fsp_support.h>
4199 +#include <asm/processor.h>
4200 +
4201 +static void unprotect_spi_flash(void)
4202 +{
4203 + u32 bc;
4204 +
4205 + bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
4206 + bc |= 0x1; /* unprotect the flash */
4207 + pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
4208 +}
4209 +
4210 +int arch_cpu_init(void)
4211 +{
4212 + struct pci_controller *hose;
4213 + int ret;
4214 +
4215 + post_code(POST_CPU_INIT);
4216 +#ifdef CONFIG_SYS_X86_TSC_TIMER
4217 + timer_set_base(rdtsc());
4218 +#endif
4219 +
4220 + ret = x86_cpu_init_f();
4221 + if (ret)
4222 + return ret;
4223 +
4224 + ret = pci_early_init_hose(&hose);
4225 + if (ret)
4226 + return ret;
4227 +
4228 + unprotect_spi_flash();
4229 +
4230 + return 0;
4231 +}
4232 +
4233 +int print_cpuinfo(void)
4234 +{
4235 + post_code(POST_CPU_INFO);
4236 + return default_print_cpuinfo();
4237 +}
4238 +
4239 +void reset_cpu(ulong addr)
4240 +{
4241 + /* cold reset */
4242 + outb(0x06, PORT_RESET);
4243 +}
4244 +
4245 +void board_final_cleanup(void)
4246 +{
4247 + u32 status;
4248 +
4249 + /* call into FspNotify */
4250 + debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
4251 + status = fsp_notify(NULL, INIT_PHASE_BOOT);
4252 + if (status != FSP_SUCCESS)
4253 + debug("fail, error code %x\n", status);
4254 + else
4255 + debug("OK\n");
4256 +
4257 + return;
4258 +}
4259 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_car.S u-boot/arch/x86/cpu/queensbay/tnc_car.S
4260 --- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_car.S 1970-01-01 01:00:00.000000000 +0100
4261 +++ u-boot/arch/x86/cpu/queensbay/tnc_car.S 2015-01-01 17:34:32.253503252 +0100
4262 @@ -0,0 +1,124 @@
4263 +/*
4264 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4265 + *
4266 + * SPDX-License-Identifier: GPL-2.0+
4267 + */
4268 +
4269 +#include <config.h>
4270 +#include <asm/post.h>
4271 +
4272 +.globl car_init
4273 +car_init:
4274 + /*
4275 + * Note: ebp holds the BIST value (built-in self test) so far, but ebp
4276 + * will be destroyed through the FSP call, thus we have to test the
4277 + * BIST value here before we call into FSP.
4278 + */
4279 + test %ebp, %ebp
4280 + jz car_init_start
4281 + post_code(POST_BIST_FAILURE)
4282 + jmp die
4283 +
4284 +car_init_start:
4285 + post_code(POST_CAR_START)
4286 + lea find_fsp_header_romstack, %esp
4287 + jmp find_fsp_header
4288 +
4289 +find_fsp_header_ret:
4290 + /* EAX points to FSP_INFO_HEADER */
4291 + mov %eax, %ebp
4292 +
4293 + /* sanity test */
4294 + cmp $CONFIG_FSP_ADDR, %eax
4295 + jb die
4296 +
4297 + /* calculate TempRamInitEntry address */
4298 + mov 0x30(%ebp), %eax
4299 + add 0x1c(%ebp), %eax
4300 +
4301 + /* call FSP TempRamInitEntry to setup temporary stack */
4302 + lea temp_ram_init_romstack, %esp
4303 + jmp *%eax
4304 +
4305 +temp_ram_init_ret:
4306 + addl $4, %esp
4307 + cmp $0, %eax
4308 + jnz car_init_fail
4309 +
4310 + post_code(POST_CAR_CPU_CACHE)
4311 +
4312 + /*
4313 + * The FSP TempRamInit initializes the ecx and edx registers to
4314 + * point to a temporary but writable memory range (Cache-As-RAM).
4315 + * ecx: the start of this temporary memory range,
4316 + * edx: the end of this range.
4317 + */
4318 +
4319 + /* stack grows down from top of CAR */
4320 + movl %edx, %esp
4321 +
4322 + /*
4323 + * TODO:
4324 + *
4325 + * According to FSP architecture spec, the fsp_init() will not return
4326 + * to its caller, instead it requires the bootloader to provide a
4327 + * so-called continuation function to pass into the FSP as a parameter
4328 + * of fsp_init, and fsp_init() will call that continuation function
4329 + * directly.
4330 + *
4331 + * The call to fsp_init() may need to be moved out of the car_init()
4332 + * to cpu_init_f() with the help of some inline assembly codes.
4333 + * Note there is another issue that fsp_init() will setup another stack
4334 + * using the fsp_init parameter stack_top after DRAM is initialized,
4335 + * which means any data on the previous stack (on the CAR) gets lost
4336 + * (ie: U-Boot global_data). FSP is supposed to support such scenario,
4337 + * however it does not work. This should be revisited in the future.
4338 + */
4339 + movl $CONFIG_FSP_TEMP_RAM_ADDR, %eax
4340 + xorl %edx, %edx
4341 + xorl %ecx, %ecx
4342 + call fsp_init
4343 +
4344 +.global fsp_init_done
4345 +fsp_init_done:
4346 + /*
4347 + * We come here from FspInit with eax pointing to the HOB list.
4348 + * Save eax to esi temporarily.
4349 + */
4350 + movl %eax, %esi
4351 + /*
4352 + * Re-initialize the ebp (BIST) to zero, as we already reach here
4353 + * which means we passed BIST testing before.
4354 + */
4355 + xorl %ebp, %ebp
4356 + jmp car_init_ret
4357 +
4358 +car_init_fail:
4359 + post_code(POST_CAR_FAILURE)
4360 +
4361 +die:
4362 + hlt
4363 + jmp die
4364 + hlt
4365 +
4366 + /*
4367 + * The function call before CAR initialization is tricky. It cannot
4368 + * be called using the 'call' instruction but only the 'jmp' with
4369 + * the help of a handcrafted stack in the ROM. The stack needs to
4370 + * contain the function return address as well as the parameters.
4371 + */
4372 + .balign 4
4373 +find_fsp_header_romstack:
4374 + .long find_fsp_header_ret
4375 +
4376 + .balign 4
4377 +temp_ram_init_romstack:
4378 + .long temp_ram_init_ret
4379 + .long temp_ram_init_params
4380 +temp_ram_init_params:
4381 +_dt_ucode_base_size:
4382 + /* These next two fields are filled in by ifdtool */
4383 + .long 0 /* microcode base */
4384 + .long 0 /* microcode size */
4385 + .long CONFIG_SYS_MONITOR_BASE /* code region base */
4386 + .long CONFIG_SYS_MONITOR_LEN /* code region size */
4387 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_dram.c u-boot/arch/x86/cpu/queensbay/tnc_dram.c
4388 --- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_dram.c 1970-01-01 01:00:00.000000000 +0100
4389 +++ u-boot/arch/x86/cpu/queensbay/tnc_dram.c 2015-01-01 17:34:32.253503252 +0100
4390 @@ -0,0 +1,78 @@
4391 +/*
4392 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4393 + *
4394 + * SPDX-License-Identifier: GPL-2.0+
4395 + */
4396 +
4397 +#include <common.h>
4398 +#include <asm/arch/fsp/fsp_support.h>
4399 +#include <asm/e820.h>
4400 +#include <asm/post.h>
4401 +
4402 +DECLARE_GLOBAL_DATA_PTR;
4403 +
4404 +int dram_init(void)
4405 +{
4406 + phys_size_t ram_size = 0;
4407 + union hob_pointers hob;
4408 +
4409 + hob.raw = gd->arch.hob_list;
4410 + while (!end_of_hob(hob)) {
4411 + if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
4412 + if (hob.res_desc->type == RES_SYS_MEM ||
4413 + hob.res_desc->type == RES_MEM_RESERVED) {
4414 + ram_size += hob.res_desc->len;
4415 + }
4416 + }
4417 + hob.raw = get_next_hob(hob);
4418 + }
4419 +
4420 + gd->ram_size = ram_size;
4421 + post_code(POST_DRAM);
4422 +
4423 + return 0;
4424 +}
4425 +
4426 +void dram_init_banksize(void)
4427 +{
4428 + gd->bd->bi_dram[0].start = 0;
4429 + gd->bd->bi_dram[0].size = gd->ram_size;
4430 +}
4431 +
4432 +/*
4433 + * This function looks for the highest region of memory lower than 4GB which
4434 + * has enough space for U-Boot where U-Boot is aligned on a page boundary.
4435 + * It overrides the default implementation found elsewhere which simply
4436 + * picks the end of ram, wherever that may be. The location of the stack,
4437 + * the relocation address, and how far U-Boot is moved by relocation are
4438 + * set in the global data structure.
4439 + */
4440 +ulong board_get_usable_ram_top(ulong total_size)
4441 +{
4442 + return fsp_get_usable_lowmem_top(gd->arch.hob_list);
4443 +}
4444 +
4445 +unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
4446 +{
4447 + unsigned num_entries = 0;
4448 +
4449 + union hob_pointers hob;
4450 +
4451 + hob.raw = gd->arch.hob_list;
4452 +
4453 + while (!end_of_hob(hob)) {
4454 + if (get_hob_type(hob) == HOB_TYPE_RES_DESC) {
4455 + entries[num_entries].addr = hob.res_desc->phys_start;
4456 + entries[num_entries].size = hob.res_desc->len;
4457 +
4458 + if (hob.res_desc->type == RES_SYS_MEM)
4459 + entries[num_entries].type = E820_RAM;
4460 + else if (hob.res_desc->type == RES_MEM_RESERVED)
4461 + entries[num_entries].type = E820_RESERVED;
4462 + }
4463 + hob.raw = get_next_hob(hob);
4464 + num_entries++;
4465 + }
4466 +
4467 + return num_entries;
4468 +}
4469 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_pci.c u-boot/arch/x86/cpu/queensbay/tnc_pci.c
4470 --- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/tnc_pci.c 1970-01-01 01:00:00.000000000 +0100
4471 +++ u-boot/arch/x86/cpu/queensbay/tnc_pci.c 2015-01-01 17:34:32.253503252 +0100
4472 @@ -0,0 +1,61 @@
4473 +/*
4474 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4475 + *
4476 + * SPDX-License-Identifier: GPL-2.0+
4477 + */
4478 +
4479 +#include <common.h>
4480 +#include <pci.h>
4481 +#include <asm/pci.h>
4482 +#include <asm/arch/fsp/fsp_support.h>
4483 +
4484 +DECLARE_GLOBAL_DATA_PTR;
4485 +
4486 +void board_pci_setup_hose(struct pci_controller *hose)
4487 +{
4488 + hose->first_busno = 0;
4489 + hose->last_busno = 0;
4490 +
4491 + /* PCI memory space */
4492 + pci_set_region(hose->regions + 0,
4493 + CONFIG_PCI_MEM_BUS,
4494 + CONFIG_PCI_MEM_PHYS,
4495 + CONFIG_PCI_MEM_SIZE,
4496 + PCI_REGION_MEM);
4497 +
4498 + /* PCI IO space */
4499 + pci_set_region(hose->regions + 1,
4500 + CONFIG_PCI_IO_BUS,
4501 + CONFIG_PCI_IO_PHYS,
4502 + CONFIG_PCI_IO_SIZE,
4503 + PCI_REGION_IO);
4504 +
4505 + pci_set_region(hose->regions + 2,
4506 + CONFIG_PCI_PREF_BUS,
4507 + CONFIG_PCI_PREF_PHYS,
4508 + CONFIG_PCI_PREF_SIZE,
4509 + PCI_REGION_PREFETCH);
4510 +
4511 + pci_set_region(hose->regions + 3,
4512 + 0,
4513 + 0,
4514 + gd->ram_size,
4515 + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
4516 +
4517 + hose->region_count = 4;
4518 +}
4519 +
4520 +int board_pci_post_scan(struct pci_controller *hose)
4521 +{
4522 + u32 status;
4523 +
4524 + /* call into FspNotify */
4525 + debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
4526 + status = fsp_notify(NULL, INIT_PHASE_PCI);
4527 + if (status != FSP_SUCCESS)
4528 + debug("fail, error code %x\n", status);
4529 + else
4530 + debug("OK\n");
4531 +
4532 + return 0;
4533 +}
4534 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/queensbay/topcliff.c u-boot/arch/x86/cpu/queensbay/topcliff.c
4535 --- u-boot-2015.01-rc3/arch/x86/cpu/queensbay/topcliff.c 1970-01-01 01:00:00.000000000 +0100
4536 +++ u-boot/arch/x86/cpu/queensbay/topcliff.c 2015-01-01 17:34:32.253503252 +0100
4537 @@ -0,0 +1,47 @@
4538 +/*
4539 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4540 + *
4541 + * SPDX-License-Identifier: GPL-2.0+
4542 + */
4543 +
4544 +#include <common.h>
4545 +#include <errno.h>
4546 +#include <malloc.h>
4547 +#include <pci.h>
4548 +#include <pci_ids.h>
4549 +#include <sdhci.h>
4550 +
4551 +static struct pci_device_id mmc_supported[] = {
4552 + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 },
4553 + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 },
4554 + { }
4555 +};
4556 +
4557 +int cpu_mmc_init(bd_t *bis)
4558 +{
4559 + struct sdhci_host *mmc_host;
4560 + pci_dev_t devbusfn;
4561 + u32 iobase;
4562 + int ret;
4563 + int i;
4564 +
4565 + for (i = 0; i < ARRAY_SIZE(mmc_supported); i++) {
4566 + devbusfn = pci_find_devices(mmc_supported, i);
4567 + if (devbusfn == -1)
4568 + return -ENODEV;
4569 +
4570 + mmc_host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
4571 + if (!mmc_host)
4572 + return -ENOMEM;
4573 +
4574 + mmc_host->name = "Topcliff SDHCI";
4575 + pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
4576 + mmc_host->ioaddr = (void *)iobase;
4577 + mmc_host->quirks = 0;
4578 + ret = add_sdhci(mmc_host, 0, 0);
4579 + if (ret)
4580 + return ret;
4581 + }
4582 +
4583 + return 0;
4584 +}
4585 diff -ruN u-boot-2015.01-rc3/arch/x86/cpu/start.S u-boot/arch/x86/cpu/start.S
4586 --- u-boot-2015.01-rc3/arch/x86/cpu/start.S 2014-12-08 22:35:08.000000000 +0100
4587 +++ u-boot/arch/x86/cpu/start.S 2015-01-01 17:34:32.253503252 +0100
4588 @@ -1,5 +1,5 @@
4589 /*
4590 - * U-boot - x86 Startup Code
4591 + * U-Boot - x86 Startup Code
4592 *
4593 * (C) Copyright 2008-2011
4594 * Graeme Russ, <graeme.russ@gmail.com>
4595 @@ -17,6 +17,7 @@
4596 #include <asm/processor.h>
4597 #include <asm/processor-flags.h>
4598 #include <generated/generic-asm-offsets.h>
4599 +#include <generated/asm-offsets.h>
4600
4601 .section .text
4602 .code32
4603 @@ -74,6 +75,7 @@
4604 jmp car_init
4605 .globl car_init_ret
4606 car_init_ret:
4607 +#ifndef CONFIG_HAVE_FSP
4608 /*
4609 * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
4610 * or fully initialised SDRAM - we really don't care which)
4611 @@ -94,6 +96,12 @@
4612 #ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
4613 subl $CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
4614 #endif
4615 +#else
4616 + /*
4617 + * When we get here after car_init, esp points to a temporary stack
4618 + * and esi holds the HOB list address returned by the FSP.
4619 + */
4620 +#endif
4621
4622 /* Reserve space on stack for global data */
4623 subl $GENERATED_GBL_DATA_SIZE, %esp
4624 @@ -108,6 +116,13 @@
4625 movl %esp, %edi
4626 rep stosb
4627
4628 +#ifdef CONFIG_HAVE_FSP
4629 + /* Store HOB list */
4630 + movl %esp, %edx
4631 + addl $GD_HOB_LIST, %edx
4632 + movl %esi, (%edx)
4633 +#endif
4634 +
4635 /* Setup first parameter to setup_gdt, pointer to global_data */
4636 movl %esp, %eax
4637
4638 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/chromebook_link.dts u-boot/arch/x86/dts/chromebook_link.dts
4639 --- u-boot-2015.01-rc3/arch/x86/dts/chromebook_link.dts 2014-12-08 22:35:08.000000000 +0100
4640 +++ u-boot/arch/x86/dts/chromebook_link.dts 2015-01-01 17:34:32.253503252 +0100
4641 @@ -214,10 +214,10 @@
4642
4643 microcode {
4644 update@0 {
4645 -#include "m12206a7_00000028.dtsi"
4646 +#include "microcode/m12206a7_00000029.dtsi"
4647 };
4648 update@1 {
4649 -#include "m12306a9_00000017.dtsi"
4650 +#include "microcode/m12306a9_0000001b.dtsi"
4651 };
4652 };
4653
4654 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/coreboot.dtsi u-boot/arch/x86/dts/coreboot.dtsi
4655 --- u-boot-2015.01-rc3/arch/x86/dts/coreboot.dtsi 2014-12-08 22:35:08.000000000 +0100
4656 +++ u-boot/arch/x86/dts/coreboot.dtsi 2015-01-01 17:34:32.253503252 +0100
4657 @@ -6,7 +6,7 @@
4658 };
4659
4660 serial {
4661 - compatible = "coreboot-uart";
4662 + compatible = "x86-uart";
4663 reg = <0x3f8 0x10>;
4664 reg-shift = <0>;
4665 io-mapped = <1>;
4666 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/crownbay.dts u-boot/arch/x86/dts/crownbay.dts
4667 --- u-boot-2015.01-rc3/arch/x86/dts/crownbay.dts 1970-01-01 01:00:00.000000000 +0100
4668 +++ u-boot/arch/x86/dts/crownbay.dts 2015-01-01 17:34:32.253503252 +0100
4669 @@ -0,0 +1,60 @@
4670 +/*
4671 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4672 + *
4673 + * SPDX-License-Identifier: GPL-2.0+
4674 + */
4675 +
4676 +/dts-v1/;
4677 +
4678 +/include/ "coreboot.dtsi"
4679 +
4680 +/ {
4681 + #address-cells = <1>;
4682 + #size-cells = <1>;
4683 + model = "Intel Crown Bay";
4684 + compatible = "intel,crownbay", "intel,queensbay";
4685 +
4686 + config {
4687 + silent_console = <0>;
4688 + };
4689 +
4690 + gpioa {
4691 + compatible = "intel,ich6-gpio";
4692 + u-boot,dm-pre-reloc;
4693 + reg = <0 0x20>;
4694 + bank-name = "A";
4695 + };
4696 +
4697 + gpiob {
4698 + compatible = "intel,ich6-gpio";
4699 + u-boot,dm-pre-reloc;
4700 + reg = <0x20 0x20>;
4701 + bank-name = "B";
4702 + };
4703 +
4704 + serial {
4705 + reg = <0x3f8 8>;
4706 + clock-frequency = <115200>;
4707 + };
4708 +
4709 + chosen { };
4710 + memory { device_type = "memory"; reg = <0 0>; };
4711 +
4712 + spi {
4713 + #address-cells = <1>;
4714 + #size-cells = <0>;
4715 + compatible = "intel,ich7";
4716 + spi-flash@0 {
4717 + reg = <0>;
4718 + compatible = "sst,25vf016b", "spi-flash";
4719 + memory-map = <0xffe00000 0x00200000>;
4720 + };
4721 + };
4722 +
4723 + microcode {
4724 + update@0 {
4725 +#include "microcode/m0220661105_cv.dtsi"
4726 + };
4727 + };
4728 +
4729 +};
4730 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h u-boot/arch/x86/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h
4731 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/include/dt-bindings/reset/altr,rst-mgr.h u-boot/arch/x86/dts/include/dt-bindings/reset/altr,rst-mgr.h
4732 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/link.dts u-boot/arch/x86/dts/link.dts
4733 --- u-boot-2015.01-rc3/arch/x86/dts/link.dts 2014-12-08 22:35:08.000000000 +0100
4734 +++ u-boot/arch/x86/dts/link.dts 2015-01-01 17:34:32.253503252 +0100
4735 @@ -214,10 +214,10 @@
4736
4737 microcode {
4738 update@0 {
4739 -#include "m12206a7_00000028.dtsi"
4740 +#include "microcode/m12206a7_00000029.dtsi"
4741 };
4742 update@1 {
4743 -#include "m12306a9_00000017.dtsi"
4744 +#include "microcode/m12306a9_0000001b.dtsi"
4745 };
4746 };
4747
4748 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/m12206a7_00000028.dtsi u-boot/arch/x86/dts/m12206a7_00000028.dtsi
4749 --- u-boot-2015.01-rc3/arch/x86/dts/m12206a7_00000028.dtsi 2014-12-08 22:35:08.000000000 +0100
4750 +++ u-boot/arch/x86/dts/m12206a7_00000028.dtsi 1970-01-01 01:00:00.000000000 +0100
4751 @@ -1,622 +0,0 @@
4752 -/*
4753 - * Copyright (c) <1995-2013>, Intel Corporation.
4754 - * All rights reserved.
4755 - *
4756 - * Redistribution. Redistribution and use in binary form, without modification, are
4757 - * permitted provided that the following conditions are met:
4758 - * .Redistributions must reproduce the above copyright notice and the following
4759 - * disclaimer in the documentation and/or other materials provided with the
4760 - * distribution.
4761 - * Neither the name of Intel Corporation nor the names of its suppliers may be used
4762 - * to endorse or promote products derived from this software without specific prior
4763 - * written permission.
4764 - * .No reverse engineering, decompilation, or disassembly of this software is
4765 - * permitted.
4766 - * ."Binary form" includes any format commonly used for electronic conveyance
4767 - * which is a reversible, bit-exact translation of binary representation to ASCII or
4768 - * ISO text, for example, "uuencode."
4769 - *
4770 - * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
4771 - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
4772 - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
4773 - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
4774 - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
4775 - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
4776 - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4777 - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
4778 - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
4779 - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
4780 - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
4781 - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
4782 - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4783 - *
4784 - *---
4785 - * This is a device tree fragment. Use #include to add these properties to a
4786 - * node.
4787 - */
4788 -
4789 -compatible = "intel,microcode";
4790 -intel,header-version = <1>;
4791 -intel,update-revision = <0x28>;
4792 -intel,date-code = <0x04242012>;
4793 -intel,processor-signature = <0x000206a7>;
4794 -intel,checksum = <0xf3e9935d>;
4795 -intel,loader-revision = <1>;
4796 -intel,processor-flags = <0x12>;
4797 -
4798 -/* The 48-byte public header is omitted. */
4799 -data = <
4800 - 0x00000000 0x000000a1 0x00020001 0x00000028
4801 - 0x00000000 0x00000000 0x20120423 0x000008f1
4802 - 0x00000001 0x000206a7 0x00000000 0x00000000
4803 - 0x00000000 0x00000000 0x00000000 0x00000000
4804 - 0x00000000 0x000008f1 0x00000000 0x00000000
4805 - 0x00000000 0x00000000 0x00000000 0x00000000
4806 - 0x52b813ac 0xdb8994c7 0x70e9f6bb 0x9d6db2ff
4807 - 0xf4d70f5d 0x5b1eccf6 0xac59106f 0x0ae2e2c1
4808 - 0x1a7bbeb1 0x355a1d62 0x2e7eb594 0x09f8dea9
4809 - 0x432a49e4 0xbf520253 0xdafa4010 0x893a858a
4810 - 0x766e0efb 0xd91e196d 0x838bd2ef 0xe5146494
4811 - 0xd515f413 0x29704828 0xe85598b6 0xdcbe6c51
4812 - 0x88eabbfa 0xa1e8909f 0xd8931721 0x35386554
4813 - 0x089a78a7 0xd9914775 0xd4644748 0x1556a4dc
4814 - 0xf44448f6 0xd054d7db 0xf30f2b7d 0x5ae223d0
4815 - 0xcbbb48b0 0x5c8b0383 0x177de157 0x9c1e5f73
4816 - 0x2ec28289 0xd72a7b6c 0x823b6eb2 0x35e02171
4817 - 0xba8deae4 0x06f4d468 0x13dbafaa 0x72b419f1
4818 - 0x033385b5 0x05806920 0x4c6034cf 0x9bd117dc
4819 - 0x976e2d04 0x250330f0 0x7250b5e1 0x184980c2
4820 - 0x12a9d7d6 0x1bc808f9 0xae79994f 0xc6f87901
4821 - 0xc0e3132f 0x671491c5 0x236cad39 0x37889d9c
4822 - 0x67f7c3f3 0x964a6be5 0xbcced7da 0x57eeaa6e
4823 - 0x7bca1522 0x654fee4c 0x2a1ca5d9 0xa1803cf3
4824 - 0x00000011 0x8c316d2c 0x17603b7e 0x32e42981
4825 - 0xc26c1400 0xf0fbccb6 0xeab6b43a 0x11d456a5
4826 - 0x5b912d46 0x15195fe0 0x542f6db3 0x0b7f212e
4827 - 0x47718dd9 0x7c41b108 0x06c21111 0x4445d5ea
4828 - 0xb4fb8128 0xe07404a6 0x8d503da4 0x78fc7e44
4829 - 0xb9919656 0x9968c797 0x87f26ab0 0x23bb1af7
4830 - 0x1ec5d761 0x26f30d2c 0x7cdb747c 0xe4d42033
4831 - 0x8a5d4801 0x768aff57 0xbcfd5d11 0x7c853c2d
4832 - 0x231e6207 0x8b1988a6 0xd68fdb75 0x58dcb417
4833 - 0x44422ef9 0x2a186ebb 0x7d27e85f 0x36ac31f7
4834 - 0x1e487e77 0x2b0b8c37 0xd8ba682f 0x2cba791b
4835 - 0xe6d3dece 0x1b2c2a99 0x4e5decab 0xfbd313a3
4836 - 0xdbc78294 0x5a80cce7 0x2d8e0f0b 0xcf564f71
4837 - 0x073d1f37 0x25162870 0x96cdb85b 0x9c553048
4838 - 0x24eba740 0xfc0f352e 0x0c83be68 0x89b5076c
4839 - 0xc39c4355 0x6a4cf25c 0x2bbd2682 0xc524fdb9
4840 - 0x7ea19bae 0x191ad6f1 0xd3fbf3bf 0x21bf77fa
4841 - 0x8f77fec4 0x0f90f635 0xe55e165c 0x868d58c0
4842 - 0x966bc0ad 0x6c276364 0x9d8f7eff 0x4b7925d4
4843 - 0x8b2f9326 0x4ab7b47e 0x33a9087c 0xf31ab949
4844 - 0x69831dfb 0x4711a215 0x8128c1fa 0x8481c213
4845 - 0x7401b01b 0xfdcfdc50 0xd6b55266 0xae9b23ac
4846 - 0xfa2ad275 0xa225bb45 0x4dd720c4 0x760a20e6
4847 - 0x5f1223c9 0x2f334372 0x6e1dcdab 0xe8ee8638
4848 - 0x1c19ba8a 0xef9341c4 0x360aaa9d 0x90452ea9
4849 - 0x65852446 0xe9398fa3 0xbba6a631 0x1a3e90b9
4850 - 0xe2a73a56 0x6e8c0747 0x35c7c53d 0xcc1ac842
4851 - 0x183356af 0xb6e98608 0x987b43c2 0xa8a3cfd2
4852 - 0xc2c5fce0 0xcc3af64a 0xd6d3a291 0xe59ad1f5
4853 - 0x124ca513 0x9522b50a 0x25150477 0xa2eb5797
4854 - 0x7fc63626 0x648c48e3 0x9f5797ff 0x2307b84d
4855 - 0x980625a4 0xabc05983 0x24980807 0x773c4f99
4856 - 0x3407b872 0x07c3657a 0xa2cd9e48 0x49c1e6a8
4857 - 0xa881b84c 0xf804d72c 0xb5319d2a 0x3e39780f
4858 - 0x97518822 0x0acd54c2 0x0721a9ff 0x10e1d2fd
4859 - 0xa7b6db77 0x845b1a56 0xef00160e 0x6b41bfd5
4860 - 0xc994df0d 0xcf44a5ca 0x794b36a4 0xf9fdb127
4861 - 0x922a1366 0x822aa8a9 0x4b137bd5 0x5722a49f
4862 - 0x8933719a 0x17edc1a9 0x079d9538 0x21fae7d5
4863 - 0xe534fd73 0x9d3038d5 0x48c3a056 0x5b22d58a
4864 - 0x6f142866 0xf1d767cd 0xb51ad5a6 0x34a0ef85
4865 - 0x0111703e 0xca4b3a30 0xa0f3c34d 0x9d48775a
4866 - 0x3f2059f9 0xf2fe2c36 0x588861a9 0xed5bd9fe
4867 - 0x8231f7cb 0x8c115969 0x3f82ba00 0x21b3730c
4868 - 0xba757997 0x3ec0bb2c 0x16f11def 0x5d4356c6
4869 - 0xdc2e0bc2 0x58c1eb6e 0x313ede0c 0xb68fcc52
4870 - 0x84d3e1b5 0xcc6d9201 0x95046196 0x276b527b
4871 - 0x80a4a729 0xe782916d 0x5cf09e0b 0x98aaf9fa
4872 - 0x1de6dd43 0xab4f1962 0x49ece734 0x81455488
4873 - 0xc2597b61 0x5b22af85 0x646f7b94 0x09213a1f
4874 - 0x08edf7e4 0x963d343c 0x059ba888 0xb4e804ed
4875 - 0xe7cc826c 0xf87bafc7 0xeecaec10 0x8e60919c
4876 - 0xbf14c996 0xd3dcaee3 0xb8fa0b7e 0x81563c6e
4877 - 0x7f59a258 0x2f344446 0x374d8aa6 0x9b6de5c9
4878 - 0xbf992857 0xbc5b94fc 0x28adb080 0x17e41044
4879 - 0xb87b469e 0xda504d12 0xf21bef8b 0xce75c1e3
4880 - 0xdbd92c83 0x58bba0af 0x77b42977 0x506cfd75
4881 - 0x1139e875 0x6ce5fe43 0xc6a5d7b3 0x87f9e628
4882 - 0x7b5c500b 0x130066b3 0x789b611f 0xec8c1ba9
4883 - 0xb7e6872d 0xaf828cd6 0xc28d3316 0x2a91f6d0
4884 - 0xc725f063 0x065ac531 0x4f9ef4b8 0x2b9d927e
4885 - 0xaf54f3f9 0x7c924f72 0xda1d77ad 0xff00db67
4886 - 0xaf4f03c0 0xb4f4ee64 0x169e64e5 0x04653ac0
4887 - 0xed51cb70 0xfeaff0e5 0x51dbf346 0x072a2407
4888 - 0x23fb74f4 0x9a906eef 0x5d6fc3f0 0xbc3c374c
4889 - 0x1cf9f063 0x919015d9 0x5b3e9d07 0xd6209d8b
4890 - 0xa3710b3d 0x90ad23b8 0x420ceedc 0x58e8371f
4891 - 0x5d419d1f 0xb8acd13f 0x7d100d6d 0x210c10d1
4892 - 0xcd0a697e 0x5023db4b 0x33e6d8e7 0x44bbe6b4
4893 - 0x827e859f 0x6ca4cc81 0x661bb2c3 0x71209ee8
4894 - 0xb8c3ffaf 0xd1075f51 0xba1eae10 0x728b0a6a
4895 - 0xe4af7a2f 0xca9bcf2e 0xb249a631 0xdce6be47
4896 - 0x5c910321 0x425c3c27 0x33083e43 0xdea067ae
4897 - 0xea594a23 0x41b75c2c 0x3a401a95 0xd33cd88a
4898 - 0xc295cad0 0x67f48045 0x1dc9ad4c 0x4bc48864
4899 - 0x53991b6e 0x7aadde5f 0x2b0bf775 0x06ba5380
4900 - 0x9eb874be 0x2c4b967a 0x1bcc342f 0xe875001b
4901 - 0x15b5642d 0x5be99c9d 0xcb210ace 0x1b4924ad
4902 - 0x3793ed81 0x8b983114 0x3ec33981 0x75ec71e7
4903 - 0x8b5b7df3 0x834756f4 0x100fad01 0x70037fdf
4904 - 0x0cef9a36 0x3d9e3a2d 0x38b48efd 0xfc4034b6
4905 - 0xa32e29dd 0x388944bc 0xc1c15614 0x3877e9c7
4906 - 0xa5e733fa 0xa621bd53 0x4b651df6 0xce082970
4907 - 0x85f30d6f 0x729a5c87 0x31dd7ba9 0xdb495828
4908 - 0x7b12c698 0x953495c9 0x6b5f99e7 0x2cc42fa8
4909 - 0x697ac512 0x1be679de 0xc116d305 0x94a36606
4910 - 0x9e5e141e 0x874affed 0x58d40b0b 0x5e3cf5e5
4911 - 0x5d05e9a9 0x06840efc 0xd2f98b21 0xa1e83ab2
4912 - 0x4f726202 0xa6394535 0x62a02403 0x9f2167ec
4913 - 0x4f9fc77b 0x98073be4 0x2bc781fa 0xfc8e4c89
4914 - 0xc7179b97 0x692cf793 0x708ff7bb 0x12ecba93
4915 - 0xacd06e21 0x202bef76 0x03852241 0xe84e02a1
4916 - 0xf1f9ac8d 0xcee61aef 0x61a4f235 0xd22991eb
4917 - 0x67a81345 0x375a15c6 0xe8fae8a3 0xb4ff2b37
4918 - 0x339ee4ea 0x14ffadc3 0xf49340dd 0xf285e568
4919 - 0x00fc6970 0x369c52d1 0x4f55368f 0x3f4d75f1
4920 - 0x6a73b603 0x963c1f59 0x171e2bdc 0x72bac76b
4921 - 0x9e2e5c32 0x307f7c3f 0xd3b48637 0x3a917acf
4922 - 0xea52a65f 0xecd209fb 0xf0ad84bf 0xd4bdea70
4923 - 0xa2647b38 0xce040b49 0xc6d5f13d 0x5d942c52
4924 - 0xf8edc042 0x798fdefd 0x4b074246 0x1cb1873a
4925 - 0x6793c186 0x23b9c774 0x77bb0202 0xc519b3aa
4926 - 0xa30c09a2 0xe1f6669a 0xb7eddb8d 0x7aaa91d6
4927 - 0x076a3789 0x0ac47791 0x1e503404 0x44fe8c54
4928 - 0xf3cbbf49 0xd3234eef 0x0d898b3f 0xe854984b
4929 - 0xe3986de9 0x923a5c76 0x2ee9abca 0x1a9fedbe
4930 - 0xdf76dcd1 0xea07936b 0xcdaaf247 0xe62d98fa
4931 - 0xa99c7f7b 0x34fc84d4 0x03a35111 0xad5675c8
4932 - 0xcc64075b 0x408203f9 0x846e1f08 0xe934019e
4933 - 0x423d1223 0x2f04f9e3 0xee1dbf40 0x65edc60f
4934 - 0x097aa22f 0x7058a2b7 0x41c8a0a5 0xa68aa391
4935 - 0x0f345c40 0x667517e6 0x860838ba 0x6dae933b
4936 - 0x764d5919 0x6673fa0f 0xf0a5e97d 0x4262ebbe
4937 - 0x64b413f2 0xd2c4145a 0x0b2c11f3 0xfdfe9f93
4938 - 0x96c77107 0x1399fdda 0xf599f215 0xb504da5d
4939 - 0xf8a95268 0x9ed1ef87 0x9ae33cfb 0x3b21f1ef
4940 - 0xc6d447c2 0xe0694d4e 0x967febab 0xc13f631d
4941 - 0x8393bfba 0x37438788 0x1724194d 0x8e77a045
4942 - 0x20e2483c 0xb961c2fc 0x485cf593 0xb3462621
4943 - 0xcb2959b8 0x10307e19 0xf71fbbfd 0xdda641e1
4944 - 0x0daf5f66 0x56d85178 0x145f6749 0xebc46ed1
4945 - 0x5593c249 0x94561f51 0x534cc654 0xca7c8814
4946 - 0xb59a578c 0x40b2b614 0xeaf3437a 0x198d5b4e
4947 - 0xf245fa53 0xfb75e0b0 0xa363c46d 0xc43b5468
4948 - 0xdf036413 0xc59f5a36 0xd8ff4381 0xa3af3e36
4949 - 0x7af63462 0x414526d7 0x7bdc41c5 0xa416f1e7
4950 - 0x6987d9ad 0x472c5499 0x4f10ee37 0x47bb7ff7
4951 - 0xc7f2e621 0x820008f7 0x33a475db 0x91ff5d72
4952 - 0x0517401c 0x73d067c8 0xe417b69d 0xb86d9903
4953 - 0x1ac9a032 0x74bbf582 0x8b65596e 0x883be34c
4954 - 0x95dcc26f 0xe232c646 0xfae9c19f 0x35cb5273
4955 - 0x6a94d095 0xfff6ca91 0xb9c40eb5 0xd351dcac
4956 - 0xc90d464f 0x9b609642 0x15663b56 0x15f7f88d
4957 - 0x22499f60 0x417fd6c5 0x2dc36fe2 0x712bf66a
4958 - 0x22f1fba8 0x531b8092 0x40d269b6 0x1d227898
4959 - 0xeb6ff35b 0x2490ac31 0xc958ed65 0x3ce6ffb7
4960 - 0x9338a806 0x3beadfe2 0x1c361ac9 0x53d0e3b0
4961 - 0x91d46102 0x4d57045f 0xb5c8afb3 0xfd2c9e7d
4962 - 0x3d578410 0x2adb9406 0x10df7459 0x90abccfb
4963 - 0xe3f217ed 0xef5f4e09 0x74925ce4 0x169b5879
4964 - 0xfeff4ad5 0xb300dd1d 0xc96022ba 0x72da501b
4965 - 0x1e694296 0x9efa33cb 0x0dc3ee6c 0x0ac4e7ea
4966 - 0x73041130 0xf0e6a295 0xc46bdb6a 0x6a927044
4967 - 0xd217ceca 0x0b744007 0xd5a2bafb 0x4220cd92
4968 - 0x70d3352a 0x5ee4f661 0xfa07e5c0 0x155542d9
4969 - 0x4a39fba0 0xcec0552d 0x30c1d8ef 0xbef9d21e
4970 - 0x183879aa 0x5b3f30a8 0x54a06db4 0xef876e4e
4971 - 0x5e823680 0x53e2a353 0xc9aa4112 0x13a56ee5
4972 - 0x848859fd 0x0ba2b801 0xec15260f 0x7bb22672
4973 - 0x1a097332 0xb141339f 0x752a67d9 0xdae373f3
4974 - 0x3c8cfd49 0x2dfaf2a9 0x95820c6c 0x956b39a2
4975 - 0x1ca0d24e 0x1312b978 0x7280e1bd 0xa7a7c2ff
4976 - 0x0b48e987 0xb6083e55 0x4b4b82f4 0x9c6104ad
4977 - 0xcb93beca 0xe1c34035 0x34de740d 0xbb151baa
4978 - 0x71f5942f 0x1eaac228 0x0c68331b 0x3d2a1dd0
4979 - 0xe7a3d41a 0x7253acae 0xfd4de230 0x79988d80
4980 - 0x4468f19b 0xac4440fd 0x6e8a6ef3 0x5736adf8
4981 - 0xded67716 0x1f1d5a4b 0x96c5f451 0x85bae181
4982 - 0x1293ab28 0xc2ba53c2 0x729ff4cf 0x60218df8
4983 - 0xc2870138 0x6127d844 0x89604e9e 0xd2b9ad4e
4984 - 0x4f6ded9f 0xdd263849 0x1633bd92 0x64b03a24
4985 - 0x96dabd4d 0x6e85d235 0x1ab69ad0 0x9aa80454
4986 - 0x6b9041e0 0x106c7e9a 0x8f54812f 0xa274efe4
4987 - 0xe45d6695 0xf3aa7bd3 0x6a5a2a63 0xe36f3525
4988 - 0x6238fa4b 0x7d6cb06f 0x16d3b4a2 0xf3b04822
4989 - 0x638f1a60 0x0e1875fa 0x1c0292b9 0x6b519ea4
4990 - 0x9faba37b 0x209341ec 0x83c9061f 0x3387dfe8
4991 - 0xc7f12ceb 0x2bef45d7 0x8f8acb47 0x35d9741b
4992 - 0x7009f514 0xfd003802 0x6f9489c5 0xe2ea2504
4993 - 0x910e996a 0xcc81d016 0x3280730d 0xdedfef59
4994 - 0x5a7357cc 0x8fe8dd39 0x15543fe5 0x976c4207
4995 - 0xe41cf62b 0x0ba6b4b5 0x5c3b7ced 0xa6c5b72b
4996 - 0x72ad3b4d 0xff143181 0x2b78a157 0x7fe231a5
4997 - 0x6ff0538a 0xe58ed1ac 0x81a311a5 0xefaa54b8
4998 - 0xf04a797e 0xce6e69c7 0xdc810726 0x7bab7be3
4999 - 0xdd5923e8 0x5a2413ed 0x31cef794 0x73dfd806
5000 - 0x1b9223c1 0x0c370882 0x04fa3b68 0x87c50bc1
5001 - 0x1d78c90f 0xf4e2cee6 0xebea941b 0x73e5838f
5002 - 0xca8d39a6 0xe004296b 0x28cf8a0e 0x7c73e7ef
5003 - 0x26a296c2 0x789d4c72 0xd1490265 0xd9a9e843
5004 - 0xf03504c3 0xfae6dffb 0x7a48f00d 0x51e369c8
5005 - 0xcb3eeee6 0x0625e936 0xe93d0d7d 0xfb15ba6b
5006 - 0xec5c76da 0x8fdf44f1 0xa036653a 0x5730c4a3
5007 - 0xe5bfe6dd 0x0b8c091f 0x3b51558c 0x403748f4
5008 - 0xf4007f86 0x952b5db6 0x5524d8ba 0x8046409a
5009 - 0xe3fc61a9 0x66f4ea56 0x5645150b 0xdb2bec15
5010 - 0x50672218 0x7f40e87d 0x2b8359f8 0x438787dc
5011 - 0x7f221597 0xf8b1590c 0x4f468251 0xff586d05
5012 - 0xb9195380 0x0ee09e0b 0x2fa7dbd9 0xd197b327
5013 - 0xa0dbad58 0xb485681f 0x5ef0937c 0x1e07ebb6
5014 - 0xcb49fe3f 0xc2427cd9 0x6c2c5298 0x4a2e171a
5015 - 0xa7f333a8 0xb3609ad6 0x94e374d6 0x0e1eb64d
5016 - 0x22c3367d 0xcdf89975 0x647aceef 0x16727c9c
5017 - 0xf476ae53 0x35a1212e 0x0db768b8 0xfff8b53d
5018 - 0xbd4fe45e 0xab28a5a3 0x59cec0af 0x28bcd1ef
5019 - 0x6f43ad69 0x2658a059 0x27aee0ec 0x4e8bbd15
5020 - 0xa9fdcf04 0xc9aa329f 0x687f010f 0x5c968a07
5021 - 0xb894e607 0x0e1cba22 0x2f00f203 0xe8e133ac
5022 - 0x494a4746 0xe8bdff9a 0xf69791a2 0x64179ce2
5023 - 0xbfd10dc6 0xc026f6d8 0x4871923a 0x8946b277
5024 - 0x609f49a4 0x6466df1b 0xd8c3c131 0x46ef0291
5025 - 0x0fdce8b6 0x2b9aedb7 0x225c4520 0x72b332cf
5026 - 0x4e220d47 0xf2f69c36 0x2c23fad9 0x57a2a918
5027 - 0xe017409c 0x490819af 0xf2121afd 0x951ff7ff
5028 - 0x40363fcf 0x5078b94e 0x9e4be775 0xee97ef16
5029 - 0xdb3a2390 0x17d42af9 0x96f56a51 0x1b4c2934
5030 - 0xc866315c 0x2b746f99 0x9a3b73f6 0xa1e081fc
5031 - 0xa9d07ebd 0xa6359fae 0xdf50d099 0x55304e01
5032 - 0xfe5aaa81 0x1e74267d 0x38b1d2d7 0x8633e9af
5033 - 0x99b013df 0x3aa05831 0x86279736 0xd2b464e0
5034 - 0xdf036a9f 0xe8162915 0x876c0d4f 0x4beb7d0e
5035 - 0xfec9b170 0x46bc9df4 0x46cb88fa 0x0cb5904d
5036 - 0x2e2961cf 0x7ea5dc1a 0x60670df2 0xf935ca32
5037 - 0x67e6777b 0x8bacc97a 0x5cd07248 0x32e483e6
5038 - 0xfdf09b0d 0xca57150b 0x3f432d09 0xdea2d7db
5039 - 0x9f6a2954 0x6f07dff3 0x4133f394 0x60272f97
5040 - 0x1b98c9ec 0x2ab648d9 0xb5df14a8 0x0d2c38f2
5041 - 0x5dfde2c4 0x7cb43ca3 0x8d0c6c01 0xe80ea41e
5042 - 0x5f58b71e 0x4ca9fef2 0xabd201a4 0x50905c08
5043 - 0xca8ba387 0x5592922b 0xfa4e05f5 0xceb64b14
5044 - 0x0845c5bd 0x518d369b 0x727e570c 0x1daaab31
5045 - 0x801e8b9c 0xec6568f3 0xd4c3760f 0x40a78d22
5046 - 0x38af58b5 0xc406a76e 0x8c3a7779 0x18272c42
5047 - 0x45cf7b70 0xa6f3c0f3 0x88021e41 0xda662504
5048 - 0xe97aa709 0xe93bafe0 0x8862ed5f 0x35bc8268
5049 - 0xf5a41551 0x3dd3bb21 0x1af0cf11 0x08fe1ad7
5050 - 0x53ecae41 0x01a4a8ae 0xfed636b7 0xf09323e6
5051 - 0x73b9b253 0x7ebd7ce2 0x7074b4de 0x21c719b2
5052 - 0x50982743 0xd23cfd27 0x136a1f4a 0x23260f6e
5053 - 0xfad89dcd 0x57586681 0xadc4fba5 0xad0f71b8
5054 - 0x91a3f188 0x20d62385 0xfecda9cb 0x33d67776
5055 - 0x2abb0e6c 0x0ad16087 0x486332da 0x2928d342
5056 - 0xf6d1b174 0x5e133a4e 0x72fc0ad4 0x940578b8
5057 - 0x320a42b1 0x9cbda7d4 0xf2a36135 0x00ab8de3
5058 - 0x5bad9000 0x5778e633 0x3952763d 0xe0e58583
5059 - 0xdfb0bf19 0xb11914b6 0xa67da7a1 0x8d9a9f81
5060 - 0x638cbcf7 0x83bf931d 0x8703b0dd 0xcab30fa4
5061 - 0xd6db2ee6 0x5cc2e5ac 0x717e636b 0xfdcbc760
5062 - 0x563b3b25 0x0e4df458 0x9efb8fa7 0x95aaa7a1
5063 - 0xf05b6680 0x5e237e59 0xc884018a 0x177b5a30
5064 - 0x3ea2c9bc 0xd0325ee6 0xb1dae51b 0x812ee29d
5065 - 0x6d58db21 0xb787fa68 0xfd092294 0x09683dd3
5066 - 0xfe0d6405 0xfdd99aad 0x78744a59 0x936738e6
5067 - 0x6ad6cba7 0x370f7f8f 0xd208c214 0x12239384
5068 - 0xbe71f0e7 0xfc0ef264 0xc04e4a49 0x354f9cf3
5069 - 0xf5d7572c 0x07839ad0 0x834a003d 0x23ba26e2
5070 - 0xf4049ecf 0x5ff402b2 0xff9d6769 0x074ebe6d
5071 - 0xdc829da1 0xc3d7697d 0x973efe4f 0xfc2a9165
5072 - 0x126dc518 0x0b824ca4 0xc438fb70 0xb7b0ee00
5073 - 0xbe56afd9 0xa3d8defd 0x971455ae 0xc11ffde7
5074 - 0x346e619a 0xb41111a9 0x6004b62e 0x896c668d
5075 - 0x738e458c 0x351f9fdd 0xe771b2ba 0xad6d7464
5076 - 0x719b57c2 0x6f6a4611 0x8a676f2d 0xb8db1c43
5077 - 0x3f102641 0x51bffdbc 0xb7862565 0x5d8dd231
5078 - 0x7a79bd39 0xfa472894 0x0fd1d2ff 0x64cf589a
5079 - 0x38234d7a 0x5c9acefd 0x8eb0b9f8 0x761e1c95
5080 - 0xf2fe78fa 0xe06220d7 0xaf82a919 0xf4e196e1
5081 - 0xa17c8935 0x06d08d16 0x6bad807b 0xf410805d
5082 - 0x4ff2bce6 0x3297c81f 0x06e35353 0xbe1f5e1c
5083 - 0x65d1cb92 0x0dc69b2f 0xac55d597 0x636ff24c
5084 - 0xe2e4f2ba 0x63d64922 0x4b2e9f71 0xad2279ec
5085 - 0x5f0b5c0e 0xac688638 0x35613358 0xf5531360
5086 - 0x54a304e8 0x27ebfe65 0x977b5a3c 0x3dc5e10c
5087 - 0x73b32ee9 0x3a2c9454 0x30a149c6 0x31e5b55c
5088 - 0x2c10854f 0x745cd38a 0x2853a27b 0x6629e355
5089 - 0x0bb67e39 0x5469184d 0x694a9bb6 0x0a0ca25f
5090 - 0xa878c5de 0xee15fd46 0x23d92ff8 0x02328404
5091 - 0x1c9402b5 0xa46b6ce0 0xefc3e947 0x0e9312ad
5092 - 0x5830ae9e 0xe30e32f2 0x9db8ee81 0xe8aeebbc
5093 - 0x30675c83 0x447278c2 0xab2bad3b 0x08ba3d0c
5094 - 0x1124e681 0x3691242d 0x903c8d2b 0x3281c312
5095 - 0x22af690f 0xd69a150c 0x57622c5b 0x29313c73
5096 - 0x6ab2d7c6 0x39b06dad 0x6e1f9f81 0x03324986
5097 - 0x53a49093 0x7654eba3 0x2527245a 0x9af596fb
5098 - 0x818ffb3a 0xa3817173 0x6a2c4b80 0xfcc42ad5
5099 - 0xfb1bbb69 0x3a3720a2 0x90a89bcf 0xed80308d
5100 - 0x7753cb1c 0x1c2654a5 0xb01ee4af 0x81091e85
5101 - 0x9067b3f1 0x2e2b9b5e 0x9fb0c7d1 0x78fd9f69
5102 - 0x5771c46d 0xacdf498d 0xfd8b8e77 0x4c15fa61
5103 - 0x607120ce 0x18a298d8 0x73716420 0x65e5e06a
5104 - 0x18c53e04 0x35b84427 0xcd82b522 0x9a7d26bb
5105 - 0xd56b4b74 0x49b47fe8 0x63178dc6 0x0bac0f46
5106 - 0xc8b0755a 0x9bbaaf1f 0x18131d2b 0xcc019330
5107 - 0x0ceb89bb 0x8808c2d6 0xfb5bd86c 0x6c945b71
5108 - 0xdc911924 0x4ebb8d35 0x44e46d08 0xabfee615
5109 - 0xf456931f 0x7a244955 0x0bffce7d 0x5533ca5f
5110 - 0xb1b2c636 0x4f29075e 0x64012561 0x7aa5e7c7
5111 - 0x9c8a0666 0x9698782d 0x3481ad8f 0x21a55b19
5112 - 0x735aa45d 0x4245b9c4 0x0d4c3fdc 0xd1b10966
5113 - 0x7035fcde 0xc2257947 0x4a37271a 0x9da464a9
5114 - 0x228adbf8 0xbf309e03 0x096f560a 0xa2b8ca78
5115 - 0x427702cd 0x35a99cf5 0x99811758 0x6953db58
5116 - 0xec07533e 0xe95838b9 0x61c71654 0xc9cce595
5117 - 0x275af106 0xc8697af3 0xb3f27e58 0x411d8d30
5118 - 0xd0d90ecd 0x1503b9dc 0x76bf070e 0x49f89ef0
5119 - 0x7333b083 0x53f9c44b 0x8330c3a2 0x6a1119c3
5120 - 0xca555f2b 0x3d51fc6f 0xac7b3320 0xf8e42cdf
5121 - 0x053753fe 0xc122336f 0x94d289c6 0x088b5a64
5122 - 0xc3aac7f0 0x96a76344 0x2ff05828 0x9b4f2af3
5123 - 0x46de6a46 0x4ed29d98 0xe2ab7634 0x27481ddc
5124 - 0x300ca71f 0xce7ac539 0x88240e09 0xb1a14e78
5125 - 0x2addd4c5 0xb3a7f320 0xe91f549b 0x6881c45b
5126 - 0x0e381c47 0x1018feb4 0x64679650 0xe62281cc
5127 - 0x670ee6d4 0x0d226160 0x947b7f08 0xbc595a74
5128 - 0x2380c0b3 0xc0235785 0x63b41221 0x80b9cc31
5129 - 0x3231b4ae 0x33ed5718 0xf2c5c90f 0xdd3b03ea
5130 - 0x67dfca08 0x453e9d29 0xa2bdecbf 0x5e9a3181
5131 - 0xad17aea2 0xff0a8f13 0xdf946849 0xcfbbecb7
5132 - 0xb0a602d7 0xb1a820c6 0xfe7abbc8 0x7f70790d
5133 - 0xeb5f8863 0x266d3cc1 0xbd552a44 0xe19b1b3d
5134 - 0x856aefbd 0x51c11f1e 0xde661b7f 0x61c075d2
5135 - 0xd0f6a834 0xff1d0d37 0x6793d1c2 0x70c133a5
5136 - 0x20c4d2cf 0x8c80d4d3 0x61ebe382 0x788b74df
5137 - 0x11c56903 0x535889ba 0x0a9c7380 0xf9de2837
5138 - 0x09437fe7 0x1627c6b2 0xb943bdb8 0x69bc29b2
5139 - 0xee9795a4 0x83c992e0 0x95437918 0x8ce166a2
5140 - 0x56b56b66 0xb0680941 0x623d38a9 0x2add07ad
5141 - 0xe583ba09 0x96f6532a 0x3eff4696 0x2a8a6b0b
5142 - 0x905b913b 0xafc01673 0xe871e006 0x2c2339ad
5143 - 0x248438e5 0x96d83e53 0xb3a75d6b 0x2258cf63
5144 - 0x69ff39bf 0x95727173 0xc3ac09d5 0xea8d2c06
5145 - 0x0e7c0a4b 0x144fcade 0x28a9a5a3 0x97c11ae8
5146 - 0x89865e3d 0x1640cd32 0xe3e551f8 0x1f7ba770
5147 - 0x6d23fb31 0x11eceae3 0xc8ccb8ee 0x46dd0bb0
5148 - 0xd01a46ff 0x0504adf5 0xec6e170e 0x2e3d7ac5
5149 - 0x70f893ac 0xaf9963db 0x061e283c 0xf0ad248f
5150 - 0x2fe97e19 0x881fd340 0xc686c9d5 0x88ea8ba5
5151 - 0x92f05cd7 0xd6716148 0x6fc47fc3 0x2c51d9b9
5152 - 0xd50a7faf 0x4eccacd1 0x7c92f802 0xa63ffc83
5153 - 0x7cb0ab1d 0x4492e81b 0x7d906554 0x43306ba1
5154 - 0x73a5d57a 0xe57a05d6 0x6850b964 0xefed595c
5155 - 0x7754978f 0x629e8236 0x62ec4dde 0x247439ee
5156 - 0x8b9982fa 0x4eece5c2 0x48599175 0x0fdc752c
5157 - 0xecd87b12 0x94936c75 0x17a45ea1 0x80a899ac
5158 - 0x22a39ee7 0x745730b6 0x03ea4daf 0x4a7570d7
5159 - 0x307621fa 0x7322e0a7 0x3a8e0316 0x454e46f7
5160 - 0x08773750 0x156dcaad 0x5562bc06 0xa23a1ee3
5161 - 0x20435211 0x1d679ea0 0xb220e205 0x682cc1a6
5162 - 0xd64a71c7 0x3ca7f8e3 0x2e92f253 0xa7cfdd0b
5163 - 0xd62b4053 0xf5c5f641 0xbf72dde1 0xdcb716c1
5164 - 0xe2f7b05d 0xa03145ea 0xc09828d2 0x7dae7916
5165 - 0x6fb97c79 0xb3a85204 0x998a9c7b 0x5f42ba8c
5166 - 0xd9c628b3 0x6b17bacb 0xa889b716 0x450ff97d
5167 - 0xe9166f3c 0x2d20777b 0x82a003ae 0x2c7ae0aa
5168 - 0x6011a9fe 0xfeed34be 0x1328f67e 0xf61003a3
5169 - 0xfaecdf20 0xee18c81e 0x731a0302 0x11a39e60
5170 - 0x355d78dc 0x99088f2c 0xcf253759 0x97347603
5171 - 0x736f71f1 0x37e4b395 0x9cc74540 0xf7e39994
5172 - 0xf01c5f64 0xbec519f1 0xa79c1067 0x76000d5e
5173 - 0x1ac85b6e 0x51e5b7a3 0x62a97ddf 0x6f20096a
5174 - 0x2af51e77 0xea5554f6 0xb4e581da 0xc1ac4ba8
5175 - 0xc8f22bf7 0x9e254d3b 0xd7dd62f6 0x6461ae3e
5176 - 0x423e1f10 0xf143e7b9 0x18c73b04 0xa43de614
5177 - 0x2da8d02f 0x9befa706 0xc01dcd49 0xa278f1e0
5178 - 0xd85f3177 0x6b6679fd 0x1ccef04e 0x53af9252
5179 - 0x34d751db 0xc8d32c86 0x3d725097 0xa64ed581
5180 - 0xd090c42f 0x9e92bf3f 0x6f82b089 0xd42728eb
5181 - 0x3dd651e0 0x1985bc52 0x4b0f4159 0x0f99bd7f
5182 - 0xe2597023 0xca0cae4c 0xce48a894 0x7249dd88
5183 - 0x8e146632 0xb4be1d6c 0x790ae7e5 0x6747b657
5184 - 0x52143947 0xa2e42ed3 0xea359617 0x6ca01a11
5185 - 0x35c5e2dc 0xc97b78fc 0x5db6db2a 0x80fe3414
5186 - 0x27da19d4 0xd7431d04 0xa91e9110 0x7d8ecb23
5187 - 0x2508700a 0xc8c71ed9 0xd28835af 0x018c2887
5188 - 0x3d0a6fab 0x3e8523d6 0xd0688dee 0xe5c3865c
5189 - 0x838d72e4 0x6bb73a1d 0x497a59ca 0xf77c56de
5190 - 0x38ecb72e 0xa55e3565 0x04b12c92 0x1aec9997
5191 - 0x037c340a 0xef0d04c3 0x78f74bd6 0xdec9b9e8
5192 - 0xd95b61ea 0x5528e8f5 0x4ecd325c 0x88ffdc0b
5193 - 0xb337ac61 0x899d90e7 0xb5eeb978 0x8295d9ae
5194 - 0x1ed8978b 0xa8849eda 0x8633b4a3 0xb8c858b5
5195 - 0xbe3c4375 0x28b9e84e 0xb2a26def 0x22f8f66b
5196 - 0x3a4aed99 0x0c4914ea 0xad103249 0xba5a5eff
5197 - 0x8a052461 0x26938899 0x915c6ed7 0xe6268ad9
5198 - 0x246e8c74 0x75f3c196 0xc3e725d6 0x92e02549
5199 - 0x1f78a5cb 0xeada57e5 0x40f14906 0x0215e49c
5200 - 0x57c06bae 0xc1896b87 0x0cd40a63 0x60741d80
5201 - 0x11a69899 0x80fed942 0x0497e115 0x56697b55
5202 - 0xba89c3d4 0x27d6b7c5 0xddff87b0 0xd3b1ff2f
5203 - 0x3160e528 0x9cca1286 0x13b4fdf1 0x38cdd907
5204 - 0xb50c4597 0x4c151714 0x1cab86c7 0x23126a3e
5205 - 0xe26e9749 0x289a0d0e 0xc4004640 0x9d33928d
5206 - 0x33b691a2 0x15ed6e6b 0x6e773980 0xadd59678
5207 - 0x188ba49f 0x08da4c6d 0x6d150d0b 0x0c6c7b98
5208 - 0xc8e1df7e 0xb8b1e692 0x5e89fd35 0xcb253d24
5209 - 0xfc6ee27c 0x8013de3d 0x1d38012b 0xe50a8f7b
5210 - 0x7d410ff1 0xceee4e9f 0x0e8094b6 0xaa1a5f57
5211 - 0xb395a551 0xbd62b2ae 0x5d7b34c8 0xbd2d6195
5212 - 0x33af4109 0x0769ff18 0x9c6cc123 0x78ee6eb6
5213 - 0x412644e7 0x70e0c6f4 0xf45d8fc6 0x0435f5af
5214 - 0xd43622b7 0x27409d5b 0x6dd04e8f 0x9f02ecf5
5215 - 0xca415f7d 0xc9f439c2 0x7198e539 0x20476b75
5216 - 0x3cdd8dd8 0xce17fbb0 0xa5bc115e 0xb0ee52c1
5217 - 0x0b074cfa 0xd26d4f99 0x3b43320b 0x230b680b
5218 - 0x9908f2d2 0xcbcb1952 0xf45a2f53 0x7b4564c6
5219 - 0xcf2fd983 0x414fe4b2 0x55ea7f11 0x63e8117d
5220 - 0xe8954052 0x7c2ea344 0x97a02aaf 0x6ca874c3
5221 - 0x1ae5b4ee 0x41754eae 0x6954abe0 0x115ddcda
5222 - 0x9a27968b 0x32a53e65 0xffe47b2f 0x4fe7e5a7
5223 - 0x6016dedc 0xb3c0893e 0x9626776d 0x5ec773f9
5224 - 0x1104e01c 0x1473cfb3 0x43b2cedf 0x8ca9d119
5225 - 0x7f1bc844 0xd8bb7387 0xba90d2ef 0x2bb0dcf4
5226 - 0x2340f124 0xa5bd514c 0x50afab05 0x718f5ad5
5227 - 0x7c03fad9 0x71d00d2d 0x1c31fdc2 0x4a938809
5228 - 0x40945ded 0x437f2a0d 0x83c10d64 0xd224c6ab
5229 - 0x0cd44481 0xb0040966 0x27fd6e7f 0x6ff45d4c
5230 - 0xab057ad1 0x8fa4e5d4 0xac50270c 0x6e4926ca
5231 - 0xc5721498 0x2529b458 0x40ee2ad5 0xde5e21f2
5232 - 0xea8964ca 0x56766e60 0xdc3b8702 0xa93528d4
5233 - 0x28d7713d 0x42edf022 0x59774dd8 0x200ff942
5234 - 0xe7a4d769 0xd8c4ef5e 0xe177f715 0xe9d53cd6
5235 - 0xc11270bb 0xb25977e5 0xb80867b4 0xfb48468b
5236 - 0xdbf166a8 0x49700d85 0x0f85f98a 0xa7ca7a75
5237 - 0x109817ce 0xca243f19 0x8bed7688 0x9a1c8231
5238 - 0x94f0ce97 0xc36309ca 0x90ecac24 0x67e7e0de
5239 - 0x86b18d62 0x18c7b7a5 0x622f5d3a 0x47e1e067
5240 - 0xdc96b94d 0xe4a03beb 0x59d17692 0x040abc0d
5241 - 0x44a5ae50 0x3d3dab7d 0xc18dfd30 0x2802b9d9
5242 - 0x6818379f 0x56db41d7 0x97cbf039 0xe41d6a32
5243 - 0x64b5fb01 0x6506e0b4 0xd60a3234 0xdf3573d2
5244 - 0xac148579 0xe7f46ac0 0x05e1c763 0x904a5aa9
5245 - 0xc7ca1ee0 0xe0c3b047 0x5e36e1bc 0x447a9141
5246 - 0xe24654df 0x9853a49b 0x6a29cedb 0x022f00dc
5247 - 0x6df2a7a7 0x3636da02 0x72bb9c81 0x4f0e0918
5248 - 0xd649f4a5 0xbb0c81f9 0xc0ba93fd 0xc1b390f1
5249 - 0xda84e720 0x1aea0064 0xf3ee67e1 0xb874ef4a
5250 - 0x82467ce6 0x59abf506 0xafbf145a 0x9a4cf8a1
5251 - 0x17247c89 0xd8669398 0x1796eaf7 0xbc2d24a9
5252 - 0xcb486570 0x17a9db23 0x3e6504f0 0x08684517
5253 - 0x2723ab28 0x7081b814 0x8a265a04 0x697e6d8b
5254 - 0x69b146dc 0x6434c182 0x27ec8101 0x864405c5
5255 - 0xfff86c9e 0x3052d8a6 0x23d283db 0x492970e8
5256 - 0xbc6c64c3 0x46d8f98b 0xe16e7ff3 0x731e4f82
5257 - 0xbd26b1af 0x6b30e6c1 0xff192fce 0x097e0bba
5258 - 0x49df63a5 0x2fdc3f01 0x50aae053 0x60177b8f
5259 - 0x1949eb85 0xa46084ce 0x9658f694 0xcb951fbc
5260 - 0xc53806d9 0x63a17d30 0x3b3f86c2 0x8a37aa6c
5261 - 0xedf8fe5c 0x87aee1d3 0x8c680126 0xfd8b27a6
5262 - 0x231fa106 0x69358c25 0x4502c348 0xc107861c
5263 - 0x46280e70 0xcf6067ac 0xf6a04ff3 0x3e488677
5264 - 0x6f3fb4c1 0xeec1f758 0x560e1c48 0xb604c06b
5265 - 0x69e34b1e 0x8ef41dec 0x854cea22 0x726581d7
5266 - 0x55ea91f3 0x38ae4053 0x5ff7389d 0x6952cbf6
5267 - 0x09aa0fc1 0xcccb1d50 0x5c1a633a 0xde1eba46
5268 - 0x797212d8 0xa943fb3d 0x6063a1a8 0xbe68ef36
5269 - 0x6ba0d5ba 0x0dbe2061 0x47711712 0x62679807
5270 - 0x6f34009e 0xe6fe8f18 0x66a6a64b 0x3f80f472
5271 - 0xe953d5e0 0xbcd8196a 0x086faad0 0x49da7f16
5272 - 0x7f2199a5 0x55af4af2 0x085b4d38 0x22e634bd
5273 - 0x6cff0416 0x343466f4 0xd121a7a6 0x6caa3942
5274 - 0xe4f365a2 0xd832eb0c 0x616728e5 0xcca4c71a
5275 - 0x4010cdc2 0xd0f1d1cb 0x5e695f89 0x27719206
5276 - 0x0ec92854 0x76144a1b 0x49808021 0x12457a1b
5277 - 0xdde7aa5c 0x8f1a077f 0x110a4a5a 0xb3a5ad31
5278 - 0xaacebf8f 0x66ff7f33 0xa2340971 0xfb4c7e82
5279 - 0x8dd536d7 0xafd2021a 0x72aa9c6e 0x22df6952
5280 - 0x83c4b4fb 0xba515555 0x93eee8f0 0x22d0ed5a
5281 - 0xbec05586 0x83828f28 0xe0d7f930 0xac0f0199
5282 - 0xef6d76f9 0xf56ebdf8 0xf67323c9 0x8b805745
5283 - 0xce5902c0 0xfa2ce3da 0x10f836dd 0xe1ac6d97
5284 - 0xa0e415ea 0xbb7c32ad 0xc421f3b0 0x8166e898
5285 - 0x74e7a73c 0xf454b82a 0x631369b1 0xe30ed23f
5286 - 0xdaa1c75b 0xe7c9c6a7 0x5f33c375 0x99c05187
5287 - 0xf2d6e6ae 0xcd2045b8 0x92ff3009 0x15082015
5288 - 0xd1a1580e 0xdce25f9b 0x21984a75 0xa9be5388
5289 - 0x099a5372 0x3ab9bcfa 0xdb9069aa 0x49a99be6
5290 - 0x42a9ee0b 0xfe32d832 0x24e11ad3 0xd16f596b
5291 - 0xb95982cc 0x754ab1c8 0x42ffa128 0x539e823d
5292 - 0x28e0f976 0x262ddfc0 0x2a16e7ad 0x49b5acd9
5293 - 0x931f3def 0xdc419b84 0x8412cc3c 0x81056cd9
5294 - 0x91933e1f 0x57710b15 0xa55d2696 0x87d88724
5295 - 0xd4fedfdc 0xcc3825c6 0x397f382f 0x80f9b6ba
5296 - 0xcdd6d59f 0x24b984d8 0x8f1c5bcf 0x25bcef1d
5297 - 0x00dc603a 0x76fd94c2 0xa267a7dc 0xa6e90a6a
5298 - 0x5c5916d6 0x065a52cf 0xa28d3263 0x9b17b72d
5299 - 0xb8436b48 0x1b1c2391 0x1fda3395 0xa6cecbcb
5300 - 0xbc4ec502 0x1766b590 0x5945fbd6 0x6a124405
5301 - 0xf92d06f2 0xe24694b7 0xf6befd08 0x8266cf5c
5302 - 0x03ed670a 0x5f98be62 0xf27b7e2e 0x598cf22c
5303 - 0x2e855591 0x879815fb 0x153799c6 0x3820faf6
5304 - 0x3d3a2cc6 0xdbb6dece 0x1a3c46b2 0x5031bdda
5305 - 0x47894c03 0xe43661fe 0x7a6ee548 0xa5ca9779
5306 - 0x6aa9e105 0xbc8505a3 0xa03b860a 0x448faeb9
5307 - 0x367de4a9 0xc9779c7d 0x6535ad8c 0x4b7fcacc
5308 - 0xb2db5c10 0x0ab41ec6 0xe528ab90 0x5e6f03da
5309 - 0x98bc76d3 0xf38df42e 0xea59b039 0x1c2eaa28
5310 - 0xca30dac5 0xdb0eb8c6 0x60063860 0x18823f8d
5311 - 0x164e2f28 0x7cbbe080 0x70a12315 0xb08f44d9
5312 - 0x5fbb9453 0x4bc62738 0x9fa15ffc 0xe4033ca1
5313 - 0xc9dfbc13 0x58245d7d 0x588113aa 0x8f5a6ac8
5314 - 0x92588a60 0x26330c74 0xb2aaf0e3 0x24ada1ea
5315 - 0xa9e973ae 0x624b73e7 0x4ef961db 0x95ede155
5316 - 0xf2bb86ff 0x96bc79d9 0x95cd646b 0x1c3af453
5317 - 0xf60fa711 0x10905115 0x0e24b740 0x169bb227
5318 - 0x34cee6f0 0x990980db 0x18d8ace5 0xd4c87504
5319 - 0x29515d32 0x2e5d9c04 0x87dffa60 0x12e815d1
5320 - 0x021db8e9 0x2c5a42fd 0x6e3a1a13 0x88889ab5
5321 - 0x3bc915a6 0x608919c5 0xd310a970 0xea8f3218
5322 - 0x949f55bc 0x9ed7aadd 0x6d990157 0x181f1c2f
5323 - 0xa940df64 0xf3be8c39 0x7ca2e699 0x7b4f07f9
5324 - 0x89e83fee 0xe66b9493 0x54fc3d17 0xa63d2d46
5325 - 0xd5e835d5 0x910e0144 0xecf67025 0x1fa6a93a
5326 - 0xe692dbca 0x466af681 0xc2bc808c 0xbb4ebd60
5327 - 0x74d5c729 0xa283ad25 0x1e66fa23 0x6d372988
5328 - 0x753c9fcb 0x1742efdb 0x5b68cf15 0x372a0e33
5329 - 0xaa3a7ebd 0xa0e944d5 0x95d5cbb4 0x4fb6020b
5330 - 0xced927b0 0xb2afea78 0xd0646b72 0x1622fad4
5331 - 0x4672c6b6 0x736ae4f8 0x8d46a4db 0x0e6a432e
5332 - 0xe0a30a98 0x4c2bcf4f 0xd87acedd 0x19682d7a
5333 - 0xf97c025c 0x55d8feb3 0xbcd4d2ff 0x236c6f9f
5334 - 0x8ba0246d 0x42812f73 0x327636f5 0xc92cd30a
5335 - 0x08a69d9d 0xc735a946 0x82eca01f 0xda0753a0
5336 - 0x7077b1d1 0x17b05834 0xfa24bc02 0xf49f4473
5337 - 0x8f9ac6b4 0xa880c630 0xf7457b4d 0xd5f829e4
5338 - 0x25c49a99 0x1176a997 0xbb2d2009 0x61d35764
5339 - 0xa322c752 0x6ef3ae02 0x5faae6f8 0x9a52acf1
5340 - 0x19176f43 0x43843b07 0x14efc471 0xee474403
5341 - 0x319c4857 0xa19adcf0 0xc0a466e1 0x02db14ad
5342 - 0xb7f211f3 0x72aa6ca6 0x0eb9bffe 0x48a6d284
5343 - 0x9a93a2ee 0xac09fc5f 0x92a62c4f 0xd34f0271
5344 - 0xffb348c7 0xf229b6e2 0xc68ec1ca 0x19577dbc
5345 - 0x069a10bf 0xf64ac347 0xf7c3c848 0x81975294
5346 - 0x6376e550 0x93b53440 0x8bb17daa 0xc4c64c07
5347 - 0xcaeff293 0xd51497b0 0x33da3565 0xa73d5def
5348 - 0x4bf4dcde 0xfb470fcd 0xca7db864 0x7ef17022
5349 - 0x47567363 0xd8fb8d74 0xa68c3c72 0x8202e4f3
5350 - 0x75bf1798 0x16a70fd2 0xcc3b697f 0xab9a1075
5351 - 0x13f56ef3 0x269d0302 0xcb655a43 0xc9a4de88
5352 - 0xfb8363de 0xff40f36d 0xd2555489 0x647a7995
5353 - 0xfd8eda6e 0xa3958c9a 0x20e029b4 0xbed3e225
5354 - 0xa7df5f17 0x63bc3c1a 0x337ecc9d 0x6c329508
5355 - 0x786aa47e 0x1db5b093 0xc0acd73b 0xf9587237
5356 - 0x243e5d40 0xd3623c3a 0x338c4740 0xb672140e
5357 - 0x43640a9b 0xb7ef3f6a 0x44151074 0x749bcc46
5358 - 0xfa1f103b 0x0fefb19e 0x58855538 0x138ad276
5359 - 0x2641fd80 0x297d99d0 0xfaa63ba2 0x00b6f11a
5360 - 0x3793fb6b 0x124763a1 0x8b9419ac 0x56abf9eb
5361 - 0xdbf83419 0x43570571 0x37299cd8 0x8b201e62
5362 - 0xa4058fa5 0xb320e91b 0xbe7d40b7 0x4eca3b2d
5363 - 0x8519c155 0xf4b17021 0x9e4c572a 0xdc1f9e16
5364 - 0x39a589a3 0xa6cfc7a8 0x5b986910 0x64e150e7
5365 - 0x60b6f2c1 0x02bacd3f 0x2f3b5a5c 0xc6f453a8
5366 - 0x15a87a7e 0x76104a14 0xafa2ef63 0x2cd48dbe
5367 - 0x3c7abddc 0xd786ea5a 0x4f65867a 0x355cda38
5368 - 0x2ae03d9e 0x4f11f6be 0xfc0a0034 0xde4ea602
5369 - 0x21ff83ea 0x0f12d913 0xedf4da28 0xc96d8fd1
5370 - 0xd7e82c3c 0xfec63bdc 0x37a456d7 0x3007e18c
5371 - 0x091a47b6 0x82f1c641 0x82219cce 0x3e7e6993
5372 - 0x7b3a2115 0x0b8e1a02 0x40f88213 0xfa2f9c21
5373 - >;
5374 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/m12306a9_00000017.dtsi u-boot/arch/x86/dts/m12306a9_00000017.dtsi
5375 --- u-boot-2015.01-rc3/arch/x86/dts/m12306a9_00000017.dtsi 2014-12-08 22:35:08.000000000 +0100
5376 +++ u-boot/arch/x86/dts/m12306a9_00000017.dtsi 1970-01-01 01:00:00.000000000 +0100
5377 @@ -1,750 +0,0 @@
5378 -/*
5379 - * Copyright (c) <1995-2013>, Intel Corporation.
5380 - * All rights reserved.
5381 - *
5382 - * Redistribution. Redistribution and use in binary form, without modification, are
5383 - * permitted provided that the following conditions are met:
5384 - * .Redistributions must reproduce the above copyright notice and the following
5385 - * disclaimer in the documentation and/or other materials provided with the
5386 - * distribution.
5387 - * Neither the name of Intel Corporation nor the names of its suppliers may be used
5388 - * to endorse or promote products derived from this software without specific prior
5389 - * written permission.
5390 - * .No reverse engineering, decompilation, or disassembly of this software is
5391 - * permitted.
5392 - * ."Binary form" includes any format commonly used for electronic conveyance
5393 - * which is a reversible, bit-exact translation of binary representation to ASCII or
5394 - * ISO text, for example, "uuencode."
5395 - *
5396 - * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
5397 - * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
5398 - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
5399 - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
5400 - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
5401 - * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
5402 - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5403 - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
5404 - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
5405 - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
5406 - * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
5407 - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
5408 - * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5409 - *
5410 - *---
5411 - * This is a device tree fragment. Use #include to add these properties to a
5412 - * node.
5413 - */
5414 -
5415 -compatible = "intel,microcode";
5416 -intel,header-version = <1>;
5417 -intel,update-revision = <0x17>;
5418 -intel,date-code = <0x01092013>;
5419 -intel,processor-signature = <0x000306a9>;
5420 -intel,checksum = <0x3546450b>;
5421 -intel,loader-revision = <1>;
5422 -intel,processor-flags = <0x12>;
5423 -
5424 -/* The 48-byte public header is omitted. */
5425 -data = <
5426 - 0x00000000 0x000000a1 0x00020001 0x00000017
5427 - 0x00000000 0x00000000 0x20130107 0x00000a61
5428 - 0x00000001 0x000306a9 0x00000000 0x00000000
5429 - 0x00000000 0x00000000 0x00000000 0x00000000
5430 - 0x00000000 0x00000000 0x00000000 0x00000000
5431 - 0x00000000 0x00000000 0x00000000 0x00000000
5432 - 0x86c5b0d4 0xf6978804 0x7f4f5870 0x6319dc3c
5433 - 0xbb3b7d61 0x33cf9075 0xe8424658 0xf611a357
5434 - 0x5a3401db 0x42caecce 0xb4d8e75e 0xe6dbaf24
5435 - 0x7861b35f 0x6bd717bc 0x23b9b731 0x82ec1ac8
5436 - 0x20337b64 0x5396dbf1 0x59973bff 0x724bc7e9
5437 - 0x5237193b 0x0b8647c1 0x6a0d0e16 0xbf9ddb5b
5438 - 0xace2cc1c 0xad707638 0x056f102f 0xa37e60f8
5439 - 0x76255642 0xfb86e030 0xb8069a40 0x367795f1
5440 - 0x653fb05e 0xab7f14ad 0xb6e8a8e1 0xd2598d20
5441 - 0x2eba3f68 0x78b372f1 0xba8d13f8 0x1f1de861
5442 - 0x97f951d5 0x8097c728 0x27dbf904 0xb97906a8
5443 - 0xffe7a4ac 0x4b947668 0xc1dbd726 0x2adcf777
5444 - 0x63b1bcf0 0x818e2a1b 0x49aa907b 0x2faf5e8d
5445 - 0xae842352 0x82707fae 0x0aa12b41 0xa0bae11c
5446 - 0xb4298c47 0xd2b4099c 0x4ff625f2 0xcd2630d4
5447 - 0x79850981 0x05dbf57d 0xb05b81a5 0x56e73ec7
5448 - 0x95cb3897 0xe262bda5 0xb2c6e288 0xcb7f8e77
5449 - 0x72b8bdd3 0x3f400494 0x63ade65b 0xbc4adc71
5450 - 0x00000011 0x06c0f8ff 0x0eb63d77 0xc54cdabf
5451 - 0x76bc8860 0xdd142643 0xe7bfc220 0x17aa0a91
5452 - 0x4fd676ba 0x4b6b1a15 0x2a1a1c16 0x4fed6de0
5453 - 0x8c3d6bcf 0xbb319bf6 0xa82532f1 0x7c8ce014
5454 - 0xb830a38b 0xec25bc6b 0x61c8a8a9 0x49a21dba
5455 - 0xfcf8bad0 0x7372f29c 0x1f7fbcdd 0xc2ff42f4
5456 - 0x780878f0 0xc967068e 0xe19cc3c9 0x155e6646
5457 - 0x75235c43 0x9aaf3741 0x9dfd116d 0x0f031b6a
5458 - 0x4963e039 0x6918daa8 0x7f0ca4ab 0xd77dad79
5459 - 0x2f8847e8 0xf79c82a4 0x6a6aaad4 0x24f07dbc
5460 - 0x895d3f6a 0xc96b2eb0 0xff50228f 0x573d364a
5461 - 0x5fca9d56 0x3c11c35b 0x3e90fb12 0xc4604067
5462 - 0x5c980234 0x7c42e0c7 0x60cca3de 0x637a4644
5463 - 0xedc43956 0xb0efb4e1 0xe94716fa 0xa6478f51
5464 - 0x33965654 0xdf6b40a3 0x48ac1b18 0xd6723c94
5465 - 0xf040d6d1 0xaf850470 0xe2bcde48 0xb90a4998
5466 - 0x8f620105 0x3d592878 0x2f697bad 0x9f7721d9
5467 - 0xec34444a 0xb0594770 0xd7180f9f 0xa510a168
5468 - 0x460563b0 0x5d4f34f4 0x21dfc16b 0x051de344
5469 - 0xa57bc344 0xff2c7863 0xf0bc063d 0xf5a89004
5470 - 0x79a81dab 0x9e8cb974 0x2309b0a4 0xa47a46de
5471 - 0xcf9c0c44 0xf761c817 0x67ab642c 0x0db4422f
5472 - 0xca3616fc 0x79e66c8a 0xd56a3332 0x5e0f338b
5473 - 0x5814cb3a 0xed1b9a4d 0x47d59f72 0x25b03786
5474 - 0x3edd1d42 0x8cd947cd 0x706e6ebd 0x82c2bada
5475 - 0x1bf6a96b 0x77dd859a 0xda35335f 0x22fab458
5476 - 0xd0661fd8 0x02bb4a42 0xe2a2bcdb 0x0616580e
5477 - 0xd35be23f 0xc206d16c 0x401218be 0x51107c3d
5478 - 0xba84b8be 0xace4d8f2 0x505b9b28 0xc517034b
5479 - 0xac5ba582 0x7419fe54 0x43493cb1 0x2fe0a66e
5480 - 0x206039b5 0x07569011 0x230ce53d 0x168d427f
5481 - 0xbfe0bd10 0x82bf11be 0x5b55475b 0x5490a0e9
5482 - 0x1c3c1e3c 0xacad77de 0x1666512f 0xfc3250d8
5483 - 0x930a6312 0xdd85c066 0x1b95c18f 0xc8bbd3b0
5484 - 0x1bb2a34e 0x642c7653 0x0f536213 0x1f7ab4eb
5485 - 0xaa5ef677 0xe6ac9581 0xd7a2fe73 0xd417dc79
5486 - 0x455a6877 0xae825a40 0xe0c98bec 0xac39ba49
5487 - 0x299d9bd9 0x957d0bb0 0x1645111b 0xe9da4beb
5488 - 0x1b005ce7 0xddb742ce 0x6c5f3ffc 0x24f74d2c
5489 - 0xf4ace044 0xb21bc7ba 0x338002dc 0x240effa1
5490 - 0xd208ae00 0xfe8c2b5c 0x9a457293 0xd9365ac4
5491 - 0x98f24244 0xf6d1aaea 0x7b874350 0x1ba4086b
5492 - 0x1d3bf168 0x2bb6f4fa 0xb27f8477 0x8da836f6
5493 - 0xa8762693 0xc377fa64 0x74cfd979 0x90435c25
5494 - 0x29d80e17 0xc3503c9c 0xaacd2178 0x232c748d
5495 - 0x6fecd3ba 0x00fb4aa0 0xbac3ee19 0x6e5c63e3
5496 - 0x17823c14 0x0e9d33bc 0x0fa9de06 0x998b14b2
5497 - 0xfdd8c80d 0x01b0591b 0xf70bc4ce 0xb278c496
5498 - 0xa7e30708 0x69cf8420 0x14f8b744 0x8bb8a0ff
5499 - 0x168f6db0 0x95da6db2 0xf96d121d 0x67fd06f7
5500 - 0xcd81d278 0x8693d095 0x15e1a24c 0xe5f554f2
5501 - 0x499874e8 0x30fc0785 0x0f4fa1b9 0x65c93dad
5502 - 0xd939bf24 0xdad29721 0xf253b752 0xf6ff59da
5503 - 0xc5dfaffc 0xf0071f34 0xdb0db8b0 0x24475e2d
5504 - 0x2a4d5b8a 0xf7624bea 0x3fdcbc90 0xb5a66e35
5505 - 0xd0f08636 0x24643caa 0xc5d08e83 0xb134c55c
5506 - 0x8e3653c7 0x34496b0c 0x6b2aeebc 0x2fbab601
5507 - 0x105613a2 0x7babd55d 0xa01af846 0x248be690
5508 - 0xed27917c 0x26ee6e13 0xa1dac5fe 0x852ed91a
5509 - 0xfc83fcca 0xdf479c33 0xfd6efe96 0xdc62521b
5510 - 0xa37d2a8c 0x1d2bad9e 0x4287614f 0xc4f7b62c
5511 - 0x2aab0562 0xec6d4226 0x52853fb4 0x264e3507
5512 - 0x1c3af366 0x33269776 0x81b8529d 0x115530dc
5513 - 0xe035f98f 0x433d1b6c 0x1ea6daea 0xecfd2ad2
5514 - 0xa57a0c22 0x1dbe3e12 0x6fafe41b 0x8e579e35
5515 - 0x6c493fbb 0x034dd4f9 0xd17cd6f2 0x05c5cfa8
5516 - 0xd9bffa39 0x0fc16e9c 0x831b88c8 0x7e7dce3e
5517 - 0x3320bc7f 0xd5abafaa 0x217ab526 0xade2597d
5518 - 0xf01b00f2 0xc9e34b72 0x00a4cb0b 0xdc198512
5519 - 0xdc7cc8a1 0x89db07b5 0x6c2153ea 0xb8bdb8aa
5520 - 0xdf8a1ae8 0xa517f6b1 0xd32569d9 0x37e79008
5521 - 0x3c7527c3 0x7d5b2d3b 0xb31cb907 0x35db7f6c
5522 - 0x0ab0cd65 0x75feaded 0x7c8260a9 0x5bc04f56
5523 - 0x2fac9f60 0xd7b3a2c0 0x2b393634 0xc2df7f43
5524 - 0x1ff2fa9f 0xc81af169 0x188b1f4e 0x08bf6f86
5525 - 0x5ab2f188 0x0a71eb64 0x03b57501 0xa684fc23
5526 - 0xa729ffef 0xe3b4a709 0xf9eb97d2 0x01506c95
5527 - 0x0d9285f5 0x8e1ee93c 0x7d15a0d8 0xd9390673
5528 - 0xf116ebd8 0x7e68798b 0x3dc8412e 0x5a9a04b4
5529 - 0xe3805f51 0x00493bb1 0x4ec65ca2 0x2aedd69a
5530 - 0x7f2a5b18 0x9994ac32 0x476f3703 0x7d3da882
5531 - 0x5635f55f 0x7a0887e0 0x0af46feb 0xfc2f3591
5532 - 0x02e29400 0x70fd3234 0xc549379e 0xaf34fa5a
5533 - 0x5bf7c649 0xeb183cff 0xa236d508 0x4525ab64
5534 - 0xc4301026 0xf281df99 0x0b298e46 0x9b7c1a99
5535 - 0xc4b24e77 0xea536992 0x5a39e37c 0x570fb6df
5536 - 0xae5d5c49 0x01142cc2 0xda05d3f1 0x337bf65c
5537 - 0x3c986598 0xbecefd30 0xb5e34c2a 0xe7c3847f
5538 - 0x18cb24b4 0x71278c26 0x4b8d6caa 0xaf7c300e
5539 - 0xfb6ce9b8 0x94c4b785 0x67275f17 0x59498cf5
5540 - 0xca8eeec6 0x3374e7a6 0x649affac 0x9049ba78
5541 - 0xff9d3908 0xaceec446 0x225ece3a 0xac1d4fec
5542 - 0xdc050fed 0x04e3ed8a 0xb303d8e9 0xe9d26aff
5543 - 0x0a98691d 0xf243492d 0xe3b42f00 0x6c21a97b
5544 - 0xa385ae98 0x14ba3f4d 0xc0215cc1 0xe1ba6c0d
5545 - 0x412bbbe4 0x39f95d1c 0x593bd878 0x45d3066a
5546 - 0x9fcee8a1 0x3f29b2fa 0xc9ae58ee 0xed6def92
5547 - 0x6c8f2182 0xdba64e20 0x276c2c21 0x81ea9dfe
5548 - 0x20ae00b2 0x8c2d2724 0x66c09f5c 0x24908e2e
5549 - 0xfecf8194 0x6be61e94 0xcdf5d7db 0x98b829a3
5550 - 0x4241ab07 0x1207ef2f 0x96e7b073 0x766293ea
5551 - 0x58eb0882 0xf12a6426 0x741b074b 0xbd4302cb
5552 - 0x909b6c4f 0x1c4949cc 0xd4d6a3e9 0x442b74b3
5553 - 0xbc8cb3f9 0x0efad89a 0xa2ceff3d 0xecdf86bb
5554 - 0x46a4a72e 0xe9d8abe4 0x94c91479 0xe99a80b9
5555 - 0x1072b708 0xb8318ad3 0x0685426f 0x3e89a0d8
5556 - 0x0b7c438e 0xb4b577d0 0x046599e2 0xd0ef85f2
5557 - 0x3566d2d2 0x43ade22b 0x8753a78a 0x8f6d8e02
5558 - 0xbdf33e56 0x8b2b6696 0x22a5e911 0xd0e0f4eb
5559 - 0x42729c29 0x425921fb 0x82f7634e 0x2c145fd5
5560 - 0xff59deeb 0x018a5372 0x33c4e11a 0xc001c097
5561 - 0xf250cfcf 0x2f682912 0x21f40dc0 0x883196aa
5562 - 0xcd5c58d0 0x7c329754 0x481c450e 0x9411c6c0
5563 - 0x69a9df82 0xacb01a1a 0xc0b569a7 0x0b7fd1a9
5564 - 0x4c339ad3 0xb0d9e211 0x07098664 0x14a5cff9
5565 - 0x53beae37 0x4e173257 0x4e1d2e6c 0xce981dd1
5566 - 0x45d6204f 0x3c193268 0x4f51ac3c 0x5ecffa12
5567 - 0x48068ee9 0xde12270f 0x0a0aa980 0xd6fe8ca2
5568 - 0x97d51da8 0xccf2db36 0xb3ad0598 0xbc56eb56
5569 - 0x0adf5e5e 0x9e320aa1 0x8ebb75ef 0x3973a323
5570 - 0x7e3d87e0 0x2c0d1858 0x83b7fa0c 0x36effdb5
5571 - 0xcd9eba1a 0xab5b5790 0xa48fbf00 0x536e2ae9
5572 - 0x2f2a3f61 0x05706a73 0xd2dfed08 0x7e4626b1
5573 - 0x172c6ced 0xbf2e44ba 0x15aefc2e 0x9cf56c37
5574 - 0x663c6695 0x04cece5f 0x4ce00027 0x465b1cd4
5575 - 0x333dc2c7 0xce41f1f1 0x6dd8503b 0x52b79af7
5576 - 0x564c81de 0x0e5e2daf 0x869753f5 0x16667889
5577 - 0xe1acaf08 0x38ffbb0b 0x83400589 0x5144052f
5578 - 0xa3819950 0xd21501c5 0x1bdadeda 0x0a874e2b
5579 - 0x05480284 0xe8f76f11 0x582cad8a 0x0553f942
5580 - 0xb6451cb9 0x76bdc86f 0x96ffe0c7 0xc630eba2
5581 - 0xa82ec683 0x5902ef45 0xc362248c 0x18c412a9
5582 - 0x1d09c103 0x2355ed98 0x5ec5c718 0x5037e359
5583 - 0x1508f804 0x09cfea9d 0xa16cbdfa 0x5f962b17
5584 - 0x85a35a27 0xa048dd30 0x6fe7ba90 0x0dc20150
5585 - 0xcb56daa0 0x4188fb20 0xb4182598 0xa1bc5dd7
5586 - 0x8c11e0bf 0x2104df35 0x025e74b8 0x79d177df
5587 - 0xad74bb77 0x4b2419aa 0xe374add2 0x411593d5
5588 - 0x796778da 0x9e43a420 0x4a2e0860 0xefb48578
5589 - 0x47cafbdb 0xea15924d 0x70ac1467 0xf52fd888
5590 - 0xd2df4bd6 0xc1fc63bb 0x119ab88e 0x0e147ead
5591 - 0xa85bd8b5 0xc2e61ddb 0xd566417d 0x6bb9f9ec
5592 - 0x69bbcf1e 0x24d46989 0x3caf067f 0x58151211
5593 - 0xc2a6b6e5 0xb233416f 0x3da28155 0xf9cd9385
5594 - 0x7a530045 0x1eab05ce 0xb86ed141 0xa8f13a5b
5595 - 0xf9819f81 0x66d5d5c5 0x148c1a02 0x496d3c56
5596 - 0x370dcd45 0x5f13f0b6 0xdd4eaeed 0x8dbad50d
5597 - 0x0747ce54 0x69d2adcc 0xfb69c18f 0xd44ea186
5598 - 0x74ab7537 0x0c642449 0x88b096cf 0x3a8ad683
5599 - 0x408cd7aa 0x6daa6708 0xb267b312 0xa4225c7a
5600 - 0x7a56dce7 0x6a8d497d 0x8837bcbb 0x6125397c
5601 - 0xeb51d233 0x362bdde9 0x689657f7 0x32d09e1f
5602 - 0x753a3d39 0xf77db5b2 0x8057908a 0xef12815d
5603 - 0x594fffe6 0xcf3402c5 0x1a0d4923 0xca547b2f
5604 - 0xaf9d604d 0x5d2e30f3 0xffe18005 0xe29bb0d9
5605 - 0x36fc10f9 0x3720aac6 0x37bc1ad3 0x47d000ae
5606 - 0xa4b0da0a 0xa178228b 0xdd9374e6 0xa1f3df5f
5607 - 0x9ae2e451 0x21c4aceb 0x8f9fb226 0x5190b712
5608 - 0x70253633 0x9c9cb5f1 0xc9178689 0x551c1a2d
5609 - 0x6db67cc0 0xcf1b1ade 0x48449272 0xd18634f1
5610 - 0x9d9c3de7 0x19025530 0x121d78d4 0xae4a39e1
5611 - 0x62850819 0xf3d4af6a 0xe5ad5b80 0xfa053c7d
5612 - 0x7ed68b9a 0xdbde2894 0x4b5c04de 0x65178203
5613 - 0x9181cdd8 0xb17e27b9 0x0e29b338 0x50156ab4
5614 - 0xf7726438 0x178108d6 0x1d8dc6b7 0xc3e7512f
5615 - 0x0eb8339c 0xe2684a6f 0x7668ed31 0xd0ed6eda
5616 - 0x4342a534 0x03840286 0xad1e6969 0xa9a6c98d
5617 - 0x1bf77774 0xd32fc9d8 0x405620d2 0x8ab19efc
5618 - 0xce4d7506 0x6f4eaae4 0x3e830dbd 0x76818782
5619 - 0xfde4ee8d 0x1953cd0f 0xd47be276 0xf2480bc0
5620 - 0xd1010013 0x2dd56a58 0x083084f4 0xc91b0ad6
5621 - 0xc2524e12 0xa60710f2 0x3d955047 0xce380846
5622 - 0x0f6dec2b 0x604d1492 0x5ca43ee1 0x6b51a626
5623 - 0x350d5483 0x8d99ae30 0xcba06491 0xcc0185eb
5624 - 0x7b64caa6 0x2f1754db 0xca0691f1 0x6219efb6
5625 - 0x43291db0 0x259d3f12 0xeaf6ef9f 0x5f0e065b
5626 - 0xad576541 0x8615a414 0x81124bdf 0x62b855a9
5627 - 0xabdc529f 0x01bfdf75 0x10e4c656 0xf8e86f78
5628 - 0x1fbe10d1 0xa6873c2c 0xdf83dcd8 0x20d35872
5629 - 0xf46f2861 0x22f3d642 0xfdcda29a 0x16adbdb4
5630 - 0x01e5844c 0x011e5454 0xf5432b04 0xd5f6a80d
5631 - 0xb081fab6 0x64fc2fbd 0x4ca76e0f 0x3a8d8b29
5632 - 0x3f03ec12 0x58e2bf6c 0x24f2b8b1 0x108e414f
5633 - 0xe76a02ab 0xcb525af9 0x623ba7a3 0x31412c27
5634 - 0x69c2f5db 0xd5546d8b 0x8200d2c9 0xf1e34a71
5635 - 0x393e24dd 0x2b867933 0x0596e778 0xc5112b49
5636 - 0xf433cdea 0xbc505e7b 0xf64bb064 0x1e892633
5637 - 0xbf17307b 0x9118de2c 0x6b1d61a8 0x1945519c
5638 - 0x32638ca4 0x5e436733 0x3dc20ff6 0x9babf127
5639 - 0x485c1555 0x0d0c4e2d 0xc4d5d718 0x8cfffc16
5640 - 0xf64050db 0xaa4ef416 0x8d398a00 0xe4a16eca
5641 - 0x5d9d9314 0xefa2bf1c 0x05917dd4 0xca5f1660
5642 - 0x59642534 0x02639b9f 0x12b895df 0xb2deaf0e
5643 - 0x20d8f0b9 0x04d8342c 0xa1ba5f57 0xa26cdb06
5644 - 0xca732ca8 0xdce0c561 0xf5e4b205 0xc05f5cfb
5645 - 0xba4a41a6 0xaf219d7b 0xce08df01 0xa02bbdb9
5646 - 0xc1adbc20 0xcb9ae4fd 0xd828cfb5 0x690b17db
5647 - 0xd29ae8bc 0x8fc71289 0xd6fc9cf6 0x61c7a6fc
5648 - 0x8e8012d5 0xd3320498 0x36e80084 0x0036d3ab
5649 - 0x53141aae 0x987d0cba 0x57581df5 0xace4704c
5650 - 0x3ce49642 0x991556c1 0x6cb0b984 0xac15e528
5651 - 0xe7d208ca 0x2486d1c5 0x93b6623e 0x340b7622
5652 - 0xe7e1cf7b 0x3cdeed88 0xa23c849a 0xcc6e8b3b
5653 - 0x292add5a 0x17763ee1 0x9f87203e 0x72cf4551
5654 - 0x2053e66f 0x06c3a411 0xb61c2e0c 0xa4a7f3ae
5655 - 0x0ff87dbb 0x03999ed8 0x48aacedc 0x2e126ef3
5656 - 0x799441bb 0xaee15b4d 0xea08bf54 0x47248787
5657 - 0xb60afc11 0x8c3d6a20 0x7c04f801 0xb902760e
5658 - 0x319040eb 0x370bbd5d 0x9a1dd5e6 0x63f7da1d
5659 - 0xb3784eac 0x3b304dea 0x987ada9f 0x2b6b1cda
5660 - 0xf9241003 0x0d3d16f2 0x1185dcbf 0x519b7a5f
5661 - 0xeb612361 0x28b57da5 0xdeb8419a 0x0ba13122
5662 - 0x062e28fa 0x5ffb9b36 0xb1258247 0x8337401f
5663 - 0xed1f6423 0x730cafe6 0xf728c690 0xe40557eb
5664 - 0xc4951a15 0x04a988a9 0xbf5fe18c 0x2766e40a
5665 - 0xe4d74d13 0x8638d052 0x8eefeaf2 0x9ad07978
5666 - 0x32042a87 0x4385f38d 0xc9b48f02 0x02ab0ae7
5667 - 0x9eaeb632 0xf386c14d 0x8b1c2ab2 0xad432a24
5668 - 0xfc5bd462 0x2d7ac5fe 0x45dff5c6 0xa235e1a6
5669 - 0x825b770c 0x5568471b 0xa7ac3a3a 0xfcc6e40c
5670 - 0x0c1be59c 0x77685a3c 0x5b1bafbd 0x40b8a139
5671 - 0x3dd1bf01 0xb6651001 0xf2915a6a 0x16fe1cf2
5672 - 0xe78467d1 0x4bec9fb1 0x88615320 0xa3920831
5673 - 0xed4afac7 0x206cffba 0x96c42567 0xcc2b5215
5674 - 0x7ca0193f 0x0e1a60e5 0xf3892c10 0x2ceee7b2
5675 - 0x110d3311 0x9a322e7e 0x3cb7e5fc 0x3fb971c1
5676 - 0x59971332 0x08386001 0xe4a2444d 0x17d9c47f
5677 - 0x9f53c4a5 0xdb54e5c2 0xfaac9f08 0x975c07c6
5678 - 0x8a6e6bcd 0x4392053a 0x6473bef8 0x4b3b91a3
5679 - 0xfb7e8ebc 0x46c6ffed 0x04939839 0x71b93766
5680 - 0x47e4f74a 0x786545c8 0x77f55b59 0xdf8e992d
5681 - 0x60a0d2a5 0x6cc8a5cb 0x113ee95c 0xa378558d
5682 - 0x5d3b8bd9 0x3c95b2a8 0x6efa3682 0x9535dd34
5683 - 0x3e29974d 0xa477d069 0x2dbf58d2 0x165edae3
5684 - 0xea25d53d 0x44e3ef71 0xba6341cf 0xc61b964c
5685 - 0x4612838b 0x62151b9e 0xc1de2511 0xa364130c
5686 - 0xa9710643 0x1a436c70 0x97030b09 0x5cef28e0
5687 - 0xd5197e49 0x02b9ffa8 0x1b52dc7b 0x04f9428b
5688 - 0x01ebed2a 0x1eaecbee 0xc53c4d54 0x3e34c125
5689 - 0x05b4f37a 0x6e3d042b 0xf1c1f40d 0x39cfe9e1
5690 - 0xd2938e89 0xa14b9846 0xb1333676 0x31068254
5691 - 0x4b627e4b 0xb5185882 0x101b52bc 0x73e05abf
5692 - 0x68a4e24c 0x67e301f4 0x6bf8b538 0xc502e1e1
5693 - 0xc3889b5b 0xdfbc6d96 0x4239d0e1 0xbf3667ab
5694 - 0xb0c4cb00 0x3efdcffd 0x7cd9661d 0x4f5eca03
5695 - 0x0ef218dd 0x464f0826 0x048fc539 0x6a1c63fe
5696 - 0x76cc341a 0x1ae2945c 0x7a339006 0x858fdc20
5697 - 0x2a4a7270 0xd4cbe12c 0x7b27e5d8 0x998cf520
5698 - 0x4795ccf7 0x52e15388 0x86aa7b96 0xff1845fa
5699 - 0xd49d1061 0x035b6a80 0x1df18220 0x28fc4fd1
5700 - 0xa8e8f333 0x3a9240a6 0x41a4caca 0xee736b6f
5701 - 0xdfa7ce4b 0xd4bf5c0c 0x4e62f6d3 0xe98ae9b4
5702 - 0x7f544550 0x2b0706df 0x8fb2e752 0x546af9d1
5703 - 0x8517758f 0x53f522fc 0x03bd1819 0x6fd264e2
5704 - 0x16839ef8 0x44a1200d 0xcd5a586b 0x1ead251c
5705 - 0xf58dd3be 0x80217ce7 0x0367ff42 0x2d8f2ce8
5706 - 0xe8a0a689 0xba33e366 0x5dc7980d 0x005c0eaf
5707 - 0xc0c44118 0x5553076a 0xdaf39389 0x703e09eb
5708 - 0xc54c8112 0x4a26135c 0x36a46f2b 0xdc93ee12
5709 - 0x7060db72 0x7778befc 0xe028fc55 0x52e86278
5710 - 0xd0b00188 0x6ed5565a 0xb5e2785c 0x3608bffa
5711 - 0x55c3f5a3 0xe1e41afa 0x08a227fe 0x94c793ce
5712 - 0x650934f7 0xddc36524 0x6dac40de 0x9eec3ceb
5713 - 0x8fe3d1cc 0x3cebab86 0x61e4d63a 0x5382ea11
5714 - 0xa90c9495 0x0277ccb3 0x412cecc1 0x5853c945
5715 - 0x97df9a48 0x364d9b10 0x7e8c9bf1 0x6b4974ef
5716 - 0xd3dbaeeb 0x6626dd26 0x2b746d2c 0xfb762155
5717 - 0xf942f687 0x1317d1b5 0x0c989def 0x5f4c0ed6
5718 - 0x31aebbd3 0x51cd8d5b 0x3d729511 0xc07c8f23
5719 - 0xa7f3e6f7 0x7683dba9 0x5f051d5c 0x750437f5
5720 - 0x1b9ffe98 0xa4de609b 0x4c498e9a 0x18dfc535
5721 - 0x376c6c34 0x19a57039 0xa70e93eb 0x7e966bc7
5722 - 0xb6e9d77a 0x3ab98e5f 0x1607125e 0xe8845aa3
5723 - 0xa20a2d80 0xb17ac63b 0xa07a9790 0x71e5a14f
5724 - 0xb6b5fc78 0x4c610f86 0xb57b21b6 0x1bcfb3ac
5725 - 0xbf812998 0xd429986b 0x02b837e9 0x0823aca8
5726 - 0xd8a85194 0x708bad39 0xff94ef19 0xc3599461
5727 - 0xaee622f6 0xa8b5a808 0xf801b298 0x0aeb35b7
5728 - 0x4db4bf27 0xfa31c205 0xa047dc66 0x7e0ae406
5729 - 0x2ceea6cb 0xef0ef96f 0x4cc4fdba 0x6161256f
5730 - 0x94505fd1 0xbced5596 0xbf9e36a5 0x271e68bd
5731 - 0x7a3308b6 0xef1af50d 0xb55ede06 0x6783e602
5732 - 0x1152acf0 0xdc644ccd 0x1b692da3 0x59f6886b
5733 - 0xd7236158 0xe39d75a6 0xe7026697 0x25496283
5734 - 0xb6b0a61c 0x09d0931c 0xe8d459a1 0x1a124097
5735 - 0x88e50621 0xf2ed18ff 0x37681783 0x4afa1ffc
5736 - 0x8a96ec4a 0x4474a860 0x274591b1 0x59df3968
5737 - 0x34f56fb9 0xce821f96 0x7ec825b2 0x6ed4a9bf
5738 - 0x687253cf 0xa511c1d3 0xaf2bd6f0 0xd1ce1a5c
5739 - 0x241dd505 0x39037238 0x0c761934 0x53181db5
5740 - 0x11ad47ec 0x915a527b 0x748bc970 0xeb8f2669
5741 - 0xb8bfd5af 0xd8d19145 0x0361ff58 0x6dc6e2f2
5742 - 0x1fd06556 0x120db4c5 0xbd704c8b 0x70a1a57c
5743 - 0x27543851 0x095403a6 0x28171887 0x640e7c92
5744 - 0xb48fd7d1 0x62ad2774 0x224767cd 0x347b8843
5745 - 0x821ca7f3 0xf94749c6 0x2bc7f40f 0x700cc1d8
5746 - 0x50d50832 0xc2f9465c 0xa6e1cbaa 0xe0f5e934
5747 - 0x7f33617f 0x8876cb07 0x408c24fe 0xc0cfcdf7
5748 - 0x39152b72 0xa0ba80ab 0x301a73eb 0x6e704f6c
5749 - 0x3b73c24b 0xd433f861 0x43192007 0xa56d2ca4
5750 - 0x2d28bd5d 0x14f4c9cd 0xb7fe189c 0x031e1818
5751 - 0xf8f4133e 0xdc8e7727 0x4f8f5a06 0xe7b114cd
5752 - 0x5cb9ff12 0xdb4c5a53 0xed956df5 0xf3634f5f
5753 - 0x6cce1cc2 0x5393f9ac 0x1184c2f7 0x0b6fd240
5754 - 0x64771374 0xaafed1a1 0xbdc55bcf 0x976414ef
5755 - 0x6a333e56 0x0c5cefb2 0xff2574e0 0x11b059ef
5756 - 0xff8b7f2a 0x9651e97b 0x594fe89b 0x7be60f6a
5757 - 0x7b7695ac 0x612036f7 0x5be0d4fa 0x25855737
5758 - 0x12e32ee2 0x8e86130f 0x46d75d41 0x3769d438
5759 - 0xd14752d4 0x1612ad6d 0x8f86f2a0 0x63e01251
5760 - 0x9a44ac4a 0x49fdb148 0xe1757062 0x42798804
5761 - 0xf21f46c1 0xed0a3794 0x5528add4 0xeddc0c90
5762 - 0x7f188ce8 0x59568b7a 0x8e25d50f 0x9277c492
5763 - 0x955c6e6a 0x79f94a59 0x3a65fb08 0xceb23267
5764 - 0x7d8dce01 0xd15c492d 0xa35f005c 0x0e7cba9a
5765 - 0x950485d9 0x2d92e448 0x4aced016 0x0d10136d
5766 - 0x3d2ec365 0xd982e881 0xe81940d2 0xb1a84849
5767 - 0xdb30d967 0x9f51d3d4 0x4fbe18a9 0xef21cd28
5768 - 0x5d3cba6c 0xaa89b02b 0xbe1e9526 0xa20a918e
5769 - 0x0c26bd72 0x8372eff8 0xcf7ab414 0x1d3ab83f
5770 - 0xfd2c8f79 0x4929f77e 0x2416e8df 0x65dcaaca
5771 - 0x58fbf7b3 0x1c4a3089 0x9bfb6e26 0xc7338ac9
5772 - 0x88e5ad26 0xc62bb3d4 0xad6d36f5 0x6445167d
5773 - 0xe9de8daf 0xc391c6bc 0xa78b4558 0x0216bcdd
5774 - 0xbd4365b9 0xb0a874b2 0xe95e9453 0x77296b9a
5775 - 0x49803c1e 0xc01fd0ed 0x165a9d5d 0xf7da6442
5776 - 0x4c00818d 0xaad5bfca 0xdb252937 0x0e4e0f74
5777 - 0x0c2738e8 0xd075b8ba 0xe3b2df11 0x8aee60a4
5778 - 0x36052cd8 0xb4aa190b 0x413e7155 0x3e7e646d
5779 - 0x807e6eea 0x97993e6f 0xa5129ff5 0x98e01bca
5780 - 0xa8bd70c9 0x8800721e 0xb3407ffa 0x266b2f99
5781 - 0xd9da73ee 0xa06f634a 0xcaae53b1 0xd98e53c6
5782 - 0x49368291 0xc89485fe 0x938a8a29 0xb57f77cc
5783 - 0x58c867de 0xcdac8a84 0xf4d57b6f 0xc6daf080
5784 - 0xe3d9c67f 0x0264b194 0xc3b2ca50 0x6d214667
5785 - 0x88503872 0x549ed8cf 0xe827689f 0xcbe94e2e
5786 - 0x4a02516d 0x24ddcfa1 0x3cbc736e 0x34c88707
5787 - 0x9f4c9376 0x4ced4d41 0xfdbabfb5 0xafd291d9
5788 - 0x2fa602a3 0x53e19d9c 0x44422427 0xf85e2c53
5789 - 0x40e91ef7 0x02646045 0x3d1fa703 0x1613b99f
5790 - 0xa108de10 0xf9cb3d04 0x7b9f9523 0x007d74b1
5791 - 0x961771dc 0x2e49fe1b 0x5fefe27d 0x54737b43
5792 - 0xa11d7c40 0x7f0cc2d9 0x67c6533e 0xd1ab10fa
5793 - 0xb1950645 0x536087d2 0xd6937b40 0xc35960c1
5794 - 0x2df0c356 0xecb5ab53 0x61e08998 0x1671bdd0
5795 - 0xd72935b5 0xdf1a9d7c 0x70b1aa4e 0xa9272818
5796 - 0x1f7b8d55 0xc7292a0f 0xda7af847 0x190076ad
5797 - 0x58370ba6 0x3020fb4e 0xff8a4b30 0x13818958
5798 - 0x6ba1ca38 0x6a90d39b 0x5e180929 0x206e8a22
5799 - 0x0568f241 0x5f83ad21 0xef05e5c6 0x21d0521c
5800 - 0xe7886eff 0x68eebbce 0x550c1659 0xa0843444
5801 - 0x19468c2b 0x539cb9b8 0xa4b18b62 0xdab0680e
5802 - 0x1b254dbc 0x47068aaf 0xa8193743 0x44b60b88
5803 - 0x90c07337 0x2e55666a 0x632f4b23 0x68af10db
5804 - 0x8e29f54b 0x5f436bcd 0x8bf81d55 0xb640ccc5
5805 - 0x2e4ab6a9 0x198697a5 0x8a1c8481 0x572fb679
5806 - 0x7597c416 0x608fd45e 0x57c8c7f4 0xe151d349
5807 - 0xed9e17bb 0xa66f2816 0x8175fe68 0xd57d91ad
5808 - 0x79df0711 0x7a349868 0x13403cd4 0x7d974c60
5809 - 0x8860ce70 0x2e6d62ea 0x8916e2f2 0x0e336838
5810 - 0xf54d382d 0xc4e172c8 0x94bfcfbf 0x5fa53172
5811 - 0x2933cecd 0x4d5b8439 0x0ca0e6e4 0x8ef87b00
5812 - 0x2fdd121c 0x24beae76 0xa85b47f4 0x4e38af2e
5813 - 0x12b8734a 0xf698abf4 0xde2c2d93 0xeb100795
5814 - 0x8ab19df8 0x93a6f4d1 0x43c4b2cb 0xbaff7c4a
5815 - 0xf52b1471 0x72804f4f 0x0c0ca257 0x1dc24c77
5816 - 0xbad7203b 0x3a998fa0 0x9cb20388 0x7ef1fb3b
5817 - 0xbae66020 0x9a22144f 0x39ac47db 0x3f145996
5818 - 0x05a32b6c 0xd201a2ec 0xd868727f 0x08b2df4f
5819 - 0x4583bbfa 0x9a422baa 0xa6a2e8f5 0x236310ec
5820 - 0x5aafc3cf 0x344156a6 0x6f964ceb 0xed0495ae
5821 - 0xb5638c98 0x2c8e84ba 0x63d8c7a5 0xec956b66
5822 - 0x69c54f32 0x767874ec 0xe8fb6ce1 0x68b1c780
5823 - 0xe4b861e4 0x2787cc38 0x4b2202e7 0x23b476be
5824 - 0xecdf296f 0x094aa000 0xe95ef073 0x4182ebb5
5825 - 0x30daa31a 0xef68cb68 0x2fbcf6bc 0x21c52620
5826 - 0x19abf83e 0x4de7528c 0x05fe4c05 0x32c2a1e9
5827 - 0x8c23abdb 0xabba9a90 0xa6a215c1 0x891f915c
5828 - 0x667cd65a 0xaa5a9b2c 0x689fd1e9 0x42b52c95
5829 - 0xd9872e76 0x05dd5278 0xc19798f7 0x8d031d86
5830 - 0x25690670 0x165f4b19 0x76b51d6f 0x61cd8232
5831 - 0x7b530271 0xa8e9326c 0xd952e94d 0x56a7021b
5832 - 0x128be860 0x4da40144 0xeb4ac3d5 0x82b7ff5a
5833 - 0xea2abda7 0x690a9ebc 0x33562378 0x6bc91b2f
5834 - 0x46134185 0x8fb77fb2 0x029518a2 0xe1fa1f4c
5835 - 0xf78783b9 0x5d8ebe63 0x103e8050 0x924085bf
5836 - 0x80593f2e 0x5be4bcb6 0xcb935edd 0x882d0a5f
5837 - 0x7deb8205 0xcdc0fe2e 0x9c333db4 0x1d0c888d
5838 - 0xf8dc3575 0x2f901125 0x6bf48cdb 0x98ab6fb4
5839 - 0x491d7df2 0xa064922e 0xbbb86c70 0x88aad77d
5840 - 0xfcff0669 0xb0c47c1c 0x0fcc6fe1 0x50df8a83
5841 - 0x014460e4 0xb014e6ab 0xbeff4bc5 0x8d939fae
5842 - 0xd750ae17 0x42dd29c9 0xdb1cbf70 0x82265be9
5843 - 0xd11afd6a 0x21834e1c 0xd11e3c3a 0xbe568139
5844 - 0x6cf92d50 0x9304ebf1 0xf177046b 0xa5b127a5
5845 - 0xfb57e4a7 0xf94291df 0x0f089d58 0x07395b5f
5846 - 0xde4ba5b9 0xf7371fc5 0xae44f190 0xd529271d
5847 - 0xbcaea246 0xfa777c0b 0xad3bab9f 0x0d6251ec
5848 - 0x6f4fa894 0xc39273e2 0x7710fcc3 0x81f08a5d
5849 - 0x395b54ee 0x87295638 0x57398bb0 0xfd46c7c9
5850 - 0x3f1dafc6 0x548479b7 0x37c42fba 0xa2130147
5851 - 0x99dc0bb0 0x3596c5cf 0xbcca6bec 0x418735ed
5852 - 0xfcd4273d 0xee141135 0x8457cf47 0x95fe7220
5853 - 0x041aaf8a 0x6e947153 0xc963afa7 0x09390a74
5854 - 0xc40dffd3 0x4208039c 0x319b1f84 0x42b6b3b7
5855 - 0xade789da 0x83338c91 0xf2d74712 0xe80011dd
5856 - 0xdd61645e 0x286fc63a 0x26e2fb23 0xfef2b4ea
5857 - 0x3290efb8 0x595a0c17 0x6cd9bea9 0x7be1338e
5858 - 0xe0ff2c09 0x1b93aea5 0xbbd97e91 0x5e1ae1e7
5859 - 0x7c6c078b 0x0b9b3a03 0x43d38011 0x824cd94b
5860 - 0x9725170d 0x87ce6f33 0x60525d85 0xc0a5e853
5861 - 0x242e613b 0xebf72857 0xcb500fc6 0x0de5c3f0
5862 - 0x382b625d 0x08840e50 0xcef30663 0x1bc848b6
5863 - 0xefa78141 0x81b860d6 0x4eb125fe 0x7e125296
5864 - 0x276a5558 0x45caa775 0x7c6ec23c 0x5dcddd08
5865 - 0xc41aa32d 0x6a2851b1 0xb69ae1c1 0x8f603c43
5866 - 0x763497f2 0x73344cbd 0xcffd175c 0xfccf5a91
5867 - 0xb2318bf7 0x66ac628f 0xa98fa975 0xb68e5426
5868 - 0x27555715 0x5157a93f 0x666fd404 0xb37fcc40
5869 - 0x563b0512 0xb70f8446 0xe10d257f 0x73793ef2
5870 - 0x31a84915 0xe0de9489 0x08dfa368 0x9169d4fd
5871 - 0xc14f5c9a 0x92e6db4f 0xa30b6cec 0xca04670e
5872 - 0x8a664367 0xe8984e70 0x1c96a39c 0x655f9abd
5873 - 0x6999a190 0x76267621 0x0f49f963 0x8ddad3a1
5874 - 0x51fdab6a 0xaf0d6863 0x23b71bdb 0x32818c8a
5875 - 0x6398044d 0x26c60bec 0xb0b631fa 0x938f69c7
5876 - 0x52f11913 0x1e6fbe7a 0x92dcd409 0x419bfeae
5877 - 0xb147bb96 0xbac5bf9d 0x08de155a 0xde8ca968
5878 - 0x20aef902 0x62df25a8 0x64a4042f 0xef19da4e
5879 - 0xc75fd112 0xc9863e47 0xaccfdbcb 0xd29b6090
5880 - 0x6dc67b4a 0xa84b3cd6 0x45a0e708 0xd28673bd
5881 - 0x00bebebe 0xd5e518d7 0xc63d647c 0xa28f5f6d
5882 - 0x3372edc8 0xa1c44ed1 0x88e61d44 0x5e095835
5883 - 0x2d8713ce 0x6791a885 0xae89c04a 0xf1dc5105
5884 - 0x6423f3b7 0xf4e2f384 0x2d2761a7 0x38ea905d
5885 - 0xa263d776 0xd1936fa6 0x2fc54081 0x429a25c2
5886 - 0x13f6c5df 0xffffa6c1 0xfaf82002 0xe4bbb103
5887 - 0x2fc0c622 0x669ee281 0xec785fda 0x91156b25
5888 - 0xa9f4444e 0x354fdfc2 0x7c5f5069 0x72ae591b
5889 - 0x73bfd64e 0x6b96d744 0xf261daaa 0x2de15dae
5890 - 0xedaba9c2 0xf287b3fd 0x8b2097b6 0x589934c0
5891 - 0x7edc2a73 0x469b16eb 0x247b9a22 0x8b7e6c7b
5892 - 0x3e71ffe2 0x5275f242 0x032a211f 0x977bff60
5893 - 0x4306ad03 0x6a212383 0xceb36448 0xa2a79209
5894 - 0xe3842f42 0xcee0cbe7 0x37cdb626 0x29a0a515
5895 - 0x2857ead6 0x981d5d9b 0xf0ff9b06 0x95de8cad
5896 - 0x4dcb565b 0x065d585d 0xe7eb754b 0x278fa774
5897 - 0xe4d8fb7a 0xe152f018 0xfb7bb25e 0x50323b64
5898 - 0xba618e43 0xf8cb1c61 0x1b6dce25 0xb4fc7867
5899 - 0x2a7fb213 0xea9e646e 0x3f9b735b 0x5640315d
5900 - 0x0793ba5b 0x71ff31fb 0x4b41f1d6 0xb1538146
5901 - 0x336f4272 0xf176d509 0xb7fc03c5 0xd6a1c927
5902 - 0x56a68c10 0x8b4740cd 0x14c54f8a 0xf07ad8a9
5903 - 0xa8403db8 0x37c23f2b 0xdca69aba 0x4b39ef9d
5904 - 0x2af13bdb 0x6baace1f 0x8c7ca0d2 0xba86bd02
5905 - 0x2a74681c 0x5542ae58 0xc36709e2 0x82b34568
5906 - 0x26ea06be 0xd4bf458c 0xde209de7 0xa311b4e5
5907 - 0xdc00e139 0x7d305958 0xc5d76ed7 0x0943a285
5908 - 0x48ce4e29 0xe371bd9a 0xfe6a6501 0x4167d215
5909 - 0x402e47ba 0x588458be 0xbf4bcf37 0xf7fa27a8
5910 - 0xb725f91a 0xc17f5c07 0xce771dbe 0x66f9d592
5911 - 0xe8521ed4 0x42f75171 0x343b3e74 0x2d5448b5
5912 - 0x2d1fca8c 0xd7a32431 0xc29a88d2 0xffb07fd7
5913 - 0xcca0333f 0x43204f2f 0x866c1867 0xcb215814
5914 - 0xfcb67d4f 0x423680be 0xdf22f6d6 0x03373eda
5915 - 0x3bd202e3 0xd8972fe3 0xb7733d70 0x7a472c76
5916 - 0x6cc8a627 0x3b27e643 0xa3475f3f 0x87ffb286
5917 - 0xf823d69f 0x6d57c38e 0xa0fd464e 0x53e2e341
5918 - 0xaaab23ef 0x439429ef 0x55ba2a2b 0x4da5ea4c
5919 - 0xc1fe05fc 0x874b7a34 0x9a875956 0x713ccc90
5920 - 0x49afcff2 0x5905dc0b 0x1f5dddb7 0x8ef5c1d9
5921 - 0xf60eca50 0x25172569 0x3525639a 0x25804bbe
5922 - 0x5729cd49 0x17f84e66 0xc540d86d 0x51524bc9
5923 - 0x9a6e9901 0xf5bcc70e 0xf7a73ffd 0x54509c8f
5924 - 0xec58b8a4 0x9993703b 0x6ef45fc4 0x5ce3a507
5925 - 0x1d73c611 0x8780e8ff 0xc7d2e02b 0x0bc825f2
5926 - 0x02f75fca 0xe80c0758 0x24646fe9 0xd378ff5a
5927 - 0x592c5619 0x6c80372e 0x1f7351d1 0x4db5182d
5928 - 0x3985fdfb 0x16ca9158 0x58ee1ae4 0xaf2b9fa0
5929 - 0xe97f60ce 0xbb911e68 0x01748fa0 0xaef578d3
5930 - 0xc3736418 0x8ab0deb5 0x0de16af1 0xb8369f7b
5931 - 0x68e43c12 0x914ca0f6 0xe950ef28 0x834eff90
5932 - 0x51adb952 0xc42ee4ce 0xf70ab4a5 0xbf9fc916
5933 - 0xed9444b1 0x845a6a1e 0xf92e7b64 0xb9ca8a1b
5934 - 0xa9cdfcd0 0xb5956bc8 0xb8520e59 0xdde7aa57
5935 - 0xb41d390f 0x364aef3c 0xf39d4482 0x8b4e651e
5936 - 0x0b82f5fb 0x7960e81c 0x12ed7b84 0xe9f123ca
5937 - 0x88a64db2 0xa0c714cb 0x57b01471 0x80ff31a6
5938 - 0x7571d8cd 0x857035d9 0x0508587c 0x594a4a42
5939 - 0x011503e5 0x27c75e55 0x03264f62 0x9316ed1d
5940 - 0x36e5cd1e 0xfa9b23b4 0x5bc8c606 0x0902bd38
5941 - 0xd6745c69 0x6fa73118 0xa50f7b94 0xc529e962
5942 - 0x28738486 0x7b85a599 0x2c495a35 0x85f2cbef
5943 - 0xa09dfe51 0x1c763ab2 0x4effdb5c 0x506586f0
5944 - 0xec182a58 0x45293146 0xaf8d78b8 0xa89bd228
5945 - 0xec24826a 0x752cc421 0xbf36aa46 0x6760e225
5946 - 0xe15d0987 0x6fa9bdf3 0x6837c755 0x9426d654
5947 - 0x14b48f5b 0x5d70567d 0x63a14f92 0x809d5361
5948 - 0x3b6e2729 0x84ce5415 0x7eaca6e0 0x9b467302
5949 - 0x8f39d484 0x8e78398c 0x33108b33 0xdc07005c
5950 - 0xbdc2500f 0x35f1f452 0x9d254e3d 0xfa61eb21
5951 - 0x2ab6c7aa 0x83561fdc 0x8735d598 0x416e8591
5952 - 0xfe10e93a 0x18da409d 0xab6d0bfd 0x675baaf1
5953 - 0x287fdd24 0x6b50b63c 0x8c08abca 0x871a59c9
5954 - 0x41bb2ae4 0xfba9abdf 0xb46491c7 0x4e433d5a
5955 - 0x01e4fbda 0x0bc40399 0x3bdb61c2 0x3cf051ba
5956 - 0x910daa46 0x8d4065d6 0x270667eb 0xf6d42459
5957 - 0x01993a1b 0x00a95dda 0x6ed5a693 0xed4fbf7b
5958 - 0x24dbb70f 0x67fd62ee 0xcef5f0a4 0x9e65b798
5959 - 0x9a9913fd 0x3d0e7190 0x4265b4e4 0x80bfc46f
5960 - 0x6b354d2c 0x2b90a987 0xc989cb75 0x773e6b64
5961 - 0x55325e9f 0x18816a56 0x07413406 0x5177ae31
5962 - 0x24a19ef7 0xdac405a4 0xdca2d3b4 0xab7c7b70
5963 - 0x42b5de0e 0xfcf918a5 0xa54d934b 0xcaa9eab6
5964 - 0x50e63e2a 0x4b168926 0xb2442913 0x594c0f94
5965 - 0xf387f31f 0x4d716749 0xc8433297 0x34c1a5de
5966 - 0xe929008e 0x5644251b 0x736476d0 0x0d00aee7
5967 - 0xf20b2f64 0x5e158173 0x9af3e568 0x5f19fa7e
5968 - 0xb23b2861 0x8659ee6e 0x94058a64 0x66ec4fb1
5969 - 0x37cd6a4a 0xbd2944fe 0x0ea44ec6 0xe7d64c24
5970 - 0x75a170e3 0xb4a9479c 0x2215716a 0x64a8a574
5971 - 0x257e86ab 0x86bae993 0x3030352b 0x15cb88bc
5972 - 0x576363a0 0x61138c36 0x7cc4fe7f 0x648977a8
5973 - 0x0ef71fec 0x1c60df47 0xc75f70ea 0x88509798
5974 - 0x172b407a 0xf888e400 0xef33cd15 0x5976757d
5975 - 0xf8cfef13 0xbf024380 0xbb9c1b02 0xe4c38ec9
5976 - 0xf30fce01 0x8efa5213 0xf4b48aad 0xc94c3a37
5977 - 0xeb1bcece 0x09a18b56 0x4e83c0d3 0x6fcf9f77
5978 - 0xf52f4d76 0xf3368a12 0x33b2797f 0x627b6e41
5979 - 0xefd05154 0xa83ae2a0 0xea211129 0xd25723d5
5980 - 0x7bbb0e3b 0x7131f088 0x5dd5193f 0xef5aa905
5981 - 0x39f77be7 0xa21b48c1 0x1ded01c1 0x5cf98c5f
5982 - 0x6e23d207 0xd7e7dadf 0x5932ed1a 0x2a729061
5983 - 0x29a89f4a 0xac0e8447 0x01ff4205 0x8b1456c6
5984 - 0x3fba0156 0x658c03f7 0x5c69f968 0xf6570582
5985 - 0x21bb0145 0x8683bf5b 0xa4b6eba5 0x4ccfe5cb
5986 - 0xd202898c 0xbd2411cc 0xc2fc702a 0x5c39b695
5987 - 0x87584ccf 0xeae3c735 0xc472b6f9 0x4249f637
5988 - 0x3fa89c0e 0xce5a8bd7 0xbb28138b 0xc080ecb1
5989 - 0x9cbf1916 0xd70424e9 0x75cc4ed1 0xa575f3e9
5990 - 0x1c571f68 0xe2906205 0xc26520cf 0xf9c1fc8e
5991 - 0x61c982de 0x1af6cfcc 0xaf397c9a 0x46830771
5992 - 0x623d98bb 0xda7b52fa 0x5a3c57d3 0xfa35d2f0
5993 - 0x4783df19 0x6ad07325 0x487406f4 0x3fae5152
5994 - 0x189137cb 0xd98a644e 0x17ffe880 0xeb6aa9f7
5995 - 0x67184e3e 0xe475734b 0x0f1113c2 0x39a4df47
5996 - 0xbf8f6ec9 0xe13a4d8b 0x63ec02f5 0xdfe7d75d
5997 - 0x1379034c 0x5db7314a 0xa9d9ad3e 0xfaaed8f2
5998 - 0xf0fb6074 0x12f27b84 0xc97a92bb 0xae5e3bb7
5999 - 0x5f7fc2bf 0x00cbc1f7 0x9360a4d9 0x3632ba04
6000 - 0xad044c83 0xeda13ec1 0x34a214c0 0xcf9c972a
6001 - 0x96352243 0xf1a35357 0x2d77bc30 0x8485bbad
6002 - 0x67fbaa99 0x8035b1a5 0x8ca763c0 0x109d7887
6003 - 0xa1c35cd8 0xdc79e308 0x4495404d 0x64419226
6004 - 0xacdcea08 0x9545c0ef 0x5493e09e 0x7fe16336
6005 - 0x41381aa2 0x5c344f46 0xb40cab9f 0xc43951c4
6006 - 0xd86e52a5 0xb141d934 0xd78efcff 0xf37ec320
6007 - 0xc184a45b 0xf4a57954 0xc8aed0bd 0xe602c15a
6008 - 0x71a6b48b 0xce837428 0x02733706 0xc4a4a044
6009 - 0xa75efb97 0xcb63d62e 0xd0580b5a 0xce499087
6010 - 0xc12bf4ca 0x9c995345 0x1d8adfbc 0xe62fd60e
6011 - 0xccbf5412 0x6161f8d0 0x64268e34 0x565d066b
6012 - 0x1896b63f 0x838f8f2a 0x1e314a00 0xac470276
6013 - 0x1879cfdf 0x4702d7f9 0x83b4d777 0x81fcb068
6014 - 0x1b6da94d 0xd075ed01 0x3c7734e8 0x56389a0b
6015 - 0x0743b9cd 0xb6b0bf0d 0x63107ab9 0x193172bc
6016 - 0xc7b84c8e 0x982ce2aa 0xb8e387a6 0xc264a4b0
6017 - 0x2ac6c802 0xb89ea335 0x052332a4 0x49932ecc
6018 - 0xb940f808 0xa7a09330 0x19f3f49d 0x7aef6b5a
6019 - 0x201d8ed0 0xf29aac4b 0x8ae2ac0f 0x998c1ca7
6020 - 0x665c3927 0xab4ef641 0xf136710d 0x9644ee9b
6021 - 0x34efae96 0x4c596035 0x8cfe8b3b 0x5d9f742e
6022 - 0xab2c63ca 0x017d864d 0xd0604d6e 0xab24eee0
6023 - 0x75916a9a 0xad0d1167 0xbeb47775 0x6ac822d1
6024 - 0x776907aa 0x9e9377f2 0x438c5d81 0xd70e9964
6025 - 0x1c09c914 0xab90e5cf 0x31cee523 0x26ba6ea7
6026 - 0xef00781d 0x622b886d 0x36a54031 0x88b1221c
6027 - 0x666333f5 0x60e1c93e 0x5e4d0e0a 0x3ee6ff69
6028 - 0xceb4c76b 0xa5deb4f8 0x0668ced8 0x30225378
6029 - 0x6697cf37 0xc5d9661d 0x089eab85 0x7684a876
6030 - 0x018a81af 0x221a7fb2 0x31d80de0 0x9f18ae90
6031 - 0xa29c9af0 0xc3e2b00f 0xda0edbab 0x7ee9cd2a
6032 - 0x3ab0f88e 0x02c58228 0x606fa7aa 0x7776cb0a
6033 - 0x4e8ad99c 0x3b527469 0x58123d62 0x4ce428d2
6034 - 0xee91a210 0x466ba2cc 0x043c57b9 0xaf7bdd43
6035 - 0x98e76fee 0x8f3eac1b 0x00dffd6c 0x6fcb1c6a
6036 - 0x5cb90573 0x485d4505 0x0df5418a 0x26eafe35
6037 - 0x0faddf3e 0x4e972930 0xe113c823 0xe45944d1
6038 - 0xa646077f 0xc1708ae5 0x6ba07c20 0xc7e4e234
6039 - 0xc6754ed5 0xbd6e85aa 0x8cc1756e 0x02afda29
6040 - 0x72809597 0x75b6f5a1 0x61141874 0x1774047f
6041 - 0x7a10afed 0xfac2c4ad 0x42cf5c99 0x24f0350e
6042 - 0x042f2864 0xfab55b67 0xc8ead5bc 0x914e9512
6043 - 0x77c8ef6b 0x8369aeb1 0x71bc947f 0x0c6b49d8
6044 - 0x8ddd0513 0x028ad10d 0x99a1b28f 0xe6cfbdc8
6045 - 0x7978b4a6 0x3ebbade8 0x9985f5cf 0x431f42f1
6046 - 0x004372b2 0x18b67f68 0x20111c21 0xbb6f77ff
6047 - 0x1783b030 0xa045d7d1 0x0e9c7e09 0x3ccbd95f
6048 - 0x0b84a2ed 0xf0ee3325 0x63f2e126 0x5ec4c67b
6049 - 0x2ca782cc 0xcaf20d04 0x8b59d515 0x3212aa33
6050 - 0x335ca0c3 0x6f9e0cdd 0x4d4bf189 0x44d2fa0c
6051 - 0x5abe9396 0x492794ee 0x10dcfcb1 0x9acda9bd
6052 - 0xe8aa2803 0x3f1b9605 0x3e2ecb5a 0x971bfa8a
6053 - 0xcbf141d2 0x0afafe10 0x2fc906a6 0xefad20c0
6054 - 0x9e922581 0xe69142cc 0xc9c0ba82 0xc069e640
6055 - 0xb99c08b6 0x4b62ca1f 0xf3c5767a 0x6ab088c7
6056 - 0x8f0f0c0b 0x6726f64a 0x9711a3cd 0x46462571
6057 - 0x3a58350e 0xa2561911 0xe24dfdfe 0x97443fdc
6058 - 0xf80540be 0x069978bf 0xb38a359b 0x8e574f62
6059 - 0x69aea75c 0xdc753fcb 0x2a74002c 0xced027b4
6060 - 0xda993254 0x03409b83 0xf827331d 0x75fb3271
6061 - 0x01ad839d 0x68520842 0xca65c45c 0x1a3db5a0
6062 - 0x91d37dd3 0x6168c0fb 0x935f5a08 0x002007c3
6063 - 0x42eb4760 0xdab3a804 0x72a6297e 0x905c32d9
6064 - 0x81abcfa9 0x1b21d04a 0x5a1289ae 0x424e7183
6065 - 0xc207906c 0x31fe9134 0x5eb2e5af 0xc9253fc7
6066 - 0xc32be24f 0xe5474cbd 0xeff6e1b0 0x710e5e69
6067 - 0xe6c4c538 0x96b5f1de 0x2abc9c35 0xddbd1a92
6068 - 0x8aca40d7 0xe359c238 0x954718f4 0x18b157e5
6069 - 0xeeed790e 0x6948a963 0x24e70bfb 0x4d681547
6070 - 0xf68369a7 0x5b54409a 0x1f0b787a 0xc2610047
6071 - 0x0f8bd269 0xd7c8c154 0x9dee62d9 0xd4738ed8
6072 - 0x1a66c6b1 0x5bad5a5b 0xb110311a 0xfaec6802
6073 - 0x6b750f2d 0xcbf8d0e0 0x11edaf4b 0xf64a07bb
6074 - 0x422e7c15 0xb1732663 0x1ff404f0 0x2d5052b0
6075 - 0x6e45356c 0x7e2201e8 0x7c5ebcd1 0x1cb4425a
6076 - 0xb1539a64 0xa2e4459f 0xcf1ade8a 0xfc476473
6077 - 0xf4147deb 0x2afbdd77 0xff01fabc 0x6597408a
6078 - 0x0951220b 0x6750f3ec 0x0a242763 0xf3d71c05
6079 - 0x84cb1c26 0xdb7a81bd 0x7aea1a5d 0x7e719a48
6080 - 0xc5c12fe1 0x0ce2e988 0x29ecc6f0 0x5ede901a
6081 - 0xda8399b1 0x31c05d6b 0xe1956aff 0x59ed7c3d
6082 - 0x60832637 0x9bcb7cac 0x63c530d1 0x14c677de
6083 - 0x9225ed18 0x065327c9 0xd1ff6a0e 0x5516517e
6084 - 0x53c6f5c2 0xed5983cf 0xaa1d18b9 0xbe300d7f
6085 - 0xadc525a7 0x07ea81b6 0xfc517a09 0x4ead3f86
6086 - 0x45435f41 0x2efa58df 0x02348ebc 0x30ed6783
6087 - 0x190b4fb9 0x85c55d6e 0xc9ed8896 0x416ee113
6088 - 0x9b3536d9 0x30577cc0 0xbc4b88c8 0xcda59612
6089 - 0xdfe2bd89 0xd60cde71 0x98843881 0xcc1f32f2
6090 - 0x18b3f643 0x671a14ca 0xd6482a47 0xac6a7d38
6091 - 0x1897da16 0x91b6fcb3 0xf199bb35 0xd38c00ba
6092 - 0xa8c946b6 0x52a1ad37 0xd38ed2d4 0xa1d6f81d
6093 - 0x5af6865b 0xebdb858f 0xb844b110 0x53201ea2
6094 - 0x08870945 0x10c869de 0x19849613 0xdb35d3ed
6095 - 0xd68ebd6e 0x1056fd48 0xf1a0e305 0xe3982ebd
6096 - 0x6f7cc391 0x5956374a 0xf414a5a2 0x325119ab
6097 - 0x99ee1f96 0x6f044bd9 0x8374805b 0xb55c366c
6098 - 0xa2c77051 0x68f199e5 0xd36a9714 0x878f847b
6099 - 0xec0394ae 0x86d0584b 0xf4df66b9 0x451cd039
6100 - 0xf4de06ae 0x35dd0554 0x818a342f 0xeefdbfc9
6101 - 0x5b4e9edd 0x22d9313a 0x3b710d60 0x6deaeb4c
6102 - 0xa9e26512 0x98d31867 0x3c2c2d61 0x7eb5ce41
6103 - 0x40890db6 0x7a3aa660 0x3ef4f306 0x7322881f
6104 - 0x49dac4d5 0x96efe685 0x27bb7f49 0xbb955283
6105 - 0x79c5f2b7 0xff599c28 0x28ee7f5e 0x9f324b73
6106 - 0x45edb7cf 0x39a8b79c 0xd0919c6e 0xe149b29d
6107 - 0x62f5f82e 0xebcfa23e 0xd4d68937 0x54270090
6108 - 0x958af0d4 0xa1e4e799 0xaf68ac19 0x82a84f4e
6109 - 0x50f67b84 0xd5e59629 0xf5fdf24c 0xab1d63c5
6110 - 0x30835807 0x431fce5f 0xe5f96f4d 0x3f6b4802
6111 - 0x14010be8 0xdca45ae5 0xc82709af 0xff76ce2c
6112 - 0x8b222c22 0x73a2d948 0xa8d59cea 0x8c31849e
6113 - 0x469c2e5f 0x3777ee84 0x5fdfa5da 0x02ef9bb2
6114 - 0x792d3194 0xbed63f21 0x0b6dc5f1 0xc9d7fe08
6115 - 0x6df7883d 0x366566cf 0xef772769 0x37826465
6116 - 0x1cdc3086 0xa69ff7b6 0x235012ea 0x292f7e75
6117 - 0x30bdd0fd 0xffdc9df1 0x95c6d570 0xec206204
6118 - 0xc6cd42cb 0xc0d6dfd9 0xb7a16b71 0x17fa527e
6119 - 0x295f2c79 0x990f9820 0x8b8f447d 0x193f9ad1
6120 - 0xebddb2af 0x5dd532eb 0xf1bbd8e8 0x3444a3f4
6121 - 0x18ccce93 0x05edeb4f 0xc4a6b935 0xba37aab0
6122 - 0x96076ba4 0x250dc2f7 0xc4093548 0x030e777d
6123 - 0x7ea40933 0x8da7b1dd 0x59c0b79f 0x807d437c
6124 - 0xf5233ddf 0x54c1983f 0xfc18771b 0xe74b85f0
6125 - 0xdbd725b5 0x70cdd153 0x4ffe300c 0xfda4bdae
6126 - 0xf4ac75d2 0x91c4e15a 0x34d92b97 0x16356a79
6127 - >;
6128 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/Makefile u-boot/arch/x86/dts/Makefile
6129 --- u-boot-2015.01-rc3/arch/x86/dts/Makefile 2014-12-08 22:35:08.000000000 +0100
6130 +++ u-boot/arch/x86/dts/Makefile 2015-01-01 17:34:32.253503252 +0100
6131 @@ -1,6 +1,7 @@
6132 dtb-y += link.dtb \
6133 chromebook_link.dtb \
6134 - alex.dtb
6135 + alex.dtb \
6136 + crownbay.dtb
6137
6138 targets += $(dtb-y)
6139
6140 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/microcode/m0220661105_cv.dtsi u-boot/arch/x86/dts/microcode/m0220661105_cv.dtsi
6141 --- u-boot-2015.01-rc3/arch/x86/dts/microcode/m0220661105_cv.dtsi 1970-01-01 01:00:00.000000000 +0100
6142 +++ u-boot/arch/x86/dts/microcode/m0220661105_cv.dtsi 2015-01-01 17:34:32.253503252 +0100
6143 @@ -0,0 +1,368 @@
6144 +/*
6145 + * Copyright (c) <1995-2014>, Intel Corporation.
6146 + * All rights reserved.
6147 + * Redistribution. Redistribution and use in binary form, without modification, are
6148 + * permitted provided that the following conditions are met:
6149 + * .Redistributions must reproduce the above copyright notice and the following
6150 + * disclaimer in the documentation and/or other materials provided with the
6151 + * distribution.
6152 + * .Neither the name of Intel Corporation nor the names of its suppliers may be used
6153 + * to endorse or promote products derived from this software without specific prior
6154 + * written permission.
6155 + * .No reverse engineering, decompilation, or disassembly of this software is
6156 + * permitted.
6157 + * ."Binary form" includes any format commonly used for electronic conveyance
6158 + * which is a reversible, bit-exact translation of binary representation to ASCII or
6159 + * ISO text, for example, "uuencode."
6160 + * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
6161 + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
6162 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
6163 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
6164 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
6165 + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
6166 + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6167 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
6168 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
6169 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
6170 + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
6171 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
6172 + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6173 + * ---
6174 + * This is a device tree fragment. Use #include to add these properties to a
6175 + * node.
6176 + *
6177 + * Date: Sat Sep 13 22:51:38 CST 2014
6178 + */
6179 +
6180 +compatible = "intel,microcode";
6181 +intel,header-version = <1>;
6182 +intel,update-revision = <0x105>;
6183 +intel,date-code = <0x7182011>;
6184 +intel,processor-signature = <0x20661>;
6185 +intel,checksum = <0x52558795>;
6186 +intel,loader-revision = <1>;
6187 +intel,processor-flags = <0x2>;
6188 +
6189 +/* The first 48-bytes are the public header which repeats the above data */
6190 +data = <
6191 + 0x01000000 0x05010000 0x11201807 0x61060200
6192 + 0x95875552 0x01000000 0x02000000 0xd0130000
6193 + 0x00140000 0x00000000 0x00000000 0x00000000
6194 + 0x00000000 0xa1000000 0x01000200 0x05010000
6195 + 0x19000000 0x00010500 0x15071120 0x01040000
6196 + 0x01000000 0x61060200 0x00000000 0x00000000
6197 + 0x00000000 0x00000000 0x00000000 0x00000000
6198 + 0x00000000 0x00000000 0x00000000 0x00000000
6199 + 0x00000000 0x00000000 0x00000000 0x00000000
6200 + 0x9557a557 0x7d7a0fe3 0x8e2fbe53 0x0db9e346
6201 + 0xd35c00d6 0x21bb34b7 0x662b6406 0xa0425035
6202 + 0x3d028208 0xcb843695 0xee06be0a 0x9817efa7
6203 + 0xb86c0d16 0x45f70c93 0x79fdc3af 0xd5f30da7
6204 + 0x460f62b0 0x238a0470 0xf0ec95bf 0x97b9c176
6205 + 0x6d612851 0x69b9b4b6 0x1df769cc 0xe11674df
6206 + 0x1b579adf 0xc8bcc050 0xcdb3e285 0x327592c1
6207 + 0xbeb6047a 0x977f6be5 0xc4854052 0x27f38b66
6208 + 0x4ca5eab3 0xf806decc 0x2be4b409 0x460a3b03
6209 + 0xde2f6e0f 0x53ce08b3 0x3ef0ef93 0x4e013088
6210 + 0x226f8a5c 0x57f7d291 0x8d640bf7 0x8a998907
6211 + 0x40464dd8 0x804ef3e5 0x647e35f3 0xeabee2d1
6212 + 0x3a5ce9c7 0x4d7ee530 0x564321ec 0x9e85107e
6213 + 0xd595581d 0xcbf6efde 0xed3010ed 0x3d607e82
6214 + 0xe32d4b6b 0xd06fec83 0xf39240a6 0xe487988d
6215 + 0xddbefcbe 0xefaf1121 0x96bf9acb 0xacce795c
6216 + 0x7fa5f89b 0xbe440e5d 0xb6d3a3dc 0xcad17290
6217 + 0x503ae748 0x04c80b8d 0xd394ea6a 0x3e4072c3
6218 + 0x11000000 0x0b0ae65d 0xc6c53cbd 0xd52a6c2d
6219 + 0x84cc192f 0x89498e7d 0x89270686 0xe68105e0
6220 + 0x4073a570 0xd3338d8e 0x51193152 0x7266182f
6221 + 0x980553fa 0x51b89c90 0xd13b6151 0xe6e40a91
6222 + 0x0ab997d8 0x2d0a443b 0x9d3d566d 0x820402d1
6223 + 0xdbe79fcc 0x7c5e0b45 0xaf94216d 0xbf717950
6224 + 0x520b3dd4 0x566a3396 0x0b6f794f 0xc5dfeda5
6225 + 0x71ba0f02 0x4839a5ed 0x39a4e4a6 0xe567c652
6226 + 0x0e044997 0x84a0effd 0x09c67178 0x89a815c8
6227 + 0xac821555 0xd6719303 0x582b964e 0xfe3a53f6
6228 + 0x241b9b8b 0xc6e65457 0x623a4e0a 0x590d7d03
6229 + 0xe50e7ce1 0x4bca4700 0xf24f5eff 0x1f1b20d9
6230 + 0x77e3227e 0x699b5e5d 0x9aa5f621 0xff08bba0
6231 + 0xf17ce716 0x0f5336f5 0xbce055a7 0x8cea9dac
6232 + 0x8e09d26c 0x66c3ddf0 0xbec71660 0x75248cd2
6233 + 0x29afcf8d 0xa5ade5ce 0xf68bace5 0x63b513cd
6234 + 0x4736a842 0x4dbf80df 0x4e85fbdf 0x4dce3d56
6235 + 0xf2150fdc 0xc4232709 0xffdc3e3a 0x92b72a3d
6236 + 0x9ffce715 0x682959d1 0x091ba33c 0x0f1dc729
6237 + 0x2f29a924 0x1df72429 0x19b0365d 0x2d5a3cd8
6238 + 0x20617351 0x109074f9 0xf232874a 0x40d79569
6239 + 0x97dbe4c6 0xa3b66845 0xa04d2faa 0x6dce9a96
6240 + 0xd4963c67 0xd4516f76 0x64a0b04d 0x0b87ddfe
6241 + 0xd8a5305d 0x717ecf67 0x77189035 0x40542ed4
6242 + 0x5a180ff1 0xb2042e2c 0x6639819b 0x0f0756c3
6243 + 0xf939bd70 0x25efe0d6 0x3eb65ae9 0x39a057d2
6244 + 0xb2595655 0xf808b4fd 0xe22d0593 0x76256500
6245 + 0x0eeee6ee 0x6895d1cf 0x9fc117a7 0xd19e5f15
6246 + 0xf677f085 0x1ecdb30d 0x704d0975 0x9099f42e
6247 + 0x421be0b2 0xd02548bd 0x3a16e675 0x7d8b051d
6248 + 0x9d24480f 0xbc006432 0x184da9ec 0xbad7abef
6249 + 0x299f58aa 0xc1a249fa 0x8d9d31f3 0xe73cda17
6250 + 0xf41ac993 0x7b88d3bb 0xf349c676 0xb8341361
6251 + 0x1b69bc01 0x98e0bfd2 0xf31db8d9 0xeb49b275
6252 + 0xabc40133 0xfb7d0701 0xcd5ff353 0x4eaceb8d
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6505 + 0x9aa7fc00 0x382cc48c 0x015f7186 0xc3fd040d
6506 + 0x505408e0 0x21cdc34c 0xbd266059 0x6e2f673e
6507 + 0xe4523c1b 0x3ba56bb3 0x1c343938 0xabc0df54
6508 + 0x8ba4f1e8 0xfbd4c592 0xb678c884 0xff3be2f1
6509 + 0xca013570 0xfb0598df 0x3cb9cc1d 0xe3ba8ca3
6510 + 0xc3d7ecee 0x0ae84a0b 0x0d70f0c3 0x963110ff
6511 + >;
6512 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/microcode/m12206a7_00000029.dtsi u-boot/arch/x86/dts/microcode/m12206a7_00000029.dtsi
6513 --- u-boot-2015.01-rc3/arch/x86/dts/microcode/m12206a7_00000029.dtsi 1970-01-01 01:00:00.000000000 +0100
6514 +++ u-boot/arch/x86/dts/microcode/m12206a7_00000029.dtsi 2015-01-01 17:34:32.253503252 +0100
6515 @@ -0,0 +1,686 @@
6516 +/*
6517 + * Copyright (c) <1995-2014>, Intel Corporation.
6518 + * All rights reserved.
6519 + * Redistribution. Redistribution and use in binary form, without modification, are
6520 + * permitted provided that the following conditions are met:
6521 + * .Redistributions must reproduce the above copyright notice and the following
6522 + * disclaimer in the documentation and/or other materials provided with the
6523 + * distribution.
6524 + * .Neither the name of Intel Corporation nor the names of its suppliers may be used
6525 + * to endorse or promote products derived from this software without specific prior
6526 + * written permission.
6527 + * .No reverse engineering, decompilation, or disassembly of this software is
6528 + * permitted.
6529 + * ."Binary form" includes any format commonly used for electronic conveyance
6530 + * which is a reversible, bit-exact translation of binary representation to ASCII or
6531 + * ISO text, for example, "uuencode."
6532 + * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
6533 + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
6534 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
6535 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
6536 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
6537 + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
6538 + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6539 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
6540 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
6541 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
6542 + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
6543 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
6544 + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6545 + * ---
6546 + * This is a device tree fragment. Use #include to add these properties to a
6547 + * node.
6548 + */
6549 +
6550 +compatible = "intel,microcode";
6551 +intel,header-version = <1>;
6552 +intel,update-revision = <0x29>;
6553 +intel,date-code = <0x6122013>;
6554 +intel,processor-signature = <0x206a7>;
6555 +intel,checksum = <0xc9c91df0>;
6556 +intel,loader-revision = <1>;
6557 +intel,processor-flags = <0x12>;
6558 +
6559 +/* The first 48-bytes are the public header which repeats the above data */
6560 +data = <
6561 + 0x01000000 0x29000000 0x13201206 0xa7060200
6562 + 0xf01dc9c9 0x01000000 0x12000000 0xd0270000
6563 + 0x00280000 0x00000000 0x00000000 0x00000000
6564 + 0x00000000 0xa1000000 0x01000200 0x29000000
6565 + 0x00000000 0x00000000 0x11061320 0xd1090000
6566 + 0x01000000 0xa7060200 0x00000000 0x00000000
6567 + 0x00000000 0x00000000 0x00000000 0x00000000
6568 + 0x00000000 0xd1090000 0x00000000 0x00000000
6569 + 0x00000000 0x00000000 0x00000000 0x00000000
6570 + 0xfd2a2f68 0x82ac7ebb 0xa4916328 0x7480b81b
6571 + 0xd329a777 0x25750339 0x9a8f7a9b 0xf1da9cb8
6572 + 0xb1be7b1a 0x621d5a35 0x94b57e2e 0xa9def809
6573 + 0xe4492a43 0x530252bf 0x1040fada 0x8a853a89
6574 + 0xfb0e6e76 0x6d191ed9 0xefd28b83 0x946414e5
6575 + 0x13f415d5 0x28487029 0xb69855e8 0x516cbedc
6576 + 0xfabbea88 0x9f90e8a1 0x211793d8 0x54653835
6577 + 0xa7789a08 0x754791d9 0x484764d4 0xdca45615
6578 + 0xf64844f4 0xdbd754d0 0x7d2b0ff3 0xd023e25a
6579 + 0xb048bbcb 0x83038b5c 0x57e17d17 0x735f1e9c
6580 + 0x8982c22e 0x6c7b2ad7 0xb26e3b82 0x7121e035
6581 + 0xe4ea8dba 0x68d4f406 0xaaafdb13 0xf119b472
6582 + 0xb5853303 0x20698005 0xcf34604c 0xdc17d19b
6583 + 0x042d6e97 0xf0300325 0xe1b55072 0xc2804918
6584 + 0xd6d7a912 0xf908c81b 0x4f9979ae 0x0179f8c6
6585 + 0x2f13e3c0 0xc5911467 0x39ad6c23 0x9c9d8837
6586 + 0xf3c3f767 0xe56b4a96 0xdad7cebc 0x6eaaee57
6587 + 0x2215ca7b 0x4cee4f65 0xd9a51c2a 0xf33c80a1
6588 + 0x11000000 0x0b468bda 0x0b57c7cb 0x885fad4b
6589 + 0x8a37307a 0x68cc7d5b 0xb6395b55 0x583626b8
6590 + 0x21efe98d 0xa516cc42 0xf5b978b1 0x585d8a11
6591 + 0xdd5f2ee4 0x17b1c7eb 0xb6f005ea 0x9ecc6ac6
6592 + 0x82c0f1b2 0x25a114fb 0xa6086296 0x93da75f4
6593 + 0x0695ff88 0xd413dd65 0xccf7609e 0xb7718aa8
6594 + 0x334406dd 0x28de253f 0xfb43ca83 0xa4674656
6595 + 0x7392e05f 0x9b062c62 0x17571892 0xb5811cbf
6596 + 0x9d64666b 0xa01c1500 0x5893e418 0x07ba6ed1
6597 + 0x0eebedd8 0x299a52bf 0xdfdb6191 0x4e846b26
6598 + 0x298b7431 0x576f4479 0xf5317e04 0xc9492745
6599 + 0x167c42e3 0x0c0cd705 0x82756ce5 0xe81ba860
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6601 + 0x73ddd76d 0xe606c66c 0xe0ad45bf 0xfebdc310
6602 + 0xcb2aa836 0x39903a79 0xe53d5dc1 0x0cb6a1ff
6603 + 0xe6091d08 0xcb2961d8 0xd38987ff 0x2bd624fd
6604 + 0xfb4e484a 0x8c60efbb 0x0ed088b5 0x5a142b04
6605 + 0xa737bab1 0x44da29a2 0xc046ecb1 0xe7ccefdc
6606 + 0x81895d2d 0x41266fa8 0x52a5e25e 0xcfeac133
6607 + 0x252b0737 0xec54b6c8 0xe1c9ebf6 0x25180c1a
6608 + 0xea65b9e2 0x5e9ada96 0x08559e07 0x414fcece
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6612 + 0xdb44dae2 0x60856af1 0x777caf5f 0x298e810a
6613 + 0x93f4f418 0x9e1ddf3f 0x6f589046 0x18ea149c
6614 + 0x4a5ce4b0 0x529db285 0x3c2dde59 0x1d680e51
6615 + 0x3a62d819 0xdf4c01d2 0x432a8f06 0x70a37043
6616 + 0x4a0d4baf 0x0d3395be 0xfce0391f 0x5228aac2
6617 + 0x9dd9b00e 0x6149f393 0x6fee1d85 0x1d3628cb
6618 + 0x107076de 0xd99fe940 0xa227eec2 0xc97d8119
6619 + 0xcf2fa8b2 0x821dac93 0x518875f2 0xd18d1d47
6620 + 0x3e27fdcb 0x47823f98 0x20d42c1e 0x9a58812b
6621 + 0xe0987435 0x1426f12f 0x61d6f627 0x5c58d415
6622 + 0xe5ca80de 0x9e11e526 0xbccc0f94 0xb49cec4d
6623 + 0x357f947c 0xbef0e2f2 0x5b9b2596 0xddc87ff7
6624 + 0x5f2705f8 0xa25f2be7 0xbb45a165 0xe49ef6d5
6625 + 0xe76e250a 0x75584c7d 0x7900da7b 0xee0e3360
6626 + 0x6988740c 0x4aa56944 0x2d485383 0xef45f5d5
6627 + 0x0df4b0f7 0x48199182 0x5b33c21c 0x8f2483c1
6628 + 0x8aae6c50 0xaf406ccb 0xb7522bda 0xeafb64de
6629 + 0x9a9b1fd7 0x3ab46c34 0x0ec5f025 0xe5bc9668
6630 + 0xdb108e78 0xd6152ac8 0xc382ec93 0x5abc2565
6631 + 0x4f256030 0x856f6eb5 0xb589dc96 0x3de80942
6632 + 0x49d20a05 0x8e3ac21b 0x0262ecc7 0x5f1bce89
6633 + 0xec50198c 0x0115b078 0xf67d94e3 0x1cc3682b
6634 + 0xfb2d4ab0 0x4d6ce252 0x1d7aace9 0xf7e99257
6635 + 0xc1235e85 0x8129ee72 0xb6cfbb13 0x6b851ab5
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6653 + 0xcbbdefc6 0x1ab8c0cc 0xd21e503a 0x20c11d27
6654 + 0x2f0adc1d 0xc24240d2 0xc73aa069 0x99afc53e
6655 + 0xcab27e40 0xbe107ccb 0x8ad5f0ae 0x9024c188
6656 + 0xe02bb39d 0xdb784309 0xf91acb54 0x4d15b75d
6657 + 0xd339c237 0x3b556619 0xf69f91f6 0xca6fcfd4
6658 + 0xb5ddf471 0x0698490e 0xb0855c30 0xe2b34b13
6659 + 0x3c979248 0xc0484a59 0xb4cf9f4f 0x7975f2ac
6660 + 0x602259d3 0x89364c24 0x37f29913 0x0b4c88a0
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6666 + 0x78a99aca 0xd60ba313 0xe502992c 0x0c25c2ba
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7036 + 0x1320540a 0xa9843a06 0x34099c74 0x4bdddd23
7037 + 0x18680496 0x44f9cc19 0x6de71a34 0xe4eae858
7038 + 0x3349a819 0x28400571 0x10a55fe9 0x05672399
7039 + 0xb376eadd 0xed4b1a35 0xe79d0a4f 0xca8d0601
7040 + 0x78a7b066 0x8ea59a40 0x7be112a2 0xe99ea438
7041 + 0x44bd9efa 0x6e5227a1 0x70325aef 0x777282e9
7042 + 0xb579c189 0x4ee92bc9 0x0d0236dd 0xb57cf232
7043 + 0xb815e184 0xd05823e4 0x0c9490b8 0x70a5fa56
7044 + 0xdf0f178a 0x99d27374 0x1aba9e05 0x18378c3d
7045 + 0x86991118 0x3a199a70 0x90b2a2cf 0x67a6923b
7046 + 0x0975e5f2 0xf50fb0a3 0xbffbd67a 0xce6371e7
7047 + 0x203564ef 0xb1d7a395 0x201cb1c4 0x30085e3c
7048 + 0xfb2c66b4 0xf80ae969 0x1d407625 0x0bca1a0f
7049 + 0xb62c078f 0x83efbf38 0xbd7b0a69 0x7d9bb66a
7050 + 0x46b5c885 0xb256d753 0x0b5d008e 0x1756d5bf
7051 + 0xa9ffdaf6 0x01231fcb 0x8c69e461 0xbb2ad661
7052 + 0x29dee8f7 0xf1f23d56 0xd5e90ffa 0x48d9d93e
7053 + 0x77b26e95 0x49c47953 0x7565da8e 0x41a6124a
7054 + 0xfce69643 0x55f99554 0xa5501d6e 0x5738b726
7055 + 0x4c989c96 0x93cbe27e 0x20ff3d38 0xf4787a09
7056 + 0xfa3520e4 0x26b2dc11 0xb701c94b 0xcd8857ee
7057 + 0xb4b07229 0x0bbcf1a7 0x3d31cd32 0x08ced413
7058 + 0x3da04c1d 0x7bdf1787 0x344f510d 0x53a02e8e
7059 + 0x7e295418 0xa5ed24b3 0x3a5a2c98 0x34947e44
7060 + 0xb398bfcb 0x7c0ea498 0x18db3289 0xec646beb
7061 + 0x2e8ed766 0x5aff9ee3 0x497dc7fa 0xa70c3be4
7062 + 0xfc9306c4 0x729f532c 0xd87d61d0 0x635fadbd
7063 + 0x1efb1234 0x66fdb543 0xf5b86d07 0x3a4836fd
7064 + 0x9caf7dd3 0x8a9d9e5b 0x179529ac 0xa9a3fee8
7065 + 0x4cfa4495 0x791b8b7a 0xc503fc2b 0x1e07d0e5
7066 + 0x0561cfae 0xb5e7c403 0x0809744a 0xea84c654
7067 + 0x23614fd6 0x23ae773f 0x545be2c5 0x3585b8b4
7068 + 0xcad8b6ed 0x088a56c0 0x81054caf 0xecb13d9f
7069 + 0x44bd49f7 0x90a3da4a 0xf4b04300 0x32a2b69f
7070 + 0x44bed501 0x85cb54ef 0x85dde589 0xe410132b
7071 + 0x1c2e41c7 0x3d28cc9b 0x4df948de 0xaa058c37
7072 + 0xb82cf615 0xfa0574f8 0xd0391f5d 0xfb2b98b3
7073 + 0x3ce5585d 0x80ca4d6a 0x4b138f75 0x721ccc65
7074 + 0x496a3e37 0x4a8dd025 0x2d77b3db 0x65800ff3
7075 + 0x1d2df03e 0xb4b12a59 0x4c6a5b9b 0x17413fda
7076 + 0x4e938a09 0x7e3aa03a 0xf86cc8f3 0x972cd7b7
7077 + 0x871849b1 0x0c0879d2 0xc7c652a9 0xe9531ae1
7078 + 0x541142d9 0x4f731afa 0x9c43e538 0x866b695d
7079 + 0x4a4c4076 0x1e8aa293 0x51bc1eaa 0x5f57d28a
7080 + 0x142eb7f5 0x14096954 0xae0e9eb3 0xef732983
7081 + 0x70187474 0x3569b88a 0xfd3a3c61 0x54f0e2d0
7082 + 0x7afff032 0xa89cd23d 0x658114ec 0x434ccbc9
7083 + 0xc25f33c7 0x1b6e9a7a 0xd97bd017 0x3b7489d7
7084 + 0x67129c97 0x333ee180 0x04bf73ae 0x4731105f
7085 + 0x09d589f9 0x7d5a67a3 0x3e8fcb8c 0x2090c536
7086 + 0x14a623c0 0x21a247fb 0xe117bbe6 0xe98bbd1c
7087 + 0x09e23674 0x02f09f22 0xba7f9f45 0xd18573b6
7088 + 0xa6eb18fb 0xe01a7904 0xa8869f58 0x82ec81ee
7089 + 0xf4549f1a 0xfa0f6085 0x1cf809e9 0xe603d078
7090 + 0x13525306 0xd5611c7a 0x2c92b32b 0x5fdc0c0a
7091 + 0x0b3aaced 0xa40059b7 0x27c42499 0xcc619db5
7092 + 0x9f9b7841 0xfdca5eb2 0x2d3e833a 0x2830a6a0
7093 + 0x4c81f3b0 0x3ec8a8bd 0x50b95605 0x33a9d515
7094 + 0x7fe14795 0x4ff1d83d 0xef92fbfe 0x87f4faed
7095 + 0x35d5fc69 0xd8764a49 0xec81abfe 0x634a2ed8
7096 + 0x9635825a 0x0943624c 0x5eea8464 0x578e2344
7097 + 0x551bd5af 0xca02915b 0xea419d8c 0x9d0fa00e
7098 + 0xf3633f48 0xc6ad62ae 0x1eeef6ab 0x21ab106a
7099 + 0xe325954d 0x60457916 0x6ac9168c 0xea8a9d6f
7100 + 0x14772361 0x7630452f 0x8795e1de 0x21144d8d
7101 + 0xe7996dd2 0x45aff64a 0xfa62c37f 0x3f5a04cf
7102 + 0x250f988b 0x7985d243 0x1f717008 0x7908d22f
7103 + 0x4fc0d5d5 0x856d9819 0xccfab84e 0x3fec2a74
7104 + 0xe75c1af6 0xe2682ac3 0x2f08e560 0x7133d2a0
7105 + 0x63e5fcca 0x3a17438f 0x9cb826c8 0x06a2f3cd
7106 + 0x4bac2001 0x50596ba4 0xe74758d4 0x64d17e0a
7107 + 0x08fc5b67 0xb0d62f6e 0x95eb8e15 0xd51bfa64
7108 + 0x421c68b9 0xdd1526a8 0xfb7ea10e 0xab21193a
7109 + 0x4b1186dc 0x77bbfd82 0x1ab08e9f 0x871659a5
7110 + 0x1658fd5f 0xa04f322d 0xf50ed273 0xb8d411a7
7111 + 0x8056489c 0xfbd858ae 0xd70f7d88 0x3c5cbc78
7112 + 0xf53ec2be 0x1d2228e2 0x8b53aace 0x212454d9
7113 + 0x76ea1d2e 0x9ca66373 0x9f6679c2 0x51c48b56
7114 + 0x47348811 0x8abc0a27 0x60050980 0x5d290483
7115 + 0x7ea8504f 0xde186466 0x91219d4c 0xa73144ed
7116 + 0xb5f36fa4 0xa37912b8 0x02625bd3 0x3bc2d9ed
7117 + 0x2e623844 0xa9a751af 0xf0ba18af 0x4433e06e
7118 + 0xca7cda24 0x686c9163 0x86a437c1 0xf8c17120
7119 + 0xed50542e 0x62b61fa1 0x600e47b6 0xdff86df8
7120 + 0x77502dd5 0xea5d75ac 0x095a06e4 0xa18efafd
7121 + 0xfbd01eaa 0x27a1cb0a 0x3dfcab8e 0x07be7250
7122 + 0x086cb680 0x2c1ddcf4 0x6fa79784 0xcd874edb
7123 + 0xa383d520 0xa5c0d1cd 0x2e09cd9a 0x34d645c4
7124 + 0xf6b9b98d 0xe8e80ab0 0x39b78c60 0x6098b6f2
7125 + 0xc3c13e53 0x88c9fd83 0x60c9e766 0xf49c4c2d
7126 + 0x79e3d3d3 0xbfade7d5 0x6ba57dc1 0x3069e3ad
7127 + 0x59632e2b 0xb86e871e 0x2dd63287 0x9704b283
7128 + 0x343a6cb3 0x37d7950d 0x283f262d 0xd49d5f75
7129 + 0xdacc49b7 0x5952e045 0xc0fefa19 0x69effce3
7130 + 0x5b2a3c0b 0x3757339f 0x18584f8a 0x77a80760
7131 + 0x5fcdadc0 0xc9b4df80 0xfa521be0 0xbcfc8ecb
7132 + 0xfd3f8eb8 0xbee4739a 0x139caf94 0xbdea1cd7
7133 + 0xab158240 0x233fd8dc 0x8ec63274 0x34eee6d8
7134 + 0x4603b2f8 0xae544fc5 0xcd444551 0x2b2b349a
7135 + 0x0a562524 0xb2e02518 0x577b1125 0x8b3c1ff9
7136 + 0xfd27d88c 0x2ad77d04 0x1f82a54e 0x20254fdc
7137 + 0xee8e63cf 0x8df3fa2f 0x9ffc7c43 0x421ae12f
7138 + 0x9b166441 0xb74a5a4f 0xdad0511e 0x0a8ee5e9
7139 + 0x8fe86041 0x37ef90ea 0x3fcf8380 0x87288691
7140 + 0x384b8b8a 0x98d8a45f 0x995443d7 0x6c617236
7141 + 0x9a40f76f 0x9f30733f 0xfdbf3927 0x7b4c0281
7142 + 0x9e87e64f 0x9802938c 0x65f9de31 0x829c3eda
7143 + 0x0a1d2f4a 0x22e0e854 0x30045b70 0xbf84a44f
7144 + 0xc2c30b57 0x47c5ff90 0xaea87e93 0x99c69ae5
7145 + 0x1080e89f 0xc2896e80 0x09ba0cb2 0xd16ee263
7146 + 0xe05337b0 0xef1d8359 0xc1d4b102 0x08620117
7147 + 0x2e4ab2bf 0x05dc3af8 0xc7ab866b 0xeee05983
7148 + 0xd0a00c19 0x96996791 0x75ac6042 0x29001ada
7149 + 0x13440a23 0x2b1eca42 0x4cddfd68 0x81a98384
7150 + 0x6bcda226 0xa8594443 0x92f26e53 0x434de4ec
7151 + 0x07596ee2 0x4c8ea6ed 0x5596054d 0xaffe0ef4
7152 + 0x6dc1ab64 0x20bc006b 0xad4e3933 0xe6df0d3f
7153 + 0xfb3ca9ee 0xc2895a4e 0x8fed0d43 0xa5ed7985
7154 + 0xc364f083 0xc397a806 0x7b651ff9 0x1d7e22e5
7155 + 0xfd02f57d 0x5f16a429 0x8612177a 0xd36b8983
7156 + 0xd87b0303 0xeaa632b0 0x57dff2b2 0x19772dd0
7157 + 0x51317bfc 0x28404b1f 0x9e35d818 0x9c771bb7
7158 + 0x6d42a5c1 0xa6030578 0x9c844d5f 0x95d5eb7f
7159 + 0xdf15f5ec 0xf0f8c86e 0xf8ebfd20 0xae32d9b5
7160 + 0x4ce2b066 0x776f0149 0xda8a429f 0x0e895a79
7161 + 0xbe62c881 0xf9c051d8 0xcaa48f97 0x9e8dcb1b
7162 + 0x69cafc21 0x411f1bff 0x4f4d71dd 0x102cf709
7163 + 0x974ebe53 0x7373aea6 0xef2a7ec1 0xedabaccc
7164 + 0xdac969c4 0xe010b562 0xb6880570 0xa7a7f5d4
7165 + 0x3c6464f2 0x96dea774 0x1614a588 0x06074080
7166 + 0xb37304f0 0x99da7dda 0xd3e36214 0xb27b7cae
7167 + 0xb4cef0b3 0xa435dc77 0x9d1c1a15 0x616993f4
7168 + 0xb8a5ec8f 0xdce1ff5a 0xaaea14c4 0xa5d2172f
7169 + 0x90c8c636 0x49c0b81e 0xff9db895 0x4252b336
7170 + 0xd420b5ce 0x87b35be4 0xae32bda2 0x441092d9
7171 + 0x321e8583 0x7d863719 0x3c888147 0x3f2bb9f6
7172 + 0xd1daf5f1 0x682f2ffe 0xae62e280 0xcf8f928a
7173 + 0x4a7237f5 0x6f3a55af 0xb91dba98 0x9b83b723
7174 + 0x0e857ed8 0xd5ac567d 0xaf8bf791 0x23f8269a
7175 + 0xe369638f 0x6a88edb1 0x5ff0be07 0x5c02b513
7176 + 0x7d22f89e 0x2f865c08 0x9cc0d56e 0x31c87205
7177 + 0x420508f2 0x95a21602 0x04d838e3 0x353353e8
7178 + 0x7ca1feb6 0x61c6f7dc 0xf78a68eb 0x918f2ac1
7179 + 0x413037a4 0x09692d1c 0xc8eceb54 0xb1bf975a
7180 + 0x2ab63552 0x467bceeb 0x408bf024 0xeaed2b31
7181 + 0x3255158b 0x8d9c6617 0xe450350f 0x615cf5f3
7182 + 0x1a7fd744 0x27a0da59 0x43298211 0x77392298
7183 + 0x9511e81a 0x08a2c2dc 0x3d6f1113 0x967e6586
7184 + 0xd1726b35 0xb9292da6 0xaa6f8ad4 0x0f13b47f
7185 + 0x34b96cea 0xebd9487d 0xfe533d60 0x41bcdc60
7186 + 0x364c8c79 0x32be8bb8 0x1395ead9 0x9e85e474
7187 + 0x146b6fbc 0xc93267cf 0xcdda98d4 0xccfb2835
7188 + 0xe779dbd5 0xf9288237 0x2073e129 0x16fe4ab8
7189 + 0x34ca576d 0xac313eb7 0x5deb3b4d 0x1727510b
7190 + 0xc168a414 0x332cd921 0xe38e8123 0x9a2c1aef
7191 + 0x80f5d1d9 0x7c88c923 0x8af17577 0x59ae1408
7192 + 0xffa5e565 0xb418ab13 0xdd6376aa 0x45cd70d9
7193 + 0x3c3a06a2 0xbc555669 0x34d1fc08 0xc2aa934a
7194 + 0x385416e2 0x91ceeadb 0xe06c9cef 0x0394dbd4
7195 + 0x43e7c657 0x296d7621 0x55dafcba 0x808b836b
7196 + 0x61c41f0c 0xd9689bc5 0x3a531ffd 0x8417ed30
7197 + 0x3f3f8616 0x641eb4a9 0x24964006 0xe8d2612a
7198 + 0x3b916d7c 0x5603319f 0x29007523 0xc9c7dc1c
7199 + 0xd1f7212e 0x22ac1932 0x05c39a5a 0xd55081ce
7200 + 0x589ae996 0xa998fcbe 0xd8df5512 0xef7d7a01
7201 + >;
7202 diff -ruN u-boot-2015.01-rc3/arch/x86/dts/microcode/m12306a9_0000001b.dtsi u-boot/arch/x86/dts/microcode/m12306a9_0000001b.dtsi
7203 --- u-boot-2015.01-rc3/arch/x86/dts/microcode/m12306a9_0000001b.dtsi 1970-01-01 01:00:00.000000000 +0100
7204 +++ u-boot/arch/x86/dts/microcode/m12306a9_0000001b.dtsi 2015-01-01 17:34:32.253503252 +0100
7205 @@ -0,0 +1,814 @@
7206 +/*
7207 + * Copyright (c) <1995-2014>, Intel Corporation.
7208 + * All rights reserved.
7209 + * Redistribution. Redistribution and use in binary form, without modification, are
7210 + * permitted provided that the following conditions are met:
7211 + * .Redistributions must reproduce the above copyright notice and the following
7212 + * disclaimer in the documentation and/or other materials provided with the
7213 + * distribution.
7214 + * .Neither the name of Intel Corporation nor the names of its suppliers may be used
7215 + * to endorse or promote products derived from this software without specific prior
7216 + * written permission.
7217 + * .No reverse engineering, decompilation, or disassembly of this software is
7218 + * permitted.
7219 + * ."Binary form" includes any format commonly used for electronic conveyance
7220 + * which is a reversible, bit-exact translation of binary representation to ASCII or
7221 + * ISO text, for example, "uuencode."
7222 + * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
7223 + * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
7224 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
7225 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
7226 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
7227 + * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
7228 + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7229 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
7230 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
7231 + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
7232 + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
7233 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
7234 + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7235 + * ---
7236 + * This is a device tree fragment. Use #include to add these properties to a
7237 + * node.
7238 + */
7239 +
7240 +compatible = "intel,microcode";
7241 +intel,header-version = <1>;
7242 +intel,update-revision = <0x1b>;
7243 +intel,date-code = <0x5292014>;
7244 +intel,processor-signature = <0x306a9>;
7245 +intel,checksum = <0x579ae07a>;
7246 +intel,loader-revision = <1>;
7247 +intel,processor-flags = <0x12>;
7248 +
7249 +/* The first 48-bytes are the public header which repeats the above data */
7250 +data = <
7251 + 0x01000000 0x1b000000 0x14202905 0xa9060300
7252 + 0x7ae09a57 0x01000000 0x12000000 0xd02f0000
7253 + 0x00300000 0x00000000 0x00000000 0x00000000
7254 + 0x00000000 0xa1000000 0x01000200 0x1b000000
7255 + 0x00000000 0x00000000 0x16051420 0x610b0000
7256 + 0x01000000 0xa9060300 0x00000000 0x00000000
7257 + 0x00000000 0x00000000 0x00000000 0x00000000
7258 + 0x00000000 0x00000000 0x00000000 0x00000000
7259 + 0x00000000 0x00000000 0x00000000 0x00000000
7260 + 0xc2b13ad8 0x6ce74fea 0xd364ad12 0xf6404a69
7261 + 0xc89041e4 0x217fa2f6 0x6ff6e43f 0x79cde4eb
7262 + 0xdb01345a 0xceecca42 0x5ee7d8b4 0x24afdbe6
7263 + 0x5fb36178 0xbc17d76b 0x31b7b923 0xc81aec82
7264 + 0x647b3320 0xf1db9653 0xff3b9759 0xe9c74b72
7265 + 0x3b193752 0xc147860b 0x160e0d6a 0x5bdb9dbf
7266 + 0x1ccce2ac 0x387670ad 0x2f106f05 0xf8607ea3
7267 + 0x42562576 0x30e086fb 0x409a06b8 0xf1957736
7268 + 0x5eb03f65 0xad147fab 0xe1a8e8b6 0x208d59d2
7269 + 0x683fba2e 0xf172b378 0xf8138dba 0x61e81d1f
7270 + 0xd551f997 0x28c79780 0x04f9db27 0xa80679b9
7271 + 0xaca4e7ff 0x6876944b 0x26d7dbc1 0x77f7dc2a
7272 + 0xf0bcb163 0x1b2a8e81 0x7b90aa49 0x8d5eaf2f
7273 + 0x522384ae 0xae7f7082 0x412ba10a 0x1ce1baa0
7274 + 0x478c29b4 0x9c09b4d2 0xf225f64f 0xd43026cd
7275 + 0x81098579 0x7df5db05 0xa5815bb0 0xc73ee756
7276 + 0x9738cb95 0xa5bd62e2 0x88e2c6b2 0x778e7fcb
7277 + 0xd3bdb872 0x9404403f 0x5be6ad63 0x71dc4abc
7278 + 0x11000000 0xd350099c 0x242d0996 0x1a4ddff8
7279 + 0xd7f1f03b 0x77590eb8 0x45c3ad79 0x3b714d23
7280 + 0xa85ba322 0x31851c5a 0x540fe0ce 0x38692bd6
7281 + 0xe3d9927b 0xb33428b5 0xcf0ac8d2 0xd3646604
7282 + 0xca88adc7 0x8afc41c8 0x721432b3 0x8fd19454
7283 + 0x26344e0d 0x3acf6c28 0xbda18c21 0x526d52ac
7284 + 0xf8d37e15 0x09305e37 0xf6907871 0xdb56cc21
7285 + 0x6802cccc 0x6693c8a3 0x0f4dbe32 0x0d924103
7286 + 0xee9242a7 0x5f867a13 0x2f65a246 0x6b35ad05
7287 + 0x39fb7da1 0xd69cb7d8 0x45869424 0x4768b466
7288 + 0xe3ace365 0xa85eea7c 0xa59939d9 0x2ae32fb9
7289 + 0xa20b1559 0x8865f3d3 0xbe02e023 0x4199575b
7290 + 0x0c43089a 0x0d57b287 0xd37544ad 0xcd4573b4
7291 + 0xa96b7485 0x05b67259 0x117414ca 0x2ba24577
7292 + 0x439db14d 0xf82c5833 0x54ec9806 0xf8282306
7293 + 0x1de7d3cf 0xf7a76dc2 0xcd897f60 0x0bb1decd
7294 + 0xae58efb0 0x743c07af 0x48adffb5 0x262260e7
7295 + 0xaa9fa071 0x9a9ef7c0 0x98e861eb 0x14a48871
7296 + 0x0b4c3292 0xad851820 0xe0f7f45c 0xd71366c5
7297 + 0xc63a2f01 0xd02f23c6 0x49645eb3 0x2365fe48
7298 + 0x44817f1f 0x576ee68e 0x396b6134 0xd9fc4857
7299 + 0x9a771368 0xda5f2693 0x6ad30ec2 0xc8d08171
7300 + 0xe40bcd42 0xf82291a8 0x3094a8b1 0xd3edffa3
7301 + 0x5d5fb5e6 0x93802a7e 0xdf0ff376 0x09ebeae6
7302 + 0x35091690 0xe938ec68 0xd203065b 0xcf2e8172
7303 + 0x85282b27 0xe59fb64d 0x4b2ad981 0xeb5dde75
7304 + 0xc07eac26 0xa78c969e 0x74165d84 0x61c4cfc8
7305 + 0x740452f3 0xe5f6435e 0xb712e157 0xac49215d
7306 + 0x5be5e61b 0x09f46a94 0xde5cd48d 0xe3ed6b11
7307 + 0x2e8173de 0xabb6759b 0x46ffc47e 0x0cd84607
7308 + 0x6046c26d 0x19356116 0xe1da098e 0x8e1bbe9f
7309 + 0x5c8d6c20 0xa17cfe55 0x101a1f91 0xd64aef70
7310 + 0xef2e7b34 0xbb428dc4 0xf2252a3d 0x8ab3f6c0
7311 + 0x161db4ef 0xfdbf4f9c 0xb5bf9f19 0x414ea8b5
7312 + 0xc3db5422 0xfc3934f2 0x635a8253 0x86260b8c
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7821 + 0x9e2c0ee5 0x78daabe2 0x2069e8eb 0x0e87f238
7822 + 0x0a928dda 0xc66e14b3 0x2a6c4031 0x73821630
7823 + 0x8b8c4a40 0x243702b7 0xded80901 0x5de34802
7824 + 0xea029b73 0x59a47771 0xe747d796 0xe80aea8d
7825 + 0x0bd01815 0x76fe1f68 0xa345fc34 0x73737383
7826 + 0x76753b6c 0x57dcba56 0xb11d6b21 0x81dc371e
7827 + 0x311f4ea0 0x3b4b2522 0xe8a66ef4 0x1932df0c
7828 + 0x9f3790d6 0x0d0478a3 0x7dd0a24b 0xeb581381
7829 + 0x6fe8ff06 0xe34c2d69 0x26842e15 0xe9a39562
7830 + 0x78f2d7d1 0x79ab33f5 0x197df69c 0x38a9a004
7831 + 0x9391dba9 0xfbb4b7c5 0xa97bb70f 0x0720b57b
7832 + 0xd9b26325 0x3ed1a3fc 0x11f5aba0 0x6e6a53ef
7833 + 0xe2ce236e 0x30994468 0x9d4369cd 0xcb6b5b5c
7834 + 0x61a0945c 0x090e7dea 0x5d9b676a 0xd474cb52
7835 + 0x8ebf1af3 0x35f2a70b 0x417d48a0 0x45062dcc
7836 + 0x841d8d90 0x30f8e590 0x1c935ad3 0x29313e0c
7837 + 0x46ecf673 0x4998b596 0x95f23529 0xf31bd581
7838 + 0x1b32045a 0x90432d28 0xa2a6c268 0xbf40fcae
7839 + 0x4104b314 0x02677221 0xa99231ac 0xe28abada
7840 + 0xd7d72a73 0xf1b2ce4c 0xf753f8be 0x9d7fc1c7
7841 + 0x9a0e7a7a 0xf04ccf32 0x58433f5f 0xab9a6d51
7842 + 0x71262b1c 0x48f84d91 0x897670bb 0x47dd10cb
7843 + 0xac7ef74d 0x78dc3e54 0x30b17eaa 0xc8f46618
7844 + 0xc636fe3b 0x86ac06e3 0xfb8edd16 0xed357170
7845 + 0xbfd34bf8 0xaeb9571a 0x4eec6a50 0xe881a1b7
7846 + 0x8a1cbbde 0xc6c077b6 0xaeda1441 0xf990296a
7847 + 0xc91e87d6 0xad0ca921 0x855537b6 0xfc0da57d
7848 + 0xf8427d87 0x9ece7413 0xc5d4b4c9 0x2fca7822
7849 + 0xa1888443 0xd3bf617e 0xab21ce7d 0xe63b5f53
7850 + 0x828501c5 0x81a39da9 0xb8cfb4c6 0x6b23b8dc
7851 + 0x853fe425 0xba262321 0x34f11b05 0x8044aea4
7852 + 0x67a3f99d 0x51e8afb7 0x04efcf27 0x7773f9ff
7853 + 0x8abceec1 0xd75d87a2 0x7e30d774 0xdd7a42f2
7854 + 0x2ca6ad73 0x27d4e62f 0xbc228d26 0x035a7713
7855 + 0x5dbcc13a 0x792a97da 0x56cf9fc2 0x5906fa3e
7856 + 0x97a3147c 0x85e59863 0x19ad1f49 0x1af659a8
7857 + 0xddc6a273 0xd254a195 0x44d83a00 0x3b7c5fa7
7858 + 0xcaf756aa 0x68ad08b9 0xfc57da12 0x3b278f24
7859 + 0xbd165574 0x3cf597ca 0xdeb872ba 0x543eb2f5
7860 + 0xfabc0d4f 0x0799c544 0x3d71181d 0x22c8a598
7861 + 0xb82840fc 0x1a198d19 0xf529a0ea 0x2f65bc24
7862 + 0xe979f99d 0xff8617b4 0x376e5abb 0xb095a03e
7863 + 0xa36b1107 0x2dacf004 0xe4c565e1 0xc96463cd
7864 + 0x3b495e2d 0x4a2c2cd7 0xa0053fc2 0x6c82a085
7865 + 0x6b801c45 0xc1481d77 0x6d95dc15 0x44dc8bf6
7866 + 0x3eed7d25 0x901a6b49 0x2797e953 0x502ad2c3
7867 + 0x8491c3f2 0x3ce059eb 0x992c1a76 0x6c56d2a2
7868 + 0xcf1878a7 0x10574487 0x5a2f85e6 0xf94e418e
7869 + 0x4c149aed 0x9381b5a3 0x79c90da4 0x635e696e
7870 + 0x243073ba 0x67504105 0xe82ac957 0xaccda7b3
7871 + 0x29bdd624 0xd0c1533c 0xbc080065 0x8d617329
7872 + 0x27e6f74a 0x31e87692 0x50a3857d 0xc5b1ec3f
7873 + 0x4f03be5f 0xa35fde17 0x537a59bb 0x793d1eb5
7874 + 0xc11a0588 0x067e5593 0x102532c3 0x4024b312
7875 + 0x32504cf4 0x4ddc0e9a 0xad5b1d24 0x41081874
7876 + 0xf94fced4 0x16f39da6 0x9bdfbe58 0xc5615db4
7877 + 0x1fdd769d 0x4278b52e 0x4525b8b6 0x7feed258
7878 + 0xe0b4348b 0xb4925ccc 0x5547cc88 0x3f7f5443
7879 + 0x5b8cc6d3 0xbe6a15cf 0x7308c088 0xde4219df
7880 + 0x4685593c 0xc4ae83a3 0xaea72ff0 0x403b0c08
7881 + 0xe533a9aa 0xed46be76 0x4390bcd0 0x683a9f3f
7882 + 0x338b5cd3 0x7cd59689 0x2eb11aec 0x74e91cfd
7883 + 0x7ae588aa 0x0eadf94e 0x30a6b42f 0x1965f165
7884 + 0xd96de54b 0x06c85abf 0x1bbc0ab8 0x79f3ddd0
7885 + 0x871fd58d 0x498dd69d 0x9197dd0e 0x6cbb3a4f
7886 + 0x8a1f2a01 0x0d9cf747 0x80e66655 0x770d2b25
7887 + 0x567bd3eb 0x59583c5a 0x58afeddd 0x9296d0e3
7888 + 0xcf5af62c 0xf48b4c78 0x746f657e 0xe543b903
7889 + 0x24603809 0xd1bceeea 0x16d04950 0x2a7c754b
7890 + 0x4ea8bb99 0x9daecb97 0x3045b9a9 0x4a3e84d9
7891 + 0x5487e79f 0xd6145e57 0xc3b17f6f 0x14448bb6
7892 + 0x8e8529f5 0xf895acb9 0x6605c0f0 0x52d00ca9
7893 + 0xabf6e3e9 0x8f36e307 0xa7a15442 0x55144801
7894 + 0x69b028b2 0x8ab3b912 0xb493f80e 0x2dc9fdfa
7895 + 0x1b091fbf 0x1bce6b31 0x79eb414e 0xe5f86ea0
7896 + 0x39ef7dbd 0x2f86faf0 0xec366923 0xe770c7be
7897 + 0x74e4aa61 0xef3b9da0 0xd77bd8be 0xfd13d3cb
7898 + 0x4e8023c6 0x3d993904 0xfcb2f700 0xa14b753b
7899 + 0xde16c1c3 0x983c5a86 0x52ba5e61 0x1d67b044
7900 + 0x0f9a302d 0x2f13b653 0x769cbb97 0xea3e1cbd
7901 + 0x5791778c 0x540fcff1 0x5e6c53f2 0xc9cbac0f
7902 + 0x40ceadf0 0x648713d3 0xb5347ada 0xfe280079
7903 + 0xb8389f3f 0x5a6be26a 0x8e683d28 0x6a3e8e3a
7904 + 0x97ecac7a 0x70b648f1 0xe4eca20e 0x088cd0b4
7905 + 0xbad30405 0x0f77e382 0x673cdf65 0x438af1f0
7906 + 0x0b4f4eea 0xf0cc34e9 0x374a3c04 0x4370d27d
7907 + 0xc3e1e84d 0x141205c2 0xfa831e8d 0x32f2f10a
7908 + 0x77899366 0xc9d07590 0x9b6f2286 0xcac96a03
7909 + 0xf822808b 0x265606cd 0xbeef275d 0x73415b15
7910 + 0x4c87250e 0xf95a8c8a 0xdc8d6166 0x68522e63
7911 + 0xb9becc14 0x7b5f20be 0x3d158dab 0xa73b1716
7912 + 0x3b2cac15 0xf0498939 0xb60653bf 0x33fafc0e
7913 + 0x3b416955 0x3addca50 0x16ab21cf 0xd18cbdb6
7914 + 0x3b29b87b 0xa6fb7e4b 0x6634147f 0x44283b1e
7915 + 0x430ae726 0xa907ab82 0x2baa6706 0x621d2390
7916 + 0x15944559 0x2516c807 0x7d1eeb61 0xe2714121
7917 + 0x288d3998 0x47713cbb 0xa1ce3c1e 0x0c29b6dd
7918 + 0x9923131c 0x2dd19cfa 0x83d0ece5 0x78474c7b
7919 + 0x92dee4f0 0xba5cb0f7 0x780c1d41 0x50da5a89
7920 + 0xe303cebb 0xe8d5a2bd 0x7d6269a9 0xb75484f1
7921 + 0x33ee8186 0x085b7657 0x7b1c7863 0xdb1a43ce
7922 + 0x3d0c4bf0 0x302c1292 0x81e42216 0xee1f2c9d
7923 + 0x822451ab 0xcefd8067 0x8330dc41 0x14492542
7924 + 0xf038f54d 0x90a1abf9 0xc3067a77 0x40d9a42c
7925 + 0x127285c1 0x80ad15ff 0xaf4854e2 0xa47874f4
7926 + 0x2ed59760 0x67252c6a 0xe2830f38 0x8150c00c
7927 + 0x16f61cca 0x1331f815 0x2d832d17 0x163c6010
7928 + 0x69464e2f 0x99940411 0xbce5e85f 0x43d39ef2
7929 + 0x9b7224dc 0x28652b6d 0x331a7632 0x127f669e
7930 + 0x44a034ad 0xe95d2cec 0x3d83fefb 0xfa6d40a2
7931 + 0x9b535bf4 0xc83411ce 0xd661655b 0x64bcd8d2
7932 + 0xd99e1570 0x7dc4d877 0x9756b210 0x7623dc0d
7933 + 0x484dd33f 0xe7bca204 0xa06efbc5 0xa358c03f
7934 + 0x362cb282 0xe40e6d04 0x17ab9f5e 0x79a71a09
7935 + 0x804bf1a9 0x6bca7d73 0x5504a4ff 0xd3946f75
7936 + 0x18b0b9d4 0xd85993cc 0x94d000a5 0x8dda1609
7937 + 0x30afb8f6 0xb3c99c3c 0x7686d59d 0x68b719db
7938 + 0xdc7b3edb 0xedb76012 0xbfa0ba3b 0x280b829d
7939 + 0x72fcf1aa 0xe3d8f83c 0x088a57cf 0x95156217
7940 + 0x3306eb47 0x1d09cf54 0x1391876f 0x5b15ecde
7941 + 0xb46104e1 0x8d8f2593 0x90ee50cc 0x78dad4b2
7942 + 0xfd96daee 0xdbf15e95 0xfc859faa 0xdb4422a5
7943 + 0xa00eeab6 0x525232c6 0x9b665668 0x8a70518b
7944 + 0xbb27f7ac 0xb066b096 0x25754db6 0xe8c7d748
7945 + 0xd4e8d361 0x380dd246 0x9bdf15e6 0x6823c660
7946 + 0x5d408fe7 0xe59a5a89 0x1eb7523b 0x4997158e
7947 + 0xfa6214d2 0x03b35025 0x9aeff33c 0x20a38aad
7948 + 0x522f79cd 0x4141f19c 0xc58cd2bd 0xc816da37
7949 + 0x62c6f8d9 0xc15ea9f4 0x138d1f45 0xd36cef03
7950 + 0x88183bd6 0xe0de9036 0xefcbe8fc 0x5ebdce26
7951 + 0x9e83b01b 0xd35f6747 0x552951f1 0x4e20dd66
7952 + 0x419702b1 0x45446e7c 0x7ce5616b 0x6152e3a8
7953 + 0xffd572e1 0x4fab25b0 0x07563b80 0x98720ee7
7954 + 0x176d29bf 0x21cbd730 0xbde74431 0x09a8cce2
7955 + 0xc15e548e 0xe6a92b4b 0x14f17e74 0x75f7817b
7956 + 0x592143e8 0x113dbd25 0x5f7d7160 0xbdd8b1e0
7957 + 0x6ce045e5 0x53b27b2d 0x371c8aa8 0xa4da8be0
7958 + 0xf1f6df4e 0x9519bac4 0x6d6169cf 0x7846253f
7959 + 0xccb95d95 0x6ad11a98 0x4a3bd21d 0x5389f44c
7960 + 0x7c07ef3a 0xb983ca57 0xcf7f290d 0x4ec516f1
7961 + 0xa7711e70 0x818d45a9 0x49db6441 0xd032fc2a
7962 + 0x657df4d3 0xe37e6809 0x459a22da 0x41df8aa5
7963 + 0x462108a6 0x65177d27 0x1ddffa9f 0x7fa6631b
7964 + 0xdd7a414c 0x6351f0d1 0x1b38a419 0x6b529c8e
7965 + 0x167745e4 0xcac35897 0x3d7bf419 0xd59ed67a
7966 + 0x6486b2c9 0x9ae4fc90 0x8f608920 0xd35335c0
7967 + 0x8f113cba 0x0fcc11a1 0xdc180fbf 0x57a99319
7968 + 0x2c54185f 0x764c18d0 0x4f84b111 0x30a11040
7969 + 0xd15620af 0x496af145 0x263b2de2 0x3ff103dd
7970 + 0x38484dac 0xf143a3bc 0xb62c0de6 0xb122c545
7971 + 0x72f10466 0x63728442 0xee0117c9 0x2309f14b
7972 + 0x4ccdd5de 0x37ae022d 0x2ee7f050 0xf2aa9af6
7973 + 0xcd314a20 0x86954941 0x97215303 0xcd7e1687
7974 + 0x1dab6672 0x1c920209 0x41102dae 0x8b21c8ab
7975 + 0x6f70b04b 0x2988b209 0x86e6f033 0x5eb91718
7976 + 0x925b3c40 0xdcad0288 0x0ee98331 0xc3096ceb
7977 + 0x9fa04740 0x3ce3fb23 0x90d75cbd 0xeab21768
7978 + 0xaca5db0a 0x1c440578 0x762cb728 0x315a699f
7979 + 0xcd2b6490 0x11e3e267 0xa10d1bbc 0x23ac26d3
7980 + 0xc0c7c268 0x37ecf7ac 0x28de6fe5 0x6fb8e3e8
7981 + 0x583d1131 0x8370812a 0x3afd5d58 0x4569a06e
7982 + 0xf27ad86f 0x0db6a631 0x9add5128 0x1748c9fd
7983 + 0xc46e3c57 0x4c0df93e 0xc595c544 0x397f7e7e
7984 + 0x241f4086 0x7d7ed51b 0x56027473 0x656a6110
7985 + 0x970a8011 0xf9c7beb5 0xc6cb9957 0xb7426461
7986 + 0x62d3d89d 0xf99d48ca 0x3e4d4a88 0x9f751b71
7987 + 0xfa020205 0xa3124337 0x59935869 0x98c58314
7988 + 0xff7c4385 0x69191265 0xaf85ebb9 0xe434cda2
7989 + 0xb1ad3e0e 0x221d32e1 0x022d73a0 0xd676ce06
7990 + 0xab7f0c21 0x915c2444 0xf5bdaba2 0x74e4e789
7991 + 0x11ff0d95 0x58c53feb 0xa54eb847 0x9af982ae
7992 + 0x8d721596 0x73510fe4 0x95e3bd19 0xd82f8359
7993 + 0xc09cdd5b 0xc07f57a4 0xbece605b 0xa8a43c5b
7994 + 0x0acbeb6d 0x3c5cd8ce 0xb631050d 0xd558c921
7995 + 0xcb5054c2 0xefb06252 0x40d2e2cc 0x14ffe6ff
7996 + 0x761001a9 0xad64e7a5 0xb55618b4 0x2a40a1fc
7997 + 0x2cbe6d40 0x2bc18fc1 0x196e7092 0x3c137791
7998 + 0xa799eb23 0x1156feb9 0xd55d7ed1 0x0149c315
7999 + 0xae77081f 0xfe724690 0x55ed2fd7 0x04b18cd7
8000 + 0x691583f4 0xb1be4fde 0x19ae1cf7 0x3250140b
8001 + 0x35daeeb2 0xc9459a84 0xea2c19e1 0x57f8c9cb
8002 + 0xe05e07a4 0xcc77a363 0x43afd702 0x48305862
8003 + 0x6c4b459f 0x66ed6178 0x26be9f81 0xeac41ee5
8004 + 0xbe5e2e6b 0x177f9068 0xede56c48 0x438b3811
8005 + 0xd5bd7ee4 0xc027d1a8 0xc1c0f725 0x48d4d4eb
8006 + 0x6ffa28d5 0xbd6ac9eb 0xd497781d 0x24d3a154
8007 + 0x409bb5c0 0x8079bf76 0x90a522dc 0x19bf7033
8008 + 0x1a529b6e 0xe5207e4d 0x3d49b7bc 0x3eca6d54
8009 + 0xa37681a6 0xaa9a62e4 0xe54aa1e1 0xb91e7157
8010 + 0x8cce8f65 0xbcbbd62c 0x7fa477b5 0x44f46b50
8011 + 0x54263fcf 0x529cbb5d 0x8923e390 0x0778d6d7
8012 + 0x0cc0503f 0x02c374ce 0xb89c3e5c 0x25b1b353
8013 + 0xb227cb2d 0x44108698 0x5e5968c2 0x82c48632
8014 + 0x0b8f4209 0x1a241879 0x9edca6f1 0xa1fa51ab
8015 + 0x206db0c6 0xbfbbbe98 0xa71c91f6 0xa1b28056
8016 + 0xb8bfaaa9 0xa5914f75 0x77d26574 0xacfd459d
8017 + 0x77f7cab2 0x249ebf26 0xef902bdd 0x77f6e48d
8018 + 0x82497035 0x93333a9d 0x34ea9953 0x8f08d41c
8019 + >;
8020 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-coreboot/gpio.h u-boot/arch/x86/include/asm/arch-coreboot/gpio.h
8021 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-coreboot/gpio.h 2014-12-08 22:35:08.000000000 +0100
8022 +++ u-boot/arch/x86/include/asm/arch-coreboot/gpio.h 2015-01-01 17:34:32.253503252 +0100
8023 @@ -7,4 +7,7 @@
8024 #ifndef _X86_ARCH_GPIO_H_
8025 #define _X86_ARCH_GPIO_H_
8026
8027 +/* Where in config space is the register that points to the GPIO registers? */
8028 +#define PCI_CFG_GPIOBASE 0x48
8029 +
8030 #endif /* _X86_ARCH_GPIO_H_ */
8031 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-ivybridge/gpio.h u-boot/arch/x86/include/asm/arch-ivybridge/gpio.h
8032 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-ivybridge/gpio.h 2014-12-08 22:35:08.000000000 +0100
8033 +++ u-boot/arch/x86/include/asm/arch-ivybridge/gpio.h 2015-01-01 17:34:32.253503252 +0100
8034 @@ -7,4 +7,7 @@
8035 #ifndef _X86_ARCH_GPIO_H_
8036 #define _X86_ARCH_GPIO_H_
8037
8038 +/* Where in config space is the register that points to the GPIO registers? */
8039 +#define PCI_CFG_GPIOBASE 0x48
8040 +
8041 #endif /* _X86_ARCH_GPIO_H_ */
8042 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-ivybridge/pei_data.h u-boot/arch/x86/include/asm/arch-ivybridge/pei_data.h
8043 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-ivybridge/pei_data.h 2014-12-08 22:35:08.000000000 +0100
8044 +++ u-boot/arch/x86/include/asm/arch-ivybridge/pei_data.h 2015-01-01 17:34:32.253503252 +0100
8045 @@ -7,6 +7,8 @@
8046 #ifndef ASM_ARCH_PEI_DATA_H
8047 #define ASM_ARCH_PEI_DATA_H
8048
8049 +#include <linux/linkage.h>
8050 +
8051 struct pch_usb3_controller_settings {
8052 /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */
8053 uint16_t mode;
8054 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h
8055 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h 1970-01-01 01:00:00.000000000 +0100
8056 +++ u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_api.h 2015-01-01 17:34:32.253503252 +0100
8057 @@ -0,0 +1,55 @@
8058 +/*
8059 + * Copyright (C) 2013, Intel Corporation
8060 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
8061 + *
8062 + * SPDX-License-Identifier: Intel
8063 + */
8064 +
8065 +#ifndef __FSP_API_H__
8066 +#define __FSP_API_H__
8067 +
8068 +/*
8069 + * FspInit continuation function prototype.
8070 + * Control will be returned to this callback function after FspInit API call.
8071 + */
8072 +typedef void (*fsp_continuation_f)(u32 status, void *hob_list);
8073 +
8074 +struct fsp_init_params {
8075 + /* Non-volatile storage buffer pointer */
8076 + void *nvs_buf;
8077 + /* Runtime buffer pointer */
8078 + void *rt_buf;
8079 + /* Continuation function address */
8080 + fsp_continuation_f continuation;
8081 +};
8082 +
8083 +struct common_buf {
8084 + /*
8085 + * Stack top pointer used by the bootloader. The new stack frame will be
8086 + * set up at this location after FspInit API call.
8087 + */
8088 + u32 *stack_top;
8089 + u32 boot_mode; /* Current system boot mode */
8090 + void *upd_data; /* User platform configuraiton data region */
8091 + u32 reserved[7]; /* Reserved */
8092 +};
8093 +
8094 +enum fsp_phase {
8095 + /* Notification code for post PCI enuermation */
8096 + INIT_PHASE_PCI = 0x20,
8097 + /* Notification code before transfering control to the payload */
8098 + INIT_PHASE_BOOT = 0x40
8099 +};
8100 +
8101 +struct fsp_notify_params {
8102 + /* Notification phase used for NotifyPhase API */
8103 + enum fsp_phase phase;
8104 +};
8105 +
8106 +/* FspInit API function prototype */
8107 +typedef u32 (*fsp_init_f)(struct fsp_init_params *params);
8108 +
8109 +/* FspNotify API function prototype */
8110 +typedef u32 (*fsp_notify_f)(struct fsp_notify_params *params);
8111 +
8112 +#endif
8113 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h
8114 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h 1970-01-01 01:00:00.000000000 +0100
8115 +++ u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_bootmode.h 2015-01-01 17:34:32.253503252 +0100
8116 @@ -0,0 +1,24 @@
8117 +/*
8118 + * Copyright (C) 2013, Intel Corporation
8119 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
8120 + *
8121 + * SPDX-License-Identifier: Intel
8122 + */
8123 +
8124 +#ifndef __FSP_BOOT_MODE_H__
8125 +#define __FSP_BOOT_MODE_H__
8126 +
8127 +/* 0x21 - 0xf..f are reserved */
8128 +#define BOOT_FULL_CONFIG 0x00
8129 +#define BOOT_MINIMAL_CONFIG 0x01
8130 +#define BOOT_NO_CONFIG_CHANGES 0x02
8131 +#define BOOT_FULL_CONFIG_PLUS_DIAG 0x03
8132 +#define BOOT_DEFAULT_SETTINGS 0x04
8133 +#define BOOT_ON_S4_RESUME 0x05
8134 +#define BOOT_ON_S5_RESUME 0x06
8135 +#define BOOT_ON_S2_RESUME 0x10
8136 +#define BOOT_ON_S3_RESUME 0x11
8137 +#define BOOT_ON_FLASH_UPDATE 0x12
8138 +#define BOOT_IN_RECOVERY_MODE 0x20
8139 +
8140 +#endif
8141 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h
8142 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h 1970-01-01 01:00:00.000000000 +0100
8143 +++ u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_ffs.h 2015-01-01 17:34:32.253503252 +0100
8144 @@ -0,0 +1,154 @@
8145 +/*
8146 + * Copyright (C) 2013, Intel Corporation
8147 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
8148 + *
8149 + * SPDX-License-Identifier: Intel
8150 + */
8151 +
8152 +#ifndef __FSP_FFS_H__
8153 +#define __FSP_FFS_H__
8154 +
8155 +/* Used to verify the integrity of the file */
8156 +union __packed ffs_integrity {
8157 + struct {
8158 + /*
8159 + * The IntegrityCheck.checksum.header field is an 8-bit
8160 + * checksum of the file header. The State and
8161 + * IntegrityCheck.checksum.file fields are assumed to be zero
8162 + * and the checksum is calculated such that the entire header
8163 + * sums to zero.
8164 + */
8165 + u8 header;
8166 + /*
8167 + * If the FFS_ATTRIB_CHECKSUM (see definition below) bit of
8168 + * the Attributes field is set to one, the
8169 + * IntegrityCheck.checksum.file field is an 8-bit checksum of
8170 + * the file data. If the FFS_ATTRIB_CHECKSUM bit of the
8171 + * Attributes field is cleared to zero, the
8172 + * IntegrityCheck.checksum.file field must be initialized with
8173 + * a value of 0xAA. The IntegrityCheck.checksum.file field is
8174 + * valid any time the EFI_FILE_DATA_VALID bit is set in the
8175 + * State field.
8176 + */
8177 + u8 file;
8178 + } checksum;
8179 +
8180 + /* This is the full 16 bits of the IntegrityCheck field */
8181 + u16 checksum16;
8182 +};
8183 +
8184 +/*
8185 + * Each file begins with the header that describe the
8186 + * contents and state of the files.
8187 + */
8188 +struct __packed ffs_file_header {
8189 + /*
8190 + * This GUID is the file name.
8191 + * It is used to uniquely identify the file.
8192 + */
8193 + struct efi_guid name;
8194 + /* Used to verify the integrity of the file */
8195 + union ffs_integrity integrity;
8196 + /* Identifies the type of file */
8197 + u8 type;
8198 + /* Declares various file attribute bits */
8199 + u8 attr;
8200 + /* The length of the file in bytes, including the FFS header */
8201 + u8 size[3];
8202 + /*
8203 + * Used to track the state of the file throughout the life of
8204 + * the file from creation to deletion.
8205 + */
8206 + u8 state;
8207 +};
8208 +
8209 +struct __packed ffs_file_header2 {
8210 + /*
8211 + * This GUID is the file name. It is used to uniquely identify the file.
8212 + * There may be only one instance of a file with the file name GUID of
8213 + * Name in any given firmware volume, except if the file type is
8214 + * EFI_FV_FILE_TYPE_FFS_PAD.
8215 + */
8216 + struct efi_guid name;
8217 + /* Used to verify the integrity of the file */
8218 + union ffs_integrity integrity;
8219 + /* Identifies the type of file */
8220 + u8 type;
8221 + /* Declares various file attribute bits */
8222 + u8 attr;
8223 + /*
8224 + * The length of the file in bytes, including the FFS header.
8225 + * The length of the file data is either
8226 + * (size - sizeof(struct ffs_file_header)). This calculation means a
8227 + * zero-length file has a size of 24 bytes, which is
8228 + * sizeof(struct ffs_file_header). Size is not required to be a
8229 + * multiple of 8 bytes. Given a file F, the next file header is located
8230 + * at the next 8-byte aligned firmware volume offset following the last
8231 + * byte of the file F.
8232 + */
8233 + u8 size[3];
8234 + /*
8235 + * Used to track the state of the file throughout the life of
8236 + * the file from creation to deletion.
8237 + */
8238 + u8 state;
8239 + /*
8240 + * If FFS_ATTRIB_LARGE_FILE is set in attr, then ext_size exists
8241 + * and size must be set to zero.
8242 + * If FFS_ATTRIB_LARGE_FILE is not set then
8243 + * struct ffs_file_header is used.
8244 + */
8245 + u32 ext_size;
8246 +};
8247 +
8248 +/*
8249 + * Pseudo type. It is used as a wild card when retrieving sections.
8250 + * The section type EFI_SECTION_ALL matches all section types.
8251 + */
8252 +#define EFI_SECTION_ALL 0x00
8253 +
8254 +/* Encapsulation section Type values */
8255 +#define EFI_SECTION_COMPRESSION 0x01
8256 +#define EFI_SECTION_GUID_DEFINED 0x02
8257 +#define EFI_SECTION_DISPOSABLE 0x03
8258 +
8259 +/* Leaf section Type values */
8260 +#define EFI_SECTION_PE32 0x10
8261 +#define EFI_SECTION_PIC 0x11
8262 +#define EFI_SECTION_TE 0x12
8263 +#define EFI_SECTION_DXE_DEPEX 0x13
8264 +#define EFI_SECTION_VERSION 0x14
8265 +#define EFI_SECTION_USER_INTERFACE 0x15
8266 +#define EFI_SECTION_COMPATIBILITY16 0x16
8267 +#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17
8268 +#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18
8269 +#define EFI_SECTION_RAW 0x19
8270 +#define EFI_SECTION_PEI_DEPEX 0x1B
8271 +#define EFI_SECTION_SMM_DEPEX 0x1C
8272 +
8273 +/* Common section header */
8274 +struct __packed raw_section {
8275 + /*
8276 + * A 24-bit unsigned integer that contains the total size of
8277 + * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
8278 + */
8279 + u8 size[3];
8280 + u8 type;
8281 +};
8282 +
8283 +struct __packed raw_section2 {
8284 + /*
8285 + * A 24-bit unsigned integer that contains the total size of
8286 + * the section in bytes, including the EFI_COMMON_SECTION_HEADER.
8287 + */
8288 + u8 size[3];
8289 + u8 type;
8290 + /*
8291 + * If size is 0xFFFFFF, then ext_size contains the size of
8292 + * the section. If size is not equal to 0xFFFFFF, then this
8293 + * field does not exist.
8294 + */
8295 + u32 ext_size;
8296 +};
8297 +
8298 +#endif
8299 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h
8300 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h 1970-01-01 01:00:00.000000000 +0100
8301 +++ u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_fv.h 2015-01-01 17:34:32.253503252 +0100
8302 @@ -0,0 +1,137 @@
8303 +/*
8304 + * Copyright (C) 2013, Intel Corporation
8305 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
8306 + *
8307 + * SPDX-License-Identifier: Intel
8308 + */
8309 +
8310 +#ifndef __FSP_FV___
8311 +#define __FSP_FV___
8312 +
8313 +/* Value of EFI_FV_FILE_ATTRIBUTES */
8314 +#define EFI_FV_FILE_ATTR_ALIGNMENT 0x0000001F
8315 +#define EFI_FV_FILE_ATTR_FIXED 0x00000100
8316 +#define EFI_FV_FILE_ATTR_MEMORY_MAPPED 0x00000200
8317 +
8318 +/* Attributes bit definitions */
8319 +#define EFI_FVB2_READ_DISABLED_CAP 0x00000001
8320 +#define EFI_FVB2_READ_ENABLED_CAP 0x00000002
8321 +#define EFI_FVB2_READ_STATUS 0x00000004
8322 +#define EFI_FVB2_WRITE_DISABLED_CAP 0x00000008
8323 +#define EFI_FVB2_WRITE_ENABLED_CAP 0x00000010
8324 +#define EFI_FVB2_WRITE_STATUS 0x00000020
8325 +#define EFI_FVB2_LOCK_CAP 0x00000040
8326 +#define EFI_FVB2_LOCK_STATUS 0x00000080
8327 +#define EFI_FVB2_STICKY_WRITE 0x00000200
8328 +#define EFI_FVB2_MEMORY_MAPPED 0x00000400
8329 +#define EFI_FVB2_ERASE_POLARITY 0x00000800
8330 +#define EFI_FVB2_READ_LOCK_CAP 0x00001000
8331 +#define EFI_FVB2_READ_LOCK_STATUS 0x00002000
8332 +#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000
8333 +#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000
8334 +#define EFI_FVB2_ALIGNMENT 0x001F0000
8335 +#define EFI_FVB2_ALIGNMENT_1 0x00000000
8336 +#define EFI_FVB2_ALIGNMENT_2 0x00010000
8337 +#define EFI_FVB2_ALIGNMENT_4 0x00020000
8338 +#define EFI_FVB2_ALIGNMENT_8 0x00030000
8339 +#define EFI_FVB2_ALIGNMENT_16 0x00040000
8340 +#define EFI_FVB2_ALIGNMENT_32 0x00050000
8341 +#define EFI_FVB2_ALIGNMENT_64 0x00060000
8342 +#define EFI_FVB2_ALIGNMENT_128 0x00070000
8343 +#define EFI_FVB2_ALIGNMENT_256 0x00080000
8344 +#define EFI_FVB2_ALIGNMENT_512 0x00090000
8345 +#define EFI_FVB2_ALIGNMENT_1K 0x000A0000
8346 +#define EFI_FVB2_ALIGNMENT_2K 0x000B0000
8347 +#define EFI_FVB2_ALIGNMENT_4K 0x000C0000
8348 +#define EFI_FVB2_ALIGNMENT_8K 0x000D0000
8349 +#define EFI_FVB2_ALIGNMENT_16K 0x000E0000
8350 +#define EFI_FVB2_ALIGNMENT_32K 0x000F0000
8351 +#define EFI_FVB2_ALIGNMENT_64K 0x00100000
8352 +#define EFI_FVB2_ALIGNMENT_128K 0x00110000
8353 +#define EFI_FVB2_ALIGNMENT_256K 0x00120000
8354 +#define EFI_FVB2_ALIGNMENT_512K 0x00130000
8355 +#define EFI_FVB2_ALIGNMENT_1M 0x00140000
8356 +#define EFI_FVB2_ALIGNMENT_2M 0x00150000
8357 +#define EFI_FVB2_ALIGNMENT_4M 0x00160000
8358 +#define EFI_FVB2_ALIGNMENT_8M 0x00170000
8359 +#define EFI_FVB2_ALIGNMENT_16M 0x00180000
8360 +#define EFI_FVB2_ALIGNMENT_32M 0x00190000
8361 +#define EFI_FVB2_ALIGNMENT_64M 0x001A0000
8362 +#define EFI_FVB2_ALIGNMENT_128M 0x001B0000
8363 +#define EFI_FVB2_ALIGNMENT_256M 0x001C0000
8364 +#define EFI_FVB2_ALIGNMENT_512M 0x001D0000
8365 +#define EFI_FVB2_ALIGNMENT_1G 0x001E0000
8366 +#define EFI_FVB2_ALIGNMENT_2G 0x001F0000
8367 +
8368 +struct fv_blkmap_entry {
8369 + /* The number of sequential blocks which are of the same size */
8370 + u32 num_blocks;
8371 + /* The size of the blocks */
8372 + u32 length;
8373 +};
8374 +
8375 +/* Describes the features and layout of the firmware volume */
8376 +struct fv_header {
8377 + /*
8378 + * The first 16 bytes are reserved to allow for the reset vector of
8379 + * processors whose reset vector is at address 0.
8380 + */
8381 + u8 zero_vec[16];
8382 + /*
8383 + * Declares the file system with which the firmware volume
8384 + * is formatted.
8385 + */
8386 + struct efi_guid fs_guid;
8387 + /*
8388 + * Length in bytes of the complete firmware volume, including
8389 + * the header.
8390 + */
8391 + u64 fv_len;
8392 + /* Set to EFI_FVH_SIGNATURE */
8393 + u32 sign;
8394 + /*
8395 + * Declares capabilities and power-on defaults for the firmware
8396 + * volume.
8397 + */
8398 + u32 attr;
8399 + /* Length in bytes of the complete firmware volume header */
8400 + u16 hdr_len;
8401 + /*
8402 + * A 16-bit checksum of the firmware volume header.
8403 + * A valid header sums to zero.
8404 + */
8405 + u16 checksum;
8406 + /*
8407 + * Offset, relative to the start of the header, of the extended
8408 + * header (EFI_FIRMWARE_VOLUME_EXT_HEADER) or zero if there is
8409 + * no extended header.
8410 + */
8411 + u16 ext_hdr_off;
8412 + /* This field must always be set to zero */
8413 + u8 reserved[1];
8414 + /*
8415 + * Set to 2. Future versions of this specification may define new
8416 + * header fields and will increment the Revision field accordingly.
8417 + */
8418 + u8 rev;
8419 + /*
8420 + * An array of run-length encoded FvBlockMapEntry structures.
8421 + * The array is terminated with an entry of {0,0}.
8422 + */
8423 + struct fv_blkmap_entry block_map[1];
8424 +};
8425 +
8426 +#define EFI_FVH_SIGNATURE SIGNATURE_32('_', 'F', 'V', 'H')
8427 +
8428 +/* Firmware Volume Header Revision definition */
8429 +#define EFI_FVH_REVISION 0x02
8430 +
8431 +/* Extension header pointed by ExtHeaderOffset of volume header */
8432 +struct fv_ext_header {
8433 + /* firmware volume name */
8434 + struct efi_guid fv_name;
8435 + /* Size of the rest of the extension header including this structure */
8436 + u32 ext_hdr_size;
8437 +};
8438 +
8439 +#endif
8440 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h
8441 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h 1970-01-01 01:00:00.000000000 +0100
8442 +++ u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_hob.h 2015-01-01 17:34:32.253503252 +0100
8443 @@ -0,0 +1,340 @@
8444 +/*
8445 + * Copyright (C) 2013, Intel Corporation
8446 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
8447 + *
8448 + * SPDX-License-Identifier: Intel
8449 + */
8450 +
8451 +#ifndef __FSP_HOB_H__
8452 +#define __FSP_HOB_H__
8453 +
8454 +/* Type of HOB Header */
8455 +#define HOB_TYPE_MEM_ALLOC 0x0002
8456 +#define HOB_TYPE_RES_DESC 0x0003
8457 +#define HOB_TYPE_GUID_EXT 0x0004
8458 +#define HOB_TYPE_UNUSED 0xFFFE
8459 +#define HOB_TYPE_EOH 0xFFFF
8460 +
8461 +/*
8462 + * Describes the format and size of the data inside the HOB.
8463 + * All HOBs must contain this generic HOB header.
8464 + */
8465 +struct hob_header {
8466 + u16 type; /* HOB type */
8467 + u16 len; /* HOB length */
8468 + u32 reserved; /* always zero */
8469 +};
8470 +
8471 +/* Enumeration of memory types introduced in UEFI */
8472 +enum efi_mem_type {
8473 + EFI_RESERVED_MEMORY_TYPE,
8474 + /*
8475 + * The code portions of a loaded application.
8476 + * (Note that UEFI OS loaders are UEFI applications.)
8477 + */
8478 + EFI_LOADER_CODE,
8479 + /*
8480 + * The data portions of a loaded application and
8481 + * the default data allocation type used by an application
8482 + * to allocate pool memory.
8483 + */
8484 + EFI_LOADER_DATA,
8485 + /* The code portions of a loaded Boot Services Driver */
8486 + EFI_BOOT_SERVICES_CODE,
8487 + /*
8488 + * The data portions of a loaded Boot Serves Driver and
8489 + * the default data allocation type used by a Boot Services
8490 + * Driver to allocate pool memory.
8491 + */
8492 + EFI_BOOT_SERVICES_DATA,
8493 + /* The code portions of a loaded Runtime Services Driver */
8494 + EFI_RUNTIME_SERVICES_CODE,
8495 + /*
8496 + * The data portions of a loaded Runtime Services Driver and
8497 + * the default data allocation type used by a Runtime Services
8498 + * Driver to allocate pool memory.
8499 + */
8500 + EFI_RUNTIME_SERVICES_DATA,
8501 + /* Free (unallocated) memory */
8502 + EFI_CONVENTIONAL_MEMORY,
8503 + /* Memory in which errors have been detected */
8504 + EFI_UNUSABLE_MEMORY,
8505 + /* Memory that holds the ACPI tables */
8506 + EFI_ACPI_RECLAIM_MEMORY,
8507 + /* Address space reserved for use by the firmware */
8508 + EFI_ACPI_MEMORY_NVS,
8509 + /*
8510 + * Used by system firmware to request that a memory-mapped IO region
8511 + * be mapped by the OS to a virtual address so it can be accessed by
8512 + * EFI runtime services.
8513 + */
8514 + EFI_MMAP_IO,
8515 + /*
8516 + * System memory-mapped IO region that is used to translate
8517 + * memory cycles to IO cycles by the processor.
8518 + */
8519 + EFI_MMAP_IO_PORT,
8520 + /*
8521 + * Address space reserved by the firmware for code that is
8522 + * part of the processor.
8523 + */
8524 + EFI_PAL_CODE,
8525 + EFI_MAX_MEMORY_TYPE
8526 +};
8527 +
8528 +/*
8529 + * Describes all memory ranges used during the HOB producer phase that
8530 + * exist outside the HOB list. This HOB type describes how memory is used,
8531 + * not the physical attributes of memory.
8532 + */
8533 +struct hob_mem_alloc {
8534 + struct hob_header hdr;
8535 + /*
8536 + * A GUID that defines the memory allocation region's type and purpose,
8537 + * as well as other fields within the memory allocation HOB. This GUID
8538 + * is used to define the additional data within the HOB that may be
8539 + * present for the memory allocation HOB. Type efi_guid is defined in
8540 + * InstallProtocolInterface() in the UEFI 2.0 specification.
8541 + */
8542 + struct efi_guid name;
8543 + /*
8544 + * The base address of memory allocated by this HOB.
8545 + * Type phys_addr_t is defined in AllocatePages() in the UEFI 2.0
8546 + * specification.
8547 + */
8548 + phys_addr_t mem_base;
8549 + /* The length in bytes of memory allocated by this HOB */
8550 + phys_size_t mem_len;
8551 + /*
8552 + * Defines the type of memory allocated by this HOB.
8553 + * The memory type definition follows the EFI_MEMORY_TYPE definition.
8554 + * Type EFI_MEMORY_TYPE is defined in AllocatePages() in the UEFI 2.0
8555 + * specification.
8556 + */
8557 + enum efi_mem_type mem_type;
8558 + /* padding */
8559 + u8 reserved[4];
8560 +};
8561 +
8562 +/* Value of ResourceType in HOB_RES_DESC */
8563 +#define RES_SYS_MEM 0x00000000
8564 +#define RES_MMAP_IO 0x00000001
8565 +#define RES_IO 0x00000002
8566 +#define RES_FW_DEVICE 0x00000003
8567 +#define RES_MMAP_IO_PORT 0x00000004
8568 +#define RES_MEM_RESERVED 0x00000005
8569 +#define RES_IO_RESERVED 0x00000006
8570 +#define RES_MAX_MEM_TYPE 0x00000007
8571 +
8572 +/*
8573 + * These types can be ORed together as needed.
8574 + *
8575 + * The first three enumerations describe settings
8576 + * The rest of the settings describe capabilities
8577 + */
8578 +#define RES_ATTR_PRESENT 0x00000001
8579 +#define RES_ATTR_INITIALIZED 0x00000002
8580 +#define RES_ATTR_TESTED 0x00000004
8581 +#define RES_ATTR_SINGLE_BIT_ECC 0x00000008
8582 +#define RES_ATTR_MULTIPLE_BIT_ECC 0x00000010
8583 +#define RES_ATTR_ECC_RESERVED_1 0x00000020
8584 +#define RES_ATTR_ECC_RESERVED_2 0x00000040
8585 +#define RES_ATTR_READ_PROTECTED 0x00000080
8586 +#define RES_ATTR_WRITE_PROTECTED 0x00000100
8587 +#define RES_ATTR_EXECUTION_PROTECTED 0x00000200
8588 +#define RES_ATTR_UNCACHEABLE 0x00000400
8589 +#define RES_ATTR_WRITE_COMBINEABLE 0x00000800
8590 +#define RES_ATTR_WRITE_THROUGH_CACHEABLE 0x00001000
8591 +#define RES_ATTR_WRITE_BACK_CACHEABLE 0x00002000
8592 +#define RES_ATTR_16_BIT_IO 0x00004000
8593 +#define RES_ATTR_32_BIT_IO 0x00008000
8594 +#define RES_ATTR_64_BIT_IO 0x00010000
8595 +#define RES_ATTR_UNCACHED_EXPORTED 0x00020000
8596 +
8597 +/*
8598 + * Describes the resource properties of all fixed, nonrelocatable resource
8599 + * ranges found on the processor host bus during the HOB producer phase.
8600 + */
8601 +struct hob_res_desc {
8602 + struct hob_header hdr;
8603 + /*
8604 + * A GUID representing the owner of the resource. This GUID is
8605 + * used by HOB consumer phase components to correlate device
8606 + * ownership of a resource.
8607 + */
8608 + struct efi_guid owner;
8609 + u32 type;
8610 + u32 attr;
8611 + /* The physical start address of the resource region */
8612 + phys_addr_t phys_start;
8613 + /* The number of bytes of the resource region */
8614 + phys_size_t len;
8615 +};
8616 +
8617 +/*
8618 + * Allows writers of executable content in the HOB producer phase to
8619 + * maintain and manage HOBs with specific GUID.
8620 + */
8621 +struct hob_guid {
8622 + struct hob_header hdr;
8623 + /* A GUID that defines the contents of this HOB */
8624 + struct efi_guid name;
8625 + /* GUID specific data goes here */
8626 +};
8627 +
8628 +/* Union of all the possible HOB Types */
8629 +union hob_pointers {
8630 + struct hob_header *hdr;
8631 + struct hob_mem_alloc *mem_alloc;
8632 + struct hob_res_desc *res_desc;
8633 + struct hob_guid *guid;
8634 + u8 *raw;
8635 +};
8636 +
8637 +/**
8638 + * get_hob_type() - return the type of a HOB
8639 + *
8640 + * This macro returns the type field from the HOB header for the
8641 + * HOB specified by hob.
8642 + *
8643 + * @hob: A pointer to a HOB.
8644 + *
8645 + * @return: HOB type.
8646 + */
8647 +static inline u16 get_hob_type(union hob_pointers hob)
8648 +{
8649 + return hob.hdr->type;
8650 +}
8651 +
8652 +/**
8653 + * get_hob_length() - return the length, in bytes, of a HOB
8654 + *
8655 + * This macro returns the len field from the HOB header for the
8656 + * HOB specified by hob.
8657 + *
8658 + * @hob: A pointer to a HOB.
8659 + *
8660 + * @return: HOB length.
8661 + */
8662 +static inline u16 get_hob_length(union hob_pointers hob)
8663 +{
8664 + return hob.hdr->len;
8665 +}
8666 +
8667 +/**
8668 + * get_next_hob() - return a pointer to the next HOB in the HOB list
8669 + *
8670 + * This macro returns a pointer to HOB that follows the HOB specified by hob
8671 + * in the HOB List.
8672 + *
8673 + * @hob: A pointer to a HOB.
8674 + *
8675 + * @return: A pointer to the next HOB in the HOB list.
8676 + */
8677 +static inline void *get_next_hob(union hob_pointers hob)
8678 +{
8679 + return (void *)(*(u8 **)&(hob) + get_hob_length(hob));
8680 +}
8681 +
8682 +/**
8683 + * end_of_hob() - determine if a HOB is the last HOB in the HOB list
8684 + *
8685 + * This macro determine if the HOB specified by hob is the last HOB in the
8686 + * HOB list. If hob is last HOB in the HOB list, then true is returned.
8687 + * Otherwise, false is returned.
8688 + *
8689 + * @hob: A pointer to a HOB.
8690 + *
8691 + * @retval true: The HOB specified by hob is the last HOB in the HOB list.
8692 + * @retval false: The HOB specified by hob is not the last HOB in the HOB list.
8693 + */
8694 +static inline bool end_of_hob(union hob_pointers hob)
8695 +{
8696 + return get_hob_type(hob) == HOB_TYPE_EOH;
8697 +}
8698 +
8699 +/**
8700 + * get_guid_hob_data() - return a pointer to data buffer from a HOB of
8701 + * type HOB_TYPE_GUID_EXT
8702 + *
8703 + * This macro returns a pointer to the data buffer in a HOB specified by hob.
8704 + * hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
8705 + *
8706 + * @hob: A pointer to a HOB.
8707 + *
8708 + * @return: A pointer to the data buffer in a HOB.
8709 + */
8710 +static inline void *get_guid_hob_data(u8 *hob)
8711 +{
8712 + return (void *)(hob + sizeof(struct hob_guid));
8713 +}
8714 +
8715 +/**
8716 + * get_guid_hob_data_size() - return the size of the data buffer from a HOB
8717 + * of type HOB_TYPE_GUID_EXT
8718 + *
8719 + * This macro returns the size, in bytes, of the data buffer in a HOB
8720 + * specified by hob. hob is assumed to be a HOB of type HOB_TYPE_GUID_EXT.
8721 + *
8722 + * @hob: A pointer to a HOB.
8723 + *
8724 + * @return: The size of the data buffer.
8725 + */
8726 +static inline u16 get_guid_hob_data_size(u8 *hob)
8727 +{
8728 + union hob_pointers hob_p = *(union hob_pointers *)hob;
8729 + return get_hob_length(hob_p) - sizeof(struct hob_guid);
8730 +}
8731 +
8732 +/* FSP specific GUID HOB definitions */
8733 +#define FSP_GUID_DATA1 0x912740be
8734 +#define FSP_GUID_DATA2 0x2284
8735 +#define FSP_GUID_DATA3 0x4734
8736 +#define FSP_GUID_DATA4_0 0xb9
8737 +#define FSP_GUID_DATA4_1 0x71
8738 +#define FSP_GUID_DATA4_2 0x84
8739 +#define FSP_GUID_DATA4_3 0xb0
8740 +#define FSP_GUID_DATA4_4 0x27
8741 +#define FSP_GUID_DATA4_5 0x35
8742 +#define FSP_GUID_DATA4_6 0x3f
8743 +#define FSP_GUID_DATA4_7 0x0c
8744 +
8745 +#define FSP_HEADER_GUID \
8746 + { \
8747 + FSP_GUID_DATA1, FSP_GUID_DATA2, FSP_GUID_DATA3, \
8748 + { FSP_GUID_DATA4_0, FSP_GUID_DATA4_1, FSP_GUID_DATA4_2, \
8749 + FSP_GUID_DATA4_3, FSP_GUID_DATA4_4, FSP_GUID_DATA4_5, \
8750 + FSP_GUID_DATA4_6, FSP_GUID_DATA4_7 } \
8751 + }
8752 +
8753 +#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
8754 + { \
8755 + 0x721acf02, 0x4d77, 0x4c2a, \
8756 + { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \
8757 + }
8758 +
8759 +#define FSP_BOOTLOADER_TEMP_MEM_HOB_GUID \
8760 + { \
8761 + 0xbbcff46c, 0xc8d3, 0x4113, \
8762 + { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \
8763 + }
8764 +
8765 +#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \
8766 + { \
8767 + 0x69a79759, 0x1373, 0x4367, \
8768 + { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \
8769 + }
8770 +
8771 +#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
8772 + { \
8773 + 0xd038747c, 0xd00c, 0x4980, \
8774 + { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \
8775 + }
8776 +
8777 +#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \
8778 + { \
8779 + 0x9c7c3aa7, 0x5332, 0x4917, \
8780 + { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \
8781 + }
8782 +
8783 +#endif
8784 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h
8785 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h 1970-01-01 01:00:00.000000000 +0100
8786 +++ u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_infoheader.h 2015-01-01 17:34:32.253503252 +0100
8787 @@ -0,0 +1,32 @@
8788 +/*
8789 + * Copyright (C) 2013, Intel Corporation
8790 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
8791 + *
8792 + * SPDX-License-Identifier: Intel
8793 + */
8794 +
8795 +#ifndef _FSP_HEADER_H_
8796 +#define _FSP_HEADER_H_
8797 +
8798 +#define FSP_HEADER_OFF 0x94 /* Fixed FSP header offset in the FSP image */
8799 +
8800 +struct __packed fsp_header {
8801 + u32 sign; /* 'FSPH' */
8802 + u32 hdr_len; /* header length */
8803 + u8 reserved1[3];
8804 + u8 hdr_rev; /* header rev */
8805 + u32 img_rev; /* image rev */
8806 + char img_id[8]; /* signature string */
8807 + u32 img_size; /* image size */
8808 + u32 img_base; /* image base */
8809 + u32 img_attr; /* image attribute */
8810 + u32 cfg_region_off; /* configuration region offset */
8811 + u32 cfg_region_size; /* configuration region size */
8812 + u32 api_num; /* number of API entries */
8813 + u32 fsp_tempram_init; /* tempram_init offset */
8814 + u32 fsp_init; /* fsp_init offset */
8815 + u32 fsp_notify; /* fsp_notify offset */
8816 + u32 reserved2;
8817 +};
8818 +
8819 +#endif
8820 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h
8821 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h 1970-01-01 01:00:00.000000000 +0100
8822 +++ u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_platform.h 2015-01-01 17:34:32.253503252 +0100
8823 @@ -0,0 +1,15 @@
8824 +/*
8825 + * Copyright (C) 2013, Intel Corporation
8826 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
8827 + *
8828 + * SPDX-License-Identifier: Intel
8829 + */
8830 +
8831 +#ifndef __FSP_PLATFORM_H__
8832 +#define __FSP_PLATFORM_H__
8833 +
8834 +struct fspinit_rtbuf {
8835 + struct common_buf common; /* FSP common runtime data structure */
8836 +};
8837 +
8838 +#endif
8839 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h
8840 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h 1970-01-01 01:00:00.000000000 +0100
8841 +++ u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_support.h 2015-01-01 17:34:32.253503252 +0100
8842 @@ -0,0 +1,207 @@
8843 +/*
8844 + * Copyright (C) 2013, Intel Corporation
8845 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
8846 + *
8847 + * SPDX-License-Identifier: Intel
8848 + */
8849 +
8850 +#ifndef __FSP_SUPPORT_H__
8851 +#define __FSP_SUPPORT_H__
8852 +
8853 +#include "fsp_types.h"
8854 +#include "fsp_fv.h"
8855 +#include "fsp_ffs.h"
8856 +#include "fsp_api.h"
8857 +#include "fsp_hob.h"
8858 +#include "fsp_platform.h"
8859 +#include "fsp_infoheader.h"
8860 +#include "fsp_bootmode.h"
8861 +#include "fsp_vpd.h"
8862 +
8863 +struct shared_data {
8864 + struct fsp_header *fsp_hdr;
8865 + u32 *stack_top;
8866 + struct upd_region fsp_upd;
8867 +};
8868 +
8869 +#define FSP_LOWMEM_BASE 0x100000UL
8870 +#define FSP_HIGHMEM_BASE 0x100000000ULL
8871 +
8872 +/**
8873 + * FSP Continuation assembly helper routine
8874 + *
8875 + * This routine jumps to the C version of FSP continuation function
8876 + */
8877 +void asm_continuation(void);
8878 +
8879 +/**
8880 + * FSP initialization complete
8881 + *
8882 + * This is the function that indicates FSP initialization is complete and jumps
8883 + * back to the bootloader with HOB list pointer as the parameter.
8884 + *
8885 + * @hob_list: HOB list pointer
8886 + */
8887 +void fsp_init_done(void *hob_list);
8888 +
8889 +/**
8890 + * FSP Continuation function
8891 + *
8892 + * @shared_data: Shared data base before stack migration
8893 + * @status: Always 0
8894 + * @hob_list: HOB list pointer
8895 + *
8896 + * @retval: Never returns
8897 + */
8898 +void fsp_continue(struct shared_data *shared_data, u32 status,
8899 + void *hob_list);
8900 +
8901 +/**
8902 + * Find FSP header offset in FSP image
8903 + *
8904 + * @retval: the offset of FSP header. If signature is invalid, returns 0.
8905 + */
8906 +u32 find_fsp_header(void);
8907 +
8908 +/**
8909 + * FSP initialization wrapper function.
8910 + *
8911 + * @stack_top: bootloader stack top address
8912 + * @boot_mode: boot mode defined in fsp_bootmode.h
8913 + * @nvs_buf: Non-volatile memory buffer pointer
8914 + */
8915 +void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf);
8916 +
8917 +/**
8918 + * FSP notification wrapper function
8919 + *
8920 + * @fsp_hdr: Pointer to FSP information header
8921 + * @phase: FSP initialization phase defined in enum fsp_phase
8922 + *
8923 + * @retval: compatible status code with EFI_STATUS defined in PI spec
8924 + */
8925 +u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
8926 +
8927 +/**
8928 + * This function retrieves the top of usable low memory.
8929 + *
8930 + * @hob_list: A HOB list pointer.
8931 + *
8932 + * @retval: Usable low memory top.
8933 + */
8934 +u32 fsp_get_usable_lowmem_top(const void *hob_list);
8935 +
8936 +/**
8937 + * This function retrieves the top of usable high memory.
8938 + *
8939 + * @hob_list: A HOB list pointer.
8940 + *
8941 + * @retval: Usable high memory top.
8942 + */
8943 +u64 fsp_get_usable_highmem_top(const void *hob_list);
8944 +
8945 +/**
8946 + * This function retrieves a special reserved memory region.
8947 + *
8948 + * @hob_list: A HOB list pointer.
8949 + * @len: A pointer to the GUID HOB data buffer length.
8950 + * If the GUID HOB is located, the length will be updated.
8951 + * @guid: A pointer to the owner guild.
8952 + *
8953 + * @retval: Reserved region start address.
8954 + * 0 if this region does not exist.
8955 + */
8956 +u64 fsp_get_reserved_mem_from_guid(const void *hob_list,
8957 + u64 *len, struct efi_guid *guid);
8958 +
8959 +/**
8960 + * This function retrieves the FSP reserved normal memory.
8961 + *
8962 + * @hob_list: A HOB list pointer.
8963 + * @len: A pointer to the FSP reserved memory length buffer.
8964 + * If the GUID HOB is located, the length will be updated.
8965 + * @retval: FSP reserved memory base
8966 + * 0 if this region does not exist.
8967 + */
8968 +u32 fsp_get_fsp_reserved_mem(const void *hob_list, u32 *len);
8969 +
8970 +/**
8971 + * This function retrieves the TSEG reserved normal memory.
8972 + *
8973 + * @hob_list: A HOB list pointer.
8974 + * @len: A pointer to the TSEG reserved memory length buffer.
8975 + * If the GUID HOB is located, the length will be updated.
8976 + *
8977 + * @retval NULL: Failed to find the TSEG reserved memory.
8978 + * @retval others: TSEG reserved memory base.
8979 + */
8980 +u32 fsp_get_tseg_reserved_mem(const void *hob_list, u32 *len);
8981 +
8982 +/**
8983 + * Returns the next instance of a HOB type from the starting HOB.
8984 + *
8985 + * @type: HOB type to search
8986 + * @hob_list: A pointer to the HOB list
8987 + *
8988 + * @retval: A HOB object with matching type; Otherwise NULL.
8989 + */
8990 +void *fsp_get_next_hob(u16 type, const void *hob_list);
8991 +
8992 +/**
8993 + * Returns the next instance of the matched GUID HOB from the starting HOB.
8994 + *
8995 + * @guid: GUID to search
8996 + * @hob_list: A pointer to the HOB list
8997 + *
8998 + * @retval: A HOB object with matching GUID; Otherwise NULL.
8999 + */
9000 +void *fsp_get_next_guid_hob(const struct efi_guid *guid, const void *hob_list);
9001 +
9002 +/**
9003 + * This function retrieves a GUID HOB data buffer and size.
9004 + *
9005 + * @hob_list: A HOB list pointer.
9006 + * @len: A pointer to the GUID HOB data buffer length.
9007 + * If the GUID HOB is located, the length will be updated.
9008 + * @guid A pointer to HOB GUID.
9009 + *
9010 + * @retval NULL: Failed to find the GUID HOB.
9011 + * @retval others: GUID HOB data buffer pointer.
9012 + */
9013 +void *fsp_get_guid_hob_data(const void *hob_list, u32 *len,
9014 + struct efi_guid *guid);
9015 +
9016 +/**
9017 + * This function retrieves FSP Non-volatile Storage HOB buffer and size.
9018 + *
9019 + * @hob_list: A HOB list pointer.
9020 + * @len: A pointer to the NVS data buffer length.
9021 + * If the HOB is located, the length will be updated.
9022 + *
9023 + * @retval NULL: Failed to find the NVS HOB.
9024 + * @retval others: FSP NVS data buffer pointer.
9025 + */
9026 +void *fsp_get_nvs_data(const void *hob_list, u32 *len);
9027 +
9028 +/**
9029 + * This function retrieves Bootloader temporary stack buffer and size.
9030 + *
9031 + * @hob_list: A HOB list pointer.
9032 + * @len: A pointer to the bootloader temporary stack length.
9033 + * If the HOB is located, the length will be updated.
9034 + *
9035 + * @retval NULL: Failed to find the bootloader temporary stack HOB.
9036 + * @retval others: Bootloader temporary stackbuffer pointer.
9037 + */
9038 +void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len);
9039 +
9040 +/**
9041 + * This function overrides the default configurations in the UPD data region.
9042 + *
9043 + * @fsp_upd: A pointer to the upd_region data strcture
9044 + *
9045 + * @return: None
9046 + */
9047 +void update_fsp_upd(struct upd_region *fsp_upd);
9048 +
9049 +#endif
9050 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h
9051 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h 1970-01-01 01:00:00.000000000 +0100
9052 +++ u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_types.h 2015-01-01 17:34:32.253503252 +0100
9053 @@ -0,0 +1,82 @@
9054 +/*
9055 + * Copyright (C) 2013, Intel Corporation
9056 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
9057 + *
9058 + * SPDX-License-Identifier: Intel
9059 + */
9060 +
9061 +#ifndef __FSP_TYPES_H__
9062 +#define __FSP_TYPES_H__
9063 +
9064 +/* 128 bit buffer containing a unique identifier value */
9065 +struct efi_guid {
9066 + u32 data1;
9067 + u16 data2;
9068 + u16 data3;
9069 + u8 data4[8];
9070 +};
9071 +
9072 +/**
9073 + * Returns a 16-bit signature built from 2 ASCII characters.
9074 + *
9075 + * This macro returns a 16-bit value built from the two ASCII characters
9076 + * specified by A and B.
9077 + *
9078 + * @A: The first ASCII character.
9079 + * @B: The second ASCII character.
9080 + *
9081 + * @return: A 16-bit value built from the two ASCII characters specified by
9082 + * A and B.
9083 + */
9084 +#define SIGNATURE_16(A, B) ((A) | (B << 8))
9085 +
9086 +/**
9087 + * Returns a 32-bit signature built from 4 ASCII characters.
9088 + *
9089 + * This macro returns a 32-bit value built from the four ASCII characters
9090 + * specified by A, B, C, and D.
9091 + *
9092 + * @A: The first ASCII character.
9093 + * @B: The second ASCII character.
9094 + * @C: The third ASCII character.
9095 + * @D: The fourth ASCII character.
9096 + *
9097 + * @return: A 32-bit value built from the two ASCII characters specified by
9098 + * A, B, C and D.
9099 + */
9100 +#define SIGNATURE_32(A, B, C, D) \
9101 + (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16))
9102 +
9103 +/**
9104 + * Returns a 64-bit signature built from 8 ASCII characters.
9105 + *
9106 + * This macro returns a 64-bit value built from the eight ASCII characters
9107 + * specified by A, B, C, D, E, F, G,and H.
9108 + *
9109 + * @A: The first ASCII character.
9110 + * @B: The second ASCII character.
9111 + * @C: The third ASCII character.
9112 + * @D: The fourth ASCII character.
9113 + * @E: The fifth ASCII character.
9114 + * @F: The sixth ASCII character.
9115 + * @G: The seventh ASCII character.
9116 + * @H: The eighth ASCII character.
9117 + *
9118 + * @return: A 64-bit value built from the two ASCII characters specified by
9119 + * A, B, C, D, E, F, G and H.
9120 + */
9121 +#define SIGNATURE_64(A, B, C, D, E, F, G, H) \
9122 + (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
9123 +
9124 +/*
9125 + * Define FSP API return status code.
9126 + * Compatiable with EFI_STATUS defined in PI Spec.
9127 + */
9128 +#define FSP_SUCCESS 0
9129 +#define FSP_INVALID_PARAM 0x80000002
9130 +#define FSP_UNSUPPORTED 0x80000003
9131 +#define FSP_DEVICE_ERROR 0x80000007
9132 +#define FSP_NOT_FOUND 0x8000000E
9133 +#define FSP_ALREADY_STARTED 0x80000014
9134 +
9135 +#endif
9136 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h
9137 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h 1970-01-01 01:00:00.000000000 +0100
9138 +++ u-boot/arch/x86/include/asm/arch-queensbay/fsp/fsp_vpd.h 2015-01-01 17:34:32.253503252 +0100
9139 @@ -0,0 +1,56 @@
9140 +/*
9141 + * Copyright (C) 2013, Intel Corporation
9142 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
9143 + *
9144 + * This file is automatically generated. Please do NOT modify !!!
9145 + *
9146 + * SPDX-License-Identifier: Intel
9147 + */
9148 +
9149 +#ifndef __VPDHEADER_H__
9150 +#define __VPDHEADER_H__
9151 +
9152 +#define UPD_TERMINATOR 0x55AA
9153 +
9154 +struct __packed upd_region {
9155 + u64 sign; /* Offset 0x0000 */
9156 + u64 reserved; /* Offset 0x0008 */
9157 + u8 dummy[240]; /* Offset 0x0010 */
9158 + u8 hda_verb_header[12]; /* Offset 0x0100 */
9159 + u32 hda_verb_length; /* Offset 0x010C */
9160 + u8 hda_verb_data0[16]; /* Offset 0x0110 */
9161 + u8 hda_verb_data1[16]; /* Offset 0x0120 */
9162 + u8 hda_verb_data2[16]; /* Offset 0x0130 */
9163 + u8 hda_verb_data3[16]; /* Offset 0x0140 */
9164 + u8 hda_verb_data4[16]; /* Offset 0x0150 */
9165 + u8 hda_verb_data5[16]; /* Offset 0x0160 */
9166 + u8 hda_verb_data6[16]; /* Offset 0x0170 */
9167 + u8 hda_verb_data7[16]; /* Offset 0x0180 */
9168 + u8 hda_verb_data8[16]; /* Offset 0x0190 */
9169 + u8 hda_verb_data9[16]; /* Offset 0x01A0 */
9170 + u8 hda_verb_data10[16]; /* Offset 0x01B0 */
9171 + u8 hda_verb_data11[16]; /* Offset 0x01C0 */
9172 + u8 hda_verb_data12[16]; /* Offset 0x01D0 */
9173 + u8 hda_verb_data13[16]; /* Offset 0x01E0 */
9174 + u8 hda_verb_pad[47]; /* Offset 0x01F0 */
9175 + u16 terminator; /* Offset 0x021F */
9176 +};
9177 +
9178 +#define VPD_IMAGE_ID 0x445056574F4E4E4D /* 'MNNOWVPD' */
9179 +#define VPD_IMAGE_REV 0x00000301
9180 +
9181 +struct __packed vpd_region {
9182 + u64 sign; /* Offset 0x0000 */
9183 + u32 img_rev; /* Offset 0x0008 */
9184 + u32 upd_offset; /* Offset 0x000C */
9185 + u8 unused[16]; /* Offset 0x0010 */
9186 + u32 fsp_res_memlen; /* Offset 0x0020 */
9187 + u8 disable_pcie1; /* Offset 0x0024 */
9188 + u8 disable_pcie2; /* Offset 0x0025 */
9189 + u8 disable_pcie3; /* Offset 0x0026 */
9190 + u8 enable_azalia; /* Offset 0x0027 */
9191 + u8 legacy_seg_decode; /* Offset 0x0028 */
9192 + u8 pcie_port_ioh; /* Offset 0x0029 */
9193 +};
9194 +
9195 +#endif
9196 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/gpio.h u-boot/arch/x86/include/asm/arch-queensbay/gpio.h
9197 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/gpio.h 1970-01-01 01:00:00.000000000 +0100
9198 +++ u-boot/arch/x86/include/asm/arch-queensbay/gpio.h 2015-01-01 17:34:32.253503252 +0100
9199 @@ -0,0 +1,13 @@
9200 +/*
9201 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
9202 + *
9203 + * SPDX-License-Identifier: GPL-2.0+
9204 + */
9205 +
9206 +#ifndef _X86_ARCH_GPIO_H_
9207 +#define _X86_ARCH_GPIO_H_
9208 +
9209 +/* Where in config space is the register that points to the GPIO registers? */
9210 +#define PCI_CFG_GPIOBASE 0x44
9211 +
9212 +#endif /* _X86_ARCH_GPIO_H_ */
9213 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/tnc.h u-boot/arch/x86/include/asm/arch-queensbay/tnc.h
9214 --- u-boot-2015.01-rc3/arch/x86/include/asm/arch-queensbay/tnc.h 1970-01-01 01:00:00.000000000 +0100
9215 +++ u-boot/arch/x86/include/asm/arch-queensbay/tnc.h 2015-01-01 17:34:32.253503252 +0100
9216 @@ -0,0 +1,15 @@
9217 +/*
9218 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
9219 + *
9220 + * SPDX-License-Identifier: GPL-2.0+
9221 + */
9222 +
9223 +#ifndef _X86_ARCH_TNC_H_
9224 +#define _X86_ARCH_TNC_H_
9225 +
9226 +#include <pci.h>
9227 +
9228 +/* PCI Configuration Space (D31:F0): LPC */
9229 +#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
9230 +
9231 +#endif /* _X86_ARCH_TNC_H_ */
9232 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/config.h u-boot/arch/x86/include/asm/config.h
9233 --- u-boot-2015.01-rc3/arch/x86/include/asm/config.h 2014-12-08 22:35:08.000000000 +0100
9234 +++ u-boot/arch/x86/include/asm/config.h 2015-01-01 17:34:32.257503186 +0100
9235 @@ -10,6 +10,5 @@
9236 #define CONFIG_SYS_GENERIC_BOARD
9237 #define CONFIG_LMB
9238 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
9239 -#define asmlinkage __attribute__((regparm(0)))
9240
9241 #endif
9242 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/global_data.h u-boot/arch/x86/include/asm/global_data.h
9243 --- u-boot-2015.01-rc3/arch/x86/include/asm/global_data.h 2014-12-08 22:35:08.000000000 +0100
9244 +++ u-boot/arch/x86/include/asm/global_data.h 2015-01-01 17:34:32.257503186 +0100
9245 @@ -47,6 +47,9 @@
9246 enum pei_boot_mode_t pei_boot_mode;
9247 const struct pch_gpio_map *gpio_map; /* board GPIO map */
9248 struct memory_info meminfo; /* Memory information */
9249 +#ifdef CONFIG_HAVE_FSP
9250 + void *hob_list; /* FSP HOB list */
9251 +#endif
9252 };
9253
9254 #endif
9255 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/gpio.h u-boot/arch/x86/include/asm/gpio.h
9256 --- u-boot-2015.01-rc3/arch/x86/include/asm/gpio.h 2014-12-08 22:35:08.000000000 +0100
9257 +++ u-boot/arch/x86/include/asm/gpio.h 2015-01-01 17:34:32.257503186 +0100
9258 @@ -11,7 +11,7 @@
9259 #include <asm-generic/gpio.h>
9260
9261 struct ich6_bank_platdata {
9262 - uint32_t base_addr;
9263 + uint16_t base_addr;
9264 const char *bank_name;
9265 };
9266
9267 @@ -147,6 +147,7 @@
9268 } set3;
9269 };
9270
9271 +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
9272 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
9273
9274 #endif /* _X86_GPIO_H_ */
9275 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/ibmpc.h u-boot/arch/x86/include/asm/ibmpc.h
9276 --- u-boot-2015.01-rc3/arch/x86/include/asm/ibmpc.h 2014-12-08 22:35:08.000000000 +0100
9277 +++ u-boot/arch/x86/include/asm/ibmpc.h 2015-01-01 17:34:32.257503186 +0100
9278 @@ -18,4 +18,7 @@
9279 #define SYSCTLA 0x92
9280 #define SLAVE_PIC 0xa0
9281
9282 +#define UART0_BASE 0x3f8
9283 +#define UART1_BASE 0x2f8
9284 +
9285 #endif
9286 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/linkage.h u-boot/arch/x86/include/asm/linkage.h
9287 --- u-boot-2015.01-rc3/arch/x86/include/asm/linkage.h 1970-01-01 01:00:00.000000000 +0100
9288 +++ u-boot/arch/x86/include/asm/linkage.h 2015-01-01 17:34:32.257503186 +0100
9289 @@ -0,0 +1,6 @@
9290 +#ifndef _ASM_X86_LINKAGE_H
9291 +#define _ASM_X86_LINKAGE_H
9292 +
9293 +#define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0)))
9294 +
9295 +#endif /* _ASM_X86_LINKAGE_H */
9296 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/pnp_def.h u-boot/arch/x86/include/asm/pnp_def.h
9297 --- u-boot-2015.01-rc3/arch/x86/include/asm/pnp_def.h 1970-01-01 01:00:00.000000000 +0100
9298 +++ u-boot/arch/x86/include/asm/pnp_def.h 2015-01-01 17:34:32.257503186 +0100
9299 @@ -0,0 +1,90 @@
9300 +/*
9301 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
9302 + *
9303 + * Adapted from coreboot src/include/device/pnp_def.h
9304 + * and arch/x86/include/arch/io.h
9305 + *
9306 + * SPDX-License-Identifier: GPL-2.0+
9307 + */
9308 +
9309 +#ifndef _ASM_PNP_DEF_H_
9310 +#define _ASM_PNP_DEF_H_
9311 +
9312 +#include <asm/io.h>
9313 +
9314 +#define PNP_IDX_EN 0x30
9315 +#define PNP_IDX_IO0 0x60
9316 +#define PNP_IDX_IO1 0x62
9317 +#define PNP_IDX_IO2 0x64
9318 +#define PNP_IDX_IO3 0x66
9319 +#define PNP_IDX_IRQ0 0x70
9320 +#define PNP_IDX_IRQ1 0x72
9321 +#define PNP_IDX_DRQ0 0x74
9322 +#define PNP_IDX_DRQ1 0x75
9323 +#define PNP_IDX_MSC0 0xf0
9324 +#define PNP_IDX_MSC1 0xf1
9325 +
9326 +/* Generic functions for pnp devices */
9327 +
9328 +/*
9329 + * pnp device is a 16-bit integer composed of its i/o port address at high byte
9330 + * and logic function number at low byte.
9331 + */
9332 +#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
9333 +
9334 +static inline void pnp_write_config(uint16_t dev, uint8_t reg, uint8_t value)
9335 +{
9336 + uint8_t port = dev >> 8;
9337 +
9338 + outb(reg, port);
9339 + outb(value, port + 1);
9340 +}
9341 +
9342 +static inline uint8_t pnp_read_config(uint16_t dev, uint8_t reg)
9343 +{
9344 + uint8_t port = dev >> 8;
9345 +
9346 + outb(reg, port);
9347 + return inb(port + 1);
9348 +}
9349 +
9350 +static inline void pnp_set_logical_device(uint16_t dev)
9351 +{
9352 + uint8_t device = dev & 0xff;
9353 +
9354 + pnp_write_config(dev, 0x07, device);
9355 +}
9356 +
9357 +static inline void pnp_set_enable(uint16_t dev, int enable)
9358 +{
9359 + pnp_write_config(dev, PNP_IDX_EN, enable ? 1 : 0);
9360 +}
9361 +
9362 +static inline int pnp_read_enable(uint16_t dev)
9363 +{
9364 + return !!pnp_read_config(dev, PNP_IDX_EN);
9365 +}
9366 +
9367 +static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase)
9368 +{
9369 + pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
9370 + pnp_write_config(dev, index + 1, iobase & 0xff);
9371 +}
9372 +
9373 +static inline uint16_t pnp_read_iobase(uint16_t dev, uint8_t index)
9374 +{
9375 + return ((uint16_t)(pnp_read_config(dev, index)) << 8) |
9376 + pnp_read_config(dev, index + 1);
9377 +}
9378 +
9379 +static inline void pnp_set_irq(uint16_t dev, uint8_t index, unsigned irq)
9380 +{
9381 + pnp_write_config(dev, index, irq);
9382 +}
9383 +
9384 +static inline void pnp_set_drq(uint16_t dev, uint8_t index, unsigned drq)
9385 +{
9386 + pnp_write_config(dev, index, drq & 0xff);
9387 +}
9388 +
9389 +#endif /* _ASM_PNP_DEF_H_ */
9390 diff -ruN u-boot-2015.01-rc3/arch/x86/include/asm/post.h u-boot/arch/x86/include/asm/post.h
9391 --- u-boot-2015.01-rc3/arch/x86/include/asm/post.h 2014-12-08 22:35:08.000000000 +0100
9392 +++ u-boot/arch/x86/include/asm/post.h 2015-01-01 17:34:32.257503186 +0100
9393 @@ -33,6 +33,8 @@
9394 #define POST_LAPIC 0x30
9395
9396 #define POST_RAM_FAILURE 0xea
9397 +#define POST_BIST_FAILURE 0xeb
9398 +#define POST_CAR_FAILURE 0xec
9399
9400 /* Output a post code using al - value must be 0 to 0xff */
9401 #ifdef __ASSEMBLY__
9402 diff -ruN u-boot-2015.01-rc3/arch/x86/Kconfig u-boot/arch/x86/Kconfig
9403 --- u-boot-2015.01-rc3/arch/x86/Kconfig 2014-12-08 22:35:08.000000000 +0100
9404 +++ u-boot/arch/x86/Kconfig 2015-01-01 17:34:32.249503317 +0100
9405 @@ -32,6 +32,15 @@
9406 and it provides a 2560x1700 high resolution touch-enabled LCD
9407 display.
9408
9409 +config TARGET_CROWNBAY
9410 + bool "Support Intel Crown Bay CRB"
9411 + help
9412 + This is the Intel Crown Bay Customer Reference Board. It contains
9413 + the Intel Atom Processor E6xx populated on the COM Express module
9414 + with 1GB DDR2 soldered down memory and a carrier board with the
9415 + Intel Platform Controller Hub EG20T, other system components and
9416 + peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
9417 +
9418 endchoice
9419
9420 config RAMBASE
9421 @@ -61,9 +70,85 @@
9422 config SMM_TSEG_SIZE
9423 hex
9424
9425 +config BOARD_ROMSIZE_KB_512
9426 + bool
9427 +config BOARD_ROMSIZE_KB_1024
9428 + bool
9429 +config BOARD_ROMSIZE_KB_2048
9430 + bool
9431 +config BOARD_ROMSIZE_KB_4096
9432 + bool
9433 +config BOARD_ROMSIZE_KB_8192
9434 + bool
9435 +config BOARD_ROMSIZE_KB_16384
9436 + bool
9437 +
9438 +choice
9439 + prompt "ROM chip size"
9440 + default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
9441 + default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
9442 + default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
9443 + default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
9444 + default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
9445 + default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
9446 + help
9447 + Select the size of the ROM chip you intend to flash U-Boot on.
9448 +
9449 + The build system will take care of creating a u-boot.rom file
9450 + of the matching size.
9451 +
9452 +config UBOOT_ROMSIZE_KB_512
9453 + bool "512 KB"
9454 + help
9455 + Choose this option if you have a 512 KB ROM chip.
9456 +
9457 +config UBOOT_ROMSIZE_KB_1024
9458 + bool "1024 KB (1 MB)"
9459 + help
9460 + Choose this option if you have a 1024 KB (1 MB) ROM chip.
9461 +
9462 +config UBOOT_ROMSIZE_KB_2048
9463 + bool "2048 KB (2 MB)"
9464 + help
9465 + Choose this option if you have a 2048 KB (2 MB) ROM chip.
9466 +
9467 +config UBOOT_ROMSIZE_KB_4096
9468 + bool "4096 KB (4 MB)"
9469 + help
9470 + Choose this option if you have a 4096 KB (4 MB) ROM chip.
9471 +
9472 +config UBOOT_ROMSIZE_KB_8192
9473 + bool "8192 KB (8 MB)"
9474 + help
9475 + Choose this option if you have a 8192 KB (8 MB) ROM chip.
9476 +
9477 +config UBOOT_ROMSIZE_KB_16384
9478 + bool "16384 KB (16 MB)"
9479 + help
9480 + Choose this option if you have a 16384 KB (16 MB) ROM chip.
9481 +
9482 +endchoice
9483 +
9484 +# Map the config names to an integer (KB).
9485 +config UBOOT_ROMSIZE_KB
9486 + int
9487 + default 512 if UBOOT_ROMSIZE_KB_512
9488 + default 1024 if UBOOT_ROMSIZE_KB_1024
9489 + default 2048 if UBOOT_ROMSIZE_KB_2048
9490 + default 4096 if UBOOT_ROMSIZE_KB_4096
9491 + default 8192 if UBOOT_ROMSIZE_KB_8192
9492 + default 16384 if UBOOT_ROMSIZE_KB_16384
9493 +
9494 +# Map the config names to a hex value (bytes).
9495 config ROM_SIZE
9496 hex
9497 - default 0x800000
9498 + default 0x80000 if UBOOT_ROMSIZE_KB_512
9499 + default 0x100000 if UBOOT_ROMSIZE_KB_1024
9500 + default 0x200000 if UBOOT_ROMSIZE_KB_2048
9501 + default 0x400000 if UBOOT_ROMSIZE_KB_4096
9502 + default 0x800000 if UBOOT_ROMSIZE_KB_8192
9503 + default 0xc00000 if UBOOT_ROMSIZE_KB_12288
9504 + default 0x1000000 if UBOOT_ROMSIZE_KB_16384
9505
9506 config HAVE_INTEL_ME
9507 bool "Platform requires Intel Management Engine"
9508 @@ -234,8 +319,12 @@
9509
9510 source "arch/x86/cpu/ivybridge/Kconfig"
9511
9512 +source "arch/x86/cpu/queensbay/Kconfig"
9513 +
9514 source "board/coreboot/coreboot/Kconfig"
9515
9516 source "board/google/chromebook_link/Kconfig"
9517
9518 +source "board/intel/crownbay/Kconfig"
9519 +
9520 endmenu
9521 diff -ruN u-boot-2015.01-rc3/arch/x86/lib/asm-offsets.c u-boot/arch/x86/lib/asm-offsets.c
9522 --- u-boot-2015.01-rc3/arch/x86/lib/asm-offsets.c 2014-12-08 22:35:08.000000000 +0100
9523 +++ u-boot/arch/x86/lib/asm-offsets.c 2015-01-01 17:34:32.257503186 +0100
9524 @@ -17,6 +17,9 @@
9525
9526 int main(void)
9527 {
9528 - DEFINE(GENERATED_GD_RELOC_OFF, offsetof(gd_t, reloc_off));
9529 + DEFINE(GD_BIST, offsetof(gd_t, arch.bist));
9530 +#ifdef CONFIG_HAVE_FSP
9531 + DEFINE(GD_HOB_LIST, offsetof(gd_t, arch.hob_list));
9532 +#endif
9533 return 0;
9534 }
9535 diff -ruN u-boot-2015.01-rc3/arch/x86/lib/bios.c u-boot/arch/x86/lib/bios.c
9536 --- u-boot-2015.01-rc3/arch/x86/lib/bios.c 2014-12-08 22:35:08.000000000 +0100
9537 +++ u-boot/arch/x86/lib/bios.c 2015-01-01 17:34:32.257503186 +0100
9538 @@ -9,6 +9,7 @@
9539 #include <common.h>
9540 #include <bios_emul.h>
9541 #include <vbe.h>
9542 +#include <linux/linkage.h>
9543 #include <asm/cache.h>
9544 #include <asm/processor.h>
9545 #include <asm/i8259.h>
9546 diff -ruN u-boot-2015.01-rc3/arch/x86/lib/bios.h u-boot/arch/x86/lib/bios.h
9547 --- u-boot-2015.01-rc3/arch/x86/lib/bios.h 2014-12-08 22:35:08.000000000 +0100
9548 +++ u-boot/arch/x86/lib/bios.h 2015-01-01 17:34:32.257503186 +0100
9549 @@ -10,6 +10,8 @@
9550 #ifndef _X86_LIB_BIOS_H
9551 #define _X86_LIB_BIOS_H
9552
9553 +#include <linux/linkage.h>
9554 +
9555 #define REALMODE_BASE 0x600
9556
9557 #ifdef __ASSEMBLY__
9558 diff -ruN u-boot-2015.01-rc3/arch/x86/lib/cmd_hob.c u-boot/arch/x86/lib/cmd_hob.c
9559 --- u-boot-2015.01-rc3/arch/x86/lib/cmd_hob.c 1970-01-01 01:00:00.000000000 +0100
9560 +++ u-boot/arch/x86/lib/cmd_hob.c 2015-01-01 17:34:32.257503186 +0100
9561 @@ -0,0 +1,65 @@
9562 +/*
9563 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
9564 + *
9565 + * SPDX-License-Identifier: GPL-2.0+
9566 + */
9567 +
9568 +#include <common.h>
9569 +#include <command.h>
9570 +#include <linux/compiler.h>
9571 +#include <asm/arch/fsp/fsp_support.h>
9572 +
9573 +DECLARE_GLOBAL_DATA_PTR;
9574 +
9575 +static char *hob_type[] = {
9576 + "reserved",
9577 + "Hand-off",
9578 + "Memory Allocation",
9579 + "Resource Descriptor",
9580 + "GUID Extension",
9581 + "Firmware Volume",
9582 + "CPU",
9583 + "Memory Pool",
9584 + "reserved",
9585 + "Firmware Volume 2",
9586 + "Load PEIM Unused",
9587 + "UEFI Capsule",
9588 +};
9589 +
9590 +int do_hob(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
9591 +{
9592 + union hob_pointers hob;
9593 + u16 type;
9594 + char *desc;
9595 + int i = 0;
9596 +
9597 + hob.raw = (u8 *)gd->arch.hob_list;
9598 +
9599 + printf("HOB list address: 0x%08x\n\n", (unsigned int)hob.raw);
9600 +
9601 + printf("No. | Address | Type | Length in Bytes\n");
9602 + printf("----|----------|---------------------|----------------\n");
9603 + while (!end_of_hob(hob)) {
9604 + printf("%-3d | %08x | ", i, (unsigned int)hob.raw);
9605 + type = get_hob_type(hob);
9606 + if (type == HOB_TYPE_UNUSED)
9607 + desc = "*Unused*";
9608 + else if (type == HOB_TYPE_EOH)
9609 + desc = "*END OF HOB*";
9610 + else if (type >= 0 && type <= ARRAY_SIZE(hob_type))
9611 + desc = hob_type[type];
9612 + else
9613 + desc = "*Invalid Type*";
9614 + printf("%-19s | %-15d\n", desc, get_hob_length(hob));
9615 + hob.raw = get_next_hob(hob);
9616 + i++;
9617 + }
9618 +
9619 + return 0;
9620 +}
9621 +
9622 +U_BOOT_CMD(
9623 + hob, 1, 1, do_hob,
9624 + "print Firmware Support Package (FSP) Hand-Off Block information",
9625 + ""
9626 +);
9627 diff -ruN u-boot-2015.01-rc3/arch/x86/lib/Makefile u-boot/arch/x86/lib/Makefile
9628 --- u-boot-2015.01-rc3/arch/x86/lib/Makefile 2014-12-08 22:35:08.000000000 +0100
9629 +++ u-boot/arch/x86/lib/Makefile 2015-01-01 17:34:32.257503186 +0100
9630 @@ -10,6 +10,7 @@
9631 obj-y += bios_interrupts.o
9632 obj-$(CONFIG_CMD_BOOTM) += bootm.o
9633 obj-y += cmd_boot.o
9634 +obj-$(CONFIG_HAVE_FSP) += cmd_hob.o
9635 obj-y += gcc.o
9636 obj-y += init_helpers.o
9637 obj-y += interrupts.o
9638 diff -ruN u-boot-2015.01-rc3/board/altera/socfpga/MAINTAINERS u-boot/board/altera/socfpga/MAINTAINERS
9639 --- u-boot-2015.01-rc3/board/altera/socfpga/MAINTAINERS 2014-12-08 22:35:08.000000000 +0100
9640 +++ u-boot/board/altera/socfpga/MAINTAINERS 2015-01-01 17:34:32.269502990 +0100
9641 @@ -5,3 +5,8 @@
9642 F: board/altera/socfpga/
9643 F: include/configs/socfpga_cyclone5.h
9644 F: configs/socfpga_cyclone5_defconfig
9645 +
9646 +SOCRATES BOARD
9647 +M: Stefan Roese <sr@denx.de>
9648 +S: Maintained
9649 +F: configs/socfpga_socrates_defconfig
9650 diff -ruN u-boot-2015.01-rc3/board/altera/socfpga/socfpga_cyclone5.c u-boot/board/altera/socfpga/socfpga_cyclone5.c
9651 --- u-boot-2015.01-rc3/board/altera/socfpga/socfpga_cyclone5.c 2014-12-08 22:35:08.000000000 +0100
9652 +++ u-boot/board/altera/socfpga/socfpga_cyclone5.c 2015-01-01 17:34:32.273502924 +0100
9653 @@ -12,7 +12,9 @@
9654 #include <usb/s3c_udc.h>
9655 #include <usb_mass_storage.h>
9656
9657 +#include <micrel.h>
9658 #include <netdev.h>
9659 +#include <phy.h>
9660
9661 DECLARE_GLOBAL_DATA_PTR;
9662
9663 @@ -44,6 +46,42 @@
9664 return 0;
9665 }
9666
9667 +/*
9668 + * PHY configuration
9669 + */
9670 +#ifdef CONFIG_PHY_MICREL_KSZ9021
9671 +int board_phy_config(struct phy_device *phydev)
9672 +{
9673 + int ret;
9674 + /*
9675 + * These skew settings for the KSZ9021 ethernet phy is required for ethernet
9676 + * to work reliably on most flavors of cyclone5 boards.
9677 + */
9678 + ret = ksz9021_phy_extended_write(phydev,
9679 + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
9680 + 0x0);
9681 + if (ret)
9682 + return ret;
9683 +
9684 + ret = ksz9021_phy_extended_write(phydev,
9685 + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
9686 + 0x0);
9687 + if (ret)
9688 + return ret;
9689 +
9690 + ret = ksz9021_phy_extended_write(phydev,
9691 + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
9692 + 0xf0f0);
9693 + if (ret)
9694 + return ret;
9695 +
9696 + if (phydev->drv->config)
9697 + return phydev->drv->config(phydev);
9698 +
9699 + return 0;
9700 +}
9701 +#endif
9702 +
9703 #ifdef CONFIG_USB_GADGET
9704 struct s3c_plat_otg_data socfpga_otg_data = {
9705 .regs_otg = CONFIG_USB_DWC2_REG_ADDR,
9706 diff -ruN u-boot-2015.01-rc3/board/aristainetos/aristainetos.c u-boot/board/aristainetos/aristainetos.c
9707 --- u-boot-2015.01-rc3/board/aristainetos/aristainetos.c 2014-12-08 22:35:08.000000000 +0100
9708 +++ u-boot/board/aristainetos/aristainetos.c 2015-01-01 17:34:32.281502792 +0100
9709 @@ -301,7 +301,7 @@
9710 /* clear gpr1[14], gpr1[18:17] to select anatop clock */
9711 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
9712
9713 - ret = enable_fec_anatop_clock(ENET_50MHz);
9714 + ret = enable_fec_anatop_clock(ENET_50MHZ);
9715 if (ret)
9716 return ret;
9717
9718 diff -ruN u-boot-2015.01-rc3/board/armltd/vexpress64/MAINTAINERS u-boot/board/armltd/vexpress64/MAINTAINERS
9719 --- u-boot-2015.01-rc3/board/armltd/vexpress64/MAINTAINERS 2014-12-08 22:35:08.000000000 +0100
9720 +++ u-boot/board/armltd/vexpress64/MAINTAINERS 2015-01-01 17:34:32.281502792 +0100
9721 @@ -6,6 +6,6 @@
9722 F: configs/vexpress_aemv8a_defconfig
9723
9724 VEXPRESS_AEMV8A_SEMI BOARD
9725 -M: Steve Rae <srae@broadcom.com>
9726 +M: Linus Walleij <linus.walleij@linaro.org>
9727 S: Maintained
9728 F: configs/vexpress_aemv8a_semi_defconfig
9729 diff -ruN u-boot-2015.01-rc3/board/avionic-design/common/tamonten-ng.c u-boot/board/avionic-design/common/tamonten-ng.c
9730 --- u-boot-2015.01-rc3/board/avionic-design/common/tamonten-ng.c 2014-12-08 22:35:08.000000000 +0100
9731 +++ u-boot/board/avionic-design/common/tamonten-ng.c 2015-01-01 17:34:32.285502727 +0100
9732 @@ -6,6 +6,7 @@
9733 */
9734
9735 #include <common.h>
9736 +#include <dm.h>
9737 #include <asm/arch/pinmux.h>
9738 #include <asm/arch/gp_padctrl.h>
9739 #include <asm/arch/gpio.h>
9740 @@ -51,8 +52,15 @@
9741
9742 void pmu_write(uchar reg, uchar data)
9743 {
9744 - i2c_set_bus_num(4); /* PMU is on bus 4 */
9745 - i2c_write(PMU_I2C_ADDRESS, reg, 1, &data, 1);
9746 + struct udevice *dev;
9747 + int ret;
9748 +
9749 + ret = i2c_get_chip_for_busnum(4, PMU_I2C_ADDRESS, &dev);
9750 + if (ret) {
9751 + debug("%s: Cannot find PMIC I2C chip\n", __func__);
9752 + return;
9753 + }
9754 + i2c_write(dev, reg, &data, 1);
9755 }
9756
9757 /*
9758 diff -ruN u-boot-2015.01-rc3/board/coreboot/coreboot/coreboot.c u-boot/board/coreboot/coreboot/coreboot.c
9759 --- u-boot-2015.01-rc3/board/coreboot/coreboot/coreboot.c 2014-12-08 22:35:08.000000000 +0100
9760 +++ u-boot/board/coreboot/coreboot/coreboot.c 2015-01-01 17:34:32.305502399 +0100
9761 @@ -6,6 +6,7 @@
9762
9763 #include <common.h>
9764 #include <cros_ec.h>
9765 +#include <asm/gpio.h>
9766
9767 int arch_early_init_r(void)
9768 {
9769 @@ -14,3 +15,8 @@
9770
9771 return 0;
9772 }
9773 +
9774 +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
9775 +{
9776 + return;
9777 +}
9778 diff -ruN u-boot-2015.01-rc3/board/freescale/common/arm_sleep.c u-boot/board/freescale/common/arm_sleep.c
9779 --- u-boot-2015.01-rc3/board/freescale/common/arm_sleep.c 1970-01-01 01:00:00.000000000 +0100
9780 +++ u-boot/board/freescale/common/arm_sleep.c 2015-01-01 17:34:32.357501547 +0100
9781 @@ -0,0 +1,95 @@
9782 +/*
9783 + * Copyright 2014 Freescale Semiconductor, Inc.
9784 + *
9785 + * SPDX-License-Identifier: GPL-2.0+
9786 + */
9787 +
9788 +#include <common.h>
9789 +#include <asm/io.h>
9790 +#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT)
9791 +#error " Deep sleep needs non-secure mode support. "
9792 +#else
9793 +#include <asm/secure.h>
9794 +#endif
9795 +#include <asm/armv7.h>
9796 +#include <asm/cache.h>
9797 +
9798 +#if defined(CONFIG_LS102XA)
9799 +#include <asm/arch/immap_ls102xa.h>
9800 +#endif
9801 +
9802 +#include "sleep.h"
9803 +
9804 +DECLARE_GLOBAL_DATA_PTR;
9805 +
9806 +void __weak board_mem_sleep_setup(void)
9807 +{
9808 +}
9809 +
9810 +void __weak board_sleep_prepare(void)
9811 +{
9812 +}
9813 +
9814 +bool is_warm_boot(void)
9815 +{
9816 + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
9817 +
9818 + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
9819 + return 1;
9820 +
9821 + return 0;
9822 +}
9823 +
9824 +void fsl_dp_disable_console(void)
9825 +{
9826 + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
9827 +}
9828 +
9829 +/*
9830 + * When wakeup from deep sleep, the first 128 bytes space
9831 + * will be used to do DDR training which corrupts the data
9832 + * in there. This function will restore them.
9833 + */
9834 +static void dp_ddr_restore(void)
9835 +{
9836 + u64 *src, *dst;
9837 + int i;
9838 + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
9839 +
9840 + /* get the address of ddr date from SPARECR3 */
9841 + src = (u64 *)in_le32(&scfg->sparecr[2]);
9842 + dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
9843 +
9844 + for (i = 0; i < DDR_BUFF_LEN / 8; i++)
9845 + *dst++ = *src++;
9846 +
9847 + flush_dcache_all();
9848 +}
9849 +
9850 +static void dp_resume_prepare(void)
9851 +{
9852 + dp_ddr_restore();
9853 + board_sleep_prepare();
9854 + armv7_init_nonsec();
9855 + cleanup_before_linux();
9856 +}
9857 +
9858 +int fsl_dp_resume(void)
9859 +{
9860 + u32 start_addr;
9861 + void (*kernel_resume)(void);
9862 + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
9863 +
9864 + if (!is_warm_boot())
9865 + return 0;
9866 +
9867 + dp_resume_prepare();
9868 +
9869 + /* Get the entry address and jump to kernel */
9870 + start_addr = in_le32(&scfg->sparecr[1]);
9871 + debug("Entry address is 0x%08x\n", start_addr);
9872 + kernel_resume = (void (*)(void))start_addr;
9873 + secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0);
9874 +
9875 + return 0;
9876 +}
9877 diff -ruN u-boot-2015.01-rc3/board/freescale/common/ls102xa_stream_id.c u-boot/board/freescale/common/ls102xa_stream_id.c
9878 --- u-boot-2015.01-rc3/board/freescale/common/ls102xa_stream_id.c 1970-01-01 01:00:00.000000000 +0100
9879 +++ u-boot/board/freescale/common/ls102xa_stream_id.c 2015-01-01 17:34:32.357501547 +0100
9880 @@ -0,0 +1,18 @@
9881 +/*
9882 + * Copyright 2014 Freescale Semiconductor
9883 + *
9884 + * SPDX-License-Identifier: GPL-2.0+
9885 + */
9886 +
9887 +#include <common.h>
9888 +#include <asm/io.h>
9889 +#include <asm/arch/ls102xa_stream_id.h>
9890 +
9891 +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
9892 +{
9893 + uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR;
9894 + int i;
9895 +
9896 + for (i = 0; i < num; i++)
9897 + out_be32(scfg + id[i].offset, id[i].stream_id);
9898 +}
9899 diff -ruN u-boot-2015.01-rc3/board/freescale/common/Makefile u-boot/board/freescale/common/Makefile
9900 --- u-boot-2015.01-rc3/board/freescale/common/Makefile 2014-12-08 22:35:08.000000000 +0100
9901 +++ u-boot/board/freescale/common/Makefile 2015-01-01 17:34:32.357501547 +0100
9902 @@ -37,6 +37,12 @@
9903
9904 obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o
9905
9906 +ifdef CONFIG_ARM
9907 +obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o
9908 +else
9909 +obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o
9910 +endif
9911 +
9912 obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o
9913
9914 obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
9915 @@ -56,10 +62,14 @@
9916 obj-$(CONFIG_ZM7300) += zm7300.o
9917 obj-$(CONFIG_POWER_PFUZE100) += pfuze.o
9918
9919 +obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
9920 +
9921 # deal with common files for P-series corenet based devices
9922 obj-$(CONFIG_P2041RDB) += p_corenet/
9923 obj-$(CONFIG_P3041DS) += p_corenet/
9924 obj-$(CONFIG_P4080DS) += p_corenet/
9925 obj-$(CONFIG_P5020DS) += p_corenet/
9926 obj-$(CONFIG_P5040DS) += p_corenet/
9927 +
9928 +obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o
9929 endif
9930 diff -ruN u-boot-2015.01-rc3/board/freescale/common/mpc85xx_sleep.c u-boot/board/freescale/common/mpc85xx_sleep.c
9931 --- u-boot-2015.01-rc3/board/freescale/common/mpc85xx_sleep.c 1970-01-01 01:00:00.000000000 +0100
9932 +++ u-boot/board/freescale/common/mpc85xx_sleep.c 2015-01-01 17:34:32.357501547 +0100
9933 @@ -0,0 +1,88 @@
9934 +/*
9935 + * Copyright 2014 Freescale Semiconductor, Inc.
9936 + *
9937 + * SPDX-License-Identifier: GPL-2.0+
9938 + */
9939 +
9940 +#include <common.h>
9941 +#include <asm/immap_85xx.h>
9942 +#include "sleep.h"
9943 +
9944 +DECLARE_GLOBAL_DATA_PTR;
9945 +
9946 +void __weak board_mem_sleep_setup(void)
9947 +{
9948 +}
9949 +
9950 +void __weak board_sleep_prepare(void)
9951 +{
9952 +}
9953 +
9954 +bool is_warm_boot(void)
9955 +{
9956 + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
9957 +
9958 + if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR)
9959 + return 1;
9960 +
9961 + return 0;
9962 +}
9963 +
9964 +void fsl_dp_disable_console(void)
9965 +{
9966 + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
9967 +}
9968 +
9969 +/*
9970 + * When wakeup from deep sleep, the first 128 bytes space
9971 + * will be used to do DDR training which corrupts the data
9972 + * in there. This function will restore them.
9973 + */
9974 +static void dp_ddr_restore(void)
9975 +{
9976 + volatile u64 *src, *dst;
9977 + int i;
9978 + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
9979 +
9980 + /* get the address of ddr date from SPARECR3 */
9981 + src = (u64 *)in_be32(&scfg->sparecr[2]);
9982 + dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
9983 +
9984 + for (i = 0; i < DDR_BUFF_LEN / 8; i++)
9985 + *dst++ = *src++;
9986 +
9987 + flush_dcache();
9988 +}
9989 +
9990 +static void dp_resume_prepare(void)
9991 +{
9992 + dp_ddr_restore();
9993 +
9994 + board_sleep_prepare();
9995 +
9996 + l2cache_init();
9997 +#if defined(CONFIG_RAMBOOT_PBL)
9998 + disable_cpc_sram();
9999 +#endif
10000 + enable_cpc();
10001 +}
10002 +
10003 +int fsl_dp_resume(void)
10004 +{
10005 + u32 start_addr;
10006 + void (*kernel_resume)(void);
10007 + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
10008 +
10009 + if (!is_warm_boot())
10010 + return 0;
10011 +
10012 + dp_resume_prepare();
10013 +
10014 + /* Get the entry address and jump to kernel */
10015 + start_addr = in_be32(&scfg->sparecr[1]);
10016 + debug("Entry address is 0x%08x\n", start_addr);
10017 + kernel_resume = (void (*)(void))start_addr;
10018 + kernel_resume();
10019 +
10020 + return 0;
10021 +}
10022 diff -ruN u-boot-2015.01-rc3/board/freescale/common/ns_access.c u-boot/board/freescale/common/ns_access.c
10023 --- u-boot-2015.01-rc3/board/freescale/common/ns_access.c 1970-01-01 01:00:00.000000000 +0100
10024 +++ u-boot/board/freescale/common/ns_access.c 2015-01-01 17:34:32.357501547 +0100
10025 @@ -0,0 +1,30 @@
10026 +/*
10027 + * Copyright 2014 Freescale Semiconductor
10028 + *
10029 + * SPDX-License-Identifier: GPL-2.0+
10030 + */
10031 +
10032 +#include <common.h>
10033 +#include <asm/io.h>
10034 +#include <asm/arch/ns_access.h>
10035 +
10036 +void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
10037 +{
10038 + u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
10039 + u32 *reg;
10040 + uint32_t val;
10041 + int i;
10042 +
10043 + for (i = 0; i < num; i++) {
10044 + reg = base + ns_dev[i].ind / 2;
10045 + val = in_be32(reg);
10046 + if (ns_dev[i].ind % 2 == 0) {
10047 + val &= 0x0000ffff;
10048 + val |= ns_dev[i].val << 16;
10049 + } else {
10050 + val &= 0xffff0000;
10051 + val |= ns_dev[i].val;
10052 + }
10053 + out_be32(reg, val);
10054 + }
10055 +}
10056 diff -ruN u-boot-2015.01-rc3/board/freescale/common/qixis.h u-boot/board/freescale/common/qixis.h
10057 --- u-boot-2015.01-rc3/board/freescale/common/qixis.h 2014-12-08 22:35:08.000000000 +0100
10058 +++ u-boot/board/freescale/common/qixis.h 2015-01-01 17:34:32.357501547 +0100
10059 @@ -100,8 +100,15 @@
10060 void qixis_write_i2c(unsigned int reg, u8 value);
10061 #endif
10062
10063 +#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR)
10064 +#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg))
10065 +#define QIXIS_WRITE(reg, value) \
10066 + qixis_write_i2c(offsetof(struct qixis, reg), value)
10067 +#else
10068 #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg))
10069 #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value)
10070 +#endif
10071 +
10072 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
10073 #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg))
10074 #define QIXIS_WRITE_I2C(reg, value) \
10075 diff -ruN u-boot-2015.01-rc3/board/freescale/common/sleep.h u-boot/board/freescale/common/sleep.h
10076 --- u-boot-2015.01-rc3/board/freescale/common/sleep.h 1970-01-01 01:00:00.000000000 +0100
10077 +++ u-boot/board/freescale/common/sleep.h 2015-01-01 17:34:32.357501547 +0100
10078 @@ -0,0 +1,21 @@
10079 +/*
10080 + * Copyright 2014 Freescale Semiconductor, Inc.
10081 + *
10082 + * SPDX-License-Identifier: GPL-2.0+
10083 + */
10084 +
10085 +#ifndef __SLEEP_H
10086 +#define __SLEEP_H
10087 +
10088 +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
10089 +#define DDR_BUFF_LEN 128
10090 +
10091 +/* determine if it is a wakeup from deep sleep */
10092 +bool is_warm_boot(void);
10093 +
10094 +/* disable console output */
10095 +void fsl_dp_disable_console(void);
10096 +
10097 +/* clean up everything and jump to kernel */
10098 +int fsl_dp_resume(void);
10099 +#endif
10100 diff -ruN u-boot-2015.01-rc3/board/freescale/ls1021aqds/ddr.c u-boot/board/freescale/ls1021aqds/ddr.c
10101 --- u-boot-2015.01-rc3/board/freescale/ls1021aqds/ddr.c 2014-12-08 22:35:08.000000000 +0100
10102 +++ u-boot/board/freescale/ls1021aqds/ddr.c 2015-01-01 17:34:32.361501481 +0100
10103 @@ -153,9 +153,12 @@
10104 {
10105 phys_size_t dram_size;
10106
10107 +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
10108 puts("Initializing DDR....using SPD\n");
10109 dram_size = fsl_ddr_sdram();
10110 -
10111 +#else
10112 + dram_size = fsl_ddr_sdram_size();
10113 +#endif
10114 return dram_size;
10115 }
10116
10117 diff -ruN u-boot-2015.01-rc3/board/freescale/ls1021aqds/ls1021aqds.c u-boot/board/freescale/ls1021aqds/ls1021aqds.c
10118 --- u-boot-2015.01-rc3/board/freescale/ls1021aqds/ls1021aqds.c 2014-12-08 22:35:08.000000000 +0100
10119 +++ u-boot/board/freescale/ls1021aqds/ls1021aqds.c 2015-01-01 17:34:32.361501481 +0100
10120 @@ -8,12 +8,17 @@
10121 #include <i2c.h>
10122 #include <asm/io.h>
10123 #include <asm/arch/immap_ls102xa.h>
10124 +#include <asm/arch/ns_access.h>
10125 #include <asm/arch/clock.h>
10126 #include <asm/arch/fsl_serdes.h>
10127 +#include <asm/arch/ls102xa_stream_id.h>
10128 +#include <asm/pcie_layerscape.h>
10129 +#include <hwconfig.h>
10130 #include <mmc.h>
10131 #include <fsl_esdhc.h>
10132 #include <fsl_ifc.h>
10133 #include <fsl_sec.h>
10134 +#include <spl.h>
10135
10136 #include "../common/qixis.h"
10137 #include "ls1021aqds_qixis.h"
10138 @@ -21,9 +26,22 @@
10139 #include "../../../drivers/qe/qe.h"
10140 #endif
10141
10142 +#define PIN_MUX_SEL_CAN 0x03
10143 +#define PIN_MUX_SEL_IIC2 0xa0
10144 +#define PIN_MUX_SEL_RGMII 0x00
10145 +#define PIN_MUX_SEL_SAI 0x0c
10146 +#define PIN_MUX_SEL_SDHC 0x00
10147 +
10148 +#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value)
10149 +#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
10150 DECLARE_GLOBAL_DATA_PTR;
10151
10152 enum {
10153 + MUX_TYPE_CAN,
10154 + MUX_TYPE_IIC2,
10155 + MUX_TYPE_RGMII,
10156 + MUX_TYPE_SAI,
10157 + MUX_TYPE_SDHC,
10158 MUX_TYPE_SD_PCI4,
10159 MUX_TYPE_SD_PC_SA_SG_SG,
10160 MUX_TYPE_SD_PC_SA_PC_SG,
10161 @@ -32,11 +50,20 @@
10162
10163 int checkboard(void)
10164 {
10165 +#ifndef CONFIG_QSPI_BOOT
10166 char buf[64];
10167 +#endif
10168 +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
10169 u8 sw;
10170 +#endif
10171
10172 puts("Board: LS1021AQDS\n");
10173
10174 +#ifdef CONFIG_SD_BOOT
10175 + puts("SD\n");
10176 +#elif CONFIG_QSPI_BOOT
10177 + puts("QSPI\n");
10178 +#else
10179 sw = QIXIS_READ(brdcfg[0]);
10180 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
10181
10182 @@ -50,13 +77,16 @@
10183 printf("IFCCard\n");
10184 else
10185 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
10186 +#endif
10187
10188 +#ifndef CONFIG_QSPI_BOOT
10189 printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
10190 QIXIS_READ(id), QIXIS_READ(arch));
10191
10192 printf("FPGA: v%d (%s), build %d\n",
10193 (int)QIXIS_READ(scver), qixis_read_tag(buf),
10194 (int)qixis_read_minor());
10195 +#endif
10196
10197 return 0;
10198 }
10199 @@ -101,8 +131,27 @@
10200 return 66666666;
10201 }
10202
10203 +int select_i2c_ch_pca9547(u8 ch)
10204 +{
10205 + int ret;
10206 +
10207 + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
10208 + if (ret) {
10209 + puts("PCA: failed to select proper channel\n");
10210 + return ret;
10211 + }
10212 +
10213 + return 0;
10214 +}
10215 +
10216 int dram_init(void)
10217 {
10218 + /*
10219 + * When resuming from deep sleep, the I2C channel may not be
10220 + * in the default channel. So, switch to the default channel
10221 + * before accessing DDR SPD.
10222 + */
10223 + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
10224 gd->ram_size = initdram(0);
10225
10226 return 0;
10227 @@ -121,19 +170,6 @@
10228 }
10229 #endif
10230
10231 -int select_i2c_ch_pca9547(u8 ch)
10232 -{
10233 - int ret;
10234 -
10235 - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
10236 - if (ret) {
10237 - puts("PCA: failed to select proper channel\n");
10238 - return ret;
10239 - }
10240 -
10241 - return 0;
10242 -}
10243 -
10244 int board_early_init_f(void)
10245 {
10246 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
10247 @@ -148,6 +184,10 @@
10248 init_early_memctl_regs();
10249 #endif
10250
10251 +#ifdef CONFIG_FSL_QSPI
10252 + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
10253 +#endif
10254 +
10255 /* Workaround for the issue that DDR could not respond to
10256 * barrier transaction which is generated by executing DSB/ISB
10257 * instruction. Set CCI-400 control override register to
10258 @@ -158,13 +198,75 @@
10259 return 0;
10260 }
10261
10262 +#ifdef CONFIG_SPL_BUILD
10263 +void board_init_f(ulong dummy)
10264 +{
10265 + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
10266 +
10267 +#ifdef CONFIG_NAND_BOOT
10268 + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
10269 + u32 porsr1, pinctl;
10270 +
10271 + /*
10272 + * There is LS1 SoC issue where NOR, FPGA are inaccessible during
10273 + * NAND boot because IFC signals > IFC_AD7 are not enabled.
10274 + * This workaround changes RCW source to make all signals enabled.
10275 + */
10276 + porsr1 = in_be32(&gur->porsr1);
10277 + pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
10278 + DCFG_CCSR_PORSR1_RCW_SRC_I2C);
10279 + out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
10280 + pinctl);
10281 +#endif
10282 +
10283 + /* Set global data pointer */
10284 + gd = &gdata;
10285 +
10286 + /* Clear the BSS */
10287 + memset(__bss_start, 0, __bss_end - __bss_start);
10288 +
10289 +#ifdef CONFIG_FSL_IFC
10290 + init_early_memctl_regs();
10291 +#endif
10292 +
10293 + get_clocks();
10294 +
10295 + preloader_console_init();
10296 +
10297 +#ifdef CONFIG_SPL_I2C_SUPPORT
10298 + i2c_init_all();
10299 +#endif
10300 + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
10301 +
10302 + dram_init();
10303 +
10304 + board_init_r(NULL, 0);
10305 +}
10306 +#endif
10307 +
10308 int config_board_mux(int ctrl_type)
10309 {
10310 - u8 reg12;
10311 + u8 reg12, reg14;
10312
10313 reg12 = QIXIS_READ(brdcfg[12]);
10314 + reg14 = QIXIS_READ(brdcfg[14]);
10315
10316 switch (ctrl_type) {
10317 + case MUX_TYPE_CAN:
10318 + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN);
10319 + break;
10320 + case MUX_TYPE_IIC2:
10321 + reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2);
10322 + break;
10323 + case MUX_TYPE_RGMII:
10324 + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII);
10325 + break;
10326 + case MUX_TYPE_SAI:
10327 + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI);
10328 + break;
10329 + case MUX_TYPE_SDHC:
10330 + reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC);
10331 + break;
10332 case MUX_TYPE_SD_PCI4:
10333 reg12 = 0x38;
10334 break;
10335 @@ -183,6 +285,7 @@
10336 }
10337
10338 QIXIS_WRITE(brdcfg[12], reg12);
10339 + QIXIS_WRITE(brdcfg[14], reg14);
10340
10341 return 0;
10342 }
10343 @@ -216,15 +319,154 @@
10344 return 0;
10345 }
10346
10347 -#if defined(CONFIG_MISC_INIT_R)
10348 int misc_init_r(void)
10349 {
10350 + int conflict_flag;
10351 +
10352 + /* some signals can not enable simultaneous*/
10353 + conflict_flag = 0;
10354 + if (hwconfig("sdhc"))
10355 + conflict_flag++;
10356 + if (hwconfig("iic2"))
10357 + conflict_flag++;
10358 + if (conflict_flag > 1) {
10359 + printf("WARNING: pin conflict !\n");
10360 + return 0;
10361 + }
10362 +
10363 + conflict_flag = 0;
10364 + if (hwconfig("rgmii"))
10365 + conflict_flag++;
10366 + if (hwconfig("can"))
10367 + conflict_flag++;
10368 + if (hwconfig("sai"))
10369 + conflict_flag++;
10370 + if (conflict_flag > 1) {
10371 + printf("WARNING: pin conflict !\n");
10372 + return 0;
10373 + }
10374 +
10375 + if (hwconfig("can"))
10376 + config_board_mux(MUX_TYPE_CAN);
10377 + else if (hwconfig("rgmii"))
10378 + config_board_mux(MUX_TYPE_RGMII);
10379 + else if (hwconfig("sai"))
10380 + config_board_mux(MUX_TYPE_SAI);
10381 +
10382 + if (hwconfig("iic2"))
10383 + config_board_mux(MUX_TYPE_IIC2);
10384 + else if (hwconfig("sdhc"))
10385 + config_board_mux(MUX_TYPE_SDHC);
10386 +
10387 #ifdef CONFIG_FSL_CAAM
10388 return sec_init();
10389 #endif
10390 + return 0;
10391 }
10392 +
10393 +#ifdef CONFIG_LS102XA_NS_ACCESS
10394 +static struct csu_ns_dev ns_dev[] = {
10395 + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
10396 + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
10397 + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
10398 + { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
10399 + { CSU_CSLX_OCRAM, CSU_ALL_RW },
10400 + { CSU_CSLX_GIC, CSU_ALL_RW },
10401 + { CSU_CSLX_PCIE1, CSU_ALL_RW },
10402 + { CSU_CSLX_OCRAM2, CSU_ALL_RW },
10403 + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
10404 + { CSU_CSLX_PCIE2, CSU_ALL_RW },
10405 + { CSU_CSLX_SATA, CSU_ALL_RW },
10406 + { CSU_CSLX_USB3, CSU_ALL_RW },
10407 + { CSU_CSLX_SERDES, CSU_ALL_RW },
10408 + { CSU_CSLX_QDMA, CSU_ALL_RW },
10409 + { CSU_CSLX_LPUART2, CSU_ALL_RW },
10410 + { CSU_CSLX_LPUART1, CSU_ALL_RW },
10411 + { CSU_CSLX_LPUART4, CSU_ALL_RW },
10412 + { CSU_CSLX_LPUART3, CSU_ALL_RW },
10413 + { CSU_CSLX_LPUART6, CSU_ALL_RW },
10414 + { CSU_CSLX_LPUART5, CSU_ALL_RW },
10415 + { CSU_CSLX_DSPI2, CSU_ALL_RW },
10416 + { CSU_CSLX_DSPI1, CSU_ALL_RW },
10417 + { CSU_CSLX_QSPI, CSU_ALL_RW },
10418 + { CSU_CSLX_ESDHC, CSU_ALL_RW },
10419 + { CSU_CSLX_2D_ACE, CSU_ALL_RW },
10420 + { CSU_CSLX_IFC, CSU_ALL_RW },
10421 + { CSU_CSLX_I2C1, CSU_ALL_RW },
10422 + { CSU_CSLX_USB2, CSU_ALL_RW },
10423 + { CSU_CSLX_I2C3, CSU_ALL_RW },
10424 + { CSU_CSLX_I2C2, CSU_ALL_RW },
10425 + { CSU_CSLX_DUART2, CSU_ALL_RW },
10426 + { CSU_CSLX_DUART1, CSU_ALL_RW },
10427 + { CSU_CSLX_WDT2, CSU_ALL_RW },
10428 + { CSU_CSLX_WDT1, CSU_ALL_RW },
10429 + { CSU_CSLX_EDMA, CSU_ALL_RW },
10430 + { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
10431 + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
10432 + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
10433 + { CSU_CSLX_DDR, CSU_ALL_RW },
10434 + { CSU_CSLX_QUICC, CSU_ALL_RW },
10435 + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
10436 + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
10437 + { CSU_CSLX_SFP, CSU_ALL_RW },
10438 + { CSU_CSLX_TMU, CSU_ALL_RW },
10439 + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
10440 + { CSU_CSLX_RESERVED0, CSU_ALL_RW },
10441 + { CSU_CSLX_ETSEC1, CSU_ALL_RW },
10442 + { CSU_CSLX_SEC5_5, CSU_ALL_RW },
10443 + { CSU_CSLX_ETSEC3, CSU_ALL_RW },
10444 + { CSU_CSLX_ETSEC2, CSU_ALL_RW },
10445 + { CSU_CSLX_GPIO2, CSU_ALL_RW },
10446 + { CSU_CSLX_GPIO1, CSU_ALL_RW },
10447 + { CSU_CSLX_GPIO4, CSU_ALL_RW },
10448 + { CSU_CSLX_GPIO3, CSU_ALL_RW },
10449 + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
10450 + { CSU_CSLX_CSU, CSU_ALL_RW },
10451 + { CSU_CSLX_ASRC, CSU_ALL_RW },
10452 + { CSU_CSLX_SPDIF, CSU_ALL_RW },
10453 + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
10454 + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
10455 + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
10456 + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
10457 + { CSU_CSLX_SAI2, CSU_ALL_RW },
10458 + { CSU_CSLX_SAI1, CSU_ALL_RW },
10459 + { CSU_CSLX_SAI4, CSU_ALL_RW },
10460 + { CSU_CSLX_SAI3, CSU_ALL_RW },
10461 + { CSU_CSLX_FTM2, CSU_ALL_RW },
10462 + { CSU_CSLX_FTM1, CSU_ALL_RW },
10463 + { CSU_CSLX_FTM4, CSU_ALL_RW },
10464 + { CSU_CSLX_FTM3, CSU_ALL_RW },
10465 + { CSU_CSLX_FTM6, CSU_ALL_RW },
10466 + { CSU_CSLX_FTM5, CSU_ALL_RW },
10467 + { CSU_CSLX_FTM8, CSU_ALL_RW },
10468 + { CSU_CSLX_FTM7, CSU_ALL_RW },
10469 + { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
10470 + { CSU_CSLX_EPU, CSU_ALL_RW },
10471 + { CSU_CSLX_GDI, CSU_ALL_RW },
10472 + { CSU_CSLX_DDI, CSU_ALL_RW },
10473 + { CSU_CSLX_RESERVED1, CSU_ALL_RW },
10474 + { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
10475 + { CSU_CSLX_RESERVED2, CSU_ALL_RW },
10476 +};
10477 #endif
10478
10479 +struct smmu_stream_id dev_stream_id[] = {
10480 + { 0x100, 0x01, "ETSEC MAC1" },
10481 + { 0x104, 0x02, "ETSEC MAC2" },
10482 + { 0x108, 0x03, "ETSEC MAC3" },
10483 + { 0x10c, 0x04, "PEX1" },
10484 + { 0x110, 0x05, "PEX2" },
10485 + { 0x114, 0x06, "qDMA" },
10486 + { 0x118, 0x07, "SATA" },
10487 + { 0x11c, 0x08, "USB3" },
10488 + { 0x120, 0x09, "QE" },
10489 + { 0x124, 0x0a, "eSDHC" },
10490 + { 0x128, 0x0b, "eMA" },
10491 + { 0x14c, 0x0c, "2D-ACE" },
10492 + { 0x150, 0x0d, "USB2" },
10493 + { 0x18c, 0x0e, "DEBUG" },
10494 +};
10495 +
10496 int board_init(void)
10497 {
10498 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
10499 @@ -247,6 +489,13 @@
10500 config_serdes_mux();
10501 #endif
10502
10503 + ls102xa_config_smmu_stream_id(dev_stream_id,
10504 + ARRAY_SIZE(dev_stream_id));
10505 +
10506 +#ifdef CONFIG_LS102XA_NS_ACCESS
10507 + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
10508 +#endif
10509 +
10510 #ifdef CONFIG_U_QE
10511 u_qe_init();
10512 #endif
10513 @@ -258,6 +507,10 @@
10514 {
10515 ft_cpu_setup(blob, bd);
10516
10517 +#ifdef CONFIG_PCIE_LAYERSCAPE
10518 + ft_pcie_setup(blob, bd);
10519 +#endif
10520 +
10521 return 0;
10522 }
10523
10524 diff -ruN u-boot-2015.01-rc3/board/freescale/ls1021aqds/ls102xa_pbi.cfg u-boot/board/freescale/ls1021aqds/ls102xa_pbi.cfg
10525 --- u-boot-2015.01-rc3/board/freescale/ls1021aqds/ls102xa_pbi.cfg 1970-01-01 01:00:00.000000000 +0100
10526 +++ u-boot/board/freescale/ls1021aqds/ls102xa_pbi.cfg 2015-01-01 17:34:32.361501481 +0100
10527 @@ -0,0 +1,12 @@
10528 +#PBI commands
10529 +
10530 +09570200 ffffffff
10531 +09570158 00000300
10532 +8940007c 21f47300
10533 +
10534 +#Configure Scratch register
10535 +09ee0200 10000000
10536 +#Configure alternate space
10537 +09570158 00001000
10538 +#Flush PBL data
10539 +096100c0 000FFFFF
10540 diff -ruN u-boot-2015.01-rc3/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg u-boot/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
10541 --- u-boot-2015.01-rc3/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 1970-01-01 01:00:00.000000000 +0100
10542 +++ u-boot/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg 2015-01-01 17:34:32.361501481 +0100
10543 @@ -0,0 +1,7 @@
10544 +#PBL preamble and RCW header
10545 +aa55aa55 01ee0100
10546 +# serdes protocol
10547 +0608000a 00000000 00000000 00000000
10548 +60000000 00407900 e0106a00 21046000
10549 +00000000 00000000 00000000 00038000
10550 +00000000 001b7200 00000000 00000000
10551 diff -ruN u-boot-2015.01-rc3/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg u-boot/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
10552 --- u-boot-2015.01-rc3/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg 1970-01-01 01:00:00.000000000 +0100
10553 +++ u-boot/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg 2015-01-01 17:34:32.361501481 +0100
10554 @@ -0,0 +1,14 @@
10555 +#PBL preamble and RCW header
10556 +aa55aa55 01ee0100
10557 +
10558 +#enable IFC, disable QSPI and DSPI
10559 +0608000a 00000000 00000000 00000000
10560 +60000000 00407900 60040a00 21046000
10561 +00000000 00000000 00000000 00038000
10562 +00000000 001b7200 00000000 00000000
10563 +
10564 +#disable IFC, enable QSPI and DSPI
10565 +#0608000a 00000000 00000000 00000000
10566 +#60000000 00407900 60040a00 21046000
10567 +#00000000 00000000 00000000 00038000
10568 +#20024800 001b7200 00000000 00000000
10569 diff -ruN u-boot-2015.01-rc3/board/freescale/ls1021aqds/MAINTAINERS u-boot/board/freescale/ls1021aqds/MAINTAINERS
10570 --- u-boot-2015.01-rc3/board/freescale/ls1021aqds/MAINTAINERS 2014-12-08 22:35:08.000000000 +0100
10571 +++ u-boot/board/freescale/ls1021aqds/MAINTAINERS 2015-01-01 17:34:32.361501481 +0100
10572 @@ -6,3 +6,6 @@
10573 F: configs/ls1021aqds_nor_defconfig
10574 F: configs/ls1021aqds_ddr4_nor_defconfig
10575 F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
10576 +F: configs/ls1021aqds_sdcard_defconfig
10577 +F: configs/ls1021aqds_qspi_defconfig
10578 +F: configs/ls1021aqds_nand_defconfig
10579 diff -ruN u-boot-2015.01-rc3/board/freescale/ls1021atwr/ls1021atwr.c u-boot/board/freescale/ls1021atwr/ls1021atwr.c
10580 --- u-boot-2015.01-rc3/board/freescale/ls1021atwr/ls1021atwr.c 2014-12-08 22:35:08.000000000 +0100
10581 +++ u-boot/board/freescale/ls1021atwr/ls1021atwr.c 2015-01-01 17:34:32.361501481 +0100
10582 @@ -8,8 +8,11 @@
10583 #include <i2c.h>
10584 #include <asm/io.h>
10585 #include <asm/arch/immap_ls102xa.h>
10586 +#include <asm/arch/ns_access.h>
10587 #include <asm/arch/clock.h>
10588 #include <asm/arch/fsl_serdes.h>
10589 +#include <asm/arch/ls102xa_stream_id.h>
10590 +#include <asm/pcie_layerscape.h>
10591 #include <mmc.h>
10592 #include <fsl_esdhc.h>
10593 #include <fsl_ifc.h>
10594 @@ -17,6 +20,7 @@
10595 #include <fsl_mdio.h>
10596 #include <tsec.h>
10597 #include <fsl_sec.h>
10598 +#include <spl.h>
10599 #ifdef CONFIG_U_QE
10600 #include "../../../drivers/qe/qe.h"
10601 #endif
10602 @@ -70,6 +74,7 @@
10603 u8 rev2; /* Reserved */
10604 };
10605
10606 +#ifndef CONFIG_QSPI_BOOT
10607 static void convert_serdes_mux(int type, int need_reset);
10608
10609 void cpld_show(void)
10610 @@ -105,11 +110,14 @@
10611 in_8(&cpld_data->serdes_mux));
10612 #endif
10613 }
10614 +#endif
10615
10616 int checkboard(void)
10617 {
10618 puts("Board: LS1021ATWR\n");
10619 +#ifndef CONFIG_QSPI_BOOT
10620 cpld_show();
10621 +#endif
10622
10623 return 0;
10624 }
10625 @@ -218,6 +226,7 @@
10626 }
10627 #endif
10628
10629 +#ifndef CONFIG_QSPI_BOOT
10630 int config_serdes_mux(void)
10631 {
10632 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
10633 @@ -249,6 +258,7 @@
10634
10635 return 0;
10636 }
10637 +#endif
10638
10639 int board_early_init_f(void)
10640 {
10641 @@ -267,9 +277,135 @@
10642 out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
10643 #endif
10644
10645 +#ifdef CONFIG_FSL_QSPI
10646 + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
10647 +#endif
10648 +
10649 return 0;
10650 }
10651
10652 +#ifdef CONFIG_SPL_BUILD
10653 +void board_init_f(ulong dummy)
10654 +{
10655 + /* Set global data pointer */
10656 + gd = &gdata;
10657 +
10658 + /* Clear the BSS */
10659 + memset(__bss_start, 0, __bss_end - __bss_start);
10660 +
10661 + get_clocks();
10662 +
10663 + preloader_console_init();
10664 +
10665 + dram_init();
10666 +
10667 + board_init_r(NULL, 0);
10668 +}
10669 +#endif
10670 +
10671 +#ifdef CONFIG_LS102XA_NS_ACCESS
10672 +static struct csu_ns_dev ns_dev[] = {
10673 + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
10674 + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
10675 + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
10676 + { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
10677 + { CSU_CSLX_OCRAM, CSU_ALL_RW },
10678 + { CSU_CSLX_GIC, CSU_ALL_RW },
10679 + { CSU_CSLX_PCIE1, CSU_ALL_RW },
10680 + { CSU_CSLX_OCRAM2, CSU_ALL_RW },
10681 + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
10682 + { CSU_CSLX_PCIE2, CSU_ALL_RW },
10683 + { CSU_CSLX_SATA, CSU_ALL_RW },
10684 + { CSU_CSLX_USB3, CSU_ALL_RW },
10685 + { CSU_CSLX_SERDES, CSU_ALL_RW },
10686 + { CSU_CSLX_QDMA, CSU_ALL_RW },
10687 + { CSU_CSLX_LPUART2, CSU_ALL_RW },
10688 + { CSU_CSLX_LPUART1, CSU_ALL_RW },
10689 + { CSU_CSLX_LPUART4, CSU_ALL_RW },
10690 + { CSU_CSLX_LPUART3, CSU_ALL_RW },
10691 + { CSU_CSLX_LPUART6, CSU_ALL_RW },
10692 + { CSU_CSLX_LPUART5, CSU_ALL_RW },
10693 + { CSU_CSLX_DSPI2, CSU_ALL_RW },
10694 + { CSU_CSLX_DSPI1, CSU_ALL_RW },
10695 + { CSU_CSLX_QSPI, CSU_ALL_RW },
10696 + { CSU_CSLX_ESDHC, CSU_ALL_RW },
10697 + { CSU_CSLX_2D_ACE, CSU_ALL_RW },
10698 + { CSU_CSLX_IFC, CSU_ALL_RW },
10699 + { CSU_CSLX_I2C1, CSU_ALL_RW },
10700 + { CSU_CSLX_USB2, CSU_ALL_RW },
10701 + { CSU_CSLX_I2C3, CSU_ALL_RW },
10702 + { CSU_CSLX_I2C2, CSU_ALL_RW },
10703 + { CSU_CSLX_DUART2, CSU_ALL_RW },
10704 + { CSU_CSLX_DUART1, CSU_ALL_RW },
10705 + { CSU_CSLX_WDT2, CSU_ALL_RW },
10706 + { CSU_CSLX_WDT1, CSU_ALL_RW },
10707 + { CSU_CSLX_EDMA, CSU_ALL_RW },
10708 + { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
10709 + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
10710 + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
10711 + { CSU_CSLX_DDR, CSU_ALL_RW },
10712 + { CSU_CSLX_QUICC, CSU_ALL_RW },
10713 + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
10714 + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
10715 + { CSU_CSLX_SFP, CSU_ALL_RW },
10716 + { CSU_CSLX_TMU, CSU_ALL_RW },
10717 + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
10718 + { CSU_CSLX_RESERVED0, CSU_ALL_RW },
10719 + { CSU_CSLX_ETSEC1, CSU_ALL_RW },
10720 + { CSU_CSLX_SEC5_5, CSU_ALL_RW },
10721 + { CSU_CSLX_ETSEC3, CSU_ALL_RW },
10722 + { CSU_CSLX_ETSEC2, CSU_ALL_RW },
10723 + { CSU_CSLX_GPIO2, CSU_ALL_RW },
10724 + { CSU_CSLX_GPIO1, CSU_ALL_RW },
10725 + { CSU_CSLX_GPIO4, CSU_ALL_RW },
10726 + { CSU_CSLX_GPIO3, CSU_ALL_RW },
10727 + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
10728 + { CSU_CSLX_CSU, CSU_ALL_RW },
10729 + { CSU_CSLX_ASRC, CSU_ALL_RW },
10730 + { CSU_CSLX_SPDIF, CSU_ALL_RW },
10731 + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
10732 + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
10733 + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
10734 + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
10735 + { CSU_CSLX_SAI2, CSU_ALL_RW },
10736 + { CSU_CSLX_SAI1, CSU_ALL_RW },
10737 + { CSU_CSLX_SAI4, CSU_ALL_RW },
10738 + { CSU_CSLX_SAI3, CSU_ALL_RW },
10739 + { CSU_CSLX_FTM2, CSU_ALL_RW },
10740 + { CSU_CSLX_FTM1, CSU_ALL_RW },
10741 + { CSU_CSLX_FTM4, CSU_ALL_RW },
10742 + { CSU_CSLX_FTM3, CSU_ALL_RW },
10743 + { CSU_CSLX_FTM6, CSU_ALL_RW },
10744 + { CSU_CSLX_FTM5, CSU_ALL_RW },
10745 + { CSU_CSLX_FTM8, CSU_ALL_RW },
10746 + { CSU_CSLX_FTM7, CSU_ALL_RW },
10747 + { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
10748 + { CSU_CSLX_EPU, CSU_ALL_RW },
10749 + { CSU_CSLX_GDI, CSU_ALL_RW },
10750 + { CSU_CSLX_DDI, CSU_ALL_RW },
10751 + { CSU_CSLX_RESERVED1, CSU_ALL_RW },
10752 + { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
10753 + { CSU_CSLX_RESERVED2, CSU_ALL_RW },
10754 +};
10755 +#endif
10756 +
10757 +struct smmu_stream_id dev_stream_id[] = {
10758 + { 0x100, 0x01, "ETSEC MAC1" },
10759 + { 0x104, 0x02, "ETSEC MAC2" },
10760 + { 0x108, 0x03, "ETSEC MAC3" },
10761 + { 0x10c, 0x04, "PEX1" },
10762 + { 0x110, 0x05, "PEX2" },
10763 + { 0x114, 0x06, "qDMA" },
10764 + { 0x118, 0x07, "SATA" },
10765 + { 0x11c, 0x08, "USB3" },
10766 + { 0x120, 0x09, "QE" },
10767 + { 0x124, 0x0a, "eSDHC" },
10768 + { 0x128, 0x0b, "eMA" },
10769 + { 0x14c, 0x0c, "2D-ACE" },
10770 + { 0x150, 0x0d, "USB2" },
10771 + { 0x18c, 0x0e, "DEBUG" },
10772 +};
10773 +
10774 int board_init(void)
10775 {
10776 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
10777 @@ -284,8 +420,17 @@
10778
10779 #ifndef CONFIG_SYS_FSL_NO_SERDES
10780 fsl_serdes_init();
10781 +#ifndef CONFIG_QSPI_BOOT
10782 config_serdes_mux();
10783 #endif
10784 +#endif
10785 +
10786 + ls102xa_config_smmu_stream_id(dev_stream_id,
10787 + ARRAY_SIZE(dev_stream_id));
10788 +
10789 +#ifdef CONFIG_LS102XA_NS_ACCESS
10790 + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
10791 +#endif
10792
10793 #ifdef CONFIG_U_QE
10794 u_qe_init();
10795 @@ -307,6 +452,10 @@
10796 {
10797 ft_cpu_setup(blob, bd);
10798
10799 +#ifdef CONFIG_PCIE_LAYERSCAPE
10800 + ft_pcie_setup(blob, bd);
10801 +#endif
10802 +
10803 return 0;
10804 }
10805
10806 @@ -329,6 +478,7 @@
10807 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
10808 }
10809
10810 +#ifndef CONFIG_QSPI_BOOT
10811 static void convert_flash_bank(char bank)
10812 {
10813 struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
10814 @@ -511,3 +661,4 @@
10815 " -change lane C & lane D to PCIeX2\n"
10816 "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
10817 );
10818 +#endif
10819 diff -ruN u-boot-2015.01-rc3/board/freescale/ls1021atwr/ls102xa_pbi.cfg u-boot/board/freescale/ls1021atwr/ls102xa_pbi.cfg
10820 --- u-boot-2015.01-rc3/board/freescale/ls1021atwr/ls102xa_pbi.cfg 1970-01-01 01:00:00.000000000 +0100
10821 +++ u-boot/board/freescale/ls1021atwr/ls102xa_pbi.cfg 2015-01-01 17:34:32.361501481 +0100
10822 @@ -0,0 +1,12 @@
10823 +#PBI commands
10824 +
10825 +09570200 ffffffff
10826 +09570158 00000300
10827 +8940007c 21f47300
10828 +
10829 +#Configure Scratch register
10830 +09ee0200 10000000
10831 +#Configure alternate space
10832 +09570158 00001000
10833 +#Flush PBL data
10834 +096100c0 000FFFFF
10835 diff -ruN u-boot-2015.01-rc3/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg u-boot/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
10836 --- u-boot-2015.01-rc3/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg 1970-01-01 01:00:00.000000000 +0100
10837 +++ u-boot/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg 2015-01-01 17:34:32.361501481 +0100
10838 @@ -0,0 +1,14 @@
10839 +#PBL preamble and RCW header
10840 +aa55aa55 01ee0100
10841 +
10842 +#enable IFC, disable QSPI and DSPI
10843 +0608000a 00000000 00000000 00000000
10844 +20000000 00407900 60040a00 21046000
10845 +00000000 00000000 00000000 00038000
10846 +00080000 881b7340 00000000 00000000
10847 +
10848 +#disable IFC, enable QSPI and DSPI
10849 +#0608000a 00000000 00000000 00000000
10850 +#20000000 00407900 60040a00 21046000
10851 +#00000000 00000000 00000000 00038000
10852 +#20084800 881b7340 00000000 00000000
10853 diff -ruN u-boot-2015.01-rc3/board/freescale/ls1021atwr/MAINTAINERS u-boot/board/freescale/ls1021atwr/MAINTAINERS
10854 --- u-boot-2015.01-rc3/board/freescale/ls1021atwr/MAINTAINERS 2014-12-08 22:35:08.000000000 +0100
10855 +++ u-boot/board/freescale/ls1021atwr/MAINTAINERS 2015-01-01 17:34:32.361501481 +0100
10856 @@ -5,3 +5,5 @@
10857 F: include/configs/ls1021atwr.h
10858 F: configs/ls1021atwr_nor_defconfig
10859 F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
10860 +F: configs/ls1021atwr_sdcard_defconfig
10861 +F: configs/ls1021atwr_qspi_defconfig
10862 diff -ruN u-boot-2015.01-rc3/board/freescale/mx6slevk/mx6slevk.c u-boot/board/freescale/mx6slevk/mx6slevk.c
10863 --- u-boot-2015.01-rc3/board/freescale/mx6slevk/mx6slevk.c 2014-12-08 22:35:08.000000000 +0100
10864 +++ u-boot/board/freescale/mx6slevk/mx6slevk.c 2015-01-01 17:34:32.381501153 +0100
10865 @@ -20,6 +20,8 @@
10866 #include <fsl_esdhc.h>
10867 #include <mmc.h>
10868 #include <netdev.h>
10869 +#include <usb.h>
10870 +#include <usb/ehci-fsl.h>
10871
10872 DECLARE_GLOBAL_DATA_PTR;
10873
10874 @@ -234,10 +236,52 @@
10875 /* clear gpr1[14], gpr1[18:17] to select anatop clock */
10876 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
10877
10878 - return enable_fec_anatop_clock(ENET_50MHz);
10879 + return enable_fec_anatop_clock(ENET_50MHZ);
10880 }
10881 #endif
10882
10883 +#ifdef CONFIG_USB_EHCI_MX6
10884 +#define USB_OTHERREGS_OFFSET 0x800
10885 +#define UCTRL_PWR_POL (1 << 9)
10886 +
10887 +static iomux_v3_cfg_t const usb_otg_pads[] = {
10888 + /* OTG1 */
10889 + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
10890 + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
10891 + /* OTG2 */
10892 + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
10893 +};
10894 +
10895 +static void setup_usb(void)
10896 +{
10897 + imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
10898 + ARRAY_SIZE(usb_otg_pads));
10899 +}
10900 +
10901 +int board_usb_phy_mode(int port)
10902 +{
10903 + if (port == 1)
10904 + return USB_INIT_HOST;
10905 + else
10906 + return usb_phy_mode(port);
10907 +}
10908 +
10909 +int board_ehci_hcd_init(int port)
10910 +{
10911 + u32 *usbnc_usb_ctrl;
10912 +
10913 + if (port > 1)
10914 + return -EINVAL;
10915 +
10916 + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
10917 + port * 4);
10918 +
10919 + /* Set Power polarity */
10920 + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
10921 +
10922 + return 0;
10923 +}
10924 +#endif
10925
10926 int board_early_init_f(void)
10927 {
10928 @@ -256,6 +300,11 @@
10929 #ifdef CONFIG_FEC_MXC
10930 setup_fec();
10931 #endif
10932 +
10933 +#ifdef CONFIG_USB_EHCI_MX6
10934 + setup_usb();
10935 +#endif
10936 +
10937 return 0;
10938 }
10939
10940 diff -ruN u-boot-2015.01-rc3/board/freescale/mx6sxsabresd/mx6sxsabresd.c u-boot/board/freescale/mx6sxsabresd/mx6sxsabresd.c
10941 --- u-boot-2015.01-rc3/board/freescale/mx6sxsabresd/mx6sxsabresd.c 2014-12-08 22:35:08.000000000 +0100
10942 +++ u-boot/board/freescale/mx6sxsabresd/mx6sxsabresd.c 2015-01-01 17:34:32.381501153 +0100
10943 @@ -26,6 +26,8 @@
10944 #include <power/pmic.h>
10945 #include <power/pfuze100_pmic.h>
10946 #include "../common/pfuze.h"
10947 +#include <usb.h>
10948 +#include <usb/ehci-fsl.h>
10949
10950 DECLARE_GLOBAL_DATA_PTR;
10951
10952 @@ -168,7 +170,7 @@
10953 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
10954 writel(reg, &anatop->pll_enet);
10955
10956 - return enable_fec_anatop_clock(ENET_125MHz);
10957 + return enable_fec_anatop_clock(ENET_125MHZ);
10958 }
10959
10960 int board_eth_init(bd_t *bis)
10961 @@ -212,6 +214,49 @@
10962 return 0;
10963 }
10964
10965 +#ifdef CONFIG_USB_EHCI_MX6
10966 +#define USB_OTHERREGS_OFFSET 0x800
10967 +#define UCTRL_PWR_POL (1 << 9)
10968 +
10969 +static iomux_v3_cfg_t const usb_otg_pads[] = {
10970 + /* OGT1 */
10971 + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
10972 + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
10973 + /* OTG2 */
10974 + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
10975 +};
10976 +
10977 +static void setup_usb(void)
10978 +{
10979 + imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
10980 + ARRAY_SIZE(usb_otg_pads));
10981 +}
10982 +
10983 +int board_usb_phy_mode(int port)
10984 +{
10985 + if (port == 1)
10986 + return USB_INIT_HOST;
10987 + else
10988 + return usb_phy_mode(port);
10989 +}
10990 +
10991 +int board_ehci_hcd_init(int port)
10992 +{
10993 + u32 *usbnc_usb_ctrl;
10994 +
10995 + if (port > 1)
10996 + return -EINVAL;
10997 +
10998 + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
10999 + port * 4);
11000 +
11001 + /* Set Power polarity */
11002 + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
11003 +
11004 + return 0;
11005 +}
11006 +#endif
11007 +
11008 int board_phy_config(struct phy_device *phydev)
11009 {
11010 /*
11011 @@ -242,6 +287,10 @@
11012 /* Active high for ncp692 */
11013 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
11014
11015 +#ifdef CONFIG_USB_EHCI_MX6
11016 + setup_usb();
11017 +#endif
11018 +
11019 return 0;
11020 }
11021
11022 @@ -322,7 +371,6 @@
11023 return 0;
11024 }
11025
11026 -
11027 int board_init(void)
11028 {
11029 /* Address of boot parameters */
11030 diff -ruN u-boot-2015.01-rc3/board/freescale/t104xrdb/ddr.c u-boot/board/freescale/t104xrdb/ddr.c
11031 --- u-boot-2015.01-rc3/board/freescale/t104xrdb/ddr.c 2014-12-08 22:35:08.000000000 +0100
11032 +++ u-boot/board/freescale/t104xrdb/ddr.c 2015-01-01 17:34:32.389501022 +0100
11033 @@ -11,6 +11,7 @@
11034 #include <fsl_ddr_sdram.h>
11035 #include <fsl_ddr_dimm_params.h>
11036 #include <asm/fsl_law.h>
11037 +#include <asm/mpc85xx_gpio.h>
11038 #include "ddr.h"
11039
11040 DECLARE_GLOBAL_DATA_PTR;
11041 @@ -109,6 +110,19 @@
11042 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
11043 }
11044
11045 +#if defined(CONFIG_DEEP_SLEEP)
11046 +void board_mem_sleep_setup(void)
11047 +{
11048 + void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
11049 +
11050 + /* does not provide HW signals for power management */
11051 + clrbits_8(cpld_base + 0x17, 0x40);
11052 + /* Disable MCKE isolation */
11053 + gpio_set_value(2, 0);
11054 + udelay(1);
11055 +}
11056 +#endif
11057 +
11058 phys_size_t initdram(int board_type)
11059 {
11060 phys_size_t dram_size;
11061 @@ -124,5 +138,10 @@
11062 #else
11063 dram_size = fsl_ddr_sdram_size();
11064 #endif
11065 +
11066 +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
11067 + fsl_dp_resume();
11068 +#endif
11069 +
11070 return dram_size;
11071 }
11072 diff -ruN u-boot-2015.01-rc3/board/freescale/t104xrdb/spl.c u-boot/board/freescale/t104xrdb/spl.c
11073 --- u-boot-2015.01-rc3/board/freescale/t104xrdb/spl.c 2014-12-08 22:35:08.000000000 +0100
11074 +++ u-boot/board/freescale/t104xrdb/spl.c 2015-01-01 17:34:32.389501022 +0100
11075 @@ -11,7 +11,7 @@
11076 #include <mmc.h>
11077 #include <fsl_esdhc.h>
11078 #include <spi_flash.h>
11079 -#include <asm/mpc85xx_gpio.h>
11080 +#include "../common/sleep.h"
11081
11082 DECLARE_GLOBAL_DATA_PTR;
11083
11084 @@ -64,8 +64,8 @@
11085
11086 #ifdef CONFIG_DEEP_SLEEP
11087 /* disable the console if boot from deep sleep */
11088 - if (in_be32(&gur->scrtsr[0]) & (1 << 3))
11089 - gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
11090 + if (is_warm_boot())
11091 + fsl_dp_disable_console();
11092 #endif
11093 /* compiler optimization barrier needed for GCC >= 3.4 */
11094 __asm__ __volatile__("" : : : "memory");
11095 @@ -132,16 +132,3 @@
11096 nand_boot();
11097 #endif
11098 }
11099 -
11100 -#ifdef CONFIG_DEEP_SLEEP
11101 -void board_mem_sleep_setup(void)
11102 -{
11103 - void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
11104 -
11105 - /* does not provide HW signals for power management */
11106 - clrbits_8(cpld_base + 0x17, 0x40);
11107 - /* Disable MCKE isolation */
11108 - gpio_set_value(2, 0);
11109 - udelay(1);
11110 -}
11111 -#endif
11112 diff -ruN u-boot-2015.01-rc3/board/freescale/t104xrdb/t104xrdb.c u-boot/board/freescale/t104xrdb/t104xrdb.c
11113 --- u-boot-2015.01-rc3/board/freescale/t104xrdb/t104xrdb.c 2014-12-08 22:35:08.000000000 +0100
11114 +++ u-boot/board/freescale/t104xrdb/t104xrdb.c 2015-01-01 17:34:32.389501022 +0100
11115 @@ -17,8 +17,7 @@
11116 #include <asm/fsl_portals.h>
11117 #include <asm/fsl_liodn.h>
11118 #include <fm_eth.h>
11119 -#include <asm/mpc85xx_gpio.h>
11120 -
11121 +#include "../common/sleep.h"
11122 #include "t104xrdb.h"
11123 #include "cpld.h"
11124
11125 @@ -44,6 +43,16 @@
11126 return 0;
11127 }
11128
11129 +int board_early_init_f(void)
11130 +{
11131 +#if defined(CONFIG_DEEP_SLEEP)
11132 + if (is_warm_boot())
11133 + fsl_dp_disable_console();
11134 +#endif
11135 +
11136 + return 0;
11137 +}
11138 +
11139 int board_early_init_r(void)
11140 {
11141 #ifdef CONFIG_SYS_FLASH_BASE
11142 @@ -113,14 +122,3 @@
11143
11144 return 0;
11145 }
11146 -
11147 -#ifdef CONFIG_DEEP_SLEEP
11148 -void board_mem_sleep_setup(void)
11149 -{
11150 - /* does not provide HW signals for power management */
11151 - CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
11152 - /* Disable MCKE isolation */
11153 - gpio_set_value(2, 0);
11154 - udelay(1);
11155 -}
11156 -#endif
11157 diff -ruN u-boot-2015.01-rc3/board/google/chromebook_link/Kconfig u-boot/board/google/chromebook_link/Kconfig
11158 --- u-boot-2015.01-rc3/board/google/chromebook_link/Kconfig 2014-12-08 22:35:08.000000000 +0100
11159 +++ u-boot/board/google/chromebook_link/Kconfig 2015-01-01 17:34:32.401500826 +0100
11160 @@ -19,6 +19,7 @@
11161 select SOUTHBRIDGE_INTEL_C216
11162 select HAVE_ACPI_RESUME
11163 select MARK_GRAPHICS_MEM_WRCOMB
11164 + select BOARD_ROMSIZE_KB_8192
11165
11166 config MMCONF_BASE_ADDRESS
11167 hex
11168 diff -ruN u-boot-2015.01-rc3/board/google/chromebook_link/link.c u-boot/board/google/chromebook_link/link.c
11169 --- u-boot-2015.01-rc3/board/google/chromebook_link/link.c 2014-12-08 22:35:08.000000000 +0100
11170 +++ u-boot/board/google/chromebook_link/link.c 2015-01-01 17:34:32.401500826 +0100
11171 @@ -7,6 +7,9 @@
11172 #include <common.h>
11173 #include <cros_ec.h>
11174 #include <asm/gpio.h>
11175 +#include <asm/io.h>
11176 +#include <asm/pci.h>
11177 +#include <asm/arch/pch.h>
11178
11179 int arch_early_init_r(void)
11180 {
11181 @@ -121,3 +124,40 @@
11182
11183 return 0;
11184 }
11185 +
11186 +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
11187 +{
11188 + /* GPIO Set 1 */
11189 + if (gpio->set1.level)
11190 + outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
11191 + if (gpio->set1.mode)
11192 + outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
11193 + if (gpio->set1.direction)
11194 + outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
11195 + if (gpio->set1.reset)
11196 + outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
11197 + if (gpio->set1.invert)
11198 + outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
11199 + if (gpio->set1.blink)
11200 + outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
11201 +
11202 + /* GPIO Set 2 */
11203 + if (gpio->set2.level)
11204 + outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
11205 + if (gpio->set2.mode)
11206 + outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
11207 + if (gpio->set2.direction)
11208 + outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
11209 + if (gpio->set2.reset)
11210 + outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
11211 +
11212 + /* GPIO Set 3 */
11213 + if (gpio->set3.level)
11214 + outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
11215 + if (gpio->set3.mode)
11216 + outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
11217 + if (gpio->set3.direction)
11218 + outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
11219 + if (gpio->set3.reset)
11220 + outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
11221 +}
11222 diff -ruN u-boot-2015.01-rc3/board/intel/crownbay/crownbay.c u-boot/board/intel/crownbay/crownbay.c
11223 --- u-boot-2015.01-rc3/board/intel/crownbay/crownbay.c 1970-01-01 01:00:00.000000000 +0100
11224 +++ u-boot/board/intel/crownbay/crownbay.c 2015-01-01 17:34:32.405500760 +0100
11225 @@ -0,0 +1,32 @@
11226 +/*
11227 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
11228 + *
11229 + * SPDX-License-Identifier: GPL-2.0+
11230 + */
11231 +
11232 +#include <common.h>
11233 +#include <asm/ibmpc.h>
11234 +#include <asm/pnp_def.h>
11235 +#include <netdev.h>
11236 +#include <smsc_lpc47m.h>
11237 +
11238 +#define SERIAL_DEV PNP_DEV(0x2e, 4)
11239 +
11240 +DECLARE_GLOBAL_DATA_PTR;
11241 +
11242 +int board_early_init_f(void)
11243 +{
11244 + lpc47m_enable_serial(SERIAL_DEV, UART0_BASE);
11245 +
11246 + return 0;
11247 +}
11248 +
11249 +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
11250 +{
11251 + return;
11252 +}
11253 +
11254 +int board_eth_init(bd_t *bis)
11255 +{
11256 + return pci_eth_init(bis);
11257 +}
11258 diff -ruN u-boot-2015.01-rc3/board/intel/crownbay/Kconfig u-boot/board/intel/crownbay/Kconfig
11259 --- u-boot-2015.01-rc3/board/intel/crownbay/Kconfig 1970-01-01 01:00:00.000000000 +0100
11260 +++ u-boot/board/intel/crownbay/Kconfig 2015-01-01 17:34:32.405500760 +0100
11261 @@ -0,0 +1,20 @@
11262 +if TARGET_CROWNBAY
11263 +
11264 +config SYS_BOARD
11265 + default "crownbay"
11266 +
11267 +config SYS_VENDOR
11268 + default "intel"
11269 +
11270 +config SYS_SOC
11271 + default "queensbay"
11272 +
11273 +config SYS_CONFIG_NAME
11274 + default "crownbay"
11275 +
11276 +config BOARD_SPECIFIC_OPTIONS # dummy
11277 + def_bool y
11278 + select INTEL_QUEENSBAY
11279 + select BOARD_ROMSIZE_KB_1024
11280 +
11281 +endif
11282 diff -ruN u-boot-2015.01-rc3/board/intel/crownbay/MAINTAINERS u-boot/board/intel/crownbay/MAINTAINERS
11283 --- u-boot-2015.01-rc3/board/intel/crownbay/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100
11284 +++ u-boot/board/intel/crownbay/MAINTAINERS 2015-01-01 17:34:32.405500760 +0100
11285 @@ -0,0 +1,6 @@
11286 +INTEL CROWNBAY BOARD
11287 +M: Bin Meng <bmeng.cn@gmail.com>
11288 +S: Maintained
11289 +F: board/intel/crownbay/
11290 +F: include/configs/crownbay.h
11291 +F: configs/crownbay_defconfig
11292 diff -ruN u-boot-2015.01-rc3/board/intel/crownbay/Makefile u-boot/board/intel/crownbay/Makefile
11293 --- u-boot-2015.01-rc3/board/intel/crownbay/Makefile 1970-01-01 01:00:00.000000000 +0100
11294 +++ u-boot/board/intel/crownbay/Makefile 2015-01-01 17:34:32.405500760 +0100
11295 @@ -0,0 +1,7 @@
11296 +#
11297 +# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
11298 +#
11299 +# SPDX-License-Identifier: GPL-2.0+
11300 +#
11301 +
11302 +obj-y += crownbay.o start.o
11303 diff -ruN u-boot-2015.01-rc3/board/intel/crownbay/start.S u-boot/board/intel/crownbay/start.S
11304 --- u-boot-2015.01-rc3/board/intel/crownbay/start.S 1970-01-01 01:00:00.000000000 +0100
11305 +++ u-boot/board/intel/crownbay/start.S 2015-01-01 17:34:32.405500760 +0100
11306 @@ -0,0 +1,9 @@
11307 +/*
11308 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
11309 + *
11310 + * SPDX-License-Identifier: GPL-2.0+
11311 + */
11312 +
11313 +.globl early_board_init
11314 +early_board_init:
11315 + jmp early_board_init_ret
11316 diff -ruN u-boot-2015.01-rc3/board/nvidia/cardhu/cardhu.c u-boot/board/nvidia/cardhu/cardhu.c
11317 --- u-boot-2015.01-rc3/board/nvidia/cardhu/cardhu.c 2014-12-08 22:35:08.000000000 +0100
11318 +++ u-boot/board/nvidia/cardhu/cardhu.c 2015-01-01 17:34:32.449500039 +0100
11319 @@ -6,6 +6,7 @@
11320 */
11321
11322 #include <common.h>
11323 +#include <dm.h>
11324 #include <asm/arch/pinmux.h>
11325 #include <asm/arch/gp_padctrl.h>
11326 #include "pinmux-config-cardhu.h"
11327 @@ -37,17 +38,23 @@
11328 */
11329 void board_sdmmc_voltage_init(void)
11330 {
11331 + struct udevice *dev;
11332 uchar reg, data_buffer[1];
11333 + int ret;
11334 int i;
11335
11336 - i2c_set_bus_num(0); /* PMU is on bus 0 */
11337 + ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
11338 + if (ret) {
11339 + debug("%s: Cannot find PMIC I2C chip\n", __func__);
11340 + return;
11341 + }
11342
11343 /* TPS659110: LDO5_REG = 3.3v, ACTIVE to SDMMC1 */
11344 data_buffer[0] = 0x65;
11345 reg = 0x32;
11346
11347 for (i = 0; i < MAX_I2C_RETRY; ++i) {
11348 - if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
11349 + if (i2c_write(dev, reg, data_buffer, 1))
11350 udelay(100);
11351 }
11352
11353 @@ -56,7 +63,7 @@
11354 reg = 0x67;
11355
11356 for (i = 0; i < MAX_I2C_RETRY; ++i) {
11357 - if (i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1))
11358 + if (i2c_write(dev, reg, data_buffer, 1))
11359 udelay(100);
11360 }
11361 }
11362 diff -ruN u-boot-2015.01-rc3/board/nvidia/common/board.c u-boot/board/nvidia/common/board.c
11363 --- u-boot-2015.01-rc3/board/nvidia/common/board.c 2014-12-08 22:35:08.000000000 +0100
11364 +++ u-boot/board/nvidia/common/board.c 2015-01-01 17:34:32.453499973 +0100
11365 @@ -113,10 +113,6 @@
11366 power_det_init();
11367
11368 #ifdef CONFIG_SYS_I2C_TEGRA
11369 -#ifndef CONFIG_SYS_I2C_INIT_BOARD
11370 -#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards"
11371 -#endif
11372 - i2c_init_board();
11373 # ifdef CONFIG_TEGRA_PMU
11374 if (pmu_set_nominal())
11375 debug("Failed to select nominal voltages\n");
11376 diff -ruN u-boot-2015.01-rc3/board/nvidia/dalmore/dalmore.c u-boot/board/nvidia/dalmore/dalmore.c
11377 --- u-boot-2015.01-rc3/board/nvidia/dalmore/dalmore.c 2014-12-08 22:35:08.000000000 +0100
11378 +++ u-boot/board/nvidia/dalmore/dalmore.c 2015-01-01 17:34:32.453499973 +0100
11379 @@ -15,6 +15,7 @@
11380 */
11381
11382 #include <common.h>
11383 +#include <dm.h>
11384 #include <asm/arch/pinmux.h>
11385 #include <asm/arch/gp_padctrl.h>
11386 #include "pinmux-config-dalmore.h"
11387 @@ -50,18 +51,21 @@
11388 */
11389 void board_sdmmc_voltage_init(void)
11390 {
11391 + struct udevice *dev;
11392 uchar reg, data_buffer[1];
11393 int ret;
11394
11395 - ret = i2c_set_bus_num(0);/* PMU is on bus 0 */
11396 - if (ret)
11397 - printf("%s: i2c_set_bus_num returned %d\n", __func__, ret);
11398 + ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
11399 + if (ret) {
11400 + debug("%s: Cannot find PMIC I2C chip\n", __func__);
11401 + return;
11402 + }
11403
11404 /* TPS65913: LDO9_VOLTAGE = 3.3V */
11405 data_buffer[0] = 0x31;
11406 reg = 0x61;
11407
11408 - ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1);
11409 + ret = i2c_write(dev, reg, data_buffer, 1);
11410 if (ret)
11411 printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
11412 __func__, reg, data_buffer[0], ret);
11413 @@ -70,7 +74,7 @@
11414 data_buffer[0] = 0x01;
11415 reg = 0x60;
11416
11417 - ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1);
11418 + ret = i2c_write(dev, reg, data_buffer, 1);
11419 if (ret)
11420 printf("%s: PMU i2c_write %02X<-%02X returned %d\n",
11421 __func__, reg, data_buffer[0], ret);
11422 @@ -79,7 +83,12 @@
11423 data_buffer[0] = 0x03;
11424 reg = 0x14;
11425
11426 - ret = i2c_write(BAT_I2C_ADDRESS, reg, 1, data_buffer, 1);
11427 + ret = i2c_get_chip_for_busnum(0, BAT_I2C_ADDRESS, &dev);
11428 + if (ret) {
11429 + debug("%s: Cannot find charger I2C chip\n", __func__);
11430 + return;
11431 + }
11432 + ret = i2c_write(dev, reg, data_buffer, 1);
11433 if (ret)
11434 printf("%s: BAT i2c_write %02X<-%02X returned %d\n",
11435 __func__, reg, data_buffer[0], ret);
11436 diff -ruN u-boot-2015.01-rc3/board/nvidia/nyan-big/Kconfig u-boot/board/nvidia/nyan-big/Kconfig
11437 --- u-boot-2015.01-rc3/board/nvidia/nyan-big/Kconfig 1970-01-01 01:00:00.000000000 +0100
11438 +++ u-boot/board/nvidia/nyan-big/Kconfig 2015-01-01 17:34:32.453499973 +0100
11439 @@ -0,0 +1,24 @@
11440 +if TARGET_NYAN_BIG
11441 +
11442 +config SYS_CPU
11443 + string
11444 + default "arm720t" if SPL_BUILD
11445 + default "armv7" if !SPL_BUILD
11446 +
11447 +config SYS_BOARD
11448 + string
11449 + default "nyan-big"
11450 +
11451 +config SYS_VENDOR
11452 + string
11453 + default "nvidia"
11454 +
11455 +config SYS_SOC
11456 + string
11457 + default "tegra124"
11458 +
11459 +config SYS_CONFIG_NAME
11460 + string
11461 + default "nyan-big"
11462 +
11463 +endif
11464 diff -ruN u-boot-2015.01-rc3/board/nvidia/nyan-big/MAINTAINERS u-boot/board/nvidia/nyan-big/MAINTAINERS
11465 --- u-boot-2015.01-rc3/board/nvidia/nyan-big/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100
11466 +++ u-boot/board/nvidia/nyan-big/MAINTAINERS 2015-01-01 17:34:32.453499973 +0100
11467 @@ -0,0 +1,6 @@
11468 +NORRIN BOARD
11469 +M: Allen Martin <amartin@nvidia.com>
11470 +S: Maintained
11471 +F: board/nvidia/nyan-big/
11472 +F: include/configs/nyan-big.h
11473 +F: configs/nyan-big_defconfig
11474 diff -ruN u-boot-2015.01-rc3/board/nvidia/nyan-big/Makefile u-boot/board/nvidia/nyan-big/Makefile
11475 --- u-boot-2015.01-rc3/board/nvidia/nyan-big/Makefile 1970-01-01 01:00:00.000000000 +0100
11476 +++ u-boot/board/nvidia/nyan-big/Makefile 2015-01-01 17:34:32.453499973 +0100
11477 @@ -0,0 +1,9 @@
11478 +#
11479 +# (C) Copyright 2014
11480 +# NVIDIA Corporation <www.nvidia.com>
11481 +#
11482 +# SPDX-License-Identifier: GPL-2.0+
11483 +#
11484 +
11485 +obj-y += ../venice2/as3722_init.o
11486 +obj-y += nyan-big.o
11487 diff -ruN u-boot-2015.01-rc3/board/nvidia/nyan-big/nyan-big.c u-boot/board/nvidia/nyan-big/nyan-big.c
11488 --- u-boot-2015.01-rc3/board/nvidia/nyan-big/nyan-big.c 1970-01-01 01:00:00.000000000 +0100
11489 +++ u-boot/board/nvidia/nyan-big/nyan-big.c 2015-01-01 17:34:32.453499973 +0100
11490 @@ -0,0 +1,27 @@
11491 +/*
11492 + * (C) Copyright 2014
11493 + * NVIDIA Corporation <www.nvidia.com>
11494 + *
11495 + * SPDX-License-Identifier: GPL-2.0+
11496 + */
11497 +
11498 +#include <common.h>
11499 +#include <asm/arch/gpio.h>
11500 +#include <asm/arch/pinmux.h>
11501 +#include "pinmux-config-nyan-big.h"
11502 +
11503 +/*
11504 + * Routine: pinmux_init
11505 + * Description: Do individual peripheral pinmux configs
11506 + */
11507 +void pinmux_init(void)
11508 +{
11509 + gpio_config_table(nyan_big_gpio_inits,
11510 + ARRAY_SIZE(nyan_big_gpio_inits));
11511 +
11512 + pinmux_config_pingrp_table(nyan_big_pingrps,
11513 + ARRAY_SIZE(nyan_big_pingrps));
11514 +
11515 + pinmux_config_drvgrp_table(nyan_big_drvgrps,
11516 + ARRAY_SIZE(nyan_big_drvgrps));
11517 +}
11518 diff -ruN u-boot-2015.01-rc3/board/nvidia/nyan-big/pinmux-config-nyan-big.h u-boot/board/nvidia/nyan-big/pinmux-config-nyan-big.h
11519 --- u-boot-2015.01-rc3/board/nvidia/nyan-big/pinmux-config-nyan-big.h 1970-01-01 01:00:00.000000000 +0100
11520 +++ u-boot/board/nvidia/nyan-big/pinmux-config-nyan-big.h 2015-01-01 17:34:32.453499973 +0100
11521 @@ -0,0 +1,287 @@
11522 +/*
11523 + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
11524 + *
11525 + * SPDX-License-Identifier: GPL-2.0+
11526 + */
11527 +
11528 +#ifndef _PINMUX_CONFIG_NYAN_BIG_H_
11529 +#define _PINMUX_CONFIG_NYAN_BIG_H_
11530 +
11531 +#define GPIO_INIT(_gpio, _init) \
11532 + { \
11533 + .gpio = GPIO_P##_gpio, \
11534 + .init = TEGRA_GPIO_INIT_##_init, \
11535 + }
11536 +
11537 +static const struct tegra_gpio_config nyan_big_gpio_inits[] = {
11538 + /* gpio, init_val */
11539 + GPIO_INIT(A0, IN),
11540 + GPIO_INIT(C7, IN),
11541 + GPIO_INIT(G0, IN),
11542 + GPIO_INIT(G1, IN),
11543 + GPIO_INIT(G2, IN),
11544 + GPIO_INIT(G3, IN),
11545 + GPIO_INIT(H2, IN),
11546 + GPIO_INIT(H4, IN),
11547 + GPIO_INIT(H6, IN),
11548 + GPIO_INIT(H7, OUT1),
11549 + GPIO_INIT(I0, IN),
11550 + GPIO_INIT(I1, IN),
11551 + GPIO_INIT(I5, OUT1),
11552 + GPIO_INIT(I6, IN),
11553 + GPIO_INIT(I7, IN),
11554 + GPIO_INIT(J0, IN),
11555 + GPIO_INIT(J7, IN),
11556 + GPIO_INIT(K1, OUT0),
11557 + GPIO_INIT(K2, IN),
11558 + GPIO_INIT(K4, OUT0),
11559 + GPIO_INIT(K6, OUT0),
11560 + GPIO_INIT(K7, IN),
11561 + GPIO_INIT(N7, IN),
11562 + GPIO_INIT(P2, OUT0),
11563 + GPIO_INIT(Q0, IN),
11564 + GPIO_INIT(Q2, IN),
11565 + GPIO_INIT(Q3, IN),
11566 + GPIO_INIT(Q6, IN),
11567 + GPIO_INIT(Q7, IN),
11568 + GPIO_INIT(R0, OUT0),
11569 + GPIO_INIT(R1, IN),
11570 + GPIO_INIT(R4, IN),
11571 + GPIO_INIT(R7, IN),
11572 + GPIO_INIT(S3, OUT0),
11573 + GPIO_INIT(S4, OUT0),
11574 + GPIO_INIT(S7, IN),
11575 + GPIO_INIT(T1, IN),
11576 + GPIO_INIT(U4, IN),
11577 + GPIO_INIT(U5, IN),
11578 + GPIO_INIT(U6, IN),
11579 + GPIO_INIT(V0, IN),
11580 + GPIO_INIT(W3, IN),
11581 + GPIO_INIT(X1, IN),
11582 + GPIO_INIT(X4, IN),
11583 + GPIO_INIT(X7, OUT0),
11584 +};
11585 +
11586 +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
11587 + { \
11588 + .pingrp = PMUX_PINGRP_##_pingrp, \
11589 + .func = PMUX_FUNC_##_mux, \
11590 + .pull = PMUX_PULL_##_pull, \
11591 + .tristate = PMUX_TRI_##_tri, \
11592 + .io = PMUX_PIN_##_io, \
11593 + .od = PMUX_PIN_OD_##_od, \
11594 + .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
11595 + .lock = PMUX_PIN_LOCK_DEFAULT, \
11596 + .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
11597 + }
11598 +
11599 +static const struct pmux_pingrp_config nyan_big_pingrps[] = {
11600 + /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
11601 + PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11602 + PINCFG(UART3_CTS_N_PA1, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11603 + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11604 + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11605 + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11606 + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11607 + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11608 + PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11609 + PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11610 + PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11611 + PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11612 + PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11613 + PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11614 + PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11615 + PINCFG(UART3_RTS_N_PC0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11616 + PINCFG(UART2_TXD_PC2, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11617 + PINCFG(UART2_RXD_PC3, IRDA, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11618 + PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
11619 + PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
11620 + PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11621 + PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11622 + PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11623 + PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11624 + PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11625 + PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11626 + PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11627 + PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11628 + PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11629 + PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11630 + PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11631 + PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11632 + PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11633 + PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11634 + PINCFG(PH5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11635 + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11636 + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11637 + PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11638 + PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11639 + PINCFG(PI2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11640 + PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11641 + PINCFG(PI4, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11642 + PINCFG(PI5, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11643 + PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11644 + PINCFG(PI7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11645 + PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11646 + PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11647 + PINCFG(UART2_CTS_N_PJ5, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11648 + PINCFG(UART2_RTS_N_PJ6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11649 + PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11650 + PINCFG(PK0, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11651 + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11652 + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11653 + PINCFG(PK3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11654 + PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11655 + PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11656 + PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11657 + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11658 + PINCFG(DAP1_FS_PN0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11659 + PINCFG(DAP1_DIN_PN1, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11660 + PINCFG(DAP1_DOUT_PN2, I2S0, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11661 + PINCFG(DAP1_SCLK_PN3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11662 + PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
11663 + PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
11664 + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
11665 + PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11666 + PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11667 + PINCFG(ULPI_DATA1_PO2, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11668 + PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11669 + PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11670 + PINCFG(ULPI_DATA4_PO5, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11671 + PINCFG(ULPI_DATA5_PO6, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11672 + PINCFG(ULPI_DATA6_PO7, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11673 + PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11674 + PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11675 + PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11676 + PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11677 + PINCFG(DAP4_FS_PP4, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11678 + PINCFG(DAP4_DIN_PP5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11679 + PINCFG(DAP4_DOUT_PP6, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11680 + PINCFG(DAP4_SCLK_PP7, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11681 + PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11682 + PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11683 + PINCFG(KB_COL2_PQ2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11684 + PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11685 + PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11686 + PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11687 + PINCFG(KB_COL6_PQ6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11688 + PINCFG(KB_COL7_PQ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11689 + PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11690 + PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11691 + PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11692 + PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11693 + PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11694 + PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11695 + PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11696 + PINCFG(KB_ROW7_PR7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11697 + PINCFG(KB_ROW8_PS0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11698 + PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11699 + PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11700 + PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11701 + PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11702 + PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11703 + PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11704 + PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11705 + PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11706 + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11707 + PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
11708 + PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
11709 + PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11710 + PINCFG(PU0, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11711 + PINCFG(PU1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11712 + PINCFG(PU2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11713 + PINCFG(PU3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11714 + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11715 + PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11716 + PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11717 + PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11718 + PINCFG(PV1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11719 + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11720 + PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11721 + PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
11722 + PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
11723 + PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11724 + PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11725 + PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11726 + PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11727 + PINCFG(UART3_TXD_PW6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11728 + PINCFG(UART3_RXD_PW7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11729 + PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11730 + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11731 + PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11732 + PINCFG(GPIO_X3_AUD_PX3, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11733 + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11734 + PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11735 + PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11736 + PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11737 + PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11738 + PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11739 + PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11740 + PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11741 + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11742 + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11743 + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11744 + PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11745 + PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11746 + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11747 + PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
11748 + PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
11749 + PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11750 + PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11751 + PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11752 + PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11753 + PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11754 + PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11755 + PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11756 + PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11757 + PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11758 + PINCFG(CAM_I2C_SCL_PBB1, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
11759 + PINCFG(CAM_I2C_SDA_PBB2, RSVD3, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
11760 + PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11761 + PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11762 + PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11763 + PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11764 + PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11765 + PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11766 + PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11767 + PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11768 + PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11769 + PINCFG(CLK2_REQ_PCC5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11770 + PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11771 + PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11772 + PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11773 + PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11774 + PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11775 + PINCFG(CLK3_OUT_PEE0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11776 + PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11777 + PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
11778 + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
11779 + PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11780 + PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11781 + PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
11782 + PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
11783 + PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
11784 + PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11785 + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11786 + PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11787 + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11788 + PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
11789 + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
11790 + PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
11791 +};
11792 +
11793 +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
11794 + { \
11795 + .drvgrp = PMUX_DRVGRP_##_drvgrp, \
11796 + .slwf = _slwf, \
11797 + .slwr = _slwr, \
11798 + .drvup = _drvup, \
11799 + .drvdn = _drvdn, \
11800 + .lpmd = PMUX_LPMD_##_lpmd, \
11801 + .schmt = PMUX_SCHMT_##_schmt, \
11802 + .hsm = PMUX_HSM_##_hsm, \
11803 + }
11804 +
11805 +static const struct pmux_drvgrp_config nyan_big_drvgrps[] = {
11806 +};
11807 +
11808 +#endif /* PINMUX_CONFIG_NYAN_BIG_H */
11809 diff -ruN u-boot-2015.01-rc3/board/nvidia/venice2/as3722_init.h u-boot/board/nvidia/venice2/as3722_init.h
11810 --- u-boot-2015.01-rc3/board/nvidia/venice2/as3722_init.h 2014-12-08 22:35:08.000000000 +0100
11811 +++ u-boot/board/nvidia/venice2/as3722_init.h 2015-01-01 17:34:32.453499973 +0100
11812 @@ -18,7 +18,7 @@
11813 #define AS3722_LDO6VOLTAGE_REG 0x16 /* VDD_SDMMC */
11814 #define AS3722_LDCONTROL_REG 0x4E
11815
11816 -#ifdef CONFIG_TARGET_JETSON_TK1
11817 +#if defined(CONFIG_TARGET_JETSON_TK1) || defined(CONFIG_TARGET_NYAN_BIG)
11818 #define AS3722_SD0VOLTAGE_DATA (0x3C00 | AS3722_SD0VOLTAGE_REG)
11819 #else
11820 #define AS3722_SD0VOLTAGE_DATA (0x2800 | AS3722_SD0VOLTAGE_REG)
11821 diff -ruN u-boot-2015.01-rc3/board/nvidia/whistler/whistler.c u-boot/board/nvidia/whistler/whistler.c
11822 --- u-boot-2015.01-rc3/board/nvidia/whistler/whistler.c 2014-12-08 22:35:08.000000000 +0100
11823 +++ u-boot/board/nvidia/whistler/whistler.c 2015-01-01 17:34:32.453499973 +0100
11824 @@ -6,6 +6,7 @@
11825 */
11826
11827 #include <common.h>
11828 +#include <dm.h>
11829 #include <asm/io.h>
11830 #include <asm/arch/tegra.h>
11831 #include <asm/arch/clock.h>
11832 @@ -21,23 +22,26 @@
11833 */
11834 void pin_mux_mmc(void)
11835 {
11836 + struct udevice *dev;
11837 uchar val;
11838 int ret;
11839
11840 /* Turn on MAX8907B LDO12 to 2.8V for J40 power */
11841 - ret = i2c_set_bus_num(0);
11842 - if (ret)
11843 - printf("i2c_set_bus_num failed: %d\n", ret);
11844 + ret = i2c_get_chip_for_busnum(0, 0x3c, &dev);
11845 + if (ret) {
11846 + printf("%s: Cannot find MAX8907B I2C chip\n", __func__);
11847 + return;
11848 + }
11849 val = 0x29;
11850 - ret = i2c_write(0x3c, 0x46, 1, &val, 1);
11851 + ret = i2c_write(dev, 0x46, &val, 1);
11852 if (ret)
11853 printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret);
11854 val = 0x00;
11855 - ret = i2c_write(0x3c, 0x45, 1, &val, 1);
11856 + ret = i2c_write(dev, 0x45, &val, 1);
11857 if (ret)
11858 printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret);
11859 val = 0x1f;
11860 - ret = i2c_write(0x3c, 0x44, 1, &val, 1);
11861 + ret = i2c_write(dev, 0x44, &val, 1);
11862 if (ret)
11863 printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret);
11864
11865 @@ -49,6 +53,7 @@
11866 /* this is a weak define that we are overriding */
11867 void pin_mux_usb(void)
11868 {
11869 + struct udevice *dev;
11870 uchar val;
11871 int ret;
11872
11873 @@ -59,15 +64,17 @@
11874 */
11875
11876 /* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */
11877 - ret = i2c_set_bus_num(0);
11878 - if (ret)
11879 - printf("i2c_set_bus_num failed: %d\n", ret);
11880 + ret = i2c_get_chip_for_busnum(0, 0x20, &dev);
11881 + if (ret) {
11882 + printf("%s: Cannot find TAC6416 I2C chip\n", __func__);
11883 + return;
11884 + }
11885 val = 0x03;
11886 - ret = i2c_write(0x20, 2, 1, &val, 1);
11887 + ret = i2c_write(dev, 2, &val, 1);
11888 if (ret)
11889 printf("i2c_write 0 0x20 2 failed: %d\n", ret);
11890 val = 0xfc;
11891 - ret = i2c_write(0x20, 6, 1, &val, 1);
11892 + ret = i2c_write(dev, 6, &val, 1);
11893 if (ret)
11894 printf("i2c_write 0 0x20 6 failed: %d\n", ret);
11895 }
11896 diff -ruN u-boot-2015.01-rc3/board/raspberrypi/rpi/rpi.c u-boot/board/raspberrypi/rpi/rpi.c
11897 --- u-boot-2015.01-rc3/board/raspberrypi/rpi/rpi.c 2014-12-08 22:35:08.000000000 +0100
11898 +++ u-boot/board/raspberrypi/rpi/rpi.c 2015-01-01 17:34:32.469499711 +0100
11899 @@ -24,6 +24,7 @@
11900 #include <asm/arch/mbox.h>
11901 #include <asm/arch/sdhci.h>
11902 #include <asm/global_data.h>
11903 +#include <dm/platform_data/serial_pl01x.h>
11904
11905 DECLARE_GLOBAL_DATA_PTR;
11906
11907 @@ -36,6 +37,17 @@
11908 .platdata = &gpio_platdata,
11909 };
11910
11911 +static const struct pl01x_serial_platdata serial_platdata = {
11912 + .base = 0x20201000,
11913 + .type = TYPE_PL011,
11914 + .clock = 3000000,
11915 +};
11916 +
11917 +U_BOOT_DEVICE(bcm2835_serials) = {
11918 + .name = "serial_pl01x",
11919 + .platdata = &serial_platdata,
11920 +};
11921 +
11922 struct msg_get_arm_mem {
11923 struct bcm2835_mbox_hdr hdr;
11924 struct bcm2835_mbox_tag_get_arm_mem get_arm_mem;
11925 @@ -70,58 +82,82 @@
11926 static const struct {
11927 const char *name;
11928 const char *fdtfile;
11929 + bool has_onboard_eth;
11930 } models[] = {
11931 + [0] = {
11932 + "Unknown model",
11933 + "bcm2835-rpi-other.dtb",
11934 + false,
11935 + },
11936 [BCM2835_BOARD_REV_B_I2C0_2] = {
11937 "Model B (no P5)",
11938 "bcm2835-rpi-b-i2c0.dtb",
11939 + true,
11940 },
11941 [BCM2835_BOARD_REV_B_I2C0_3] = {
11942 "Model B (no P5)",
11943 "bcm2835-rpi-b-i2c0.dtb",
11944 + true,
11945 },
11946 [BCM2835_BOARD_REV_B_I2C1_4] = {
11947 "Model B",
11948 "bcm2835-rpi-b.dtb",
11949 + true,
11950 },
11951 [BCM2835_BOARD_REV_B_I2C1_5] = {
11952 "Model B",
11953 "bcm2835-rpi-b.dtb",
11954 + true,
11955 },
11956 [BCM2835_BOARD_REV_B_I2C1_6] = {
11957 "Model B",
11958 "bcm2835-rpi-b.dtb",
11959 + true,
11960 },
11961 [BCM2835_BOARD_REV_A_7] = {
11962 "Model A",
11963 "bcm2835-rpi-a.dtb",
11964 + false,
11965 },
11966 [BCM2835_BOARD_REV_A_8] = {
11967 "Model A",
11968 "bcm2835-rpi-a.dtb",
11969 + false,
11970 },
11971 [BCM2835_BOARD_REV_A_9] = {
11972 "Model A",
11973 "bcm2835-rpi-a.dtb",
11974 + false,
11975 },
11976 [BCM2835_BOARD_REV_B_REV2_d] = {
11977 "Model B rev2",
11978 "bcm2835-rpi-b-rev2.dtb",
11979 + true,
11980 },
11981 [BCM2835_BOARD_REV_B_REV2_e] = {
11982 "Model B rev2",
11983 "bcm2835-rpi-b-rev2.dtb",
11984 + true,
11985 },
11986 [BCM2835_BOARD_REV_B_REV2_f] = {
11987 "Model B rev2",
11988 "bcm2835-rpi-b-rev2.dtb",
11989 + true,
11990 },
11991 [BCM2835_BOARD_REV_B_PLUS] = {
11992 "Model B+",
11993 "bcm2835-rpi-b-plus.dtb",
11994 + true,
11995 },
11996 [BCM2835_BOARD_REV_CM] = {
11997 "Compute Module",
11998 "bcm2835-rpi-cm.dtb",
11999 + false,
12000 + },
12001 + [BCM2835_BOARD_REV_A_PLUS] = {
12002 + "Model A+",
12003 + "bcm2835-rpi-a-plus.dtb",
12004 + false,
12005 },
12006 };
12007
12008 @@ -154,9 +190,6 @@
12009 return;
12010
12011 fdtfile = models[rpi_board_rev].fdtfile;
12012 - if (!fdtfile)
12013 - fdtfile = "bcm2835-rpi-other.dtb";
12014 -
12015 setenv("fdtfile", fdtfile);
12016 }
12017
12018 @@ -165,6 +198,9 @@
12019 ALLOC_ALIGN_BUFFER(struct msg_get_mac_address, msg, 1, 16);
12020 int ret;
12021
12022 + if (!models[rpi_board_rev].has_onboard_eth)
12023 + return;
12024 +
12025 if (getenv("usbethaddr"))
12026 return;
12027
12028 @@ -231,12 +267,17 @@
12029 }
12030
12031 rpi_board_rev = msg->get_board_rev.body.resp.rev;
12032 - if (rpi_board_rev >= ARRAY_SIZE(models))
12033 + if (rpi_board_rev >= ARRAY_SIZE(models)) {
12034 + printf("RPI: Board rev %u outside known range\n",
12035 + rpi_board_rev);
12036 rpi_board_rev = 0;
12037 + }
12038 + if (!models[rpi_board_rev].name) {
12039 + printf("RPI: Board rev %u unknown\n", rpi_board_rev);
12040 + rpi_board_rev = 0;
12041 + }
12042
12043 name = models[rpi_board_rev].name;
12044 - if (!name)
12045 - name = "Unknown model";
12046 printf("RPI model: %s\n", name);
12047 }
12048
12049 diff -ruN u-boot-2015.01-rc3/board/renesas/alt/alt.c u-boot/board/renesas/alt/alt.c
12050 --- u-boot-2015.01-rc3/board/renesas/alt/alt.c 2014-12-08 22:35:08.000000000 +0100
12051 +++ u-boot/board/renesas/alt/alt.c 2015-01-01 17:34:32.473499645 +0100
12052 @@ -15,6 +15,8 @@
12053 #include <asm/arch/sys_proto.h>
12054 #include <asm/gpio.h>
12055 #include <asm/arch/rmobile.h>
12056 +#include <asm/arch/rcar-mstp.h>
12057 +#include <asm/arch/mmc.h>
12058 #include <netdev.h>
12059 #include <miiphy.h>
12060 #include <i2c.h>
12061 @@ -37,30 +39,11 @@
12062 qos_init();
12063 }
12064
12065 -#define MSTPSR1 0xE6150038
12066 -#define SMSTPCR1 0xE6150134
12067 #define TMU0_MSTP125 (1 << 25)
12068 -
12069 -#define MSTPSR7 0xE61501C4
12070 -#define SMSTPCR7 0xE615014C
12071 #define SCIF2_MSTP719 (1 << 19)
12072 -
12073 -#define MSTPSR8 0xE61509A0
12074 -#define SMSTPCR8 0xE6150990
12075 #define ETHER_MSTP813 (1 << 13)
12076 -
12077 -#define MSTPSR3 0xE6150048
12078 -#define SMSTPCR3 0xE615013C
12079 #define IIC1_MSTP323 (1 << 23)
12080 -
12081 -#define mstp_setbits(type, addr, saddr, set) \
12082 - out_##type((saddr), in_##type(addr) | (set))
12083 -#define mstp_clrbits(type, addr, saddr, clear) \
12084 - out_##type((saddr), in_##type(addr) & ~(clear))
12085 -#define mstp_setbits_le32(addr, saddr, set) \
12086 - mstp_setbits(le32, addr, saddr, set)
12087 -#define mstp_clrbits_le32(addr, saddr, clear) \
12088 - mstp_clrbits(le32, addr, saddr, clear)
12089 +#define MMC0_MSTP315 (1 << 15)
12090
12091 int board_early_init_f(void)
12092 {
12093 @@ -76,15 +59,13 @@
12094 /* IIC1 / sh-i2c ch1 */
12095 mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323);
12096
12097 +#ifdef CONFIG_SH_MMCIF
12098 + /* MMC */
12099 + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315);
12100 +#endif
12101 return 0;
12102 }
12103
12104 -void arch_preboot_os(void)
12105 -{
12106 - /* Disable TMU0 */
12107 - mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
12108 -}
12109 -
12110 int board_init(void)
12111 {
12112 /* adress of boot parameters */
12113 @@ -145,6 +126,19 @@
12114 #endif
12115 }
12116
12117 +int board_mmc_init(bd_t *bis)
12118 +{
12119 + int ret = 0;
12120 +
12121 +#ifdef CONFIG_SH_MMCIF
12122 + gpio_request(GPIO_GP_4_31, NULL);
12123 + gpio_set_value(GPIO_GP_4_31, 1);
12124 +
12125 + ret = mmcif_mmc_init();
12126 +#endif
12127 + return ret;
12128 +}
12129 +
12130 int dram_init(void)
12131 {
12132 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
12133 diff -ruN u-boot-2015.01-rc3/board/renesas/alt/Makefile u-boot/board/renesas/alt/Makefile
12134 --- u-boot-2015.01-rc3/board/renesas/alt/Makefile 2014-12-08 22:35:08.000000000 +0100
12135 +++ u-boot/board/renesas/alt/Makefile 2015-01-01 17:34:32.473499645 +0100
12136 @@ -6,4 +6,4 @@
12137 # SPDX-License-Identifier: GPL-2.0
12138 #
12139
12140 -obj-y := alt.o qos.o
12141 +obj-y := alt.o qos.o ../rcar-gen2-common/common.o
12142 diff -ruN u-boot-2015.01-rc3/board/renesas/gose/gose.c u-boot/board/renesas/gose/gose.c
12143 --- u-boot-2015.01-rc3/board/renesas/gose/gose.c 2014-12-08 22:35:08.000000000 +0100
12144 +++ u-boot/board/renesas/gose/gose.c 2015-01-01 17:34:32.473499645 +0100
12145 @@ -15,6 +15,7 @@
12146 #include <asm/arch/sys_proto.h>
12147 #include <asm/gpio.h>
12148 #include <asm/arch/rmobile.h>
12149 +#include <asm/arch/rcar-mstp.h>
12150 #include <netdev.h>
12151 #include <miiphy.h>
12152 #include <i2c.h>
12153 @@ -41,27 +42,10 @@
12154 qos_init();
12155 }
12156
12157 -#define MSTPSR1 0xE6150038
12158 -#define SMSTPCR1 0xE6150134
12159 #define TMU0_MSTP125 (1 << 25)
12160 -
12161 -#define MSTPSR7 0xE61501C4
12162 -#define SMSTPCR7 0xE615014C
12163 #define SCIF0_MSTP721 (1 << 21)
12164 -
12165 -#define MSTPSR8 0xE61509A0
12166 -#define SMSTPCR8 0xE6150990
12167 #define ETHER_MSTP813 (1 << 13)
12168
12169 -#define mstp_setbits(type, addr, saddr, set) \
12170 - out_##type((saddr), in_##type(addr) | (set))
12171 -#define mstp_clrbits(type, addr, saddr, clear) \
12172 - out_##type((saddr), in_##type(addr) & ~(clear))
12173 -#define mstp_setbits_le32(addr, saddr, set) \
12174 - mstp_setbits(le32, addr, saddr, set)
12175 -#define mstp_clrbits_le32(addr, saddr, clear) \
12176 - mstp_clrbits(le32, addr, saddr, clear)
12177 -
12178 int board_early_init_f(void)
12179 {
12180 /* TMU0 */
12181 @@ -76,16 +60,6 @@
12182 return 0;
12183 }
12184
12185 -#define TSTR0 0x04
12186 -#define TSTR0_STR0 0x01
12187 -void arch_preboot_os(void)
12188 -{
12189 - /* stop TMU0 */
12190 - mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
12191 - /* Disable TMU0 */
12192 - mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
12193 -}
12194 -
12195 #define PUPR5 0xE6060114
12196 #define PUPR5_ETH 0x3FFC0000
12197 #define PUPR5_ETH_MAGIC (1 << 27)
12198 diff -ruN u-boot-2015.01-rc3/board/renesas/gose/Makefile u-boot/board/renesas/gose/Makefile
12199 --- u-boot-2015.01-rc3/board/renesas/gose/Makefile 2014-12-08 22:35:08.000000000 +0100
12200 +++ u-boot/board/renesas/gose/Makefile 2015-01-01 17:34:32.473499645 +0100
12201 @@ -6,4 +6,4 @@
12202 # SPDX-License-Identifier: GPL-2.0
12203 #
12204
12205 -obj-y := gose.o qos.o
12206 +obj-y := gose.o qos.o ../rcar-gen2-common/common.o
12207 diff -ruN u-boot-2015.01-rc3/board/renesas/koelsch/koelsch.c u-boot/board/renesas/koelsch/koelsch.c
12208 --- u-boot-2015.01-rc3/board/renesas/koelsch/koelsch.c 2014-12-08 22:35:08.000000000 +0100
12209 +++ u-boot/board/renesas/koelsch/koelsch.c 2015-01-01 17:34:32.473499645 +0100
12210 @@ -16,6 +16,7 @@
12211 #include <asm/arch/sys_proto.h>
12212 #include <asm/gpio.h>
12213 #include <asm/arch/rmobile.h>
12214 +#include <asm/arch/rcar-mstp.h>
12215 #include <netdev.h>
12216 #include <miiphy.h>
12217 #include <i2c.h>
12218 @@ -43,27 +44,10 @@
12219 qos_init();
12220 }
12221
12222 -#define MSTPSR1 0xE6150038
12223 -#define SMSTPCR1 0xE6150134
12224 #define TMU0_MSTP125 (1 << 25)
12225 -
12226 -#define MSTPSR7 0xE61501C4
12227 -#define SMSTPCR7 0xE615014C
12228 #define SCIF0_MSTP721 (1 << 21)
12229 -
12230 -#define MSTPSR8 0xE61509A0
12231 -#define SMSTPCR8 0xE6150990
12232 #define ETHER_MSTP813 (1 << 13)
12233
12234 -#define mstp_setbits(type, addr, saddr, set) \
12235 - out_##type((saddr), in_##type(addr) | (set))
12236 -#define mstp_clrbits(type, addr, saddr, clear) \
12237 - out_##type((saddr), in_##type(addr) & ~(clear))
12238 -#define mstp_setbits_le32(addr, saddr, set) \
12239 - mstp_setbits(le32, addr, saddr, set)
12240 -#define mstp_clrbits_le32(addr, saddr, clear) \
12241 - mstp_clrbits(le32, addr, saddr, clear)
12242 -
12243 int board_early_init_f(void)
12244 {
12245 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
12246 @@ -77,12 +61,6 @@
12247 return 0;
12248 }
12249
12250 -void arch_preboot_os(void)
12251 -{
12252 - /* Disable TMU0 */
12253 - mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
12254 -}
12255 -
12256 /* LSI pin pull-up control */
12257 #define PUPR5 0xe6060114
12258 #define PUPR5_ETH 0x3FFC0000
12259 diff -ruN u-boot-2015.01-rc3/board/renesas/koelsch/Makefile u-boot/board/renesas/koelsch/Makefile
12260 --- u-boot-2015.01-rc3/board/renesas/koelsch/Makefile 2014-12-08 22:35:08.000000000 +0100
12261 +++ u-boot/board/renesas/koelsch/Makefile 2015-01-01 17:34:32.473499645 +0100
12262 @@ -6,4 +6,4 @@
12263 # SPDX-License-Identifier: GPL-2.0
12264 #
12265
12266 -obj-y := koelsch.o qos.o
12267 +obj-y := koelsch.o qos.o ../rcar-gen2-common/common.o
12268 diff -ruN u-boot-2015.01-rc3/board/renesas/lager/lager.c u-boot/board/renesas/lager/lager.c
12269 --- u-boot-2015.01-rc3/board/renesas/lager/lager.c 2014-12-08 22:35:08.000000000 +0100
12270 +++ u-boot/board/renesas/lager/lager.c 2015-01-01 17:34:32.473499645 +0100
12271 @@ -18,8 +18,11 @@
12272 #include <asm/arch/sys_proto.h>
12273 #include <asm/gpio.h>
12274 #include <asm/arch/rmobile.h>
12275 +#include <asm/arch/rcar-mstp.h>
12276 +#include <asm/arch/mmc.h>
12277 #include <miiphy.h>
12278 #include <i2c.h>
12279 +#include <mmc.h>
12280 #include "qos.h"
12281
12282 DECLARE_GLOBAL_DATA_PTR;
12283 @@ -50,26 +53,10 @@
12284 qos_init();
12285 }
12286
12287 -#define MSTPSR1 0xE6150038
12288 -#define SMSTPCR1 0xE6150134
12289 #define TMU0_MSTP125 (1 << 25)
12290 -
12291 -#define MSTPSR7 0xE61501C4
12292 -#define SMSTPCR7 0xE615014C
12293 #define SCIF0_MSTP721 (1 << 21)
12294 -
12295 -#define MSTPSR8 0xE61509A0
12296 -#define SMSTPCR8 0xE6150990
12297 #define ETHER_MSTP813 (1 << 13)
12298 -
12299 -#define mstp_setbits(type, addr, saddr, set) \
12300 - out_##type((saddr), in_##type(addr) | (set))
12301 -#define mstp_clrbits(type, addr, saddr, clear) \
12302 - out_##type((saddr), in_##type(addr) & ~(clear))
12303 -#define mstp_setbits_le32(addr, saddr, set) \
12304 - mstp_setbits(le32, addr, saddr, set)
12305 -#define mstp_clrbits_le32(addr, saddr, clear) \
12306 - mstp_clrbits(le32, addr, saddr, clear)
12307 +#define MMC1_MSTP305 (1 << 5)
12308
12309 int board_early_init_f(void)
12310 {
12311 @@ -79,16 +66,12 @@
12312 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
12313 /* ETHER */
12314 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
12315 + /* eMMC */
12316 + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305);
12317
12318 return 0;
12319 }
12320
12321 -void arch_preboot_os(void)
12322 -{
12323 - /* Disable TMU0 */
12324 - mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
12325 -}
12326 -
12327 DECLARE_GLOBAL_DATA_PTR;
12328 int board_init(void)
12329 {
12330 @@ -163,6 +146,28 @@
12331 return 0;
12332 }
12333
12334 +int board_mmc_init(bd_t *bis)
12335 +{
12336 + int ret = 0;
12337 +
12338 +#ifdef CONFIG_SH_MMCIF
12339 + gpio_request(GPIO_FN_MMC1_D0, NULL);
12340 + gpio_request(GPIO_FN_MMC1_D1, NULL);
12341 + gpio_request(GPIO_FN_MMC1_D2, NULL);
12342 + gpio_request(GPIO_FN_MMC1_D3, NULL);
12343 + gpio_request(GPIO_FN_MMC1_D4, NULL);
12344 + gpio_request(GPIO_FN_MMC1_D5, NULL);
12345 + gpio_request(GPIO_FN_MMC1_D6, NULL);
12346 + gpio_request(GPIO_FN_MMC1_D7, NULL);
12347 + gpio_request(GPIO_FN_MMC1_CLK, NULL);
12348 + gpio_request(GPIO_FN_MMC1_CMD, NULL);
12349 +
12350 + ret = mmcif_mmc_init();
12351 +#endif
12352 + return ret;
12353 +}
12354 +
12355 +
12356 int dram_init(void)
12357 {
12358 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
12359 diff -ruN u-boot-2015.01-rc3/board/renesas/lager/Makefile u-boot/board/renesas/lager/Makefile
12360 --- u-boot-2015.01-rc3/board/renesas/lager/Makefile 2014-12-08 22:35:08.000000000 +0100
12361 +++ u-boot/board/renesas/lager/Makefile 2015-01-01 17:34:32.473499645 +0100
12362 @@ -6,4 +6,4 @@
12363 # SPDX-License-Identifier: GPL-2.0
12364 #
12365
12366 -obj-y := lager.o qos.o
12367 +obj-y := lager.o qos.o ../rcar-gen2-common/common.o
12368 diff -ruN u-boot-2015.01-rc3/board/renesas/rcar-gen2-common/common.c u-boot/board/renesas/rcar-gen2-common/common.c
12369 --- u-boot-2015.01-rc3/board/renesas/rcar-gen2-common/common.c 1970-01-01 01:00:00.000000000 +0100
12370 +++ u-boot/board/renesas/rcar-gen2-common/common.c 2015-01-01 17:34:32.477499579 +0100
12371 @@ -0,0 +1,59 @@
12372 +/*
12373 + * board/renesas/rcar-gen2-common/common.c
12374 + *
12375 + * Copyright (C) 2013 Renesas Electronics Corporation
12376 + * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
12377 + *
12378 + * SPDX-License-Identifier: GPL-2.0
12379 + */
12380 +
12381 +#include <common.h>
12382 +#include <asm/io.h>
12383 +#include <asm/arch/sys_proto.h>
12384 +#include <asm/arch/rmobile.h>
12385 +#include <asm/arch/rcar-mstp.h>
12386 +
12387 +#define TSTR0 0x04
12388 +#define TSTR0_STR0 0x01
12389 +
12390 +static struct mstp_ctl mstptbl[] = {
12391 + { SMSTPCR0, MSTP0_BITS, CONFIG_SMSTP0_ENA,
12392 + RMSTPCR0, MSTP0_BITS, CONFIG_RMSTP0_ENA },
12393 + { SMSTPCR1, MSTP1_BITS, CONFIG_SMSTP1_ENA,
12394 + RMSTPCR1, MSTP1_BITS, CONFIG_RMSTP1_ENA },
12395 + { SMSTPCR2, MSTP2_BITS, CONFIG_SMSTP2_ENA,
12396 + RMSTPCR2, MSTP2_BITS, CONFIG_RMSTP2_ENA },
12397 + { SMSTPCR3, MSTP3_BITS, CONFIG_SMSTP3_ENA,
12398 + RMSTPCR3, MSTP3_BITS, CONFIG_RMSTP3_ENA },
12399 + { SMSTPCR4, MSTP4_BITS, CONFIG_SMSTP4_ENA,
12400 + RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
12401 + { SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
12402 + RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
12403 + /* No MSTP6 */
12404 + { SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
12405 + RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
12406 + { SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
12407 + RMSTPCR8, MSTP8_BITS, CONFIG_RMSTP8_ENA },
12408 + { SMSTPCR9, MSTP9_BITS, CONFIG_SMSTP9_ENA,
12409 + RMSTPCR9, MSTP9_BITS, CONFIG_RMSTP9_ENA },
12410 + { SMSTPCR10, MSTP10_BITS, CONFIG_SMSTP10_ENA,
12411 + RMSTPCR10, MSTP10_BITS, CONFIG_RMSTP10_ENA },
12412 + { SMSTPCR11, MSTP11_BITS, CONFIG_SMSTP1_ENA,
12413 + RMSTPCR11, MSTP11_BITS, CONFIG_RMSTP11_ENA },
12414 +};
12415 +
12416 +void arch_preboot_os(void)
12417 +{
12418 + int i;
12419 +
12420 + /* stop TMU0 */
12421 + mstp_clrbits_le32(TMU_BASE + TSTR0, TMU_BASE + TSTR0, TSTR0_STR0);
12422 +
12423 + /* Stop module clock */
12424 + for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
12425 + mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis,
12426 + mstptbl[i].s_ena);
12427 + mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis,
12428 + mstptbl[i].r_ena);
12429 + }
12430 +}
12431 diff -ruN u-boot-2015.01-rc3/board/solidrun/hummingboard/hummingboard.c u-boot/board/solidrun/hummingboard/hummingboard.c
12432 --- u-boot-2015.01-rc3/board/solidrun/hummingboard/hummingboard.c 2014-12-08 22:35:08.000000000 +0100
12433 +++ u-boot/board/solidrun/hummingboard/hummingboard.c 2015-01-01 17:34:32.497499251 +0100
12434 @@ -146,7 +146,7 @@
12435 {
12436 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
12437
12438 - int ret = enable_fec_anatop_clock(ENET_25MHz);
12439 + int ret = enable_fec_anatop_clock(ENET_25MHZ);
12440 if (ret)
12441 return ret;
12442
12443 diff -ruN u-boot-2015.01-rc3/board/st/stv0991/Kconfig u-boot/board/st/stv0991/Kconfig
12444 --- u-boot-2015.01-rc3/board/st/stv0991/Kconfig 1970-01-01 01:00:00.000000000 +0100
12445 +++ u-boot/board/st/stv0991/Kconfig 2015-01-01 17:34:32.501499185 +0100
12446 @@ -0,0 +1,23 @@
12447 +if TARGET_STV0991
12448 +
12449 +config SYS_CPU
12450 + string
12451 + default "armv7"
12452 +
12453 +config SYS_BOARD
12454 + string
12455 + default "stv0991"
12456 +
12457 +config SYS_VENDOR
12458 + string
12459 + default "st"
12460 +
12461 +config SYS_SOC
12462 + string
12463 + default "stv0991"
12464 +
12465 +config SYS_CONFIG_NAME
12466 + string
12467 + default "stv0991"
12468 +
12469 +endif
12470 diff -ruN u-boot-2015.01-rc3/board/st/stv0991/MAINTAINERS u-boot/board/st/stv0991/MAINTAINERS
12471 --- u-boot-2015.01-rc3/board/st/stv0991/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100
12472 +++ u-boot/board/st/stv0991/MAINTAINERS 2015-01-01 17:34:32.501499185 +0100
12473 @@ -0,0 +1,5 @@
12474 +STV0991 APPLICATION BOARD
12475 +M: Vikas Manocha <vikas.manocha@st.com>
12476 +S: Maintained
12477 +F: board/st/stv0991/
12478 +F: include/configs/stv0991.h
12479 diff -ruN u-boot-2015.01-rc3/board/st/stv0991/Makefile u-boot/board/st/stv0991/Makefile
12480 --- u-boot-2015.01-rc3/board/st/stv0991/Makefile 1970-01-01 01:00:00.000000000 +0100
12481 +++ u-boot/board/st/stv0991/Makefile 2015-01-01 17:34:32.501499185 +0100
12482 @@ -0,0 +1,8 @@
12483 +#
12484 +# (C) Copyright 2014
12485 +# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
12486 +#
12487 +# SPDX-License-Identifier: GPL-2.0+
12488 +#
12489 +
12490 +obj-y := stv0991.o
12491 diff -ruN u-boot-2015.01-rc3/board/st/stv0991/stv0991.c u-boot/board/st/stv0991/stv0991.c
12492 --- u-boot-2015.01-rc3/board/st/stv0991/stv0991.c 1970-01-01 01:00:00.000000000 +0100
12493 +++ u-boot/board/st/stv0991/stv0991.c 2015-01-01 17:34:32.501499185 +0100
12494 @@ -0,0 +1,104 @@
12495 +/*
12496 + * (C) Copyright 2014
12497 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
12498 + *
12499 + * SPDX-License-Identifier: GPL-2.0+
12500 + */
12501 +
12502 +#include <common.h>
12503 +#include <miiphy.h>
12504 +#include <asm/arch/stv0991_periph.h>
12505 +#include <asm/arch/stv0991_defs.h>
12506 +#include <asm/arch/hardware.h>
12507 +#include <asm/arch/gpio.h>
12508 +#include <netdev.h>
12509 +#include <asm/io.h>
12510 +#include <dm/platdata.h>
12511 +#include <dm/platform_data/serial_pl01x.h>
12512 +
12513 +DECLARE_GLOBAL_DATA_PTR;
12514 +
12515 +struct gpio_regs *const gpioa_regs =
12516 + (struct gpio_regs *) GPIOA_BASE_ADDR;
12517 +
12518 +static const struct pl01x_serial_platdata serial_platdata = {
12519 + .base = 0x80406000,
12520 + .type = TYPE_PL011,
12521 + .clock = 2700 * 1000,
12522 +};
12523 +
12524 +U_BOOT_DEVICE(stv09911_serials) = {
12525 + .name = "serial_pl01x",
12526 + .platdata = &serial_platdata,
12527 +};
12528 +
12529 +#ifdef CONFIG_SHOW_BOOT_PROGRESS
12530 +void show_boot_progress(int progress)
12531 +{
12532 + printf("%i\n", progress);
12533 +}
12534 +#endif
12535 +
12536 +void enable_eth_phy(void)
12537 +{
12538 + /* Set GPIOA_06 pad HIGH (Appli board)*/
12539 + writel(readl(&gpioa_regs->dir) | 0x40, &gpioa_regs->dir);
12540 + writel(readl(&gpioa_regs->data) | 0x40, &gpioa_regs->data);
12541 +}
12542 +int board_eth_enable(void)
12543 +{
12544 + stv0991_pinmux_config(ETH_GPIOB_10_31_C_0_4);
12545 + clock_setup(ETH_CLOCK_CFG);
12546 + enable_eth_phy();
12547 + return 0;
12548 +}
12549 +
12550 +/*
12551 + * Miscellaneous platform dependent initialisations
12552 + */
12553 +int board_init(void)
12554 +{
12555 + board_eth_enable();
12556 + return 0;
12557 +}
12558 +
12559 +int board_uart_init(void)
12560 +{
12561 + stv0991_pinmux_config(UART_GPIOC_30_31);
12562 + clock_setup(UART_CLOCK_CFG);
12563 + return 0;
12564 +}
12565 +
12566 +#ifdef CONFIG_BOARD_EARLY_INIT_F
12567 +int board_early_init_f(void)
12568 +{
12569 + board_uart_init();
12570 + return 0;
12571 +}
12572 +#endif
12573 +
12574 +int dram_init(void)
12575 +{
12576 + gd->ram_size = PHYS_SDRAM_1_SIZE;
12577 + return 0;
12578 +}
12579 +
12580 +void dram_init_banksize(void)
12581 +{
12582 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
12583 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
12584 +}
12585 +
12586 +#ifdef CONFIG_CMD_NET
12587 +int board_eth_init(bd_t *bis)
12588 +{
12589 + int ret = 0;
12590 +
12591 +#if defined(CONFIG_DESIGNWARE_ETH)
12592 + u32 interface = PHY_INTERFACE_MODE_MII;
12593 + if (designware_initialize(GMAC_BASE_ADDR, interface) >= 0)
12594 + ret++;
12595 +#endif
12596 + return ret;
12597 +}
12598 +#endif
12599 diff -ruN u-boot-2015.01-rc3/board/tbs/tbs2910/Kconfig u-boot/board/tbs/tbs2910/Kconfig
12600 --- u-boot-2015.01-rc3/board/tbs/tbs2910/Kconfig 2014-12-08 22:35:08.000000000 +0100
12601 +++ u-boot/board/tbs/tbs2910/Kconfig 2015-01-01 17:34:32.505499121 +0100
12602 @@ -1,23 +1,15 @@
12603 if TARGET_TBS2910
12604
12605 -config SYS_CPU
12606 - string
12607 - default "armv7"
12608 -
12609 config SYS_BOARD
12610 - string
12611 default "tbs2910"
12612
12613 config SYS_VENDOR
12614 - string
12615 default "tbs"
12616
12617 config SYS_SOC
12618 - string
12619 default "mx6"
12620
12621 config SYS_CONFIG_NAME
12622 - string
12623 default "tbs2910"
12624
12625 endif
12626 diff -ruN u-boot-2015.01-rc3/board/toradex/apalis_t30/apalis_t30.c u-boot/board/toradex/apalis_t30/apalis_t30.c
12627 --- u-boot-2015.01-rc3/board/toradex/apalis_t30/apalis_t30.c 2014-12-08 22:35:08.000000000 +0100
12628 +++ u-boot/board/toradex/apalis_t30/apalis_t30.c 2015-01-01 17:34:32.509499055 +0100
12629 @@ -6,7 +6,7 @@
12630 */
12631
12632 #include <common.h>
12633 -
12634 +#include <dm.h>
12635 #include <asm/arch/gp_padctrl.h>
12636 #include <asm/arch/pinmux.h>
12637 #include <asm/gpio.h>
12638 @@ -38,23 +38,20 @@
12639 #ifdef CONFIG_PCI_TEGRA
12640 int tegra_pcie_board_init(void)
12641 {
12642 - unsigned int old_bus;
12643 + struct udevice *dev;
12644 u8 addr, data[1];
12645 int err;
12646
12647 - old_bus = i2c_get_bus_num();
12648 -
12649 - err = i2c_set_bus_num(0);
12650 + err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev);
12651 if (err) {
12652 - debug("failed to set I2C bus\n");
12653 + debug("%s: Cannot find PMIC I2C chip\n", __func__);
12654 return err;
12655 }
12656 -
12657 /* TPS659110: VDD2_OP_REG = 1.05V */
12658 data[0] = 0x27;
12659 addr = 0x25;
12660
12661 - err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1);
12662 + err = i2c_write(dev, addr, data, 1);
12663 if (err) {
12664 debug("failed to set VDD supply\n");
12665 return err;
12666 @@ -64,7 +61,7 @@
12667 data[0] = 0x0D;
12668 addr = 0x24;
12669
12670 - err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1);
12671 + err = i2c_write(dev, addr, data, 1);
12672 if (err) {
12673 debug("failed to enable VDD supply\n");
12674 return err;
12675 @@ -74,14 +71,12 @@
12676 data[0] = 0x0D;
12677 addr = 0x35;
12678
12679 - err = i2c_write(PMU_I2C_ADDRESS, addr, 1, data, 1);
12680 + err = i2c_write(dev, addr, data, 1);
12681 if (err) {
12682 debug("failed to set AVDD supply\n");
12683 return err;
12684 }
12685
12686 - i2c_set_bus_num(old_bus);
12687 -
12688 return 0;
12689 }
12690
12691 diff -ruN u-boot-2015.01-rc3/common/board_f.c u-boot/common/board_f.c
12692 --- u-boot-2015.01-rc3/common/board_f.c 2014-12-08 22:35:08.000000000 +0100
12693 +++ u-boot/common/board_f.c 2015-01-01 17:34:32.521498858 +0100
12694 @@ -813,7 +813,9 @@
12695 #endif
12696 setup_mon_len,
12697 setup_fdt,
12698 +#ifdef CONFIG_TRACE
12699 trace_early_init,
12700 +#endif
12701 initf_malloc,
12702 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
12703 /* TODO: can this go into arch_cpu_init()? */
12704 diff -ruN u-boot-2015.01-rc3/common/cmd_dfu.c u-boot/common/cmd_dfu.c
12705 --- u-boot-2015.01-rc3/common/cmd_dfu.c 2014-12-08 22:35:08.000000000 +0100
12706 +++ u-boot/common/cmd_dfu.c 2015-01-01 17:34:32.525498793 +0100
12707 @@ -38,10 +38,10 @@
12708
12709 int controller_index = simple_strtoul(usb_controller, NULL, 0);
12710 board_usb_init(controller_index, USB_INIT_DEVICE);
12711 - dfu_clear_detach();
12712 + g_dnl_clear_detach();
12713 g_dnl_register("usb_dnl_dfu");
12714 while (1) {
12715 - if (dfu_detach()) {
12716 + if (g_dnl_detach()) {
12717 /*
12718 * Check if USB bus reset is performed after detach,
12719 * which indicates that -R switch has been passed to
12720 @@ -74,7 +74,7 @@
12721 if (dfu_reset)
12722 run_command("reset", 0);
12723
12724 - dfu_clear_detach();
12725 + g_dnl_clear_detach();
12726
12727 return ret;
12728 }
12729 diff -ruN u-boot-2015.01-rc3/common/cmd_fastboot.c u-boot/common/cmd_fastboot.c
12730 --- u-boot-2015.01-rc3/common/cmd_fastboot.c 2014-12-08 22:35:08.000000000 +0100
12731 +++ u-boot/common/cmd_fastboot.c 2015-01-01 17:34:32.525498793 +0100
12732 @@ -15,17 +15,21 @@
12733 {
12734 int ret;
12735
12736 + g_dnl_clear_detach();
12737 ret = g_dnl_register("usb_dnl_fastboot");
12738 if (ret)
12739 return ret;
12740
12741 while (1) {
12742 + if (g_dnl_detach())
12743 + break;
12744 if (ctrlc())
12745 break;
12746 usb_gadget_handle_interrupts();
12747 }
12748
12749 g_dnl_unregister();
12750 + g_dnl_clear_detach();
12751 return CMD_RET_SUCCESS;
12752 }
12753
12754 diff -ruN u-boot-2015.01-rc3/common/cmd_hash.c u-boot/common/cmd_hash.c
12755 --- u-boot-2015.01-rc3/common/cmd_hash.c 2014-12-08 22:35:08.000000000 +0100
12756 +++ u-boot/common/cmd_hash.c 2015-01-01 17:34:32.529498727 +0100
12757 @@ -18,9 +18,9 @@
12758 static int do_hash(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
12759 {
12760 char *s;
12761 -#ifdef CONFIG_HASH_VERIFY
12762 int flags = HASH_FLAG_ENV;
12763
12764 +#ifdef CONFIG_HASH_VERIFY
12765 if (argc < 4)
12766 return CMD_RET_USAGE;
12767 if (!strcmp(argv[1], "-v")) {
12768 @@ -28,8 +28,6 @@
12769 argc--;
12770 argv++;
12771 }
12772 -#else
12773 - const int flags = HASH_FLAG_ENV;
12774 #endif
12775 /* Move forward to 'algorithm' parameter */
12776 argc--;
12777 @@ -40,19 +38,19 @@
12778 }
12779
12780 #ifdef CONFIG_HASH_VERIFY
12781 -U_BOOT_CMD(
12782 - hash, 6, 1, do_hash,
12783 - "compute hash message digest",
12784 - "algorithm address count [[*]sum_dest]\n"
12785 - " - compute message digest [save to env var / *address]\n"
12786 - "hash -v algorithm address count [*]sum\n"
12787 - " - verify hash of memory area with env var / *address"
12788 -);
12789 +#define HARGS 6
12790 #else
12791 +#define HARGS 5
12792 +#endif
12793 +
12794 U_BOOT_CMD(
12795 - hash, 5, 1, do_hash,
12796 - "compute message digest",
12797 - "algorithm address count [[*]sum_dest]\n"
12798 + hash, HARGS, 1, do_hash,
12799 + "compute hash message digest",
12800 + "algorithm address count [[*]hash_dest]\n"
12801 " - compute message digest [save to env var / *address]"
12802 -);
12803 +#ifdef CONFIG_HASH_VERIFY
12804 + "\nhash -v algorithm address count [*]hash\n"
12805 + " - verify message digest of memory area to immediate value, \n"
12806 + " env var or *address"
12807 #endif
12808 +);
12809 diff -ruN u-boot-2015.01-rc3/common/cmd_i2c.c u-boot/common/cmd_i2c.c
12810 --- u-boot-2015.01-rc3/common/cmd_i2c.c 2014-12-08 22:35:08.000000000 +0100
12811 +++ u-boot/common/cmd_i2c.c 2015-01-01 17:34:32.529498727 +0100
12812 @@ -69,8 +69,10 @@
12813 #include <bootretry.h>
12814 #include <cli.h>
12815 #include <command.h>
12816 +#include <dm.h>
12817 #include <edid.h>
12818 #include <environment.h>
12819 +#include <errno.h>
12820 #include <i2c.h>
12821 #include <malloc.h>
12822 #include <asm/byteorder.h>
12823 @@ -117,6 +119,60 @@
12824
12825 #define DISP_LINE_LEN 16
12826
12827 +/*
12828 + * Default for driver model is to use the chip's existing address length.
12829 + * For legacy code, this is not stored, so we need to use a suitable
12830 + * default.
12831 + */
12832 +#ifdef CONFIG_DM_I2C
12833 +#define DEFAULT_ADDR_LEN (-1)
12834 +#else
12835 +#define DEFAULT_ADDR_LEN 1
12836 +#endif
12837 +
12838 +#ifdef CONFIG_DM_I2C
12839 +static struct udevice *i2c_cur_bus;
12840 +
12841 +static int i2c_set_bus_num(unsigned int busnum)
12842 +{
12843 + struct udevice *bus;
12844 + int ret;
12845 +
12846 + ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus);
12847 + if (ret) {
12848 + debug("%s: No bus %d\n", __func__, busnum);
12849 + return ret;
12850 + }
12851 + i2c_cur_bus = bus;
12852 +
12853 + return 0;
12854 +}
12855 +
12856 +static int i2c_get_cur_bus(struct udevice **busp)
12857 +{
12858 + if (!i2c_cur_bus) {
12859 + puts("No I2C bus selected\n");
12860 + return -ENODEV;
12861 + }
12862 + *busp = i2c_cur_bus;
12863 +
12864 + return 0;
12865 +}
12866 +
12867 +static int i2c_get_cur_bus_chip(uint chip_addr, struct udevice **devp)
12868 +{
12869 + struct udevice *bus;
12870 + int ret;
12871 +
12872 + ret = i2c_get_cur_bus(&bus);
12873 + if (ret)
12874 + return ret;
12875 +
12876 + return i2c_get_chip(bus, chip_addr, devp);
12877 +}
12878 +
12879 +#endif
12880 +
12881 /**
12882 * i2c_init_board() - Board-specific I2C bus init
12883 *
12884 @@ -143,7 +199,7 @@
12885 *
12886 * Returns I2C bus speed in Hz.
12887 */
12888 -#if !defined(CONFIG_SYS_I2C)
12889 +#if !defined(CONFIG_SYS_I2C) && !defined(CONFIG_DM_I2C)
12890 /*
12891 * TODO: Implement architecture-specific get/set functions
12892 * Should go away, if we switched completely to new multibus support
12893 @@ -182,12 +238,12 @@
12894 *
12895 * Returns the address length.
12896 */
12897 -static uint get_alen(char *arg)
12898 +static uint get_alen(char *arg, int default_len)
12899 {
12900 int j;
12901 int alen;
12902
12903 - alen = 1;
12904 + alen = default_len;
12905 for (j = 0; j < 8; j++) {
12906 if (arg[j] == '.') {
12907 alen = arg[j+1] - '0';
12908 @@ -227,8 +283,13 @@
12909 static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
12910 {
12911 u_char chip;
12912 - uint devaddr, alen, length;
12913 + uint devaddr, length;
12914 + int alen;
12915 u_char *memaddr;
12916 + int ret;
12917 +#ifdef CONFIG_DM_I2C
12918 + struct udevice *dev;
12919 +#endif
12920
12921 if (argc != 5)
12922 return CMD_RET_USAGE;
12923 @@ -243,7 +304,7 @@
12924 * 2 bytes long. Some day it might be 3 bytes long :-).
12925 */
12926 devaddr = simple_strtoul(argv[2], NULL, 16);
12927 - alen = get_alen(argv[2]);
12928 + alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
12929 if (alen > 3)
12930 return CMD_RET_USAGE;
12931
12932 @@ -257,18 +318,31 @@
12933 */
12934 memaddr = (u_char *)simple_strtoul(argv[4], NULL, 16);
12935
12936 - if (i2c_read(chip, devaddr, alen, memaddr, length) != 0) {
12937 - i2c_report_err(-1, I2C_ERR_READ);
12938 - return 1;
12939 - }
12940 +#ifdef CONFIG_DM_I2C
12941 + ret = i2c_get_cur_bus_chip(chip, &dev);
12942 + if (!ret && alen != -1)
12943 + ret = i2c_set_chip_offset_len(dev, alen);
12944 + if (!ret)
12945 + ret = i2c_read(dev, devaddr, memaddr, length);
12946 +#else
12947 + ret = i2c_read(chip, devaddr, alen, memaddr, length);
12948 +#endif
12949 + if (ret)
12950 + return i2c_report_err(ret, I2C_ERR_READ);
12951 +
12952 return 0;
12953 }
12954
12955 static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
12956 {
12957 u_char chip;
12958 - uint devaddr, alen, length;
12959 + uint devaddr, length;
12960 + int alen;
12961 u_char *memaddr;
12962 + int ret;
12963 +#ifdef CONFIG_DM_I2C
12964 + struct udevice *dev;
12965 +#endif
12966
12967 if (argc != 5)
12968 return cmd_usage(cmdtp);
12969 @@ -288,7 +362,7 @@
12970 * 2 bytes long. Some day it might be 3 bytes long :-).
12971 */
12972 devaddr = simple_strtoul(argv[3], NULL, 16);
12973 - alen = get_alen(argv[3]);
12974 + alen = get_alen(argv[3], DEFAULT_ADDR_LEN);
12975 if (alen > 3)
12976 return cmd_usage(cmdtp);
12977
12978 @@ -297,10 +371,22 @@
12979 */
12980 length = simple_strtoul(argv[4], NULL, 16);
12981
12982 +#ifdef CONFIG_DM_I2C
12983 + ret = i2c_get_cur_bus_chip(chip, &dev);
12984 + if (!ret && alen != -1)
12985 + ret = i2c_set_chip_offset_len(dev, alen);
12986 + if (ret)
12987 + return i2c_report_err(ret, I2C_ERR_WRITE);
12988 +#endif
12989 +
12990 while (length-- > 0) {
12991 - if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) {
12992 - return i2c_report_err(-1, I2C_ERR_WRITE);
12993 - }
12994 +#ifdef CONFIG_DM_I2C
12995 + ret = i2c_write(dev, devaddr++, memaddr++, 1);
12996 +#else
12997 + ret = i2c_write(chip, devaddr++, alen, memaddr++, 1);
12998 +#endif
12999 + if (ret)
13000 + return i2c_report_err(ret, I2C_ERR_WRITE);
13001 /*
13002 * No write delay with FRAM devices.
13003 */
13004 @@ -311,6 +397,38 @@
13005 return 0;
13006 }
13007
13008 +#ifdef CONFIG_DM_I2C
13009 +static int do_i2c_flags(cmd_tbl_t *cmdtp, int flag, int argc,
13010 + char *const argv[])
13011 +{
13012 + struct udevice *dev;
13013 + uint flags;
13014 + int chip;
13015 + int ret;
13016 +
13017 + if (argc < 2)
13018 + return CMD_RET_USAGE;
13019 +
13020 + chip = simple_strtoul(argv[1], NULL, 16);
13021 + ret = i2c_get_cur_bus_chip(chip, &dev);
13022 + if (ret)
13023 + return i2c_report_err(ret, I2C_ERR_READ);
13024 +
13025 + if (argc > 2) {
13026 + flags = simple_strtoul(argv[2], NULL, 16);
13027 + ret = i2c_set_chip_flags(dev, flags);
13028 + } else {
13029 + ret = i2c_get_chip_flags(dev, &flags);
13030 + if (!ret)
13031 + printf("%x\n", flags);
13032 + }
13033 + if (ret)
13034 + return i2c_report_err(ret, I2C_ERR_READ);
13035 +
13036 + return 0;
13037 +}
13038 +#endif
13039 +
13040 /**
13041 * do_i2c_md() - Handle the "i2c md" command-line command
13042 * @cmdtp: Command data struct pointer
13043 @@ -327,8 +445,13 @@
13044 static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
13045 {
13046 u_char chip;
13047 - uint addr, alen, length;
13048 + uint addr, length;
13049 + int alen;
13050 int j, nbytes, linebytes;
13051 + int ret;
13052 +#ifdef CONFIG_DM_I2C
13053 + struct udevice *dev;
13054 +#endif
13055
13056 /* We use the last specified parameters, unless new ones are
13057 * entered.
13058 @@ -356,7 +479,7 @@
13059 * 2 bytes long. Some day it might be 3 bytes long :-).
13060 */
13061 addr = simple_strtoul(argv[2], NULL, 16);
13062 - alen = get_alen(argv[2]);
13063 + alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
13064 if (alen > 3)
13065 return CMD_RET_USAGE;
13066
13067 @@ -368,6 +491,14 @@
13068 length = simple_strtoul(argv[3], NULL, 16);
13069 }
13070
13071 +#ifdef CONFIG_DM_I2C
13072 + ret = i2c_get_cur_bus_chip(chip, &dev);
13073 + if (!ret && alen != -1)
13074 + ret = i2c_set_chip_offset_len(dev, alen);
13075 + if (ret)
13076 + return i2c_report_err(ret, I2C_ERR_READ);
13077 +#endif
13078 +
13079 /*
13080 * Print the lines.
13081 *
13082 @@ -381,8 +512,13 @@
13083
13084 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
13085
13086 - if (i2c_read(chip, addr, alen, linebuf, linebytes) != 0)
13087 - i2c_report_err(-1, I2C_ERR_READ);
13088 +#ifdef CONFIG_DM_I2C
13089 + ret = i2c_read(dev, addr, linebuf, linebytes);
13090 +#else
13091 + ret = i2c_read(chip, addr, alen, linebuf, linebytes);
13092 +#endif
13093 + if (ret)
13094 + i2c_report_err(ret, I2C_ERR_READ);
13095 else {
13096 printf("%04x:", addr);
13097 cp = linebuf;
13098 @@ -429,9 +565,13 @@
13099 {
13100 uchar chip;
13101 ulong addr;
13102 - uint alen;
13103 + int alen;
13104 uchar byte;
13105 int count;
13106 + int ret;
13107 +#ifdef CONFIG_DM_I2C
13108 + struct udevice *dev;
13109 +#endif
13110
13111 if ((argc < 4) || (argc > 5))
13112 return CMD_RET_USAGE;
13113 @@ -445,10 +585,17 @@
13114 * Address is always specified.
13115 */
13116 addr = simple_strtoul(argv[2], NULL, 16);
13117 - alen = get_alen(argv[2]);
13118 + alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
13119 if (alen > 3)
13120 return CMD_RET_USAGE;
13121
13122 +#ifdef CONFIG_DM_I2C
13123 + ret = i2c_get_cur_bus_chip(chip, &dev);
13124 + if (!ret && alen != -1)
13125 + ret = i2c_set_chip_offset_len(dev, alen);
13126 + if (ret)
13127 + return i2c_report_err(ret, I2C_ERR_WRITE);
13128 +#endif
13129 /*
13130 * Value to write is always specified.
13131 */
13132 @@ -463,8 +610,13 @@
13133 count = 1;
13134
13135 while (count-- > 0) {
13136 - if (i2c_write(chip, addr++, alen, &byte, 1) != 0)
13137 - i2c_report_err(-1, I2C_ERR_WRITE);
13138 +#ifdef CONFIG_DM_I2C
13139 + ret = i2c_write(dev, addr++, &byte, 1);
13140 +#else
13141 + ret = i2c_write(chip, addr++, alen, &byte, 1);
13142 +#endif
13143 + if (ret)
13144 + i2c_report_err(ret, I2C_ERR_WRITE);
13145 /*
13146 * Wait for the write to complete. The write can take
13147 * up to 10mSec (we allow a little more time).
13148 @@ -499,11 +651,15 @@
13149 {
13150 uchar chip;
13151 ulong addr;
13152 - uint alen;
13153 + int alen;
13154 int count;
13155 uchar byte;
13156 ulong crc;
13157 ulong err;
13158 + int ret = 0;
13159 +#ifdef CONFIG_DM_I2C
13160 + struct udevice *dev;
13161 +#endif
13162
13163 if (argc < 4)
13164 return CMD_RET_USAGE;
13165 @@ -517,10 +673,17 @@
13166 * Address is always specified.
13167 */
13168 addr = simple_strtoul(argv[2], NULL, 16);
13169 - alen = get_alen(argv[2]);
13170 + alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
13171 if (alen > 3)
13172 return CMD_RET_USAGE;
13173
13174 +#ifdef CONFIG_DM_I2C
13175 + ret = i2c_get_cur_bus_chip(chip, &dev);
13176 + if (!ret && alen != -1)
13177 + ret = i2c_set_chip_offset_len(dev, alen);
13178 + if (ret)
13179 + return i2c_report_err(ret, I2C_ERR_READ);
13180 +#endif
13181 /*
13182 * Count is always specified
13183 */
13184 @@ -534,13 +697,18 @@
13185 crc = 0;
13186 err = 0;
13187 while (count-- > 0) {
13188 - if (i2c_read(chip, addr, alen, &byte, 1) != 0)
13189 +#ifdef CONFIG_DM_I2C
13190 + ret = i2c_read(dev, addr, &byte, 1);
13191 +#else
13192 + ret = i2c_read(chip, addr, alen, &byte, 1);
13193 +#endif
13194 + if (ret)
13195 err++;
13196 crc = crc32 (crc, &byte, 1);
13197 addr++;
13198 }
13199 if (err > 0)
13200 - i2c_report_err(-1, I2C_ERR_READ);
13201 + i2c_report_err(ret, I2C_ERR_READ);
13202 else
13203 printf ("%08lx\n", crc);
13204
13205 @@ -568,10 +736,14 @@
13206 {
13207 uchar chip;
13208 ulong addr;
13209 - uint alen;
13210 + int alen;
13211 ulong data;
13212 int size = 1;
13213 int nbytes;
13214 + int ret;
13215 +#ifdef CONFIG_DM_I2C
13216 + struct udevice *dev;
13217 +#endif
13218
13219 if (argc != 3)
13220 return CMD_RET_USAGE;
13221 @@ -601,19 +773,32 @@
13222 * Address is always specified.
13223 */
13224 addr = simple_strtoul(argv[2], NULL, 16);
13225 - alen = get_alen(argv[2]);
13226 + alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
13227 if (alen > 3)
13228 return CMD_RET_USAGE;
13229 }
13230
13231 +#ifdef CONFIG_DM_I2C
13232 + ret = i2c_get_cur_bus_chip(chip, &dev);
13233 + if (!ret && alen != -1)
13234 + ret = i2c_set_chip_offset_len(dev, alen);
13235 + if (ret)
13236 + return i2c_report_err(ret, I2C_ERR_WRITE);
13237 +#endif
13238 +
13239 /*
13240 * Print the address, followed by value. Then accept input for
13241 * the next value. A non-converted value exits.
13242 */
13243 do {
13244 printf("%08lx:", addr);
13245 - if (i2c_read(chip, addr, alen, (uchar *)&data, size) != 0)
13246 - i2c_report_err(-1, I2C_ERR_READ);
13247 +#ifdef CONFIG_DM_I2C
13248 + ret = i2c_read(dev, addr, (uchar *)&data, size);
13249 +#else
13250 + ret = i2c_read(chip, addr, alen, (uchar *)&data, size);
13251 +#endif
13252 + if (ret)
13253 + i2c_report_err(ret, I2C_ERR_READ);
13254 else {
13255 data = cpu_to_be32(data);
13256 if (size == 1)
13257 @@ -655,8 +840,15 @@
13258 * good enough to not time out
13259 */
13260 bootretry_reset_cmd_timeout();
13261 - if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
13262 - i2c_report_err(-1, I2C_ERR_WRITE);
13263 +#ifdef CONFIG_DM_I2C
13264 + ret = i2c_write(dev, addr, (uchar *)&data,
13265 + size);
13266 +#else
13267 + ret = i2c_write(chip, addr, alen,
13268 + (uchar *)&data, size);
13269 +#endif
13270 + if (ret)
13271 + i2c_report_err(ret, I2C_ERR_WRITE);
13272 #ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
13273 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
13274 #endif
13275 @@ -697,6 +889,13 @@
13276 int k, skip;
13277 unsigned int bus = GET_BUS_NUM;
13278 #endif /* NOPROBES */
13279 + int ret;
13280 +#ifdef CONFIG_DM_I2C
13281 + struct udevice *bus, *dev;
13282 +
13283 + if (i2c_get_cur_bus(&bus))
13284 + return CMD_RET_FAILURE;
13285 +#endif
13286
13287 if (argc == 2)
13288 addr = simple_strtol(argv[1], 0, 16);
13289 @@ -717,7 +916,12 @@
13290 if (skip)
13291 continue;
13292 #endif
13293 - if (i2c_probe(j) == 0) {
13294 +#ifdef CONFIG_DM_I2C
13295 + ret = i2c_probe(bus, j, 0, &dev);
13296 +#else
13297 + ret = i2c_probe(j);
13298 +#endif
13299 + if (ret == 0) {
13300 printf(" %02X", j);
13301 found++;
13302 }
13303 @@ -754,11 +958,15 @@
13304 static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
13305 {
13306 u_char chip;
13307 - ulong alen;
13308 + int alen;
13309 uint addr;
13310 uint length;
13311 u_char bytes[16];
13312 int delay;
13313 + int ret;
13314 +#ifdef CONFIG_DM_I2C
13315 + struct udevice *dev;
13316 +#endif
13317
13318 if (argc < 3)
13319 return CMD_RET_USAGE;
13320 @@ -772,9 +980,16 @@
13321 * Address is always specified.
13322 */
13323 addr = simple_strtoul(argv[2], NULL, 16);
13324 - alen = get_alen(argv[2]);
13325 + alen = get_alen(argv[2], DEFAULT_ADDR_LEN);
13326 if (alen > 3)
13327 return CMD_RET_USAGE;
13328 +#ifdef CONFIG_DM_I2C
13329 + ret = i2c_get_cur_bus_chip(chip, &dev);
13330 + if (!ret && alen != -1)
13331 + ret = i2c_set_chip_offset_len(dev, alen);
13332 + if (ret)
13333 + return i2c_report_err(ret, I2C_ERR_WRITE);
13334 +#endif
13335
13336 /*
13337 * Length is the number of objects, not number of bytes.
13338 @@ -794,8 +1009,13 @@
13339 * Run the loop...
13340 */
13341 while (1) {
13342 - if (i2c_read(chip, addr, alen, bytes, length) != 0)
13343 - i2c_report_err(-1, I2C_ERR_READ);
13344 +#ifdef CONFIG_DM_I2C
13345 + ret = i2c_read(dev, addr, bytes, length);
13346 +#else
13347 + ret = i2c_read(chip, addr, alen, bytes, length);
13348 +#endif
13349 + if (ret)
13350 + i2c_report_err(ret, I2C_ERR_READ);
13351 udelay(delay);
13352 }
13353
13354 @@ -1345,6 +1565,10 @@
13355 {
13356 u_char chip;
13357 struct edid1_info edid;
13358 + int ret;
13359 +#ifdef CONFIG_DM_I2C
13360 + struct udevice *dev;
13361 +#endif
13362
13363 if (argc < 2) {
13364 cmd_usage(cmdtp);
13365 @@ -1352,10 +1576,15 @@
13366 }
13367
13368 chip = simple_strtoul(argv[1], NULL, 16);
13369 - if (i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid)) != 0) {
13370 - i2c_report_err(-1, I2C_ERR_READ);
13371 - return 1;
13372 - }
13373 +#ifdef CONFIG_DM_I2C
13374 + ret = i2c_get_cur_bus_chip(chip, &dev);
13375 + if (!ret)
13376 + ret = i2c_read(dev, 0, (uchar *)&edid, sizeof(edid));
13377 +#else
13378 + ret = i2c_read(chip, 0, 1, (uchar *)&edid, sizeof(edid));
13379 +#endif
13380 + if (ret)
13381 + return i2c_report_err(ret, I2C_ERR_READ);
13382
13383 if (edid_check_info(&edid)) {
13384 puts("Content isn't valid EDID.\n");
13385 @@ -1437,17 +1666,28 @@
13386 * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
13387 * on error.
13388 */
13389 -#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS)
13390 +#if defined(CONFIG_SYS_I2C) || defined(CONFIG_I2C_MULTI_BUS) || \
13391 + defined(CONFIG_DM_I2C)
13392 static int do_i2c_bus_num(cmd_tbl_t *cmdtp, int flag, int argc,
13393 char * const argv[])
13394 {
13395 int ret = 0;
13396 - unsigned int bus_no;
13397 + int bus_no;
13398
13399 - if (argc == 1)
13400 + if (argc == 1) {
13401 /* querying current setting */
13402 - printf("Current bus is %d\n", i2c_get_bus_num());
13403 - else {
13404 +#ifdef CONFIG_DM_I2C
13405 + struct udevice *bus;
13406 +
13407 + if (!i2c_get_cur_bus(&bus))
13408 + bus_no = bus->seq;
13409 + else
13410 + bus_no = -1;
13411 +#else
13412 + bus_no = i2c_get_bus_num();
13413 +#endif
13414 + printf("Current bus is %d\n", bus_no);
13415 + } else {
13416 bus_no = simple_strtoul(argv[1], NULL, 10);
13417 #if defined(CONFIG_SYS_I2C)
13418 if (bus_no >= CONFIG_SYS_NUM_I2C_BUSES) {
13419 @@ -1478,13 +1718,28 @@
13420 {
13421 int speed, ret=0;
13422
13423 - if (argc == 1)
13424 +#ifdef CONFIG_DM_I2C
13425 + struct udevice *bus;
13426 +
13427 + if (i2c_get_cur_bus(&bus))
13428 + return 1;
13429 +#endif
13430 + if (argc == 1) {
13431 +#ifdef CONFIG_DM_I2C
13432 + speed = i2c_get_bus_speed(bus);
13433 +#else
13434 + speed = i2c_get_bus_speed();
13435 +#endif
13436 /* querying current speed */
13437 - printf("Current bus speed=%d\n", i2c_get_bus_speed());
13438 - else {
13439 + printf("Current bus speed=%d\n", speed);
13440 + } else {
13441 speed = simple_strtoul(argv[1], NULL, 10);
13442 printf("Setting bus speed to %d Hz\n", speed);
13443 +#ifdef CONFIG_DM_I2C
13444 + ret = i2c_set_bus_speed(bus, speed);
13445 +#else
13446 ret = i2c_set_bus_speed(speed);
13447 +#endif
13448 if (ret)
13449 printf("Failure changing bus speed (%d)\n", ret);
13450 }
13451 @@ -1532,7 +1787,16 @@
13452 */
13453 static int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
13454 {
13455 -#if defined(CONFIG_SYS_I2C)
13456 +#if defined(CONFIG_DM_I2C)
13457 + struct udevice *bus;
13458 +
13459 + if (i2c_get_cur_bus(&bus))
13460 + return CMD_RET_FAILURE;
13461 + if (i2c_deblock(bus)) {
13462 + printf("Error: Not supported by the driver\n");
13463 + return CMD_RET_FAILURE;
13464 + }
13465 +#elif defined(CONFIG_SYS_I2C)
13466 i2c_init(I2C_ADAP->speed, I2C_ADAP->slaveaddr);
13467 #else
13468 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
13469 @@ -1546,7 +1810,7 @@
13470 #endif
13471 U_BOOT_CMD_MKENT(crc32, 3, 1, do_i2c_crc, "", ""),
13472 #if defined(CONFIG_SYS_I2C) || \
13473 - defined(CONFIG_I2C_MULTI_BUS)
13474 + defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
13475 U_BOOT_CMD_MKENT(dev, 1, 1, do_i2c_bus_num, "", ""),
13476 #endif /* CONFIG_I2C_MULTI_BUS */
13477 #if defined(CONFIG_I2C_EDID)
13478 @@ -1560,6 +1824,9 @@
13479 U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
13480 U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
13481 U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""),
13482 +#ifdef CONFIG_DM_I2C
13483 + U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""),
13484 +#endif
13485 U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
13486 #if defined(CONFIG_CMD_SDRAM)
13487 U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
13488 @@ -1610,7 +1877,7 @@
13489 #endif
13490 "crc32 chip address[.0, .1, .2] count - compute CRC32 checksum\n"
13491 #if defined(CONFIG_SYS_I2C) || \
13492 - defined(CONFIG_I2C_MULTI_BUS)
13493 + defined(CONFIG_I2C_MULTI_BUS) || defined(CONFIG_DM_I2C)
13494 "i2c dev [dev] - show or set current I2C bus\n"
13495 #endif /* CONFIG_I2C_MULTI_BUS */
13496 #if defined(CONFIG_I2C_EDID)
13497 @@ -1622,8 +1889,11 @@
13498 "i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
13499 "i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
13500 "i2c probe [address] - test for and show device(s) on the I2C bus\n"
13501 - "i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
13502 + "i2c read chip address[.0, .1, .2] length memaddress - read to memory\n"
13503 "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n"
13504 +#ifdef CONFIG_DM_I2C
13505 + "i2c flags chip [flags] - set or get chip flags\n"
13506 +#endif
13507 "i2c reset - re-init the I2C Controller\n"
13508 #if defined(CONFIG_CMD_SDRAM)
13509 "i2c sdram chip - print SDRAM configuration information\n"
13510 diff -ruN u-boot-2015.01-rc3/common/cmd_mmc.c u-boot/common/cmd_mmc.c
13511 --- u-boot-2015.01-rc3/common/cmd_mmc.c 2014-12-08 22:35:08.000000000 +0100
13512 +++ u-boot/common/cmd_mmc.c 2015-01-01 17:34:32.529498727 +0100
13513 @@ -90,7 +90,8 @@
13514 puts("Capacity: ");
13515 print_size(mmc->capacity, "\n");
13516
13517 - printf("Bus Width: %d-bit\n", mmc->bus_width);
13518 + printf("Bus Width: %d-bit%s\n", mmc->bus_width,
13519 + mmc->ddr_mode ? " DDR" : "");
13520 }
13521 static struct mmc *init_mmc_device(int dev, bool force_init)
13522 {
13523 diff -ruN u-boot-2015.01-rc3/common/fb_mmc.c u-boot/common/fb_mmc.c
13524 --- u-boot-2015.01-rc3/common/fb_mmc.c 2014-12-08 22:35:08.000000000 +0100
13525 +++ u-boot/common/fb_mmc.c 2015-01-01 17:34:32.537498596 +0100
13526 @@ -4,12 +4,17 @@
13527 * SPDX-License-Identifier: GPL-2.0+
13528 */
13529
13530 +#include <config.h>
13531 #include <common.h>
13532 #include <fb_mmc.h>
13533 #include <part.h>
13534 #include <aboot.h>
13535 #include <sparse_format.h>
13536
13537 +#ifndef CONFIG_FASTBOOT_GPT_NAME
13538 +#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
13539 +#endif
13540 +
13541 /* The 64 defined bytes plus the '\0' */
13542 #define RESPONSE_LEN (64 + 1)
13543
13544 @@ -62,7 +67,6 @@
13545 void fb_mmc_flash_write(const char *cmd, void *download_buffer,
13546 unsigned int download_bytes, char *response)
13547 {
13548 - int ret;
13549 block_dev_desc_t *dev_desc;
13550 disk_partition_t info;
13551
13552 @@ -76,8 +80,24 @@
13553 return;
13554 }
13555
13556 - ret = get_partition_info_efi_by_name(dev_desc, cmd, &info);
13557 - if (ret) {
13558 + if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) {
13559 + printf("%s: updating MBR, Primary and Backup GPT(s)\n",
13560 + __func__);
13561 + if (is_valid_gpt_buf(dev_desc, download_buffer)) {
13562 + printf("%s: invalid GPT - refusing to write to flash\n",
13563 + __func__);
13564 + fastboot_fail("invalid GPT partition");
13565 + return;
13566 + }
13567 + if (write_mbr_and_gpt_partitions(dev_desc, download_buffer)) {
13568 + printf("%s: writing GPT partitions failed\n", __func__);
13569 + fastboot_fail("writing GPT partitions failed");
13570 + return;
13571 + }
13572 + printf("........ success\n");
13573 + fastboot_okay("");
13574 + return;
13575 + } else if (get_partition_info_efi_by_name(dev_desc, cmd, &info)) {
13576 error("cannot find partition: '%s'\n", cmd);
13577 fastboot_fail("cannot find partition");
13578 return;
13579 diff -ruN u-boot-2015.01-rc3/common/hash.c u-boot/common/hash.c
13580 --- u-boot-2015.01-rc3/common/hash.c 2014-12-08 22:35:08.000000000 +0100
13581 +++ u-boot/common/hash.c 2015-01-01 17:34:32.537498596 +0100
13582 @@ -256,7 +256,7 @@
13583 env_var = 1;
13584 }
13585
13586 - if (env_var) {
13587 + if (!env_var) {
13588 ulong addr;
13589 void *buf;
13590
13591 @@ -347,7 +347,7 @@
13592 {
13593 ulong addr, len;
13594
13595 - if (argc < 2)
13596 + if ((argc < 2) || ((flags & HASH_FLAG_VERIFY) && (argc < 3)))
13597 return CMD_RET_USAGE;
13598
13599 addr = simple_strtoul(*argv++, NULL, 16);
13600 @@ -380,8 +380,6 @@
13601 #else
13602 if (0) {
13603 #endif
13604 - if (!argc)
13605 - return CMD_RET_USAGE;
13606 if (parse_verify_sum(algo, *argv, vsum,
13607 flags & HASH_FLAG_ENV)) {
13608 printf("ERROR: %s does not contain a valid "
13609 diff -ruN u-boot-2015.01-rc3/configs/armadillo-800eva_defconfig u-boot/configs/armadillo-800eva_defconfig
13610 --- u-boot-2015.01-rc3/configs/armadillo-800eva_defconfig 2014-12-08 22:35:08.000000000 +0100
13611 +++ u-boot/configs/armadillo-800eva_defconfig 2015-01-01 17:34:32.557498268 +0100
13612 @@ -1,3 +1,3 @@
13613 CONFIG_ARM=y
13614 -+S:CONFIG_RMOBILE=y
13615 +CONFIG_RMOBILE=y
13616 CONFIG_TARGET_ARMADILLO_800EVA=y
13617 diff -ruN u-boot-2015.01-rc3/configs/crownbay_defconfig u-boot/configs/crownbay_defconfig
13618 --- u-boot-2015.01-rc3/configs/crownbay_defconfig 1970-01-01 01:00:00.000000000 +0100
13619 +++ u-boot/configs/crownbay_defconfig 2015-01-01 17:34:32.561498202 +0100
13620 @@ -0,0 +1,6 @@
13621 +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
13622 +CONFIG_X86=y
13623 +CONFIG_TARGET_CROWNBAY=y
13624 +CONFIG_OF_CONTROL=y
13625 +CONFIG_OF_SEPARATE=y
13626 +CONFIG_DEFAULT_DEVICE_TREE="crownbay"
13627 diff -ruN u-boot-2015.01-rc3/configs/kzm9g_defconfig u-boot/configs/kzm9g_defconfig
13628 --- u-boot-2015.01-rc3/configs/kzm9g_defconfig 2014-12-08 22:35:08.000000000 +0100
13629 +++ u-boot/configs/kzm9g_defconfig 2015-01-01 17:34:32.561498202 +0100
13630 @@ -1,3 +1,3 @@
13631 CONFIG_ARM=y
13632 -+S:CONFIG_RMOBILE=y
13633 +CONFIG_RMOBILE=y
13634 CONFIG_TARGET_KZM9G=y
13635 diff -ruN u-boot-2015.01-rc3/configs/ls1021aqds_nand_defconfig u-boot/configs/ls1021aqds_nand_defconfig
13636 --- u-boot-2015.01-rc3/configs/ls1021aqds_nand_defconfig 1970-01-01 01:00:00.000000000 +0100
13637 +++ u-boot/configs/ls1021aqds_nand_defconfig 2015-01-01 17:34:32.561498202 +0100
13638 @@ -0,0 +1,4 @@
13639 +CONFIG_SPL=y
13640 +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
13641 ++S:CONFIG_ARM=y
13642 ++S:CONFIG_TARGET_LS1021AQDS=y
13643 diff -ruN u-boot-2015.01-rc3/configs/ls1021aqds_qspi_defconfig u-boot/configs/ls1021aqds_qspi_defconfig
13644 --- u-boot-2015.01-rc3/configs/ls1021aqds_qspi_defconfig 1970-01-01 01:00:00.000000000 +0100
13645 +++ u-boot/configs/ls1021aqds_qspi_defconfig 2015-01-01 17:34:32.561498202 +0100
13646 @@ -0,0 +1,3 @@
13647 +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
13648 ++S:CONFIG_ARM=y
13649 ++S:CONFIG_TARGET_LS1021AQDS=y
13650 diff -ruN u-boot-2015.01-rc3/configs/ls1021aqds_sdcard_defconfig u-boot/configs/ls1021aqds_sdcard_defconfig
13651 --- u-boot-2015.01-rc3/configs/ls1021aqds_sdcard_defconfig 1970-01-01 01:00:00.000000000 +0100
13652 +++ u-boot/configs/ls1021aqds_sdcard_defconfig 2015-01-01 17:34:32.565498136 +0100
13653 @@ -0,0 +1,4 @@
13654 +CONFIG_SPL=y
13655 +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
13656 ++S:CONFIG_ARM=y
13657 ++S:CONFIG_TARGET_LS1021AQDS=y
13658 diff -ruN u-boot-2015.01-rc3/configs/ls1021atwr_qspi_defconfig u-boot/configs/ls1021atwr_qspi_defconfig
13659 --- u-boot-2015.01-rc3/configs/ls1021atwr_qspi_defconfig 1970-01-01 01:00:00.000000000 +0100
13660 +++ u-boot/configs/ls1021atwr_qspi_defconfig 2015-01-01 17:34:32.565498136 +0100
13661 @@ -0,0 +1,3 @@
13662 +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
13663 ++S:CONFIG_ARM=y
13664 ++S:CONFIG_TARGET_LS1021ATWR=y
13665 diff -ruN u-boot-2015.01-rc3/configs/ls1021atwr_sdcard_defconfig u-boot/configs/ls1021atwr_sdcard_defconfig
13666 --- u-boot-2015.01-rc3/configs/ls1021atwr_sdcard_defconfig 1970-01-01 01:00:00.000000000 +0100
13667 +++ u-boot/configs/ls1021atwr_sdcard_defconfig 2015-01-01 17:34:32.565498136 +0100
13668 @@ -0,0 +1,4 @@
13669 +CONFIG_SPL=y
13670 +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
13671 ++S:CONFIG_ARM=y
13672 ++S:CONFIG_TARGET_LS1021ATWR=y
13673 diff -ruN u-boot-2015.01-rc3/configs/nyan-big_defconfig u-boot/configs/nyan-big_defconfig
13674 --- u-boot-2015.01-rc3/configs/nyan-big_defconfig 1970-01-01 01:00:00.000000000 +0100
13675 +++ u-boot/configs/nyan-big_defconfig 2015-01-01 17:34:32.565498136 +0100
13676 @@ -0,0 +1,5 @@
13677 ++S:CONFIG_ARM=y
13678 ++S:CONFIG_TEGRA=y
13679 ++S:CONFIG_TEGRA124=y
13680 ++S:CONFIG_TARGET_NYAN_BIG=y
13681 +CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big"
13682 diff -ruN u-boot-2015.01-rc3/configs/ph1_ld4_defconfig u-boot/configs/ph1_ld4_defconfig
13683 --- u-boot-2015.01-rc3/configs/ph1_ld4_defconfig 2014-12-08 22:35:08.000000000 +0100
13684 +++ u-boot/configs/ph1_ld4_defconfig 2015-01-01 17:34:32.565498136 +0100
13685 @@ -1,4 +1,3 @@
13686 -CONFIG_SPL=y
13687 CONFIG_FIT=y
13688 CONFIG_FIT_VERBOSE=y
13689 +S:CONFIG_ARM=y
13690 diff -ruN u-boot-2015.01-rc3/configs/ph1_pro4_defconfig u-boot/configs/ph1_pro4_defconfig
13691 --- u-boot-2015.01-rc3/configs/ph1_pro4_defconfig 2014-12-08 22:35:08.000000000 +0100
13692 +++ u-boot/configs/ph1_pro4_defconfig 2015-01-01 17:34:32.565498136 +0100
13693 @@ -1,4 +1,3 @@
13694 -CONFIG_SPL=y
13695 CONFIG_FIT=y
13696 CONFIG_FIT_VERBOSE=y
13697 +S:CONFIG_ARM=y
13698 diff -ruN u-boot-2015.01-rc3/configs/ph1_sld8_defconfig u-boot/configs/ph1_sld8_defconfig
13699 --- u-boot-2015.01-rc3/configs/ph1_sld8_defconfig 2014-12-08 22:35:08.000000000 +0100
13700 +++ u-boot/configs/ph1_sld8_defconfig 2015-01-01 17:34:32.565498136 +0100
13701 @@ -1,4 +1,3 @@
13702 -CONFIG_SPL=y
13703 CONFIG_FIT=y
13704 CONFIG_FIT_VERBOSE=y
13705 +S:CONFIG_ARM=y
13706 diff -ruN u-boot-2015.01-rc3/configs/stv0991_defconfig u-boot/configs/stv0991_defconfig
13707 --- u-boot-2015.01-rc3/configs/stv0991_defconfig 1970-01-01 01:00:00.000000000 +0100
13708 +++ u-boot/configs/stv0991_defconfig 2015-01-01 17:34:32.569498072 +0100
13709 @@ -0,0 +1,3 @@
13710 +CONFIG_SYS_EXTRA_OPTIONS="stv0991"
13711 +CONFIG_ARM=y
13712 +CONFIG_TARGET_STV0991=y
13713 diff -ruN u-boot-2015.01-rc3/disk/part_efi.c u-boot/disk/part_efi.c
13714 --- u-boot-2015.01-rc3/disk/part_efi.c 2014-12-08 22:35:08.000000000 +0100
13715 +++ u-boot/disk/part_efi.c 2015-01-01 17:34:32.573498006 +0100
13716 @@ -69,6 +69,107 @@
13717 sizeof(efi_guid_t));
13718 }
13719
13720 +static int validate_gpt_header(gpt_header *gpt_h, lbaint_t lba,
13721 + lbaint_t lastlba)
13722 +{
13723 + uint32_t crc32_backup = 0;
13724 + uint32_t calc_crc32;
13725 +
13726 + /* Check the GPT header signature */
13727 + if (le64_to_cpu(gpt_h->signature) != GPT_HEADER_SIGNATURE) {
13728 + printf("%s signature is wrong: 0x%llX != 0x%llX\n",
13729 + "GUID Partition Table Header",
13730 + le64_to_cpu(gpt_h->signature),
13731 + GPT_HEADER_SIGNATURE);
13732 + return -1;
13733 + }
13734 +
13735 + /* Check the GUID Partition Table CRC */
13736 + memcpy(&crc32_backup, &gpt_h->header_crc32, sizeof(crc32_backup));
13737 + memset(&gpt_h->header_crc32, 0, sizeof(gpt_h->header_crc32));
13738 +
13739 + calc_crc32 = efi_crc32((const unsigned char *)gpt_h,
13740 + le32_to_cpu(gpt_h->header_size));
13741 +
13742 + memcpy(&gpt_h->header_crc32, &crc32_backup, sizeof(crc32_backup));
13743 +
13744 + if (calc_crc32 != le32_to_cpu(crc32_backup)) {
13745 + printf("%s CRC is wrong: 0x%x != 0x%x\n",
13746 + "GUID Partition Table Header",
13747 + le32_to_cpu(crc32_backup), calc_crc32);
13748 + return -1;
13749 + }
13750 +
13751 + /*
13752 + * Check that the my_lba entry points to the LBA that contains the GPT
13753 + */
13754 + if (le64_to_cpu(gpt_h->my_lba) != lba) {
13755 + printf("GPT: my_lba incorrect: %llX != " LBAF "\n",
13756 + le64_to_cpu(gpt_h->my_lba),
13757 + lba);
13758 + return -1;
13759 + }
13760 +
13761 + /*
13762 + * Check that the first_usable_lba and that the last_usable_lba are
13763 + * within the disk.
13764 + */
13765 + if (le64_to_cpu(gpt_h->first_usable_lba) > lastlba) {
13766 + printf("GPT: first_usable_lba incorrect: %llX > " LBAF "\n",
13767 + le64_to_cpu(gpt_h->first_usable_lba), lastlba);
13768 + return -1;
13769 + }
13770 + if (le64_to_cpu(gpt_h->last_usable_lba) > lastlba) {
13771 + printf("GPT: last_usable_lba incorrect: %llX > " LBAF "\n",
13772 + le64_to_cpu(gpt_h->last_usable_lba), lastlba);
13773 + return -1;
13774 + }
13775 +
13776 + debug("GPT: first_usable_lba: %llX last_usable_lba: %llX last lba: "
13777 + LBAF "\n", le64_to_cpu(gpt_h->first_usable_lba),
13778 + le64_to_cpu(gpt_h->last_usable_lba), lastlba);
13779 +
13780 + return 0;
13781 +}
13782 +
13783 +static int validate_gpt_entries(gpt_header *gpt_h, gpt_entry *gpt_e)
13784 +{
13785 + uint32_t calc_crc32;
13786 +
13787 + /* Check the GUID Partition Table Entry Array CRC */
13788 + calc_crc32 = efi_crc32((const unsigned char *)gpt_e,
13789 + le32_to_cpu(gpt_h->num_partition_entries) *
13790 + le32_to_cpu(gpt_h->sizeof_partition_entry));
13791 +
13792 + if (calc_crc32 != le32_to_cpu(gpt_h->partition_entry_array_crc32)) {
13793 + printf("%s: 0x%x != 0x%x\n",
13794 + "GUID Partition Table Entry Array CRC is wrong",
13795 + le32_to_cpu(gpt_h->partition_entry_array_crc32),
13796 + calc_crc32);
13797 + return -1;
13798 + }
13799 +
13800 + return 0;
13801 +}
13802 +
13803 +static void prepare_backup_gpt_header(gpt_header *gpt_h)
13804 +{
13805 + uint32_t calc_crc32;
13806 + uint64_t val;
13807 +
13808 + /* recalculate the values for the Backup GPT Header */
13809 + val = le64_to_cpu(gpt_h->my_lba);
13810 + gpt_h->my_lba = gpt_h->alternate_lba;
13811 + gpt_h->alternate_lba = cpu_to_le64(val);
13812 + gpt_h->partition_entry_lba =
13813 + cpu_to_le64(le64_to_cpu(gpt_h->last_usable_lba) + 1);
13814 + gpt_h->header_crc32 = 0;
13815 +
13816 + calc_crc32 = efi_crc32((const unsigned char *)gpt_h,
13817 + le32_to_cpu(gpt_h->header_size));
13818 + gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
13819 +}
13820 +
13821 #ifdef CONFIG_EFI_PARTITION
13822 /*
13823 * Public Functions (include/part.h)
13824 @@ -259,7 +360,6 @@
13825 const int pte_blk_cnt = BLOCK_CNT((gpt_h->num_partition_entries
13826 * sizeof(gpt_entry)), dev_desc);
13827 u32 calc_crc32;
13828 - u64 val;
13829
13830 debug("max lba: %x\n", (u32) dev_desc->lba);
13831 /* Setup the Protective MBR */
13832 @@ -284,15 +384,7 @@
13833 != pte_blk_cnt)
13834 goto err;
13835
13836 - /* recalculate the values for the Backup GPT Header */
13837 - val = le64_to_cpu(gpt_h->my_lba);
13838 - gpt_h->my_lba = gpt_h->alternate_lba;
13839 - gpt_h->alternate_lba = cpu_to_le64(val);
13840 - gpt_h->header_crc32 = 0;
13841 -
13842 - calc_crc32 = efi_crc32((const unsigned char *)gpt_h,
13843 - le32_to_cpu(gpt_h->header_size));
13844 - gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
13845 + prepare_backup_gpt_header(gpt_h);
13846
13847 if (dev_desc->block_write(dev_desc->dev,
13848 (lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
13849 @@ -455,6 +547,97 @@
13850 free(gpt_h);
13851 return ret;
13852 }
13853 +
13854 +int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf)
13855 +{
13856 + gpt_header *gpt_h;
13857 + gpt_entry *gpt_e;
13858 +
13859 + /* determine start of GPT Header in the buffer */
13860 + gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA *
13861 + dev_desc->blksz);
13862 + if (validate_gpt_header(gpt_h, GPT_PRIMARY_PARTITION_TABLE_LBA,
13863 + dev_desc->lba))
13864 + return -1;
13865 +
13866 + /* determine start of GPT Entries in the buffer */
13867 + gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) *
13868 + dev_desc->blksz);
13869 + if (validate_gpt_entries(gpt_h, gpt_e))
13870 + return -1;
13871 +
13872 + return 0;
13873 +}
13874 +
13875 +int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf)
13876 +{
13877 + gpt_header *gpt_h;
13878 + gpt_entry *gpt_e;
13879 + int gpt_e_blk_cnt;
13880 + lbaint_t lba;
13881 + int cnt;
13882 +
13883 + if (is_valid_gpt_buf(dev_desc, buf))
13884 + return -1;
13885 +
13886 + /* determine start of GPT Header in the buffer */
13887 + gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA *
13888 + dev_desc->blksz);
13889 +
13890 + /* determine start of GPT Entries in the buffer */
13891 + gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) *
13892 + dev_desc->blksz);
13893 + gpt_e_blk_cnt = BLOCK_CNT((le32_to_cpu(gpt_h->num_partition_entries) *
13894 + le32_to_cpu(gpt_h->sizeof_partition_entry)),
13895 + dev_desc);
13896 +
13897 + /* write MBR */
13898 + lba = 0; /* MBR is always at 0 */
13899 + cnt = 1; /* MBR (1 block) */
13900 + if (dev_desc->block_write(dev_desc->dev, lba, cnt, buf) != cnt) {
13901 + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
13902 + __func__, "MBR", cnt, lba);
13903 + return 1;
13904 + }
13905 +
13906 + /* write Primary GPT */
13907 + lba = GPT_PRIMARY_PARTITION_TABLE_LBA;
13908 + cnt = 1; /* GPT Header (1 block) */
13909 + if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) {
13910 + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
13911 + __func__, "Primary GPT Header", cnt, lba);
13912 + return 1;
13913 + }
13914 +
13915 + lba = le64_to_cpu(gpt_h->partition_entry_lba);
13916 + cnt = gpt_e_blk_cnt;
13917 + if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) {
13918 + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
13919 + __func__, "Primary GPT Entries", cnt, lba);
13920 + return 1;
13921 + }
13922 +
13923 + prepare_backup_gpt_header(gpt_h);
13924 +
13925 + /* write Backup GPT */
13926 + lba = le64_to_cpu(gpt_h->partition_entry_lba);
13927 + cnt = gpt_e_blk_cnt;
13928 + if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_e) != cnt) {
13929 + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
13930 + __func__, "Backup GPT Entries", cnt, lba);
13931 + return 1;
13932 + }
13933 +
13934 + lba = le64_to_cpu(gpt_h->my_lba);
13935 + cnt = 1; /* GPT Header (1 block) */
13936 + if (dev_desc->block_write(dev_desc->dev, lba, cnt, gpt_h) != cnt) {
13937 + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n",
13938 + __func__, "Backup GPT Header", cnt, lba);
13939 + return 1;
13940 + }
13941 +
13942 + return 0;
13943 +}
13944 #endif
13945
13946 /*
13947 @@ -511,10 +694,6 @@
13948 static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba,
13949 gpt_header *pgpt_head, gpt_entry **pgpt_pte)
13950 {
13951 - u32 crc32_backup = 0;
13952 - u32 calc_crc32;
13953 - u64 lastlba;
13954 -
13955 if (!dev_desc || !pgpt_head) {
13956 printf("%s: Invalid Argument(s)\n", __func__);
13957 return 0;
13958 @@ -527,55 +706,8 @@
13959 return 0;
13960 }
13961
13962 - /* Check the GPT header signature */
13963 - if (le64_to_cpu(pgpt_head->signature) != GPT_HEADER_SIGNATURE) {
13964 - printf("GUID Partition Table Header signature is wrong:"
13965 - "0x%llX != 0x%llX\n",
13966 - le64_to_cpu(pgpt_head->signature),
13967 - GPT_HEADER_SIGNATURE);
13968 - return 0;
13969 - }
13970 -
13971 - /* Check the GUID Partition Table CRC */
13972 - memcpy(&crc32_backup, &pgpt_head->header_crc32, sizeof(crc32_backup));
13973 - memset(&pgpt_head->header_crc32, 0, sizeof(pgpt_head->header_crc32));
13974 -
13975 - calc_crc32 = efi_crc32((const unsigned char *)pgpt_head,
13976 - le32_to_cpu(pgpt_head->header_size));
13977 -
13978 - memcpy(&pgpt_head->header_crc32, &crc32_backup, sizeof(crc32_backup));
13979 -
13980 - if (calc_crc32 != le32_to_cpu(crc32_backup)) {
13981 - printf("GUID Partition Table Header CRC is wrong:"
13982 - "0x%x != 0x%x\n",
13983 - le32_to_cpu(crc32_backup), calc_crc32);
13984 - return 0;
13985 - }
13986 -
13987 - /* Check that the my_lba entry points to the LBA that contains the GPT */
13988 - if (le64_to_cpu(pgpt_head->my_lba) != lba) {
13989 - printf("GPT: my_lba incorrect: %llX != %" PRIX64 "\n",
13990 - le64_to_cpu(pgpt_head->my_lba),
13991 - lba);
13992 + if (validate_gpt_header(pgpt_head, (lbaint_t)lba, dev_desc->lba))
13993 return 0;
13994 - }
13995 -
13996 - /* Check the first_usable_lba and last_usable_lba are within the disk. */
13997 - lastlba = (u64)dev_desc->lba;
13998 - if (le64_to_cpu(pgpt_head->first_usable_lba) > lastlba) {
13999 - printf("GPT: first_usable_lba incorrect: %llX > %" PRIX64 "\n",
14000 - le64_to_cpu(pgpt_head->first_usable_lba), lastlba);
14001 - return 0;
14002 - }
14003 - if (le64_to_cpu(pgpt_head->last_usable_lba) > lastlba) {
14004 - printf("GPT: last_usable_lba incorrect: %llX > %" PRIX64 "\n",
14005 - le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
14006 - return 0;
14007 - }
14008 -
14009 - debug("GPT: first_usable_lba: %llX last_usable_lba %llX last lba %"
14010 - PRIX64 "\n", le64_to_cpu(pgpt_head->first_usable_lba),
14011 - le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
14012
14013 /* Read and allocate Partition Table Entries */
14014 *pgpt_pte = alloc_read_gpt_entries(dev_desc, pgpt_head);
14015 @@ -584,17 +716,7 @@
14016 return 0;
14017 }
14018
14019 - /* Check the GUID Partition Table Entry Array CRC */
14020 - calc_crc32 = efi_crc32((const unsigned char *)*pgpt_pte,
14021 - le32_to_cpu(pgpt_head->num_partition_entries) *
14022 - le32_to_cpu(pgpt_head->sizeof_partition_entry));
14023 -
14024 - if (calc_crc32 != le32_to_cpu(pgpt_head->partition_entry_array_crc32)) {
14025 - printf("GUID Partition Table Entry Array CRC is wrong:"
14026 - "0x%x != 0x%x\n",
14027 - le32_to_cpu(pgpt_head->partition_entry_array_crc32),
14028 - calc_crc32);
14029 -
14030 + if (validate_gpt_entries(pgpt_head, *pgpt_pte)) {
14031 free(*pgpt_pte);
14032 return 0;
14033 }
14034 diff -ruN u-boot-2015.01-rc3/doc/README.x86 u-boot/doc/README.x86
14035 --- u-boot-2015.01-rc3/doc/README.x86 1970-01-01 01:00:00.000000000 +0100
14036 +++ u-boot/doc/README.x86 2015-01-01 17:34:32.597497612 +0100
14037 @@ -0,0 +1,126 @@
14038 +#
14039 +# Copyright (C) 2014, Simon Glass <sjg@chromium.org>
14040 +# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
14041 +#
14042 +# SPDX-License-Identifier: GPL-2.0+
14043 +#
14044 +
14045 +U-Boot on x86
14046 +=============
14047 +
14048 +This document describes the information about U-Boot running on x86 targets,
14049 +including supported boards, build instructions, todo list, etc.
14050 +
14051 +Status
14052 +------
14053 +U-Boot supports running as a coreboot [1] payload on x86. So far only Link
14054 +(Chromebook Pixel) has been tested, but it should work with minimal adjustments
14055 +on other x86 boards since coreboot deals with most of the low-level details.
14056 +
14057 +U-Boot also supports booting directly from x86 reset vector without coreboot,
14058 +aka raw support or bare support. Currently Link and Intel Crown Bay board
14059 +support running U-Boot 'bare metal'.
14060 +
14061 +As for loading OS, U-Boot supports directly booting a 32-bit or 64-bit Linux
14062 +kernel as part of a FIT image. It also supports a compressed zImage.
14063 +
14064 +Build Instructions
14065 +------------------
14066 +Building U-Boot as a coreboot payload is just like building U-Boot for targets
14067 +on other architectures, like below:
14068 +
14069 +$ make coreboot-x86_defconfig
14070 +$ make all
14071 +
14072 +Building ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
14073 +little bit tricky, as generally it requires several binary blobs which are not
14074 +shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
14075 +not turned on by default in the U-Boot source tree. Firstly, you need turn it
14076 +on by uncommenting the following line in the main U-Boot Makefile:
14077 +
14078 +# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
14079 +
14080 +Link-specific instructions:
14081 +
14082 +First, you need the following binary blobs:
14083 +
14084 +* descriptor.bin - Intel flash descriptor
14085 +* me.bin - Intel Management Engine
14086 +* mrc.bin - Memory Reference Code, which sets up SDRAM
14087 +* video ROM - sets up the display
14088 +
14089 +You can get these binary blobs by:
14090 +
14091 +$ git clone http://review.coreboot.org/p/blobs.git
14092 +$ cd blobs
14093 +
14094 +Find the following files:
14095 +
14096 +* ./mainboard/google/link/descriptor.bin
14097 +* ./mainboard/google/link/me.bin
14098 +* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin
14099 +
14100 +The 3rd one should be renamed to mrc.bin.
14101 +As for the video ROM, you can get it here [2].
14102 +Make sure all these binary blobs are put in the board directory.
14103 +
14104 +Now you can build U-Boot and obtain u-boot.rom:
14105 +
14106 +$ make chromebook_link_defconfig
14107 +$ make all
14108 +
14109 +Intel Crown Bay specific instructions:
14110 +
14111 +U-Boot support of Intel Crown Bay board [3] relies on a binary blob called
14112 +Firmware Support Package [4] to perform all the necessary initialization steps
14113 +as documented in the BIOS Writer Guide, including initialization of the CPU,
14114 +memory controller, chipset and certain bus interfaces.
14115 +
14116 +Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
14117 +install it on your host and locate the FSP binary blob. Note this platform
14118 +also requires a Chipset Micro Code (CMC) state machine binary to be present in
14119 +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
14120 +in this FSP package too.
14121 +
14122 +* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
14123 +* ./Microcode/C0_22211.BIN
14124 +
14125 +Rename the first one to fsp.bin and second one to cmc.bin and put them in the
14126 +board directory.
14127 +
14128 +Now you can build U-Boot and obtaim u-boot.rom
14129 +
14130 +$ make crownbay_defconfig
14131 +$ make all
14132 +
14133 +CPU Microcode
14134 +-------------
14135 +Modern CPU usually requires a special bit stream called microcode [5] to be
14136 +loaded on the processor after power up in order to function properly. U-Boot
14137 +has already integrated these as hex dumps in the source tree.
14138 +
14139 +Driver Model
14140 +------------
14141 +x86 has been converted to use driver model for serial and GPIO.
14142 +
14143 +Device Tree
14144 +-----------
14145 +x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
14146 +be turned on. Not every device on the board is configured via devie tree, but
14147 +more and more devices will be added as time goes by. Check out the directory
14148 +arch/x86/dts/ for these device tree source files.
14149 +
14150 +TODO List
14151 +---------
14152 +- MTRR support (for performance)
14153 +- Audio
14154 +- Chrome OS verified boot
14155 +- SMI and ACPI support, to provide platform info and facilities to Linux
14156 +
14157 +References
14158 +----------
14159 +[1] http://www.coreboot.org
14160 +[2] http://www.coreboot.org/~stepan/pci8086,0166.rom
14161 +[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
14162 +[4] http://www.intel.com/fsp
14163 +[5] http://en.wikipedia.org/wiki/Microcode
14164 diff -ruN u-boot-2015.01-rc3/drivers/bios_emulator/besys.c u-boot/drivers/bios_emulator/besys.c
14165 --- u-boot-2015.01-rc3/drivers/bios_emulator/besys.c 2014-12-08 22:35:08.000000000 +0100
14166 +++ u-boot/drivers/bios_emulator/besys.c 2015-01-01 17:34:32.605497481 +0100
14167 @@ -48,8 +48,8 @@
14168 ****************************************************************************/
14169
14170 #define __io
14171 -#include <asm/io.h>
14172 #include <common.h>
14173 +#include <asm/io.h>
14174 #include "biosemui.h"
14175
14176 /*------------------------- Global Variables ------------------------------*/
14177 diff -ruN u-boot-2015.01-rc3/drivers/bios_emulator/bios.c u-boot/drivers/bios_emulator/bios.c
14178 --- u-boot-2015.01-rc3/drivers/bios_emulator/bios.c 2014-12-08 22:35:08.000000000 +0100
14179 +++ u-boot/drivers/bios_emulator/bios.c 2015-01-01 17:34:32.605497481 +0100
14180 @@ -42,8 +42,8 @@
14181 ****************************************************************************/
14182
14183 #define __io
14184 -#include <asm/io.h>
14185 #include <common.h>
14186 +#include <asm/io.h>
14187 #include "biosemui.h"
14188
14189 /*----------------------------- Implementation ----------------------------*/
14190 diff -ruN u-boot-2015.01-rc3/drivers/block/dwc_ahsata.c u-boot/drivers/block/dwc_ahsata.c
14191 --- u-boot-2015.01-rc3/drivers/block/dwc_ahsata.c 2014-12-08 22:35:08.000000000 +0100
14192 +++ u-boot/drivers/block/dwc_ahsata.c 2015-01-01 17:34:32.613497350 +0100
14193 @@ -594,22 +594,24 @@
14194
14195 int reset_sata(int dev)
14196 {
14197 - struct ahci_probe_ent *probe_ent =
14198 - (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
14199 - struct sata_host_regs *host_mmio =
14200 - (struct sata_host_regs *)probe_ent->mmio_base;
14201 + struct ahci_probe_ent *probe_ent;
14202 + struct sata_host_regs *host_mmio;
14203
14204 if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
14205 printf("The sata index %d is out of ranges\n\r", dev);
14206 return -1;
14207 }
14208
14209 + probe_ent = (struct ahci_probe_ent *)sata_dev_desc[dev].priv;
14210 + if (NULL == probe_ent)
14211 + /* not initialized, so nothing to reset */
14212 + return 0;
14213 +
14214 + host_mmio = (struct sata_host_regs *)probe_ent->mmio_base;
14215 setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
14216 while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
14217 udelay(100);
14218
14219 - disable_sata_clock();
14220 -
14221 return 0;
14222 }
14223
14224 diff -ruN u-boot-2015.01-rc3/drivers/core/device.c u-boot/drivers/core/device.c
14225 --- u-boot-2015.01-rc3/drivers/core/device.c 2014-12-08 22:35:08.000000000 +0100
14226 +++ u-boot/drivers/core/device.c 2015-01-01 17:34:32.621497219 +0100
14227 @@ -234,7 +234,7 @@
14228 void *dev_get_platdata(struct udevice *dev)
14229 {
14230 if (!dev) {
14231 - dm_warn("%s: null device", __func__);
14232 + dm_warn("%s: null device\n", __func__);
14233 return NULL;
14234 }
14235
14236 @@ -244,7 +244,7 @@
14237 void *dev_get_priv(struct udevice *dev)
14238 {
14239 if (!dev) {
14240 - dm_warn("%s: null device", __func__);
14241 + dm_warn("%s: null device\n", __func__);
14242 return NULL;
14243 }
14244
14245 @@ -254,7 +254,7 @@
14246 void *dev_get_parentdata(struct udevice *dev)
14247 {
14248 if (!dev) {
14249 - dm_warn("%s: null device", __func__);
14250 + dm_warn("%s: null device\n", __func__);
14251 return NULL;
14252 }
14253
14254 diff -ruN u-boot-2015.01-rc3/drivers/crypto/fsl/jr.c u-boot/drivers/crypto/fsl/jr.c
14255 --- u-boot-2015.01-rc3/drivers/crypto/fsl/jr.c 2014-12-08 22:35:08.000000000 +0100
14256 +++ u-boot/drivers/crypto/fsl/jr.c 2015-01-01 17:34:32.621497219 +0100
14257 @@ -246,7 +246,7 @@
14258 struct result op;
14259 int ret = 0;
14260
14261 - memset(&op, sizeof(op), 0);
14262 + memset(&op, 0, sizeof(op));
14263
14264 ret = jr_enqueue(desc, desc_done, &op);
14265 if (ret) {
14266 diff -ruN u-boot-2015.01-rc3/drivers/ddr/fsl/arm_ddr_gen3.c u-boot/drivers/ddr/fsl/arm_ddr_gen3.c
14267 --- u-boot-2015.01-rc3/drivers/ddr/fsl/arm_ddr_gen3.c 2014-12-08 22:35:08.000000000 +0100
14268 +++ u-boot/drivers/ddr/fsl/arm_ddr_gen3.c 2015-01-01 17:34:32.621497219 +0100
14269 @@ -92,7 +92,6 @@
14270 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
14271 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
14272 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
14273 - ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
14274 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
14275 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
14276 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
14277 @@ -105,9 +104,6 @@
14278 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
14279 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
14280 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
14281 - ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
14282 - ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
14283 -
14284 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
14285 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
14286 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
14287 @@ -128,7 +124,24 @@
14288 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
14289 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
14290 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
14291 - ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
14292 +#ifdef CONFIG_DEEP_SLEEP
14293 + if (is_warm_boot()) {
14294 + ddr_out32(&ddr->sdram_cfg_2,
14295 + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
14296 + ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
14297 + ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
14298 +
14299 + /* DRAM VRef will not be trained */
14300 + ddr_out32(&ddr->ddr_cdr2,
14301 + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
14302 + } else
14303 +#endif
14304 + {
14305 + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
14306 + ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
14307 + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
14308 + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
14309 + }
14310 ddr_out32(&ddr->err_disable, regs->err_disable);
14311 ddr_out32(&ddr->err_int_en, regs->err_int_en);
14312 for (i = 0; i < 32; i++) {
14313 @@ -167,8 +180,20 @@
14314 udelay(500);
14315 asm volatile("dsb sy;isb");
14316
14317 +#ifdef CONFIG_DEEP_SLEEP
14318 + if (is_warm_boot()) {
14319 + /* enter self-refresh */
14320 + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
14321 + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
14322 + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
14323 + /* do board specific memory setup */
14324 + board_mem_sleep_setup();
14325 +
14326 + temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
14327 + } else
14328 +#endif
14329 + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
14330 /* Let the controller go */
14331 - temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
14332 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
14333 asm volatile("dsb sy;isb");
14334
14335 @@ -211,4 +236,12 @@
14336
14337 if (timeout <= 0)
14338 printf("Waiting for D_INIT timeout. Memory may not work.\n");
14339 +#ifdef CONFIG_DEEP_SLEEP
14340 + if (is_warm_boot()) {
14341 + /* exit self-refresh */
14342 + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
14343 + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
14344 + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
14345 + }
14346 +#endif
14347 }
14348 diff -ruN u-boot-2015.01-rc3/drivers/ddr/fsl/ctrl_regs.c u-boot/drivers/ddr/fsl/ctrl_regs.c
14349 --- u-boot-2015.01-rc3/drivers/ddr/fsl/ctrl_regs.c 2014-12-08 22:35:08.000000000 +0100
14350 +++ u-boot/drivers/ddr/fsl/ctrl_regs.c 2015-01-01 17:34:32.625497153 +0100
14351 @@ -324,6 +324,7 @@
14352 #elif defined(CONFIG_SYS_FSL_DDR3)
14353 unsigned int data_rate = get_ddr_freq(0);
14354 int txp;
14355 + unsigned int ip_rev;
14356 int odt_overlap;
14357 /*
14358 * (tXARD and tXARDS). Empirical?
14359 @@ -336,7 +337,25 @@
14360 */
14361 txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
14362
14363 - tmrd_mclk = 4;
14364 + ip_rev = fsl_ddr_get_version();
14365 + if (ip_rev >= 0x40700) {
14366 + /*
14367 + * MRS_CYC = max(tMRD, tMOD)
14368 + * tMRD = 4nCK (8nCK for RDIMM)
14369 + * tMOD = max(12nCK, 15ns)
14370 + */
14371 + tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000));
14372 + } else {
14373 + /*
14374 + * MRS_CYC = tMRD
14375 + * tMRD = 4nCK (8nCK for RDIMM)
14376 + */
14377 + if (popts->registered_dimm_en)
14378 + tmrd_mclk = 8;
14379 + else
14380 + tmrd_mclk = 4;
14381 + }
14382 +
14383 /* set the turnaround time */
14384
14385 /*
14386 diff -ruN u-boot-2015.01-rc3/drivers/ddr/fsl/fsl_ddr_gen4.c u-boot/drivers/ddr/fsl/fsl_ddr_gen4.c
14387 --- u-boot-2015.01-rc3/drivers/ddr/fsl/fsl_ddr_gen4.c 2014-12-08 22:35:08.000000000 +0100
14388 +++ u-boot/drivers/ddr/fsl/fsl_ddr_gen4.c 2015-01-01 17:34:32.625497153 +0100
14389 @@ -103,7 +103,6 @@
14390 ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
14391 ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
14392 ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
14393 - ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
14394 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
14395 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
14396 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
14397 @@ -124,8 +123,6 @@
14398 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
14399 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
14400 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
14401 - ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
14402 - ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
14403 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
14404 #ifndef CONFIG_SYS_FSL_DDR_EMU
14405 /*
14406 @@ -147,7 +144,24 @@
14407 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
14408 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
14409 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
14410 - ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
14411 +#ifdef CONFIG_DEEP_SLEEP
14412 + if (is_warm_boot()) {
14413 + ddr_out32(&ddr->sdram_cfg_2,
14414 + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
14415 + ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
14416 + ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
14417 +
14418 + /* DRAM VRef will not be trained */
14419 + ddr_out32(&ddr->ddr_cdr2,
14420 + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
14421 + } else
14422 +#endif
14423 + {
14424 + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
14425 + ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
14426 + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
14427 + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
14428 + }
14429 ddr_out32(&ddr->err_disable, regs->err_disable);
14430 ddr_out32(&ddr->err_int_en, regs->err_int_en);
14431 for (i = 0; i < 32; i++) {
14432 @@ -187,8 +201,20 @@
14433 mb();
14434 isb();
14435
14436 +#ifdef CONFIG_DEEP_SLEEP
14437 + if (is_warm_boot()) {
14438 + /* enter self-refresh */
14439 + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
14440 + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
14441 + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
14442 + /* do board specific memory setup */
14443 + board_mem_sleep_setup();
14444 +
14445 + temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
14446 + } else
14447 +#endif
14448 + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
14449 /* Let the controller go */
14450 - temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
14451 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
14452 mb();
14453 isb();
14454 @@ -233,4 +259,12 @@
14455
14456 if (timeout <= 0)
14457 printf("Waiting for D_INIT timeout. Memory may not work.\n");
14458 +#ifdef CONFIG_DEEP_SLEEP
14459 + if (is_warm_boot()) {
14460 + /* exit self-refresh */
14461 + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
14462 + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
14463 + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
14464 + }
14465 +#endif
14466 }
14467 diff -ruN u-boot-2015.01-rc3/drivers/ddr/fsl/mpc85xx_ddr_gen3.c u-boot/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
14468 --- u-boot-2015.01-rc3/drivers/ddr/fsl/mpc85xx_ddr_gen3.c 2014-12-08 22:35:08.000000000 +0100
14469 +++ u-boot/drivers/ddr/fsl/mpc85xx_ddr_gen3.c 2015-01-01 17:34:32.625497153 +0100
14470 @@ -15,8 +15,6 @@
14471 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
14472 #endif
14473
14474 -DECLARE_GLOBAL_DATA_PTR;
14475 -
14476 /*
14477 * regs has the to-be-set values for DDR controller registers
14478 * ctrl_num is the DDR controller number
14479 @@ -44,16 +42,6 @@
14480 u32 save1, save2;
14481 #endif
14482
14483 -#ifdef CONFIG_DEEP_SLEEP
14484 - const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
14485 - bool sleep_flag = 0;
14486 -#endif
14487 -
14488 -#ifdef CONFIG_DEEP_SLEEP
14489 - if (in_be32(&gur->scrtsr[0]) & (1 << 3))
14490 - sleep_flag = 1;
14491 -#endif
14492 -
14493 switch (ctrl_num) {
14494 case 0:
14495 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
14496 @@ -130,13 +118,6 @@
14497 out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
14498 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
14499 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
14500 -#ifdef CONFIG_DEEP_SLEEP
14501 - if (sleep_flag)
14502 - out_be32(&ddr->sdram_cfg_2,
14503 - regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
14504 - else
14505 -#endif
14506 - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
14507 out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
14508 out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
14509 out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
14510 @@ -149,17 +130,6 @@
14511 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
14512 out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
14513 out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
14514 -#ifdef CONFIG_DEEP_SLEEP
14515 - if (sleep_flag) {
14516 - out_be32(&ddr->init_addr, 0);
14517 - out_be32(&ddr->init_ext_addr, (1 << 31));
14518 - } else
14519 -#endif
14520 - {
14521 - out_be32(&ddr->init_addr, regs->ddr_init_addr);
14522 - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
14523 - }
14524 -
14525 out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
14526 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
14527 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
14528 @@ -180,7 +150,24 @@
14529 out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
14530 out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
14531 out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
14532 - out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
14533 +#ifdef CONFIG_DEEP_SLEEP
14534 + if (is_warm_boot()) {
14535 + out_be32(&ddr->sdram_cfg_2,
14536 + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
14537 + out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
14538 + out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
14539 +
14540 + /* DRAM VRef will not be trained */
14541 + out_be32(&ddr->ddr_cdr2,
14542 + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
14543 + } else
14544 +#endif
14545 + {
14546 + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
14547 + out_be32(&ddr->init_addr, regs->ddr_init_addr);
14548 + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
14549 + out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
14550 + }
14551 out_be32(&ddr->err_disable, regs->err_disable);
14552 out_be32(&ddr->err_int_en, regs->err_int_en);
14553 for (i = 0; i < 32; i++) {
14554 @@ -400,21 +387,17 @@
14555 asm volatile("sync;isync");
14556
14557 #ifdef CONFIG_DEEP_SLEEP
14558 - if (sleep_flag) {
14559 + if (is_warm_boot()) {
14560 /* enter self-refresh */
14561 - setbits_be32(&ddr->sdram_cfg_2, (1 << 31));
14562 + setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
14563 /* do board specific memory setup */
14564 board_mem_sleep_setup();
14565 - }
14566 -#endif
14567 -
14568 - /* Let the controller go */
14569 -#ifdef CONFIG_DEEP_SLEEP
14570 - if (sleep_flag)
14571 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
14572 - else
14573 + } else
14574 #endif
14575 temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
14576 +
14577 + /* Let the controller go */
14578 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
14579 asm volatile("sync;isync");
14580
14581 @@ -566,8 +549,8 @@
14582 }
14583 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
14584 #ifdef CONFIG_DEEP_SLEEP
14585 - if (sleep_flag)
14586 + if (is_warm_boot())
14587 /* exit self-refresh */
14588 - clrbits_be32(&ddr->sdram_cfg_2, (1 << 31));
14589 + clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
14590 #endif
14591 }
14592 diff -ruN u-boot-2015.01-rc3/drivers/dfu/dfu.c u-boot/drivers/dfu/dfu.c
14593 --- u-boot-2015.01-rc3/drivers/dfu/dfu.c 2014-12-08 22:35:08.000000000 +0100
14594 +++ u-boot/drivers/dfu/dfu.c 2015-01-01 17:34:32.629497087 +0100
14595 @@ -17,7 +17,6 @@
14596 #include <linux/list.h>
14597 #include <linux/compiler.h>
14598
14599 -static bool dfu_detach_request;
14600 static LIST_HEAD(dfu_list);
14601 static int dfu_alt_num;
14602 static int alt_num_cnt;
14603 @@ -39,21 +38,6 @@
14604 return true;
14605 }
14606
14607 -bool dfu_detach(void)
14608 -{
14609 - return dfu_detach_request;
14610 -}
14611 -
14612 -void dfu_trigger_detach(void)
14613 -{
14614 - dfu_detach_request = true;
14615 -}
14616 -
14617 -void dfu_clear_detach(void)
14618 -{
14619 - dfu_detach_request = false;
14620 -}
14621 -
14622 static int dfu_find_alt_num(const char *s)
14623 {
14624 int i = 0;
14625 @@ -111,8 +95,12 @@
14626 return dfu_buf;
14627
14628 s = getenv("dfu_bufsiz");
14629 - dfu_buf_size = s ? (unsigned long)simple_strtol(s, NULL, 16) :
14630 - CONFIG_SYS_DFU_DATA_BUF_SIZE;
14631 + if (s)
14632 + dfu_buf_size = (unsigned long)simple_strtol(s, NULL, 0);
14633 +
14634 + if (!s || !dfu_buf_size)
14635 + dfu_buf_size = CONFIG_SYS_DFU_DATA_BUF_SIZE;
14636 +
14637 if (dfu->max_buf_size && dfu_buf_size > dfu->max_buf_size)
14638 dfu_buf_size = dfu->max_buf_size;
14639
14640 @@ -544,10 +532,35 @@
14641 int dfu_get_alt(char *name)
14642 {
14643 struct dfu_entity *dfu;
14644 + char *str;
14645
14646 list_for_each_entry(dfu, &dfu_list, list) {
14647 - if (!strncmp(dfu->name, name, strlen(dfu->name)))
14648 - return dfu->alt;
14649 + if (dfu->name[0] != '/') {
14650 + if (!strncmp(dfu->name, name, strlen(dfu->name)))
14651 + return dfu->alt;
14652 + } else {
14653 + /*
14654 + * One must also consider absolute path
14655 + * (/boot/bin/uImage) available at dfu->name when
14656 + * compared "plain" file name (uImage)
14657 + *
14658 + * It is the case for e.g. thor gadget where lthor SW
14659 + * sends only the file name, so only the very last part
14660 + * of path must be checked for equality
14661 + */
14662 +
14663 + str = strstr(dfu->name, name);
14664 + if (!str)
14665 + continue;
14666 +
14667 + /*
14668 + * Check if matching substring is the last element of
14669 + * dfu->name (uImage)
14670 + */
14671 + if (strlen(dfu->name) ==
14672 + ((str - dfu->name) + strlen(name)))
14673 + return dfu->alt;
14674 + }
14675 }
14676
14677 return -ENODEV;
14678 diff -ruN u-boot-2015.01-rc3/drivers/dfu/dfu_mmc.c u-boot/drivers/dfu/dfu_mmc.c
14679 --- u-boot-2015.01-rc3/drivers/dfu/dfu_mmc.c 2014-12-08 22:35:08.000000000 +0100
14680 +++ u-boot/drivers/dfu/dfu_mmc.c 2015-01-01 17:34:32.629497087 +0100
14681 @@ -40,10 +40,16 @@
14682 static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu,
14683 u64 offset, void *buf, long *len)
14684 {
14685 - struct mmc *mmc = find_mmc_device(dfu->data.mmc.dev_num);
14686 + struct mmc *mmc;
14687 u32 blk_start, blk_count, n = 0;
14688 int ret, part_num_bkp = 0;
14689
14690 + mmc = find_mmc_device(dfu->data.mmc.dev_num);
14691 + if (!mmc) {
14692 + error("Device MMC %d - not found!", dfu->data.mmc.dev_num);
14693 + return -ENODEV;
14694 + }
14695 +
14696 /*
14697 * We must ensure that we work in lba_blk_size chunks, so ALIGN
14698 * this value.
14699 diff -ruN u-boot-2015.01-rc3/drivers/gpio/intel_ich6_gpio.c u-boot/drivers/gpio/intel_ich6_gpio.c
14700 --- u-boot-2015.01-rc3/drivers/gpio/intel_ich6_gpio.c 2014-12-08 22:35:08.000000000 +0100
14701 +++ u-boot/drivers/gpio/intel_ich6_gpio.c 2015-01-01 17:34:32.637496957 +0100
14702 @@ -34,69 +34,21 @@
14703 #include <asm/gpio.h>
14704 #include <asm/io.h>
14705 #include <asm/pci.h>
14706 -#ifdef CONFIG_X86_RESET_VECTOR
14707 -#include <asm/arch/pch.h>
14708 -#define SUPPORT_GPIO_SETUP
14709 -#endif
14710
14711 #define GPIO_PER_BANK 32
14712
14713 -/* Where in config space is the register that points to the GPIO registers? */
14714 -#define PCI_CFG_GPIOBASE 0x48
14715 -
14716 struct ich6_bank_priv {
14717 /* These are I/O addresses */
14718 - uint32_t use_sel;
14719 - uint32_t io_sel;
14720 - uint32_t lvl;
14721 + uint16_t use_sel;
14722 + uint16_t io_sel;
14723 + uint16_t lvl;
14724 };
14725
14726 -#ifdef SUPPORT_GPIO_SETUP
14727 -static void setup_pch_gpios(const struct pch_gpio_map *gpio)
14728 -{
14729 - u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
14730 -
14731 - /* GPIO Set 1 */
14732 - if (gpio->set1.level)
14733 - outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
14734 - if (gpio->set1.mode)
14735 - outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
14736 - if (gpio->set1.direction)
14737 - outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
14738 - if (gpio->set1.reset)
14739 - outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
14740 - if (gpio->set1.invert)
14741 - outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
14742 - if (gpio->set1.blink)
14743 - outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
14744 -
14745 - /* GPIO Set 2 */
14746 - if (gpio->set2.level)
14747 - outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
14748 - if (gpio->set2.mode)
14749 - outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
14750 - if (gpio->set2.direction)
14751 - outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
14752 - if (gpio->set2.reset)
14753 - outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
14754 -
14755 - /* GPIO Set 3 */
14756 - if (gpio->set3.level)
14757 - outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
14758 - if (gpio->set3.mode)
14759 - outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
14760 - if (gpio->set3.direction)
14761 - outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
14762 - if (gpio->set3.reset)
14763 - outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
14764 -}
14765 -
14766 /* TODO: Move this to device tree, or platform data */
14767 void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
14768 {
14769 gd->arch.gpio_map = map;
14770 }
14771 -#endif /* SUPPORT_GPIO_SETUP */
14772
14773 static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
14774 {
14775 @@ -105,7 +57,7 @@
14776 u8 tmpbyte;
14777 u16 tmpword;
14778 u32 tmplong;
14779 - u32 gpiobase;
14780 + u16 gpiobase;
14781 int offset;
14782
14783 /* Where should it be? */
14784 @@ -164,11 +116,15 @@
14785 /*
14786 * GPIOBASE moved to its current offset with ICH6, but prior to
14787 * that it was unused (or undocumented). Check that it looks
14788 - * okay: not all ones or zeros, and mapped to I/O space (bit 0).
14789 + * okay: not all ones or zeros.
14790 + *
14791 + * Note we don't need check bit0 here, because the Tunnel Creek
14792 + * GPIO base address register bit0 is reserved (read returns 0),
14793 + * while on the Ivybridge the bit0 is used to indicate it is an
14794 + * I/O space.
14795 */
14796 tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE);
14797 - if (tmplong == 0x00000000 || tmplong == 0xffffffff ||
14798 - !(tmplong & 0x00000001)) {
14799 + if (tmplong == 0x00000000 || tmplong == 0xffffffff) {
14800 debug("%s: unexpected GPIOBASE value\n", __func__);
14801 return -ENODEV;
14802 }
14803 @@ -179,7 +135,7 @@
14804 * at the offset that we just read. Bit 0 indicates that it's
14805 * an I/O address, not a memory address, so mask that off.
14806 */
14807 - gpiobase = tmplong & 0xfffffffe;
14808 + gpiobase = tmplong & 0xfffe;
14809 offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1);
14810 if (offset == -1) {
14811 debug("%s: Invalid register offset %d\n", __func__, offset);
14812 @@ -198,12 +154,11 @@
14813 struct gpio_dev_priv *uc_priv = dev->uclass_priv;
14814 struct ich6_bank_priv *bank = dev_get_priv(dev);
14815
14816 -#ifdef SUPPORT_GPIO_SETUP
14817 if (gd->arch.gpio_map) {
14818 - setup_pch_gpios(gd->arch.gpio_map);
14819 + setup_pch_gpios(plat->base_addr, gd->arch.gpio_map);
14820 gd->arch.gpio_map = NULL;
14821 }
14822 -#endif
14823 +
14824 uc_priv->gpio_count = GPIO_PER_BANK;
14825 uc_priv->bank_name = plat->bank_name;
14826 bank->use_sel = plat->base_addr;
14827 @@ -251,6 +206,8 @@
14828 struct ich6_bank_priv *bank = dev_get_priv(dev);
14829 u32 tmplong;
14830
14831 + gpio_set_value(offset, value);
14832 +
14833 tmplong = inl(bank->io_sel);
14834 tmplong &= ~(1UL << offset);
14835 outl(bank->io_sel, tmplong);
14836 diff -ruN u-boot-2015.01-rc3/drivers/i2c/i2c-emul-uclass.c u-boot/drivers/i2c/i2c-emul-uclass.c
14837 --- u-boot-2015.01-rc3/drivers/i2c/i2c-emul-uclass.c 1970-01-01 01:00:00.000000000 +0100
14838 +++ u-boot/drivers/i2c/i2c-emul-uclass.c 2015-01-01 17:34:32.645496825 +0100
14839 @@ -0,0 +1,14 @@
14840 +/*
14841 + * Copyright (c) 2014 Google, Inc
14842 + *
14843 + * SPDX-License-Identifier: GPL-2.0+
14844 + */
14845 +
14846 +#include <common.h>
14847 +#include <dm.h>
14848 +#include <i2c.h>
14849 +
14850 +UCLASS_DRIVER(i2c_emul) = {
14851 + .id = UCLASS_I2C_EMUL,
14852 + .name = "i2c_emul",
14853 +};
14854 diff -ruN u-boot-2015.01-rc3/drivers/i2c/i2c-uclass.c u-boot/drivers/i2c/i2c-uclass.c
14855 --- u-boot-2015.01-rc3/drivers/i2c/i2c-uclass.c 1970-01-01 01:00:00.000000000 +0100
14856 +++ u-boot/drivers/i2c/i2c-uclass.c 2015-01-01 17:34:32.645496825 +0100
14857 @@ -0,0 +1,466 @@
14858 +/*
14859 + * Copyright (c) 2014 Google, Inc
14860 + *
14861 + * SPDX-License-Identifier: GPL-2.0+
14862 + */
14863 +
14864 +#include <common.h>
14865 +#include <dm.h>
14866 +#include <errno.h>
14867 +#include <fdtdec.h>
14868 +#include <i2c.h>
14869 +#include <malloc.h>
14870 +#include <dm/device-internal.h>
14871 +#include <dm/lists.h>
14872 +#include <dm/root.h>
14873 +
14874 +DECLARE_GLOBAL_DATA_PTR;
14875 +
14876 +#define I2C_MAX_OFFSET_LEN 4
14877 +
14878 +/**
14879 + * i2c_setup_offset() - Set up a new message with a chip offset
14880 + *
14881 + * @chip: Chip to use
14882 + * @offset: Byte offset within chip
14883 + * @offset_buf: Place to put byte offset
14884 + * @msg: Message buffer
14885 + * @return 0 if OK, -EADDRNOTAVAIL if the offset length is 0. In that case the
14886 + * message is still set up but will not contain an offset.
14887 + */
14888 +static int i2c_setup_offset(struct dm_i2c_chip *chip, uint offset,
14889 + uint8_t offset_buf[], struct i2c_msg *msg)
14890 +{
14891 + int offset_len;
14892 +
14893 + msg->addr = chip->chip_addr;
14894 + msg->flags = chip->flags & DM_I2C_CHIP_10BIT ? I2C_M_TEN : 0;
14895 + msg->len = chip->offset_len;
14896 + msg->buf = offset_buf;
14897 + if (!chip->offset_len)
14898 + return -EADDRNOTAVAIL;
14899 + assert(chip->offset_len <= I2C_MAX_OFFSET_LEN);
14900 + offset_len = chip->offset_len;
14901 + while (offset_len--)
14902 + *offset_buf++ = offset >> (8 * offset_len);
14903 +
14904 + return 0;
14905 +}
14906 +
14907 +static int i2c_read_bytewise(struct udevice *dev, uint offset,
14908 + uint8_t *buffer, int len)
14909 +{
14910 + struct dm_i2c_chip *chip = dev_get_parentdata(dev);
14911 + struct udevice *bus = dev_get_parent(dev);
14912 + struct dm_i2c_ops *ops = i2c_get_ops(bus);
14913 + struct i2c_msg msg[2], *ptr;
14914 + uint8_t offset_buf[I2C_MAX_OFFSET_LEN];
14915 + int ret;
14916 + int i;
14917 +
14918 + for (i = 0; i < len; i++) {
14919 + if (i2c_setup_offset(chip, offset + i, offset_buf, msg))
14920 + return -EINVAL;
14921 + ptr = msg + 1;
14922 + ptr->addr = chip->chip_addr;
14923 + ptr->flags = msg->flags | I2C_M_RD;
14924 + ptr->len = 1;
14925 + ptr->buf = &buffer[i];
14926 + ptr++;
14927 +
14928 + ret = ops->xfer(bus, msg, ptr - msg);
14929 + if (ret)
14930 + return ret;
14931 + }
14932 +
14933 + return 0;
14934 +}
14935 +
14936 +static int i2c_write_bytewise(struct udevice *dev, uint offset,
14937 + const uint8_t *buffer, int len)
14938 +{
14939 + struct dm_i2c_chip *chip = dev_get_parentdata(dev);
14940 + struct udevice *bus = dev_get_parent(dev);
14941 + struct dm_i2c_ops *ops = i2c_get_ops(bus);
14942 + struct i2c_msg msg[1];
14943 + uint8_t buf[I2C_MAX_OFFSET_LEN + 1];
14944 + int ret;
14945 + int i;
14946 +
14947 + for (i = 0; i < len; i++) {
14948 + if (i2c_setup_offset(chip, offset + i, buf, msg))
14949 + return -EINVAL;
14950 + buf[msg->len++] = buffer[i];
14951 +
14952 + ret = ops->xfer(bus, msg, 1);
14953 + if (ret)
14954 + return ret;
14955 + }
14956 +
14957 + return 0;
14958 +}
14959 +
14960 +int i2c_read(struct udevice *dev, uint offset, uint8_t *buffer, int len)
14961 +{
14962 + struct dm_i2c_chip *chip = dev_get_parentdata(dev);
14963 + struct udevice *bus = dev_get_parent(dev);
14964 + struct dm_i2c_ops *ops = i2c_get_ops(bus);
14965 + struct i2c_msg msg[2], *ptr;
14966 + uint8_t offset_buf[I2C_MAX_OFFSET_LEN];
14967 + int msg_count;
14968 +
14969 + if (!ops->xfer)
14970 + return -ENOSYS;
14971 + if (chip->flags & DM_I2C_CHIP_RD_ADDRESS)
14972 + return i2c_read_bytewise(dev, offset, buffer, len);
14973 + ptr = msg;
14974 + if (!i2c_setup_offset(chip, offset, offset_buf, ptr))
14975 + ptr++;
14976 +
14977 + if (len) {
14978 + ptr->addr = chip->chip_addr;
14979 + ptr->flags = chip->flags & DM_I2C_CHIP_10BIT ? I2C_M_TEN : 0;
14980 + ptr->flags |= I2C_M_RD;
14981 + ptr->len = len;
14982 + ptr->buf = buffer;
14983 + ptr++;
14984 + }
14985 + msg_count = ptr - msg;
14986 +
14987 + return ops->xfer(bus, msg, msg_count);
14988 +}
14989 +
14990 +int i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer, int len)
14991 +{
14992 + struct dm_i2c_chip *chip = dev_get_parentdata(dev);
14993 + struct udevice *bus = dev_get_parent(dev);
14994 + struct dm_i2c_ops *ops = i2c_get_ops(bus);
14995 + struct i2c_msg msg[1];
14996 +
14997 + if (!ops->xfer)
14998 + return -ENOSYS;
14999 +
15000 + if (chip->flags & DM_I2C_CHIP_WR_ADDRESS)
15001 + return i2c_write_bytewise(dev, offset, buffer, len);
15002 + /*
15003 + * The simple approach would be to send two messages here: one to
15004 + * set the offset and one to write the bytes. However some drivers
15005 + * will not be expecting this, and some chips won't like how the
15006 + * driver presents this on the I2C bus.
15007 + *
15008 + * The API does not support separate offset and data. We could extend
15009 + * it with a flag indicating that there is data in the next message
15010 + * that needs to be processed in the same transaction. We could
15011 + * instead add an additional buffer to each message. For now, handle
15012 + * this in the uclass since it isn't clear what the impact on drivers
15013 + * would be with this extra complication. Unfortunately this means
15014 + * copying the message.
15015 + *
15016 + * Use the stack for small messages, malloc() for larger ones. We
15017 + * need to allow space for the offset (up to 4 bytes) and the message
15018 + * itself.
15019 + */
15020 + if (len < 64) {
15021 + uint8_t buf[I2C_MAX_OFFSET_LEN + len];
15022 +
15023 + i2c_setup_offset(chip, offset, buf, msg);
15024 + msg->len += len;
15025 + memcpy(buf + chip->offset_len, buffer, len);
15026 +
15027 + return ops->xfer(bus, msg, 1);
15028 + } else {
15029 + uint8_t *buf;
15030 + int ret;
15031 +
15032 + buf = malloc(I2C_MAX_OFFSET_LEN + len);
15033 + if (!buf)
15034 + return -ENOMEM;
15035 + i2c_setup_offset(chip, offset, buf, msg);
15036 + msg->len += len;
15037 + memcpy(buf + chip->offset_len, buffer, len);
15038 +
15039 + ret = ops->xfer(bus, msg, 1);
15040 + free(buf);
15041 + return ret;
15042 + }
15043 +}
15044 +
15045 +/**
15046 + * i2c_probe_chip() - probe for a chip on a bus
15047 + *
15048 + * @bus: Bus to probe
15049 + * @chip_addr: Chip address to probe
15050 + * @flags: Flags for the chip
15051 + * @return 0 if found, -ENOSYS if the driver is invalid, -EREMOTEIO if the chip
15052 + * does not respond to probe
15053 + */
15054 +static int i2c_probe_chip(struct udevice *bus, uint chip_addr,
15055 + enum dm_i2c_chip_flags chip_flags)
15056 +{
15057 + struct dm_i2c_ops *ops = i2c_get_ops(bus);
15058 + struct i2c_msg msg[1];
15059 + int ret;
15060 +
15061 + if (ops->probe_chip) {
15062 + ret = ops->probe_chip(bus, chip_addr, chip_flags);
15063 + if (!ret || ret != -ENOSYS)
15064 + return ret;
15065 + }
15066 +
15067 + if (!ops->xfer)
15068 + return -ENOSYS;
15069 +
15070 + /* Probe with a zero-length message */
15071 + msg->addr = chip_addr;
15072 + msg->flags = chip_flags & DM_I2C_CHIP_10BIT ? I2C_M_TEN : 0;
15073 + msg->len = 0;
15074 + msg->buf = NULL;
15075 +
15076 + return ops->xfer(bus, msg, 1);
15077 +}
15078 +
15079 +static int i2c_bind_driver(struct udevice *bus, uint chip_addr,
15080 + struct udevice **devp)
15081 +{
15082 + struct dm_i2c_chip chip;
15083 + char name[30], *str;
15084 + struct udevice *dev;
15085 + int ret;
15086 +
15087 + snprintf(name, sizeof(name), "generic_%x", chip_addr);
15088 + str = strdup(name);
15089 + ret = device_bind_driver(bus, "i2c_generic_chip_drv", str, &dev);
15090 + debug("%s: device_bind_driver: ret=%d\n", __func__, ret);
15091 + if (ret)
15092 + goto err_bind;
15093 +
15094 + /* Tell the device what we know about it */
15095 + memset(&chip, '\0', sizeof(chip));
15096 + chip.chip_addr = chip_addr;
15097 + chip.offset_len = 1; /* we assume */
15098 + ret = device_probe_child(dev, &chip);
15099 + debug("%s: device_probe_child: ret=%d\n", __func__, ret);
15100 + if (ret)
15101 + goto err_probe;
15102 +
15103 + *devp = dev;
15104 + return 0;
15105 +
15106 +err_probe:
15107 + device_unbind(dev);
15108 +err_bind:
15109 + free(str);
15110 + return ret;
15111 +}
15112 +
15113 +int i2c_get_chip(struct udevice *bus, uint chip_addr, struct udevice **devp)
15114 +{
15115 + struct udevice *dev;
15116 +
15117 + debug("%s: Searching bus '%s' for address %02x: ", __func__,
15118 + bus->name, chip_addr);
15119 + for (device_find_first_child(bus, &dev); dev;
15120 + device_find_next_child(&dev)) {
15121 + struct dm_i2c_chip store;
15122 + struct dm_i2c_chip *chip = dev_get_parentdata(dev);
15123 + int ret;
15124 +
15125 + if (!chip) {
15126 + chip = &store;
15127 + i2c_chip_ofdata_to_platdata(gd->fdt_blob,
15128 + dev->of_offset, chip);
15129 + }
15130 + if (chip->chip_addr == chip_addr) {
15131 + ret = device_probe(dev);
15132 + debug("found, ret=%d\n", ret);
15133 + if (ret)
15134 + return ret;
15135 + *devp = dev;
15136 + return 0;
15137 + }
15138 + }
15139 + debug("not found\n");
15140 + return i2c_bind_driver(bus, chip_addr, devp);
15141 +}
15142 +
15143 +int i2c_get_chip_for_busnum(int busnum, int chip_addr, struct udevice **devp)
15144 +{
15145 + struct udevice *bus;
15146 + int ret;
15147 +
15148 + ret = uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus);
15149 + if (ret) {
15150 + debug("Cannot find I2C bus %d\n", busnum);
15151 + return ret;
15152 + }
15153 + ret = i2c_get_chip(bus, chip_addr, devp);
15154 + if (ret) {
15155 + debug("Cannot find I2C chip %02x on bus %d\n", chip_addr,
15156 + busnum);
15157 + return ret;
15158 + }
15159 +
15160 + return 0;
15161 +}
15162 +
15163 +int i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags,
15164 + struct udevice **devp)
15165 +{
15166 + int ret;
15167 +
15168 + *devp = NULL;
15169 +
15170 + /* First probe that chip */
15171 + ret = i2c_probe_chip(bus, chip_addr, chip_flags);
15172 + debug("%s: bus='%s', address %02x, ret=%d\n", __func__, bus->name,
15173 + chip_addr, ret);
15174 + if (ret)
15175 + return ret;
15176 +
15177 + /* The chip was found, see if we have a driver, and probe it */
15178 + ret = i2c_get_chip(bus, chip_addr, devp);
15179 + debug("%s: i2c_get_chip: ret=%d\n", __func__, ret);
15180 +
15181 + return ret;
15182 +}
15183 +
15184 +int i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
15185 +{
15186 + struct dm_i2c_ops *ops = i2c_get_ops(bus);
15187 + struct dm_i2c_bus *i2c = bus->uclass_priv;
15188 + int ret;
15189 +
15190 + /*
15191 + * If we have a method, call it. If not then the driver probably wants
15192 + * to deal with speed changes on the next transfer. It can easily read
15193 + * the current speed from this uclass
15194 + */
15195 + if (ops->set_bus_speed) {
15196 + ret = ops->set_bus_speed(bus, speed);
15197 + if (ret)
15198 + return ret;
15199 + }
15200 + i2c->speed_hz = speed;
15201 +
15202 + return 0;
15203 +}
15204 +
15205 +/*
15206 + * i2c_get_bus_speed:
15207 + *
15208 + * Returns speed of selected I2C bus in Hz
15209 + */
15210 +int i2c_get_bus_speed(struct udevice *bus)
15211 +{
15212 + struct dm_i2c_ops *ops = i2c_get_ops(bus);
15213 + struct dm_i2c_bus *i2c = bus->uclass_priv;
15214 +
15215 + if (!ops->get_bus_speed)
15216 + return i2c->speed_hz;
15217 +
15218 + return ops->get_bus_speed(bus);
15219 +}
15220 +
15221 +int i2c_set_chip_flags(struct udevice *dev, uint flags)
15222 +{
15223 + struct udevice *bus = dev->parent;
15224 + struct dm_i2c_chip *chip = dev_get_parentdata(dev);
15225 + struct dm_i2c_ops *ops = i2c_get_ops(bus);
15226 + int ret;
15227 +
15228 + if (ops->set_flags) {
15229 + ret = ops->set_flags(dev, flags);
15230 + if (ret)
15231 + return ret;
15232 + }
15233 + chip->flags = flags;
15234 +
15235 + return 0;
15236 +}
15237 +
15238 +int i2c_get_chip_flags(struct udevice *dev, uint *flagsp)
15239 +{
15240 + struct dm_i2c_chip *chip = dev_get_parentdata(dev);
15241 +
15242 + *flagsp = chip->flags;
15243 +
15244 + return 0;
15245 +}
15246 +
15247 +int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len)
15248 +{
15249 + struct dm_i2c_chip *chip = dev_get_parentdata(dev);
15250 +
15251 + if (offset_len > I2C_MAX_OFFSET_LEN)
15252 + return -EINVAL;
15253 + chip->offset_len = offset_len;
15254 +
15255 + return 0;
15256 +}
15257 +
15258 +int i2c_deblock(struct udevice *bus)
15259 +{
15260 + struct dm_i2c_ops *ops = i2c_get_ops(bus);
15261 +
15262 + /*
15263 + * We could implement a software deblocking here if we could get
15264 + * access to the GPIOs used by I2C, and switch them to GPIO mode
15265 + * and then back to I2C. This is somewhat beyond our powers in
15266 + * driver model at present, so for now just fail.
15267 + *
15268 + * See https://patchwork.ozlabs.org/patch/399040/
15269 + */
15270 + if (!ops->deblock)
15271 + return -ENOSYS;
15272 +
15273 + return ops->deblock(bus);
15274 +}
15275 +
15276 +int i2c_chip_ofdata_to_platdata(const void *blob, int node,
15277 + struct dm_i2c_chip *chip)
15278 +{
15279 + chip->offset_len = 1; /* default */
15280 + chip->flags = 0;
15281 + chip->chip_addr = fdtdec_get_int(gd->fdt_blob, node, "reg", -1);
15282 + if (chip->chip_addr == -1) {
15283 + debug("%s: I2C Node '%s' has no 'reg' property\n", __func__,
15284 + fdt_get_name(blob, node, NULL));
15285 + return -EINVAL;
15286 + }
15287 +
15288 + return 0;
15289 +}
15290 +
15291 +static int i2c_post_probe(struct udevice *dev)
15292 +{
15293 + struct dm_i2c_bus *i2c = dev->uclass_priv;
15294 +
15295 + i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
15296 + "clock-frequency", 100000);
15297 +
15298 + return i2c_set_bus_speed(dev, i2c->speed_hz);
15299 +}
15300 +
15301 +int i2c_post_bind(struct udevice *dev)
15302 +{
15303 + /* Scan the bus for devices */
15304 + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
15305 +}
15306 +
15307 +UCLASS_DRIVER(i2c) = {
15308 + .id = UCLASS_I2C,
15309 + .name = "i2c",
15310 + .per_device_auto_alloc_size = sizeof(struct dm_i2c_bus),
15311 + .post_bind = i2c_post_bind,
15312 + .post_probe = i2c_post_probe,
15313 +};
15314 +
15315 +UCLASS_DRIVER(i2c_generic) = {
15316 + .id = UCLASS_I2C_GENERIC,
15317 + .name = "i2c_generic",
15318 +};
15319 +
15320 +U_BOOT_DRIVER(i2c_generic_chip_drv) = {
15321 + .name = "i2c_generic_chip_drv",
15322 + .id = UCLASS_I2C_GENERIC,
15323 +};
15324 diff -ruN u-boot-2015.01-rc3/drivers/i2c/Makefile u-boot/drivers/i2c/Makefile
15325 --- u-boot-2015.01-rc3/drivers/i2c/Makefile 2014-12-08 22:35:08.000000000 +0100
15326 +++ u-boot/drivers/i2c/Makefile 2015-01-01 17:34:32.641496891 +0100
15327 @@ -4,6 +4,7 @@
15328 #
15329 # SPDX-License-Identifier: GPL-2.0+
15330 #
15331 +obj-$(CONFIG_DM_I2C) += i2c-uclass.o
15332
15333 obj-$(CONFIG_SYS_I2C_ADI) += adi_i2c.o
15334 obj-$(CONFIG_I2C_MV) += mv_i2c.o
15335 @@ -26,6 +27,7 @@
15336 obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
15337 obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
15338 obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
15339 +obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
15340 obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
15341 obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
15342 obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
15343 diff -ruN u-boot-2015.01-rc3/drivers/i2c/sandbox_i2c.c u-boot/drivers/i2c/sandbox_i2c.c
15344 --- u-boot-2015.01-rc3/drivers/i2c/sandbox_i2c.c 1970-01-01 01:00:00.000000000 +0100
15345 +++ u-boot/drivers/i2c/sandbox_i2c.c 2015-01-01 17:34:32.649496760 +0100
15346 @@ -0,0 +1,111 @@
15347 +/*
15348 + * Simulate an I2C port
15349 + *
15350 + * Copyright (c) 2014 Google, Inc
15351 + *
15352 + * SPDX-License-Identifier: GPL-2.0+
15353 + */
15354 +
15355 +#include <common.h>
15356 +#include <dm.h>
15357 +#include <errno.h>
15358 +#include <fdtdec.h>
15359 +#include <i2c.h>
15360 +#include <asm/test.h>
15361 +#include <dm/lists.h>
15362 +#include <dm/device-internal.h>
15363 +#include <dm/root.h>
15364 +
15365 +DECLARE_GLOBAL_DATA_PTR;
15366 +
15367 +struct dm_sandbox_i2c_emul_priv {
15368 + struct udevice *emul;
15369 +};
15370 +
15371 +static int get_emul(struct udevice *dev, struct udevice **devp,
15372 + struct dm_i2c_ops **opsp)
15373 +{
15374 + struct dm_i2c_chip *priv;
15375 + int ret;
15376 +
15377 + *devp = NULL;
15378 + *opsp = NULL;
15379 + priv = dev_get_parentdata(dev);
15380 + if (!priv->emul) {
15381 + ret = dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset,
15382 + false);
15383 + if (ret)
15384 + return ret;
15385 +
15386 + ret = device_get_child(dev, 0, &priv->emul);
15387 + if (ret)
15388 + return ret;
15389 + }
15390 + *devp = priv->emul;
15391 + *opsp = i2c_get_ops(priv->emul);
15392 +
15393 + return 0;
15394 +}
15395 +
15396 +static int sandbox_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
15397 + int nmsgs)
15398 +{
15399 + struct dm_i2c_bus *i2c = bus->uclass_priv;
15400 + struct dm_i2c_ops *ops;
15401 + struct udevice *emul, *dev;
15402 + bool is_read;
15403 + int ret;
15404 +
15405 + /* Special test code to return success but with no emulation */
15406 + if (msg->addr == SANDBOX_I2C_TEST_ADDR)
15407 + return 0;
15408 +
15409 + ret = i2c_get_chip(bus, msg->addr, &dev);
15410 + if (ret)
15411 + return ret;
15412 +
15413 + ret = get_emul(dev, &emul, &ops);
15414 + if (ret)
15415 + return ret;
15416 +
15417 + /*
15418 + * For testing, don't allow writing above 100KHz for writes and
15419 + * 400KHz for reads
15420 + */
15421 + is_read = nmsgs > 1;
15422 + if (i2c->speed_hz > (is_read ? 400000 : 100000))
15423 + return -EINVAL;
15424 + return ops->xfer(emul, msg, nmsgs);
15425 +}
15426 +
15427 +static const struct dm_i2c_ops sandbox_i2c_ops = {
15428 + .xfer = sandbox_i2c_xfer,
15429 +};
15430 +
15431 +static int sandbox_i2c_child_pre_probe(struct udevice *dev)
15432 +{
15433 + struct dm_i2c_chip *i2c_chip = dev_get_parentdata(dev);
15434 +
15435 + /* Ignore our test address */
15436 + if (i2c_chip->chip_addr == SANDBOX_I2C_TEST_ADDR)
15437 + return 0;
15438 + if (dev->of_offset == -1)
15439 + return 0;
15440 +
15441 + return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset,
15442 + i2c_chip);
15443 +}
15444 +
15445 +static const struct udevice_id sandbox_i2c_ids[] = {
15446 + { .compatible = "sandbox,i2c" },
15447 + { }
15448 +};
15449 +
15450 +U_BOOT_DRIVER(i2c_sandbox) = {
15451 + .name = "i2c_sandbox",
15452 + .id = UCLASS_I2C,
15453 + .of_match = sandbox_i2c_ids,
15454 + .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
15455 + .child_pre_probe = sandbox_i2c_child_pre_probe,
15456 + .ops = &sandbox_i2c_ops,
15457 +};
15458 diff -ruN u-boot-2015.01-rc3/drivers/i2c/tegra_i2c.c u-boot/drivers/i2c/tegra_i2c.c
15459 --- u-boot-2015.01-rc3/drivers/i2c/tegra_i2c.c 2014-12-08 22:35:08.000000000 +0100
15460 +++ u-boot/drivers/i2c/tegra_i2c.c 2015-01-01 17:34:32.649496760 +0100
15461 @@ -7,6 +7,8 @@
15462 */
15463
15464 #include <common.h>
15465 +#include <dm.h>
15466 +#include <errno.h>
15467 #include <fdtdec.h>
15468 #include <i2c.h>
15469 #include <asm/io.h>
15470 @@ -19,6 +21,12 @@
15471
15472 DECLARE_GLOBAL_DATA_PTR;
15473
15474 +enum i2c_type {
15475 + TYPE_114,
15476 + TYPE_STD,
15477 + TYPE_DVC,
15478 +};
15479 +
15480 /* Information about i2c controller */
15481 struct i2c_bus {
15482 int id;
15483 @@ -27,20 +35,17 @@
15484 int pinmux_config;
15485 struct i2c_control *control;
15486 struct i2c_ctlr *regs;
15487 - int is_dvc; /* DVC type, rather than I2C */
15488 - int is_scs; /* single clock source (T114+) */
15489 + enum i2c_type type;
15490 int inited; /* bus is inited */
15491 };
15492
15493 -static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS];
15494 -
15495 static void set_packet_mode(struct i2c_bus *i2c_bus)
15496 {
15497 u32 config;
15498
15499 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
15500
15501 - if (i2c_bus->is_dvc) {
15502 + if (i2c_bus->type == TYPE_DVC) {
15503 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
15504
15505 writel(config, &dvc->cnfg);
15506 @@ -65,6 +70,9 @@
15507
15508 static void i2c_init_controller(struct i2c_bus *i2c_bus)
15509 {
15510 + if (!i2c_bus->speed)
15511 + return;
15512 + debug("%s: speed=%d\n", __func__, i2c_bus->speed);
15513 /*
15514 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
15515 * here, in section 23.3.1, but in fact we seem to need a factor of
15516 @@ -73,7 +81,7 @@
15517 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH,
15518 i2c_bus->speed * 2 * 8);
15519
15520 - if (i2c_bus->is_scs) {
15521 + if (i2c_bus->type == TYPE_114) {
15522 /*
15523 * T114 I2C went to a single clock source for standard/fast and
15524 * HS clock speeds. The new clock rate setting calculation is:
15525 @@ -98,7 +106,7 @@
15526 i2c_reset_controller(i2c_bus);
15527
15528 /* Configure I2C controller. */
15529 - if (i2c_bus->is_dvc) { /* only for DVC I2C */
15530 + if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
15531 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
15532
15533 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
15534 @@ -272,7 +280,7 @@
15535 return error;
15536 }
15537
15538 -static int tegra_i2c_write_data(struct i2c_bus *bus, u32 addr, u8 *data,
15539 +static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
15540 u32 len, bool end_with_repeated_start)
15541 {
15542 int error;
15543 @@ -286,14 +294,14 @@
15544 trans_info.num_bytes = len;
15545 trans_info.is_10bit_address = 0;
15546
15547 - error = send_recv_packets(bus, &trans_info);
15548 + error = send_recv_packets(i2c_bus, &trans_info);
15549 if (error)
15550 debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
15551
15552 return error;
15553 }
15554
15555 -static int tegra_i2c_read_data(struct i2c_bus *bus, u32 addr, u8 *data,
15556 +static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
15557 u32 len)
15558 {
15559 int error;
15560 @@ -305,52 +313,32 @@
15561 trans_info.num_bytes = len;
15562 trans_info.is_10bit_address = 0;
15563
15564 - error = send_recv_packets(bus, &trans_info);
15565 + error = send_recv_packets(i2c_bus, &trans_info);
15566 if (error)
15567 debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
15568
15569 return error;
15570 }
15571
15572 -#ifndef CONFIG_OF_CONTROL
15573 -#error "Please enable device tree support to use this driver"
15574 -#endif
15575 -
15576 -/**
15577 - * Check that a bus number is valid and return a pointer to it
15578 - *
15579 - * @param bus_num Bus number to check / return
15580 - * @return pointer to bus, if valid, else NULL
15581 - */
15582 -static struct i2c_bus *tegra_i2c_get_bus(struct i2c_adapter *adap)
15583 +static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
15584 {
15585 - struct i2c_bus *bus;
15586 + struct i2c_bus *i2c_bus = dev_get_priv(dev);
15587
15588 - bus = &i2c_controllers[adap->hwadapnr];
15589 - if (!bus->inited) {
15590 - debug("%s: Bus %u not available\n", __func__, adap->hwadapnr);
15591 - return NULL;
15592 - }
15593 -
15594 - return bus;
15595 -}
15596 -
15597 -static unsigned int tegra_i2c_set_bus_speed(struct i2c_adapter *adap,
15598 - unsigned int speed)
15599 -{
15600 - struct i2c_bus *bus;
15601 -
15602 - bus = tegra_i2c_get_bus(adap);
15603 - if (!bus)
15604 - return 0;
15605 - bus->speed = speed;
15606 - i2c_init_controller(bus);
15607 + i2c_bus->speed = speed;
15608 + i2c_init_controller(i2c_bus);
15609
15610 return 0;
15611 }
15612
15613 -static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus)
15614 +static int tegra_i2c_probe(struct udevice *dev)
15615 {
15616 + struct i2c_bus *i2c_bus = dev_get_priv(dev);
15617 + const void *blob = gd->fdt_blob;
15618 + int node = dev->of_offset;
15619 + bool is_dvc;
15620 +
15621 + i2c_bus->id = dev->seq;
15622 + i2c_bus->type = dev_get_of_data(dev);
15623 i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg");
15624
15625 /*
15626 @@ -358,7 +346,6 @@
15627 * far no one needs anything other than the default.
15628 */
15629 i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
15630 - i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0);
15631 i2c_bus->periph_id = clock_decode_periph_id(blob, node);
15632
15633 /*
15634 @@ -371,107 +358,25 @@
15635 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
15636 */
15637 if (i2c_bus->periph_id == -1)
15638 - return -FDT_ERR_NOTFOUND;
15639 + return -EINVAL;
15640
15641 - return 0;
15642 -}
15643 -
15644 -/*
15645 - * Process a list of nodes, adding them to our list of I2C ports.
15646 - *
15647 - * @param blob fdt blob
15648 - * @param node_list list of nodes to process (any <=0 are ignored)
15649 - * @param count number of nodes to process
15650 - * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
15651 - * @param is_scs 1 if this HW uses a single clock source (T114+)
15652 - * @return 0 if ok, -1 on error
15653 - */
15654 -static int process_nodes(const void *blob, int node_list[], int count,
15655 - int is_dvc, int is_scs)
15656 -{
15657 - struct i2c_bus *i2c_bus;
15658 - int i;
15659 -
15660 - /* build the i2c_controllers[] for each controller */
15661 - for (i = 0; i < count; i++) {
15662 - int node = node_list[i];
15663 -
15664 - if (node <= 0)
15665 - continue;
15666 -
15667 - i2c_bus = &i2c_controllers[i];
15668 - i2c_bus->id = i;
15669 -
15670 - if (i2c_get_config(blob, node, i2c_bus)) {
15671 - printf("i2c_init_board: failed to decode bus %d\n", i);
15672 - return -1;
15673 - }
15674 -
15675 - i2c_bus->is_scs = is_scs;
15676 -
15677 - i2c_bus->is_dvc = is_dvc;
15678 - if (is_dvc) {
15679 - i2c_bus->control =
15680 - &((struct dvc_ctlr *)i2c_bus->regs)->control;
15681 - } else {
15682 - i2c_bus->control = &i2c_bus->regs->control;
15683 - }
15684 - debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
15685 - is_dvc ? "dvc" : "i2c", i, i2c_bus->regs,
15686 - i2c_bus->periph_id, i2c_bus->speed);
15687 - i2c_init_controller(i2c_bus);
15688 - debug("ok\n");
15689 - i2c_bus->inited = 1;
15690 -
15691 - /* Mark position as used */
15692 - node_list[i] = -1;
15693 + is_dvc = dev_get_of_data(dev) == TYPE_DVC;
15694 + if (is_dvc) {
15695 + i2c_bus->control =
15696 + &((struct dvc_ctlr *)i2c_bus->regs)->control;
15697 + } else {
15698 + i2c_bus->control = &i2c_bus->regs->control;
15699 }
15700 + i2c_init_controller(i2c_bus);
15701 + debug("%s: controller bus %d at %p, periph_id %d, speed %d: ",
15702 + is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs,
15703 + i2c_bus->periph_id, i2c_bus->speed);
15704
15705 return 0;
15706 }
15707
15708 -/* Sadly there is no error return from this function */
15709 -void i2c_init_board(void)
15710 -{
15711 - int node_list[TEGRA_I2C_NUM_CONTROLLERS];
15712 - const void *blob = gd->fdt_blob;
15713 - int count;
15714 -
15715 - /* First check for newer (T114+) I2C ports */
15716 - count = fdtdec_find_aliases_for_id(blob, "i2c",
15717 - COMPAT_NVIDIA_TEGRA114_I2C, node_list,
15718 - TEGRA_I2C_NUM_CONTROLLERS);
15719 - if (process_nodes(blob, node_list, count, 0, 1))
15720 - return;
15721 -
15722 - /* Now get the older (T20/T30) normal I2C ports */
15723 - count = fdtdec_find_aliases_for_id(blob, "i2c",
15724 - COMPAT_NVIDIA_TEGRA20_I2C, node_list,
15725 - TEGRA_I2C_NUM_CONTROLLERS);
15726 - if (process_nodes(blob, node_list, count, 0, 0))
15727 - return;
15728 -
15729 - /* Now look for dvc ports */
15730 - count = fdtdec_add_aliases_for_id(blob, "i2c",
15731 - COMPAT_NVIDIA_TEGRA20_DVC, node_list,
15732 - TEGRA_I2C_NUM_CONTROLLERS);
15733 - if (process_nodes(blob, node_list, count, 1, 0))
15734 - return;
15735 -}
15736 -
15737 -static void tegra_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
15738 -{
15739 - /* No i2c support prior to relocation */
15740 - if (!(gd->flags & GD_FLG_RELOC))
15741 - return;
15742 -
15743 - /* This will override the speed selected in the fdt for that port */
15744 - debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr);
15745 - i2c_set_bus_speed(speed);
15746 -}
15747 -
15748 /* i2c write version without the register address */
15749 -static int i2c_write_data(struct i2c_bus *bus, uchar chip, uchar *buffer,
15750 +static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
15751 int len, bool end_with_repeated_start)
15752 {
15753 int rc;
15754 @@ -484,7 +389,7 @@
15755 debug("\n");
15756
15757 /* Shift 7-bit address over for lower-level i2c functions */
15758 - rc = tegra_i2c_write_data(bus, chip << 1, buffer, len,
15759 + rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
15760 end_with_repeated_start);
15761 if (rc)
15762 debug("i2c_write_data(): rc=%d\n", rc);
15763 @@ -493,14 +398,14 @@
15764 }
15765
15766 /* i2c read version without the register address */
15767 -static int i2c_read_data(struct i2c_bus *bus, uchar chip, uchar *buffer,
15768 - int len)
15769 +static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
15770 + int len)
15771 {
15772 int rc;
15773
15774 debug("inside i2c_read_data():\n");
15775 /* Shift 7-bit address over for lower-level i2c functions */
15776 - rc = tegra_i2c_read_data(bus, chip << 1, buffer, len);
15777 + rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
15778 if (rc) {
15779 debug("i2c_read_data(): rc=%d\n", rc);
15780 return rc;
15781 @@ -516,132 +421,99 @@
15782 }
15783
15784 /* Probe to see if a chip is present. */
15785 -static int tegra_i2c_probe(struct i2c_adapter *adap, uchar chip)
15786 +static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
15787 + uint chip_flags)
15788 {
15789 - struct i2c_bus *bus;
15790 + struct i2c_bus *i2c_bus = dev_get_priv(bus);
15791 int rc;
15792 - uchar reg;
15793 + u8 reg;
15794
15795 - debug("i2c_probe: addr=0x%x\n", chip);
15796 - bus = tegra_i2c_get_bus(adap);
15797 - if (!bus)
15798 - return 1;
15799 - reg = 0;
15800 - rc = i2c_write_data(bus, chip, &reg, 1, false);
15801 - if (rc) {
15802 - debug("Error probing 0x%x.\n", chip);
15803 - return 1;
15804 - }
15805 - return 0;
15806 + /* Shift 7-bit address over for lower-level i2c functions */
15807 + rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, &reg, sizeof(reg),
15808 + false);
15809 +
15810 + return rc;
15811 }
15812
15813 -static int i2c_addr_ok(const uint addr, const int alen)
15814 +static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
15815 + int nmsgs)
15816 {
15817 - /* We support 7 or 10 bit addresses, so one or two bytes each */
15818 - return alen == 1 || alen == 2;
15819 -}
15820 + struct i2c_bus *i2c_bus = dev_get_priv(bus);
15821 + int ret;
15822
15823 -/* Read bytes */
15824 -static int tegra_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
15825 - int alen, uchar *buffer, int len)
15826 -{
15827 - struct i2c_bus *bus;
15828 - uint offset;
15829 - int i;
15830 -
15831 - debug("i2c_read: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
15832 - chip, addr, alen, len);
15833 - bus = tegra_i2c_get_bus(adap);
15834 - if (!bus)
15835 - return 1;
15836 - if (!i2c_addr_ok(addr, alen)) {
15837 - debug("i2c_read: Bad address %x.%d.\n", addr, alen);
15838 - return 1;
15839 - }
15840 - for (offset = 0; offset < len; offset++) {
15841 - if (alen) {
15842 - uchar data[alen];
15843 - for (i = 0; i < alen; i++) {
15844 - data[alen - i - 1] =
15845 - (addr + offset) >> (8 * i);
15846 - }
15847 - if (i2c_write_data(bus, chip, data, alen, true)) {
15848 - debug("i2c_read: error sending (0x%x)\n",
15849 - addr);
15850 - return 1;
15851 - }
15852 + debug("i2c_xfer: %d messages\n", nmsgs);
15853 + for (; nmsgs > 0; nmsgs--, msg++) {
15854 + bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
15855 +
15856 + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
15857 + if (msg->flags & I2C_M_RD) {
15858 + ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
15859 + msg->len);
15860 + } else {
15861 + ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
15862 + msg->len, next_is_read);
15863 }
15864 - if (i2c_read_data(bus, chip, buffer + offset, 1)) {
15865 - debug("i2c_read: error reading (0x%x)\n", addr);
15866 - return 1;
15867 + if (ret) {
15868 + debug("i2c_write: error sending\n");
15869 + return -EREMOTEIO;
15870 }
15871 }
15872
15873 return 0;
15874 }
15875
15876 -/* Write bytes */
15877 -static int tegra_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
15878 - int alen, uchar *buffer, int len)
15879 -{
15880 - struct i2c_bus *bus;
15881 - uint offset;
15882 - int i;
15883 -
15884 - debug("i2c_write: chip=0x%x, addr=0x%x, alen=0x%x len=0x%x\n",
15885 - chip, addr, alen, len);
15886 - bus = tegra_i2c_get_bus(adap);
15887 - if (!bus)
15888 - return 1;
15889 - if (!i2c_addr_ok(addr, alen)) {
15890 - debug("i2c_write: Bad address %x.%d.\n", addr, alen);
15891 - return 1;
15892 - }
15893 - for (offset = 0; offset < len; offset++) {
15894 - uchar data[alen + 1];
15895 - for (i = 0; i < alen; i++)
15896 - data[alen - i - 1] = (addr + offset) >> (8 * i);
15897 - data[alen] = buffer[offset];
15898 - if (i2c_write_data(bus, chip, data, alen + 1, false)) {
15899 - debug("i2c_write: error sending (0x%x)\n", addr);
15900 - return 1;
15901 +int tegra_i2c_get_dvc_bus(struct udevice **busp)
15902 +{
15903 + struct udevice *bus;
15904 +
15905 + for (uclass_first_device(UCLASS_I2C, &bus);
15906 + bus;
15907 + uclass_next_device(&bus)) {
15908 + if (dev_get_of_data(bus) == TYPE_DVC) {
15909 + *busp = bus;
15910 + return 0;
15911 }
15912 }
15913
15914 - return 0;
15915 + return -ENODEV;
15916 }
15917
15918 -int tegra_i2c_get_dvc_bus_num(void)
15919 -{
15920 - int i;
15921 +static const struct dm_i2c_ops tegra_i2c_ops = {
15922 + .xfer = tegra_i2c_xfer,
15923 + .probe_chip = tegra_i2c_probe_chip,
15924 + .set_bus_speed = tegra_i2c_set_bus_speed,
15925 +};
15926
15927 - for (i = 0; i < TEGRA_I2C_NUM_CONTROLLERS; i++) {
15928 - struct i2c_bus *bus = &i2c_controllers[i];
15929 +static int tegra_i2c_child_pre_probe(struct udevice *dev)
15930 +{
15931 + struct dm_i2c_chip *i2c_chip = dev_get_parentdata(dev);
15932
15933 - if (bus->inited && bus->is_dvc)
15934 - return i;
15935 - }
15936 + if (dev->of_offset == -1)
15937 + return 0;
15938 + return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset,
15939 + i2c_chip);
15940 +}
15941
15942 - return -1;
15943 +static int tegra_i2c_ofdata_to_platdata(struct udevice *dev)
15944 +{
15945 + return 0;
15946 }
15947
15948 -/*
15949 - * Register soft i2c adapters
15950 - */
15951 -U_BOOT_I2C_ADAP_COMPLETE(tegra0, tegra_i2c_init, tegra_i2c_probe,
15952 - tegra_i2c_read, tegra_i2c_write,
15953 - tegra_i2c_set_bus_speed, 100000, 0, 0)
15954 -U_BOOT_I2C_ADAP_COMPLETE(tegra1, tegra_i2c_init, tegra_i2c_probe,
15955 - tegra_i2c_read, tegra_i2c_write,
15956 - tegra_i2c_set_bus_speed, 100000, 0, 1)
15957 -U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
15958 - tegra_i2c_read, tegra_i2c_write,
15959 - tegra_i2c_set_bus_speed, 100000, 0, 2)
15960 -U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
15961 - tegra_i2c_read, tegra_i2c_write,
15962 - tegra_i2c_set_bus_speed, 100000, 0, 3)
15963 -#if TEGRA_I2C_NUM_CONTROLLERS > 4
15964 -U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe,
15965 - tegra_i2c_read, tegra_i2c_write,
15966 - tegra_i2c_set_bus_speed, 100000, 0, 4)
15967 -#endif
15968 +static const struct udevice_id tegra_i2c_ids[] = {
15969 + { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
15970 + { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
15971 + { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
15972 + { }
15973 +};
15974 +
15975 +U_BOOT_DRIVER(i2c_tegra) = {
15976 + .name = "i2c_tegra",
15977 + .id = UCLASS_I2C,
15978 + .of_match = tegra_i2c_ids,
15979 + .ofdata_to_platdata = tegra_i2c_ofdata_to_platdata,
15980 + .probe = tegra_i2c_probe,
15981 + .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
15982 + .child_pre_probe = tegra_i2c_child_pre_probe,
15983 + .priv_auto_alloc_size = sizeof(struct i2c_bus),
15984 + .ops = &tegra_i2c_ops,
15985 +};
15986 diff -ruN u-boot-2015.01-rc3/drivers/misc/i2c_eeprom.c u-boot/drivers/misc/i2c_eeprom.c
15987 --- u-boot-2015.01-rc3/drivers/misc/i2c_eeprom.c 1970-01-01 01:00:00.000000000 +0100
15988 +++ u-boot/drivers/misc/i2c_eeprom.c 2015-01-01 17:34:32.649496760 +0100
15989 @@ -0,0 +1,51 @@
15990 +/*
15991 + * Copyright (c) 2014 Google, Inc
15992 + *
15993 + * SPDX-License-Identifier: GPL-2.0+
15994 + */
15995 +
15996 +#include <common.h>
15997 +#include <dm.h>
15998 +#include <i2c.h>
15999 +#include <i2c_eeprom.h>
16000 +
16001 +static int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf,
16002 + int size)
16003 +{
16004 + return -ENODEV;
16005 +}
16006 +
16007 +static int i2c_eeprom_write(struct udevice *dev, int offset,
16008 + const uint8_t *buf, int size)
16009 +{
16010 + return -ENODEV;
16011 +}
16012 +
16013 +struct i2c_eeprom_ops i2c_eeprom_std_ops = {
16014 + .read = i2c_eeprom_read,
16015 + .write = i2c_eeprom_write,
16016 +};
16017 +
16018 +int i2c_eeprom_std_probe(struct udevice *dev)
16019 +{
16020 + return 0;
16021 +}
16022 +
16023 +static const struct udevice_id i2c_eeprom_std_ids[] = {
16024 + { .compatible = "i2c-eeprom" },
16025 + { }
16026 +};
16027 +
16028 +U_BOOT_DRIVER(i2c_eeprom_std) = {
16029 + .name = "i2c_eeprom",
16030 + .id = UCLASS_I2C_EEPROM,
16031 + .of_match = i2c_eeprom_std_ids,
16032 + .probe = i2c_eeprom_std_probe,
16033 + .priv_auto_alloc_size = sizeof(struct i2c_eeprom),
16034 + .ops = &i2c_eeprom_std_ops,
16035 +};
16036 +
16037 +UCLASS_DRIVER(i2c_eeprom) = {
16038 + .id = UCLASS_I2C_EEPROM,
16039 + .name = "i2c_eeprom",
16040 +};
16041 diff -ruN u-boot-2015.01-rc3/drivers/misc/i2c_eeprom_emul.c u-boot/drivers/misc/i2c_eeprom_emul.c
16042 --- u-boot-2015.01-rc3/drivers/misc/i2c_eeprom_emul.c 1970-01-01 01:00:00.000000000 +0100
16043 +++ u-boot/drivers/misc/i2c_eeprom_emul.c 2015-01-01 17:34:32.649496760 +0100
16044 @@ -0,0 +1,168 @@
16045 +/*
16046 + * Simulate an I2C eeprom
16047 + *
16048 + * Copyright (c) 2014 Google, Inc
16049 + *
16050 + * SPDX-License-Identifier: GPL-2.0+
16051 + */
16052 +
16053 +#include <common.h>
16054 +#include <dm.h>
16055 +#include <fdtdec.h>
16056 +#include <i2c.h>
16057 +#include <malloc.h>
16058 +#include <asm/test.h>
16059 +
16060 +#ifdef DEBUG
16061 +#define debug_buffer print_buffer
16062 +#else
16063 +#define debug_buffer(x, ...)
16064 +#endif
16065 +
16066 +DECLARE_GLOBAL_DATA_PTR;
16067 +
16068 +struct sandbox_i2c_flash_plat_data {
16069 + enum sandbox_i2c_eeprom_test_mode test_mode;
16070 + const char *filename;
16071 + int offset_len; /* Length of an offset in bytes */
16072 + int size; /* Size of data buffer */
16073 +};
16074 +
16075 +struct sandbox_i2c_flash {
16076 + uint8_t *data;
16077 +};
16078 +
16079 +void sandbox_i2c_eeprom_set_test_mode(struct udevice *dev,
16080 + enum sandbox_i2c_eeprom_test_mode mode)
16081 +{
16082 + struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
16083 +
16084 + plat->test_mode = mode;
16085 +}
16086 +
16087 +void sandbox_i2c_eeprom_set_offset_len(struct udevice *dev, int offset_len)
16088 +{
16089 + struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
16090 +
16091 + plat->offset_len = offset_len;
16092 +}
16093 +
16094 +static int sandbox_i2c_eeprom_xfer(struct udevice *emul, struct i2c_msg *msg,
16095 + int nmsgs)
16096 +{
16097 + struct sandbox_i2c_flash *priv = dev_get_priv(emul);
16098 + uint offset = 0;
16099 +
16100 + debug("\n%s\n", __func__);
16101 + debug_buffer(0, priv->data, 1, 16, 0);
16102 + for (; nmsgs > 0; nmsgs--, msg++) {
16103 + struct sandbox_i2c_flash_plat_data *plat =
16104 + dev_get_platdata(emul);
16105 + int len;
16106 + u8 *ptr;
16107 +
16108 + if (!plat->size)
16109 + return -ENODEV;
16110 + if (msg->addr + msg->len > plat->size) {
16111 + debug("%s: Address %x, len %x is outside range 0..%x\n",
16112 + __func__, msg->addr, msg->len, plat->size);
16113 + return -EINVAL;
16114 + }
16115 + len = msg->len;
16116 + debug(" %s: msg->len=%d",
16117 + msg->flags & I2C_M_RD ? "read" : "write",
16118 + msg->len);
16119 + if (msg->flags & I2C_M_RD) {
16120 + if (plat->test_mode == SIE_TEST_MODE_SINGLE_BYTE)
16121 + len = 1;
16122 + debug(", offset %x, len %x: ", offset, len);
16123 + memcpy(msg->buf, priv->data + offset, len);
16124 + memset(msg->buf + len, '\xff', msg->len - len);
16125 + debug_buffer(0, msg->buf, 1, msg->len, 0);
16126 + } else if (len >= plat->offset_len) {
16127 + int i;
16128 +
16129 + ptr = msg->buf;
16130 + for (i = 0; i < plat->offset_len; i++, len--)
16131 + offset = (offset << 8) | *ptr++;
16132 + debug(", set offset %x: ", offset);
16133 + debug_buffer(0, msg->buf, 1, msg->len, 0);
16134 + if (plat->test_mode == SIE_TEST_MODE_SINGLE_BYTE)
16135 + len = min(len, 1);
16136 +
16137 + /* For testing, map offsets into our limited buffer */
16138 + for (i = 24; i > 0; i -= 8) {
16139 + if (offset > (1 << i)) {
16140 + offset = (offset >> i) |
16141 + (offset & ((1 << i) - 1));
16142 + offset += i;
16143 + }
16144 + }
16145 + memcpy(priv->data + offset, ptr, len);
16146 + }
16147 + }
16148 + debug_buffer(0, priv->data, 1, 16, 0);
16149 +
16150 + return 0;
16151 +}
16152 +
16153 +struct dm_i2c_ops sandbox_i2c_emul_ops = {
16154 + .xfer = sandbox_i2c_eeprom_xfer,
16155 +};
16156 +
16157 +static int sandbox_i2c_eeprom_ofdata_to_platdata(struct udevice *dev)
16158 +{
16159 + struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
16160 +
16161 + plat->size = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
16162 + "sandbox,size", 32);
16163 + plat->filename = fdt_getprop(gd->fdt_blob, dev->of_offset,
16164 + "sandbox,filename", NULL);
16165 + if (!plat->filename) {
16166 + debug("%s: No filename for device '%s'\n", __func__,
16167 + dev->name);
16168 + return -EINVAL;
16169 + }
16170 + plat->test_mode = SIE_TEST_MODE_NONE;
16171 + plat->offset_len = 1;
16172 +
16173 + return 0;
16174 +}
16175 +
16176 +static int sandbox_i2c_eeprom_probe(struct udevice *dev)
16177 +{
16178 + struct sandbox_i2c_flash_plat_data *plat = dev_get_platdata(dev);
16179 + struct sandbox_i2c_flash *priv = dev_get_priv(dev);
16180 +
16181 + priv->data = calloc(1, plat->size);
16182 + if (!priv->data)
16183 + return -ENOMEM;
16184 +
16185 + return 0;
16186 +}
16187 +
16188 +static int sandbox_i2c_eeprom_remove(struct udevice *dev)
16189 +{
16190 + struct sandbox_i2c_flash *priv = dev_get_priv(dev);
16191 +
16192 + free(priv->data);
16193 +
16194 + return 0;
16195 +}
16196 +
16197 +static const struct udevice_id sandbox_i2c_ids[] = {
16198 + { .compatible = "sandbox,i2c-eeprom" },
16199 + { }
16200 +};
16201 +
16202 +U_BOOT_DRIVER(sandbox_i2c_emul) = {
16203 + .name = "sandbox_i2c_eeprom_emul",
16204 + .id = UCLASS_I2C_EMUL,
16205 + .of_match = sandbox_i2c_ids,
16206 + .ofdata_to_platdata = sandbox_i2c_eeprom_ofdata_to_platdata,
16207 + .probe = sandbox_i2c_eeprom_probe,
16208 + .remove = sandbox_i2c_eeprom_remove,
16209 + .priv_auto_alloc_size = sizeof(struct sandbox_i2c_flash),
16210 + .platdata_auto_alloc_size = sizeof(struct sandbox_i2c_flash_plat_data),
16211 + .ops = &sandbox_i2c_emul_ops,
16212 +};
16213 diff -ruN u-boot-2015.01-rc3/drivers/misc/Makefile u-boot/drivers/misc/Makefile
16214 --- u-boot-2015.01-rc3/drivers/misc/Makefile 2014-12-08 22:35:08.000000000 +0100
16215 +++ u-boot/drivers/misc/Makefile 2015-01-01 17:34:32.649496760 +0100
16216 @@ -15,11 +15,16 @@
16217 obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
16218 obj-$(CONFIG_FSL_IIM) += fsl_iim.o
16219 obj-$(CONFIG_GPIO_LED) += gpio_led.o
16220 +obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o
16221 obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
16222 obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
16223 obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
16224 obj-$(CONFIG_NS87308) += ns87308.o
16225 obj-$(CONFIG_PDSP188x) += pdsp188x.o
16226 +ifdef CONFIG_DM_I2C
16227 +obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
16228 +endif
16229 +obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
16230 obj-$(CONFIG_STATUS_LED) += status_led.o
16231 obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
16232 obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
16233 diff -ruN u-boot-2015.01-rc3/drivers/misc/mxc_ocotp.c u-boot/drivers/misc/mxc_ocotp.c
16234 --- u-boot-2015.01-rc3/drivers/misc/mxc_ocotp.c 2014-12-08 22:35:08.000000000 +0100
16235 +++ u-boot/drivers/misc/mxc_ocotp.c 2015-01-01 17:34:32.649496760 +0100
16236 @@ -81,8 +81,6 @@
16237 err = !!(readl(&regs->ctrl) & BM_CTRL_ERROR);
16238 clear_error(regs);
16239
16240 - enable_ocotp_clk(0);
16241 -
16242 if (err) {
16243 printf("mxc_ocotp %s(): Access protect error\n", caller);
16244 return -EIO;
16245 diff -ruN u-boot-2015.01-rc3/drivers/misc/mxs_ocotp.c u-boot/drivers/misc/mxs_ocotp.c
16246 --- u-boot-2015.01-rc3/drivers/misc/mxs_ocotp.c 2014-12-08 22:35:08.000000000 +0100
16247 +++ u-boot/drivers/misc/mxs_ocotp.c 2015-01-01 17:34:32.649496760 +0100
16248 @@ -187,6 +187,8 @@
16249 uint32_t hclk_val, vddio_val;
16250 int ret;
16251
16252 + mxs_ocotp_clear_error();
16253 +
16254 /* Make sure the banks are closed for reading. */
16255 ret = mxs_ocotp_read_bank_open(0);
16256 if (ret) {
16257 @@ -221,13 +223,17 @@
16258 goto fail;
16259 }
16260
16261 + /* Check for errors */
16262 + if (readl(&ocotp_regs->hw_ocotp_ctrl) & OCOTP_CTRL_ERROR) {
16263 + puts("Failed writing fuses!\n");
16264 + ret = -EPERM;
16265 + goto fail;
16266 + }
16267 +
16268 fail:
16269 mxs_ocotp_scale_vddio(0, &vddio_val);
16270 - ret = mxs_ocotp_scale_hclk(0, &hclk_val);
16271 - if (ret) {
16272 + if (mxs_ocotp_scale_hclk(0, &hclk_val))
16273 puts("Failed scaling up the HCLK!\n");
16274 - return ret;
16275 - }
16276
16277 return ret;
16278 }
16279 diff -ruN u-boot-2015.01-rc3/drivers/misc/smsc_lpc47m.c u-boot/drivers/misc/smsc_lpc47m.c
16280 --- u-boot-2015.01-rc3/drivers/misc/smsc_lpc47m.c 1970-01-01 01:00:00.000000000 +0100
16281 +++ u-boot/drivers/misc/smsc_lpc47m.c 2015-01-01 17:34:32.649496760 +0100
16282 @@ -0,0 +1,33 @@
16283 +/*
16284 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
16285 + *
16286 + * SPDX-License-Identifier: GPL-2.0+
16287 + */
16288 +
16289 +#include <common.h>
16290 +#include <asm/io.h>
16291 +#include <asm/pnp_def.h>
16292 +
16293 +static void pnp_enter_conf_state(u16 dev)
16294 +{
16295 + u16 port = dev >> 8;
16296 +
16297 + outb(0x55, port);
16298 +}
16299 +
16300 +static void pnp_exit_conf_state(u16 dev)
16301 +{
16302 + u16 port = dev >> 8;
16303 +
16304 + outb(0xaa, port);
16305 +}
16306 +
16307 +void lpc47m_enable_serial(u16 dev, u16 iobase)
16308 +{
16309 + pnp_enter_conf_state(dev);
16310 + pnp_set_logical_device(dev);
16311 + pnp_set_enable(dev, 0);
16312 + pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
16313 + pnp_set_enable(dev, 1);
16314 + pnp_exit_conf_state(dev);
16315 +}
16316 diff -ruN u-boot-2015.01-rc3/drivers/mmc/dw_mmc.c u-boot/drivers/mmc/dw_mmc.c
16317 --- u-boot-2015.01-rc3/drivers/mmc/dw_mmc.c 2014-12-08 22:35:08.000000000 +0100
16318 +++ u-boot/drivers/mmc/dw_mmc.c 2015-01-01 17:34:32.653496694 +0100
16319 @@ -318,7 +318,7 @@
16320 dwmci_writel(host, DWMCI_CTYPE, ctype);
16321
16322 regs = dwmci_readl(host, DWMCI_UHS_REG);
16323 - if (mmc->card_caps & MMC_MODE_DDR_52MHz)
16324 + if (mmc->ddr_mode)
16325 regs |= DWMCI_DDR_MODE;
16326 else
16327 regs &= DWMCI_DDR_MODE;
16328 diff -ruN u-boot-2015.01-rc3/drivers/mmc/exynos_dw_mmc.c u-boot/drivers/mmc/exynos_dw_mmc.c
16329 --- u-boot-2015.01-rc3/drivers/mmc/exynos_dw_mmc.c 2014-12-08 22:35:08.000000000 +0100
16330 +++ u-boot/drivers/mmc/exynos_dw_mmc.c 2015-01-01 17:34:32.653496694 +0100
16331 @@ -101,7 +101,7 @@
16332 host->get_mmc_clk = exynos_dwmci_get_clk;
16333 /* Add the mmc channel to be registered with mmc core */
16334 if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
16335 - debug("dwmmc%d registration failed\n", index);
16336 + printf("DWMMC%d registration failed\n", index);
16337 return -1;
16338 }
16339 return 0;
16340 @@ -146,7 +146,7 @@
16341 flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
16342 err = exynos_pinmux_config(host->dev_id, flag);
16343 if (err) {
16344 - debug("DWMMC not configure\n");
16345 + printf("DWMMC%d not configure\n", index);
16346 return err;
16347 }
16348
16349 @@ -162,21 +162,22 @@
16350 /* Extract device id for each mmc channel */
16351 host->dev_id = pinmux_decode_periph_id(blob, node);
16352
16353 + host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
16354 + if (host->dev_index == host->dev_id)
16355 + host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
16356 +
16357 +
16358 /* Get the bus width from the device node */
16359 host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
16360 if (host->buswidth <= 0) {
16361 - debug("DWMMC: Can't get bus-width\n");
16362 + printf("DWMMC%d: Can't get bus-width\n", host->dev_index);
16363 return -EINVAL;
16364 }
16365
16366 - host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
16367 - if (host->dev_index == host->dev_id)
16368 - host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
16369 -
16370 /* Set the base address from the device node */
16371 base = fdtdec_get_addr(blob, node, "reg");
16372 if (!base) {
16373 - debug("DWMMC: Can't get base address\n");
16374 + printf("DWMMC%d: Can't get base address\n", host->dev_index);
16375 return -EINVAL;
16376 }
16377 host->ioaddr = (void *)base;
16378 @@ -184,7 +185,8 @@
16379 /* Extract the timing info from the node */
16380 err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
16381 if (err) {
16382 - debug("Can't get sdr-timings for devider\n");
16383 + printf("DWMMC%d: Can't get sdr-timings for devider\n",
16384 + host->dev_index);
16385 return -EINVAL;
16386 }
16387
16388 @@ -214,7 +216,7 @@
16389 host = &dwmci_host[i];
16390 err = exynos_dwmci_get_config(blob, node, host);
16391 if (err) {
16392 - debug("%s: failed to decode dev %d\n", __func__, i);
16393 + printf("%s: failed to decode dev %d\n", __func__, i);
16394 return err;
16395 }
16396
16397 diff -ruN u-boot-2015.01-rc3/drivers/mmc/mmc.c u-boot/drivers/mmc/mmc.c
16398 --- u-boot-2015.01-rc3/drivers/mmc/mmc.c 2014-12-08 22:35:08.000000000 +0100
16399 +++ u-boot/drivers/mmc/mmc.c 2015-01-01 17:34:32.653496694 +0100
16400 @@ -159,7 +159,7 @@
16401 {
16402 struct mmc_cmd cmd;
16403
16404 - if (mmc->card_caps & MMC_MODE_DDR_52MHz)
16405 + if (mmc->ddr_mode)
16406 return 0;
16407
16408 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
16409 @@ -486,7 +486,7 @@
16410 char cardtype;
16411 int err;
16412
16413 - mmc->card_caps = 0;
16414 + mmc->card_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
16415
16416 if (mmc_host_is_spi(mmc))
16417 return 0;
16418 @@ -519,7 +519,7 @@
16419
16420 /* High Speed is set, there are two types: 52MHz and 26MHz */
16421 if (cardtype & EXT_CSD_CARD_TYPE_52) {
16422 - if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
16423 + if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
16424 mmc->card_caps |= MMC_MODE_DDR_52MHz;
16425 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
16426 } else {
16427 @@ -1001,6 +1001,9 @@
16428 case 6:
16429 mmc->version = MMC_VERSION_4_5;
16430 break;
16431 + case 7:
16432 + mmc->version = MMC_VERSION_5_0;
16433 + break;
16434 }
16435
16436 /*
16437 @@ -1022,6 +1025,21 @@
16438 mmc->erase_grp_size =
16439 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
16440 MMC_MAX_BLOCK_LEN * 1024;
16441 + /*
16442 + * if high capacity and partition setting completed
16443 + * SEC_COUNT is valid even if it is smaller than 2 GiB
16444 + * JEDEC Standard JESD84-B45, 6.2.4
16445 + */
16446 + if (mmc->high_capacity &&
16447 + (ext_csd[EXT_CSD_PARTITION_SETTING] &
16448 + EXT_CSD_PARTITION_SETTING_COMPLETED)) {
16449 + capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
16450 + (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
16451 + (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
16452 + (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
16453 + capacity *= MMC_MAX_BLOCK_LEN;
16454 + mmc->capacity_user = capacity;
16455 + }
16456 } else {
16457 /* Calculate the group size from the csd value. */
16458 int erase_gsz, erase_gmul;
16459 @@ -1103,8 +1121,10 @@
16460
16461 /* An array to map CSD bus widths to host cap bits */
16462 static unsigned ext_to_hostcaps[] = {
16463 - [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
16464 - [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
16465 + [EXT_CSD_DDR_BUS_WIDTH_4] =
16466 + MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
16467 + [EXT_CSD_DDR_BUS_WIDTH_8] =
16468 + MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
16469 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
16470 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
16471 };
16472 @@ -1116,13 +1136,13 @@
16473
16474 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
16475 unsigned int extw = ext_csd_bits[idx];
16476 + unsigned int caps = ext_to_hostcaps[extw];
16477
16478 /*
16479 - * Check to make sure the controller supports
16480 - * this bus width, if it's more than 1
16481 + * Check to make sure the card and controller support
16482 + * these capabilities
16483 */
16484 - if (extw != EXT_CSD_BUS_WIDTH_1 &&
16485 - !(mmc->cfg->host_caps & ext_to_hostcaps[extw]))
16486 + if ((mmc->card_caps & caps) != caps)
16487 continue;
16488
16489 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
16490 @@ -1131,26 +1151,33 @@
16491 if (err)
16492 continue;
16493
16494 + mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
16495 mmc_set_bus_width(mmc, widths[idx]);
16496
16497 err = mmc_send_ext_csd(mmc, test_csd);
16498 - /* Only compare read only fields */
16499 - if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
16500 - == test_csd[EXT_CSD_PARTITIONING_SUPPORT]
16501 - && ext_csd[EXT_CSD_HC_WP_GRP_SIZE] \
16502 - == test_csd[EXT_CSD_HC_WP_GRP_SIZE] \
16503 - && ext_csd[EXT_CSD_REV] \
16504 - == test_csd[EXT_CSD_REV]
16505 - && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
16506 - == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
16507 - && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
16508 - &test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
16509
16510 - mmc->card_caps |= ext_to_hostcaps[extw];
16511 + if (err)
16512 + continue;
16513 +
16514 + /* Only compare read only fields */
16515 + if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
16516 + == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
16517 + ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
16518 + == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
16519 + ext_csd[EXT_CSD_REV]
16520 + == test_csd[EXT_CSD_REV] &&
16521 + ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
16522 + == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
16523 + memcmp(&ext_csd[EXT_CSD_SEC_CNT],
16524 + &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
16525 break;
16526 - }
16527 + else
16528 + err = SWITCH_ERR;
16529 }
16530
16531 + if (err)
16532 + return err;
16533 +
16534 if (mmc->card_caps & MMC_MODE_HS) {
16535 if (mmc->card_caps & MMC_MODE_HS_52MHz)
16536 mmc->tran_speed = 52000000;
16537 @@ -1161,6 +1188,12 @@
16538
16539 mmc_set_clock(mmc, mmc->tran_speed);
16540
16541 + /* Fix the block length for DDR mode */
16542 + if (mmc->ddr_mode) {
16543 + mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
16544 + mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
16545 + }
16546 +
16547 /* fill in device description */
16548 mmc->block_dev.lun = 0;
16549 mmc->block_dev.type = 0;
16550 @@ -1306,6 +1339,7 @@
16551 if (err)
16552 return err;
16553
16554 + mmc->ddr_mode = 0;
16555 mmc_set_bus_width(mmc, 1);
16556 mmc_set_clock(mmc, 1);
16557
16558 @@ -1408,8 +1442,11 @@
16559
16560 printf("%s: %d", m->cfg->name, m->block_dev.dev);
16561
16562 - if (entry->next != &mmc_devices)
16563 - printf("%c ", separator);
16564 + if (entry->next != &mmc_devices) {
16565 + printf("%c", separator);
16566 + if (separator != '\n')
16567 + puts (" ");
16568 + }
16569 }
16570
16571 printf("\n");
16572 diff -ruN u-boot-2015.01-rc3/drivers/mtd/nand/fsl_ifc_nand.c u-boot/drivers/mtd/nand/fsl_ifc_nand.c
16573 --- u-boot-2015.01-rc3/drivers/mtd/nand/fsl_ifc_nand.c 2014-12-08 22:35:08.000000000 +0100
16574 +++ u-boot/drivers/mtd/nand/fsl_ifc_nand.c 2015-01-01 17:34:32.657496629 +0100
16575 @@ -292,7 +292,7 @@
16576 struct fsl_ifc *ifc = ctrl->regs;
16577 u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
16578 u32 time_start;
16579 - u32 eccstat[4];
16580 + u32 eccstat[4] = {0};
16581 int i;
16582
16583 /* set the chip select for NAND Transaction */
16584 diff -ruN u-boot-2015.01-rc3/drivers/mtd/nand/fsl_ifc_spl.c u-boot/drivers/mtd/nand/fsl_ifc_spl.c
16585 --- u-boot-2015.01-rc3/drivers/mtd/nand/fsl_ifc_spl.c 2014-12-08 22:35:08.000000000 +0100
16586 +++ u-boot/drivers/mtd/nand/fsl_ifc_spl.c 2015-01-01 17:34:32.657496629 +0100
16587 @@ -254,3 +254,13 @@
16588 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
16589 uboot();
16590 }
16591 +
16592 +#ifndef CONFIG_SPL_NAND_INIT
16593 +void nand_init(void)
16594 +{
16595 +}
16596 +
16597 +void nand_deselect(void)
16598 +{
16599 +}
16600 +#endif
16601 diff -ruN u-boot-2015.01-rc3/drivers/mtd/spi/sf_internal.h u-boot/drivers/mtd/spi/sf_internal.h
16602 --- u-boot-2015.01-rc3/drivers/mtd/spi/sf_internal.h 2014-12-08 22:35:08.000000000 +0100
16603 +++ u-boot/drivers/mtd/spi/sf_internal.h 2015-01-01 17:34:32.665496498 +0100
16604 @@ -23,13 +23,16 @@
16605 /* Enum list - Full read commands */
16606 enum spi_read_cmds {
16607 ARRAY_SLOW = 1 << 0,
16608 - DUAL_OUTPUT_FAST = 1 << 1,
16609 - DUAL_IO_FAST = 1 << 2,
16610 - QUAD_OUTPUT_FAST = 1 << 3,
16611 - QUAD_IO_FAST = 1 << 4,
16612 + ARRAY_FAST = 1 << 1,
16613 + DUAL_OUTPUT_FAST = 1 << 2,
16614 + DUAL_IO_FAST = 1 << 3,
16615 + QUAD_OUTPUT_FAST = 1 << 4,
16616 + QUAD_IO_FAST = 1 << 5,
16617 };
16618
16619 -#define RD_EXTN (ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
16620 +/* Normal - Extended - Full command set */
16621 +#define RD_NORM (ARRAY_SLOW | ARRAY_FAST)
16622 +#define RD_EXTN (RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
16623 #define RD_FULL (RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
16624
16625 /* sf param flags */
16626 @@ -37,9 +40,13 @@
16627 SECT_4K = 1 << 0,
16628 SECT_32K = 1 << 1,
16629 E_FSR = 1 << 2,
16630 - WR_QPP = 1 << 3,
16631 + SST_BP = 1 << 3,
16632 + SST_WP = 1 << 4,
16633 + WR_QPP = 1 << 5,
16634 };
16635
16636 +#define SST_WR (SST_BP | SST_WP)
16637 +
16638 #define SPI_FLASH_3B_ADDR_LEN 3
16639 #define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
16640 #define SPI_FLASH_16MB_BOUN 0x1000000
16641 @@ -101,12 +108,13 @@
16642
16643 /* SST specific */
16644 #ifdef CONFIG_SPI_FLASH_SST
16645 -# define SST_WP 0x01 /* Supports AAI word program */
16646 # define CMD_SST_BP 0x02 /* Byte Program */
16647 # define CMD_SST_AAI_WP 0xAD /* Auto Address Incr Word Program */
16648
16649 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
16650 const void *buf);
16651 +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
16652 + const void *buf);
16653 #endif
16654
16655 /**
16656 diff -ruN u-boot-2015.01-rc3/drivers/mtd/spi/sf_ops.c u-boot/drivers/mtd/spi/sf_ops.c
16657 --- u-boot-2015.01-rc3/drivers/mtd/spi/sf_ops.c 2014-12-08 22:35:08.000000000 +0100
16658 +++ u-boot/drivers/mtd/spi/sf_ops.c 2015-01-01 17:34:32.665496498 +0100
16659 @@ -517,4 +517,35 @@
16660 spi_release_bus(flash->spi);
16661 return ret;
16662 }
16663 +
16664 +int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
16665 + const void *buf)
16666 +{
16667 + size_t actual;
16668 + int ret;
16669 +
16670 + ret = spi_claim_bus(flash->spi);
16671 + if (ret) {
16672 + debug("SF: Unable to claim SPI bus\n");
16673 + return ret;
16674 + }
16675 +
16676 + for (actual = 0; actual < len; actual++) {
16677 + ret = sst_byte_write(flash, offset, buf + actual);
16678 + if (ret) {
16679 + debug("SF: sst byte program failed\n");
16680 + break;
16681 + }
16682 + offset++;
16683 + }
16684 +
16685 + if (!ret)
16686 + ret = spi_flash_cmd_write_disable(flash);
16687 +
16688 + debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
16689 + ret ? "failure" : "success", len, offset - actual);
16690 +
16691 + spi_release_bus(flash->spi);
16692 + return ret;
16693 +}
16694 #endif
16695 diff -ruN u-boot-2015.01-rc3/drivers/mtd/spi/sf_params.c u-boot/drivers/mtd/spi/sf_params.c
16696 --- u-boot-2015.01-rc3/drivers/mtd/spi/sf_params.c 2014-12-08 22:35:08.000000000 +0100
16697 +++ u-boot/drivers/mtd/spi/sf_params.c 2015-01-01 17:34:32.665496498 +0100
16698 @@ -15,42 +15,42 @@
16699 /* SPI/QSPI flash device params structure */
16700 const struct spi_flash_params spi_flash_params_table[] = {
16701 #ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
16702 - {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, 0, SECT_4K},
16703 - {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, 0, SECT_4K},
16704 - {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, 0, SECT_4K},
16705 - {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, 0, SECT_4K},
16706 - {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, 0, SECT_4K},
16707 - {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, 0, SECT_4K},
16708 - {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, 0, SECT_4K},
16709 - {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, 0, SECT_4K},
16710 + {"AT45DB011D", 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K},
16711 + {"AT45DB021D", 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
16712 + {"AT45DB041D", 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
16713 + {"AT45DB081D", 0x1f2500, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K},
16714 + {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
16715 + {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
16716 + {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
16717 + {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
16718 #endif
16719 #ifdef CONFIG_SPI_FLASH_EON /* EON */
16720 - {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, 0, 0},
16721 - {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
16722 - {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0, 0},
16723 - {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0, 0},
16724 + {"EN25Q32B", 0x1c3016, 0x0, 64 * 1024, 64, RD_NORM, 0},
16725 + {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
16726 + {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM, 0},
16727 + {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, RD_NORM, 0},
16728 #endif
16729 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
16730 - {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, 0, SECT_4K},
16731 - {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, 0, SECT_4K},
16732 + {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
16733 + {"GD25LQ32", 0xc86016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
16734 #endif
16735 #ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
16736 - {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, 0, 0},
16737 - {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, 0, 0},
16738 - {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, 0, 0},
16739 - {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, 0, 0},
16740 - {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, 0, 0},
16741 - {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, 0, 0},
16742 + {"MX25L2006E", 0xc22012, 0x0, 64 * 1024, 4, RD_NORM, 0},
16743 + {"MX25L4005", 0xc22013, 0x0, 64 * 1024, 8, RD_NORM, 0},
16744 + {"MX25L8005", 0xc22014, 0x0, 64 * 1024, 16, RD_NORM, 0},
16745 + {"MX25L1605D", 0xc22015, 0x0, 64 * 1024, 32, RD_NORM, 0},
16746 + {"MX25L3205D", 0xc22016, 0x0, 64 * 1024, 64, RD_NORM, 0},
16747 + {"MX25L6405D", 0xc22017, 0x0, 64 * 1024, 128, RD_NORM, 0},
16748 {"MX25L12805", 0xc22018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
16749 {"MX25L25635F", 0xc22019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP},
16750 {"MX25L51235F", 0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP},
16751 {"MX25L12855E", 0xc22618, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP},
16752 #endif
16753 #ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
16754 - {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, 0, 0},
16755 - {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0},
16756 - {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0},
16757 - {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0},
16758 + {"S25FL008A", 0x010213, 0x0, 64 * 1024, 16, RD_NORM, 0},
16759 + {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, RD_NORM, 0},
16760 + {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, RD_NORM, 0},
16761 + {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, RD_NORM, 0},
16762 {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP},
16763 {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP},
16764 {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP},
16765 @@ -64,17 +64,17 @@
16766 {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
16767 #endif
16768 #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
16769 - {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
16770 - {"M25P20", 0x202012, 0x0, 64 * 1024, 4, 0, 0},
16771 - {"M25P40", 0x202013, 0x0, 64 * 1024, 8, 0, 0},
16772 - {"M25P80", 0x202014, 0x0, 64 * 1024, 16, 0, 0},
16773 - {"M25P16", 0x202015, 0x0, 64 * 1024, 32, 0, 0},
16774 - {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, 0, 0},
16775 + {"M25P10", 0x202011, 0x0, 32 * 1024, 4, RD_NORM, 0},
16776 + {"M25P20", 0x202012, 0x0, 64 * 1024, 4, RD_NORM, 0},
16777 + {"M25P40", 0x202013, 0x0, 64 * 1024, 8, RD_NORM, 0},
16778 + {"M25P80", 0x202014, 0x0, 64 * 1024, 16, RD_NORM, 0},
16779 + {"M25P16", 0x202015, 0x0, 64 * 1024, 32, RD_NORM, 0},
16780 + {"M25PE16", 0x208015, 0x1000, 64 * 1024, 32, RD_NORM, 0},
16781 {"M25PX16", 0x207115, 0x1000, 64 * 1024, 32, RD_EXTN, 0},
16782 - {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0},
16783 - {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0},
16784 - {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0},
16785 - {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, 0, SECT_4K},
16786 + {"M25P32", 0x202016, 0x0, 64 * 1024, 64, RD_NORM, 0},
16787 + {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0},
16788 + {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0},
16789 + {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
16790 {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
16791 {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
16792 {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K},
16793 @@ -89,25 +89,25 @@
16794 {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K},
16795 #endif
16796 #ifdef CONFIG_SPI_FLASH_SST /* SST */
16797 - {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
16798 - {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
16799 - {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, 0, SECT_4K | SST_WP},
16800 - {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, 0, SECT_4K | SST_WP},
16801 - {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, 0, SECT_4K},
16802 - {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, 0, SECT_4K | SST_WP},
16803 - {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, 0, SECT_4K | SST_WP},
16804 - {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, 0, SECT_4K | SST_WP},
16805 - {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP},
16806 - {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, 0, SECT_4K | SST_WP},
16807 + {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
16808 + {"SST25VF080B", 0xbf258e, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
16809 + {"SST25VF016B", 0xbf2541, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K | SST_WR},
16810 + {"SST25VF032B", 0xbf254a, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K | SST_WR},
16811 + {"SST25VF064C", 0xbf254b, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
16812 + {"SST25WF512", 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM, SECT_4K | SST_WR},
16813 + {"SST25WF010", 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM, SECT_4K | SST_WR},
16814 + {"SST25WF020", 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM, SECT_4K | SST_WR},
16815 + {"SST25WF040", 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K | SST_WR},
16816 + {"SST25WF080", 0xbf2505, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K | SST_WR},
16817 #endif
16818 #ifdef CONFIG_SPI_FLASH_WINBOND /* WINBOND */
16819 - {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, 0, 0},
16820 - {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, 0, 0},
16821 - {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, 0, 0},
16822 - {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, 0, SECT_4K},
16823 - {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K},
16824 - {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K},
16825 - {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K},
16826 + {"W25P80", 0xef2014, 0x0, 64 * 1024, 16, RD_NORM, 0},
16827 + {"W25P16", 0xef2015, 0x0, 64 * 1024, 32, RD_NORM, 0},
16828 + {"W25P32", 0xef2016, 0x0, 64 * 1024, 64, RD_NORM, 0},
16829 + {"W25X40", 0xef3013, 0x0, 64 * 1024, 8, RD_NORM, SECT_4K},
16830 + {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K},
16831 + {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K},
16832 + {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K},
16833 {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K},
16834 {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K},
16835 {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K},
16836 diff -ruN u-boot-2015.01-rc3/drivers/mtd/spi/sf_probe.c u-boot/drivers/mtd/spi/sf_probe.c
16837 --- u-boot-2015.01-rc3/drivers/mtd/spi/sf_probe.c 2014-12-08 22:35:08.000000000 +0100
16838 +++ u-boot/drivers/mtd/spi/sf_probe.c 2015-01-01 17:34:32.665496498 +0100
16839 @@ -24,6 +24,7 @@
16840 /* Read commands array */
16841 static u8 spi_read_cmds_array[] = {
16842 CMD_READ_ARRAY_SLOW,
16843 + CMD_READ_ARRAY_FAST,
16844 CMD_READ_DUAL_OUTPUT_FAST,
16845 CMD_READ_DUAL_IO_FAST,
16846 CMD_READ_QUAD_OUTPUT_FAST,
16847 @@ -135,8 +136,12 @@
16848 #ifndef CONFIG_DM_SPI_FLASH
16849 flash->write = spi_flash_cmd_write_ops;
16850 #if defined(CONFIG_SPI_FLASH_SST)
16851 - if (params->flags & SST_WP)
16852 - flash->write = sst_write_wp;
16853 + if (params->flags & SST_WR) {
16854 + if (flash->spi->op_mode_tx & SPI_OPM_TX_BP)
16855 + flash->write = sst_write_bp;
16856 + else
16857 + flash->write = sst_write_wp;
16858 + }
16859 #endif
16860 flash->erase = spi_flash_cmd_erase_ops;
16861 flash->read = spi_flash_cmd_read_ops;
16862 diff -ruN u-boot-2015.01-rc3/drivers/net/fm/init.c u-boot/drivers/net/fm/init.c
16863 --- u-boot-2015.01-rc3/drivers/net/fm/init.c 2014-12-08 22:35:08.000000000 +0100
16864 +++ u-boot/drivers/net/fm/init.c 2015-01-01 17:34:32.677496300 +0100
16865 @@ -247,17 +247,17 @@
16866 }
16867
16868 #ifdef CONFIG_SYS_FMAN_V3
16869 +#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
16870 /*
16871 - * Physically FM1_DTSEC9 and FM1_10GEC1 use the same dual-role MAC, when
16872 - * FM1_10GEC1 is enabled and FM1_DTSEC9 is disabled, ensure that the
16873 - * dual-role MAC is not disabled, ditto for other dual-role MACs.
16874 + * On T2/T4 SoCs, physically FM1_DTSEC9 and FM1_10GEC1 use the same
16875 + * dual-role MAC, when FM1_10GEC1 is enabled and FM1_DTSEC9
16876 + * is disabled, ensure that the dual-role MAC is not disabled,
16877 + * ditto for other dual-role MACs.
16878 */
16879 if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
16880 ((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
16881 - ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
16882 ((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
16883 ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
16884 - ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
16885 ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) ||
16886 ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) ||
16887 ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
16888 @@ -269,6 +269,17 @@
16889 ((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9))) ||
16890 ((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10)))
16891 #endif
16892 +#else
16893 + /* FM1_DTSECx and FM1_10GECx use the same dual-role MAC */
16894 + if (((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
16895 + ((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
16896 + ((info->port == FM1_DTSEC3) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
16897 + ((info->port == FM1_DTSEC4) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
16898 + ((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
16899 + ((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC2))) ||
16900 + ((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC3))) ||
16901 + ((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4)))
16902 +#endif
16903 )
16904 return;
16905 #endif
16906 diff -ruN u-boot-2015.01-rc3/drivers/pci/Makefile u-boot/drivers/pci/Makefile
16907 --- u-boot-2015.01-rc3/drivers/pci/Makefile 2014-12-08 22:35:08.000000000 +0100
16908 +++ u-boot/drivers/pci/Makefile 2015-01-01 17:34:32.685496170 +0100
16909 @@ -17,3 +17,4 @@
16910 obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
16911 obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
16912 obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
16913 +obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
16914 diff -ruN u-boot-2015.01-rc3/drivers/pci/pcie_layerscape.c u-boot/drivers/pci/pcie_layerscape.c
16915 --- u-boot-2015.01-rc3/drivers/pci/pcie_layerscape.c 1970-01-01 01:00:00.000000000 +0100
16916 +++ u-boot/drivers/pci/pcie_layerscape.c 2015-01-01 17:34:32.689496104 +0100
16917 @@ -0,0 +1,51 @@
16918 +/*
16919 + * Copyright 2014 Freescale Semiconductor, Inc.
16920 + * Layerscape PCIe driver
16921 + *
16922 + * SPDX-License-Identifier: GPL-2.0+
16923 + */
16924 +
16925 +#include <common.h>
16926 +#include <asm/arch/fsl_serdes.h>
16927 +#include <pci.h>
16928 +#include <asm/io.h>
16929 +#include <asm/pcie_layerscape.h>
16930 +
16931 +#ifdef CONFIG_OF_BOARD_SETUP
16932 +#include <libfdt.h>
16933 +#include <fdt_support.h>
16934 +
16935 +static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
16936 + unsigned long ctrl_addr, enum srds_prtcl dev)
16937 +{
16938 + int off;
16939 +
16940 + off = fdt_node_offset_by_compat_reg(blob, pci_compat,
16941 + (phys_addr_t)ctrl_addr);
16942 + if (off < 0)
16943 + return;
16944 +
16945 + if (!is_serdes_configured(dev))
16946 + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
16947 +}
16948 +
16949 +void ft_pcie_setup(void *blob, bd_t *bd)
16950 +{
16951 + #ifdef CONFIG_PCIE1
16952 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
16953 + #endif
16954 +
16955 + #ifdef CONFIG_PCIE2
16956 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
16957 + #endif
16958 +}
16959 +
16960 +#else
16961 +void ft_pcie_setup(void *blob, bd_t *bd)
16962 +{
16963 +}
16964 +#endif
16965 +
16966 +void pci_init_board(void)
16967 +{
16968 +}
16969 diff -ruN u-boot-2015.01-rc3/drivers/power/tps6586x.c u-boot/drivers/power/tps6586x.c
16970 --- u-boot-2015.01-rc3/drivers/power/tps6586x.c 2014-12-08 22:35:08.000000000 +0100
16971 +++ u-boot/drivers/power/tps6586x.c 2015-01-01 17:34:32.693496038 +0100
16972 @@ -10,9 +10,7 @@
16973 #include <asm/io.h>
16974 #include <i2c.h>
16975
16976 -static int bus_num; /* I2C bus we are on */
16977 -#define I2C_ADDRESS 0x34 /* chip requires this address */
16978 -static char inited; /* 1 if we have been inited */
16979 +static struct udevice *tps6586x_dev;
16980
16981 enum {
16982 /* Registers that we access */
16983 @@ -37,13 +35,9 @@
16984 int i;
16985 uchar data;
16986 int retval = -1;
16987 - int old_bus_num;
16988 -
16989 - old_bus_num = i2c_get_bus_num();
16990 - i2c_set_bus_num(bus_num);
16991
16992 for (i = 0; i < MAX_I2C_RETRY; ++i) {
16993 - if (!i2c_read(I2C_ADDRESS, reg, 1, &data, 1)) {
16994 + if (!i2c_read(tps6586x_dev, reg, &data, 1)) {
16995 retval = (int)data;
16996 goto exit;
16997 }
16998 @@ -53,7 +47,6 @@
16999 }
17000
17001 exit:
17002 - i2c_set_bus_num(old_bus_num);
17003 debug("pmu_read %x=%x\n", reg, retval);
17004 if (retval < 0)
17005 debug("%s: failed to read register %#x: %d\n", __func__, reg,
17006 @@ -65,13 +58,9 @@
17007 {
17008 int i;
17009 int retval = -1;
17010 - int old_bus_num;
17011 -
17012 - old_bus_num = i2c_get_bus_num();
17013 - i2c_set_bus_num(bus_num);
17014
17015 for (i = 0; i < MAX_I2C_RETRY; ++i) {
17016 - if (!i2c_write(I2C_ADDRESS, reg, 1, data, len)) {
17017 + if (!i2c_write(tps6586x_dev, reg, data, len)) {
17018 retval = 0;
17019 goto exit;
17020 }
17021 @@ -81,7 +70,6 @@
17022 }
17023
17024 exit:
17025 - i2c_set_bus_num(old_bus_num);
17026 debug("pmu_write %x=%x: ", reg, retval);
17027 for (i = 0; i < len; i++)
17028 debug("%x ", data[i]);
17029 @@ -163,7 +151,7 @@
17030 uchar val;
17031 int ret;
17032
17033 - assert(inited);
17034 + assert(tps6586x_dev);
17035 ret = tps6586x_read(PFM_MODE);
17036 if (ret != -1) {
17037 val = (uchar)ret;
17038 @@ -184,7 +172,7 @@
17039 int sm0, sm1;
17040 int bad;
17041
17042 - assert(inited);
17043 + assert(tps6586x_dev);
17044
17045 /* get current voltage settings */
17046 if (read_voltages(&sm0, &sm1)) {
17047 @@ -255,10 +243,9 @@
17048 return bad ? -1 : 0;
17049 }
17050
17051 -int tps6586x_init(int bus)
17052 +int tps6586x_init(struct udevice *dev)
17053 {
17054 - bus_num = bus;
17055 - inited = 1;
17056 + tps6586x_dev = dev;
17057
17058 return 0;
17059 }
17060 diff -ruN u-boot-2015.01-rc3/drivers/qe/qe.c u-boot/drivers/qe/qe.c
17061 --- u-boot-2015.01-rc3/drivers/qe/qe.c 2014-12-08 22:35:08.000000000 +0100
17062 +++ u-boot/drivers/qe/qe.c 2015-01-01 17:34:32.693496038 +0100
17063 @@ -13,6 +13,9 @@
17064 #include "asm/io.h"
17065 #include "linux/immap_qe.h"
17066 #include "qe.h"
17067 +#ifdef CONFIG_LS102XA
17068 +#include <asm/arch/immap_ls102xa.h>
17069 +#endif
17070
17071 #define MPC85xx_DEVDISR_QE_DISABLE 0x1
17072
17073 @@ -335,8 +338,12 @@
17074 size_t length;
17075 const struct qe_header *hdr;
17076 #ifdef CONFIG_DEEP_SLEEP
17077 +#ifdef CONFIG_LS102XA
17078 + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
17079 +#else
17080 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
17081 #endif
17082 +#endif
17083 if (!firmware) {
17084 printf("Invalid address\n");
17085 return -EINVAL;
17086 @@ -470,8 +477,12 @@
17087 size_t length;
17088 const struct qe_header *hdr;
17089 #ifdef CONFIG_DEEP_SLEEP
17090 +#ifdef CONFIG_LS102XA
17091 + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
17092 +#else
17093 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
17094 #endif
17095 +#endif
17096 if (!firmware) {
17097 printf("Invalid address\n");
17098 return -EINVAL;
17099 diff -ruN u-boot-2015.01-rc3/drivers/serial/Makefile u-boot/drivers/serial/Makefile
17100 --- u-boot-2015.01-rc3/drivers/serial/Makefile 2014-12-08 22:35:08.000000000 +0100
17101 +++ u-boot/drivers/serial/Makefile 2015-01-01 17:34:32.697495972 +0100
17102 @@ -43,7 +43,7 @@
17103 obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
17104 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
17105 obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
17106 -obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
17107 +obj-$(CONFIG_X86_SERIAL) += serial_x86.o
17108
17109 ifndef CONFIG_SPL_BUILD
17110 obj-$(CONFIG_USB_TTY) += usbtty.o
17111 diff -ruN u-boot-2015.01-rc3/drivers/serial/serial_coreboot.c u-boot/drivers/serial/serial_coreboot.c
17112 --- u-boot-2015.01-rc3/drivers/serial/serial_coreboot.c 2014-12-08 22:35:08.000000000 +0100
17113 +++ u-boot/drivers/serial/serial_coreboot.c 1970-01-01 01:00:00.000000000 +0100
17114 @@ -1,38 +0,0 @@
17115 -/*
17116 - * Copyright (c) 2014 Google, Inc
17117 - *
17118 - * SPDX-License-Identifier: GPL-2.0+
17119 - */
17120 -
17121 -#include <common.h>
17122 -#include <dm.h>
17123 -#include <ns16550.h>
17124 -#include <serial.h>
17125 -
17126 -static const struct udevice_id coreboot_serial_ids[] = {
17127 - { .compatible = "coreboot-uart" },
17128 - { }
17129 -};
17130 -
17131 -static int coreboot_serial_ofdata_to_platdata(struct udevice *dev)
17132 -{
17133 - struct ns16550_platdata *plat = dev_get_platdata(dev);
17134 - int ret;
17135 -
17136 - ret = ns16550_serial_ofdata_to_platdata(dev);
17137 - if (ret)
17138 - return ret;
17139 - plat->clock = 1843200;
17140 -
17141 - return 0;
17142 -}
17143 -U_BOOT_DRIVER(serial_ns16550) = {
17144 - .name = "serial_coreboot",
17145 - .id = UCLASS_SERIAL,
17146 - .of_match = coreboot_serial_ids,
17147 - .ofdata_to_platdata = coreboot_serial_ofdata_to_platdata,
17148 - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
17149 - .priv_auto_alloc_size = sizeof(struct NS16550),
17150 - .probe = ns16550_serial_probe,
17151 - .ops = &ns16550_serial_ops,
17152 -};
17153 diff -ruN u-boot-2015.01-rc3/drivers/serial/serial_pl01x.c u-boot/drivers/serial/serial_pl01x.c
17154 --- u-boot-2015.01-rc3/drivers/serial/serial_pl01x.c 2014-12-08 22:35:08.000000000 +0100
17155 +++ u-boot/drivers/serial/serial_pl01x.c 2015-01-01 17:34:32.697495972 +0100
17156 @@ -348,6 +348,7 @@
17157 .probe = pl01x_serial_probe,
17158 .ops = &pl01x_serial_ops,
17159 .flags = DM_FLAG_PRE_RELOC,
17160 + .priv_auto_alloc_size = sizeof(struct pl01x_priv),
17161 };
17162
17163 #endif
17164 diff -ruN u-boot-2015.01-rc3/drivers/serial/serial_x86.c u-boot/drivers/serial/serial_x86.c
17165 --- u-boot-2015.01-rc3/drivers/serial/serial_x86.c 1970-01-01 01:00:00.000000000 +0100
17166 +++ u-boot/drivers/serial/serial_x86.c 2015-01-01 17:34:32.697495972 +0100
17167 @@ -0,0 +1,38 @@
17168 +/*
17169 + * Copyright (c) 2014 Google, Inc
17170 + *
17171 + * SPDX-License-Identifier: GPL-2.0+
17172 + */
17173 +
17174 +#include <common.h>
17175 +#include <dm.h>
17176 +#include <ns16550.h>
17177 +#include <serial.h>
17178 +
17179 +static const struct udevice_id x86_serial_ids[] = {
17180 + { .compatible = "x86-uart" },
17181 + { }
17182 +};
17183 +
17184 +static int x86_serial_ofdata_to_platdata(struct udevice *dev)
17185 +{
17186 + struct ns16550_platdata *plat = dev_get_platdata(dev);
17187 + int ret;
17188 +
17189 + ret = ns16550_serial_ofdata_to_platdata(dev);
17190 + if (ret)
17191 + return ret;
17192 + plat->clock = 1843200;
17193 +
17194 + return 0;
17195 +}
17196 +U_BOOT_DRIVER(serial_ns16550) = {
17197 + .name = "serial_x86",
17198 + .id = UCLASS_SERIAL,
17199 + .of_match = x86_serial_ids,
17200 + .ofdata_to_platdata = x86_serial_ofdata_to_platdata,
17201 + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
17202 + .priv_auto_alloc_size = sizeof(struct NS16550),
17203 + .probe = ns16550_serial_probe,
17204 + .ops = &ns16550_serial_ops,
17205 +};
17206 diff -ruN u-boot-2015.01-rc3/drivers/spi/cadence_qspi_apb.c u-boot/drivers/spi/cadence_qspi_apb.c
17207 --- u-boot-2015.01-rc3/drivers/spi/cadence_qspi_apb.c 1970-01-01 01:00:00.000000000 +0100
17208 +++ u-boot/drivers/spi/cadence_qspi_apb.c 2015-01-01 17:34:32.701495908 +0100
17209 @@ -0,0 +1,898 @@
17210 +/*
17211 + * Copyright (C) 2012 Altera Corporation <www.altera.com>
17212 + * All rights reserved.
17213 + *
17214 + * Redistribution and use in source and binary forms, with or without
17215 + * modification, are permitted provided that the following conditions are met:
17216 + * - Redistributions of source code must retain the above copyright
17217 + * notice, this list of conditions and the following disclaimer.
17218 + * - Redistributions in binary form must reproduce the above copyright
17219 + * notice, this list of conditions and the following disclaimer in the
17220 + * documentation and/or other materials provided with the distribution.
17221 + * - Neither the name of the Altera Corporation nor the
17222 + * names of its contributors may be used to endorse or promote products
17223 + * derived from this software without specific prior written permission.
17224 + *
17225 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17226 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17227 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17228 + * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
17229 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
17230 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
17231 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
17232 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17233 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
17234 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17235 + */
17236 +
17237 +#include <common.h>
17238 +#include <asm/io.h>
17239 +#include <asm/errno.h>
17240 +#include "cadence_qspi.h"
17241 +
17242 +#define CQSPI_REG_POLL_US (1) /* 1us */
17243 +#define CQSPI_REG_RETRY (10000)
17244 +#define CQSPI_POLL_IDLE_RETRY (3)
17245 +
17246 +#define CQSPI_FIFO_WIDTH (4)
17247 +
17248 +/* Controller sram size in word */
17249 +#define CQSPI_REG_SRAM_SIZE_WORD (128)
17250 +#define CQSPI_REG_SRAM_RESV_WORDS (2)
17251 +#define CQSPI_REG_SRAM_PARTITION_WR (1)
17252 +#define CQSPI_REG_SRAM_PARTITION_RD \
17253 + (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
17254 +#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
17255 +
17256 +/* Transfer mode */
17257 +#define CQSPI_INST_TYPE_SINGLE (0)
17258 +#define CQSPI_INST_TYPE_DUAL (1)
17259 +#define CQSPI_INST_TYPE_QUAD (2)
17260 +
17261 +#define CQSPI_STIG_DATA_LEN_MAX (8)
17262 +#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF)
17263 +
17264 +#define CQSPI_DUMMY_CLKS_PER_BYTE (8)
17265 +#define CQSPI_DUMMY_BYTES_MAX (4)
17266 +
17267 +
17268 +#define CQSPI_REG_SRAM_FILL_THRESHOLD \
17269 + ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH)
17270 +/****************************************************************************
17271 + * Controller's configuration and status register (offset from QSPI_BASE)
17272 + ****************************************************************************/
17273 +#define CQSPI_REG_CONFIG 0x00
17274 +#define CQSPI_REG_CONFIG_CLK_POL_LSB 1
17275 +#define CQSPI_REG_CONFIG_CLK_PHA_LSB 2
17276 +#define CQSPI_REG_CONFIG_ENABLE_MASK (1 << 0)
17277 +#define CQSPI_REG_CONFIG_DIRECT_MASK (1 << 7)
17278 +#define CQSPI_REG_CONFIG_DECODE_MASK (1 << 9)
17279 +#define CQSPI_REG_CONFIG_XIP_IMM_MASK (1 << 18)
17280 +#define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
17281 +#define CQSPI_REG_CONFIG_BAUD_LSB 19
17282 +#define CQSPI_REG_CONFIG_IDLE_LSB 31
17283 +#define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
17284 +#define CQSPI_REG_CONFIG_BAUD_MASK 0xF
17285 +
17286 +#define CQSPI_REG_RD_INSTR 0x04
17287 +#define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
17288 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
17289 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
17290 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
17291 +#define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
17292 +#define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
17293 +#define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
17294 +#define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
17295 +#define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
17296 +#define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
17297 +
17298 +#define CQSPI_REG_WR_INSTR 0x08
17299 +#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
17300 +
17301 +#define CQSPI_REG_DELAY 0x0C
17302 +#define CQSPI_REG_DELAY_TSLCH_LSB 0
17303 +#define CQSPI_REG_DELAY_TCHSH_LSB 8
17304 +#define CQSPI_REG_DELAY_TSD2D_LSB 16
17305 +#define CQSPI_REG_DELAY_TSHSL_LSB 24
17306 +#define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
17307 +#define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
17308 +#define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
17309 +#define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
17310 +
17311 +#define CQSPI_READLCAPTURE 0x10
17312 +#define CQSPI_READLCAPTURE_BYPASS_LSB 0
17313 +#define CQSPI_READLCAPTURE_DELAY_LSB 1
17314 +#define CQSPI_READLCAPTURE_DELAY_MASK 0xF
17315 +
17316 +#define CQSPI_REG_SIZE 0x14
17317 +#define CQSPI_REG_SIZE_ADDRESS_LSB 0
17318 +#define CQSPI_REG_SIZE_PAGE_LSB 4
17319 +#define CQSPI_REG_SIZE_BLOCK_LSB 16
17320 +#define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
17321 +#define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
17322 +#define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
17323 +
17324 +#define CQSPI_REG_SRAMPARTITION 0x18
17325 +#define CQSPI_REG_INDIRECTTRIGGER 0x1C
17326 +
17327 +#define CQSPI_REG_REMAP 0x24
17328 +#define CQSPI_REG_MODE_BIT 0x28
17329 +
17330 +#define CQSPI_REG_SDRAMLEVEL 0x2C
17331 +#define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
17332 +#define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
17333 +#define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
17334 +#define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
17335 +
17336 +#define CQSPI_REG_IRQSTATUS 0x40
17337 +#define CQSPI_REG_IRQMASK 0x44
17338 +
17339 +#define CQSPI_REG_INDIRECTRD 0x60
17340 +#define CQSPI_REG_INDIRECTRD_START_MASK (1 << 0)
17341 +#define CQSPI_REG_INDIRECTRD_CANCEL_MASK (1 << 1)
17342 +#define CQSPI_REG_INDIRECTRD_INPROGRESS_MASK (1 << 2)
17343 +#define CQSPI_REG_INDIRECTRD_DONE_MASK (1 << 5)
17344 +
17345 +#define CQSPI_REG_INDIRECTRDWATERMARK 0x64
17346 +#define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
17347 +#define CQSPI_REG_INDIRECTRDBYTES 0x6C
17348 +
17349 +#define CQSPI_REG_CMDCTRL 0x90
17350 +#define CQSPI_REG_CMDCTRL_EXECUTE_MASK (1 << 0)
17351 +#define CQSPI_REG_CMDCTRL_INPROGRESS_MASK (1 << 1)
17352 +#define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
17353 +#define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
17354 +#define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
17355 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
17356 +#define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
17357 +#define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
17358 +#define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
17359 +#define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
17360 +#define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
17361 +#define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
17362 +#define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
17363 +#define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
17364 +#define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
17365 +
17366 +#define CQSPI_REG_INDIRECTWR 0x70
17367 +#define CQSPI_REG_INDIRECTWR_START_MASK (1 << 0)
17368 +#define CQSPI_REG_INDIRECTWR_CANCEL_MASK (1 << 1)
17369 +#define CQSPI_REG_INDIRECTWR_INPROGRESS_MASK (1 << 2)
17370 +#define CQSPI_REG_INDIRECTWR_DONE_MASK (1 << 5)
17371 +
17372 +#define CQSPI_REG_INDIRECTWRWATERMARK 0x74
17373 +#define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
17374 +#define CQSPI_REG_INDIRECTWRBYTES 0x7C
17375 +
17376 +#define CQSPI_REG_CMDADDRESS 0x94
17377 +#define CQSPI_REG_CMDREADDATALOWER 0xA0
17378 +#define CQSPI_REG_CMDREADDATAUPPER 0xA4
17379 +#define CQSPI_REG_CMDWRITEDATALOWER 0xA8
17380 +#define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
17381 +
17382 +#define CQSPI_REG_IS_IDLE(base) \
17383 + ((readl(base + CQSPI_REG_CONFIG) >> \
17384 + CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
17385 +
17386 +#define CQSPI_CAL_DELAY(tdelay_ns, tref_ns, tsclk_ns) \
17387 + ((((tdelay_ns) - (tsclk_ns)) / (tref_ns)))
17388 +
17389 +#define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
17390 + (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
17391 + CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
17392 +
17393 +#define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
17394 + (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
17395 + CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
17396 +
17397 +static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
17398 + unsigned int addr_width)
17399 +{
17400 + unsigned int addr;
17401 +
17402 + addr = (addr_buf[0] << 16) | (addr_buf[1] << 8) | addr_buf[2];
17403 +
17404 + if (addr_width == 4)
17405 + addr = (addr << 8) | addr_buf[3];
17406 +
17407 + return addr;
17408 +}
17409 +
17410 +static void cadence_qspi_apb_read_fifo_data(void *dest,
17411 + const void *src_ahb_addr, unsigned int bytes)
17412 +{
17413 + unsigned int temp;
17414 + int remaining = bytes;
17415 + unsigned int *dest_ptr = (unsigned int *)dest;
17416 + unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
17417 +
17418 + while (remaining > 0) {
17419 + if (remaining >= CQSPI_FIFO_WIDTH) {
17420 + *dest_ptr = readl(src_ptr);
17421 + remaining -= CQSPI_FIFO_WIDTH;
17422 + } else {
17423 + /* dangling bytes */
17424 + temp = readl(src_ptr);
17425 + memcpy(dest_ptr, &temp, remaining);
17426 + break;
17427 + }
17428 + dest_ptr++;
17429 + }
17430 +
17431 + return;
17432 +}
17433 +
17434 +static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
17435 + const void *src, unsigned int bytes)
17436 +{
17437 + unsigned int temp;
17438 + int remaining = bytes;
17439 + unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
17440 + unsigned int *src_ptr = (unsigned int *)src;
17441 +
17442 + while (remaining > 0) {
17443 + if (remaining >= CQSPI_FIFO_WIDTH) {
17444 + writel(*src_ptr, dest_ptr);
17445 + remaining -= sizeof(unsigned int);
17446 + } else {
17447 + /* dangling bytes */
17448 + memcpy(&temp, src_ptr, remaining);
17449 + writel(temp, dest_ptr);
17450 + break;
17451 + }
17452 + src_ptr++;
17453 + }
17454 +
17455 + return;
17456 +}
17457 +
17458 +/* Read from SRAM FIFO with polling SRAM fill level. */
17459 +static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
17460 + const void *src_addr, unsigned int num_bytes)
17461 +{
17462 + unsigned int remaining = num_bytes;
17463 + unsigned int retry;
17464 + unsigned int sram_level = 0;
17465 + unsigned char *dest = (unsigned char *)dest_addr;
17466 +
17467 + while (remaining > 0) {
17468 + retry = CQSPI_REG_RETRY;
17469 + while (retry--) {
17470 + sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
17471 + if (sram_level)
17472 + break;
17473 + udelay(1);
17474 + }
17475 +
17476 + if (!retry) {
17477 + printf("QSPI: No receive data after polling for %d times\n",
17478 + CQSPI_REG_RETRY);
17479 + return -1;
17480 + }
17481 +
17482 + sram_level *= CQSPI_FIFO_WIDTH;
17483 + sram_level = sram_level > remaining ? remaining : sram_level;
17484 +
17485 + /* Read data from FIFO. */
17486 + cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
17487 + dest += sram_level;
17488 + remaining -= sram_level;
17489 + udelay(1);
17490 + }
17491 + return 0;
17492 +}
17493 +
17494 +/* Write to SRAM FIFO with polling SRAM fill level. */
17495 +static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
17496 + const void *src_addr, unsigned int num_bytes)
17497 +{
17498 + const void *reg_base = plat->regbase;
17499 + void *dest_addr = plat->ahbbase;
17500 + unsigned int retry = CQSPI_REG_RETRY;
17501 + unsigned int sram_level;
17502 + unsigned int wr_bytes;
17503 + unsigned char *src = (unsigned char *)src_addr;
17504 + int remaining = num_bytes;
17505 + unsigned int page_size = plat->page_size;
17506 + unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
17507 +
17508 + while (remaining > 0) {
17509 + retry = CQSPI_REG_RETRY;
17510 + while (retry--) {
17511 + sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
17512 + if (sram_level <= sram_threshold_words)
17513 + break;
17514 + }
17515 + if (!retry) {
17516 + printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
17517 + sram_level, sram_threshold_words);
17518 + return -1;
17519 + }
17520 + /* Write a page or remaining bytes. */
17521 + wr_bytes = (remaining > page_size) ?
17522 + page_size : remaining;
17523 +
17524 + cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
17525 + src += wr_bytes;
17526 + remaining -= wr_bytes;
17527 + }
17528 +
17529 + return 0;
17530 +}
17531 +
17532 +void cadence_qspi_apb_controller_enable(void *reg_base)
17533 +{
17534 + unsigned int reg;
17535 + reg = readl(reg_base + CQSPI_REG_CONFIG);
17536 + reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
17537 + writel(reg, reg_base + CQSPI_REG_CONFIG);
17538 + return;
17539 +}
17540 +
17541 +void cadence_qspi_apb_controller_disable(void *reg_base)
17542 +{
17543 + unsigned int reg;
17544 + reg = readl(reg_base + CQSPI_REG_CONFIG);
17545 + reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK;
17546 + writel(reg, reg_base + CQSPI_REG_CONFIG);
17547 + return;
17548 +}
17549 +
17550 +/* Return 1 if idle, otherwise return 0 (busy). */
17551 +static unsigned int cadence_qspi_wait_idle(void *reg_base)
17552 +{
17553 + unsigned int start, count = 0;
17554 + /* timeout in unit of ms */
17555 + unsigned int timeout = 5000;
17556 +
17557 + start = get_timer(0);
17558 + for ( ; get_timer(start) < timeout ; ) {
17559 + if (CQSPI_REG_IS_IDLE(reg_base))
17560 + count++;
17561 + else
17562 + count = 0;
17563 + /*
17564 + * Ensure the QSPI controller is in true idle state after
17565 + * reading back the same idle status consecutively
17566 + */
17567 + if (count >= CQSPI_POLL_IDLE_RETRY)
17568 + return 1;
17569 + }
17570 +
17571 + /* Timeout, still in busy mode. */
17572 + printf("QSPI: QSPI is still busy after poll for %d times.\n",
17573 + CQSPI_REG_RETRY);
17574 + return 0;
17575 +}
17576 +
17577 +void cadence_qspi_apb_readdata_capture(void *reg_base,
17578 + unsigned int bypass, unsigned int delay)
17579 +{
17580 + unsigned int reg;
17581 + cadence_qspi_apb_controller_disable(reg_base);
17582 +
17583 + reg = readl(reg_base + CQSPI_READLCAPTURE);
17584 +
17585 + if (bypass)
17586 + reg |= (1 << CQSPI_READLCAPTURE_BYPASS_LSB);
17587 + else
17588 + reg &= ~(1 << CQSPI_READLCAPTURE_BYPASS_LSB);
17589 +
17590 + reg &= ~(CQSPI_READLCAPTURE_DELAY_MASK
17591 + << CQSPI_READLCAPTURE_DELAY_LSB);
17592 +
17593 + reg |= ((delay & CQSPI_READLCAPTURE_DELAY_MASK)
17594 + << CQSPI_READLCAPTURE_DELAY_LSB);
17595 +
17596 + writel(reg, reg_base + CQSPI_READLCAPTURE);
17597 +
17598 + cadence_qspi_apb_controller_enable(reg_base);
17599 + return;
17600 +}
17601 +
17602 +void cadence_qspi_apb_config_baudrate_div(void *reg_base,
17603 + unsigned int ref_clk_hz, unsigned int sclk_hz)
17604 +{
17605 + unsigned int reg;
17606 + unsigned int div;
17607 +
17608 + cadence_qspi_apb_controller_disable(reg_base);
17609 + reg = readl(reg_base + CQSPI_REG_CONFIG);
17610 + reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
17611 +
17612 + div = ref_clk_hz / sclk_hz;
17613 +
17614 + if (div > 32)
17615 + div = 32;
17616 +
17617 + /* Check if even number. */
17618 + if ((div & 1)) {
17619 + div = (div / 2);
17620 + } else {
17621 + if (ref_clk_hz % sclk_hz)
17622 + /* ensure generated SCLK doesn't exceed user
17623 + specified sclk_hz */
17624 + div = (div / 2);
17625 + else
17626 + div = (div / 2) - 1;
17627 + }
17628 +
17629 + debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
17630 + ref_clk_hz, sclk_hz, div);
17631 +
17632 + div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
17633 + reg |= div;
17634 + writel(reg, reg_base + CQSPI_REG_CONFIG);
17635 +
17636 + cadence_qspi_apb_controller_enable(reg_base);
17637 + return;
17638 +}
17639 +
17640 +void cadence_qspi_apb_set_clk_mode(void *reg_base,
17641 + unsigned int clk_pol, unsigned int clk_pha)
17642 +{
17643 + unsigned int reg;
17644 +
17645 + cadence_qspi_apb_controller_disable(reg_base);
17646 + reg = readl(reg_base + CQSPI_REG_CONFIG);
17647 + reg &= ~(1 <<
17648 + (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB));
17649 +
17650 + reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB);
17651 + reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);
17652 +
17653 + writel(reg, reg_base + CQSPI_REG_CONFIG);
17654 +
17655 + cadence_qspi_apb_controller_enable(reg_base);
17656 + return;
17657 +}
17658 +
17659 +void cadence_qspi_apb_chipselect(void *reg_base,
17660 + unsigned int chip_select, unsigned int decoder_enable)
17661 +{
17662 + unsigned int reg;
17663 +
17664 + cadence_qspi_apb_controller_disable(reg_base);
17665 +
17666 + debug("%s : chipselect %d decode %d\n", __func__, chip_select,
17667 + decoder_enable);
17668 +
17669 + reg = readl(reg_base + CQSPI_REG_CONFIG);
17670 + /* docoder */
17671 + if (decoder_enable) {
17672 + reg |= CQSPI_REG_CONFIG_DECODE_MASK;
17673 + } else {
17674 + reg &= ~CQSPI_REG_CONFIG_DECODE_MASK;
17675 + /* Convert CS if without decoder.
17676 + * CS0 to 4b'1110
17677 + * CS1 to 4b'1101
17678 + * CS2 to 4b'1011
17679 + * CS3 to 4b'0111
17680 + */
17681 + chip_select = 0xF & ~(1 << chip_select);
17682 + }
17683 +
17684 + reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
17685 + << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
17686 + reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
17687 + << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
17688 + writel(reg, reg_base + CQSPI_REG_CONFIG);
17689 +
17690 + cadence_qspi_apb_controller_enable(reg_base);
17691 + return;
17692 +}
17693 +
17694 +void cadence_qspi_apb_delay(void *reg_base,
17695 + unsigned int ref_clk, unsigned int sclk_hz,
17696 + unsigned int tshsl_ns, unsigned int tsd2d_ns,
17697 + unsigned int tchsh_ns, unsigned int tslch_ns)
17698 +{
17699 + unsigned int ref_clk_ns;
17700 + unsigned int sclk_ns;
17701 + unsigned int tshsl, tchsh, tslch, tsd2d;
17702 + unsigned int reg;
17703 +
17704 + cadence_qspi_apb_controller_disable(reg_base);
17705 +
17706 + /* Convert to ns. */
17707 + ref_clk_ns = (1000000000) / ref_clk;
17708 +
17709 + /* Convert to ns. */
17710 + sclk_ns = (1000000000) / sclk_hz;
17711 +
17712 + /* Plus 1 to round up 1 clock cycle. */
17713 + tshsl = CQSPI_CAL_DELAY(tshsl_ns, ref_clk_ns, sclk_ns) + 1;
17714 + tchsh = CQSPI_CAL_DELAY(tchsh_ns, ref_clk_ns, sclk_ns) + 1;
17715 + tslch = CQSPI_CAL_DELAY(tslch_ns, ref_clk_ns, sclk_ns) + 1;
17716 + tsd2d = CQSPI_CAL_DELAY(tsd2d_ns, ref_clk_ns, sclk_ns) + 1;
17717 +
17718 + reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
17719 + << CQSPI_REG_DELAY_TSHSL_LSB);
17720 + reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
17721 + << CQSPI_REG_DELAY_TCHSH_LSB);
17722 + reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
17723 + << CQSPI_REG_DELAY_TSLCH_LSB);
17724 + reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
17725 + << CQSPI_REG_DELAY_TSD2D_LSB);
17726 + writel(reg, reg_base + CQSPI_REG_DELAY);
17727 +
17728 + cadence_qspi_apb_controller_enable(reg_base);
17729 + return;
17730 +}
17731 +
17732 +void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
17733 +{
17734 + unsigned reg;
17735 +
17736 + cadence_qspi_apb_controller_disable(plat->regbase);
17737 +
17738 + /* Configure the device size and address bytes */
17739 + reg = readl(plat->regbase + CQSPI_REG_SIZE);
17740 + /* Clear the previous value */
17741 + reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
17742 + reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
17743 + reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
17744 + reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
17745 + writel(reg, plat->regbase + CQSPI_REG_SIZE);
17746 +
17747 + /* Configure the remap address register, no remap */
17748 + writel(0, plat->regbase + CQSPI_REG_REMAP);
17749 +
17750 + /* Disable all interrupts */
17751 + writel(0, plat->regbase + CQSPI_REG_IRQMASK);
17752 +
17753 + cadence_qspi_apb_controller_enable(plat->regbase);
17754 + return;
17755 +}
17756 +
17757 +static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
17758 + unsigned int reg)
17759 +{
17760 + unsigned int retry = CQSPI_REG_RETRY;
17761 +
17762 + /* Write the CMDCTRL without start execution. */
17763 + writel(reg, reg_base + CQSPI_REG_CMDCTRL);
17764 + /* Start execute */
17765 + reg |= CQSPI_REG_CMDCTRL_EXECUTE_MASK;
17766 + writel(reg, reg_base + CQSPI_REG_CMDCTRL);
17767 +
17768 + while (retry--) {
17769 + reg = readl(reg_base + CQSPI_REG_CMDCTRL);
17770 + if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS_MASK) == 0)
17771 + break;
17772 + udelay(1);
17773 + }
17774 +
17775 + if (!retry) {
17776 + printf("QSPI: flash command execution timeout\n");
17777 + return -EIO;
17778 + }
17779 +
17780 + /* Polling QSPI idle status. */
17781 + if (!cadence_qspi_wait_idle(reg_base))
17782 + return -EIO;
17783 +
17784 + return 0;
17785 +}
17786 +
17787 +/* For command RDID, RDSR. */
17788 +int cadence_qspi_apb_command_read(void *reg_base,
17789 + unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen,
17790 + u8 *rxbuf)
17791 +{
17792 + unsigned int reg;
17793 + unsigned int read_len;
17794 + int status;
17795 +
17796 + if (!cmdlen || rxlen > CQSPI_STIG_DATA_LEN_MAX || rxbuf == NULL) {
17797 + printf("QSPI: Invalid input arguments cmdlen %d rxlen %d\n",
17798 + cmdlen, rxlen);
17799 + return -EINVAL;
17800 + }
17801 +
17802 + reg = cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
17803 +
17804 + reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
17805 +
17806 + /* 0 means 1 byte. */
17807 + reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
17808 + << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
17809 + status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
17810 + if (status != 0)
17811 + return status;
17812 +
17813 + reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
17814 +
17815 + /* Put the read value into rx_buf */
17816 + read_len = (rxlen > 4) ? 4 : rxlen;
17817 + memcpy(rxbuf, &reg, read_len);
17818 + rxbuf += read_len;
17819 +
17820 + if (rxlen > 4) {
17821 + reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
17822 +
17823 + read_len = rxlen - read_len;
17824 + memcpy(rxbuf, &reg, read_len);
17825 + }
17826 + return 0;
17827 +}
17828 +
17829 +/* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
17830 +int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,
17831 + const u8 *cmdbuf, unsigned int txlen, const u8 *txbuf)
17832 +{
17833 + unsigned int reg = 0;
17834 + unsigned int addr_value;
17835 + unsigned int wr_data;
17836 + unsigned int wr_len;
17837 +
17838 + if (!cmdlen || cmdlen > 5 || txlen > 8 || cmdbuf == NULL) {
17839 + printf("QSPI: Invalid input arguments cmdlen %d txlen %d\n",
17840 + cmdlen, txlen);
17841 + return -EINVAL;
17842 + }
17843 +
17844 + reg |= cmdbuf[0] << CQSPI_REG_CMDCTRL_OPCODE_LSB;
17845 +
17846 + if (cmdlen == 4 || cmdlen == 5) {
17847 + /* Command with address */
17848 + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB);
17849 + /* Number of bytes to write. */
17850 + reg |= ((cmdlen - 2) & CQSPI_REG_CMDCTRL_ADD_BYTES_MASK)
17851 + << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB;
17852 + /* Get address */
17853 + addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1],
17854 + cmdlen >= 5 ? 4 : 3);
17855 +
17856 + writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);
17857 + }
17858 +
17859 + if (txlen) {
17860 + /* writing data = yes */
17861 + reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
17862 + reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
17863 + << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
17864 +
17865 + wr_len = txlen > 4 ? 4 : txlen;
17866 + memcpy(&wr_data, txbuf, wr_len);
17867 + writel(wr_data, reg_base +
17868 + CQSPI_REG_CMDWRITEDATALOWER);
17869 +
17870 + if (txlen > 4) {
17871 + txbuf += wr_len;
17872 + wr_len = txlen - wr_len;
17873 + memcpy(&wr_data, txbuf, wr_len);
17874 + writel(wr_data, reg_base +
17875 + CQSPI_REG_CMDWRITEDATAUPPER);
17876 + }
17877 + }
17878 +
17879 + /* Execute the command */
17880 + return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
17881 +}
17882 +
17883 +/* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
17884 +int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
17885 + unsigned int cmdlen, const u8 *cmdbuf)
17886 +{
17887 + unsigned int reg;
17888 + unsigned int rd_reg;
17889 + unsigned int addr_value;
17890 + unsigned int dummy_clk;
17891 + unsigned int dummy_bytes;
17892 + unsigned int addr_bytes;
17893 +
17894 + /*
17895 + * Identify addr_byte. All NOR flash device drivers are using fast read
17896 + * which always expecting 1 dummy byte, 1 cmd byte and 3/4 addr byte.
17897 + * With that, the length is in value of 5 or 6. Only FRAM chip from
17898 + * ramtron using normal read (which won't need dummy byte).
17899 + * Unlikely NOR flash using normal read due to performance issue.
17900 + */
17901 + if (cmdlen >= 5)
17902 + /* to cater fast read where cmd + addr + dummy */
17903 + addr_bytes = cmdlen - 2;
17904 + else
17905 + /* for normal read (only ramtron as of now) */
17906 + addr_bytes = cmdlen - 1;
17907 +
17908 + /* Setup the indirect trigger address */
17909 + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
17910 + plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
17911 +
17912 + /* Configure SRAM partition for read. */
17913 + writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
17914 + CQSPI_REG_SRAMPARTITION);
17915 +
17916 + /* Configure the opcode */
17917 + rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
17918 +
17919 +#if (CONFIG_SPI_FLASH_QUAD == 1)
17920 + /* Instruction and address at DQ0, data at DQ0-3. */
17921 + rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
17922 +#endif
17923 +
17924 + /* Get address */
17925 + addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
17926 + writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
17927 +
17928 + /* The remaining lenght is dummy bytes. */
17929 + dummy_bytes = cmdlen - addr_bytes - 1;
17930 + if (dummy_bytes) {
17931 + if (dummy_bytes > CQSPI_DUMMY_BYTES_MAX)
17932 + dummy_bytes = CQSPI_DUMMY_BYTES_MAX;
17933 +
17934 + rd_reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
17935 +#if defined(CONFIG_SPL_SPI_XIP) && defined(CONFIG_SPL_BUILD)
17936 + writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT);
17937 +#else
17938 + writel(0xFF, plat->regbase + CQSPI_REG_MODE_BIT);
17939 +#endif
17940 +
17941 + /* Convert to clock cycles. */
17942 + dummy_clk = dummy_bytes * CQSPI_DUMMY_CLKS_PER_BYTE;
17943 + /* Need to minus the mode byte (8 clocks). */
17944 + dummy_clk -= CQSPI_DUMMY_CLKS_PER_BYTE;
17945 +
17946 + if (dummy_clk)
17947 + rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
17948 + << CQSPI_REG_RD_INSTR_DUMMY_LSB;
17949 + }
17950 +
17951 + writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
17952 +
17953 + /* set device size */
17954 + reg = readl(plat->regbase + CQSPI_REG_SIZE);
17955 + reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
17956 + reg |= (addr_bytes - 1);
17957 + writel(reg, plat->regbase + CQSPI_REG_SIZE);
17958 + return 0;
17959 +}
17960 +
17961 +int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
17962 + unsigned int rxlen, u8 *rxbuf)
17963 +{
17964 + unsigned int reg;
17965 +
17966 + writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
17967 +
17968 + /* Start the indirect read transfer */
17969 + writel(CQSPI_REG_INDIRECTRD_START_MASK,
17970 + plat->regbase + CQSPI_REG_INDIRECTRD);
17971 +
17972 + if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
17973 + (const void *)plat->ahbbase, rxlen))
17974 + goto failrd;
17975 +
17976 + /* Check flash indirect controller */
17977 + reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
17978 + if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
17979 + reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
17980 + printf("QSPI: indirect completion status error with reg 0x%08x\n",
17981 + reg);
17982 + goto failrd;
17983 + }
17984 +
17985 + /* Clear indirect completion status */
17986 + writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
17987 + plat->regbase + CQSPI_REG_INDIRECTRD);
17988 + return 0;
17989 +
17990 +failrd:
17991 + /* Cancel the indirect read */
17992 + writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
17993 + plat->regbase + CQSPI_REG_INDIRECTRD);
17994 + return -1;
17995 +}
17996 +
17997 +/* Opcode + Address (3/4 bytes) */
17998 +int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
17999 + unsigned int cmdlen, const u8 *cmdbuf)
18000 +{
18001 + unsigned int reg;
18002 + unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
18003 +
18004 + if (cmdlen < 4 || cmdbuf == NULL) {
18005 + printf("QSPI: iInvalid input argument, len %d cmdbuf 0x%08x\n",
18006 + cmdlen, (unsigned int)cmdbuf);
18007 + return -EINVAL;
18008 + }
18009 + /* Setup the indirect trigger address */
18010 + writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
18011 + plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
18012 +
18013 + writel(CQSPI_REG_SRAM_PARTITION_WR,
18014 + plat->regbase + CQSPI_REG_SRAMPARTITION);
18015 +
18016 + /* Configure the opcode */
18017 + reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
18018 + writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
18019 +
18020 + /* Setup write address. */
18021 + reg = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes);
18022 + writel(reg, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
18023 +
18024 + reg = readl(plat->regbase + CQSPI_REG_SIZE);
18025 + reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
18026 + reg |= (addr_bytes - 1);
18027 + writel(reg, plat->regbase + CQSPI_REG_SIZE);
18028 + return 0;
18029 +}
18030 +
18031 +int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
18032 + unsigned int txlen, const u8 *txbuf)
18033 +{
18034 + unsigned int reg = 0;
18035 + unsigned int retry;
18036 +
18037 + /* Configure the indirect read transfer bytes */
18038 + writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
18039 +
18040 + /* Start the indirect write transfer */
18041 + writel(CQSPI_REG_INDIRECTWR_START_MASK,
18042 + plat->regbase + CQSPI_REG_INDIRECTWR);
18043 +
18044 + if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
18045 + goto failwr;
18046 +
18047 + /* Wait until last write is completed (FIFO empty) */
18048 + retry = CQSPI_REG_RETRY;
18049 + while (retry--) {
18050 + reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
18051 + if (reg == 0)
18052 + break;
18053 +
18054 + udelay(1);
18055 + }
18056 +
18057 + if (reg != 0) {
18058 + printf("QSPI: timeout for indirect write\n");
18059 + goto failwr;
18060 + }
18061 +
18062 + /* Check flash indirect controller status */
18063 + retry = CQSPI_REG_RETRY;
18064 + while (retry--) {
18065 + reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
18066 + if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
18067 + break;
18068 + udelay(1);
18069 + }
18070 +
18071 + if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
18072 + printf("QSPI: indirect completion status error with reg 0x%08x\n",
18073 + reg);
18074 + goto failwr;
18075 + }
18076 +
18077 + /* Clear indirect completion status */
18078 + writel(CQSPI_REG_INDIRECTWR_DONE_MASK,
18079 + plat->regbase + CQSPI_REG_INDIRECTWR);
18080 + return 0;
18081 +
18082 +failwr:
18083 + /* Cancel the indirect write */
18084 + writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
18085 + plat->regbase + CQSPI_REG_INDIRECTWR);
18086 + return -1;
18087 +}
18088 +
18089 +void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
18090 +{
18091 + unsigned int reg;
18092 +
18093 + /* enter XiP mode immediately and enable direct mode */
18094 + reg = readl(reg_base + CQSPI_REG_CONFIG);
18095 + reg |= CQSPI_REG_CONFIG_ENABLE_MASK;
18096 + reg |= CQSPI_REG_CONFIG_DIRECT_MASK;
18097 + reg |= CQSPI_REG_CONFIG_XIP_IMM_MASK;
18098 + writel(reg, reg_base + CQSPI_REG_CONFIG);
18099 +
18100 + /* keep the XiP mode */
18101 + writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
18102 +
18103 + /* Enable mode bit at devrd */
18104 + reg = readl(reg_base + CQSPI_REG_RD_INSTR);
18105 + reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
18106 + writel(reg, reg_base + CQSPI_REG_RD_INSTR);
18107 +}
18108 diff -ruN u-boot-2015.01-rc3/drivers/spi/cadence_qspi.c u-boot/drivers/spi/cadence_qspi.c
18109 --- u-boot-2015.01-rc3/drivers/spi/cadence_qspi.c 1970-01-01 01:00:00.000000000 +0100
18110 +++ u-boot/drivers/spi/cadence_qspi.c 2015-01-01 17:34:32.701495908 +0100
18111 @@ -0,0 +1,345 @@
18112 +/*
18113 + * Copyright (C) 2012
18114 + * Altera Corporation <www.altera.com>
18115 + *
18116 + * SPDX-License-Identifier: GPL-2.0+
18117 + */
18118 +
18119 +#include <common.h>
18120 +#include <dm.h>
18121 +#include <fdtdec.h>
18122 +#include <malloc.h>
18123 +#include <spi.h>
18124 +#include <asm/errno.h>
18125 +#include "cadence_qspi.h"
18126 +
18127 +#define CQSPI_STIG_READ 0
18128 +#define CQSPI_STIG_WRITE 1
18129 +#define CQSPI_INDIRECT_READ 2
18130 +#define CQSPI_INDIRECT_WRITE 3
18131 +
18132 +DECLARE_GLOBAL_DATA_PTR;
18133 +
18134 +static int cadence_spi_write_speed(struct udevice *bus, uint hz)
18135 +{
18136 + struct cadence_spi_platdata *plat = bus->platdata;
18137 + struct cadence_spi_priv *priv = dev_get_priv(bus);
18138 +
18139 + cadence_qspi_apb_config_baudrate_div(priv->regbase,
18140 + CONFIG_CQSPI_REF_CLK, hz);
18141 +
18142 + /* Reconfigure delay timing if speed is changed. */
18143 + cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
18144 + plat->tshsl_ns, plat->tsd2d_ns,
18145 + plat->tchsh_ns, plat->tslch_ns);
18146 +
18147 + return 0;
18148 +}
18149 +
18150 +/* Calibration sequence to determine the read data capture delay register */
18151 +static int spi_calibration(struct udevice *bus)
18152 +{
18153 + struct cadence_spi_platdata *plat = bus->platdata;
18154 + struct cadence_spi_priv *priv = dev_get_priv(bus);
18155 + void *base = priv->regbase;
18156 + u8 opcode_rdid = 0x9F;
18157 + unsigned int idcode = 0, temp = 0;
18158 + int err = 0, i, range_lo = -1, range_hi = -1;
18159 +
18160 + /* start with slowest clock (1 MHz) */
18161 + cadence_spi_write_speed(bus, 1000000);
18162 +
18163 + /* configure the read data capture delay register to 0 */
18164 + cadence_qspi_apb_readdata_capture(base, 1, 0);
18165 +
18166 + /* Enable QSPI */
18167 + cadence_qspi_apb_controller_enable(base);
18168 +
18169 + /* read the ID which will be our golden value */
18170 + err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
18171 + 3, (u8 *)&idcode);
18172 + if (err) {
18173 + puts("SF: Calibration failed (read)\n");
18174 + return err;
18175 + }
18176 +
18177 + /* use back the intended clock and find low range */
18178 + cadence_spi_write_speed(bus, plat->max_hz);
18179 + for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
18180 + /* Disable QSPI */
18181 + cadence_qspi_apb_controller_disable(base);
18182 +
18183 + /* reconfigure the read data capture delay register */
18184 + cadence_qspi_apb_readdata_capture(base, 1, i);
18185 +
18186 + /* Enable back QSPI */
18187 + cadence_qspi_apb_controller_enable(base);
18188 +
18189 + /* issue a RDID to get the ID value */
18190 + err = cadence_qspi_apb_command_read(base, 1, &opcode_rdid,
18191 + 3, (u8 *)&temp);
18192 + if (err) {
18193 + puts("SF: Calibration failed (read)\n");
18194 + return err;
18195 + }
18196 +
18197 + /* search for range lo */
18198 + if (range_lo == -1 && temp == idcode) {
18199 + range_lo = i;
18200 + continue;
18201 + }
18202 +
18203 + /* search for range hi */
18204 + if (range_lo != -1 && temp != idcode) {
18205 + range_hi = i - 1;
18206 + break;
18207 + }
18208 + range_hi = i;
18209 + }
18210 +
18211 + if (range_lo == -1) {
18212 + puts("SF: Calibration failed (low range)\n");
18213 + return err;
18214 + }
18215 +
18216 + /* Disable QSPI for subsequent initialization */
18217 + cadence_qspi_apb_controller_disable(base);
18218 +
18219 + /* configure the final value for read data capture delay register */
18220 + cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
18221 + debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
18222 + (range_hi + range_lo) / 2, range_lo, range_hi);
18223 +
18224 + /* just to ensure we do once only when speed or chip select change */
18225 + priv->qspi_calibrated_hz = plat->max_hz;
18226 + priv->qspi_calibrated_cs = spi_chip_select(bus);
18227 +
18228 + return 0;
18229 +}
18230 +
18231 +static int cadence_spi_set_speed(struct udevice *bus, uint hz)
18232 +{
18233 + struct cadence_spi_platdata *plat = bus->platdata;
18234 + struct cadence_spi_priv *priv = dev_get_priv(bus);
18235 + int err;
18236 +
18237 + /* Disable QSPI */
18238 + cadence_qspi_apb_controller_disable(priv->regbase);
18239 +
18240 + cadence_spi_write_speed(bus, hz);
18241 +
18242 + /* Calibration required for different SCLK speed or chip select */
18243 + if (priv->qspi_calibrated_hz != plat->max_hz ||
18244 + priv->qspi_calibrated_cs != spi_chip_select(bus)) {
18245 + err = spi_calibration(bus);
18246 + if (err)
18247 + return err;
18248 + }
18249 +
18250 + /* Enable QSPI */
18251 + cadence_qspi_apb_controller_enable(priv->regbase);
18252 +
18253 + debug("%s: speed=%d\n", __func__, hz);
18254 +
18255 + return 0;
18256 +}
18257 +
18258 +static int cadence_spi_probe(struct udevice *bus)
18259 +{
18260 + struct cadence_spi_platdata *plat = bus->platdata;
18261 + struct cadence_spi_priv *priv = dev_get_priv(bus);
18262 +
18263 + priv->regbase = plat->regbase;
18264 + priv->ahbbase = plat->ahbbase;
18265 +
18266 + if (!priv->qspi_is_init) {
18267 + cadence_qspi_apb_controller_init(plat);
18268 + priv->qspi_is_init = 1;
18269 + }
18270 +
18271 + return 0;
18272 +}
18273 +
18274 +static int cadence_spi_set_mode(struct udevice *bus, uint mode)
18275 +{
18276 + struct cadence_spi_priv *priv = dev_get_priv(bus);
18277 + unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0;
18278 + unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0;
18279 +
18280 + /* Disable QSPI */
18281 + cadence_qspi_apb_controller_disable(priv->regbase);
18282 +
18283 + /* Set SPI mode */
18284 + cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha);
18285 +
18286 + /* Enable QSPI */
18287 + cadence_qspi_apb_controller_enable(priv->regbase);
18288 +
18289 + return 0;
18290 +}
18291 +
18292 +static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
18293 + const void *dout, void *din, unsigned long flags)
18294 +{
18295 + struct udevice *bus = dev->parent;
18296 + struct cadence_spi_platdata *plat = bus->platdata;
18297 + struct cadence_spi_priv *priv = dev_get_priv(bus);
18298 + void *base = priv->regbase;
18299 + u8 *cmd_buf = priv->cmd_buf;
18300 + size_t data_bytes;
18301 + int err = 0;
18302 + u32 mode = CQSPI_STIG_WRITE;
18303 +
18304 + if (flags & SPI_XFER_BEGIN) {
18305 + /* copy command to local buffer */
18306 + priv->cmd_len = bitlen / 8;
18307 + memcpy(cmd_buf, dout, priv->cmd_len);
18308 + }
18309 +
18310 + if (flags == (SPI_XFER_BEGIN | SPI_XFER_END)) {
18311 + /* if start and end bit are set, the data bytes is 0. */
18312 + data_bytes = 0;
18313 + } else {
18314 + data_bytes = bitlen / 8;
18315 + }
18316 + debug("%s: len=%d [bytes]\n", __func__, data_bytes);
18317 +
18318 + /* Set Chip select */
18319 + cadence_qspi_apb_chipselect(base, spi_chip_select(dev),
18320 + CONFIG_CQSPI_DECODER);
18321 +
18322 + if ((flags & SPI_XFER_END) || (flags == 0)) {
18323 + if (priv->cmd_len == 0) {
18324 + printf("QSPI: Error, command is empty.\n");
18325 + return -1;
18326 + }
18327 +
18328 + if (din && data_bytes) {
18329 + /* read */
18330 + /* Use STIG if no address. */
18331 + if (!CQSPI_IS_ADDR(priv->cmd_len))
18332 + mode = CQSPI_STIG_READ;
18333 + else
18334 + mode = CQSPI_INDIRECT_READ;
18335 + } else if (dout && !(flags & SPI_XFER_BEGIN)) {
18336 + /* write */
18337 + if (!CQSPI_IS_ADDR(priv->cmd_len))
18338 + mode = CQSPI_STIG_WRITE;
18339 + else
18340 + mode = CQSPI_INDIRECT_WRITE;
18341 + }
18342 +
18343 + switch (mode) {
18344 + case CQSPI_STIG_READ:
18345 + err = cadence_qspi_apb_command_read(
18346 + base, priv->cmd_len, cmd_buf,
18347 + data_bytes, din);
18348 +
18349 + break;
18350 + case CQSPI_STIG_WRITE:
18351 + err = cadence_qspi_apb_command_write(base,
18352 + priv->cmd_len, cmd_buf,
18353 + data_bytes, dout);
18354 + break;
18355 + case CQSPI_INDIRECT_READ:
18356 + err = cadence_qspi_apb_indirect_read_setup(plat,
18357 + priv->cmd_len, cmd_buf);
18358 + if (!err) {
18359 + err = cadence_qspi_apb_indirect_read_execute
18360 + (plat, data_bytes, din);
18361 + }
18362 + break;
18363 + case CQSPI_INDIRECT_WRITE:
18364 + err = cadence_qspi_apb_indirect_write_setup
18365 + (plat, priv->cmd_len, cmd_buf);
18366 + if (!err) {
18367 + err = cadence_qspi_apb_indirect_write_execute
18368 + (plat, data_bytes, dout);
18369 + }
18370 + break;
18371 + default:
18372 + err = -1;
18373 + break;
18374 + }
18375 +
18376 + if (flags & SPI_XFER_END) {
18377 + /* clear command buffer */
18378 + memset(cmd_buf, 0, sizeof(priv->cmd_buf));
18379 + priv->cmd_len = 0;
18380 + }
18381 + }
18382 +
18383 + return err;
18384 +}
18385 +
18386 +static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
18387 +{
18388 + struct cadence_spi_platdata *plat = bus->platdata;
18389 + const void *blob = gd->fdt_blob;
18390 + int node = bus->of_offset;
18391 + int subnode;
18392 + u32 data[4];
18393 + int ret;
18394 +
18395 + /* 2 base addresses are needed, lets get them from the DT */
18396 + ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data));
18397 + if (ret) {
18398 + printf("Error: Can't get base addresses (ret=%d)!\n", ret);
18399 + return -ENODEV;
18400 + }
18401 +
18402 + plat->regbase = (void *)data[0];
18403 + plat->ahbbase = (void *)data[2];
18404 +
18405 + /* Use 500KHz as a suitable default */
18406 + plat->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency",
18407 + 500000);
18408 +
18409 + /* All other paramters are embedded in the child node */
18410 + subnode = fdt_first_subnode(blob, node);
18411 + if (!subnode) {
18412 + printf("Error: subnode with SPI flash config missing!\n");
18413 + return -ENODEV;
18414 + }
18415 +
18416 + /* Read other parameters from DT */
18417 + plat->page_size = fdtdec_get_int(blob, subnode, "page-size", 256);
18418 + plat->block_size = fdtdec_get_int(blob, subnode, "block-size", 16);
18419 + plat->tshsl_ns = fdtdec_get_int(blob, subnode, "tshsl-ns", 200);
18420 + plat->tsd2d_ns = fdtdec_get_int(blob, subnode, "tsd2d-ns", 255);
18421 + plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20);
18422 + plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20);
18423 +
18424 + debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
18425 + __func__, plat->regbase, plat->ahbbase, plat->max_hz,
18426 + plat->page_size);
18427 +
18428 + return 0;
18429 +}
18430 +
18431 +static const struct dm_spi_ops cadence_spi_ops = {
18432 + .xfer = cadence_spi_xfer,
18433 + .set_speed = cadence_spi_set_speed,
18434 + .set_mode = cadence_spi_set_mode,
18435 + /*
18436 + * cs_info is not needed, since we require all chip selects to be
18437 + * in the device tree explicitly
18438 + */
18439 +};
18440 +
18441 +static const struct udevice_id cadence_spi_ids[] = {
18442 + { .compatible = "cadence,qspi" },
18443 + { }
18444 +};
18445 +
18446 +U_BOOT_DRIVER(cadence_spi) = {
18447 + .name = "cadence_spi",
18448 + .id = UCLASS_SPI,
18449 + .of_match = cadence_spi_ids,
18450 + .ops = &cadence_spi_ops,
18451 + .ofdata_to_platdata = cadence_spi_ofdata_to_platdata,
18452 + .platdata_auto_alloc_size = sizeof(struct cadence_spi_platdata),
18453 + .priv_auto_alloc_size = sizeof(struct cadence_spi_priv),
18454 + .per_child_auto_alloc_size = sizeof(struct spi_slave),
18455 + .probe = cadence_spi_probe,
18456 +};
18457 diff -ruN u-boot-2015.01-rc3/drivers/spi/cadence_qspi.h u-boot/drivers/spi/cadence_qspi.h
18458 --- u-boot-2015.01-rc3/drivers/spi/cadence_qspi.h 1970-01-01 01:00:00.000000000 +0100
18459 +++ u-boot/drivers/spi/cadence_qspi.h 2015-01-01 17:34:32.701495908 +0100
18460 @@ -0,0 +1,76 @@
18461 +/*
18462 + * Copyright (C) 2012
18463 + * Altera Corporation <www.altera.com>
18464 + *
18465 + * SPDX-License-Identifier: GPL-2.0+
18466 + */
18467 +
18468 +#ifndef __CADENCE_QSPI_H__
18469 +#define __CADENCE_QSPI_H__
18470 +
18471 +#define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0)
18472 +
18473 +#define CQSPI_NO_DECODER_MAX_CS 4
18474 +#define CQSPI_DECODER_MAX_CS 16
18475 +#define CQSPI_READ_CAPTURE_MAX_DELAY 16
18476 +
18477 +struct cadence_spi_platdata {
18478 + unsigned int max_hz;
18479 + void *regbase;
18480 + void *ahbbase;
18481 +
18482 + u32 page_size;
18483 + u32 block_size;
18484 + u32 tshsl_ns;
18485 + u32 tsd2d_ns;
18486 + u32 tchsh_ns;
18487 + u32 tslch_ns;
18488 +};
18489 +
18490 +struct cadence_spi_priv {
18491 + void *regbase;
18492 + void *ahbbase;
18493 + size_t cmd_len;
18494 + u8 cmd_buf[32];
18495 + size_t data_len;
18496 +
18497 + int qspi_is_init;
18498 + unsigned int qspi_calibrated_hz;
18499 + unsigned int qspi_calibrated_cs;
18500 +};
18501 +
18502 +/* Functions call declaration */
18503 +void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat);
18504 +void cadence_qspi_apb_controller_enable(void *reg_base_addr);
18505 +void cadence_qspi_apb_controller_disable(void *reg_base_addr);
18506 +
18507 +int cadence_qspi_apb_command_read(void *reg_base_addr,
18508 + unsigned int cmdlen, const u8 *cmdbuf, unsigned int rxlen, u8 *rxbuf);
18509 +int cadence_qspi_apb_command_write(void *reg_base_addr,
18510 + unsigned int cmdlen, const u8 *cmdbuf,
18511 + unsigned int txlen, const u8 *txbuf);
18512 +
18513 +int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
18514 + unsigned int cmdlen, const u8 *cmdbuf);
18515 +int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
18516 + unsigned int rxlen, u8 *rxbuf);
18517 +int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
18518 + unsigned int cmdlen, const u8 *cmdbuf);
18519 +int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
18520 + unsigned int txlen, const u8 *txbuf);
18521 +
18522 +void cadence_qspi_apb_chipselect(void *reg_base,
18523 + unsigned int chip_select, unsigned int decoder_enable);
18524 +void cadence_qspi_apb_set_clk_mode(void *reg_base_addr,
18525 + unsigned int clk_pol, unsigned int clk_pha);
18526 +void cadence_qspi_apb_config_baudrate_div(void *reg_base,
18527 + unsigned int ref_clk_hz, unsigned int sclk_hz);
18528 +void cadence_qspi_apb_delay(void *reg_base,
18529 + unsigned int ref_clk, unsigned int sclk_hz,
18530 + unsigned int tshsl_ns, unsigned int tsd2d_ns,
18531 + unsigned int tchsh_ns, unsigned int tslch_ns);
18532 +void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
18533 +void cadence_qspi_apb_readdata_capture(void *reg_base,
18534 + unsigned int bypass, unsigned int delay);
18535 +
18536 +#endif /* __CADENCE_QSPI_H__ */
18537 diff -ruN u-boot-2015.01-rc3/drivers/spi/designware_spi.c u-boot/drivers/spi/designware_spi.c
18538 --- u-boot-2015.01-rc3/drivers/spi/designware_spi.c 1970-01-01 01:00:00.000000000 +0100
18539 +++ u-boot/drivers/spi/designware_spi.c 2015-01-01 17:34:32.701495908 +0100
18540 @@ -0,0 +1,426 @@
18541 +/*
18542 + * Designware master SPI core controller driver
18543 + *
18544 + * Copyright (C) 2014 Stefan Roese <sr@denx.de>
18545 + *
18546 + * Very loosely based on the Linux driver:
18547 + * drivers/spi/spi-dw.c, which is:
18548 + * Copyright (c) 2009, Intel Corporation.
18549 + *
18550 + * SPDX-License-Identifier: GPL-2.0
18551 + */
18552 +
18553 +#include <common.h>
18554 +#include <dm.h>
18555 +#include <errno.h>
18556 +#include <malloc.h>
18557 +#include <spi.h>
18558 +#include <fdtdec.h>
18559 +#include <linux/compat.h>
18560 +#include <asm/io.h>
18561 +#include <asm/arch/clock_manager.h>
18562 +
18563 +DECLARE_GLOBAL_DATA_PTR;
18564 +
18565 +/* Register offsets */
18566 +#define DW_SPI_CTRL0 0x00
18567 +#define DW_SPI_CTRL1 0x04
18568 +#define DW_SPI_SSIENR 0x08
18569 +#define DW_SPI_MWCR 0x0c
18570 +#define DW_SPI_SER 0x10
18571 +#define DW_SPI_BAUDR 0x14
18572 +#define DW_SPI_TXFLTR 0x18
18573 +#define DW_SPI_RXFLTR 0x1c
18574 +#define DW_SPI_TXFLR 0x20
18575 +#define DW_SPI_RXFLR 0x24
18576 +#define DW_SPI_SR 0x28
18577 +#define DW_SPI_IMR 0x2c
18578 +#define DW_SPI_ISR 0x30
18579 +#define DW_SPI_RISR 0x34
18580 +#define DW_SPI_TXOICR 0x38
18581 +#define DW_SPI_RXOICR 0x3c
18582 +#define DW_SPI_RXUICR 0x40
18583 +#define DW_SPI_MSTICR 0x44
18584 +#define DW_SPI_ICR 0x48
18585 +#define DW_SPI_DMACR 0x4c
18586 +#define DW_SPI_DMATDLR 0x50
18587 +#define DW_SPI_DMARDLR 0x54
18588 +#define DW_SPI_IDR 0x58
18589 +#define DW_SPI_VERSION 0x5c
18590 +#define DW_SPI_DR 0x60
18591 +
18592 +/* Bit fields in CTRLR0 */
18593 +#define SPI_DFS_OFFSET 0
18594 +
18595 +#define SPI_FRF_OFFSET 4
18596 +#define SPI_FRF_SPI 0x0
18597 +#define SPI_FRF_SSP 0x1
18598 +#define SPI_FRF_MICROWIRE 0x2
18599 +#define SPI_FRF_RESV 0x3
18600 +
18601 +#define SPI_MODE_OFFSET 6
18602 +#define SPI_SCPH_OFFSET 6
18603 +#define SPI_SCOL_OFFSET 7
18604 +
18605 +#define SPI_TMOD_OFFSET 8
18606 +#define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
18607 +#define SPI_TMOD_TR 0x0 /* xmit & recv */
18608 +#define SPI_TMOD_TO 0x1 /* xmit only */
18609 +#define SPI_TMOD_RO 0x2 /* recv only */
18610 +#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
18611 +
18612 +#define SPI_SLVOE_OFFSET 10
18613 +#define SPI_SRL_OFFSET 11
18614 +#define SPI_CFS_OFFSET 12
18615 +
18616 +/* Bit fields in SR, 7 bits */
18617 +#define SR_MASK 0x7f /* cover 7 bits */
18618 +#define SR_BUSY (1 << 0)
18619 +#define SR_TF_NOT_FULL (1 << 1)
18620 +#define SR_TF_EMPT (1 << 2)
18621 +#define SR_RF_NOT_EMPT (1 << 3)
18622 +#define SR_RF_FULL (1 << 4)
18623 +#define SR_TX_ERR (1 << 5)
18624 +#define SR_DCOL (1 << 6)
18625 +
18626 +#define RX_TIMEOUT 1000 /* timeout in ms */
18627 +
18628 +struct dw_spi_platdata {
18629 + s32 frequency; /* Default clock frequency, -1 for none */
18630 + void __iomem *regs;
18631 +};
18632 +
18633 +struct dw_spi_priv {
18634 + void __iomem *regs;
18635 + unsigned int freq; /* Default frequency */
18636 + unsigned int mode;
18637 +
18638 + int bits_per_word;
18639 + u8 cs; /* chip select pin */
18640 + u8 tmode; /* TR/TO/RO/EEPROM */
18641 + u8 type; /* SPI/SSP/MicroWire */
18642 + int len;
18643 +
18644 + u32 fifo_len; /* depth of the FIFO buffer */
18645 + void *tx;
18646 + void *tx_end;
18647 + void *rx;
18648 + void *rx_end;
18649 +};
18650 +
18651 +static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset)
18652 +{
18653 + return __raw_readl(priv->regs + offset);
18654 +}
18655 +
18656 +static inline void dw_writel(struct dw_spi_priv *priv, u32 offset, u32 val)
18657 +{
18658 + __raw_writel(val, priv->regs + offset);
18659 +}
18660 +
18661 +static inline u16 dw_readw(struct dw_spi_priv *priv, u32 offset)
18662 +{
18663 + return __raw_readw(priv->regs + offset);
18664 +}
18665 +
18666 +static inline void dw_writew(struct dw_spi_priv *priv, u32 offset, u16 val)
18667 +{
18668 + __raw_writew(val, priv->regs + offset);
18669 +}
18670 +
18671 +static int dw_spi_ofdata_to_platdata(struct udevice *bus)
18672 +{
18673 + struct dw_spi_platdata *plat = bus->platdata;
18674 + const void *blob = gd->fdt_blob;
18675 + int node = bus->of_offset;
18676 +
18677 + plat->regs = (struct dw_spi *)fdtdec_get_addr(blob, node, "reg");
18678 +
18679 + /* Use 500KHz as a suitable default */
18680 + plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
18681 + 500000);
18682 + debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs,
18683 + plat->frequency);
18684 +
18685 + return 0;
18686 +}
18687 +
18688 +static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable)
18689 +{
18690 + dw_writel(priv, DW_SPI_SSIENR, (enable ? 1 : 0));
18691 +}
18692 +
18693 +/* Restart the controller, disable all interrupts, clean rx fifo */
18694 +static void spi_hw_init(struct dw_spi_priv *priv)
18695 +{
18696 + spi_enable_chip(priv, 0);
18697 + dw_writel(priv, DW_SPI_IMR, 0xff);
18698 + spi_enable_chip(priv, 1);
18699 +
18700 + /*
18701 + * Try to detect the FIFO depth if not set by interface driver,
18702 + * the depth could be from 2 to 256 from HW spec
18703 + */
18704 + if (!priv->fifo_len) {
18705 + u32 fifo;
18706 +
18707 + for (fifo = 2; fifo <= 257; fifo++) {
18708 + dw_writew(priv, DW_SPI_TXFLTR, fifo);
18709 + if (fifo != dw_readw(priv, DW_SPI_TXFLTR))
18710 + break;
18711 + }
18712 +
18713 + priv->fifo_len = (fifo == 257) ? 0 : fifo;
18714 + dw_writew(priv, DW_SPI_TXFLTR, 0);
18715 + }
18716 + debug("%s: fifo_len=%d\n", __func__, priv->fifo_len);
18717 +}
18718 +
18719 +static int dw_spi_probe(struct udevice *bus)
18720 +{
18721 + struct dw_spi_platdata *plat = dev_get_platdata(bus);
18722 + struct dw_spi_priv *priv = dev_get_priv(bus);
18723 +
18724 + priv->regs = plat->regs;
18725 + priv->freq = plat->frequency;
18726 +
18727 + /* Currently only bits_per_word == 8 supported */
18728 + priv->bits_per_word = 8;
18729 +
18730 + priv->tmode = 0; /* Tx & Rx */
18731 +
18732 + /* Basic HW init */
18733 + spi_hw_init(priv);
18734 +
18735 + return 0;
18736 +}
18737 +
18738 +/* Return the max entries we can fill into tx fifo */
18739 +static inline u32 tx_max(struct dw_spi_priv *priv)
18740 +{
18741 + u32 tx_left, tx_room, rxtx_gap;
18742 +
18743 + tx_left = (priv->tx_end - priv->tx) / (priv->bits_per_word >> 3);
18744 + tx_room = priv->fifo_len - dw_readw(priv, DW_SPI_TXFLR);
18745 +
18746 + /*
18747 + * Another concern is about the tx/rx mismatch, we
18748 + * thought about using (priv->fifo_len - rxflr - txflr) as
18749 + * one maximum value for tx, but it doesn't cover the
18750 + * data which is out of tx/rx fifo and inside the
18751 + * shift registers. So a control from sw point of
18752 + * view is taken.
18753 + */
18754 + rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) /
18755 + (priv->bits_per_word >> 3);
18756 +
18757 + return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap));
18758 +}
18759 +
18760 +/* Return the max entries we should read out of rx fifo */
18761 +static inline u32 rx_max(struct dw_spi_priv *priv)
18762 +{
18763 + u32 rx_left = (priv->rx_end - priv->rx) / (priv->bits_per_word >> 3);
18764 +
18765 + return min_t(u32, rx_left, dw_readw(priv, DW_SPI_RXFLR));
18766 +}
18767 +
18768 +static void dw_writer(struct dw_spi_priv *priv)
18769 +{
18770 + u32 max = tx_max(priv);
18771 + u16 txw = 0;
18772 +
18773 + while (max--) {
18774 + /* Set the tx word if the transfer's original "tx" is not null */
18775 + if (priv->tx_end - priv->len) {
18776 + if (priv->bits_per_word == 8)
18777 + txw = *(u8 *)(priv->tx);
18778 + else
18779 + txw = *(u16 *)(priv->tx);
18780 + }
18781 + dw_writew(priv, DW_SPI_DR, txw);
18782 + debug("%s: tx=0x%02x\n", __func__, txw);
18783 + priv->tx += priv->bits_per_word >> 3;
18784 + }
18785 +}
18786 +
18787 +static int dw_reader(struct dw_spi_priv *priv)
18788 +{
18789 + unsigned start = get_timer(0);
18790 + u32 max;
18791 + u16 rxw;
18792 +
18793 + /* Wait for rx data to be ready */
18794 + while (rx_max(priv) == 0) {
18795 + if (get_timer(start) > RX_TIMEOUT)
18796 + return -ETIMEDOUT;
18797 + }
18798 +
18799 + max = rx_max(priv);
18800 +
18801 + while (max--) {
18802 + rxw = dw_readw(priv, DW_SPI_DR);
18803 + debug("%s: rx=0x%02x\n", __func__, rxw);
18804 +
18805 + /*
18806 + * Care about rx only if the transfer's original "rx" is
18807 + * not null
18808 + */
18809 + if (priv->rx_end - priv->len) {
18810 + if (priv->bits_per_word == 8)
18811 + *(u8 *)(priv->rx) = rxw;
18812 + else
18813 + *(u16 *)(priv->rx) = rxw;
18814 + }
18815 + priv->rx += priv->bits_per_word >> 3;
18816 + }
18817 +
18818 + return 0;
18819 +}
18820 +
18821 +static int poll_transfer(struct dw_spi_priv *priv)
18822 +{
18823 + int ret;
18824 +
18825 + do {
18826 + dw_writer(priv);
18827 + ret = dw_reader(priv);
18828 + if (ret < 0)
18829 + return ret;
18830 + } while (priv->rx_end > priv->rx);
18831 +
18832 + return 0;
18833 +}
18834 +
18835 +static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen,
18836 + const void *dout, void *din, unsigned long flags)
18837 +{
18838 + struct udevice *bus = dev->parent;
18839 + struct dw_spi_priv *priv = dev_get_priv(bus);
18840 + const u8 *tx = dout;
18841 + u8 *rx = din;
18842 + int ret = 0;
18843 + u32 cr0 = 0;
18844 + u32 cs;
18845 +
18846 + /* spi core configured to do 8 bit transfers */
18847 + if (bitlen % 8) {
18848 + debug("Non byte aligned SPI transfer.\n");
18849 + return -1;
18850 + }
18851 +
18852 + cr0 = (priv->bits_per_word - 1) | (priv->type << SPI_FRF_OFFSET) |
18853 + (priv->mode << SPI_MODE_OFFSET) |
18854 + (priv->tmode << SPI_TMOD_OFFSET);
18855 +
18856 + if (rx && tx)
18857 + priv->tmode = SPI_TMOD_TR;
18858 + else if (rx)
18859 + priv->tmode = SPI_TMOD_RO;
18860 + else
18861 + priv->tmode = SPI_TMOD_TO;
18862 +
18863 + cr0 &= ~SPI_TMOD_MASK;
18864 + cr0 |= (priv->tmode << SPI_TMOD_OFFSET);
18865 +
18866 + priv->len = bitlen >> 3;
18867 + debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len);
18868 +
18869 + priv->tx = (void *)tx;
18870 + priv->tx_end = priv->tx + priv->len;
18871 + priv->rx = rx;
18872 + priv->rx_end = priv->rx + priv->len;
18873 +
18874 + /* Disable controller before writing control registers */
18875 + spi_enable_chip(priv, 0);
18876 +
18877 + debug("%s: cr0=%08x\n", __func__, cr0);
18878 + /* Reprogram cr0 only if changed */
18879 + if (dw_readw(priv, DW_SPI_CTRL0) != cr0)
18880 + dw_writew(priv, DW_SPI_CTRL0, cr0);
18881 +
18882 + /*
18883 + * Configure the desired SS (slave select 0...3) in the controller
18884 + * The DW SPI controller will activate and deactivate this CS
18885 + * automatically. So no cs_activate() etc is needed in this driver.
18886 + */
18887 + cs = spi_chip_select(dev);
18888 + dw_writel(priv, DW_SPI_SER, 1 << cs);
18889 +
18890 + /* Enable controller after writing control registers */
18891 + spi_enable_chip(priv, 1);
18892 +
18893 + /* Start transfer in a polling loop */
18894 + ret = poll_transfer(priv);
18895 +
18896 + return ret;
18897 +}
18898 +
18899 +static int dw_spi_set_speed(struct udevice *bus, uint speed)
18900 +{
18901 + struct dw_spi_platdata *plat = bus->platdata;
18902 + struct dw_spi_priv *priv = dev_get_priv(bus);
18903 + u16 clk_div;
18904 +
18905 + if (speed > plat->frequency)
18906 + speed = plat->frequency;
18907 +
18908 + /* Disable controller before writing control registers */
18909 + spi_enable_chip(priv, 0);
18910 +
18911 + /* clk_div doesn't support odd number */
18912 + clk_div = cm_get_spi_controller_clk_hz() / speed;
18913 + clk_div = (clk_div + 1) & 0xfffe;
18914 + dw_writel(priv, DW_SPI_BAUDR, clk_div);
18915 +
18916 + /* Enable controller after writing control registers */
18917 + spi_enable_chip(priv, 1);
18918 +
18919 + priv->freq = speed;
18920 + debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs,
18921 + priv->freq, clk_div);
18922 +
18923 + return 0;
18924 +}
18925 +
18926 +static int dw_spi_set_mode(struct udevice *bus, uint mode)
18927 +{
18928 + struct dw_spi_priv *priv = dev_get_priv(bus);
18929 +
18930 + /*
18931 + * Can't set mode yet. Since this depends on if rx, tx, or
18932 + * rx & tx is requested. So we have to defer this to the
18933 + * real transfer function.
18934 + */
18935 + priv->mode = mode;
18936 + debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
18937 +
18938 + return 0;
18939 +}
18940 +
18941 +static const struct dm_spi_ops dw_spi_ops = {
18942 + .xfer = dw_spi_xfer,
18943 + .set_speed = dw_spi_set_speed,
18944 + .set_mode = dw_spi_set_mode,
18945 + /*
18946 + * cs_info is not needed, since we require all chip selects to be
18947 + * in the device tree explicitly
18948 + */
18949 +};
18950 +
18951 +static const struct udevice_id dw_spi_ids[] = {
18952 + { .compatible = "snps,dw-spi-mmio" },
18953 + { }
18954 +};
18955 +
18956 +U_BOOT_DRIVER(dw_spi) = {
18957 + .name = "dw_spi",
18958 + .id = UCLASS_SPI,
18959 + .of_match = dw_spi_ids,
18960 + .ops = &dw_spi_ops,
18961 + .ofdata_to_platdata = dw_spi_ofdata_to_platdata,
18962 + .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata),
18963 + .priv_auto_alloc_size = sizeof(struct dw_spi_priv),
18964 + .per_child_auto_alloc_size = sizeof(struct spi_slave),
18965 + .probe = dw_spi_probe,
18966 +};
18967 diff -ruN u-boot-2015.01-rc3/drivers/spi/ich.c u-boot/drivers/spi/ich.c
18968 --- u-boot-2015.01-rc3/drivers/spi/ich.c 2014-12-08 22:35:08.000000000 +0100
18969 +++ u-boot/drivers/spi/ich.c 2015-01-01 17:34:32.701495908 +0100
18970 @@ -141,6 +141,15 @@
18971 ich->slave.max_write_size = ctlr.databytes;
18972 ich->speed = max_hz;
18973
18974 + /*
18975 + * ICH 7 SPI controller only supports array read command
18976 + * and byte program command for SST flash
18977 + */
18978 + if (ctlr.ich_version == 7) {
18979 + ich->slave.op_mode_rx = SPI_OPM_RX_AS;
18980 + ich->slave.op_mode_tx = SPI_OPM_TX_BP;
18981 + }
18982 +
18983 return &ich->slave;
18984 }
18985
18986 @@ -158,7 +167,8 @@
18987 */
18988 static int get_ich_version(uint16_t device_id)
18989 {
18990 - if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC)
18991 + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC ||
18992 + device_id == PCI_DEVICE_ID_INTEL_ITC_LPC)
18993 return 7;
18994
18995 if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
18996 @@ -483,8 +493,6 @@
18997 struct spi_trans *trans = &ich->trans;
18998 unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
18999 int using_cmd = 0;
19000 - /* Align read transactions to 64-byte boundaries */
19001 - char buff[ctlr.databytes];
19002
19003 /* Ee don't support writing partial bytes. */
19004 if (bitlen % 8) {
19005 @@ -632,14 +640,9 @@
19006 */
19007 while (trans->bytesout || trans->bytesin) {
19008 uint32_t data_length;
19009 - uint32_t aligned_offset;
19010 - uint32_t diff;
19011 -
19012 - aligned_offset = trans->offset & ~(ctlr.databytes - 1);
19013 - diff = trans->offset - aligned_offset;
19014
19015 /* SPI addresses are 24 bit only */
19016 - ich_writel(aligned_offset & 0x00FFFFFF, ctlr.addr);
19017 + ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr);
19018
19019 if (trans->bytesout)
19020 data_length = min(trans->bytesout, ctlr.databytes);
19021 @@ -673,13 +676,7 @@
19022 }
19023
19024 if (trans->bytesin) {
19025 - if (diff) {
19026 - data_length -= diff;
19027 - read_reg(ctlr.data, buff, ctlr.databytes);
19028 - memcpy(trans->in, buff + diff, data_length);
19029 - } else {
19030 - read_reg(ctlr.data, trans->in, data_length);
19031 - }
19032 + read_reg(ctlr.data, trans->in, data_length);
19033 spi_use_in(trans, data_length);
19034 if (with_address)
19035 trans->offset += data_length;
19036 diff -ruN u-boot-2015.01-rc3/drivers/spi/Makefile u-boot/drivers/spi/Makefile
19037 --- u-boot-2015.01-rc3/drivers/spi/Makefile 2014-12-08 22:35:08.000000000 +0100
19038 +++ u-boot/drivers/spi/Makefile 2015-01-01 17:34:32.701495908 +0100
19039 @@ -23,9 +23,11 @@
19040 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
19041 obj-$(CONFIG_BFIN_SPI) += bfin_spi.o
19042 obj-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
19043 +obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
19044 obj-$(CONFIG_CF_SPI) += cf_spi.o
19045 obj-$(CONFIG_CF_QSPI) += cf_qspi.o
19046 obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
19047 +obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
19048 obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
19049 obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
19050 obj-$(CONFIG_ICH_SPI) += ich.o
19051 diff -ruN u-boot-2015.01-rc3/drivers/thermal/imx_thermal.c u-boot/drivers/thermal/imx_thermal.c
19052 --- u-boot-2015.01-rc3/drivers/thermal/imx_thermal.c 2014-12-08 22:35:08.000000000 +0100
19053 +++ u-boot/drivers/thermal/imx_thermal.c 2015-01-01 17:34:32.705495842 +0100
19054 @@ -156,8 +156,6 @@
19055 if (fuse == 0 || fuse == ~0) {
19056 printf("CPU: Thermal invalid data, fuse: 0x%x\n", fuse);
19057 return -EPERM;
19058 - } else {
19059 - printf("CPU: Thermal calibration data: 0x%x\n", fuse);
19060 }
19061
19062 *priv = fuse;
19063 diff -ruN u-boot-2015.01-rc3/drivers/usb/gadget/atmel_usba_udc.c u-boot/drivers/usb/gadget/atmel_usba_udc.c
19064 --- u-boot-2015.01-rc3/drivers/usb/gadget/atmel_usba_udc.c 2014-12-08 22:35:08.000000000 +0100
19065 +++ u-boot/drivers/usb/gadget/atmel_usba_udc.c 2015-01-01 17:34:32.709495776 +0100
19066 @@ -1062,7 +1062,6 @@
19067 if ((epstatus & epctrl) & USBA_RX_BK_RDY) {
19068 DBG(DBG_BUS, "%s: RX data ready\n", ep->ep.name);
19069 receive_data(ep);
19070 - usba_ep_writel(ep, CLR_STA, USBA_RX_BK_RDY);
19071 }
19072 }
19073
19074 diff -ruN u-boot-2015.01-rc3/drivers/usb/gadget/ether.c u-boot/drivers/usb/gadget/ether.c
19075 --- u-boot-2015.01-rc3/drivers/usb/gadget/ether.c 2014-12-08 22:35:08.000000000 +0100
19076 +++ u-boot/drivers/usb/gadget/ether.c 2015-01-01 17:34:32.709495776 +0100
19077 @@ -852,30 +852,6 @@
19078 DEFINE_CACHE_ALIGN_BUFFER(u8, status_req, STATUS_BYTECOUNT);
19079 #endif
19080
19081 -
19082 -/**
19083 - * strlcpy - Copy a %NUL terminated string into a sized buffer
19084 - * @dest: Where to copy the string to
19085 - * @src: Where to copy the string from
19086 - * @size: size of destination buffer
19087 - *
19088 - * Compatible with *BSD: the result is always a valid
19089 - * NUL-terminated string that fits in the buffer (unless,
19090 - * of course, the buffer size is zero). It does not pad
19091 - * out the result like strncpy() does.
19092 - */
19093 -size_t strlcpy(char *dest, const char *src, size_t size)
19094 -{
19095 - size_t ret = strlen(src);
19096 -
19097 - if (size) {
19098 - size_t len = (ret >= size) ? size - 1 : ret;
19099 - memcpy(dest, src, len);
19100 - dest[len] = '\0';
19101 - }
19102 - return ret;
19103 -}
19104 -
19105 /*============================================================================*/
19106
19107 /*
19108 diff -ruN u-boot-2015.01-rc3/drivers/usb/gadget/f_dfu.c u-boot/drivers/usb/gadget/f_dfu.c
19109 --- u-boot-2015.01-rc3/drivers/usb/gadget/f_dfu.c 2014-12-08 22:35:08.000000000 +0100
19110 +++ u-boot/drivers/usb/gadget/f_dfu.c 2015-01-01 17:34:32.709495776 +0100
19111 @@ -366,7 +366,7 @@
19112 to_runtime_mode(f_dfu);
19113 f_dfu->dfu_state = DFU_STATE_appIDLE;
19114
19115 - dfu_trigger_detach();
19116 + g_dnl_trigger_detach();
19117 break;
19118 default:
19119 f_dfu->dfu_state = DFU_STATE_dfuERROR;
19120 diff -ruN u-boot-2015.01-rc3/drivers/usb/gadget/f_fastboot.c u-boot/drivers/usb/gadget/f_fastboot.c
19121 --- u-boot-2015.01-rc3/drivers/usb/gadget/f_fastboot.c 2014-12-08 22:35:08.000000000 +0100
19122 +++ u-boot/drivers/usb/gadget/f_fastboot.c 2015-01-01 17:34:32.709495776 +0100
19123 @@ -480,6 +480,17 @@
19124 fastboot_tx_write_str("OKAY");
19125 }
19126
19127 +static void do_exit_on_complete(struct usb_ep *ep, struct usb_request *req)
19128 +{
19129 + g_dnl_trigger_detach();
19130 +}
19131 +
19132 +static void cb_continue(struct usb_ep *ep, struct usb_request *req)
19133 +{
19134 + fastboot_func->in_req->complete = do_exit_on_complete;
19135 + fastboot_tx_write_str("OKAY");
19136 +}
19137 +
19138 #ifdef CONFIG_FASTBOOT_FLASH
19139 static void cb_flash(struct usb_ep *ep, struct usb_request *req)
19140 {
19141 @@ -520,6 +531,9 @@
19142 }, {
19143 .cmd = "boot",
19144 .cb = cb_boot,
19145 + }, {
19146 + .cmd = "continue",
19147 + .cb = cb_continue,
19148 },
19149 #ifdef CONFIG_FASTBOOT_FLASH
19150 {
19151 diff -ruN u-boot-2015.01-rc3/drivers/usb/gadget/f_thor.c u-boot/drivers/usb/gadget/f_thor.c
19152 --- u-boot-2015.01-rc3/drivers/usb/gadget/f_thor.c 2014-12-08 22:35:08.000000000 +0100
19153 +++ u-boot/drivers/usb/gadget/f_thor.c 2015-01-01 17:34:32.709495776 +0100
19154 @@ -205,12 +205,24 @@
19155
19156 static int download_tail(long long int left, int cnt)
19157 {
19158 - struct dfu_entity *dfu_entity = dfu_get_entity(alt_setting_num);
19159 - void *transfer_buffer = dfu_get_buf(dfu_entity);
19160 + struct dfu_entity *dfu_entity;
19161 + void *transfer_buffer;
19162 int ret;
19163
19164 debug("%s: left: %llu cnt: %d\n", __func__, left, cnt);
19165
19166 + dfu_entity = dfu_get_entity(alt_setting_num);
19167 + if (!dfu_entity) {
19168 + error("Alt setting: %d entity not found!\n", alt_setting_num);
19169 + return -ENOENT;
19170 + }
19171 +
19172 + transfer_buffer = dfu_get_buf(dfu_entity);
19173 + if (!transfer_buffer) {
19174 + error("Transfer buffer not allocated!");
19175 + return -ENXIO;
19176 + }
19177 +
19178 if (left) {
19179 ret = dfu_write(dfu_entity, transfer_buffer, left, cnt++);
19180 if (ret) {
19181 diff -ruN u-boot-2015.01-rc3/drivers/usb/gadget/g_dnl.c u-boot/drivers/usb/gadget/g_dnl.c
19182 --- u-boot-2015.01-rc3/drivers/usb/gadget/g_dnl.c 2014-12-08 22:35:08.000000000 +0100
19183 +++ u-boot/drivers/usb/gadget/g_dnl.c 2015-01-01 17:34:32.709495776 +0100
19184 @@ -163,6 +163,23 @@
19185 return -EOPNOTSUPP;
19186 }
19187
19188 +static bool g_dnl_detach_request;
19189 +
19190 +bool g_dnl_detach(void)
19191 +{
19192 + return g_dnl_detach_request;
19193 +}
19194 +
19195 +void g_dnl_trigger_detach(void)
19196 +{
19197 + g_dnl_detach_request = true;
19198 +}
19199 +
19200 +void g_dnl_clear_detach(void)
19201 +{
19202 + g_dnl_detach_request = false;
19203 +}
19204 +
19205 static int g_dnl_get_bcd_device_number(struct usb_composite_dev *cdev)
19206 {
19207 struct usb_gadget *gadget = cdev->gadget;
19208 diff -ruN u-boot-2015.01-rc3/drivers/usb/host/ehci-fsl.c u-boot/drivers/usb/host/ehci-fsl.c
19209 --- u-boot-2015.01-rc3/drivers/usb/host/ehci-fsl.c 2014-12-08 22:35:08.000000000 +0100
19210 +++ u-boot/drivers/usb/host/ehci-fsl.c 2015-01-01 17:34:32.713495710 +0100
19211 @@ -15,9 +15,14 @@
19212 #include <usb/ehci-fsl.h>
19213 #include <hwconfig.h>
19214 #include <fsl_usb.h>
19215 +#include <fdt_support.h>
19216
19217 #include "ehci.h"
19218
19219 +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
19220 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
19221 +#endif
19222 +
19223 static void set_txfifothresh(struct usb_ehci *, u32);
19224
19225 /* Check USB PHY clock valid */
19226 @@ -158,3 +163,184 @@
19227 cmd |= TXFIFO_THRESH(txfifo_thresh);
19228 ehci_writel(&ehci->txfilltuning, cmd);
19229 }
19230 +
19231 +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
19232 +static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode,
19233 + const char *phy_type, int start_offset)
19234 +{
19235 + const char *compat_dr = "fsl-usb2-dr";
19236 + const char *compat_mph = "fsl-usb2-mph";
19237 + const char *prop_mode = "dr_mode";
19238 + const char *prop_type = "phy_type";
19239 + const char *node_type = NULL;
19240 + int node_offset;
19241 + int err;
19242 +
19243 + node_offset = fdt_node_offset_by_compatible(blob,
19244 + start_offset, compat_mph);
19245 + if (node_offset < 0) {
19246 + node_offset = fdt_node_offset_by_compatible(blob,
19247 + start_offset,
19248 + compat_dr);
19249 + if (node_offset < 0) {
19250 + printf("WARNING: could not find compatible node: %s",
19251 + fdt_strerror(node_offset));
19252 + return -1;
19253 + }
19254 + node_type = compat_dr;
19255 + } else {
19256 + node_type = compat_mph;
19257 + }
19258 +
19259 + if (mode) {
19260 + err = fdt_setprop(blob, node_offset, prop_mode, mode,
19261 + strlen(mode) + 1);
19262 + if (err < 0)
19263 + printf("WARNING: could not set %s for %s: %s.\n",
19264 + prop_mode, node_type, fdt_strerror(err));
19265 + }
19266 +
19267 + if (phy_type) {
19268 + err = fdt_setprop(blob, node_offset, prop_type, phy_type,
19269 + strlen(phy_type) + 1);
19270 + if (err < 0)
19271 + printf("WARNING: could not set %s for %s: %s.\n",
19272 + prop_type, node_type, fdt_strerror(err));
19273 + }
19274 +
19275 + return node_offset;
19276 +}
19277 +
19278 +static const char *fdt_usb_get_node_type(void *blob, int start_offset,
19279 + int *node_offset)
19280 +{
19281 + const char *compat_dr = "fsl-usb2-dr";
19282 + const char *compat_mph = "fsl-usb2-mph";
19283 + const char *node_type = NULL;
19284 +
19285 + *node_offset = fdt_node_offset_by_compatible(blob, start_offset,
19286 + compat_mph);
19287 + if (*node_offset < 0) {
19288 + *node_offset = fdt_node_offset_by_compatible(blob,
19289 + start_offset,
19290 + compat_dr);
19291 + if (*node_offset < 0) {
19292 + printf("ERROR: could not find compatible node: %s\n",
19293 + fdt_strerror(*node_offset));
19294 + } else {
19295 + node_type = compat_dr;
19296 + }
19297 + } else {
19298 + node_type = compat_mph;
19299 + }
19300 +
19301 + return node_type;
19302 +}
19303 +
19304 +static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum,
19305 + int start_offset)
19306 +{
19307 + int node_offset, err;
19308 + const char *node_type = NULL;
19309 +
19310 + node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset);
19311 + if (!node_type)
19312 + return -1;
19313 +
19314 + err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0);
19315 + if (err < 0) {
19316 + printf("ERROR: could not set %s for %s: %s.\n",
19317 + prop_erratum, node_type, fdt_strerror(err));
19318 + }
19319 +
19320 + return node_offset;
19321 +}
19322 +
19323 +void fdt_fixup_dr_usb(void *blob, bd_t *bd)
19324 +{
19325 + static const char * const modes[] = { "host", "peripheral", "otg" };
19326 + static const char * const phys[] = { "ulpi", "utmi" };
19327 + int usb_erratum_a006261_off = -1;
19328 + int usb_erratum_a007075_off = -1;
19329 + int usb_erratum_a007792_off = -1;
19330 + int usb_mode_off = -1;
19331 + int usb_phy_off = -1;
19332 + char str[5];
19333 + int i, j;
19334 +
19335 + for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
19336 + const char *dr_mode_type = NULL;
19337 + const char *dr_phy_type = NULL;
19338 + int mode_idx = -1, phy_idx = -1;
19339 +
19340 + snprintf(str, 5, "%s%d", "usb", i);
19341 + if (hwconfig(str)) {
19342 + for (j = 0; j < ARRAY_SIZE(modes); j++) {
19343 + if (hwconfig_subarg_cmp(str, "dr_mode",
19344 + modes[j])) {
19345 + mode_idx = j;
19346 + break;
19347 + }
19348 + }
19349 +
19350 + for (j = 0; j < ARRAY_SIZE(phys); j++) {
19351 + if (hwconfig_subarg_cmp(str, "phy_type",
19352 + phys[j])) {
19353 + phy_idx = j;
19354 + break;
19355 + }
19356 + }
19357 +
19358 + if (mode_idx < 0 && phy_idx < 0) {
19359 + printf("WARNING: invalid phy or mode\n");
19360 + return;
19361 + }
19362 +
19363 + if (mode_idx > -1)
19364 + dr_mode_type = modes[mode_idx];
19365 +
19366 + if (phy_idx > -1)
19367 + dr_phy_type = phys[phy_idx];
19368 + }
19369 +
19370 + usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
19371 + dr_mode_type, NULL,
19372 + usb_mode_off);
19373 +
19374 + if (usb_mode_off < 0)
19375 + return;
19376 +
19377 + usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
19378 + NULL, dr_phy_type,
19379 + usb_phy_off);
19380 +
19381 + if (usb_phy_off < 0)
19382 + return;
19383 +
19384 + if (has_erratum_a006261()) {
19385 + usb_erratum_a006261_off = fdt_fixup_usb_erratum
19386 + (blob,
19387 + "fsl,usb-erratum-a006261",
19388 + usb_erratum_a006261_off);
19389 + if (usb_erratum_a006261_off < 0)
19390 + return;
19391 + }
19392 + if (has_erratum_a007075()) {
19393 + usb_erratum_a007075_off = fdt_fixup_usb_erratum
19394 + (blob,
19395 + "fsl,usb-erratum-a007075",
19396 + usb_erratum_a007075_off);
19397 + if (usb_erratum_a007075_off < 0)
19398 + return;
19399 + }
19400 + if (has_erratum_a007792()) {
19401 + usb_erratum_a007792_off = fdt_fixup_usb_erratum
19402 + (blob,
19403 + "fsl,usb-erratum-a007792",
19404 + usb_erratum_a007792_off);
19405 + if (usb_erratum_a007792_off < 0)
19406 + return;
19407 + }
19408 + }
19409 +}
19410 +#endif
19411 diff -ruN u-boot-2015.01-rc3/drivers/usb/host/ehci-hcd.c u-boot/drivers/usb/host/ehci-hcd.c
19412 --- u-boot-2015.01-rc3/drivers/usb/host/ehci-hcd.c 2014-12-08 22:35:08.000000000 +0100
19413 +++ u-boot/drivers/usb/host/ehci-hcd.c 2015-01-01 17:34:32.713495710 +0100
19414 @@ -971,7 +971,6 @@
19415 qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
19416 qh_list->qh_endpt1 = cpu_to_hc32(QH_ENDPT1_H(1) |
19417 QH_ENDPT1_EPS(USB_SPEED_HIGH));
19418 - qh_list->qh_curtd = cpu_to_hc32(QT_NEXT_TERMINATE);
19419 qh_list->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE);
19420 qh_list->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE);
19421 qh_list->qh_overlay.qt_token =
19422 diff -ruN u-boot-2015.01-rc3/drivers/usb/host/ehci-mx6.c u-boot/drivers/usb/host/ehci-mx6.c
19423 --- u-boot-2015.01-rc3/drivers/usb/host/ehci-mx6.c 2014-12-08 22:35:08.000000000 +0100
19424 +++ u-boot/drivers/usb/host/ehci-mx6.c 2015-01-01 17:34:32.713495710 +0100
19425 @@ -160,7 +160,7 @@
19426 val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
19427 __raw_writel(val, phy_ctrl);
19428
19429 - return val & USBPHY_CTRL_OTG_ID;
19430 + return 0;
19431 }
19432
19433 /* Base address for this IP block is 0x02184800 */
19434 @@ -193,6 +193,28 @@
19435 __raw_writel(val, ctrl);
19436 }
19437
19438 +int usb_phy_mode(int port)
19439 +{
19440 + void __iomem *phy_reg;
19441 + void __iomem *phy_ctrl;
19442 + u32 val;
19443 +
19444 + phy_reg = (void __iomem *)phy_bases[port];
19445 + phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
19446 +
19447 + val = __raw_readl(phy_ctrl);
19448 +
19449 + if (val & USBPHY_CTRL_OTG_ID)
19450 + return USB_INIT_DEVICE;
19451 + else
19452 + return USB_INIT_HOST;
19453 +}
19454 +
19455 +int __weak board_usb_phy_mode(int port)
19456 +{
19457 + return usb_phy_mode(port);
19458 +}
19459 +
19460 int __weak board_ehci_hcd_init(int port)
19461 {
19462 return 0;
19463 @@ -221,7 +243,8 @@
19464 usb_power_config(index);
19465 usb_oc_config(index);
19466 usb_internal_phy_clock_gate(index, 1);
19467 - type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
19468 + usb_phy_enable(index, ehci);
19469 + type = board_usb_phy_mode(index);
19470
19471 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
19472 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
19473 diff -ruN u-boot-2015.01-rc3/.git/config u-boot/.git/config
19474 --- u-boot-2015.01-rc3/.git/config 1970-01-01 01:00:00.000000000 +0100
19475 +++ u-boot/.git/config 2015-01-01 17:34:31.953508170 +0100
19476 @@ -0,0 +1,11 @@
19477 +[core]
19478 + repositoryformatversion = 0
19479 + filemode = true
19480 + bare = false
19481 + logallrefupdates = true
19482 +[remote "origin"]
19483 + fetch = +refs/heads/*:refs/remotes/origin/*
19484 + url = git://git.denx.de/u-boot.git
19485 +[branch "master"]
19486 + remote = origin
19487 + merge = refs/heads/master
19488 diff -ruN u-boot-2015.01-rc3/.git/description u-boot/.git/description
19489 --- u-boot-2015.01-rc3/.git/description 1970-01-01 01:00:00.000000000 +0100
19490 +++ u-boot/.git/description 2015-01-01 17:34:05.785937163 +0100
19491 @@ -0,0 +1 @@
19492 +Unnamed repository; edit this file 'description' to name the repository.
19493 diff -ruN u-boot-2015.01-rc3/.git/HEAD u-boot/.git/HEAD
19494 --- u-boot-2015.01-rc3/.git/HEAD 1970-01-01 01:00:00.000000000 +0100
19495 +++ u-boot/.git/HEAD 2015-01-01 17:34:31.953508170 +0100
19496 @@ -0,0 +1 @@
19497 +ref: refs/heads/master
19498 diff -ruN u-boot-2015.01-rc3/.git/hooks/applypatch-msg.sample u-boot/.git/hooks/applypatch-msg.sample
19499 --- u-boot-2015.01-rc3/.git/hooks/applypatch-msg.sample 1970-01-01 01:00:00.000000000 +0100
19500 +++ u-boot/.git/hooks/applypatch-msg.sample 2015-01-01 17:34:05.793937033 +0100
19501 @@ -0,0 +1,15 @@
19502 +#!/bin/sh
19503 +#
19504 +# An example hook script to check the commit log message taken by
19505 +# applypatch from an e-mail message.
19506 +#
19507 +# The hook should exit with non-zero status after issuing an
19508 +# appropriate message if it wants to stop the commit. The hook is
19509 +# allowed to edit the commit message file.
19510 +#
19511 +# To enable this hook, rename this file to "applypatch-msg".
19512 +
19513 +. git-sh-setup
19514 +test -x "$GIT_DIR/hooks/commit-msg" &&
19515 + exec "$GIT_DIR/hooks/commit-msg" ${1+"$@"}
19516 +:
19517 diff -ruN u-boot-2015.01-rc3/.git/hooks/commit-msg.sample u-boot/.git/hooks/commit-msg.sample
19518 --- u-boot-2015.01-rc3/.git/hooks/commit-msg.sample 1970-01-01 01:00:00.000000000 +0100
19519 +++ u-boot/.git/hooks/commit-msg.sample 2015-01-01 17:34:05.793937033 +0100
19520 @@ -0,0 +1,24 @@
19521 +#!/bin/sh
19522 +#
19523 +# An example hook script to check the commit log message.
19524 +# Called by "git commit" with one argument, the name of the file
19525 +# that has the commit message. The hook should exit with non-zero
19526 +# status after issuing an appropriate message if it wants to stop the
19527 +# commit. The hook is allowed to edit the commit message file.
19528 +#
19529 +# To enable this hook, rename this file to "commit-msg".
19530 +
19531 +# Uncomment the below to add a Signed-off-by line to the message.
19532 +# Doing this in a hook is a bad idea in general, but the prepare-commit-msg
19533 +# hook is more suited to it.
19534 +#
19535 +# SOB=$(git var GIT_AUTHOR_IDENT | sed -n 's/^\(.*>\).*$/Signed-off-by: \1/p')
19536 +# grep -qs "^$SOB" "$1" || echo "$SOB" >> "$1"
19537 +
19538 +# This example catches duplicate Signed-off-by lines.
19539 +
19540 +test "" = "$(grep '^Signed-off-by: ' "$1" |
19541 + sort | uniq -c | sed -e '/^[ ]*1[ ]/d')" || {
19542 + echo >&2 Duplicate Signed-off-by lines.
19543 + exit 1
19544 +}
19545 diff -ruN u-boot-2015.01-rc3/.git/hooks/post-update.sample u-boot/.git/hooks/post-update.sample
19546 --- u-boot-2015.01-rc3/.git/hooks/post-update.sample 1970-01-01 01:00:00.000000000 +0100
19547 +++ u-boot/.git/hooks/post-update.sample 2015-01-01 17:34:05.797936967 +0100
19548 @@ -0,0 +1,8 @@
19549 +#!/bin/sh
19550 +#
19551 +# An example hook script to prepare a packed repository for use over
19552 +# dumb transports.
19553 +#
19554 +# To enable this hook, rename this file to "post-update".
19555 +
19556 +exec git update-server-info
19557 diff -ruN u-boot-2015.01-rc3/.git/hooks/pre-applypatch.sample u-boot/.git/hooks/pre-applypatch.sample
19558 --- u-boot-2015.01-rc3/.git/hooks/pre-applypatch.sample 1970-01-01 01:00:00.000000000 +0100
19559 +++ u-boot/.git/hooks/pre-applypatch.sample 2015-01-01 17:34:05.793937033 +0100
19560 @@ -0,0 +1,14 @@
19561 +#!/bin/sh
19562 +#
19563 +# An example hook script to verify what is about to be committed
19564 +# by applypatch from an e-mail message.
19565 +#
19566 +# The hook should exit with non-zero status after issuing an
19567 +# appropriate message if it wants to stop the commit.
19568 +#
19569 +# To enable this hook, rename this file to "pre-applypatch".
19570 +
19571 +. git-sh-setup
19572 +test -x "$GIT_DIR/hooks/pre-commit" &&
19573 + exec "$GIT_DIR/hooks/pre-commit" ${1+"$@"}
19574 +:
19575 diff -ruN u-boot-2015.01-rc3/.git/hooks/pre-commit.sample u-boot/.git/hooks/pre-commit.sample
19576 --- u-boot-2015.01-rc3/.git/hooks/pre-commit.sample 1970-01-01 01:00:00.000000000 +0100
19577 +++ u-boot/.git/hooks/pre-commit.sample 2015-01-01 17:34:05.793937033 +0100
19578 @@ -0,0 +1,50 @@
19579 +#!/bin/sh
19580 +#
19581 +# An example hook script to verify what is about to be committed.
19582 +# Called by "git commit" with no arguments. The hook should
19583 +# exit with non-zero status after issuing an appropriate message if
19584 +# it wants to stop the commit.
19585 +#
19586 +# To enable this hook, rename this file to "pre-commit".
19587 +
19588 +if git rev-parse --verify HEAD >/dev/null 2>&1
19589 +then
19590 + against=HEAD
19591 +else
19592 + # Initial commit: diff against an empty tree object
19593 + against=4b825dc642cb6eb9a060e54bf8d69288fbee4904
19594 +fi
19595 +
19596 +# If you want to allow non-ascii filenames set this variable to true.
19597 +allownonascii=$(git config hooks.allownonascii)
19598 +
19599 +# Redirect output to stderr.
19600 +exec 1>&2
19601 +
19602 +# Cross platform projects tend to avoid non-ascii filenames; prevent
19603 +# them from being added to the repository. We exploit the fact that the
19604 +# printable range starts at the space character and ends with tilde.
19605 +if [ "$allownonascii" != "true" ] &&
19606 + # Note that the use of brackets around a tr range is ok here, (it's
19607 + # even required, for portability to Solaris 10's /usr/bin/tr), since
19608 + # the square bracket bytes happen to fall in the designated range.
19609 + test $(git diff --cached --name-only --diff-filter=A -z $against |
19610 + LC_ALL=C tr -d '[ -~]\0' | wc -c) != 0
19611 +then
19612 + echo "Error: Attempt to add a non-ascii file name."
19613 + echo
19614 + echo "This can cause problems if you want to work"
19615 + echo "with people on other platforms."
19616 + echo
19617 + echo "To be portable it is advisable to rename the file ..."
19618 + echo
19619 + echo "If you know what you are doing you can disable this"
19620 + echo "check using:"
19621 + echo
19622 + echo " git config hooks.allownonascii true"
19623 + echo
19624 + exit 1
19625 +fi
19626 +
19627 +# If there are whitespace errors, print the offending file names and fail.
19628 +exec git diff-index --check --cached $against --
19629 diff -ruN u-boot-2015.01-rc3/.git/hooks/prepare-commit-msg.sample u-boot/.git/hooks/prepare-commit-msg.sample
19630 --- u-boot-2015.01-rc3/.git/hooks/prepare-commit-msg.sample 1970-01-01 01:00:00.000000000 +0100
19631 +++ u-boot/.git/hooks/prepare-commit-msg.sample 2015-01-01 17:34:05.801936901 +0100
19632 @@ -0,0 +1,36 @@
19633 +#!/bin/sh
19634 +#
19635 +# An example hook script to prepare the commit log message.
19636 +# Called by "git commit" with the name of the file that has the
19637 +# commit message, followed by the description of the commit
19638 +# message's source. The hook's purpose is to edit the commit
19639 +# message file. If the hook fails with a non-zero status,
19640 +# the commit is aborted.
19641 +#
19642 +# To enable this hook, rename this file to "prepare-commit-msg".
19643 +
19644 +# This hook includes three examples. The first comments out the
19645 +# "Conflicts:" part of a merge commit.
19646 +#
19647 +# The second includes the output of "git diff --name-status -r"
19648 +# into the message, just before the "git status" output. It is
19649 +# commented because it doesn't cope with --amend or with squashed
19650 +# commits.
19651 +#
19652 +# The third example adds a Signed-off-by line to the message, that can
19653 +# still be edited. This is rarely a good idea.
19654 +
19655 +case "$2,$3" in
19656 + merge,)
19657 + /usr/bin/perl -i.bak -ne 's/^/# /, s/^# #/#/ if /^Conflicts/ .. /#/; print' "$1" ;;
19658 +
19659 +# ,|template,)
19660 +# /usr/bin/perl -i.bak -pe '
19661 +# print "\n" . `git diff --cached --name-status -r`
19662 +# if /^#/ && $first++ == 0' "$1" ;;
19663 +
19664 + *) ;;
19665 +esac
19666 +
19667 +# SOB=$(git var GIT_AUTHOR_IDENT | sed -n 's/^\(.*>\).*$/Signed-off-by: \1/p')
19668 +# grep -qs "^$SOB" "$1" || echo "$SOB" >> "$1"
19669 diff -ruN u-boot-2015.01-rc3/.git/hooks/pre-rebase.sample u-boot/.git/hooks/pre-rebase.sample
19670 --- u-boot-2015.01-rc3/.git/hooks/pre-rebase.sample 1970-01-01 01:00:00.000000000 +0100
19671 +++ u-boot/.git/hooks/pre-rebase.sample 2015-01-01 17:34:05.801936901 +0100
19672 @@ -0,0 +1,169 @@
19673 +#!/bin/sh
19674 +#
19675 +# Copyright (c) 2006, 2008 Junio C Hamano
19676 +#
19677 +# The "pre-rebase" hook is run just before "git rebase" starts doing
19678 +# its job, and can prevent the command from running by exiting with
19679 +# non-zero status.
19680 +#
19681 +# The hook is called with the following parameters:
19682 +#
19683 +# $1 -- the upstream the series was forked from.
19684 +# $2 -- the branch being rebased (or empty when rebasing the current branch).
19685 +#
19686 +# This sample shows how to prevent topic branches that are already
19687 +# merged to 'next' branch from getting rebased, because allowing it
19688 +# would result in rebasing already published history.
19689 +
19690 +publish=next
19691 +basebranch="$1"
19692 +if test "$#" = 2
19693 +then
19694 + topic="refs/heads/$2"
19695 +else
19696 + topic=`git symbolic-ref HEAD` ||
19697 + exit 0 ;# we do not interrupt rebasing detached HEAD
19698 +fi
19699 +
19700 +case "$topic" in
19701 +refs/heads/??/*)
19702 + ;;
19703 +*)
19704 + exit 0 ;# we do not interrupt others.
19705 + ;;
19706 +esac
19707 +
19708 +# Now we are dealing with a topic branch being rebased
19709 +# on top of master. Is it OK to rebase it?
19710 +
19711 +# Does the topic really exist?
19712 +git show-ref -q "$topic" || {
19713 + echo >&2 "No such branch $topic"
19714 + exit 1
19715 +}
19716 +
19717 +# Is topic fully merged to master?
19718 +not_in_master=`git rev-list --pretty=oneline ^master "$topic"`
19719 +if test -z "$not_in_master"
19720 +then
19721 + echo >&2 "$topic is fully merged to master; better remove it."
19722 + exit 1 ;# we could allow it, but there is no point.
19723 +fi
19724 +
19725 +# Is topic ever merged to next? If so you should not be rebasing it.
19726 +only_next_1=`git rev-list ^master "^$topic" ${publish} | sort`
19727 +only_next_2=`git rev-list ^master ${publish} | sort`
19728 +if test "$only_next_1" = "$only_next_2"
19729 +then
19730 + not_in_topic=`git rev-list "^$topic" master`
19731 + if test -z "$not_in_topic"
19732 + then
19733 + echo >&2 "$topic is already up-to-date with master"
19734 + exit 1 ;# we could allow it, but there is no point.
19735 + else
19736 + exit 0
19737 + fi
19738 +else
19739 + not_in_next=`git rev-list --pretty=oneline ^${publish} "$topic"`
19740 + /usr/bin/perl -e '
19741 + my $topic = $ARGV[0];
19742 + my $msg = "* $topic has commits already merged to public branch:\n";
19743 + my (%not_in_next) = map {
19744 + /^([0-9a-f]+) /;
19745 + ($1 => 1);
19746 + } split(/\n/, $ARGV[1]);
19747 + for my $elem (map {
19748 + /^([0-9a-f]+) (.*)$/;
19749 + [$1 => $2];
19750 + } split(/\n/, $ARGV[2])) {
19751 + if (!exists $not_in_next{$elem->[0]}) {
19752 + if ($msg) {
19753 + print STDERR $msg;
19754 + undef $msg;
19755 + }
19756 + print STDERR " $elem->[1]\n";
19757 + }
19758 + }
19759 + ' "$topic" "$not_in_next" "$not_in_master"
19760 + exit 1
19761 +fi
19762 +
19763 +<<\DOC_END
19764 +
19765 +This sample hook safeguards topic branches that have been
19766 +published from being rewound.
19767 +
19768 +The workflow assumed here is:
19769 +
19770 + * Once a topic branch forks from "master", "master" is never
19771 + merged into it again (either directly or indirectly).
19772 +
19773 + * Once a topic branch is fully cooked and merged into "master",
19774 + it is deleted. If you need to build on top of it to correct
19775 + earlier mistakes, a new topic branch is created by forking at
19776 + the tip of the "master". This is not strictly necessary, but
19777 + it makes it easier to keep your history simple.
19778 +
19779 + * Whenever you need to test or publish your changes to topic
19780 + branches, merge them into "next" branch.
19781 +
19782 +The script, being an example, hardcodes the publish branch name
19783 +to be "next", but it is trivial to make it configurable via
19784 +$GIT_DIR/config mechanism.
19785 +
19786 +With this workflow, you would want to know:
19787 +
19788 +(1) ... if a topic branch has ever been merged to "next". Young
19789 + topic branches can have stupid mistakes you would rather
19790 + clean up before publishing, and things that have not been
19791 + merged into other branches can be easily rebased without
19792 + affecting other people. But once it is published, you would
19793 + not want to rewind it.
19794 +
19795 +(2) ... if a topic branch has been fully merged to "master".
19796 + Then you can delete it. More importantly, you should not
19797 + build on top of it -- other people may already want to
19798 + change things related to the topic as patches against your
19799 + "master", so if you need further changes, it is better to
19800 + fork the topic (perhaps with the same name) afresh from the
19801 + tip of "master".
19802 +
19803 +Let's look at this example:
19804 +
19805 + o---o---o---o---o---o---o---o---o---o "next"
19806 + / / / /
19807 + / a---a---b A / /
19808 + / / / /
19809 + / / c---c---c---c B /
19810 + / / / \ /
19811 + / / / b---b C \ /
19812 + / / / / \ /
19813 + ---o---o---o---o---o---o---o---o---o---o---o "master"
19814 +
19815 +
19816 +A, B and C are topic branches.
19817 +
19818 + * A has one fix since it was merged up to "next".
19819 +
19820 + * B has finished. It has been fully merged up to "master" and "next",
19821 + and is ready to be deleted.
19822 +
19823 + * C has not merged to "next" at all.
19824 +
19825 +We would want to allow C to be rebased, refuse A, and encourage
19826 +B to be deleted.
19827 +
19828 +To compute (1):
19829 +
19830 + git rev-list ^master ^topic next
19831 + git rev-list ^master next
19832 +
19833 + if these match, topic has not merged in next at all.
19834 +
19835 +To compute (2):
19836 +
19837 + git rev-list master..topic
19838 +
19839 + if this is empty, it is fully merged to "master".
19840 +
19841 +DOC_END
19842 diff -ruN u-boot-2015.01-rc3/.git/hooks/update.sample u-boot/.git/hooks/update.sample
19843 --- u-boot-2015.01-rc3/.git/hooks/update.sample 1970-01-01 01:00:00.000000000 +0100
19844 +++ u-boot/.git/hooks/update.sample 2015-01-01 17:34:05.793937033 +0100
19845 @@ -0,0 +1,128 @@
19846 +#!/bin/sh
19847 +#
19848 +# An example hook script to blocks unannotated tags from entering.
19849 +# Called by "git receive-pack" with arguments: refname sha1-old sha1-new
19850 +#
19851 +# To enable this hook, rename this file to "update".
19852 +#
19853 +# Config
19854 +# ------
19855 +# hooks.allowunannotated
19856 +# This boolean sets whether unannotated tags will be allowed into the
19857 +# repository. By default they won't be.
19858 +# hooks.allowdeletetag
19859 +# This boolean sets whether deleting tags will be allowed in the
19860 +# repository. By default they won't be.
19861 +# hooks.allowmodifytag
19862 +# This boolean sets whether a tag may be modified after creation. By default
19863 +# it won't be.
19864 +# hooks.allowdeletebranch
19865 +# This boolean sets whether deleting branches will be allowed in the
19866 +# repository. By default they won't be.
19867 +# hooks.denycreatebranch
19868 +# This boolean sets whether remotely creating branches will be denied
19869 +# in the repository. By default this is allowed.
19870 +#
19871 +
19872 +# --- Command line
19873 +refname="$1"
19874 +oldrev="$2"
19875 +newrev="$3"
19876 +
19877 +# --- Safety check
19878 +if [ -z "$GIT_DIR" ]; then
19879 + echo "Don't run this script from the command line." >&2
19880 + echo " (if you want, you could supply GIT_DIR then run" >&2
19881 + echo " $0 <ref> <oldrev> <newrev>)" >&2
19882 + exit 1
19883 +fi
19884 +
19885 +if [ -z "$refname" -o -z "$oldrev" -o -z "$newrev" ]; then
19886 + echo "Usage: $0 <ref> <oldrev> <newrev>" >&2
19887 + exit 1
19888 +fi
19889 +
19890 +# --- Config
19891 +allowunannotated=$(git config --bool hooks.allowunannotated)
19892 +allowdeletebranch=$(git config --bool hooks.allowdeletebranch)
19893 +denycreatebranch=$(git config --bool hooks.denycreatebranch)
19894 +allowdeletetag=$(git config --bool hooks.allowdeletetag)
19895 +allowmodifytag=$(git config --bool hooks.allowmodifytag)
19896 +
19897 +# check for no description
19898 +projectdesc=$(sed -e '1q' "$GIT_DIR/description")
19899 +case "$projectdesc" in
19900 +"Unnamed repository"* | "")
19901 + echo "*** Project description file hasn't been set" >&2
19902 + exit 1
19903 + ;;
19904 +esac
19905 +
19906 +# --- Check types
19907 +# if $newrev is 0000...0000, it's a commit to delete a ref.
19908 +zero="0000000000000000000000000000000000000000"
19909 +if [ "$newrev" = "$zero" ]; then
19910 + newrev_type=delete
19911 +else
19912 + newrev_type=$(git cat-file -t $newrev)
19913 +fi
19914 +
19915 +case "$refname","$newrev_type" in
19916 + refs/tags/*,commit)
19917 + # un-annotated tag
19918 + short_refname=${refname##refs/tags/}
19919 + if [ "$allowunannotated" != "true" ]; then
19920 + echo "*** The un-annotated tag, $short_refname, is not allowed in this repository" >&2
19921 + echo "*** Use 'git tag [ -a | -s ]' for tags you want to propagate." >&2
19922 + exit 1
19923 + fi
19924 + ;;
19925 + refs/tags/*,delete)
19926 + # delete tag
19927 + if [ "$allowdeletetag" != "true" ]; then
19928 + echo "*** Deleting a tag is not allowed in this repository" >&2
19929 + exit 1
19930 + fi
19931 + ;;
19932 + refs/tags/*,tag)
19933 + # annotated tag
19934 + if [ "$allowmodifytag" != "true" ] && git rev-parse $refname > /dev/null 2>&1
19935 + then
19936 + echo "*** Tag '$refname' already exists." >&2
19937 + echo "*** Modifying a tag is not allowed in this repository." >&2
19938 + exit 1
19939 + fi
19940 + ;;
19941 + refs/heads/*,commit)
19942 + # branch
19943 + if [ "$oldrev" = "$zero" -a "$denycreatebranch" = "true" ]; then
19944 + echo "*** Creating a branch is not allowed in this repository" >&2
19945 + exit 1
19946 + fi
19947 + ;;
19948 + refs/heads/*,delete)
19949 + # delete branch
19950 + if [ "$allowdeletebranch" != "true" ]; then
19951 + echo "*** Deleting a branch is not allowed in this repository" >&2
19952 + exit 1
19953 + fi
19954 + ;;
19955 + refs/remotes/*,commit)
19956 + # tracking branch
19957 + ;;
19958 + refs/remotes/*,delete)
19959 + # delete tracking branch
19960 + if [ "$allowdeletebranch" != "true" ]; then
19961 + echo "*** Deleting a tracking branch is not allowed in this repository" >&2
19962 + exit 1
19963 + fi
19964 + ;;
19965 + *)
19966 + # Anything else (is there anything else?)
19967 + echo "*** Update hook: unknown type of update to ref $refname of type $newrev_type" >&2
19968 + exit 1
19969 + ;;
19970 +esac
19971 +
19972 +# --- Finished
19973 +exit 0
19974 Binary files u-boot-2015.01-rc3/.git/index and u-boot/.git/index differ
19975 diff -ruN u-boot-2015.01-rc3/.git/info/exclude u-boot/.git/info/exclude
19976 --- u-boot-2015.01-rc3/.git/info/exclude 1970-01-01 01:00:00.000000000 +0100
19977 +++ u-boot/.git/info/exclude 2015-01-01 17:34:05.789937097 +0100
19978 @@ -0,0 +1,6 @@
19979 +# git ls-files --others --exclude-from=.git/info/exclude
19980 +# Lines that start with '#' are comments.
19981 +# For a project mostly in C, the following would be a good set of
19982 +# exclude patterns (uncomment them if you want to use them):
19983 +# *.[oa]
19984 +# *~
19985 diff -ruN u-boot-2015.01-rc3/.git/logs/HEAD u-boot/.git/logs/HEAD
19986 --- u-boot-2015.01-rc3/.git/logs/HEAD 1970-01-01 01:00:00.000000000 +0100
19987 +++ u-boot/.git/logs/HEAD 2015-01-01 17:34:31.953508170 +0100
19988 @@ -0,0 +1 @@
19989 +0000000000000000000000000000000000000000 125738e819a3b9d15210794b3dcef9f4d9bcf866 Zoltan HERPAI <wigyori@uid0.hu> 1420130071 +0100 clone: from git://git.denx.de/u-boot.git
19990 diff -ruN u-boot-2015.01-rc3/.git/logs/refs/heads/master u-boot/.git/logs/refs/heads/master
19991 --- u-boot-2015.01-rc3/.git/logs/refs/heads/master 1970-01-01 01:00:00.000000000 +0100
19992 +++ u-boot/.git/logs/refs/heads/master 2015-01-01 17:34:31.953508170 +0100
19993 @@ -0,0 +1 @@
19994 +0000000000000000000000000000000000000000 125738e819a3b9d15210794b3dcef9f4d9bcf866 Zoltan HERPAI <wigyori@uid0.hu> 1420130071 +0100 clone: from git://git.denx.de/u-boot.git
19995 diff -ruN u-boot-2015.01-rc3/.git/logs/refs/remotes/origin/HEAD u-boot/.git/logs/refs/remotes/origin/HEAD
19996 --- u-boot-2015.01-rc3/.git/logs/refs/remotes/origin/HEAD 1970-01-01 01:00:00.000000000 +0100
19997 +++ u-boot/.git/logs/refs/remotes/origin/HEAD 2015-01-01 17:34:31.953508170 +0100
19998 @@ -0,0 +1 @@
19999 +0000000000000000000000000000000000000000 125738e819a3b9d15210794b3dcef9f4d9bcf866 Zoltan HERPAI <wigyori@uid0.hu> 1420130071 +0100 clone: from git://git.denx.de/u-boot.git
20000 Binary files u-boot-2015.01-rc3/.git/objects/pack/pack-e62dd83e4128e234ff5dabb586722d23d1bae06c.idx and u-boot/.git/objects/pack/pack-e62dd83e4128e234ff5dabb586722d23d1bae06c.idx differ
20001 Binary files u-boot-2015.01-rc3/.git/objects/pack/pack-e62dd83e4128e234ff5dabb586722d23d1bae06c.pack and u-boot/.git/objects/pack/pack-e62dd83e4128e234ff5dabb586722d23d1bae06c.pack differ
20002 diff -ruN u-boot-2015.01-rc3/.git/packed-refs u-boot/.git/packed-refs
20003 --- u-boot-2015.01-rc3/.git/packed-refs 1970-01-01 01:00:00.000000000 +0100
20004 +++ u-boot/.git/packed-refs 2015-01-01 17:34:31.865509612 +0100
20005 @@ -0,0 +1,388 @@
20006 +# pack-refs with: peeled
20007 +125738e819a3b9d15210794b3dcef9f4d9bcf866 refs/remotes/origin/master
20008 +ece0d370144fdecb6f3ed5738ffe96f5b12f9e96 refs/remotes/origin/next
20009 +cd5b2b9941d5b6f6596787ebdb03c215d91fc44d refs/remotes/origin/origin
20010 +f20393c5e787b3776c179d20f82a86bda124d651 refs/remotes/origin/u-boot-2009.11.y
20011 +e8ae0fa5edd152b2b29c470b88429be4cdcd2c46 refs/remotes/origin/u-boot-2013.01.y
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20341 +^68c517eafcb060aa8ef92ed2620f0f41c5275d89
20342 +2d65a6b5a3f069ea92ee33c1c925d79610af12d0 refs/tags/v2013.10
20343 +^183acb700378a8cfc5d50a01a65de93fb2c24586
20344 +ff92b6e5cf51421163e4ea1d29004eeffd6b6a99 refs/tags/v2013.10-rc1
20345 +^40a60c6e8bdd00330310eaa351c9391e74d0bc2c
20346 +bab9dca36165be177a74ff31eabda75f94e26599 refs/tags/v2013.10-rc2
20347 +^fb18fa95a14ae875ef0a5421cd9fecc00c7c3a4c
20348 +c1d48b0698c9b7ddf342f5808d3a4a973317c2dc refs/tags/v2013.10-rc3
20349 +^46ef4faed18196472eb95216b2f74c1397ecf024
20350 +c99ec7332286341649cd5337eb1bbeabdff13a3a refs/tags/v2013.10-rc4
20351 +^0c5274e6f3231a3a28dafc1204b3f71a3534c520
20352 +e3fbee81eccebfd6c91609f6bc4b4aec3a017131 refs/tags/v2014.01
20353 +^b44bd2c73c4cfb6e3b9e7f8cf987e8e39aa74a0b
20354 +0b3dd5f23cf6eeb9ec84da8c77d8c7d1e7d23680 refs/tags/v2014.01-rc1
20355 +^d19ad726bcd5d9106f7ba9c750462fcc369f1020
20356 +e68eecb2d896ddef422984ae6d52793099b74e9a refs/tags/v2014.01-rc2
20357 +^fd44194945714a478fab6407c04453caaef0bac9
20358 +5f60aba0d3f6b827de8dc7e0850c1050f655b572 refs/tags/v2014.01-rc3
20359 +^cddb6b8304bfbc34f43920051256de7fe6c4c0ab
20360 +5b3ba909f4f881add7756d820f2eb67d3e31b112 refs/tags/v2014.04
20361 +^dda0dbfc69f3d560c87f5be85f127ed862ea6721
20362 +9574fdf82ff62a7086b257c89c01bde937a0c45e refs/tags/v2014.04-rc1
20363 +^0a8e823ad0c5a602c93c2e8a54caf622ade6d3fb
20364 +4017dac218f34783977c36af8f65984a57ace7e3 refs/tags/v2014.04-rc2
20365 +^8ee950dd273aef6a074d41bf2ee4ef11d6f848fb
20366 +ba34c9404626f23a41ef07bcdf3e7e5cbf133b82 refs/tags/v2014.04-rc3
20367 +^c494eaf409cb8db9a5a513e9bdfac20b7a83daca
20368 +590a74953a76f2b4cc552bd85b475ea54ba02f66 refs/tags/v2014.07
20369 +^524123a70761110c5cf3ccc5f52f6d4da071b959
20370 +2db93972561773246cb7498bf1ee73e3d34fa697 refs/tags/v2014.07-rc1
20371 +^3e41c54ad8099951d57c3c5a0f5ebc6e8becf70c
20372 +3472f37f1ce4d2737476b4ec7c768c04afe20046 refs/tags/v2014.07-rc2
20373 +^0116f40bbc269c57566d69e0db8cb9da2e194d33
20374 +d3b233a6a320688e22419134d6f7bb23e9c0332b refs/tags/v2014.07-rc3
20375 +^76b21026ceb5a6a83fc53b0ecdf425f240318022
20376 +9019e02a9d98f6788035ea352289a5afdbbf133d refs/tags/v2014.07-rc4
20377 +^a176ff0705351bf6d993a8f15e081bfa2ba2e1af
20378 +d96885d68127e270d16484c0fbc252953a2bf2e8 refs/tags/v2014.10
20379 +^c43fd23cf619856b0763a64a6a3bcf3663058c49
20380 +49fe41ad45d09cf083db39ce4a2653d903fbe1a7 refs/tags/v2014.10-rc1
20381 +^e76b933e02e1b38e48754c435e9dba1c0deeb3c6
20382 +8d6f7381cd8f915f6599044b1848a8a6a7faff02 refs/tags/v2014.10-rc2
20383 +^d6c1ffc7d23f4fe4ae8c91101861055b8e1501b6
20384 +1f254ba729e8b21ccba3c9caf02bf358a0e8d136 refs/tags/v2014.10-rc3
20385 +^742de9076e8a8f44b77794b43e6175d86b897996
20386 +a013989f700d43f79af64fb74b05b2f333a60c7d refs/tags/v2015.01-rc1
20387 +^9906090f527153afddc5aa64d37cb5f89c6ee129
20388 +77831f3e5f83e12b4e7df418e7d43977b189031d refs/tags/v2015.01-rc2
20389 +^2a82ec77d27ef5f860a107c4b764643a655dceeb
20390 +ecb091a9035a9c89a57b7fbd6cdf1db1c5ee9a80 refs/tags/v2015.01-rc3
20391 +^32fdf0e4d82bdca5d64d86330e461e59685f9959
20392 +9305547115a8073900fec5e8f3938b93c675f2c2 refs/tags/v2015.01-rc4
20393 +^125738e819a3b9d15210794b3dcef9f4d9bcf866
20394 diff -ruN u-boot-2015.01-rc3/.git/refs/heads/master u-boot/.git/refs/heads/master
20395 --- u-boot-2015.01-rc3/.git/refs/heads/master 1970-01-01 01:00:00.000000000 +0100
20396 +++ u-boot/.git/refs/heads/master 2015-01-01 17:34:31.953508170 +0100
20397 @@ -0,0 +1 @@
20398 +125738e819a3b9d15210794b3dcef9f4d9bcf866
20399 diff -ruN u-boot-2015.01-rc3/.git/refs/remotes/origin/HEAD u-boot/.git/refs/remotes/origin/HEAD
20400 --- u-boot-2015.01-rc3/.git/refs/remotes/origin/HEAD 1970-01-01 01:00:00.000000000 +0100
20401 +++ u-boot/.git/refs/remotes/origin/HEAD 2015-01-01 17:34:31.937508433 +0100
20402 @@ -0,0 +1 @@
20403 +ref: refs/remotes/origin/master
20404 diff -ruN u-boot-2015.01-rc3/include/common.h u-boot/include/common.h
20405 --- u-boot-2015.01-rc3/include/common.h 2014-12-08 22:35:08.000000000 +0100
20406 +++ u-boot/include/common.h 2015-01-01 17:34:32.757494989 +0100
20407 @@ -70,12 +70,6 @@
20408 #ifdef CONFIG_4xx
20409 #include <asm/ppc4xx.h>
20410 #endif
20411 -#ifdef CONFIG_ARM
20412 -#define asmlinkage /* nothing */
20413 -#endif
20414 -#ifdef CONFIG_X86
20415 -#define asmlinkage __attribute__((regparm(0)))
20416 -#endif
20417 #ifdef CONFIG_BLACKFIN
20418 #include <asm/blackfin.h>
20419 #endif
20420 diff -ruN u-boot-2015.01-rc3/include/config_fallbacks.h u-boot/include/config_fallbacks.h
20421 --- u-boot-2015.01-rc3/include/config_fallbacks.h 2014-12-08 22:35:08.000000000 +0100
20422 +++ u-boot/include/config_fallbacks.h 2015-01-01 17:34:32.757494989 +0100
20423 @@ -79,6 +79,10 @@
20424 #define CONFIG_SYS_PROMPT "=> "
20425 #endif
20426
20427 +#ifndef CONFIG_SYS_PBSIZE
20428 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 128)
20429 +#endif
20430 +
20431 #ifndef CONFIG_FIT_SIGNATURE
20432 #define CONFIG_IMAGE_FORMAT_LEGACY
20433 #endif
20434 @@ -87,4 +91,10 @@
20435 #undef CONFIG_IMAGE_FORMAT_LEGACY
20436 #endif
20437
20438 +#ifdef CONFIG_DM_I2C
20439 +# ifdef CONFIG_SYS_I2C
20440 +# error "Cannot define CONFIG_SYS_I2C when CONFIG_DM_I2C is used"
20441 +# endif
20442 +#endif
20443 +
20444 #endif /* __CONFIG_FALLBACKS_H */
20445 diff -ruN u-boot-2015.01-rc3/include/configs/alt.h u-boot/include/configs/alt.h
20446 --- u-boot-2015.01-rc3/include/configs/alt.h 2014-12-08 22:35:08.000000000 +0100
20447 +++ u-boot/include/configs/alt.h 2015-01-01 17:34:32.777494661 +0100
20448 @@ -95,4 +95,23 @@
20449 #define CONFIG_USB_EHCI_RMOBILE
20450 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
20451
20452 +/* MMCIF */
20453 +#define CONFIG_MMC
20454 +#define CONFIG_GENERIC_MMC
20455 +#define CONFIG_CMD_MMC
20456 +
20457 +#define CONFIG_SH_MMCIF
20458 +#define CONFIG_SH_MMCIF_ADDR 0xee200000
20459 +#define CONFIG_SH_MMCIF_CLK 48000000
20460 +
20461 +/* Module stop status bits */
20462 +/* INTC-RT */
20463 +#define CONFIG_SMSTP0_ENA 0x00400000
20464 +/* MSIF */
20465 +#define CONFIG_SMSTP2_ENA 0x00002000
20466 +/* INTC-SYS, IRQC */
20467 +#define CONFIG_SMSTP4_ENA 0x00000180
20468 +/* SCIF2 */
20469 +#define CONFIG_SMSTP7_ENA 0x00080000
20470 +
20471 #endif /* __ALT_H */
20472 diff -ruN u-boot-2015.01-rc3/include/configs/apalis_t30.h u-boot/include/configs/apalis_t30.h
20473 --- u-boot-2015.01-rc3/include/configs/apalis_t30.h 2014-12-08 22:35:08.000000000 +0100
20474 +++ u-boot/include/configs/apalis_t30.h 2015-01-01 17:34:32.777494661 +0100
20475 @@ -26,10 +26,7 @@
20476
20477 /* I2C */
20478 #define CONFIG_SYS_I2C_TEGRA
20479 -#define CONFIG_SYS_I2C_INIT_BOARD
20480 -#define CONFIG_SYS_I2C_SPEED 100000
20481 #define CONFIG_CMD_I2C
20482 -#define CONFIG_SYS_I2C
20483
20484 /* SD/MMC */
20485 #define CONFIG_MMC
20486 diff -ruN u-boot-2015.01-rc3/include/configs/B4860QDS.h u-boot/include/configs/B4860QDS.h
20487 --- u-boot-2015.01-rc3/include/configs/B4860QDS.h 2014-12-08 22:35:08.000000000 +0100
20488 +++ u-boot/include/configs/B4860QDS.h 2015-01-01 17:34:32.757494989 +0100
20489 @@ -641,6 +641,14 @@
20490 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
20491 #endif
20492 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
20493 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
20494 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
20495 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
20496 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
20497 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
20498 + CONFIG_SYS_BMAN_CENA_SIZE)
20499 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
20500 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
20501 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
20502 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
20503 #ifdef CONFIG_PHYS_64BIT
20504 @@ -649,6 +657,14 @@
20505 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
20506 #endif
20507 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
20508 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
20509 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
20510 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
20511 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
20512 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
20513 + CONFIG_SYS_QMAN_CENA_SIZE)
20514 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
20515 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
20516
20517 #define CONFIG_SYS_DPAA_FMAN
20518
20519 diff -ruN u-boot-2015.01-rc3/include/configs/beaver.h u-boot/include/configs/beaver.h
20520 --- u-boot-2015.01-rc3/include/configs/beaver.h 2014-12-08 22:35:08.000000000 +0100
20521 +++ u-boot/include/configs/beaver.h 2015-01-01 17:34:32.781494596 +0100
20522 @@ -40,10 +40,7 @@
20523
20524 /* I2C */
20525 #define CONFIG_SYS_I2C_TEGRA
20526 -#define CONFIG_SYS_I2C_INIT_BOARD
20527 -#define CONFIG_SYS_I2C_SPEED 100000
20528 #define CONFIG_CMD_I2C
20529 -#define CONFIG_SYS_I2C
20530
20531 /* SD/MMC */
20532 #define CONFIG_MMC
20533 diff -ruN u-boot-2015.01-rc3/include/configs/BSC9131RDB.h u-boot/include/configs/BSC9131RDB.h
20534 --- u-boot-2015.01-rc3/include/configs/BSC9131RDB.h 2014-12-08 22:35:08.000000000 +0100
20535 +++ u-boot/include/configs/BSC9131RDB.h 2015-01-01 17:34:32.757494989 +0100
20536 @@ -11,6 +11,9 @@
20537 #ifndef __CONFIG_H
20538 #define __CONFIG_H
20539
20540 +#define CONFIG_SYS_GENERIC_BOARD
20541 +#define CONFIG_DISPLAY_BOARDINFO
20542 +
20543 #ifdef CONFIG_BSC9131RDB
20544 #define CONFIG_BSC9131
20545 #define CONFIG_NAND_FSL_IFC
20546 diff -ruN u-boot-2015.01-rc3/include/configs/BSC9132QDS.h u-boot/include/configs/BSC9132QDS.h
20547 --- u-boot-2015.01-rc3/include/configs/BSC9132QDS.h 2014-12-08 22:35:08.000000000 +0100
20548 +++ u-boot/include/configs/BSC9132QDS.h 2015-01-01 17:34:32.761494923 +0100
20549 @@ -11,6 +11,9 @@
20550 #ifndef __CONFIG_H
20551 #define __CONFIG_H
20552
20553 +#define CONFIG_SYS_GENERIC_BOARD
20554 +#define CONFIG_DISPLAY_BOARDINFO
20555 +
20556 #ifdef CONFIG_BSC9132QDS
20557 #define CONFIG_BSC9132
20558 #endif
20559 diff -ruN u-boot-2015.01-rc3/include/configs/cardhu.h u-boot/include/configs/cardhu.h
20560 --- u-boot-2015.01-rc3/include/configs/cardhu.h 2014-12-08 22:35:08.000000000 +0100
20561 +++ u-boot/include/configs/cardhu.h 2015-01-01 17:34:32.785494529 +0100
20562 @@ -43,12 +43,7 @@
20563
20564 /* I2C */
20565 #define CONFIG_SYS_I2C_TEGRA
20566 -#define CONFIG_SYS_I2C_INIT_BOARD
20567 -#define CONFIG_I2C_MULTI_BUS
20568 -#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
20569 -#define CONFIG_SYS_I2C_SPEED 100000
20570 #define CONFIG_CMD_I2C
20571 -#define CONFIG_SYS_I2C
20572
20573 /* SD/MMC */
20574 #define CONFIG_MMC
20575 diff -ruN u-boot-2015.01-rc3/include/configs/chromebook_link.h u-boot/include/configs/chromebook_link.h
20576 --- u-boot-2015.01-rc3/include/configs/chromebook_link.h 2014-12-08 22:35:08.000000000 +0100
20577 +++ u-boot/include/configs/chromebook_link.h 2015-01-01 17:34:32.785494529 +0100
20578 @@ -25,10 +25,10 @@
20579
20580 #define CONFIG_X86_RESET_VECTOR
20581 #define CONFIG_NR_DRAM_BANKS 8
20582 -#define CONFIG_X86_MRC_START 0xfffa0000
20583 +#define CONFIG_X86_MRC_ADDR 0xfffa0000
20584 #define CONFIG_CACHE_MRC_SIZE_KB 512
20585
20586 -#define CONFIG_COREBOOT_SERIAL
20587 +#define CONFIG_X86_SERIAL
20588
20589 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
20590 PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
20591 @@ -39,7 +39,7 @@
20592 {PCI_VENDOR_ID_INTEL, \
20593 PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
20594
20595 -#define CONFIG_X86_OPTION_ROM_FILENAME pci8086,0166.bin
20596 +#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin
20597 #define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
20598 #define CONFIG_VIDEO_X86
20599
20600 diff -ruN u-boot-2015.01-rc3/include/configs/colibri_t30.h u-boot/include/configs/colibri_t30.h
20601 --- u-boot-2015.01-rc3/include/configs/colibri_t30.h 2014-12-08 22:35:08.000000000 +0100
20602 +++ u-boot/include/configs/colibri_t30.h 2015-01-01 17:34:32.785494529 +0100
20603 @@ -25,10 +25,7 @@
20604
20605 /* I2C */
20606 #define CONFIG_SYS_I2C_TEGRA
20607 -#define CONFIG_SYS_I2C_INIT_BOARD
20608 -#define CONFIG_SYS_I2C_SPEED 100000
20609 #define CONFIG_CMD_I2C
20610 -#define CONFIG_SYS_I2C
20611
20612 /* SD/MMC */
20613 #define CONFIG_MMC
20614 diff -ruN u-boot-2015.01-rc3/include/configs/coreboot.h u-boot/include/configs/coreboot.h
20615 --- u-boot-2015.01-rc3/include/configs/coreboot.h 2014-12-08 22:35:08.000000000 +0100
20616 +++ u-boot/include/configs/coreboot.h 2015-01-01 17:34:32.785494529 +0100
20617 @@ -49,7 +49,7 @@
20618 {PCI_VENDOR_ID_INTEL, \
20619 PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
20620
20621 -#define CONFIG_COREBOOT_SERIAL
20622 +#define CONFIG_X86_SERIAL
20623
20624 #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
20625 "stdout=vga,serial,cbmem\0" \
20626 diff -ruN u-boot-2015.01-rc3/include/configs/corenet_ds.h u-boot/include/configs/corenet_ds.h
20627 --- u-boot-2015.01-rc3/include/configs/corenet_ds.h 2014-12-08 22:35:08.000000000 +0100
20628 +++ u-boot/include/configs/corenet_ds.h 2015-01-01 17:34:32.785494529 +0100
20629 @@ -495,6 +495,14 @@
20630 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
20631 #endif
20632 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
20633 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
20634 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
20635 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
20636 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
20637 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
20638 + CONFIG_SYS_BMAN_CENA_SIZE)
20639 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
20640 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
20641 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
20642 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
20643 #ifdef CONFIG_PHYS_64BIT
20644 @@ -503,6 +511,14 @@
20645 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
20646 #endif
20647 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
20648 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
20649 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
20650 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
20651 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
20652 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
20653 + CONFIG_SYS_QMAN_CENA_SIZE)
20654 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
20655 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
20656
20657 #define CONFIG_SYS_DPAA_FMAN
20658 #define CONFIG_SYS_DPAA_PME
20659 diff -ruN u-boot-2015.01-rc3/include/configs/crownbay.h u-boot/include/configs/crownbay.h
20660 --- u-boot-2015.01-rc3/include/configs/crownbay.h 1970-01-01 01:00:00.000000000 +0100
20661 +++ u-boot/include/configs/crownbay.h 2015-01-01 17:34:32.785494529 +0100
20662 @@ -0,0 +1,61 @@
20663 +/*
20664 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
20665 + *
20666 + * SPDX-License-Identifier: GPL-2.0+
20667 + */
20668 +
20669 +/*
20670 + * board/config.h - configuration options, board specific
20671 + */
20672 +
20673 +#ifndef __CONFIG_H
20674 +#define __CONFIG_H
20675 +
20676 +#include <configs/x86-common.h>
20677 +
20678 +#define CONFIG_SYS_MONITOR_LEN (1 << 20)
20679 +#define CONFIG_SYS_X86_START16 0xfffff800
20680 +#define CONFIG_BOARD_EARLY_INIT_F
20681 +
20682 +#define CONFIG_X86_RESET_VECTOR
20683 +#define CONFIG_NR_DRAM_BANKS 1
20684 +
20685 +#define CONFIG_X86_SERIAL
20686 +#define CONFIG_SMSC_LPC47M
20687 +
20688 +#define CONFIG_PCI_MEM_BUS 0x40000000
20689 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
20690 +#define CONFIG_PCI_MEM_SIZE 0x80000000
20691 +
20692 +#define CONFIG_PCI_PREF_BUS 0xc0000000
20693 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
20694 +#define CONFIG_PCI_PREF_SIZE 0x20000000
20695 +
20696 +#define CONFIG_PCI_IO_BUS 0x2000
20697 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
20698 +#define CONFIG_PCI_IO_SIZE 0xe000
20699 +
20700 +#define CONFIG_SYS_EARLY_PCI_INIT
20701 +#define CONFIG_PCI_PNP
20702 +#define CONFIG_E1000
20703 +
20704 +#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
20705 + "stdout=serial\0" \
20706 + "stderr=serial\0"
20707 +
20708 +#define CONFIG_SCSI_DEV_LIST \
20709 + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
20710 +
20711 +#define CONFIG_SPI_FLASH_SST
20712 +
20713 +#define CONFIG_MMC
20714 +#define CONFIG_SDHCI
20715 +#define CONFIG_GENERIC_MMC
20716 +#define CONFIG_MMC_SDMA
20717 +#define CONFIG_CMD_MMC
20718 +
20719 +/* Video is not supported */
20720 +#undef CONFIG_VIDEO
20721 +#undef CONFIG_CFB_CONSOLE
20722 +
20723 +#endif /* __CONFIG_H */
20724 diff -ruN u-boot-2015.01-rc3/include/configs/dalmore.h u-boot/include/configs/dalmore.h
20725 --- u-boot-2015.01-rc3/include/configs/dalmore.h 2014-12-08 22:35:08.000000000 +0100
20726 +++ u-boot/include/configs/dalmore.h 2015-01-01 17:34:32.789494465 +0100
20727 @@ -36,12 +36,7 @@
20728
20729 /* I2C */
20730 #define CONFIG_SYS_I2C_TEGRA
20731 -#define CONFIG_SYS_I2C_INIT_BOARD
20732 -#define CONFIG_I2C_MULTI_BUS
20733 -#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
20734 -#define CONFIG_SYS_I2C_SPEED 100000
20735 #define CONFIG_CMD_I2C
20736 -#define CONFIG_SYS_I2C
20737
20738 /* SD/MMC */
20739 #define CONFIG_MMC
20740 diff -ruN u-boot-2015.01-rc3/include/configs/gose.h u-boot/include/configs/gose.h
20741 --- u-boot-2015.01-rc3/include/configs/gose.h 2014-12-08 22:35:08.000000000 +0100
20742 +++ u-boot/include/configs/gose.h 2015-01-01 17:34:32.793494399 +0100
20743 @@ -91,4 +91,14 @@
20744 #define CONFIG_USB_EHCI_RMOBILE
20745 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
20746
20747 +/* Module stop status bits */
20748 +/* INTC-RT */
20749 +#define CONFIG_SMSTP0_ENA 0x00400000
20750 +/* MSIF */
20751 +#define CONFIG_SMSTP2_ENA 0x00002000
20752 +/* INTC-SYS, IRQC */
20753 +#define CONFIG_SMSTP4_ENA 0x00000180
20754 +/* SCIF0 */
20755 +#define CONFIG_SMSTP7_ENA 0x00200000
20756 +
20757 #endif /* __GOSE_H */
20758 diff -ruN u-boot-2015.01-rc3/include/configs/jetson-tk1.h u-boot/include/configs/jetson-tk1.h
20759 --- u-boot-2015.01-rc3/include/configs/jetson-tk1.h 2014-12-08 22:35:08.000000000 +0100
20760 +++ u-boot/include/configs/jetson-tk1.h 2015-01-01 17:34:32.797494333 +0100
20761 @@ -25,12 +25,7 @@
20762
20763 /* I2C */
20764 #define CONFIG_SYS_I2C_TEGRA
20765 -#define CONFIG_SYS_I2C_INIT_BOARD
20766 -#define CONFIG_I2C_MULTI_BUS
20767 -#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
20768 -#define CONFIG_SYS_I2C_SPEED 100000
20769 #define CONFIG_CMD_I2C
20770 -#define CONFIG_SYS_I2C
20771
20772 /* SD/MMC */
20773 #define CONFIG_MMC
20774 diff -ruN u-boot-2015.01-rc3/include/configs/km/kmp204x-common.h u-boot/include/configs/km/kmp204x-common.h
20775 --- u-boot-2015.01-rc3/include/configs/km/kmp204x-common.h 2014-12-08 22:35:08.000000000 +0100
20776 +++ u-boot/include/configs/km/kmp204x-common.h 2015-01-01 17:34:32.797494333 +0100
20777 @@ -339,10 +339,26 @@
20778 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
20779 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
20780 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
20781 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
20782 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
20783 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
20784 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
20785 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
20786 + CONFIG_SYS_BMAN_CENA_SIZE)
20787 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
20788 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
20789 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
20790 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
20791 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
20792 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
20793 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
20794 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
20795 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
20796 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
20797 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
20798 + CONFIG_SYS_QMAN_CENA_SIZE)
20799 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
20800 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
20801
20802 #define CONFIG_SYS_DPAA_FMAN
20803 #define CONFIG_SYS_DPAA_PME
20804 diff -ruN u-boot-2015.01-rc3/include/configs/koelsch.h u-boot/include/configs/koelsch.h
20805 --- u-boot-2015.01-rc3/include/configs/koelsch.h 2014-12-08 22:35:08.000000000 +0100
20806 +++ u-boot/include/configs/koelsch.h 2015-01-01 17:34:32.797494333 +0100
20807 @@ -92,4 +92,15 @@
20808 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
20809 #define CONFIG_USB_STORAGE
20810
20811 +
20812 +/* Module stop status bits */
20813 +/* INTC-RT */
20814 +#define CONFIG_SMSTP0_ENA 0x00400000
20815 +/* MSIF*/
20816 +#define CONFIG_SMSTP2_ENA 0x00002000
20817 +/* INTC-SYS, IRQC */
20818 +#define CONFIG_SMSTP4_ENA 0x00000180
20819 +/* SCIF0 */
20820 +#define CONFIG_SMSTP7_ENA 0x00200000
20821 +
20822 #endif /* __KOELSCH_H */
20823 diff -ruN u-boot-2015.01-rc3/include/configs/lager.h u-boot/include/configs/lager.h
20824 --- u-boot-2015.01-rc3/include/configs/lager.h 2014-12-08 22:35:08.000000000 +0100
20825 +++ u-boot/include/configs/lager.h 2015-01-01 17:34:32.797494333 +0100
20826 @@ -93,4 +93,23 @@
20827 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
20828 #define CONFIG_USB_STORAGE
20829
20830 +/* MMC */
20831 +#define CONFIG_MMC
20832 +#define CONFIG_CMD_MMC
20833 +#define CONFIG_GENERIC_MMC
20834 +
20835 +#define CONFIG_SH_MMCIF
20836 +#define CONFIG_SH_MMCIF_ADDR 0xEE220000
20837 +#define CONFIG_SH_MMCIF_CLK 97500000
20838 +
20839 +/* Module stop status bits */
20840 +/* INTC-RT */
20841 +#define CONFIG_SMSTP0_ENA 0x00400000
20842 +/* MSIF */
20843 +#define CONFIG_SMSTP2_ENA 0x00002000
20844 +/* INTC-SYS, IRQC */
20845 +#define CONFIG_SMSTP4_ENA 0x00000180
20846 +/* SCIF0 */
20847 +#define CONFIG_SMSTP7_ENA 0x00200000
20848 +
20849 #endif /* __LAGER_H */
20850 diff -ruN u-boot-2015.01-rc3/include/configs/ls1021aqds.h u-boot/include/configs/ls1021aqds.h
20851 --- u-boot-2015.01-rc3/include/configs/ls1021aqds.h 2014-12-08 22:35:08.000000000 +0100
20852 +++ u-boot/include/configs/ls1021aqds.h 2015-01-01 17:34:32.797494333 +0100
20853 @@ -37,8 +37,85 @@
20854 unsigned long get_board_ddr_clk(void);
20855 #endif
20856
20857 +#ifdef CONFIG_QSPI_BOOT
20858 +#define CONFIG_SYS_CLK_FREQ 100000000
20859 +#define CONFIG_DDR_CLK_FREQ 100000000
20860 +#define CONFIG_QIXIS_I2C_ACCESS
20861 +#else
20862 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
20863 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
20864 +#endif
20865 +
20866 +#ifdef CONFIG_RAMBOOT_PBL
20867 +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
20868 +#endif
20869 +
20870 +#ifdef CONFIG_SD_BOOT
20871 +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
20872 +#define CONFIG_SPL_FRAMEWORK
20873 +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
20874 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
20875 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
20876 +#define CONFIG_SPL_ENV_SUPPORT
20877 +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
20878 +#define CONFIG_SPL_I2C_SUPPORT
20879 +#define CONFIG_SPL_WATCHDOG_SUPPORT
20880 +#define CONFIG_SPL_SERIAL_SUPPORT
20881 +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
20882 +#define CONFIG_SPL_MMC_SUPPORT
20883 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
20884 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
20885 +
20886 +#define CONFIG_SPL_TEXT_BASE 0x10000000
20887 +#define CONFIG_SPL_MAX_SIZE 0x1a000
20888 +#define CONFIG_SPL_STACK 0x1001d000
20889 +#define CONFIG_SPL_PAD_TO 0x1c000
20890 +#define CONFIG_SYS_TEXT_BASE 0x82000000
20891 +
20892 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
20893 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
20894 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000
20895 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
20896 +#define CONFIG_SYS_MONITOR_LEN 0x80000
20897 +#endif
20898 +
20899 +#ifdef CONFIG_QSPI_BOOT
20900 +#define CONFIG_SYS_TEXT_BASE 0x40010000
20901 +#define CONFIG_SYS_NO_FLASH
20902 +#endif
20903 +
20904 +#ifdef CONFIG_NAND_BOOT
20905 +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
20906 +#define CONFIG_SPL_FRAMEWORK
20907 +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
20908 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
20909 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
20910 +#define CONFIG_SPL_ENV_SUPPORT
20911 +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
20912 +#define CONFIG_SPL_I2C_SUPPORT
20913 +#define CONFIG_SPL_WATCHDOG_SUPPORT
20914 +#define CONFIG_SPL_SERIAL_SUPPORT
20915 +#define CONFIG_SPL_NAND_SUPPORT
20916 +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
20917 +
20918 +#define CONFIG_SPL_TEXT_BASE 0x10000000
20919 +#define CONFIG_SPL_MAX_SIZE 0x1a000
20920 +#define CONFIG_SPL_STACK 0x1001d000
20921 +#define CONFIG_SPL_PAD_TO 0x1c000
20922 +#define CONFIG_SYS_TEXT_BASE 0x82000000
20923 +
20924 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
20925 +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
20926 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048
20927 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
20928 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
20929 +
20930 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
20931 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
20932 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000
20933 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
20934 +#define CONFIG_SYS_MONITOR_LEN 0x80000
20935 +#endif
20936
20937 #ifndef CONFIG_SYS_TEXT_BASE
20938 #define CONFIG_SYS_TEXT_BASE 0x67f80000
20939 @@ -71,13 +148,15 @@
20940
20941 #define CONFIG_FSL_CAAM /* Enable CAAM */
20942
20943 -#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
20944 +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
20945 + !defined(CONFIG_QSPI_BOOT)
20946 #define CONFIG_U_QE
20947 #endif
20948
20949 /*
20950 * IFC Definitions
20951 */
20952 +#ifndef CONFIG_QSPI_BOOT
20953 #define CONFIG_FSL_IFC
20954 #define CONFIG_SYS_FLASH_BASE 0x60000000
20955 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
20956 @@ -170,6 +249,7 @@
20957 #define CONFIG_CMD_NAND
20958
20959 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
20960 +#endif
20961
20962 /*
20963 * QIXIS Definitions
20964 @@ -214,6 +294,40 @@
20965 #define CONFIG_SYS_FPGA_FTIM3 0x0
20966 #endif
20967
20968 +#if defined(CONFIG_NAND_BOOT)
20969 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
20970 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
20971 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
20972 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
20973 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
20974 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
20975 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
20976 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
20977 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
20978 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
20979 +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
20980 +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
20981 +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
20982 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
20983 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
20984 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
20985 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
20986 +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
20987 +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
20988 +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
20989 +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
20990 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
20991 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
20992 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
20993 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
20994 +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
20995 +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
20996 +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
20997 +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
20998 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
20999 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
21000 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
21001 +#else
21002 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
21003 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
21004 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
21005 @@ -246,6 +360,7 @@
21006 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
21007 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
21008 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
21009 +#endif
21010
21011 /*
21012 * Serial Port
21013 @@ -279,6 +394,21 @@
21014 #define CONFIG_FSL_ESDHC
21015 #define CONFIG_GENERIC_MMC
21016
21017 +#define CONFIG_CMD_FAT
21018 +#define CONFIG_DOS_PARTITION
21019 +
21020 +/* QSPI */
21021 +#ifdef CONFIG_QSPI_BOOT
21022 +#define CONFIG_FSL_QSPI
21023 +#define QSPI0_AMBA_BASE 0x40000000
21024 +#define FSL_QSPI_FLASH_SIZE (1 << 24)
21025 +#define FSL_QSPI_FLASH_NUM 2
21026 +
21027 +#define CONFIG_CMD_SF
21028 +#define CONFIG_SPI_FLASH
21029 +#define CONFIG_SPI_FLASH_SPANSION
21030 +#endif
21031 +
21032 /*
21033 * USB
21034 */
21035 @@ -341,6 +471,14 @@
21036 #endif
21037
21038 #endif
21039 +
21040 +/* PCIe */
21041 +#define CONFIG_PCI /* Enable PCI/PCIE */
21042 +#define CONFIG_PCIE1 /* PCIE controler 1 */
21043 +#define CONFIG_PCIE2 /* PCIE controler 2 */
21044 +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
21045 +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
21046 +
21047 #define CONFIG_CMD_PING
21048 #define CONFIG_CMD_DHCP
21049 #define CONFIG_CMD_MII
21050 @@ -348,7 +486,20 @@
21051
21052 #define CONFIG_CMDLINE_TAG
21053 #define CONFIG_CMDLINE_EDITING
21054 +
21055 +#ifdef CONFIG_QSPI_BOOT
21056 +#undef CONFIG_CMD_IMLS
21057 +#else
21058 #define CONFIG_CMD_IMLS
21059 +#endif
21060 +
21061 +#define CONFIG_ARMV7_NONSEC
21062 +#define CONFIG_ARMV7_VIRT
21063 +#define CONFIG_PEN_ADDR_BIG_ENDIAN
21064 +#define CONFIG_LS102XA_NS_ACCESS
21065 +#define CONFIG_SMP_PEN_ADDR 0x01ee0200
21066 +#define CONFIG_TIMER_CLK_FREQ 12500000
21067 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
21068
21069 #define CONFIG_HWCONFIG
21070 #define HWCONFIG_BUFFER_SIZE 128
21071 @@ -385,6 +536,8 @@
21072
21073 #define CONFIG_SYS_LOAD_ADDR 0x82000000
21074
21075 +#define CONFIG_LS102XA_STREAM_ID
21076 +
21077 /*
21078 * Stack sizes
21079 * The stack sizes are set up in start.S using the settings below
21080 @@ -396,17 +549,37 @@
21081 #define CONFIG_SYS_INIT_SP_ADDR \
21082 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
21083
21084 +#ifdef CONFIG_SPL_BUILD
21085 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
21086 +#else
21087 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
21088 +#endif
21089
21090 /*
21091 * Environment
21092 */
21093 #define CONFIG_ENV_OVERWRITE
21094
21095 +#if defined(CONFIG_SD_BOOT)
21096 +#define CONFIG_ENV_OFFSET 0x100000
21097 +#define CONFIG_ENV_IS_IN_MMC
21098 +#define CONFIG_SYS_MMC_ENV_DEV 0
21099 +#define CONFIG_ENV_SIZE 0x2000
21100 +#elif defined(CONFIG_QSPI_BOOT)
21101 +#define CONFIG_ENV_IS_IN_SPI_FLASH
21102 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
21103 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
21104 +#define CONFIG_ENV_SECT_SIZE 0x10000
21105 +#elif defined(CONFIG_NAND_BOOT)
21106 +#define CONFIG_ENV_IS_IN_NAND
21107 +#define CONFIG_ENV_SIZE 0x2000
21108 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
21109 +#else
21110 #define CONFIG_ENV_IS_IN_FLASH
21111 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
21112 #define CONFIG_ENV_SIZE 0x2000
21113 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
21114 +#endif
21115
21116 #define CONFIG_OF_LIBFDT
21117 #define CONFIG_OF_BOARD_SETUP
21118 diff -ruN u-boot-2015.01-rc3/include/configs/ls1021atwr.h u-boot/include/configs/ls1021atwr.h
21119 --- u-boot-2015.01-rc3/include/configs/ls1021atwr.h 2014-12-08 22:35:08.000000000 +0100
21120 +++ u-boot/include/configs/ls1021atwr.h 2015-01-01 17:34:32.797494333 +0100
21121 @@ -35,6 +35,43 @@
21122 #define CONFIG_SYS_CLK_FREQ 100000000
21123 #define CONFIG_DDR_CLK_FREQ 100000000
21124
21125 +#ifdef CONFIG_RAMBOOT_PBL
21126 +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
21127 +#endif
21128 +
21129 +#ifdef CONFIG_SD_BOOT
21130 +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
21131 +#define CONFIG_SPL_FRAMEWORK
21132 +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
21133 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
21134 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
21135 +#define CONFIG_SPL_ENV_SUPPORT
21136 +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
21137 +#define CONFIG_SPL_I2C_SUPPORT
21138 +#define CONFIG_SPL_WATCHDOG_SUPPORT
21139 +#define CONFIG_SPL_SERIAL_SUPPORT
21140 +#define CONFIG_SPL_MMC_SUPPORT
21141 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
21142 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
21143 +
21144 +#define CONFIG_SPL_TEXT_BASE 0x10000000
21145 +#define CONFIG_SPL_MAX_SIZE 0x1a000
21146 +#define CONFIG_SPL_STACK 0x1001d000
21147 +#define CONFIG_SPL_PAD_TO 0x1c000
21148 +#define CONFIG_SYS_TEXT_BASE 0x82000000
21149 +
21150 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
21151 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
21152 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000
21153 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
21154 +#define CONFIG_SYS_MONITOR_LEN 0x80000
21155 +#endif
21156 +
21157 +#ifdef CONFIG_QSPI_BOOT
21158 +#define CONFIG_SYS_TEXT_BASE 0x40010000
21159 +#define CONFIG_SYS_NO_FLASH
21160 +#endif
21161 +
21162 #ifndef CONFIG_SYS_TEXT_BASE
21163 #define CONFIG_SYS_TEXT_BASE 0x67f80000
21164 #endif
21165 @@ -50,13 +87,15 @@
21166
21167 #define CONFIG_FSL_CAAM /* Enable CAAM */
21168
21169 -#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
21170 +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
21171 + !defined(CONFIG_QSPI_BOOT)
21172 #define CONFIG_U_QE
21173 #endif
21174
21175 /*
21176 * IFC Definitions
21177 */
21178 +#ifndef CONFIG_QSPI_BOOT
21179 #define CONFIG_FSL_IFC
21180 #define CONFIG_SYS_FLASH_BASE 0x60000000
21181 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
21182 @@ -100,6 +139,7 @@
21183
21184 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
21185 #define CONFIG_SYS_WRITE_SWAPPED_DATA
21186 +#endif
21187
21188 /* CPLD */
21189
21190 @@ -180,6 +220,21 @@
21191 #define CONFIG_FSL_ESDHC
21192 #define CONFIG_GENERIC_MMC
21193
21194 +#define CONFIG_CMD_FAT
21195 +#define CONFIG_DOS_PARTITION
21196 +
21197 +/* QSPI */
21198 +#ifdef CONFIG_QSPI_BOOT
21199 +#define CONFIG_FSL_QSPI
21200 +#define QSPI0_AMBA_BASE 0x40000000
21201 +#define FSL_QSPI_FLASH_SIZE (1 << 24)
21202 +#define FSL_QSPI_FLASH_NUM 2
21203 +
21204 +#define CONFIG_CMD_SF
21205 +#define CONFIG_SPI_FLASH
21206 +#define CONFIG_SPI_FLASH_STMICRO
21207 +#endif
21208 +
21209 /*
21210 * Video
21211 */
21212 @@ -236,6 +291,13 @@
21213 #define CONFIG_HAS_ETH2
21214 #endif
21215
21216 +/* PCIe */
21217 +#define CONFIG_PCI /* Enable PCI/PCIE */
21218 +#define CONFIG_PCIE1 /* PCIE controler 1 */
21219 +#define CONFIG_PCIE2 /* PCIE controler 2 */
21220 +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
21221 +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
21222 +
21223 #define CONFIG_CMD_PING
21224 #define CONFIG_CMD_DHCP
21225 #define CONFIG_CMD_MII
21226 @@ -243,7 +305,20 @@
21227
21228 #define CONFIG_CMDLINE_TAG
21229 #define CONFIG_CMDLINE_EDITING
21230 +
21231 +#ifdef CONFIG_QSPI_BOOT
21232 +#undef CONFIG_CMD_IMLS
21233 +#else
21234 #define CONFIG_CMD_IMLS
21235 +#endif
21236 +
21237 +#define CONFIG_ARMV7_NONSEC
21238 +#define CONFIG_ARMV7_VIRT
21239 +#define CONFIG_PEN_ADDR_BIG_ENDIAN
21240 +#define CONFIG_LS102XA_NS_ACCESS
21241 +#define CONFIG_SMP_PEN_ADDR 0x01ee0200
21242 +#define CONFIG_TIMER_CLK_FREQ 12500000
21243 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
21244
21245 #define CONFIG_HWCONFIG
21246 #define HWCONFIG_BUFFER_SIZE 128
21247 @@ -277,6 +352,8 @@
21248
21249 #define CONFIG_SYS_LOAD_ADDR 0x82000000
21250
21251 +#define CONFIG_LS102XA_STREAM_ID
21252 +
21253 /*
21254 * Stack sizes
21255 * The stack sizes are set up in start.S using the settings below
21256 @@ -288,7 +365,11 @@
21257 #define CONFIG_SYS_INIT_SP_ADDR \
21258 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
21259
21260 +#ifdef CONFIG_SPL_BUILD
21261 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
21262 +#else
21263 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
21264 +#endif
21265
21266 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
21267
21268 @@ -297,10 +378,22 @@
21269 */
21270 #define CONFIG_ENV_OVERWRITE
21271
21272 +#if defined(CONFIG_SD_BOOT)
21273 +#define CONFIG_ENV_OFFSET 0x100000
21274 +#define CONFIG_ENV_IS_IN_MMC
21275 +#define CONFIG_SYS_MMC_ENV_DEV 0
21276 +#define CONFIG_ENV_SIZE 0x20000
21277 +#elif defined(CONFIG_QSPI_BOOT)
21278 +#define CONFIG_ENV_IS_IN_SPI_FLASH
21279 +#define CONFIG_ENV_SIZE 0x2000
21280 +#define CONFIG_ENV_OFFSET 0x100000
21281 +#define CONFIG_ENV_SECT_SIZE 0x10000
21282 +#else
21283 #define CONFIG_ENV_IS_IN_FLASH
21284 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
21285 #define CONFIG_ENV_SIZE 0x20000
21286 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
21287 +#endif
21288
21289 #define CONFIG_OF_LIBFDT
21290 #define CONFIG_OF_BOARD_SETUP
21291 diff -ruN u-boot-2015.01-rc3/include/configs/mx53loco.h u-boot/include/configs/mx53loco.h
21292 --- u-boot-2015.01-rc3/include/configs/mx53loco.h 2014-12-08 22:35:08.000000000 +0100
21293 +++ u-boot/include/configs/mx53loco.h 2015-01-01 17:34:32.801494268 +0100
21294 @@ -94,6 +94,7 @@
21295 /* Command definition */
21296 #include <config_cmd_default.h>
21297 #define CONFIG_CMD_BOOTZ
21298 +#define CONFIG_SUPPORT_RAW_INITRD
21299
21300 #undef CONFIG_CMD_IMLS
21301
21302 diff -ruN u-boot-2015.01-rc3/include/configs/mx6sabre_common.h u-boot/include/configs/mx6sabre_common.h
21303 --- u-boot-2015.01-rc3/include/configs/mx6sabre_common.h 2014-12-08 22:35:08.000000000 +0100
21304 +++ u-boot/include/configs/mx6sabre_common.h 2015-01-01 17:34:32.801494268 +0100
21305 @@ -220,9 +220,6 @@
21306 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
21307 #define CONFIG_AUTO_COMPLETE
21308 #define CONFIG_SYS_CBSIZE 256
21309 -
21310 -/* Print Buffer Size */
21311 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
21312 #define CONFIG_SYS_MAXARGS 16
21313 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
21314
21315 diff -ruN u-boot-2015.01-rc3/include/configs/mx6slevk.h u-boot/include/configs/mx6slevk.h
21316 --- u-boot-2015.01-rc3/include/configs/mx6slevk.h 2014-12-08 22:35:08.000000000 +0100
21317 +++ u-boot/include/configs/mx6slevk.h 2015-01-01 17:34:32.805494202 +0100
21318 @@ -209,6 +209,20 @@
21319 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
21320 #endif
21321
21322 +/* USB Configs */
21323 +#define CONFIG_CMD_USB
21324 +#ifdef CONFIG_CMD_USB
21325 +#define CONFIG_USB_EHCI
21326 +#define CONFIG_USB_EHCI_MX6
21327 +#define CONFIG_USB_STORAGE
21328 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
21329 +#define CONFIG_USB_HOST_ETHER
21330 +#define CONFIG_USB_ETHER_ASIX
21331 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
21332 +#define CONFIG_MXC_USB_FLAGS 0
21333 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
21334 +#endif
21335 +
21336 #define CONFIG_SYS_FSL_USDHC_NUM 3
21337 #if defined(CONFIG_ENV_IS_IN_MMC)
21338 #define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/
21339 diff -ruN u-boot-2015.01-rc3/include/configs/mx6sxsabresd.h u-boot/include/configs/mx6sxsabresd.h
21340 --- u-boot-2015.01-rc3/include/configs/mx6sxsabresd.h 2014-12-08 22:35:08.000000000 +0100
21341 +++ u-boot/include/configs/mx6sxsabresd.h 2015-01-01 17:34:32.805494202 +0100
21342 @@ -198,6 +198,20 @@
21343 #define CONFIG_PHYLIB
21344 #define CONFIG_PHY_ATHEROS
21345
21346 +
21347 +#define CONFIG_CMD_USB
21348 +#ifdef CONFIG_CMD_USB
21349 +#define CONFIG_USB_EHCI
21350 +#define CONFIG_USB_EHCI_MX6
21351 +#define CONFIG_USB_STORAGE
21352 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
21353 +#define CONFIG_USB_HOST_ETHER
21354 +#define CONFIG_USB_ETHER_ASIX
21355 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
21356 +#define CONFIG_MXC_USB_FLAGS 0
21357 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
21358 +#endif
21359 +
21360 #define CONFIG_CMD_PCI
21361 #ifdef CONFIG_CMD_PCI
21362 #define CONFIG_PCI
21363 @@ -208,6 +222,16 @@
21364 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
21365 #endif
21366
21367 +#define CONFIG_DM
21368 +#define CONFIG_DM_THERMAL
21369 +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
21370 +#define CONFIG_IMX6_THERMAL
21371 +
21372 +#define CONFIG_CMD_FUSE
21373 +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
21374 +#define CONFIG_MXC_OCOTP
21375 +#endif
21376 +
21377 /* FLASH and environment organization */
21378 #define CONFIG_SYS_NO_FLASH
21379
21380 diff -ruN u-boot-2015.01-rc3/include/configs/nyan-big.h u-boot/include/configs/nyan-big.h
21381 --- u-boot-2015.01-rc3/include/configs/nyan-big.h 1970-01-01 01:00:00.000000000 +0100
21382 +++ u-boot/include/configs/nyan-big.h 2015-01-01 17:34:32.805494202 +0100
21383 @@ -0,0 +1,74 @@
21384 +/*
21385 + * (C) Copyright 2014
21386 + * NVIDIA Corporation <www.nvidia.com>
21387 + *
21388 + * SPDX-License-Identifier: GPL-2.0+
21389 + */
21390 +
21391 +#ifndef __CONFIG_H
21392 +#define __CONFIG_H
21393 +
21394 +#include <linux/sizes.h>
21395 +
21396 +#include "tegra124-common.h"
21397 +
21398 +/* High-level configuration options */
21399 +#define V_PROMPT "Tegra124 (Nyan-big) # "
21400 +#define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big"
21401 +
21402 +/* Board-specific serial config */
21403 +#define CONFIG_SERIAL_MULTI
21404 +#define CONFIG_TEGRA_ENABLE_UARTA
21405 +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
21406 +
21407 +#define CONFIG_BOARD_EARLY_INIT_F
21408 +
21409 +/* I2C */
21410 +#define CONFIG_SYS_I2C_TEGRA
21411 +#define CONFIG_CMD_I2C
21412 +
21413 +/* SD/MMC */
21414 +#define CONFIG_MMC
21415 +#define CONFIG_GENERIC_MMC
21416 +#define CONFIG_TEGRA_MMC
21417 +#define CONFIG_CMD_MMC
21418 +
21419 +/* Environment in eMMC, at the end of 2nd "boot sector" */
21420 +#define CONFIG_ENV_IS_IN_MMC
21421 +#define CONFIG_SYS_MMC_ENV_DEV 0
21422 +#define CONFIG_SYS_MMC_ENV_PART 2
21423 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
21424 +
21425 +/* SPI */
21426 +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
21427 +#define CONFIG_TEGRA114_SPI_CTRLS 6
21428 +#define CONFIG_SPI_FLASH
21429 +#define CONFIG_SPI_FLASH_WINBOND
21430 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
21431 +#define CONFIG_SF_DEFAULT_SPEED 24000000
21432 +#define CONFIG_CMD_SPI
21433 +#define CONFIG_CMD_SF
21434 +#define CONFIG_SPI_FLASH_SIZE (4 << 20)
21435 +
21436 +/* USB Host support */
21437 +#define CONFIG_USB_EHCI
21438 +#define CONFIG_USB_EHCI_TEGRA
21439 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
21440 +#define CONFIG_USB_STORAGE
21441 +#define CONFIG_CMD_USB
21442 +
21443 +/* USB networking support */
21444 +#define CONFIG_USB_HOST_ETHER
21445 +#define CONFIG_USB_ETHER_ASIX
21446 +
21447 +/* General networking support */
21448 +#define CONFIG_CMD_NET
21449 +#define CONFIG_CMD_DHCP
21450 +
21451 +#define CONFIG_FIT
21452 +#define CONFIG_OF_LIBFDT
21453 +
21454 +#include "tegra-common-usb-gadget.h"
21455 +#include "tegra-common-post.h"
21456 +
21457 +#endif /* __CONFIG_H */
21458 diff -ruN u-boot-2015.01-rc3/include/configs/P1023RDB.h u-boot/include/configs/P1023RDB.h
21459 --- u-boot-2015.01-rc3/include/configs/P1023RDB.h 2014-12-08 22:35:08.000000000 +0100
21460 +++ u-boot/include/configs/P1023RDB.h 2015-01-01 17:34:32.769494793 +0100
21461 @@ -347,9 +347,25 @@
21462 #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000
21463 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
21464 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
21465 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
21466 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
21467 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
21468 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21469 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
21470 + CONFIG_SYS_QMAN_CENA_SIZE)
21471 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21472 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
21473 #define CONFIG_SYS_BMAN_MEM_BASE 0xff200000
21474 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
21475 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
21476 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
21477 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
21478 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
21479 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21480 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
21481 + CONFIG_SYS_BMAN_CENA_SIZE)
21482 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21483 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
21484
21485 /* For FM */
21486 #define CONFIG_SYS_DPAA_FMAN
21487 diff -ruN u-boot-2015.01-rc3/include/configs/P2041RDB.h u-boot/include/configs/P2041RDB.h
21488 --- u-boot-2015.01-rc3/include/configs/P2041RDB.h 2014-12-08 22:35:08.000000000 +0100
21489 +++ u-boot/include/configs/P2041RDB.h 2015-01-01 17:34:32.769494793 +0100
21490 @@ -13,6 +13,8 @@
21491
21492 #define CONFIG_P2041RDB
21493 #define CONFIG_PHYS_64BIT
21494 +#define CONFIG_SYS_GENERIC_BOARD
21495 +#define CONFIG_DISPLAY_BOARDINFO
21496 #define CONFIG_PPC_P2041
21497
21498 #ifdef CONFIG_RAMBOOT_PBL
21499 @@ -489,6 +491,14 @@
21500 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
21501 #endif
21502 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
21503 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
21504 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
21505 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
21506 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21507 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
21508 + CONFIG_SYS_BMAN_CENA_SIZE)
21509 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21510 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
21511 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
21512 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
21513 #ifdef CONFIG_PHYS_64BIT
21514 @@ -497,6 +507,14 @@
21515 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
21516 #endif
21517 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
21518 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
21519 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
21520 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
21521 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21522 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
21523 + CONFIG_SYS_QMAN_CENA_SIZE)
21524 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21525 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
21526
21527 #define CONFIG_SYS_DPAA_FMAN
21528 #define CONFIG_SYS_DPAA_PME
21529 diff -ruN u-boot-2015.01-rc3/include/configs/rcar-gen2-common.h u-boot/include/configs/rcar-gen2-common.h
21530 --- u-boot-2015.01-rc3/include/configs/rcar-gen2-common.h 2014-12-08 22:35:08.000000000 +0100
21531 +++ u-boot/include/configs/rcar-gen2-common.h 2015-01-01 17:34:32.809494137 +0100
21532 @@ -28,6 +28,9 @@
21533 #define CONFIG_CMD_FAT
21534 #define CONFIG_CMD_SF
21535 #define CONFIG_CMD_SPI
21536 +#define CONFIG_CMD_EXT2
21537 +#define CONFIG_CMD_EXT4
21538 +#define CONFIG_CMD_EXT4_WRITE
21539
21540 #define CONFIG_SYS_THUMB_BUILD
21541 #define CONFIG_SYS_GENERIC_BOARD
21542 @@ -36,6 +39,7 @@
21543 #define CONFIG_FAT_WRITE
21544 #define CONFIG_DOS_PARTITION
21545 #define CONFIG_SUPPORT_VFAT
21546 +#define CONFIG_FS_EXT4
21547 #define CONFIG_EXT4_WRITE
21548
21549 #define CONFIG_CMDLINE_TAG
21550 diff -ruN u-boot-2015.01-rc3/include/configs/rpi.h u-boot/include/configs/rpi.h
21551 --- u-boot-2015.01-rc3/include/configs/rpi.h 2014-12-08 22:35:08.000000000 +0100
21552 +++ u-boot/include/configs/rpi.h 2015-01-01 17:34:32.809494137 +0100
21553 @@ -34,6 +34,7 @@
21554 #define CONFIG_DM
21555 #define CONFIG_CMD_DM
21556 #define CONFIG_DM_GPIO
21557 +#define CONFIG_DM_SERIAL
21558
21559 /* Memory layout */
21560 #define CONFIG_NR_DRAM_BANKS 1
21561 @@ -51,6 +52,7 @@
21562 CONFIG_SYS_SDRAM_SIZE - \
21563 GENERATED_GBL_DATA_SIZE)
21564 #define CONFIG_SYS_MALLOC_LEN SZ_4M
21565 +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
21566 #define CONFIG_SYS_MEMTEST_START 0x00100000
21567 #define CONFIG_SYS_MEMTEST_END 0x00200000
21568 #define CONFIG_LOADADDR 0x00200000
21569 @@ -92,9 +94,7 @@
21570 #endif
21571
21572 /* Console UART */
21573 -#define CONFIG_PL011_SERIAL
21574 -#define CONFIG_PL011_CLOCK 3000000
21575 -#define CONFIG_PL01x_PORTS { (void *)0x20201000 }
21576 +#define CONFIG_PL01X_SERIAL
21577 #define CONFIG_CONS_INDEX 0
21578 #define CONFIG_BAUDRATE 115200
21579
21580 diff -ruN u-boot-2015.01-rc3/include/configs/sandbox.h u-boot/include/configs/sandbox.h
21581 --- u-boot-2015.01-rc3/include/configs/sandbox.h 2014-12-08 22:35:08.000000000 +0100
21582 +++ u-boot/include/configs/sandbox.h 2015-01-01 17:34:32.809494137 +0100
21583 @@ -112,6 +112,12 @@
21584 #define CONFIG_SPI_FLASH_STMICRO
21585 #define CONFIG_SPI_FLASH_WINBOND
21586
21587 +#define CONFIG_DM_I2C
21588 +#define CONFIG_CMD_I2C
21589 +#define CONFIG_SYS_I2C_SANDBOX
21590 +#define CONFIG_I2C_EDID
21591 +#define CONFIG_I2C_EEPROM
21592 +
21593 /* Memory things - we don't really want a memory test */
21594 #define CONFIG_SYS_LOAD_ADDR 0x00000000
21595 #define CONFIG_SYS_MEMTEST_START 0x00100000
21596 diff -ruN u-boot-2015.01-rc3/include/configs/seaboard.h u-boot/include/configs/seaboard.h
21597 --- u-boot-2015.01-rc3/include/configs/seaboard.h 2014-12-08 22:35:08.000000000 +0100
21598 +++ u-boot/include/configs/seaboard.h 2015-01-01 17:34:32.813494071 +0100
21599 @@ -37,10 +37,7 @@
21600
21601 /* I2C */
21602 #define CONFIG_SYS_I2C_TEGRA
21603 -#define CONFIG_SYS_I2C_INIT_BOARD
21604 -#define CONFIG_SYS_I2C_SPEED 100000
21605 #define CONFIG_CMD_I2C
21606 -#define CONFIG_SYS_I2C
21607
21608 /* SD/MMC */
21609 #define CONFIG_MMC
21610 diff -ruN u-boot-2015.01-rc3/include/configs/socfpga_common.h u-boot/include/configs/socfpga_common.h
21611 --- u-boot-2015.01-rc3/include/configs/socfpga_common.h 2014-12-08 22:35:08.000000000 +0100
21612 +++ u-boot/include/configs/socfpga_common.h 2015-01-01 17:34:32.813494071 +0100
21613 @@ -159,7 +159,7 @@
21614 #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
21615 #endif
21616
21617 - /*
21618 +/*
21619 * I2C support
21620 */
21621 #define CONFIG_SYS_I2C
21622 @@ -187,6 +187,37 @@
21623 #define CONFIG_CMD_I2C
21624
21625 /*
21626 + * QSPI support
21627 + */
21628 +#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */
21629 +#define CONFIG_CMD_DM
21630 +#define CONFIG_DM
21631 +#define CONFIG_DM_SPI
21632 +#define CONFIG_DM_SPI_FLASH
21633 +#define CONFIG_CADENCE_QSPI
21634 +/* Enable multiple SPI NOR flash manufacturers */
21635 +#define CONFIG_SPI_FLASH /* SPI flash subsystem */
21636 +#define CONFIG_SPI_FLASH_STMICRO /* Micron/Numonyx flash */
21637 +#define CONFIG_SPI_FLASH_SPANSION /* Spansion flash */
21638 +#define CONFIG_SPI_FLASH_MTD
21639 +/* QSPI reference clock */
21640 +#ifndef __ASSEMBLY__
21641 +unsigned int cm_get_qspi_controller_clk_hz(void);
21642 +#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
21643 +#endif
21644 +#define CONFIG_CQSPI_DECODER 0
21645 +#define CONFIG_CMD_SF
21646 +#endif
21647 +
21648 +#ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */
21649 +#define CONFIG_CMD_DM
21650 +#define CONFIG_DM
21651 +#define CONFIG_DM_SPI
21652 +#define CONFIG_DESIGNWARE_SPI
21653 +#define CONFIG_CMD_SPI
21654 +#endif
21655 +
21656 +/*
21657 * Serial Driver
21658 */
21659 #define CONFIG_SYS_NS16550
21660 diff -ruN u-boot-2015.01-rc3/include/configs/stv0991.h u-boot/include/configs/stv0991.h
21661 --- u-boot-2015.01-rc3/include/configs/stv0991.h 1970-01-01 01:00:00.000000000 +0100
21662 +++ u-boot/include/configs/stv0991.h 2015-01-01 17:34:32.813494071 +0100
21663 @@ -0,0 +1,95 @@
21664 +/*
21665 + * (C) Copyright 2014
21666 + * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
21667 + *
21668 + * SPDX-License-Identifier: GPL-2.0+
21669 + */
21670 +
21671 +#ifndef __CONFIG_STV0991_H
21672 +#define __CONFIG_STV0991_H
21673 +#define CONFIG_SYS_DCACHE_OFF
21674 +#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
21675 +#define CONFIG_BOARD_EARLY_INIT_F
21676 +
21677 +#define CONFIG_SYS_CORTEX_R4
21678 +
21679 +#define CONFIG_SYS_GENERIC_BOARD
21680 +#define CONFIG_SYS_NO_FLASH
21681 +
21682 +/* ram memory-related information */
21683 +#define CONFIG_NR_DRAM_BANKS 1
21684 +#define PHYS_SDRAM_1 0x00000000
21685 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
21686 +#define PHYS_SDRAM_1_SIZE 0x00198000
21687 +
21688 +#define CONFIG_ENV_SIZE 0x10000
21689 +#define CONFIG_ENV_IS_IN_FLASH
21690 +#define CONFIG_ENV_ADDR \
21691 + (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE)
21692 +#define CONFIG_SYS_MAXARGS 16
21693 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024)
21694 +#define CONFIG_SYS_MALLOC_F_LEN 0x2000
21695 +
21696 +#define CONFIG_DM
21697 +/* serial port (PL011) configuration */
21698 +#define CONFIG_BAUDRATE 115200
21699 +#ifdef CONFIG_DM
21700 +#define CONFIG_DM_SERIAL
21701 +#define CONFIG_PL01X_SERIAL
21702 +#else
21703 +#define CONFIG_SYS_SERIAL0 0x80406000
21704 +#define CONFIG_CONS_INDEX 0
21705 +#define CONFIG_PL011_SERIAL
21706 +#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0}
21707 +#define CONFIG_PL011_CLOCK (2700 * 1000)
21708 +#endif
21709 +
21710 +/* user interface */
21711 +#define CONFIG_SYS_PROMPT "STV0991> "
21712 +#define CONFIG_SYS_CBSIZE 1024
21713 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
21714 + +sizeof(CONFIG_SYS_PROMPT) + 16)
21715 +
21716 +/* MISC */
21717 +#define CONFIG_SYS_LOAD_ADDR 0x00000000
21718 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000
21719 +#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000
21720 +#define CONFIG_SYS_INIT_SP_OFFSET \
21721 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
21722 +/* U-boot Load Address */
21723 +#define CONFIG_SYS_TEXT_BASE 0x00010000
21724 +#define CONFIG_SYS_INIT_SP_ADDR \
21725 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
21726 +
21727 +/* GMAC related configs */
21728 +
21729 +#define CONFIG_MII
21730 +#define CONFIG_PHYLIB
21731 +#define CONFIG_CMD_NET
21732 +#define CONFIG_DESIGNWARE_ETH
21733 +#define CONFIG_DW_ALTDESCRIPTOR
21734 +#define CONFIG_PHY_MICREL
21735 +
21736 +/* Command support defines */
21737 +#define CONFIG_CMD_PING
21738 +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
21739 +
21740 +#include "config_cmd_default.h"
21741 +#undef CONFIG_CMD_SAVEENV
21742 +
21743 +#define CONFIG_SYS_MEMTEST_START 0x0000
21744 +#define CONFIG_SYS_MEMTEST_END 1024*1024
21745 +#define CONFIG_CMD_MEMTEST
21746 +
21747 +/* Misc configuration */
21748 +#define CONFIG_SYS_LONGHELP
21749 +#define CONFIG_CMDLINE_EDITING
21750 +
21751 +#define CONFIG_BOOTDELAY 3
21752 +#define CONFIG_BOOTCOMMAND "go 0x40040000"
21753 +#define CONFIG_AUTOBOOT_KEYED
21754 +#define CONFIG_AUTOBOOT_STOP_STR " "
21755 +#define CONFIG_AUTOBOOT_PROMPT \
21756 + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay
21757 +
21758 +#endif /* __CONFIG_H */
21759 diff -ruN u-boot-2015.01-rc3/include/configs/sun7i.h u-boot/include/configs/sun7i.h
21760 --- u-boot-2015.01-rc3/include/configs/sun7i.h 2014-12-08 22:35:08.000000000 +0100
21761 +++ u-boot/include/configs/sun7i.h 2015-01-01 17:34:32.813494071 +0100
21762 @@ -25,6 +25,7 @@
21763 #define CONFIG_ARMV7_PSCI 1
21764 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
21765 #define CONFIG_SYS_CLK_FREQ 24000000
21766 +#define CONFIG_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ
21767
21768 /*
21769 * Include common sunxi configuration where most the settings are
21770 diff -ruN u-boot-2015.01-rc3/include/configs/T102xQDS.h u-boot/include/configs/T102xQDS.h
21771 --- u-boot-2015.01-rc3/include/configs/T102xQDS.h 2014-12-08 22:35:08.000000000 +0100
21772 +++ u-boot/include/configs/T102xQDS.h 2015-01-01 17:34:32.773494727 +0100
21773 @@ -720,7 +720,7 @@
21774 /* Qman/Bman */
21775 #ifndef CONFIG_NOBQFMAN
21776 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
21777 -#define CONFIG_SYS_BMAN_NUM_PORTALS 25
21778 +#define CONFIG_SYS_BMAN_NUM_PORTALS 10
21779 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
21780 #ifdef CONFIG_PHYS_64BIT
21781 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
21782 @@ -728,7 +728,15 @@
21783 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
21784 #endif
21785 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
21786 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25
21787 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
21788 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
21789 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
21790 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21791 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
21792 + CONFIG_SYS_BMAN_CENA_SIZE)
21793 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21794 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
21795 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10
21796 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
21797 #ifdef CONFIG_PHYS_64BIT
21798 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
21799 @@ -736,6 +744,14 @@
21800 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
21801 #endif
21802 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
21803 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
21804 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
21805 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
21806 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21807 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
21808 + CONFIG_SYS_QMAN_CENA_SIZE)
21809 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21810 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
21811
21812 #define CONFIG_SYS_DPAA_FMAN
21813
21814 diff -ruN u-boot-2015.01-rc3/include/configs/T102xRDB.h u-boot/include/configs/T102xRDB.h
21815 --- u-boot-2015.01-rc3/include/configs/T102xRDB.h 2014-12-08 22:35:08.000000000 +0100
21816 +++ u-boot/include/configs/T102xRDB.h 2015-01-01 17:34:32.773494727 +0100
21817 @@ -677,7 +677,7 @@
21818 /* Qman/Bman */
21819 #ifndef CONFIG_NOBQFMAN
21820 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
21821 -#define CONFIG_SYS_BMAN_NUM_PORTALS 25
21822 +#define CONFIG_SYS_BMAN_NUM_PORTALS 10
21823 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
21824 #ifdef CONFIG_PHYS_64BIT
21825 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
21826 @@ -685,7 +685,15 @@
21827 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
21828 #endif
21829 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
21830 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25
21831 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
21832 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
21833 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
21834 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21835 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
21836 + CONFIG_SYS_BMAN_CENA_SIZE)
21837 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21838 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
21839 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10
21840 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
21841 #ifdef CONFIG_PHYS_64BIT
21842 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
21843 @@ -693,6 +701,14 @@
21844 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
21845 #endif
21846 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
21847 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
21848 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
21849 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
21850 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21851 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
21852 + CONFIG_SYS_QMAN_CENA_SIZE)
21853 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21854 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
21855
21856 #define CONFIG_SYS_DPAA_FMAN
21857
21858 diff -ruN u-boot-2015.01-rc3/include/configs/T1040QDS.h u-boot/include/configs/T1040QDS.h
21859 --- u-boot-2015.01-rc3/include/configs/T1040QDS.h 2014-12-08 22:35:08.000000000 +0100
21860 +++ u-boot/include/configs/T1040QDS.h 2015-01-01 17:34:32.773494727 +0100
21861 @@ -605,14 +605,30 @@
21862 /* Qman/Bman */
21863 #ifndef CONFIG_NOBQFMAN
21864 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
21865 -#define CONFIG_SYS_BMAN_NUM_PORTALS 25
21866 +#define CONFIG_SYS_BMAN_NUM_PORTALS 10
21867 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
21868 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
21869 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
21870 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25
21871 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
21872 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
21873 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
21874 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21875 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
21876 + CONFIG_SYS_BMAN_CENA_SIZE)
21877 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21878 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
21879 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10
21880 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
21881 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
21882 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
21883 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
21884 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
21885 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
21886 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21887 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
21888 + CONFIG_SYS_QMAN_CENA_SIZE)
21889 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21890 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
21891
21892 #define CONFIG_SYS_DPAA_FMAN
21893 #define CONFIG_SYS_DPAA_PME
21894 diff -ruN u-boot-2015.01-rc3/include/configs/T104xRDB.h u-boot/include/configs/T104xRDB.h
21895 --- u-boot-2015.01-rc3/include/configs/T104xRDB.h 2014-12-08 22:35:08.000000000 +0100
21896 +++ u-boot/include/configs/T104xRDB.h 2015-01-01 17:34:32.773494727 +0100
21897 @@ -104,7 +104,10 @@
21898
21899 /* support deep sleep */
21900 #define CONFIG_DEEP_SLEEP
21901 +#if defined(CONFIG_DEEP_SLEEP)
21902 +#define CONFIG_BOARD_EARLY_INIT_F
21903 #define CONFIG_SILENT_CONSOLE
21904 +#endif
21905
21906 #ifndef CONFIG_SYS_TEXT_BASE
21907 #define CONFIG_SYS_TEXT_BASE 0xeff40000
21908 @@ -636,14 +639,30 @@
21909 /* Qman/Bman */
21910 #ifndef CONFIG_NOBQFMAN
21911 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
21912 -#define CONFIG_SYS_BMAN_NUM_PORTALS 25
21913 +#define CONFIG_SYS_BMAN_NUM_PORTALS 10
21914 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
21915 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
21916 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
21917 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25
21918 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
21919 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
21920 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
21921 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21922 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
21923 + CONFIG_SYS_BMAN_CENA_SIZE)
21924 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21925 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
21926 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10
21927 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
21928 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
21929 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
21930 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
21931 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
21932 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
21933 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21934 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
21935 + CONFIG_SYS_QMAN_CENA_SIZE)
21936 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21937 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
21938
21939 #define CONFIG_SYS_DPAA_FMAN
21940 #define CONFIG_SYS_DPAA_PME
21941 diff -ruN u-boot-2015.01-rc3/include/configs/T208xQDS.h u-boot/include/configs/T208xQDS.h
21942 --- u-boot-2015.01-rc3/include/configs/T208xQDS.h 2014-12-08 22:35:08.000000000 +0100
21943 +++ u-boot/include/configs/T208xQDS.h 2015-01-01 17:34:32.773494727 +0100
21944 @@ -634,10 +634,26 @@
21945 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
21946 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
21947 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
21948 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
21949 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
21950 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
21951 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21952 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
21953 + CONFIG_SYS_BMAN_CENA_SIZE)
21954 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21955 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
21956 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
21957 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
21958 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
21959 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
21960 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
21961 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
21962 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
21963 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21964 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
21965 + CONFIG_SYS_QMAN_CENA_SIZE)
21966 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21967 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
21968
21969 #define CONFIG_SYS_DPAA_FMAN
21970 #define CONFIG_SYS_DPAA_PME
21971 diff -ruN u-boot-2015.01-rc3/include/configs/T208xRDB.h u-boot/include/configs/T208xRDB.h
21972 --- u-boot-2015.01-rc3/include/configs/T208xRDB.h 2014-12-08 22:35:08.000000000 +0100
21973 +++ u-boot/include/configs/T208xRDB.h 2015-01-01 17:34:32.773494727 +0100
21974 @@ -567,10 +567,26 @@
21975 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
21976 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
21977 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
21978 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
21979 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
21980 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
21981 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21982 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
21983 + CONFIG_SYS_BMAN_CENA_SIZE)
21984 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
21985 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
21986 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
21987 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
21988 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
21989 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
21990 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
21991 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
21992 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
21993 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21994 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
21995 + CONFIG_SYS_QMAN_CENA_SIZE)
21996 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
21997 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
21998
21999 #define CONFIG_SYS_DPAA_FMAN
22000 #define CONFIG_SYS_DPAA_PME
22001 diff -ruN u-boot-2015.01-rc3/include/configs/T4240EMU.h u-boot/include/configs/T4240EMU.h
22002 --- u-boot-2015.01-rc3/include/configs/T4240EMU.h 2014-12-08 22:35:08.000000000 +0100
22003 +++ u-boot/include/configs/T4240EMU.h 2015-01-01 17:34:32.773494727 +0100
22004 @@ -85,10 +85,26 @@
22005 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
22006 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
22007 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
22008 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
22009 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
22010 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
22011 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
22012 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
22013 + CONFIG_SYS_BMAN_CENA_SIZE)
22014 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
22015 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
22016 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
22017 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
22018 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
22019 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
22020 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
22021 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
22022 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
22023 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
22024 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
22025 + CONFIG_SYS_QMAN_CENA_SIZE)
22026 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
22027 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
22028
22029 #define CONFIG_SYS_DPAA_FMAN
22030 #define CONFIG_SYS_DPAA_PME
22031 diff -ruN u-boot-2015.01-rc3/include/configs/T4240QDS.h u-boot/include/configs/T4240QDS.h
22032 --- u-boot-2015.01-rc3/include/configs/T4240QDS.h 2014-12-08 22:35:08.000000000 +0100
22033 +++ u-boot/include/configs/T4240QDS.h 2015-01-01 17:34:32.773494727 +0100
22034 @@ -417,10 +417,26 @@
22035 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
22036 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
22037 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
22038 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
22039 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
22040 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
22041 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
22042 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
22043 + CONFIG_SYS_BMAN_CENA_SIZE)
22044 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
22045 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
22046 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
22047 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
22048 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
22049 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
22050 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
22051 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
22052 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
22053 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
22054 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
22055 + CONFIG_SYS_QMAN_CENA_SIZE)
22056 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
22057 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
22058
22059 #define CONFIG_SYS_DPAA_FMAN
22060 #define CONFIG_SYS_DPAA_PME
22061 diff -ruN u-boot-2015.01-rc3/include/configs/T4240RDB.h u-boot/include/configs/T4240RDB.h
22062 --- u-boot-2015.01-rc3/include/configs/T4240RDB.h 2014-12-08 22:35:08.000000000 +0100
22063 +++ u-boot/include/configs/T4240RDB.h 2015-01-01 17:34:32.773494727 +0100
22064 @@ -12,6 +12,8 @@
22065
22066 #define CONFIG_T4240RDB
22067 #define CONFIG_PHYS_64BIT
22068 +#define CONFIG_SYS_GENERIC_BOARD
22069 +#define CONFIG_DISPLAY_BOARDINFO
22070
22071 #define CONFIG_FSL_SATA_V2
22072 #define CONFIG_PCIE4
22073 @@ -577,10 +579,26 @@
22074 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
22075 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
22076 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
22077 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
22078 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
22079 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
22080 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
22081 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
22082 + CONFIG_SYS_BMAN_CENA_SIZE)
22083 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
22084 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
22085 #define CONFIG_SYS_QMAN_NUM_PORTALS 50
22086 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
22087 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
22088 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
22089 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
22090 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
22091 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
22092 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
22093 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
22094 + CONFIG_SYS_QMAN_CENA_SIZE)
22095 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
22096 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
22097
22098 #define CONFIG_SYS_DPAA_FMAN
22099 #define CONFIG_SYS_DPAA_PME
22100 diff -ruN u-boot-2015.01-rc3/include/configs/tbs2910.h u-boot/include/configs/tbs2910.h
22101 --- u-boot-2015.01-rc3/include/configs/tbs2910.h 2014-12-08 22:35:08.000000000 +0100
22102 +++ u-boot/include/configs/tbs2910.h 2015-01-01 17:34:32.817494006 +0100
22103 @@ -167,7 +167,7 @@
22104 #define CONFIG_USB_STORAGE
22105 #define CONFIG_USB_KEYBOARD
22106 #ifdef CONFIG_USB_KEYBOARD
22107 -#define CONFIG_SYS_USB_EVENT_POLL
22108 +#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
22109 #define CONFIG_SYS_STDIO_DEREGISTER
22110 #define CONFIG_PREBOOT "if hdmidet; then usb start; fi"
22111 #endif /* CONFIG_USB_KEYBOARD */
22112 diff -ruN u-boot-2015.01-rc3/include/configs/tec-ng.h u-boot/include/configs/tec-ng.h
22113 --- u-boot-2015.01-rc3/include/configs/tec-ng.h 2014-12-08 22:35:08.000000000 +0100
22114 +++ u-boot/include/configs/tec-ng.h 2015-01-01 17:34:32.817494006 +0100
22115 @@ -23,12 +23,7 @@
22116
22117 /* I2C */
22118 #define CONFIG_SYS_I2C_TEGRA
22119 -#define CONFIG_SYS_I2C_INIT_BOARD
22120 -#define CONFIG_I2C_MULTI_BUS
22121 -#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
22122 -#define CONFIG_SYS_I2C_SPEED 100000
22123 #define CONFIG_CMD_I2C
22124 -#define CONFIG_SYS_I2C
22125
22126 /* SD/MMC */
22127 #define CONFIG_MMC
22128 diff -ruN u-boot-2015.01-rc3/include/configs/tegra114-common.h u-boot/include/configs/tegra114-common.h
22129 --- u-boot-2015.01-rc3/include/configs/tegra114-common.h 2014-12-08 22:35:08.000000000 +0100
22130 +++ u-boot/include/configs/tegra114-common.h 2015-01-01 17:34:32.817494006 +0100
22131 @@ -76,9 +76,6 @@
22132 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000
22133 #define CONFIG_SPL_STACK 0x800ffffc
22134
22135 -/* Total I2C ports on Tegra114 */
22136 -#define TEGRA_I2C_NUM_CONTROLLERS 5
22137 -
22138 /* For USB EHCI controller */
22139 #define CONFIG_EHCI_IS_TDI
22140 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
22141 diff -ruN u-boot-2015.01-rc3/include/configs/tegra124-common.h u-boot/include/configs/tegra124-common.h
22142 --- u-boot-2015.01-rc3/include/configs/tegra124-common.h 2014-12-08 22:35:08.000000000 +0100
22143 +++ u-boot/include/configs/tegra124-common.h 2015-01-01 17:34:32.817494006 +0100
22144 @@ -68,9 +68,6 @@
22145 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000
22146 #define CONFIG_SPL_STACK 0x800ffffc
22147
22148 -/* Total I2C ports on Tegra124 */
22149 -#define TEGRA_I2C_NUM_CONTROLLERS 5
22150 -
22151 /* For USB EHCI controller */
22152 #define CONFIG_EHCI_IS_TDI
22153 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
22154 diff -ruN u-boot-2015.01-rc3/include/configs/tegra20-common.h u-boot/include/configs/tegra20-common.h
22155 --- u-boot-2015.01-rc3/include/configs/tegra20-common.h 2014-12-08 22:35:08.000000000 +0100
22156 +++ u-boot/include/configs/tegra20-common.h 2015-01-01 17:34:32.817494006 +0100
22157 @@ -97,9 +97,6 @@
22158 #define CONFIG_EHCI_IS_TDI
22159 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
22160
22161 -/* Total I2C ports on Tegra20 */
22162 -#define TEGRA_I2C_NUM_CONTROLLERS 4
22163 -
22164 #define CONFIG_SYS_NAND_SELF_INIT
22165 #define CONFIG_SYS_NAND_ONFI_DETECTION
22166
22167 diff -ruN u-boot-2015.01-rc3/include/configs/tegra30-common.h u-boot/include/configs/tegra30-common.h
22168 --- u-boot-2015.01-rc3/include/configs/tegra30-common.h 2014-12-08 22:35:08.000000000 +0100
22169 +++ u-boot/include/configs/tegra30-common.h 2015-01-01 17:34:32.817494006 +0100
22170 @@ -73,9 +73,6 @@
22171 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000
22172 #define CONFIG_SPL_STACK 0x800ffffc
22173
22174 -/* Total I2C ports on Tegra30 */
22175 -#define TEGRA_I2C_NUM_CONTROLLERS 5
22176 -
22177 /* For USB EHCI controller */
22178 #define CONFIG_EHCI_IS_TDI
22179 #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
22180 diff -ruN u-boot-2015.01-rc3/include/configs/tegra-common.h u-boot/include/configs/tegra-common.h
22181 --- u-boot-2015.01-rc3/include/configs/tegra-common.h 2014-12-08 22:35:08.000000000 +0100
22182 +++ u-boot/include/configs/tegra-common.h 2015-01-01 17:34:32.817494006 +0100
22183 @@ -26,6 +26,7 @@
22184 #endif
22185 #define CONFIG_DM_SPI
22186 #define CONFIG_DM_SPI_FLASH
22187 +#define CONFIG_DM_I2C
22188
22189 #define CONFIG_SYS_TIMER_RATE 1000000
22190 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
22191 diff -ruN u-boot-2015.01-rc3/include/configs/trimslice.h u-boot/include/configs/trimslice.h
22192 --- u-boot-2015.01-rc3/include/configs/trimslice.h 2014-12-08 22:35:08.000000000 +0100
22193 +++ u-boot/include/configs/trimslice.h 2015-01-01 17:34:32.817494006 +0100
22194 @@ -34,10 +34,7 @@
22195
22196 /* I2C */
22197 #define CONFIG_SYS_I2C_TEGRA
22198 -#define CONFIG_SYS_I2C_INIT_BOARD
22199 -#define CONFIG_SYS_I2C_SPEED 100000
22200 #define CONFIG_CMD_I2C
22201 -#define CONFIG_SYS_I2C
22202
22203 /* SD/MMC */
22204 #define CONFIG_MMC
22205 diff -ruN u-boot-2015.01-rc3/include/configs/uniphier.h u-boot/include/configs/uniphier.h
22206 --- u-boot-2015.01-rc3/include/configs/uniphier.h 2014-12-08 22:35:08.000000000 +0100
22207 +++ u-boot/include/configs/uniphier.h 2015-01-01 17:34:32.817494006 +0100
22208 @@ -187,6 +187,8 @@
22209 #define CONFIG_FAT_WRITE
22210 #define CONFIG_DOS_PARTITION
22211
22212 +#define CONFIG_CMD_DM
22213 +
22214 /* memtest works on */
22215 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
22216 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000)
22217 @@ -273,7 +275,11 @@
22218 #define CONFIG_SYS_SPL_MALLOC_START (0x0ff00000)
22219 #define CONFIG_SYS_SPL_MALLOC_SIZE (0x00004000)
22220
22221 +#ifdef CONFIG_SPL_BUILD
22222 #define CONFIG_SYS_INIT_SP_ADDR (0x0ff08000)
22223 +#else
22224 +#define CONFIG_SYS_INIT_SP_ADDR ((CONFIG_SYS_TEXT_BASE) - 0x00001000)
22225 +#endif
22226
22227 #define CONFIG_SPL_FRAMEWORK
22228 #define CONFIG_SPL_NAND_SUPPORT
22229 diff -ruN u-boot-2015.01-rc3/include/configs/venice2.h u-boot/include/configs/venice2.h
22230 --- u-boot-2015.01-rc3/include/configs/venice2.h 2014-12-08 22:35:08.000000000 +0100
22231 +++ u-boot/include/configs/venice2.h 2015-01-01 17:34:32.821493940 +0100
22232 @@ -25,12 +25,7 @@
22233
22234 /* I2C */
22235 #define CONFIG_SYS_I2C_TEGRA
22236 -#define CONFIG_SYS_I2C_INIT_BOARD
22237 -#define CONFIG_I2C_MULTI_BUS
22238 -#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS
22239 -#define CONFIG_SYS_I2C_SPEED 100000
22240 #define CONFIG_CMD_I2C
22241 -#define CONFIG_SYS_I2C
22242
22243 /* SD/MMC */
22244 #define CONFIG_MMC
22245 diff -ruN u-boot-2015.01-rc3/include/configs/vexpress_aemv8a.h u-boot/include/configs/vexpress_aemv8a.h
22246 --- u-boot-2015.01-rc3/include/configs/vexpress_aemv8a.h 2014-12-08 22:35:08.000000000 +0100
22247 +++ u-boot/include/configs/vexpress_aemv8a.h 2015-01-01 17:34:32.821493940 +0100
22248 @@ -8,6 +8,9 @@
22249 #ifndef __VEXPRESS_AEMV8A_H
22250 #define __VEXPRESS_AEMV8A_H
22251
22252 +/* We use generic board for v8 Versatile Express */
22253 +#define CONFIG_SYS_GENERIC_BOARD
22254 +
22255 #ifdef CONFIG_BASE_FVP
22256 #ifndef CONFIG_SEMIHOSTING
22257 #error CONFIG_BASE_FVP requires CONFIG_SEMIHOSTING
22258 @@ -25,8 +28,6 @@
22259
22260 /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
22261
22262 -/*#define CONFIG_SYS_GENERIC_BOARD*/
22263 -
22264 #define CONFIG_SYS_NO_FLASH
22265
22266 #define CONFIG_SUPPORT_RAW_INITRD
22267 diff -ruN u-boot-2015.01-rc3/include/configs/whistler.h u-boot/include/configs/whistler.h
22268 --- u-boot-2015.01-rc3/include/configs/whistler.h 2014-12-08 22:35:08.000000000 +0100
22269 +++ u-boot/include/configs/whistler.h 2015-01-01 17:34:32.821493940 +0100
22270 @@ -26,10 +26,7 @@
22271
22272 /* I2C */
22273 #define CONFIG_SYS_I2C_TEGRA
22274 -#define CONFIG_SYS_I2C_INIT_BOARD
22275 -#define CONFIG_SYS_I2C_SPEED 100000
22276 #define CONFIG_CMD_I2C
22277 -#define CONFIG_SYS_I2C
22278
22279 /* SD/MMC */
22280 #define CONFIG_MMC
22281 diff -ruN u-boot-2015.01-rc3/include/dfu.h u-boot/include/dfu.h
22282 --- u-boot-2015.01-rc3/include/dfu.h 2014-12-08 22:35:08.000000000 +0100
22283 +++ u-boot/include/dfu.h 2015-01-01 17:34:32.825493874 +0100
22284 @@ -150,9 +150,6 @@
22285 char *dfu_extract_token(char** e, int *n);
22286 void dfu_trigger_reset(void);
22287 int dfu_get_alt(char *name);
22288 -bool dfu_detach(void);
22289 -void dfu_trigger_detach(void);
22290 -void dfu_clear_detach(void);
22291 int dfu_init_env_entities(char *interface, char *devstr);
22292 unsigned char *dfu_get_buf(struct dfu_entity *dfu);
22293 unsigned char *dfu_free_buf(void);
22294 diff -ruN u-boot-2015.01-rc3/include/dm/uclass-id.h u-boot/include/dm/uclass-id.h
22295 --- u-boot-2015.01-rc3/include/dm/uclass-id.h 2014-12-08 22:35:08.000000000 +0100
22296 +++ u-boot/include/dm/uclass-id.h 2015-01-01 17:34:32.825493874 +0100
22297 @@ -19,6 +19,7 @@
22298 UCLASS_TEST_FDT,
22299 UCLASS_TEST_BUS,
22300 UCLASS_SPI_EMUL, /* sandbox SPI device emulator */
22301 + UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
22302 UCLASS_SIMPLE_BUS,
22303
22304 /* U-Boot uclasses start here */
22305 @@ -29,6 +30,9 @@
22306 UCLASS_SPI_FLASH, /* SPI flash */
22307 UCLASS_CROS_EC, /* Chrome OS EC */
22308 UCLASS_THERMAL, /* Thermal sensor */
22309 + UCLASS_I2C, /* I2C bus */
22310 + UCLASS_I2C_GENERIC, /* Generic I2C device */
22311 + UCLASS_I2C_EEPROM, /* I2C EEPROM device */
22312
22313 UCLASS_COUNT,
22314 UCLASS_INVALID = -1,
22315 diff -ruN u-boot-2015.01-rc3/include/dm/ut.h u-boot/include/dm/ut.h
22316 --- u-boot-2015.01-rc3/include/dm/ut.h 2014-12-08 22:35:08.000000000 +0100
22317 +++ u-boot/include/dm/ut.h 2015-01-01 17:34:32.825493874 +0100
22318 @@ -89,6 +89,18 @@
22319 } \
22320 }
22321
22322 +/* Assert that a pointer is not NULL */
22323 +#define ut_assertnonnull(expr) { \
22324 + const void *val = (expr); \
22325 + \
22326 + if (val == NULL) { \
22327 + ut_failf(dms, __FILE__, __LINE__, __func__, \
22328 + #expr " = NULL", \
22329 + "Expected non-null, got NULL"); \
22330 + return -1; \
22331 + } \
22332 +}
22333 +
22334 /* Assert that an operation succeeds (returns 0) */
22335 #define ut_assertok(cond) ut_asserteq(0, cond)
22336
22337 diff -ruN u-boot-2015.01-rc3/include/dt-bindings/pinctrl/pinctrl-tegra.h u-boot/include/dt-bindings/pinctrl/pinctrl-tegra.h
22338 --- u-boot-2015.01-rc3/include/dt-bindings/pinctrl/pinctrl-tegra.h 1970-01-01 01:00:00.000000000 +0100
22339 +++ u-boot/include/dt-bindings/pinctrl/pinctrl-tegra.h 2015-01-01 17:34:32.825493874 +0100
22340 @@ -0,0 +1,45 @@
22341 +/*
22342 + * This header provides constants for Tegra pinctrl bindings.
22343 + *
22344 + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
22345 + *
22346 + * Author: Laxman Dewangan <ldewangan@nvidia.com>
22347 + *
22348 + * This program is free software; you can redistribute it and/or modify it
22349 + * under the terms and conditions of the GNU General Public License,
22350 + * version 2, as published by the Free Software Foundation.
22351 + *
22352 + * This program is distributed in the hope it will be useful, but WITHOUT
22353 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
22354 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22355 + * more details.
22356 + */
22357 +
22358 +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H
22359 +#define _DT_BINDINGS_PINCTRL_TEGRA_H
22360 +
22361 +/*
22362 + * Enable/disable for diffeent dt properties. This is applicable for
22363 + * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain,
22364 + * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt.
22365 + */
22366 +#define TEGRA_PIN_DISABLE 0
22367 +#define TEGRA_PIN_ENABLE 1
22368 +
22369 +#define TEGRA_PIN_PULL_NONE 0
22370 +#define TEGRA_PIN_PULL_DOWN 1
22371 +#define TEGRA_PIN_PULL_UP 2
22372 +
22373 +/* Low power mode driver */
22374 +#define TEGRA_PIN_LP_DRIVE_DIV_8 0
22375 +#define TEGRA_PIN_LP_DRIVE_DIV_4 1
22376 +#define TEGRA_PIN_LP_DRIVE_DIV_2 2
22377 +#define TEGRA_PIN_LP_DRIVE_DIV_1 3
22378 +
22379 +/* Rising/Falling slew rate */
22380 +#define TEGRA_PIN_SLEW_RATE_FASTEST 0
22381 +#define TEGRA_PIN_SLEW_RATE_FAST 1
22382 +#define TEGRA_PIN_SLEW_RATE_SLOW 2
22383 +#define TEGRA_PIN_SLEW_RATE_SLOWEST 3
22384 +
22385 +#endif
22386 diff -ruN u-boot-2015.01-rc3/include/dt-bindings/reset/altr,rst-mgr.h u-boot/include/dt-bindings/reset/altr,rst-mgr.h
22387 --- u-boot-2015.01-rc3/include/dt-bindings/reset/altr,rst-mgr.h 2014-12-08 22:35:08.000000000 +0100
22388 +++ u-boot/include/dt-bindings/reset/altr,rst-mgr.h 2015-01-01 17:34:32.825493874 +0100
22389 @@ -1,14 +1,7 @@
22390 /*
22391 * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
22392 *
22393 - * This software is licensed under the terms of the GNU General Public
22394 - * License version 2, as published by the Free Software Foundation, and
22395 - * may be copied, distributed, and modified under those terms.
22396 - *
22397 - * This program is distributed in the hope that it will be useful,
22398 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
22399 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22400 - * GNU General Public License for more details.
22401 + * SPDX-License-Identifier: GPL-2.0
22402 */
22403
22404 #ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H
22405 diff -ruN u-boot-2015.01-rc3/include/errno.h u-boot/include/errno.h
22406 --- u-boot-2015.01-rc3/include/errno.h 2014-12-08 22:35:08.000000000 +0100
22407 +++ u-boot/include/errno.h 2015-01-01 17:34:32.829493808 +0100
22408 @@ -6,4 +6,7 @@
22409
22410 #define __set_errno(val) do { errno = val; } while (0)
22411
22412 +#ifdef CONFIG_ERRNO_STR
22413 +const char *errno_str(int errno);
22414 +#endif
22415 #endif /* _ERRNO_H */
22416 diff -ruN u-boot-2015.01-rc3/include/fsl_ddr_sdram.h u-boot/include/fsl_ddr_sdram.h
22417 --- u-boot-2015.01-rc3/include/fsl_ddr_sdram.h 2014-12-08 22:35:08.000000000 +0100
22418 +++ u-boot/include/fsl_ddr_sdram.h 2015-01-01 17:34:32.829493808 +0100
22419 @@ -114,6 +114,7 @@
22420 #define SDRAM_CFG_2T_EN 0x00008000
22421 #define SDRAM_CFG_BI 0x00000001
22422
22423 +#define SDRAM_CFG2_FRC_SR 0x80000000
22424 #define SDRAM_CFG2_D_INIT 0x00000010
22425 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000
22426 #define SDRAM_CFG2_ODT_NEVER 0
22427 @@ -163,6 +164,7 @@
22428 #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
22429 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
22430 #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
22431 +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
22432
22433 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
22434 (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
22435 @@ -202,6 +204,8 @@
22436 #define DDR_CDR_ODT_120ohm 0x6
22437 #endif
22438
22439 +#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
22440 +
22441 /* Record of register values computed */
22442 typedef struct fsl_ddr_cfg_regs_s {
22443 struct {
22444 @@ -414,9 +418,11 @@
22445 int board_need_mem_reset(void)
22446 __attribute__((weak, alias("__board_need_mem_reset")));
22447
22448 -void __weak board_mem_sleep_setup(void)
22449 -{
22450 -}
22451 +#if defined(CONFIG_DEEP_SLEEP)
22452 +void board_mem_sleep_setup(void);
22453 +bool is_warm_boot(void);
22454 +int fsl_dp_resume(void);
22455 +#endif
22456
22457 /*
22458 * The 85xx boards have a common prototype for fixed_sdram so put the
22459 diff -ruN u-boot-2015.01-rc3/include/fsl_usb.h u-boot/include/fsl_usb.h
22460 --- u-boot-2015.01-rc3/include/fsl_usb.h 2014-12-08 22:35:08.000000000 +0100
22461 +++ u-boot/include/fsl_usb.h 2015-01-01 17:34:32.829493808 +0100
22462 @@ -145,6 +145,25 @@
22463 return SVR_SOC_VER(get_svr()) == SVR_T4240 &&
22464 IS_SVR_REV(get_svr(), 2, 0);
22465 }
22466 +
22467 +static inline bool has_erratum_a007792(void)
22468 +{
22469 + u32 svr = get_svr();
22470 + u32 soc = SVR_SOC_VER(svr);
22471 +
22472 + switch (soc) {
22473 + case SVR_T4240:
22474 + case SVR_T4160:
22475 + return IS_SVR_REV(svr, 2, 0);
22476 + case SVR_T1040:
22477 + return IS_SVR_REV(svr, 1, 0);
22478 + case SVR_T2080:
22479 + case SVR_T2081:
22480 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
22481 + }
22482 + return false;
22483 +}
22484 +
22485 #else
22486 static inline bool has_erratum_a006261(void)
22487 {
22488 @@ -161,5 +180,9 @@
22489 return false;
22490 }
22491
22492 +static inline bool has_erratum_a007792(void)
22493 +{
22494 + return false;
22495 +}
22496 #endif
22497 #endif /*_ASM_FSL_USB_H_ */
22498 diff -ruN u-boot-2015.01-rc3/include/g_dnl.h u-boot/include/g_dnl.h
22499 --- u-boot-2015.01-rc3/include/g_dnl.h 2014-12-08 22:35:08.000000000 +0100
22500 +++ u-boot/include/g_dnl.h 2015-01-01 17:34:32.829493808 +0100
22501 @@ -39,4 +39,8 @@
22502 void g_dnl_unregister(void);
22503 void g_dnl_set_serialnumber(char *);
22504
22505 +bool g_dnl_detach(void);
22506 +void g_dnl_trigger_detach(void);
22507 +void g_dnl_clear_detach(void);
22508 +
22509 #endif /* __G_DOWNLOAD_H_ */
22510 diff -ruN u-boot-2015.01-rc3/include/i2c_eeprom.h u-boot/include/i2c_eeprom.h
22511 --- u-boot-2015.01-rc3/include/i2c_eeprom.h 1970-01-01 01:00:00.000000000 +0100
22512 +++ u-boot/include/i2c_eeprom.h 2015-01-01 17:34:32.833493744 +0100
22513 @@ -0,0 +1,19 @@
22514 +/*
22515 + * Copyright (c) 2014 Google, Inc
22516 + *
22517 + * SPDX-License-Identifier: GPL-2.0+
22518 + */
22519 +
22520 +#ifndef __I2C_EEPROM
22521 +#define __I2C_EEPROM
22522 +
22523 +struct i2c_eeprom_ops {
22524 + int (*read)(struct udevice *dev, int offset, uint8_t *buf, int size);
22525 + int (*write)(struct udevice *dev, int offset, const uint8_t *buf,
22526 + int size);
22527 +};
22528 +
22529 +struct i2c_eeprom {
22530 +};
22531 +
22532 +#endif
22533 diff -ruN u-boot-2015.01-rc3/include/i2c.h u-boot/include/i2c.h
22534 --- u-boot-2015.01-rc3/include/i2c.h 2014-12-08 22:35:08.000000000 +0100
22535 +++ u-boot/include/i2c.h 2015-01-01 17:34:32.833493744 +0100
22536 @@ -18,6 +18,355 @@
22537 #define _I2C_H_
22538
22539 /*
22540 + * For now there are essentially two parts to this file - driver model
22541 + * here at the top, and the older code below (with CONFIG_SYS_I2C being
22542 + * most recent). The plan is to migrate everything to driver model.
22543 + * The driver model structures and API are separate as they are different
22544 + * enough as to be incompatible for compilation purposes.
22545 + */
22546 +
22547 +#ifdef CONFIG_DM_I2C
22548 +
22549 +enum dm_i2c_chip_flags {
22550 + DM_I2C_CHIP_10BIT = 1 << 0, /* Use 10-bit addressing */
22551 + DM_I2C_CHIP_RD_ADDRESS = 1 << 1, /* Send address for each read byte */
22552 + DM_I2C_CHIP_WR_ADDRESS = 1 << 2, /* Send address for each write byte */
22553 +};
22554 +
22555 +/**
22556 + * struct dm_i2c_chip - information about an i2c chip
22557 + *
22558 + * An I2C chip is a device on the I2C bus. It sits at a particular address
22559 + * and normally supports 7-bit or 10-bit addressing.
22560 + *
22561 + * To obtain this structure, use dev_get_parentdata(dev) where dev is the
22562 + * chip to examine.
22563 + *
22564 + * @chip_addr: Chip address on bus
22565 + * @offset_len: Length of offset in bytes. A single byte offset can
22566 + * represent up to 256 bytes. A value larger than 1 may be
22567 + * needed for larger devices.
22568 + * @flags: Flags for this chip (dm_i2c_chip_flags)
22569 + * @emul: Emulator for this chip address (only used for emulation)
22570 + */
22571 +struct dm_i2c_chip {
22572 + uint chip_addr;
22573 + uint offset_len;
22574 + uint flags;
22575 +#ifdef CONFIG_SANDBOX
22576 + struct udevice *emul;
22577 +#endif
22578 +};
22579 +
22580 +/**
22581 + * struct dm_i2c_bus- information about an i2c bus
22582 + *
22583 + * An I2C bus contains 0 or more chips on it, each at its own address. The
22584 + * bus can operate at different speeds (measured in Hz, typically 100KHz
22585 + * or 400KHz).
22586 + *
22587 + * To obtain this structure, use bus->uclass_priv where bus is the I2C
22588 + * bus udevice.
22589 + *
22590 + * @speed_hz: Bus speed in hertz (typically 100000)
22591 + */
22592 +struct dm_i2c_bus {
22593 + int speed_hz;
22594 +};
22595 +
22596 +/**
22597 + * i2c_read() - read bytes from an I2C chip
22598 + *
22599 + * To obtain an I2C device (called a 'chip') given the I2C bus address you
22600 + * can use i2c_get_chip(). To obtain a bus by bus number use
22601 + * uclass_get_device_by_seq(UCLASS_I2C, <bus number>).
22602 + *
22603 + * To set the address length of a devce use i2c_set_addr_len(). It
22604 + * defaults to 1.
22605 + *
22606 + * @dev: Chip to read from
22607 + * @offset: Offset within chip to start reading
22608 + * @buffer: Place to put data
22609 + * @len: Number of bytes to read
22610 + *
22611 + * @return 0 on success, -ve on failure
22612 + */
22613 +int i2c_read(struct udevice *dev, uint offset, uint8_t *buffer,
22614 + int len);
22615 +
22616 +/**
22617 + * i2c_write() - write bytes to an I2C chip
22618 + *
22619 + * See notes for i2c_read() above.
22620 + *
22621 + * @dev: Chip to write to
22622 + * @offset: Offset within chip to start writing
22623 + * @buffer: Buffer containing data to write
22624 + * @len: Number of bytes to write
22625 + *
22626 + * @return 0 on success, -ve on failure
22627 + */
22628 +int i2c_write(struct udevice *dev, uint offset, const uint8_t *buffer,
22629 + int len);
22630 +
22631 +/**
22632 + * i2c_probe() - probe a particular chip address
22633 + *
22634 + * This can be useful to check for the existence of a chip on the bus.
22635 + * It is typically implemented by writing the chip address to the bus
22636 + * and checking that the chip replies with an ACK.
22637 + *
22638 + * @bus: Bus to probe
22639 + * @chip_addr: 7-bit address to probe (10-bit and others are not supported)
22640 + * @chip_flags: Flags for the probe (see enum dm_i2c_chip_flags)
22641 + * @devp: Returns the device found, or NULL if none
22642 + * @return 0 if a chip was found at that address, -ve if not
22643 + */
22644 +int i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags,
22645 + struct udevice **devp);
22646 +
22647 +/**
22648 + * i2c_set_bus_speed() - set the speed of a bus
22649 + *
22650 + * @bus: Bus to adjust
22651 + * @speed: Requested speed in Hz
22652 + * @return 0 if OK, -EINVAL for invalid values
22653 + */
22654 +int i2c_set_bus_speed(struct udevice *bus, unsigned int speed);
22655 +
22656 +/**
22657 + * i2c_get_bus_speed() - get the speed of a bus
22658 + *
22659 + * @bus: Bus to check
22660 + * @return speed of selected I2C bus in Hz, -ve on error
22661 + */
22662 +int i2c_get_bus_speed(struct udevice *bus);
22663 +
22664 +/**
22665 + * i2c_set_chip_flags() - set flags for a chip
22666 + *
22667 + * Typically addresses are 7 bits, but for 10-bit addresses you should set
22668 + * flags to DM_I2C_CHIP_10BIT. All accesses will then use 10-bit addressing.
22669 + *
22670 + * @dev: Chip to adjust
22671 + * @flags: New flags
22672 + * @return 0 if OK, -EINVAL if value is unsupported, other -ve value on error
22673 + */
22674 +int i2c_set_chip_flags(struct udevice *dev, uint flags);
22675 +
22676 +/**
22677 + * i2c_get_chip_flags() - get flags for a chip
22678 + *
22679 + * @dev: Chip to check
22680 + * @flagsp: Place to put flags
22681 + * @return 0 if OK, other -ve value on error
22682 + */
22683 +int i2c_get_chip_flags(struct udevice *dev, uint *flagsp);
22684 +
22685 +/**
22686 + * i2c_set_offset_len() - set the offset length for a chip
22687 + *
22688 + * The offset used to access a chip may be up to 4 bytes long. Typically it
22689 + * is only 1 byte, which is enough for chips with 256 bytes of memory or
22690 + * registers. The default value is 1, but you can call this function to
22691 + * change it.
22692 + *
22693 + * @offset_len: New offset length value (typically 1 or 2)
22694 + */
22695 +
22696 +int i2c_set_chip_offset_len(struct udevice *dev, uint offset_len);
22697 +/**
22698 + * i2c_deblock() - recover a bus that is in an unknown state
22699 + *
22700 + * See the deblock() method in 'struct dm_i2c_ops' for full information
22701 + *
22702 + * @bus: Bus to recover
22703 + * @return 0 if OK, -ve on error
22704 + */
22705 +int i2c_deblock(struct udevice *bus);
22706 +
22707 +/*
22708 + * Not all of these flags are implemented in the U-Boot API
22709 + */
22710 +enum dm_i2c_msg_flags {
22711 + I2C_M_TEN = 0x0010, /* ten-bit chip address */
22712 + I2C_M_RD = 0x0001, /* read data, from slave to master */
22713 + I2C_M_STOP = 0x8000, /* send stop after this message */
22714 + I2C_M_NOSTART = 0x4000, /* no start before this message */
22715 + I2C_M_REV_DIR_ADDR = 0x2000, /* invert polarity of R/W bit */
22716 + I2C_M_IGNORE_NAK = 0x1000, /* continue after NAK */
22717 + I2C_M_NO_RD_ACK = 0x0800, /* skip the Ack bit on reads */
22718 + I2C_M_RECV_LEN = 0x0400, /* length is first received byte */
22719 +};
22720 +
22721 +/**
22722 + * struct i2c_msg - an I2C message
22723 + *
22724 + * @addr: Slave address
22725 + * @flags: Flags (see enum dm_i2c_msg_flags)
22726 + * @len: Length of buffer in bytes, may be 0 for a probe
22727 + * @buf: Buffer to send/receive, or NULL if no data
22728 + */
22729 +struct i2c_msg {
22730 + uint addr;
22731 + uint flags;
22732 + uint len;
22733 + u8 *buf;
22734 +};
22735 +
22736 +/**
22737 + * struct i2c_msg_list - a list of I2C messages
22738 + *
22739 + * This is called i2c_rdwr_ioctl_data in Linux but the name does not seem
22740 + * appropriate in U-Boot.
22741 + *
22742 + * @msg: Pointer to i2c_msg array
22743 + * @nmsgs: Number of elements in the array
22744 + */
22745 +struct i2c_msg_list {
22746 + struct i2c_msg *msgs;
22747 + uint nmsgs;
22748 +};
22749 +
22750 +/**
22751 + * struct dm_i2c_ops - driver operations for I2C uclass
22752 + *
22753 + * Drivers should support these operations unless otherwise noted. These
22754 + * operations are intended to be used by uclass code, not directly from
22755 + * other code.
22756 + */
22757 +struct dm_i2c_ops {
22758 + /**
22759 + * xfer() - transfer a list of I2C messages
22760 + *
22761 + * @bus: Bus to read from
22762 + * @msg: List of messages to transfer
22763 + * @nmsgs: Number of messages in the list
22764 + * @return 0 if OK, -EREMOTEIO if the slave did not ACK a byte,
22765 + * -ECOMM if the speed cannot be supported, -EPROTO if the chip
22766 + * flags cannot be supported, other -ve value on some other error
22767 + */
22768 + int (*xfer)(struct udevice *bus, struct i2c_msg *msg, int nmsgs);
22769 +
22770 + /**
22771 + * probe_chip() - probe for the presense of a chip address
22772 + *
22773 + * This function is optional. If omitted, the uclass will send a zero
22774 + * length message instead.
22775 + *
22776 + * @bus: Bus to probe
22777 + * @chip_addr: Chip address to probe
22778 + * @chip_flags: Probe flags (enum dm_i2c_chip_flags)
22779 + * @return 0 if chip was found, -EREMOTEIO if not, -ENOSYS to fall back
22780 + * to default probem other -ve value on error
22781 + */
22782 + int (*probe_chip)(struct udevice *bus, uint chip_addr, uint chip_flags);
22783 +
22784 + /**
22785 + * set_bus_speed() - set the speed of a bus (optional)
22786 + *
22787 + * The bus speed value will be updated by the uclass if this function
22788 + * does not return an error. This method is optional - if it is not
22789 + * provided then the driver can read the speed from
22790 + * bus->uclass_priv->speed_hz
22791 + *
22792 + * @bus: Bus to adjust
22793 + * @speed: Requested speed in Hz
22794 + * @return 0 if OK, -EINVAL for invalid values
22795 + */
22796 + int (*set_bus_speed)(struct udevice *bus, unsigned int speed);
22797 +
22798 + /**
22799 + * get_bus_speed() - get the speed of a bus (optional)
22800 + *
22801 + * Normally this can be provided by the uclass, but if you want your
22802 + * driver to check the bus speed by looking at the hardware, you can
22803 + * implement that here. This method is optional. This method would
22804 + * normally be expected to return bus->uclass_priv->speed_hz.
22805 + *
22806 + * @bus: Bus to check
22807 + * @return speed of selected I2C bus in Hz, -ve on error
22808 + */
22809 + int (*get_bus_speed)(struct udevice *bus);
22810 +
22811 + /**
22812 + * set_flags() - set the flags for a chip (optional)
22813 + *
22814 + * This is generally implemented by the uclass, but drivers can
22815 + * check the value to ensure that unsupported options are not used.
22816 + * This method is optional. If provided, this method will always be
22817 + * called when the flags change.
22818 + *
22819 + * @dev: Chip to adjust
22820 + * @flags: New flags value
22821 + * @return 0 if OK, -EINVAL if value is unsupported
22822 + */
22823 + int (*set_flags)(struct udevice *dev, uint flags);
22824 +
22825 + /**
22826 + * deblock() - recover a bus that is in an unknown state
22827 + *
22828 + * I2C is a synchronous protocol and resets of the processor in the
22829 + * middle of an access can block the I2C Bus until a powerdown of
22830 + * the full unit is done. This is because slaves can be stuck
22831 + * waiting for addition bus transitions for a transaction that will
22832 + * never complete. Resetting the I2C master does not help. The only
22833 + * way is to force the bus through a series of transitions to make
22834 + * sure that all slaves are done with the transaction. This method
22835 + * performs this 'deblocking' if support by the driver.
22836 + *
22837 + * This method is optional.
22838 + */
22839 + int (*deblock)(struct udevice *bus);
22840 +};
22841 +
22842 +#define i2c_get_ops(dev) ((struct dm_i2c_ops *)(dev)->driver->ops)
22843 +
22844 +/**
22845 + * i2c_get_chip() - get a device to use to access a chip on a bus
22846 + *
22847 + * This returns the device for the given chip address. The device can then
22848 + * be used with calls to i2c_read(), i2c_write(), i2c_probe(), etc.
22849 + *
22850 + * @bus: Bus to examine
22851 + * @chip_addr: Chip address for the new device
22852 + * @devp: Returns pointer to new device if found or -ENODEV if not
22853 + * found
22854 + */
22855 +int i2c_get_chip(struct udevice *bus, uint chip_addr, struct udevice **devp);
22856 +
22857 +/**
22858 + * i2c_get_chip() - get a device to use to access a chip on a bus number
22859 + *
22860 + * This returns the device for the given chip address on a particular bus
22861 + * number.
22862 + *
22863 + * @busnum: Bus number to examine
22864 + * @chip_addr: Chip address for the new device
22865 + * @devp: Returns pointer to new device if found or -ENODEV if not
22866 + * found
22867 + */
22868 +int i2c_get_chip_for_busnum(int busnum, int chip_addr, struct udevice **devp);
22869 +
22870 +/**
22871 + * i2c_chip_ofdata_to_platdata() - Decode standard I2C platform data
22872 + *
22873 + * This decodes the chip address from a device tree node and puts it into
22874 + * its dm_i2c_chip structure. This should be called in your driver's
22875 + * ofdata_to_platdata() method.
22876 + *
22877 + * @blob: Device tree blob
22878 + * @node: Node offset to read from
22879 + * @spi: Place to put the decoded information
22880 + */
22881 +int i2c_chip_ofdata_to_platdata(const void *blob, int node,
22882 + struct dm_i2c_chip *chip);
22883 +
22884 +#endif
22885 +
22886 +#ifndef CONFIG_DM_I2C
22887 +
22888 +/*
22889 * WARNING WARNING WARNING WARNING WARNING WARNING WARNING WARNING
22890 *
22891 * The implementation MUST NOT use static or global variables if the
22892 @@ -451,4 +800,7 @@
22893 * @return 0 if port was reset, -1 if not found
22894 */
22895 int i2c_reset_port_fdt(const void *blob, int node);
22896 +
22897 +#endif /* !CONFIG_DM_I2C */
22898 +
22899 #endif /* _I2C_H_ */
22900 diff -ruN u-boot-2015.01-rc3/include/linux/linkage.h u-boot/include/linux/linkage.h
22901 --- u-boot-2015.01-rc3/include/linux/linkage.h 2014-12-08 22:35:08.000000000 +0100
22902 +++ u-boot/include/linux/linkage.h 2015-01-01 17:34:32.837493678 +0100
22903 @@ -17,7 +17,9 @@
22904 #define CPP_ASMLINKAGE
22905 #endif
22906
22907 +#ifndef asmlinkage
22908 #define asmlinkage CPP_ASMLINKAGE
22909 +#endif
22910
22911 #define SYMBOL_NAME_STR(X) #X
22912 #define SYMBOL_NAME(X) X
22913 diff -ruN u-boot-2015.01-rc3/include/linux/string.h u-boot/include/linux/string.h
22914 --- u-boot-2015.01-rc3/include/linux/string.h 2014-12-08 22:35:08.000000000 +0100
22915 +++ u-boot/include/linux/string.h 2015-01-01 17:34:32.837493678 +0100
22916 @@ -30,6 +30,9 @@
22917 #ifndef __HAVE_ARCH_STRNCPY
22918 extern char * strncpy(char *,const char *, __kernel_size_t);
22919 #endif
22920 +#ifndef __HAVE_ARCH_STRLCPY
22921 +size_t strlcpy(char *, const char *, size_t);
22922 +#endif
22923 #ifndef __HAVE_ARCH_STRCAT
22924 extern char * strcat(char *, const char *);
22925 #endif
22926 diff -ruN u-boot-2015.01-rc3/include/mmc.h u-boot/include/mmc.h
22927 --- u-boot-2015.01-rc3/include/mmc.h 2014-12-08 22:35:08.000000000 +0100
22928 +++ u-boot/include/mmc.h 2015-01-01 17:34:32.841493612 +0100
22929 @@ -31,6 +31,7 @@
22930 #define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403)
22931 #define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429)
22932 #define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405)
22933 +#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x500)
22934
22935 #define MMC_MODE_HS (1 << 0)
22936 #define MMC_MODE_HS_52MHz (1 << 1)
22937 @@ -147,6 +148,7 @@
22938 * EXT_CSD fields
22939 */
22940 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
22941 +#define EXT_CSD_PARTITION_SETTING 155 /* R/W */
22942 #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
22943 #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
22944 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
22945 @@ -197,6 +199,8 @@
22946 #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
22947 #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
22948
22949 +#define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
22950 +
22951 #define R1_ILLEGAL_COMMAND (1 << 22)
22952 #define R1_APP_CMD (1 << 5)
22953
22954 @@ -314,6 +318,7 @@
22955 char init_in_progress; /* 1 if we have done mmc_start_init() */
22956 char preinit; /* start init as early as possible */
22957 uint op_cond_response; /* the response byte from the last op_cond */
22958 + int ddr_mode;
22959 };
22960
22961 int mmc_register(struct mmc *mmc);
22962 diff -ruN u-boot-2015.01-rc3/include/part.h u-boot/include/part.h
22963 --- u-boot-2015.01-rc3/include/part.h 2014-12-08 22:35:08.000000000 +0100
22964 +++ u-boot/include/part.h 2015-01-01 17:34:32.845493546 +0100
22965 @@ -244,6 +244,26 @@
22966 */
22967 int gpt_restore(block_dev_desc_t *dev_desc, char *str_disk_guid,
22968 disk_partition_t *partitions, const int parts_count);
22969 +
22970 +/**
22971 + * is_valid_gpt_buf() - Ensure that the Primary GPT information is valid
22972 + *
22973 + * @param dev_desc - block device descriptor
22974 + * @param buf - buffer which contains the MBR and Primary GPT info
22975 + *
22976 + * @return - '0' on success, otherwise error
22977 + */
22978 +int is_valid_gpt_buf(block_dev_desc_t *dev_desc, void *buf);
22979 +
22980 +/**
22981 + * write_mbr_and_gpt_partitions() - write MBR, Primary GPT and Backup GPT
22982 + *
22983 + * @param dev_desc - block device descriptor
22984 + * @param buf - buffer which contains the MBR and Primary GPT info
22985 + *
22986 + * @return - '0' on success, otherwise error
22987 + */
22988 +int write_mbr_and_gpt_partitions(block_dev_desc_t *dev_desc, void *buf);
22989 #endif
22990
22991 #endif /* _PART_H */
22992 diff -ruN u-boot-2015.01-rc3/include/pci_ids.h u-boot/include/pci_ids.h
22993 --- u-boot-2015.01-rc3/include/pci_ids.h 2014-12-08 22:35:08.000000000 +0100
22994 +++ u-boot/include/pci_ids.h 2015-01-01 17:34:32.845493546 +0100
22995 @@ -2998,6 +2998,14 @@
22996 #define PCI_DEVICE_ID_INTEL_82454NX 0x84cb
22997 #define PCI_DEVICE_ID_INTEL_84460GX 0x84ea
22998 #define PCI_DEVICE_ID_INTEL_IXP4XX 0x8500
22999 +#define PCI_DEVICE_ID_INTEL_TCF_GBE 0x8802
23000 +#define PCI_DEVICE_ID_INTEL_TCF_SDIO_0 0x8809
23001 +#define PCI_DEVICE_ID_INTEL_TCF_SDIO_1 0x880a
23002 +#define PCI_DEVICE_ID_INTEL_TCF_SATA 0x880b
23003 +#define PCI_DEVICE_ID_INTEL_TCF_UART_0 0x8811
23004 +#define PCI_DEVICE_ID_INTEL_TCF_UART_1 0x8812
23005 +#define PCI_DEVICE_ID_INTEL_TCF_UART_2 0x8813
23006 +#define PCI_DEVICE_ID_INTEL_TCF_UART_3 0x8814
23007 #define PCI_DEVICE_ID_INTEL_IXP2800 0x9004
23008 #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152
23009
23010 diff -ruN u-boot-2015.01-rc3/include/smsc_lpc47m.h u-boot/include/smsc_lpc47m.h
23011 --- u-boot-2015.01-rc3/include/smsc_lpc47m.h 1970-01-01 01:00:00.000000000 +0100
23012 +++ u-boot/include/smsc_lpc47m.h 2015-01-01 17:34:32.849493480 +0100
23013 @@ -0,0 +1,19 @@
23014 +/*
23015 + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
23016 + *
23017 + * SPDX-License-Identifier: GPL-2.0+
23018 + */
23019 +
23020 +#ifndef _SMSC_LPC47M_H_
23021 +#define _SMSC_LPC47M_H_
23022 +
23023 +/**
23024 + * Configure the base I/O port of the specified serial device and enable the
23025 + * serial device.
23026 + *
23027 + * @dev: High 8 bits = Super I/O port, low 8 bits = logical device number.
23028 + * @iobase: Processor I/O port address to assign to this serial device.
23029 + */
23030 +void lpc47m_enable_serial(u16 dev, u16 iobase);
23031 +
23032 +#endif /* _SMSC_LPC47M_H_ */
23033 diff -ruN u-boot-2015.01-rc3/include/spi.h u-boot/include/spi.h
23034 --- u-boot-2015.01-rc3/include/spi.h 2014-12-08 22:35:08.000000000 +0100
23035 +++ u-boot/include/spi.h 2015-01-01 17:34:32.849493480 +0100
23036 @@ -34,6 +34,7 @@
23037
23038 /* SPI TX operation modes */
23039 #define SPI_OPM_TX_QPP (1 << 0)
23040 +#define SPI_OPM_TX_BP (1 << 1)
23041
23042 /* SPI RX operation modes */
23043 #define SPI_OPM_RX_AS (1 << 0)
23044 diff -ruN u-boot-2015.01-rc3/include/tps6586x.h u-boot/include/tps6586x.h
23045 --- u-boot-2015.01-rc3/include/tps6586x.h 2014-12-08 22:35:08.000000000 +0100
23046 +++ u-boot/include/tps6586x.h 2015-01-01 17:34:32.849493480 +0100
23047 @@ -44,9 +44,9 @@
23048 * Set up the TPS6586X I2C bus number. This will be used for all operations
23049 * on the device. This function must be called before using other functions.
23050 *
23051 - * @param bus I2C bus number containing the TPS6586X chip
23052 + * @param bus I2C bus containing the TPS6586X chip
23053 * @return 0 (always succeeds)
23054 */
23055 -int tps6586x_init(int bus);
23056 +int tps6586x_init(struct udevice *bus);
23057
23058 #endif /* _TPS6586X_H_ */
23059 diff -ruN u-boot-2015.01-rc3/include/usb/ehci-fsl.h u-boot/include/usb/ehci-fsl.h
23060 --- u-boot-2015.01-rc3/include/usb/ehci-fsl.h 2014-12-08 22:35:08.000000000 +0100
23061 +++ u-boot/include/usb/ehci-fsl.h 2015-01-01 17:34:32.853493416 +0100
23062 @@ -280,7 +280,9 @@
23063 #define MXC_EHCI_IPPUE_DOWN (1 << 10)
23064 #define MXC_EHCI_IPPUE_UP (1 << 11)
23065
23066 +int usb_phy_mode(int port);
23067 /* Board-specific initialization */
23068 int board_ehci_hcd_init(int port);
23069 +int board_usb_phy_mode(int port);
23070
23071 #endif /* _EHCI_FSL_H */
23072 diff -ruN u-boot-2015.01-rc3/lib/asm-offsets.c u-boot/lib/asm-offsets.c
23073 --- u-boot-2015.01-rc3/lib/asm-offsets.c 2014-12-08 22:35:08.000000000 +0100
23074 +++ u-boot/lib/asm-offsets.c 2015-01-01 17:34:32.857493350 +0100
23075 @@ -31,9 +31,6 @@
23076 #ifdef CONFIG_SYS_MALLOC_F_LEN
23077 DEFINE(GD_MALLOC_BASE, offsetof(struct global_data, malloc_base));
23078 #endif
23079 -#ifdef CONFIG_X86
23080 - DEFINE(GD_BIST, offsetof(struct global_data, arch.bist));
23081 -#endif
23082
23083 #if defined(CONFIG_ARM)
23084
23085 diff -ruN u-boot-2015.01-rc3/lib/errno_str.c u-boot/lib/errno_str.c
23086 --- u-boot-2015.01-rc3/lib/errno_str.c 1970-01-01 01:00:00.000000000 +0100
23087 +++ u-boot/lib/errno_str.c 2015-01-01 17:34:32.857493350 +0100
23088 @@ -0,0 +1,147 @@
23089 +/*
23090 + * Copyright (C) 2014 Samsung Electronics
23091 + * Przemyslaw Marczak <p.marczak@samsung.com>
23092 + *
23093 + * SDPX-License-Identifier: GPL-2.0+
23094 + */
23095 +#include <common.h>
23096 +#include <errno.h>
23097 +
23098 +#define ERRNO_MSG(errno, msg) msg
23099 +#define SAME_AS(x) (const char *)&errno_message[x]
23100 +
23101 +static const char * const errno_message[] = {
23102 + ERRNO_MSG(0, "Success"),
23103 + ERRNO_MSG(EPERM, "Operation not permitted"),
23104 + ERRNO_MSG(ENOEN, "No such file or directory"),
23105 + ERRNO_MSG(ESRCH, "No such process"),
23106 + ERRNO_MSG(EINTR, "Interrupted system call"),
23107 + ERRNO_MSG(EIO, "I/O error"),
23108 + ERRNO_MSG(ENXIO, "No such device or address"),
23109 + ERRNO_MSG(E2BIG, "Argument list too long"),
23110 + ERRNO_MSG(ENOEXEC, "Exec format error"),
23111 + ERRNO_MSG(EBADF, "Bad file number"),
23112 + ERRNO_MSG(ECHILD, "No child processes"),
23113 + ERRNO_MSG(EAGAIN, "Try again"),
23114 + ERRNO_MSG(ENOMEM, "Out of memory"),
23115 + ERRNO_MSG(EACCES, "Permission denied"),
23116 + ERRNO_MSG(EFAULT, "Bad address"),
23117 + ERRNO_MSG(ENOTBL, "Block device required"),
23118 + ERRNO_MSG(EBUSY, "Device or resource busy"),
23119 + ERRNO_MSG(EEXIST, "File exists"),
23120 + ERRNO_MSG(EXDEV, "Cross-device link"),
23121 + ERRNO_MSG(ENODEV, "No such device"),
23122 + ERRNO_MSG(ENOTDIR, "Not a directory"),
23123 + ERRNO_MSG(EISDIR, "Is a directory"),
23124 + ERRNO_MSG(EINVAL, "Invalid argument"),
23125 + ERRNO_MSG(ENFILE, "File table overflow"),
23126 + ERRNO_MSG(EMFILE, "Too many open files"),
23127 + ERRNO_MSG(ENOTTY, "Not a typewriter"),
23128 + ERRNO_MSG(ETXTBSY, "Text file busy"),
23129 + ERRNO_MSG(EFBIG, "File too large"),
23130 + ERRNO_MSG(ENOSPC, "No space left on device"),
23131 + ERRNO_MSG(ESPIPE, "Illegal seek"),
23132 + ERRNO_MSG(EROFS, "Read-only file system"),
23133 + ERRNO_MSG(EMLINK, "Too many links"),
23134 + ERRNO_MSG(EPIPE, "Broken pipe"),
23135 + ERRNO_MSG(EDOM, "Math argument out of domain of func"),
23136 + ERRNO_MSG(ERANGE, "Math result not representable"),
23137 + ERRNO_MSG(EDEADLK, "Resource deadlock would occur"),
23138 + ERRNO_MSG(ENAMETOOLONG, "File name too long"),
23139 + ERRNO_MSG(ENOLCK, "No record locks available"),
23140 + ERRNO_MSG(ENOSYS, "Function not implemented"),
23141 + ERRNO_MSG(ENOTEMPTY, "Directory not empty"),
23142 + ERRNO_MSG(ELOOP, "Too many symbolic links encountered"),
23143 + ERRNO_MSG(EWOULDBLOCK, SAME_AS(EAGAIN)),
23144 + ERRNO_MSG(ENOMSG, "No message of desired type"),
23145 + ERRNO_MSG(EIDRM, "Identifier removed"),
23146 + ERRNO_MSG(ECHRNG, "Channel number out of range"),
23147 + ERRNO_MSG(EL2NSYNC, "Level 2 not synchronized"),
23148 + ERRNO_MSG(EL3HLT, "Level 3 halted"),
23149 + ERRNO_MSG(EL3RST, "Level 3 reset"),
23150 + ERRNO_MSG(ELNRNG, "Link number out of range"),
23151 + ERRNO_MSG(EUNATCH, "Protocol driver not attached"),
23152 + ERRNO_MSG(ENOCSI, "No CSI structure available"),
23153 + ERRNO_MSG(EL2HLT, "Level 2 halted"),
23154 + ERRNO_MSG(EBADE, "Invalid exchange"),
23155 + ERRNO_MSG(EBADR, "Invalid request descriptor"),
23156 + ERRNO_MSG(EXFULL, "Exchange full"),
23157 + ERRNO_MSG(ENOANO, "No anode"),
23158 + ERRNO_MSG(EBADRQC, "Invalid request code"),
23159 + ERRNO_MSG(EBADSLT, "Invalid slot"),
23160 + ERRNO_MSG(EDEADLOCK, SAME_AS(EDEADLK)),
23161 + ERRNO_MSG(EBFONT, "Bad font file format"),
23162 + ERRNO_MSG(ENOSTR, "Device not a stream"),
23163 + ERRNO_MSG(ENODATA, "No data available"),
23164 + ERRNO_MSG(ETIME, "Timer expired"),
23165 + ERRNO_MSG(ENOSR, "Out of streams resources"),
23166 + ERRNO_MSG(ENONET, "Machine is not on the network"),
23167 + ERRNO_MSG(ENOPKG, "Package not installed"),
23168 + ERRNO_MSG(EREMOTE, "Object is remote"),
23169 + ERRNO_MSG(ENOLINK, "Link has been severed"),
23170 + ERRNO_MSG(EADV, "Advertise error"),
23171 + ERRNO_MSG(ESRMNT, "Srmount error"),
23172 + ERRNO_MSG(ECOMM, "Communication error on send"),
23173 + ERRNO_MSG(EPROTO, "Protocol error"),
23174 + ERRNO_MSG(EMULTIHOP, "Multihop attempted"),
23175 + ERRNO_MSG(EDOTDOT, "RFS specific error"),
23176 + ERRNO_MSG(EBADMSG, "Not a data message"),
23177 + ERRNO_MSG(EOVERFLOW, "Value too large for defined data type"),
23178 + ERRNO_MSG(ENOTUNIQ, "Name not unique on network"),
23179 + ERRNO_MSG(EBADFD, "File descriptor in bad state"),
23180 + ERRNO_MSG(EREMCHG, "Remote address changed"),
23181 + ERRNO_MSG(ELIBACC, "Can not access a needed shared library"),
23182 + ERRNO_MSG(ELIBBAD, "Accessing a corrupted shared library"),
23183 + ERRNO_MSG(ELIBSCN, ".lib section in a.out corrupted"),
23184 + ERRNO_MSG(ELIBMAX, "Attempting to link in too many shared libraries"),
23185 + ERRNO_MSG(ELIBEXEC, "Cannot exec a shared library directly"),
23186 + ERRNO_MSG(EILSEQ, "Illegal byte sequence"),
23187 + ERRNO_MSG(ERESTART, "Interrupted system call should be restarted"),
23188 + ERRNO_MSG(ESTRPIPE, "Streams pipe error"),
23189 + ERRNO_MSG(EUSERS, "Too many users"),
23190 + ERRNO_MSG(ENOTSOCK, "Socket operation on non-socket"),
23191 + ERRNO_MSG(EDESTADDRREQ, "Destination address required"),
23192 + ERRNO_MSG(EMSGSIZE, "Message too long"),
23193 + ERRNO_MSG(EPROTOTYPE, "Protocol wrong type for socket"),
23194 + ERRNO_MSG(ENOPROTOOPT, "Protocol not available"),
23195 + ERRNO_MSG(EPROTONOSUPPORT, "Protocol not supported"),
23196 + ERRNO_MSG(ESOCKTNOSUPPORT, "Socket type not supported"),
23197 + ERRNO_MSG(EOPNOTSUPP, "Operation not supported on transport endpoint"),
23198 + ERRNO_MSG(EPFNOSUPPORT, "Protocol family not supported"),
23199 + ERRNO_MSG(AFNOSUPPORT, "Address family not supported by protocol"),
23200 + ERRNO_MSG(EADDRINUSE, "Address already in use"),
23201 + ERRNO_MSG(EADDRNOTAVAIL, "Cannot assign requested address"),
23202 + ERRNO_MSG(ENETDOWN, "Network is down"),
23203 + ERRNO_MSG(ENETUNREACH, "Network is unreachable"),
23204 + ERRNO_MSG(ENETRESET, "Network dropped connection because of reset"),
23205 + ERRNO_MSG(ECONNABORTED, "Software caused connection abort"),
23206 + ERRNO_MSG(ECONNRESET, "Connection reset by peer"),
23207 + ERRNO_MSG(ENOBUFS, "No buffer space available"),
23208 + ERRNO_MSG(EISCONN, "Transport endpoint is already connected"),
23209 + ERRNO_MSG(ENOTCONN, "Transport endpoint is not connected"),
23210 + ERRNO_MSG(ESHUTDOWN, "Cannot send after transport endpoint shutdown"),
23211 + ERRNO_MSG(ETOOMANYREFS, "Too many references: cannot splice"),
23212 + ERRNO_MSG(ETIMEDOUT, "Connection timed out"),
23213 + ERRNO_MSG(ECONNREFUSED, "Connection refused"),
23214 + ERRNO_MSG(EHOSTDOWN, "Host is down"),
23215 + ERRNO_MSG(EHOSTUNREACH, "No route to host"),
23216 + ERRNO_MSG(EALREADY, "Operation already in progress"),
23217 + ERRNO_MSG(EINPROGRESS, "Operation now in progress"),
23218 + ERRNO_MSG(ESTALE, "Stale NFS file handle"),
23219 + ERRNO_MSG(EUCLEAN, "Structure needs cleaning"),
23220 + ERRNO_MSG(ENOTNAM, "Not a XENIX named type file"),
23221 + ERRNO_MSG(ENAVAIL, "No XENIX semaphores available"),
23222 + ERRNO_MSG(EISNAM, "Is a named type file"),
23223 + ERRNO_MSG(EREMOTEIO, "Remote I/O error"),
23224 + ERRNO_MSG(EDQUOT, "Quota exceeded"),
23225 + ERRNO_MSG(ENOMEDIUM, "No medium found"),
23226 + ERRNO_MSG(EMEDIUMTYPE, "Wrong medium type"),
23227 +};
23228 +
23229 +const char *errno_str(int errno)
23230 +{
23231 + if (errno >= 0)
23232 + return errno_message[0];
23233 +
23234 + return errno_message[abs(errno)];
23235 +}
23236 diff -ruN u-boot-2015.01-rc3/lib/initcall.c u-boot/lib/initcall.c
23237 --- u-boot-2015.01-rc3/lib/initcall.c 2014-12-08 22:35:08.000000000 +0100
23238 +++ u-boot/lib/initcall.c 2015-01-01 17:34:32.861493284 +0100
23239 @@ -19,7 +19,11 @@
23240
23241 if (gd->flags & GD_FLG_RELOC)
23242 reloc_ofs = gd->reloc_off;
23243 - debug("initcall: %p\n", (char *)*init_fnc_ptr - reloc_ofs);
23244 + debug("initcall: %p", (char *)*init_fnc_ptr - reloc_ofs);
23245 + if (gd->flags & GD_FLG_RELOC)
23246 + debug(" (relocated to %p)\n", (char *)*init_fnc_ptr);
23247 + else
23248 + debug("\n");
23249 ret = (*init_fnc_ptr)();
23250 if (ret) {
23251 printf("initcall sequence %p failed at call %p (err=%d)\n",
23252 diff -ruN u-boot-2015.01-rc3/lib/Makefile u-boot/lib/Makefile
23253 --- u-boot-2015.01-rc3/lib/Makefile 2014-12-08 22:35:08.000000000 +0100
23254 +++ u-boot/lib/Makefile 2015-01-01 17:34:32.857493350 +0100
23255 @@ -51,6 +51,7 @@
23256 obj-$(CONFIG_ADDR_MAP) += addr_map.o
23257 obj-y += hashtable.o
23258 obj-y += errno.o
23259 +obj-$(CONFIG_ERRNO_STR) += errno_str.o
23260 obj-y += display_options.o
23261 obj-$(CONFIG_BCH) += bch.o
23262 obj-y += crc32.o
23263 diff -ruN u-boot-2015.01-rc3/lib/string.c u-boot/lib/string.c
23264 --- u-boot-2015.01-rc3/lib/string.c 2014-12-08 22:35:08.000000000 +0100
23265 +++ u-boot/lib/string.c 2015-01-01 17:34:32.861493284 +0100
23266 @@ -102,6 +102,31 @@
23267 }
23268 #endif
23269
23270 +#ifndef __HAVE_ARCH_STRLCPY
23271 +/**
23272 + * strlcpy - Copy a C-string into a sized buffer
23273 + * @dest: Where to copy the string to
23274 + * @src: Where to copy the string from
23275 + * @size: size of destination buffer
23276 + *
23277 + * Compatible with *BSD: the result is always a valid
23278 + * NUL-terminated string that fits in the buffer (unless,
23279 + * of course, the buffer size is zero). It does not pad
23280 + * out the result like strncpy() does.
23281 + */
23282 +size_t strlcpy(char *dest, const char *src, size_t size)
23283 +{
23284 + size_t ret = strlen(src);
23285 +
23286 + if (size) {
23287 + size_t len = (ret >= size) ? size - 1 : ret;
23288 + memcpy(dest, src, len);
23289 + dest[len] = '\0';
23290 + }
23291 + return ret;
23292 +}
23293 +#endif
23294 +
23295 #ifndef __HAVE_ARCH_STRCAT
23296 /**
23297 * strcat - Append one %NUL-terminated string to another
23298 diff -ruN u-boot-2015.01-rc3/MAINTAINERS u-boot/MAINTAINERS
23299 --- u-boot-2015.01-rc3/MAINTAINERS 2014-12-08 22:35:08.000000000 +0100
23300 +++ u-boot/MAINTAINERS 2015-01-01 17:34:31.981507711 +0100
23301 @@ -128,6 +128,12 @@
23302 F: arch/arm/cpu/arm926ejs/spear/
23303 F: arch/arm/include/asm/arch-spear/
23304
23305 +ARM STM STV0991
23306 +M: Vikas Manocha <vikas.manocha@st.com>
23307 +S: Maintained
23308 +F: arch/arm/cpu/armv7/stv0991/
23309 +F: arch/arm/include/asm/arch-stv0991/
23310 +
23311 ARM SUNXI
23312 M: Ian Campbell <ijc@hellion.org.uk>
23313 M: Hans De Goede <hdegoede@redhat.com>
23314 diff -ruN u-boot-2015.01-rc3/Makefile u-boot/Makefile
23315 --- u-boot-2015.01-rc3/Makefile 2014-12-08 22:35:08.000000000 +0100
23316 +++ u-boot/Makefile 2015-01-01 17:34:31.981507711 +0100
23317 @@ -1,7 +1,7 @@
23318 VERSION = 2015
23319 PATCHLEVEL = 01
23320 SUBLEVEL =
23321 -EXTRAVERSION = -rc3
23322 +EXTRAVERSION = -rc4
23323 NAME =
23324
23325 # *DOCUMENTATION*
23326 @@ -946,27 +946,43 @@
23327 ifneq ($(CONFIG_X86_RESET_VECTOR),)
23328 rom: u-boot.rom FORCE
23329
23330 -u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \
23331 - $(srctree)/board/$(BOARDDIR)/mrc.bin
23332 - $(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) u-boot.tmp
23333 - if [ -n "$(CONFIG_HAVE_INTEL_ME)" ]; then \
23334 - $(objtree)/tools/ifdtool -D \
23335 - $(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp; \
23336 - $(objtree)/tools/ifdtool \
23337 - -i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp; \
23338 - fi
23339 - $(objtree)/tools/ifdtool -w \
23340 - $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp
23341 - $(objtree)/tools/ifdtool -w \
23342 - $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \
23343 - u-boot.tmp
23344 - $(objtree)/tools/ifdtool -w \
23345 - $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
23346 - u-boot.tmp
23347 - $(objtree)/tools/ifdtool -w \
23348 - $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILENAME) \
23349 - u-boot.tmp
23350 - mv u-boot.tmp $@
23351 +IFDTOOL=$(objtree)/tools/ifdtool
23352 +IFDTOOL_FLAGS = -f 0:$(objtree)/u-boot.dtb
23353 +IFDTOOL_FLAGS += -m 0x$(shell $(NM) u-boot |grep _dt_ucode_base_size |cut -d' ' -f1)
23354 +IFDTOOL_FLAGS += -U $(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot.bin
23355 +IFDTOOL_FLAGS += -w $(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin
23356 +
23357 +ifneq ($(CONFIG_HAVE_INTEL_ME),)
23358 +IFDTOOL_ME_FLAGS = -D $(srctree)/board/$(BOARDDIR)/descriptor.bin
23359 +IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
23360 +endif
23361 +
23362 +ifneq ($(CONFIG_HAVE_MRC),)
23363 +IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
23364 +endif
23365 +
23366 +ifneq ($(CONFIG_HAVE_FSP),)
23367 +IFDTOOL_FLAGS += -w $(CONFIG_FSP_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_FSP_FILE)
23368 +endif
23369 +
23370 +ifneq ($(CONFIG_HAVE_CMC),)
23371 +IFDTOOL_FLAGS += -w $(CONFIG_CMC_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_CMC_FILE)
23372 +endif
23373 +
23374 +ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)
23375 +IFDTOOL_FLAGS += -w $(CONFIG_X86_OPTION_ROM_ADDR):$(srctree)/board/$(BOARDDIR)/$(CONFIG_X86_OPTION_ROM_FILE)
23376 +endif
23377 +
23378 +quiet_cmd_ifdtool = IFDTOOL $@
23379 +cmd_ifdtool = $(IFDTOOL) -c -r $(CONFIG_ROM_SIZE) u-boot.tmp;
23380 +ifneq ($(CONFIG_HAVE_INTEL_ME),)
23381 +cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_ME_FLAGS) u-boot.tmp;
23382 +endif
23383 +cmd_ifdtool += $(IFDTOOL) $(IFDTOOL_FLAGS) u-boot.tmp;
23384 +cmd_ifdtool += mv u-boot.tmp $@
23385 +
23386 +u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin
23387 + $(call if_changed,ifdtool)
23388
23389 OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
23390 u-boot-x86-16bit.bin: u-boot FORCE
23391 @@ -999,15 +1015,22 @@
23392 #concatenated with u-boot binary. It is need by PowerPC SoC having
23393 #internal SRAM <= 512KB.
23394 MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
23395 - -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
23396 + -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage \
23397 + -A $(ARCH) -a $(CONFIG_SPL_TEXT_BASE)
23398
23399 spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
23400 $(call if_changed,mkimage)
23401
23402 +ifeq ($(ARCH),arm)
23403 +UBOOT_BINLOAD := u-boot.img
23404 +else
23405 +UBOOT_BINLOAD := u-boot.bin
23406 +endif
23407 +
23408 OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
23409 --gap-fill=0xff
23410
23411 -u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE
23412 +u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(UBOOT_BINLOAD) FORCE
23413 $(call if_changed,pad_cat)
23414
23415 # PPC4xx needs the SPL at the end of the image, since the reset vector
23416 diff -ruN u-boot-2015.01-rc3/README u-boot/README
23417 --- u-boot-2015.01-rc3/README 2014-12-08 22:35:08.000000000 +0100
23418 +++ u-boot/README 2015-01-01 17:34:31.985507645 +0100
23419 @@ -1773,6 +1773,15 @@
23420 regarding the non-volatile storage device. Define this to
23421 the eMMC device that fastboot should use to store the image.
23422
23423 + CONFIG_FASTBOOT_GPT_NAME
23424 + The fastboot "flash" command supports writing the downloaded
23425 + image to the Protective MBR and the Primary GUID Partition
23426 + Table. (Additionally, this downloaded image is post-processed
23427 + to generate and write the Backup GUID Partition Table.)
23428 + This occurs when the specified "partition name" on the
23429 + "fastboot flash" command line matches this value.
23430 + Default is GPT_ENTRY_NAME (currently "gpt") if undefined.
23431 +
23432 - Journaling Flash filesystem support:
23433 CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE,
23434 CONFIG_JFFS2_NAND_DEV
23435 diff -ruN u-boot-2015.01-rc3/scripts/binutils-version.sh u-boot/scripts/binutils-version.sh
23436 --- u-boot-2015.01-rc3/scripts/binutils-version.sh 2014-12-08 22:35:08.000000000 +0100
23437 +++ u-boot/scripts/binutils-version.sh 2015-01-01 17:34:32.877493022 +0100
23438 @@ -14,7 +14,9 @@
23439 exit 1
23440 fi
23441
23442 -MAJOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 1)
23443 -MINOR=$($gas --version | head -1 | awk '{print $NF}' | cut -d . -f 2)
23444 +version_string=$($gas --version | head -1 | sed -e 's/.*) *\([0-9.]*\).*/\1/' )
23445 +
23446 +MAJOR=$(echo $version_string | cut -d . -f 1)
23447 +MINOR=$(echo $version_string | cut -d . -f 2)
23448
23449 printf "%02d%02d\\n" $MAJOR $MINOR
23450 diff -ruN u-boot-2015.01-rc3/snapshot.commit u-boot/snapshot.commit
23451 --- u-boot-2015.01-rc3/snapshot.commit 2014-12-08 22:35:08.000000000 +0100
23452 +++ u-boot/snapshot.commit 2015-01-01 17:34:32.885492891 +0100
23453 @@ -1 +1 @@
23454 -32fdf0e4d82bdca5d64d86330e461e59685f9959 Mon, 8 Dec 2014 16:35:08 -0500
23455 +$Format:%H %cD$
23456 diff -ruN u-boot-2015.01-rc3/test/dm/cmd_dm.c u-boot/test/dm/cmd_dm.c
23457 --- u-boot-2015.01-rc3/test/dm/cmd_dm.c 2014-12-08 22:35:08.000000000 +0100
23458 +++ u-boot/test/dm/cmd_dm.c 2015-01-01 17:34:32.885492891 +0100
23459 @@ -16,17 +16,65 @@
23460 #include <dm/test.h>
23461 #include <dm/uclass-internal.h>
23462
23463 +static void show_devices(struct udevice *dev, int depth, int last_flag)
23464 +{
23465 + int i, is_last;
23466 + struct udevice *child;
23467 + char class_name[12];
23468 +
23469 + /* print the first 11 characters to not break the tree-format. */
23470 + strlcpy(class_name, dev->uclass->uc_drv->name, sizeof(class_name));
23471 + printf(" %-11s [ %c ] ", class_name,
23472 + dev->flags & DM_FLAG_ACTIVATED ? '+' : ' ');
23473 +
23474 + for (i = depth; i >= 0; i--) {
23475 + is_last = (last_flag >> i) & 1;
23476 + if (i) {
23477 + if (is_last)
23478 + printf(" ");
23479 + else
23480 + printf("| ");
23481 + } else {
23482 + if (is_last)
23483 + printf("`-- ");
23484 + else
23485 + printf("|-- ");
23486 + }
23487 + }
23488 +
23489 + printf("%s\n", dev->name);
23490 +
23491 + list_for_each_entry(child, &dev->child_head, sibling_node) {
23492 + is_last = list_is_last(&child->sibling_node, &dev->child_head);
23493 + show_devices(child, depth + 1, (last_flag << 1) | is_last);
23494 + }
23495 +}
23496 +
23497 +static int do_dm_dump_all(cmd_tbl_t *cmdtp, int flag, int argc,
23498 + char * const argv[])
23499 +{
23500 + struct udevice *root;
23501 +
23502 + root = dm_root();
23503 + if (root) {
23504 + printf(" Class Probed Name\n");
23505 + printf("----------------------------------------\n");
23506 + show_devices(root, -1, 0);
23507 + }
23508 +
23509 + return 0;
23510 +}
23511 +
23512 /**
23513 * dm_display_line() - Display information about a single device
23514 *
23515 * Displays a single line of information with an option prefix
23516 *
23517 * @dev: Device to display
23518 - * @buf: Prefix to display at the start of the line
23519 */
23520 -static void dm_display_line(struct udevice *dev, char *buf)
23521 +static void dm_display_line(struct udevice *dev)
23522 {
23523 - printf("%s- %c %s @ %08lx", buf,
23524 + printf("- %c %s @ %08lx",
23525 dev->flags & DM_FLAG_ACTIVATED ? '*' : ' ',
23526 dev->name, (ulong)map_to_sysmem(dev));
23527 if (dev->req_seq != -1)
23528 @@ -34,53 +82,6 @@
23529 puts("\n");
23530 }
23531
23532 -static int display_succ(struct udevice *in, char *buf)
23533 -{
23534 - int len;
23535 - int ip = 0;
23536 - char local[16];
23537 - struct udevice *pos, *n, *prev = NULL;
23538 -
23539 - dm_display_line(in, buf);
23540 -
23541 - if (list_empty(&in->child_head))
23542 - return 0;
23543 -
23544 - len = strlen(buf);
23545 - strncpy(local, buf, sizeof(local));
23546 - snprintf(local + len, 2, "|");
23547 - if (len && local[len - 1] == '`')
23548 - local[len - 1] = ' ';
23549 -
23550 - list_for_each_entry_safe(pos, n, &in->child_head, sibling_node) {
23551 - if (ip++)
23552 - display_succ(prev, local);
23553 - prev = pos;
23554 - }
23555 -
23556 - snprintf(local + len, 2, "`");
23557 - display_succ(prev, local);
23558 -
23559 - return 0;
23560 -}
23561 -
23562 -static int dm_dump(struct udevice *dev)
23563 -{
23564 - if (!dev)
23565 - return -EINVAL;
23566 - return display_succ(dev, "");
23567 -}
23568 -
23569 -static int do_dm_dump_all(cmd_tbl_t *cmdtp, int flag, int argc,
23570 - char * const argv[])
23571 -{
23572 - struct udevice *root;
23573 -
23574 - root = dm_root();
23575 - printf("ROOT %08lx\n", (ulong)map_to_sysmem(root));
23576 - return dm_dump(root);
23577 -}
23578 -
23579 static int do_dm_dump_uclass(cmd_tbl_t *cmdtp, int flag, int argc,
23580 char * const argv[])
23581 {
23582 @@ -99,7 +100,7 @@
23583 if (list_empty(&uc->dev_head))
23584 continue;
23585 list_for_each_entry(dev, &uc->dev_head, uclass_node) {
23586 - dm_display_line(dev, "");
23587 + dm_display_line(dev);
23588 }
23589 puts("\n");
23590 }
23591 diff -ruN u-boot-2015.01-rc3/test/dm/i2c.c u-boot/test/dm/i2c.c
23592 --- u-boot-2015.01-rc3/test/dm/i2c.c 1970-01-01 01:00:00.000000000 +0100
23593 +++ u-boot/test/dm/i2c.c 2015-01-01 17:34:32.885492891 +0100
23594 @@ -0,0 +1,216 @@
23595 +/*
23596 + * Copyright (C) 2013 Google, Inc
23597 + *
23598 + * SPDX-License-Identifier: GPL-2.0+
23599 + *
23600 + * Note: Test coverage does not include 10-bit addressing
23601 + */
23602 +
23603 +#include <common.h>
23604 +#include <dm.h>
23605 +#include <fdtdec.h>
23606 +#include <i2c.h>
23607 +#include <dm/device-internal.h>
23608 +#include <dm/test.h>
23609 +#include <dm/uclass-internal.h>
23610 +#include <dm/ut.h>
23611 +#include <dm/util.h>
23612 +#include <asm/state.h>
23613 +#include <asm/test.h>
23614 +
23615 +static const int busnum;
23616 +static const int chip = 0x2c;
23617 +
23618 +/* Test that we can find buses and chips */
23619 +static int dm_test_i2c_find(struct dm_test_state *dms)
23620 +{
23621 + struct udevice *bus, *dev;
23622 + const int no_chip = 0x10;
23623 +
23624 + ut_asserteq(-ENODEV, uclass_find_device_by_seq(UCLASS_I2C, busnum,
23625 + false, &bus));
23626 +
23627 + /*
23628 + * i2c_post_bind() will bind devices to chip selects. Check this then
23629 + * remove the emulation and the slave device.
23630 + */
23631 + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
23632 + ut_assertok(i2c_probe(bus, chip, 0, &dev));
23633 + ut_asserteq(-ENODEV, i2c_probe(bus, no_chip, 0, &dev));
23634 + ut_asserteq(-ENODEV, uclass_get_device_by_seq(UCLASS_I2C, 1, &bus));
23635 +
23636 + return 0;
23637 +}
23638 +DM_TEST(dm_test_i2c_find, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
23639 +
23640 +static int dm_test_i2c_read_write(struct dm_test_state *dms)
23641 +{
23642 + struct udevice *bus, *dev;
23643 + uint8_t buf[5];
23644 +
23645 + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
23646 + ut_assertok(i2c_get_chip(bus, chip, &dev));
23647 + ut_assertok(i2c_read(dev, 0, buf, 5));
23648 + ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
23649 + ut_assertok(i2c_write(dev, 2, (uint8_t *)"AB", 2));
23650 + ut_assertok(i2c_read(dev, 0, buf, 5));
23651 + ut_assertok(memcmp(buf, "\0\0AB\0", sizeof(buf)));
23652 +
23653 + return 0;
23654 +}
23655 +DM_TEST(dm_test_i2c_read_write, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
23656 +
23657 +static int dm_test_i2c_speed(struct dm_test_state *dms)
23658 +{
23659 + struct udevice *bus, *dev;
23660 + uint8_t buf[5];
23661 +
23662 + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
23663 + ut_assertok(i2c_get_chip(bus, chip, &dev));
23664 + ut_assertok(i2c_set_bus_speed(bus, 100000));
23665 + ut_assertok(i2c_read(dev, 0, buf, 5));
23666 + ut_assertok(i2c_set_bus_speed(bus, 400000));
23667 + ut_asserteq(400000, i2c_get_bus_speed(bus));
23668 + ut_assertok(i2c_read(dev, 0, buf, 5));
23669 + ut_asserteq(-EINVAL, i2c_write(dev, 0, buf, 5));
23670 +
23671 + return 0;
23672 +}
23673 +DM_TEST(dm_test_i2c_speed, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
23674 +
23675 +static int dm_test_i2c_offset_len(struct dm_test_state *dms)
23676 +{
23677 + struct udevice *bus, *dev;
23678 + uint8_t buf[5];
23679 +
23680 + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
23681 + ut_assertok(i2c_get_chip(bus, chip, &dev));
23682 + ut_assertok(i2c_set_chip_offset_len(dev, 1));
23683 + ut_assertok(i2c_read(dev, 0, buf, 5));
23684 +
23685 + /* This is not supported by the uclass */
23686 + ut_asserteq(-EINVAL, i2c_set_chip_offset_len(dev, 5));
23687 +
23688 + return 0;
23689 +}
23690 +DM_TEST(dm_test_i2c_offset_len, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
23691 +
23692 +static int dm_test_i2c_probe_empty(struct dm_test_state *dms)
23693 +{
23694 + struct udevice *bus, *dev;
23695 +
23696 + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
23697 + ut_assertok(i2c_probe(bus, SANDBOX_I2C_TEST_ADDR, 0, &dev));
23698 +
23699 + return 0;
23700 +}
23701 +DM_TEST(dm_test_i2c_probe_empty, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
23702 +
23703 +static int dm_test_i2c_bytewise(struct dm_test_state *dms)
23704 +{
23705 + struct udevice *bus, *dev;
23706 + struct udevice *eeprom;
23707 + uint8_t buf[5];
23708 +
23709 + ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus));
23710 + ut_assertok(i2c_get_chip(bus, chip, &dev));
23711 + ut_assertok(i2c_read(dev, 0, buf, 5));
23712 + ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
23713 +
23714 + /* Tell the EEPROM to only read/write one register at a time */
23715 + ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
23716 + ut_assertnonnull(eeprom);
23717 + sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_SINGLE_BYTE);
23718 +
23719 + /* Now we only get the first byte - the rest will be 0xff */
23720 + ut_assertok(i2c_read(dev, 0, buf, 5));
23721 + ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
23722 +
23723 + /* If we do a separate transaction for each byte, it works */
23724 + ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
23725 + ut_assertok(i2c_read(dev, 0, buf, 5));
23726 + ut_assertok(memcmp(buf, "\0\0\0\0\0", sizeof(buf)));
23727 +
23728 + /* This will only write A */
23729 + ut_assertok(i2c_set_chip_flags(dev, 0));
23730 + ut_assertok(i2c_write(dev, 2, (uint8_t *)"AB", 2));
23731 + ut_assertok(i2c_read(dev, 0, buf, 5));
23732 + ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
23733 +
23734 + /* Check that the B was ignored */
23735 + ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_RD_ADDRESS));
23736 + ut_assertok(i2c_read(dev, 0, buf, 5));
23737 + ut_assertok(memcmp(buf, "\0\0A\0\0\0", sizeof(buf)));
23738 +
23739 + /* Now write it again with the new flags, it should work */
23740 + ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS));
23741 + ut_assertok(i2c_write(dev, 2, (uint8_t *)"AB", 2));
23742 + ut_assertok(i2c_read(dev, 0, buf, 5));
23743 + ut_assertok(memcmp(buf, "\0\xff\xff\xff\xff", sizeof(buf)));
23744 +
23745 + ut_assertok(i2c_set_chip_flags(dev, DM_I2C_CHIP_WR_ADDRESS |
23746 + DM_I2C_CHIP_RD_ADDRESS));
23747 + ut_assertok(i2c_read(dev, 0, buf, 5));
23748 + ut_assertok(memcmp(buf, "\0\0AB\0\0", sizeof(buf)));
23749 +
23750 + /* Restore defaults */
23751 + sandbox_i2c_eeprom_set_test_mode(eeprom, SIE_TEST_MODE_NONE);
23752 + ut_assertok(i2c_set_chip_flags(dev, 0));
23753 +
23754 + return 0;
23755 +}
23756 +DM_TEST(dm_test_i2c_bytewise, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
23757 +
23758 +static int dm_test_i2c_offset(struct dm_test_state *dms)
23759 +{
23760 + struct udevice *eeprom;
23761 + struct udevice *dev;
23762 + uint8_t buf[5];
23763 +
23764 + ut_assertok(i2c_get_chip_for_busnum(busnum, chip, &dev));
23765 +
23766 + /* Do a transfer so we can find the emulator */
23767 + ut_assertok(i2c_read(dev, 0, buf, 5));
23768 + ut_assertok(uclass_first_device(UCLASS_I2C_EMUL, &eeprom));
23769 +
23770 + /* Offset length 0 */
23771 + sandbox_i2c_eeprom_set_offset_len(eeprom, 0);
23772 + ut_assertok(i2c_set_chip_offset_len(dev, 0));
23773 + ut_assertok(i2c_write(dev, 10 /* ignored */, (uint8_t *)"AB", 2));
23774 + ut_assertok(i2c_read(dev, 0, buf, 5));
23775 + ut_assertok(memcmp(buf, "AB\0\0\0\0", sizeof(buf)));
23776 +
23777 + /* Offset length 1 */
23778 + sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
23779 + ut_assertok(i2c_set_chip_offset_len(dev, 1));
23780 + ut_assertok(i2c_write(dev, 2, (uint8_t *)"AB", 2));
23781 + ut_assertok(i2c_read(dev, 0, buf, 5));
23782 + ut_assertok(memcmp(buf, "ABAB\0", sizeof(buf)));
23783 +
23784 + /* Offset length 2 */
23785 + sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
23786 + ut_assertok(i2c_set_chip_offset_len(dev, 2));
23787 + ut_assertok(i2c_write(dev, 0x210, (uint8_t *)"AB", 2));
23788 + ut_assertok(i2c_read(dev, 0x210, buf, 5));
23789 + ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
23790 +
23791 + /* Offset length 3 */
23792 + sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
23793 + ut_assertok(i2c_set_chip_offset_len(dev, 2));
23794 + ut_assertok(i2c_write(dev, 0x410, (uint8_t *)"AB", 2));
23795 + ut_assertok(i2c_read(dev, 0x410, buf, 5));
23796 + ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
23797 +
23798 + /* Offset length 4 */
23799 + sandbox_i2c_eeprom_set_offset_len(eeprom, 2);
23800 + ut_assertok(i2c_set_chip_offset_len(dev, 2));
23801 + ut_assertok(i2c_write(dev, 0x420, (uint8_t *)"AB", 2));
23802 + ut_assertok(i2c_read(dev, 0x420, buf, 5));
23803 + ut_assertok(memcmp(buf, "AB\0\0\0", sizeof(buf)));
23804 +
23805 + /* Restore defaults */
23806 + sandbox_i2c_eeprom_set_offset_len(eeprom, 1);
23807 +
23808 + return 0;
23809 +}
23810 +DM_TEST(dm_test_i2c_offset, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);
23811 diff -ruN u-boot-2015.01-rc3/test/dm/Makefile u-boot/test/dm/Makefile
23812 --- u-boot-2015.01-rc3/test/dm/Makefile 2014-12-08 22:35:08.000000000 +0100
23813 +++ u-boot/test/dm/Makefile 2015-01-01 17:34:32.885492891 +0100
23814 @@ -20,4 +20,5 @@
23815 obj-$(CONFIG_DM_GPIO) += gpio.o
23816 obj-$(CONFIG_DM_SPI) += spi.o
23817 obj-$(CONFIG_DM_SPI_FLASH) += sf.o
23818 +obj-$(CONFIG_DM_I2C) += i2c.o
23819 endif
23820 diff -ruN u-boot-2015.01-rc3/test/dm/test.dts u-boot/test/dm/test.dts
23821 --- u-boot-2015.01-rc3/test/dm/test.dts 2014-12-08 22:35:08.000000000 +0100
23822 +++ u-boot/test/dm/test.dts 2015-01-01 17:34:32.885492891 +0100
23823 @@ -93,6 +93,23 @@
23824 num-gpios = <10>;
23825 };
23826
23827 + i2c@0 {
23828 + #address-cells = <1>;
23829 + #size-cells = <0>;
23830 + reg = <0>;
23831 + compatible = "sandbox,i2c";
23832 + clock-frequency = <100000>;
23833 + eeprom@2c {
23834 + reg = <0x2c>;
23835 + compatible = "i2c-eeprom";
23836 + emul {
23837 + compatible = "sandbox,i2c-eeprom";
23838 + sandbox,filename = "i2c.bin";
23839 + sandbox,size = <256>;
23840 + };
23841 + };
23842 + };
23843 +
23844 spi@0 {
23845 #address-cells = <1>;
23846 #size-cells = <0>;
23847 diff -ruN u-boot-2015.01-rc3/test/ums/ums_gadget_test.sh u-boot/test/ums/ums_gadget_test.sh
23848 --- u-boot-2015.01-rc3/test/ums/ums_gadget_test.sh 2014-12-08 22:35:08.000000000 +0100
23849 +++ u-boot/test/ums/ums_gadget_test.sh 2015-01-01 17:34:32.885492891 +0100
23850 @@ -11,6 +11,7 @@
23851
23852 COLOUR_RED="\33[31m"
23853 COLOUR_GREEN="\33[32m"
23854 +COLOUR_ORANGE="\33[33m"
23855 COLOUR_DEFAULT="\33[0m"
23856
23857 DIR=./
23858 @@ -59,8 +60,15 @@
23859 fi
23860
23861 cp ./$1 $MNT_DIR
23862 - umount $MNT_DIR
23863
23864 + while true; do
23865 + umount $MNT_DIR > /dev/null 2>&1
23866 + if [ $? -eq 0 ]; then
23867 + break
23868 + fi
23869 + printf "$COLOUR_ORANGE\tSleeping to wait for umount...$COLOUR_DEFAULT\n"
23870 + sleep 1
23871 + done
23872
23873 echo -n "TX: "
23874 calculate_md5sum $1
23875 diff -ruN u-boot-2015.01-rc3/tools/buildman/README u-boot/tools/buildman/README
23876 --- u-boot-2015.01-rc3/tools/buildman/README 2014-12-08 22:35:08.000000000 +0100
23877 +++ u-boot/tools/buildman/README 2015-01-01 17:34:32.885492891 +0100
23878 @@ -42,7 +42,7 @@
23879 Buildman is a builder. It is not make, although it runs make. It does not
23880 produce any useful output on the terminal while building, except for
23881 progress information (except with -v, see below). All the output (errors,
23882 -warnings and binaries if you are ask for them) is stored in output
23883 +warnings and binaries if you ask for them) is stored in output
23884 directories, which you can look at while the build is progressing, or when
23885 it is finished.
23886
23887 @@ -121,7 +121,7 @@
23888 means to build all arm boards except nvidia, freescale and anything ending
23889 with 'ball'.
23890
23891 -It is convenient to use the -n option to see whaat will be built based on
23892 +It is convenient to use the -n option to see what will be built based on
23893 the subset given.
23894
23895 Buildman does not store intermediate object files. It optionally copies
23896 @@ -371,7 +371,7 @@
23897
23898
23899 To find out how the build went, ask for a summary with -s. You can do this
23900 -either before the build completes (presumably in another terminal) or or
23901 +either before the build completes (presumably in another terminal) or
23902 afterwards. Let's work through an example of how this is used:
23903
23904 $ ./tools/buildman/buildman -b lcd9b -s
23905 @@ -439,7 +439,7 @@
23906
23907 At commit 16, the error moves - you can see that the old error at line 120
23908 is fixed, but there is a new one at line 126. This is probably only because
23909 -we added some code and moved the broken line father down the file.
23910 +we added some code and moved the broken line further down the file.
23911
23912 If many boards have the same error, then -e will display the error only
23913 once. This makes the output as concise as possible. To see which boards have
23914 @@ -647,8 +647,8 @@
23915 board was built) and by 96 bytes for powerpc. This increase was offset in both
23916 cases by reductions in rodata and data/bss.
23917
23918 -Shown below the summary lines is the sizes for each board. Below each board
23919 -is the sizes for each function. This information starts with:
23920 +Shown below the summary lines are the sizes for each board. Below each board
23921 +are the sizes for each function. This information starts with:
23922
23923 add - number of functions added / removed
23924 grow - number of functions which grew / shrunk
23925 @@ -817,7 +817,7 @@
23926 This has mostly be written in my spare time as a response to my difficulties
23927 in testing large series of patches. Apart from tidying up there is quite a
23928 bit of scope for improvement. Things like better error diffs and easier
23929 -access to log files. Also it would be nice it buildman could 'hunt' for
23930 +access to log files. Also it would be nice if buildman could 'hunt' for
23931 problems, perhaps by building a few boards for each arch, or checking
23932 commits for changed files and building only boards which use those files.
23933
23934 diff -ruN u-boot-2015.01-rc3/tools/ifdtool.c u-boot/tools/ifdtool.c
23935 --- u-boot-2015.01-rc3/tools/ifdtool.c 2014-12-08 22:35:08.000000000 +0100
23936 +++ u-boot/tools/ifdtool.c 2015-01-01 17:34:32.893492759 +0100
23937 @@ -18,6 +18,7 @@
23938 #include <unistd.h>
23939 #include <sys/types.h>
23940 #include <sys/stat.h>
23941 +#include <libfdt.h>
23942 #include "ifdtool.h"
23943
23944 #undef DEBUG
23945 @@ -32,6 +33,18 @@
23946 #define FLREG_BASE(reg) ((reg & 0x00000fff) << 12);
23947 #define FLREG_LIMIT(reg) (((reg & 0x0fff0000) >> 4) | 0xfff);
23948
23949 +enum input_file_type_t {
23950 + IF_normal,
23951 + IF_fdt,
23952 + IF_uboot,
23953 +};
23954 +
23955 +struct input_file {
23956 + char *fname;
23957 + unsigned int addr;
23958 + enum input_file_type_t type;
23959 +};
23960 +
23961 /**
23962 * find_fd() - Find the flash description in the ROM image
23963 *
23964 @@ -54,7 +67,8 @@
23965 return NULL;
23966 }
23967
23968 - debug("Found Flash Descriptor signature at 0x%08x\n", i);
23969 + debug("Found Flash Descriptor signature at 0x%08lx\n",
23970 + (char *)ptr - image);
23971
23972 return (struct fdbar_t *)ptr;
23973 }
23974 @@ -464,6 +478,16 @@
23975 return ret;
23976 }
23977
23978 +static int perror_fname(const char *fmt, const char *fname)
23979 +{
23980 + char msg[strlen(fmt) + strlen(fname) + 1];
23981 +
23982 + sprintf(msg, fmt, fname);
23983 + perror(msg);
23984 +
23985 + return -1;
23986 +}
23987 +
23988 /**
23989 * write_image() - Write the image to a file
23990 *
23991 @@ -480,10 +504,10 @@
23992
23993 new_fd = open(filename, O_WRONLY | O_CREAT | O_TRUNC, S_IRUSR |
23994 S_IWUSR | S_IRGRP | S_IROTH);
23995 - if (write(new_fd, image, size) != size) {
23996 - perror("Error while writing");
23997 - return -1;
23998 - }
23999 + if (new_fd < 0)
24000 + return perror_fname("Could not open file '%s'", filename);
24001 + if (write(new_fd, image, size) != size)
24002 + return perror_fname("Could not write file '%s'", filename);
24003 close(new_fd);
24004
24005 return 0;
24006 @@ -585,14 +609,10 @@
24007 int fd = open(fname, O_RDONLY);
24008 struct stat buf;
24009
24010 - if (fd == -1) {
24011 - perror("Could not open file");
24012 - return -1;
24013 - }
24014 - if (fstat(fd, &buf) == -1) {
24015 - perror("Could not stat file");
24016 - return -1;
24017 - }
24018 + if (fd == -1)
24019 + return perror_fname("Could not open file '%s'", fname);
24020 + if (fstat(fd, &buf) == -1)
24021 + return perror_fname("Could not stat file '%s'", fname);
24022 *sizep = buf.st_size;
24023 debug("File %s is %d bytes\n", fname, *sizep);
24024
24025 @@ -686,7 +706,7 @@
24026 * 0xffffffff so use an address relative to that. For an
24027 * 8MB ROM the start address is 0xfff80000.
24028 * @write_fname: Filename to add to the image
24029 - * @return 0 if OK, -ve on error
24030 + * @return number of bytes written if OK, -ve on error
24031 */
24032 static int write_data(char *image, int size, unsigned int addr,
24033 const char *write_fname)
24034 @@ -698,7 +718,7 @@
24035 if (write_fd < 0)
24036 return write_fd;
24037
24038 - offset = addr + size;
24039 + offset = (uint32_t)(addr + size);
24040 debug("Writing %s to offset %#x\n", write_fname, offset);
24041
24042 if (offset < 0 || offset + write_size > size) {
24043 @@ -714,6 +734,68 @@
24044
24045 close(write_fd);
24046
24047 + return write_size;
24048 +}
24049 +
24050 +/**
24051 + * write_uboot() - Write U-Boot, device tree and microcode pointer
24052 + *
24053 + * This writes U-Boot into a place in the flash, followed by its device tree.
24054 + * The microcode pointer is written so that U-Boot can find the microcode in
24055 + * the device tree very early in boot.
24056 + *
24057 + * @image: Pointer to image
24058 + * @size: Size of image in bytes
24059 + * @uboot: Input file information for u-boot.bin
24060 + * @fdt: Input file information for u-boot.dtb
24061 + * @ucode_ptr: Address in U-Boot where the microcode pointer should be placed
24062 + * @return 0 if OK, -ve on error
24063 + */
24064 +static int write_uboot(char *image, int size, struct input_file *uboot,
24065 + struct input_file *fdt, unsigned int ucode_ptr)
24066 +{
24067 + const void *blob;
24068 + const char *data;
24069 + int uboot_size;
24070 + uint32_t *ptr;
24071 + int data_size;
24072 + int offset;
24073 + int node;
24074 + int ret;
24075 +
24076 + uboot_size = write_data(image, size, uboot->addr, uboot->fname);
24077 + if (uboot_size < 0)
24078 + return uboot_size;
24079 + fdt->addr = uboot->addr + uboot_size;
24080 + debug("U-Boot size %#x, FDT at %#x\n", uboot_size, fdt->addr);
24081 + ret = write_data(image, size, fdt->addr, fdt->fname);
24082 + if (ret < 0)
24083 + return ret;
24084 +
24085 + if (ucode_ptr) {
24086 + blob = (void *)image + (uint32_t)(fdt->addr + size);
24087 + debug("DTB at %lx\n", (char *)blob - image);
24088 + node = fdt_node_offset_by_compatible(blob, 0,
24089 + "intel,microcode");
24090 + if (node < 0) {
24091 + debug("No microcode found in FDT: %s\n",
24092 + fdt_strerror(node));
24093 + return -ENOENT;
24094 + }
24095 + data = fdt_getprop(blob, node, "data", &data_size);
24096 + if (!data) {
24097 + debug("No microcode data found in FDT: %s\n",
24098 + fdt_strerror(data_size));
24099 + return -ENOENT;
24100 + }
24101 + offset = ucode_ptr - uboot->addr;
24102 + ptr = (void *)image + offset;
24103 + ptr[0] = uboot->addr + (data - image);
24104 + ptr[1] = data_size;
24105 + debug("Wrote microcode pointer at %x: addr=%x, size=%x\n",
24106 + ucode_ptr, ptr[0], ptr[1]);
24107 + }
24108 +
24109 return 0;
24110 }
24111
24112 @@ -732,6 +814,7 @@
24113 " -x | --extract: extract intel fd modules\n"
24114 " -i | --inject <region>:<module> inject file <module> into region <region>\n"
24115 " -w | --write <addr>:<file> write file to appear at memory address <addr>\n"
24116 + " multiple files can be written simultaneously\n"
24117 " -s | --spifreq <20|33|50> set the SPI frequency\n"
24118 " -e | --em100 set SPI frequency to 20MHz and disable\n"
24119 " Dual Output Fast Read Support\n"
24120 @@ -778,17 +861,20 @@
24121 int mode_spifreq = 0, mode_em100 = 0, mode_locked = 0;
24122 int mode_unlocked = 0, mode_write = 0, mode_write_descriptor = 0;
24123 int create = 0;
24124 - char *region_type_string = NULL, *src_fname = NULL;
24125 - char *addr_str = NULL;
24126 + char *region_type_string = NULL, *inject_fname = NULL;
24127 + char *desc_fname = NULL, *addr_str = NULL;
24128 int region_type = -1, inputfreq = 0;
24129 enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ;
24130 - unsigned int addr = 0;
24131 + struct input_file input_file[WRITE_MAX], *ifile, *fdt = NULL;
24132 + unsigned char wr_idx, wr_num = 0;
24133 int rom_size = -1;
24134 bool write_it;
24135 char *filename;
24136 char *outfile = NULL;
24137 struct stat buf;
24138 int size = 0;
24139 + unsigned int ucode_ptr = 0;
24140 + bool have_uboot = false;
24141 int bios_fd;
24142 char *image;
24143 int ret;
24144 @@ -798,18 +884,21 @@
24145 {"descriptor", 1, NULL, 'D'},
24146 {"em100", 0, NULL, 'e'},
24147 {"extract", 0, NULL, 'x'},
24148 + {"fdt", 1, NULL, 'f'},
24149 {"inject", 1, NULL, 'i'},
24150 {"lock", 0, NULL, 'l'},
24151 + {"microcode", 1, NULL, 'm'},
24152 {"romsize", 1, NULL, 'r'},
24153 {"spifreq", 1, NULL, 's'},
24154 {"unlock", 0, NULL, 'u'},
24155 + {"uboot", 1, NULL, 'U'},
24156 {"write", 1, NULL, 'w'},
24157 {"version", 0, NULL, 'v'},
24158 {"help", 0, NULL, 'h'},
24159 {0, 0, 0, 0}
24160 };
24161
24162 - while ((opt = getopt_long(argc, argv, "cdD:ehi:lr:s:uvw:x?",
24163 + while ((opt = getopt_long(argc, argv, "cdD:ef:hi:lm:r:s:uU:vw:x?",
24164 long_options, &option_index)) != EOF) {
24165 switch (opt) {
24166 case 'c':
24167 @@ -820,14 +909,14 @@
24168 break;
24169 case 'D':
24170 mode_write_descriptor = 1;
24171 - src_fname = optarg;
24172 + desc_fname = optarg;
24173 break;
24174 case 'e':
24175 mode_em100 = 1;
24176 break;
24177 case 'i':
24178 if (get_two_words(optarg, &region_type_string,
24179 - &src_fname)) {
24180 + &inject_fname)) {
24181 print_usage(argv[0]);
24182 exit(EXIT_FAILURE);
24183 }
24184 @@ -852,6 +941,9 @@
24185 case 'l':
24186 mode_locked = 1;
24187 break;
24188 + case 'm':
24189 + ucode_ptr = strtoul(optarg, NULL, 0);
24190 + break;
24191 case 'r':
24192 rom_size = strtol(optarg, NULL, 0);
24193 debug("ROM size %d\n", rom_size);
24194 @@ -885,12 +977,29 @@
24195 exit(EXIT_SUCCESS);
24196 break;
24197 case 'w':
24198 + case 'U':
24199 + case 'f':
24200 + ifile = &input_file[wr_num];
24201 mode_write = 1;
24202 - if (get_two_words(optarg, &addr_str, &src_fname)) {
24203 - print_usage(argv[0]);
24204 - exit(EXIT_FAILURE);
24205 + if (wr_num < WRITE_MAX) {
24206 + if (get_two_words(optarg, &addr_str,
24207 + &ifile->fname)) {
24208 + print_usage(argv[0]);
24209 + exit(EXIT_FAILURE);
24210 + }
24211 + ifile->addr = strtol(optarg, NULL, 0);
24212 + ifile->type = opt == 'f' ? IF_fdt :
24213 + opt == 'U' ? IF_uboot : IF_normal;
24214 + if (ifile->type == IF_fdt)
24215 + fdt = ifile;
24216 + else if (ifile->type == IF_uboot)
24217 + have_uboot = true;
24218 + wr_num++;
24219 + } else {
24220 + fprintf(stderr,
24221 + "The number of files to write simultaneously exceeds the limitation (%d)\n",
24222 + WRITE_MAX);
24223 }
24224 - addr = strtol(optarg, NULL, 0);
24225 break;
24226 case 'x':
24227 mode_extract = 1;
24228 @@ -941,6 +1050,13 @@
24229 exit(EXIT_FAILURE);
24230 }
24231
24232 + if (have_uboot && !fdt) {
24233 + fprintf(stderr,
24234 + "You must supply a device tree file for U-Boot\n\n");
24235 + print_usage(argv[0]);
24236 + exit(EXIT_FAILURE);
24237 + }
24238 +
24239 filename = argv[optind];
24240 if (optind + 2 != argc)
24241 outfile = argv[optind + 1];
24242 @@ -997,13 +1113,27 @@
24243 }
24244
24245 if (mode_write_descriptor)
24246 - ret = write_data(image, size, -size, src_fname);
24247 + ret = write_data(image, size, -size, desc_fname);
24248
24249 if (mode_inject)
24250 - ret = inject_region(image, size, region_type, src_fname);
24251 + ret = inject_region(image, size, region_type, inject_fname);
24252
24253 - if (mode_write)
24254 - ret = write_data(image, size, addr, src_fname);
24255 + if (mode_write) {
24256 + for (wr_idx = 0; wr_idx < wr_num; wr_idx++) {
24257 + ifile = &input_file[wr_idx];
24258 + if (ifile->type == IF_fdt) {
24259 + continue;
24260 + } else if (ifile->type == IF_uboot) {
24261 + ret = write_uboot(image, size, ifile, fdt,
24262 + ucode_ptr);
24263 + } else {
24264 + ret = write_data(image, size, ifile->addr,
24265 + ifile->fname);
24266 + }
24267 + if (ret < 0)
24268 + break;
24269 + }
24270 + }
24271
24272 if (mode_spifreq)
24273 set_spi_frequency(image, size, spifreq);
24274 @@ -1035,5 +1165,5 @@
24275 free(image);
24276 close(bios_fd);
24277
24278 - return ret ? 1 : 0;
24279 + return ret < 0 ? 1 : 0;
24280 }
24281 diff -ruN u-boot-2015.01-rc3/tools/ifdtool.h u-boot/tools/ifdtool.h
24282 --- u-boot-2015.01-rc3/tools/ifdtool.h 2014-12-08 22:35:08.000000000 +0100
24283 +++ u-boot/tools/ifdtool.h 2015-01-01 17:34:32.893492759 +0100
24284 @@ -14,6 +14,8 @@
24285
24286 #define IFDTOOL_VERSION "1.1-U-Boot"
24287
24288 +#define WRITE_MAX 16
24289 +
24290 enum spi_frequency {
24291 SPI_FREQUENCY_20MHZ = 0,
24292 SPI_FREQUENCY_33MHZ = 1,
24293 diff -ruN u-boot-2015.01-rc3/tools/Makefile u-boot/tools/Makefile
24294 --- u-boot-2015.01-rc3/tools/Makefile 2014-12-08 22:35:08.000000000 +0100
24295 +++ u-boot/tools/Makefile 2015-01-01 17:34:32.885492891 +0100
24296 @@ -126,6 +126,7 @@
24297 hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl
24298 HOSTCFLAGS_mkexynosspl.o := -pedantic
24299
24300 +ifdtool-objs := $(LIBFDT_OBJS) ifdtool.o
24301 hostprogs-$(CONFIG_X86) += ifdtool
24302
24303 hostprogs-$(CONFIG_MX23) += mxsboot
24304 diff -ruN u-boot-2015.01-rc3/tools/microcode-tool u-boot/tools/microcode-tool
24305 --- u-boot-2015.01-rc3/tools/microcode-tool 1970-01-01 01:00:00.000000000 +0100
24306 +++ u-boot/tools/microcode-tool 2015-01-01 17:34:32.897492694 +0100
24307 @@ -0,0 +1,253 @@
24308 +#!/usr/bin/env python
24309 +#
24310 +# Copyright (c) 2014 Google, Inc
24311 +#
24312 +# SPDX-License-Identifier: GPL-2.0+
24313 +#
24314 +# Intel microcode update tool
24315 +
24316 +from optparse import OptionParser
24317 +import os
24318 +import re
24319 +import struct
24320 +import sys
24321 +
24322 +MICROCODE_DIR = 'arch/x86/dts/microcode'
24323 +
24324 +class Microcode:
24325 + """Holds information about the microcode for a particular model of CPU.
24326 +
24327 + Attributes:
24328 + name: Name of the CPU this microcode is for, including any version
24329 + information (e.g. 'm12206a7_00000029')
24330 + model: Model code string (this is cpuid(1).eax, e.g. '206a7')
24331 + words: List of hex words containing the microcode. The first 16 words
24332 + are the public header.
24333 + """
24334 + def __init__(self, name, data):
24335 + self.name = name
24336 + # Convert data into a list of hex words
24337 + self.words = []
24338 + for value in ''.join(data).split(','):
24339 + hexval = value.strip()
24340 + if hexval:
24341 + self.words.append(int(hexval, 0))
24342 +
24343 + # The model is in the 4rd hex word
24344 + self.model = '%x' % self.words[3]
24345 +
24346 +def ParseFile(fname):
24347 + """Parse a micrcode.dat file and return the component parts
24348 +
24349 + Args:
24350 + fname: Filename to parse
24351 + Returns:
24352 + 3-Tuple:
24353 + date: String containing date from the file's header
24354 + license_text: List of text lines for the license file
24355 + microcodes: List of Microcode objects from the file
24356 + """
24357 + re_date = re.compile('/\* *(.* [0-9]{4}) *\*/$')
24358 + re_license = re.compile('/[^-*+] *(.*)$')
24359 + re_name = re.compile('/\* *(.*)\.inc *\*/', re.IGNORECASE)
24360 + microcodes = {}
24361 + license_text = []
24362 + date = ''
24363 + data = []
24364 + name = None
24365 + with open(fname) as fd:
24366 + for line in fd:
24367 + line = line.rstrip()
24368 + m_date = re_date.match(line)
24369 + m_license = re_license.match(line)
24370 + m_name = re_name.match(line)
24371 + if m_name:
24372 + if name:
24373 + microcodes[name] = Microcode(name, data)
24374 + name = m_name.group(1).lower()
24375 + data = []
24376 + elif m_license:
24377 + license_text.append(m_license.group(1))
24378 + elif m_date:
24379 + date = m_date.group(1)
24380 + else:
24381 + data.append(line)
24382 + if name:
24383 + microcodes[name] = Microcode(name, data)
24384 + return date, license_text, microcodes
24385 +
24386 +def List(date, microcodes, model):
24387 + """List the available microcode chunks
24388 +
24389 + Args:
24390 + date: Date of the microcode file
24391 + microcodes: Dict of Microcode objects indexed by name
24392 + model: Model string to search for, or None
24393 + """
24394 + print 'Date: %s' % date
24395 + if model:
24396 + mcode_list, tried = FindMicrocode(microcodes, model.lower())
24397 + print 'Matching models %s:' % (', '.join(tried))
24398 + else:
24399 + print 'All models:'
24400 + mcode_list = [microcodes[m] for m in microcodes.keys()]
24401 + for mcode in mcode_list:
24402 + print '%-20s: model %s' % (mcode.name, mcode.model)
24403 +
24404 +def FindMicrocode(microcodes, model):
24405 + """Find all the microcode chunks which match the given model.
24406 +
24407 + This model is something like 306a9 (the value returned in eax from
24408 + cpuid(1) when running on Intel CPUs). But we allow a partial match,
24409 + omitting the last 1 or two characters to allow many families to have the
24410 + same microcode.
24411 +
24412 + If the model name is ambiguous we return a list of matches.
24413 +
24414 + Args:
24415 + microcodes: Dict of Microcode objects indexed by name
24416 + model: String containing model name to find
24417 + Returns:
24418 + Tuple:
24419 + List of matching Microcode objects
24420 + List of abbreviations we tried
24421 + """
24422 + # Allow a full name to be used
24423 + mcode = microcodes.get(model)
24424 + if mcode:
24425 + return [mcode], []
24426 +
24427 + tried = []
24428 + found = []
24429 + for i in range(3):
24430 + abbrev = model[:-i] if i else model
24431 + tried.append(abbrev)
24432 + for mcode in microcodes.values():
24433 + if mcode.model.startswith(abbrev):
24434 + found.append(mcode)
24435 + if found:
24436 + break
24437 + return found, tried
24438 +
24439 +def CreateFile(date, license_text, mcode, outfile):
24440 + """Create a microcode file in U-Boot's .dtsi format
24441 +
24442 + Args:
24443 + date: String containing date of original microcode file
24444 + license: List of text lines for the license file
24445 + mcode: Microcode object to write
24446 + outfile: Filename to write to ('-' for stdout)
24447 + """
24448 + out = '''/*%s
24449 + * ---
24450 + * This is a device tree fragment. Use #include to add these properties to a
24451 + * node.
24452 + *
24453 + * Date: %s
24454 + */
24455 +
24456 +compatible = "intel,microcode";
24457 +intel,header-version = <%d>;
24458 +intel,update-revision = <%#x>;
24459 +intel,date-code = <%#x>;
24460 +intel,processor-signature = <%#x>;
24461 +intel,checksum = <%#x>;
24462 +intel,loader-revision = <%d>;
24463 +intel,processor-flags = <%#x>;
24464 +
24465 +/* The first 48-bytes are the public header which repeats the above data */
24466 +data = <%s
24467 +\t>;'''
24468 + words = ''
24469 + for i in range(len(mcode.words)):
24470 + if not (i & 3):
24471 + words += '\n'
24472 + val = mcode.words[i]
24473 + # Change each word so it will be little-endian in the FDT
24474 + # This data is needed before RAM is available on some platforms so we
24475 + # cannot do an endianness swap on boot.
24476 + val = struct.unpack("<I", struct.pack(">I", val))[0]
24477 + words += '\t%#010x' % val
24478 +
24479 + # Take care to avoid adding a space before a tab
24480 + text = ''
24481 + for line in license_text:
24482 + if line[0] == '\t':
24483 + text += '\n *' + line
24484 + else:
24485 + text += '\n * ' + line
24486 + args = [text, date]
24487 + args += [mcode.words[i] for i in range(7)]
24488 + args.append(words)
24489 + if outfile == '-':
24490 + print out % tuple(args)
24491 + else:
24492 + if not outfile:
24493 + if not os.path.exists(MICROCODE_DIR):
24494 + print >> sys.stderr, "Creating directory '%s'" % MICROCODE_DIR
24495 + os.makedirs(MICROCODE_DIR)
24496 + outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi')
24497 + print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
24498 + mcode.name, outfile)
24499 + with open(outfile, 'w') as fd:
24500 + print >> fd, out % tuple(args)
24501 +
24502 +def MicrocodeTool():
24503 + """Run the microcode tool"""
24504 + commands = 'create,license,list'.split(',')
24505 + parser = OptionParser()
24506 + parser.add_option('-d', '--mcfile', type='string', action='store',
24507 + help='Name of microcode.dat file')
24508 + parser.add_option('-m', '--model', type='string', action='store',
24509 + help='Model name to extract')
24510 + parser.add_option('-o', '--outfile', type='string', action='store',
24511 + help='Filename to use for output (- for stdout), default is'
24512 + ' %s/<name>.dtsi' % MICROCODE_DIR)
24513 + parser.usage += """ command
24514 +
24515 + Process an Intel microcode file (use -h for help). Commands:
24516 +
24517 + create Create microcode .dtsi file for a model
24518 + list List available models in microcode file
24519 + license Print the license
24520 +
24521 + Typical usage:
24522 +
24523 + ./tools/microcode-tool -d microcode.dat -m 306a create
24524 +
24525 + This will find the appropriate file and write it to %s.""" % MICROCODE_DIR
24526 +
24527 + (options, args) = parser.parse_args()
24528 + if not args:
24529 + parser.error('Please specify a command')
24530 + cmd = args[0]
24531 + if cmd not in commands:
24532 + parser.error("Unknown command '%s'" % cmd)
24533 +
24534 + if not options.mcfile:
24535 + parser.error('You must specify a microcode file')
24536 + date, license_text, microcodes = ParseFile(options.mcfile)
24537 +
24538 + if cmd == 'list':
24539 + List(date, microcodes, options.model)
24540 + elif cmd == 'license':
24541 + print '\n'.join(license_text)
24542 + elif cmd == 'create':
24543 + if not options.model:
24544 + parser.error('You must specify a model to create')
24545 + model = options.model.lower()
24546 + mcode_list, tried = FindMicrocode(microcodes, model)
24547 + if not mcode_list:
24548 + parser.error("Unknown model '%s' (%s) - try 'list' to list" %
24549 + (model, ', '.join(tried)))
24550 + if len(mcode_list) > 1:
24551 + parser.error("Ambiguous model '%s' (%s) matched %s - try 'list' "
24552 + "to list or specify a particular file" %
24553 + (model, ', '.join(tried),
24554 + ', '.join([m.name for m in mcode_list])))
24555 + CreateFile(date, license_text, mcode_list[0], options.outfile)
24556 + else:
24557 + parser.error("Unknown command '%s'" % cmd)
24558 +
24559 +if __name__ == "__main__":
24560 + MicrocodeTool()
24561 diff -ruN u-boot-2015.01-rc3/tools/microcode-tool.py u-boot/tools/microcode-tool.py
24562 --- u-boot-2015.01-rc3/tools/microcode-tool.py 1970-01-01 01:00:00.000000000 +0100
24563 +++ u-boot/tools/microcode-tool.py 2015-01-01 17:34:32.897492694 +0100
24564 @@ -0,0 +1,253 @@
24565 +#!/usr/bin/env python
24566 +#
24567 +# Copyright (c) 2014 Google, Inc
24568 +#
24569 +# SPDX-License-Identifier: GPL-2.0+
24570 +#
24571 +# Intel microcode update tool
24572 +
24573 +from optparse import OptionParser
24574 +import os
24575 +import re
24576 +import struct
24577 +import sys
24578 +
24579 +MICROCODE_DIR = 'arch/x86/dts/microcode'
24580 +
24581 +class Microcode:
24582 + """Holds information about the microcode for a particular model of CPU.
24583 +
24584 + Attributes:
24585 + name: Name of the CPU this microcode is for, including any version
24586 + information (e.g. 'm12206a7_00000029')
24587 + model: Model code string (this is cpuid(1).eax, e.g. '206a7')
24588 + words: List of hex words containing the microcode. The first 16 words
24589 + are the public header.
24590 + """
24591 + def __init__(self, name, data):
24592 + self.name = name
24593 + # Convert data into a list of hex words
24594 + self.words = []
24595 + for value in ''.join(data).split(','):
24596 + hexval = value.strip()
24597 + if hexval:
24598 + self.words.append(int(hexval, 0))
24599 +
24600 + # The model is in the 4rd hex word
24601 + self.model = '%x' % self.words[3]
24602 +
24603 +def ParseFile(fname):
24604 + """Parse a micrcode.dat file and return the component parts
24605 +
24606 + Args:
24607 + fname: Filename to parse
24608 + Returns:
24609 + 3-Tuple:
24610 + date: String containing date from the file's header
24611 + license_text: List of text lines for the license file
24612 + microcodes: List of Microcode objects from the file
24613 + """
24614 + re_date = re.compile('/\* *(.* [0-9]{4}) *\*/$')
24615 + re_license = re.compile('/[^-*+] *(.*)$')
24616 + re_name = re.compile('/\* *(.*)\.inc *\*/', re.IGNORECASE)
24617 + microcodes = {}
24618 + license_text = []
24619 + date = ''
24620 + data = []
24621 + name = None
24622 + with open(fname) as fd:
24623 + for line in fd:
24624 + line = line.rstrip()
24625 + m_date = re_date.match(line)
24626 + m_license = re_license.match(line)
24627 + m_name = re_name.match(line)
24628 + if m_name:
24629 + if name:
24630 + microcodes[name] = Microcode(name, data)
24631 + name = m_name.group(1).lower()
24632 + data = []
24633 + elif m_license:
24634 + license_text.append(m_license.group(1))
24635 + elif m_date:
24636 + date = m_date.group(1)
24637 + else:
24638 + data.append(line)
24639 + if name:
24640 + microcodes[name] = Microcode(name, data)
24641 + return date, license_text, microcodes
24642 +
24643 +def List(date, microcodes, model):
24644 + """List the available microcode chunks
24645 +
24646 + Args:
24647 + date: Date of the microcode file
24648 + microcodes: Dict of Microcode objects indexed by name
24649 + model: Model string to search for, or None
24650 + """
24651 + print 'Date: %s' % date
24652 + if model:
24653 + mcode_list, tried = FindMicrocode(microcodes, model.lower())
24654 + print 'Matching models %s:' % (', '.join(tried))
24655 + else:
24656 + print 'All models:'
24657 + mcode_list = [microcodes[m] for m in microcodes.keys()]
24658 + for mcode in mcode_list:
24659 + print '%-20s: model %s' % (mcode.name, mcode.model)
24660 +
24661 +def FindMicrocode(microcodes, model):
24662 + """Find all the microcode chunks which match the given model.
24663 +
24664 + This model is something like 306a9 (the value returned in eax from
24665 + cpuid(1) when running on Intel CPUs). But we allow a partial match,
24666 + omitting the last 1 or two characters to allow many families to have the
24667 + same microcode.
24668 +
24669 + If the model name is ambiguous we return a list of matches.
24670 +
24671 + Args:
24672 + microcodes: Dict of Microcode objects indexed by name
24673 + model: String containing model name to find
24674 + Returns:
24675 + Tuple:
24676 + List of matching Microcode objects
24677 + List of abbreviations we tried
24678 + """
24679 + # Allow a full name to be used
24680 + mcode = microcodes.get(model)
24681 + if mcode:
24682 + return [mcode], []
24683 +
24684 + tried = []
24685 + found = []
24686 + for i in range(3):
24687 + abbrev = model[:-i] if i else model
24688 + tried.append(abbrev)
24689 + for mcode in microcodes.values():
24690 + if mcode.model.startswith(abbrev):
24691 + found.append(mcode)
24692 + if found:
24693 + break
24694 + return found, tried
24695 +
24696 +def CreateFile(date, license_text, mcode, outfile):
24697 + """Create a microcode file in U-Boot's .dtsi format
24698 +
24699 + Args:
24700 + date: String containing date of original microcode file
24701 + license: List of text lines for the license file
24702 + mcode: Microcode object to write
24703 + outfile: Filename to write to ('-' for stdout)
24704 + """
24705 + out = '''/*%s
24706 + * ---
24707 + * This is a device tree fragment. Use #include to add these properties to a
24708 + * node.
24709 + *
24710 + * Date: %s
24711 + */
24712 +
24713 +compatible = "intel,microcode";
24714 +intel,header-version = <%d>;
24715 +intel,update-revision = <%#x>;
24716 +intel,date-code = <%#x>;
24717 +intel,processor-signature = <%#x>;
24718 +intel,checksum = <%#x>;
24719 +intel,loader-revision = <%d>;
24720 +intel,processor-flags = <%#x>;
24721 +
24722 +/* The first 48-bytes are the public header which repeats the above data */
24723 +data = <%s
24724 +\t>;'''
24725 + words = ''
24726 + for i in range(len(mcode.words)):
24727 + if not (i & 3):
24728 + words += '\n'
24729 + val = mcode.words[i]
24730 + # Change each word so it will be little-endian in the FDT
24731 + # This data is needed before RAM is available on some platforms so we
24732 + # cannot do an endianness swap on boot.
24733 + val = struct.unpack("<I", struct.pack(">I", val))[0]
24734 + words += '\t%#010x' % val
24735 +
24736 + # Take care to avoid adding a space before a tab
24737 + text = ''
24738 + for line in license_text:
24739 + if line[0] == '\t':
24740 + text += '\n *' + line
24741 + else:
24742 + text += '\n * ' + line
24743 + args = [text, date]
24744 + args += [mcode.words[i] for i in range(7)]
24745 + args.append(words)
24746 + if outfile == '-':
24747 + print out % tuple(args)
24748 + else:
24749 + if not outfile:
24750 + if not os.path.exists(MICROCODE_DIR):
24751 + print >> sys.stderr, "Creating directory '%s'" % MICROCODE_DIR
24752 + os.makedirs(MICROCODE_DIR)
24753 + outfile = os.path.join(MICROCODE_DIR, mcode.name + '.dtsi')
24754 + print >> sys.stderr, "Writing microcode for '%s' to '%s'" % (
24755 + mcode.name, outfile)
24756 + with open(outfile, 'w') as fd:
24757 + print >> fd, out % tuple(args)
24758 +
24759 +def MicrocodeTool():
24760 + """Run the microcode tool"""
24761 + commands = 'create,license,list'.split(',')
24762 + parser = OptionParser()
24763 + parser.add_option('-d', '--mcfile', type='string', action='store',
24764 + help='Name of microcode.dat file')
24765 + parser.add_option('-m', '--model', type='string', action='store',
24766 + help='Model name to extract')
24767 + parser.add_option('-o', '--outfile', type='string', action='store',
24768 + help='Filename to use for output (- for stdout), default is'
24769 + ' %s/<name>.dtsi' % MICROCODE_DIR)
24770 + parser.usage += """ command
24771 +
24772 + Process an Intel microcode file (use -h for help). Commands:
24773 +
24774 + create Create microcode .dtsi file for a model
24775 + list List available models in microcode file
24776 + license Print the license
24777 +
24778 + Typical usage:
24779 +
24780 + ./tools/microcode-tool -d microcode.dat -m 306a create
24781 +
24782 + This will find the appropriate file and write it to %s.""" % MICROCODE_DIR
24783 +
24784 + (options, args) = parser.parse_args()
24785 + if not args:
24786 + parser.error('Please specify a command')
24787 + cmd = args[0]
24788 + if cmd not in commands:
24789 + parser.error("Unknown command '%s'" % cmd)
24790 +
24791 + if not options.mcfile:
24792 + parser.error('You must specify a microcode file')
24793 + date, license_text, microcodes = ParseFile(options.mcfile)
24794 +
24795 + if cmd == 'list':
24796 + List(date, microcodes, options.model)
24797 + elif cmd == 'license':
24798 + print '\n'.join(license_text)
24799 + elif cmd == 'create':
24800 + if not options.model:
24801 + parser.error('You must specify a model to create')
24802 + model = options.model.lower()
24803 + mcode_list, tried = FindMicrocode(microcodes, model)
24804 + if not mcode_list:
24805 + parser.error("Unknown model '%s' (%s) - try 'list' to list" %
24806 + (model, ', '.join(tried)))
24807 + if len(mcode_list) > 1:
24808 + parser.error("Ambiguous model '%s' (%s) matched %s - try 'list' "
24809 + "to list or specify a particular file" %
24810 + (model, ', '.join(tried),
24811 + ', '.join([m.name for m in mcode_list])))
24812 + CreateFile(date, license_text, mcode_list[0], options.outfile)
24813 + else:
24814 + parser.error("Unknown command '%s'" % cmd)
24815 +
24816 +if __name__ == "__main__":
24817 + MicrocodeTool()
24818 diff -ruN u-boot-2015.01-rc3/tools/pblimage.c u-boot/tools/pblimage.c
24819 --- u-boot-2015.01-rc3/tools/pblimage.c 2014-12-08 22:35:08.000000000 +0100
24820 +++ u-boot/tools/pblimage.c 2015-01-01 17:34:32.905492563 +0100
24821 @@ -1,5 +1,5 @@
24822 /*
24823 - * Copyright 2012 Freescale Semiconductor, Inc.
24824 + * Copyright 2012-2014 Freescale Semiconductor, Inc.
24825 *
24826 * SPDX-License-Identifier: GPL-2.0+
24827 */
24828 @@ -8,6 +8,10 @@
24829 #include "pblimage.h"
24830 #include "pbl_crc32.h"
24831
24832 +#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
24833 +#define PBL_ACS_CONT_CMD 0x81000000
24834 +#define PBL_ADDR_24BIT_MASK 0x00ffffff
24835 +
24836 /*
24837 * Initialize to an invalid value.
24838 */
24839 @@ -22,6 +26,13 @@
24840 static char *fname = "Unknown";
24841 static int lineno = -1;
24842 static struct pbl_header pblimage_header;
24843 +static int uboot_size;
24844 +static int arch_flag;
24845 +
24846 +static uint32_t pbl_cmd_initaddr;
24847 +static uint32_t pbi_crc_cmd1;
24848 +static uint32_t pbi_crc_cmd2;
24849 +static uint32_t pbl_end_cmd[4];
24850
24851 static union
24852 {
24853 @@ -38,20 +49,6 @@
24854 * start offset by subtracting the size of the u-boot image from the
24855 * top of the allowable 24-bit range.
24856 */
24857 -static void init_next_pbl_cmd(FILE *fp_uboot)
24858 -{
24859 - struct stat st;
24860 - int fd = fileno(fp_uboot);
24861 -
24862 - if (fstat(fd, &st) == -1) {
24863 - printf("Error: Could not determine u-boot image size. %s\n",
24864 - strerror(errno));
24865 - exit(EXIT_FAILURE);
24866 - }
24867 -
24868 - next_pbl_cmd = 0x82000000 - st.st_size;
24869 -}
24870 -
24871 static void generate_pbl_cmd(void)
24872 {
24873 uint32_t val = next_pbl_cmd;
24874 @@ -66,11 +63,15 @@
24875
24876 static void pbl_fget(size_t size, FILE *stream)
24877 {
24878 - unsigned char c;
24879 + unsigned char c = 0xff;
24880 int c_temp;
24881
24882 - while (size && (c_temp = fgetc(stream)) != EOF) {
24883 - c = (unsigned char)c_temp;
24884 + while (size) {
24885 + c_temp = fgetc(stream);
24886 + if (c_temp != EOF)
24887 + c = (unsigned char)c_temp;
24888 + else if ((c_temp == EOF) && (arch_flag == IH_ARCH_ARM))
24889 + c = 0xff;
24890 *pmem_buf++ = c;
24891 pbl_size++;
24892 size--;
24893 @@ -80,8 +81,8 @@
24894 /* load split u-boot with PBI command 81xxxxxx. */
24895 static void load_uboot(FILE *fp_uboot)
24896 {
24897 - init_next_pbl_cmd(fp_uboot);
24898 - while (next_pbl_cmd < 0x82000000) {
24899 + next_pbl_cmd = pbl_cmd_initaddr - uboot_size;
24900 + while (next_pbl_cmd < pbl_cmd_initaddr) {
24901 generate_pbl_cmd();
24902 pbl_fget(64, fp_uboot);
24903 }
24904 @@ -154,8 +155,6 @@
24905 /* write end command and crc command to memory. */
24906 static void add_end_cmd(void)
24907 {
24908 - uint32_t pbl_end_cmd[4] = {0x09138000, 0x00000000,
24909 - 0x091380c0, 0x00000000};
24910 uint32_t crc32_pbl;
24911 int i;
24912 unsigned char *p = (unsigned char *)&pbl_end_cmd;
24913 @@ -172,8 +171,8 @@
24914
24915 /* Add PBI CRC command. */
24916 *pmem_buf++ = 0x08;
24917 - *pmem_buf++ = 0x13;
24918 - *pmem_buf++ = 0x80;
24919 + *pmem_buf++ = pbi_crc_cmd1;
24920 + *pmem_buf++ = pbi_crc_cmd2;
24921 *pmem_buf++ = 0x40;
24922 pbl_size += 4;
24923
24924 @@ -184,17 +183,6 @@
24925 *pmem_buf++ = (crc32_pbl >> 8) & 0xff;
24926 *pmem_buf++ = (crc32_pbl) & 0xff;
24927 pbl_size += 4;
24928 -
24929 - if ((pbl_size % 16) != 0) {
24930 - for (i = 0; i < 8; i++) {
24931 - *pmem_buf++ = 0x0;
24932 - pbl_size++;
24933 - }
24934 - }
24935 - if ((pbl_size % 16 != 0)) {
24936 - printf("Error: Bad size of image file\n");
24937 - exit(EXIT_FAILURE);
24938 - }
24939 }
24940
24941 void pbl_load_uboot(int ifd, struct image_tool_params *params)
24942 @@ -268,12 +256,64 @@
24943 /*nothing need to do, pbl_load_uboot takes care of whole file. */
24944 }
24945
24946 +int pblimage_check_params(struct image_tool_params *params)
24947 +{
24948 + FILE *fp_uboot;
24949 + int fd;
24950 + struct stat st;
24951 +
24952 + if (!params)
24953 + return EXIT_FAILURE;
24954 +
24955 + fp_uboot = fopen(params->datafile, "r");
24956 + if (fp_uboot == NULL) {
24957 + printf("Error: %s open failed\n", params->datafile);
24958 + exit(EXIT_FAILURE);
24959 + }
24960 + fd = fileno(fp_uboot);
24961 +
24962 + if (fstat(fd, &st) == -1) {
24963 + printf("Error: Could not determine u-boot image size. %s\n",
24964 + strerror(errno));
24965 + exit(EXIT_FAILURE);
24966 + }
24967 +
24968 + /* For the variable size, we need to pad it to 64 byte boundary */
24969 + uboot_size = roundup(st.st_size, 64);
24970 +
24971 + if (params->arch == IH_ARCH_ARM) {
24972 + arch_flag = IH_ARCH_ARM;
24973 + pbi_crc_cmd1 = 0x61;
24974 + pbi_crc_cmd2 = 0;
24975 + pbl_cmd_initaddr = params->addr & PBL_ADDR_24BIT_MASK;
24976 + pbl_cmd_initaddr |= PBL_ACS_CONT_CMD;
24977 + pbl_cmd_initaddr |= uboot_size;
24978 + pbl_end_cmd[0] = 0x09610000;
24979 + pbl_end_cmd[1] = 0x00000000;
24980 + pbl_end_cmd[2] = 0x096100c0;
24981 + pbl_end_cmd[3] = 0x00000000;
24982 + } else if (params->arch == IH_ARCH_PPC) {
24983 + arch_flag = IH_ARCH_PPC;
24984 + pbi_crc_cmd1 = 0x13;
24985 + pbi_crc_cmd2 = 0x80;
24986 + pbl_cmd_initaddr = 0x82000000;
24987 + pbl_end_cmd[0] = 0x09138000;
24988 + pbl_end_cmd[1] = 0x00000000;
24989 + pbl_end_cmd[2] = 0x091380c0;
24990 + pbl_end_cmd[3] = 0x00000000;
24991 + }
24992 +
24993 + next_pbl_cmd = pbl_cmd_initaddr;
24994 + return 0;
24995 +};
24996 +
24997 /* pblimage parameters */
24998 static struct image_type_params pblimage_params = {
24999 .name = "Freescale PBL Boot Image support",
25000 .header_size = sizeof(struct pbl_header),
25001 .hdr = (void *)&pblimage_header,
25002 .check_image_type = pblimage_check_image_types,
25003 + .check_params = pblimage_check_params,
25004 .verify_header = pblimage_verify_header,
25005 .print_header = pblimage_print_header,
25006 .set_header = pblimage_set_header,
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