kernel: add missing config symbol for 3.18
[openwrt/openwrt.git] / package / boot / uboot-sunxi / patches / 001-u-boot-trunk-3e1ded1fff32d8af8cc5eec22c56797621ea6649.patch
1 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
2 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c 2014-12-08 22:35:08.000000000 +0100
3 +++ u-boot/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c 2015-01-01 17:34:32.005507318 +0100
4 @@ -209,6 +209,10 @@
5 .gate = SW_ONLY_GATE(0x0360, 20, 4),
6 };
7
8 +static struct bus_clk_data usb_otg_ahb_data = {
9 + .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
10 +};
11 +
12 static struct bus_clk_data sdio1_ahb_data = {
13 .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
14 };
15 @@ -331,6 +335,17 @@
16 */
17
18 /* KPM bus clocks */
19 +static struct bus_clock usb_otg_ahb_clk = {
20 + .clk = {
21 + .name = "usb_otg_ahb_clk",
22 + .parent = &kpm_ccu_clk.clk,
23 + .ops = &bus_clk_ops,
24 + .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
25 + },
26 + .freq_tbl = master_ahb_freq_tbl,
27 + .data = &usb_otg_ahb_data,
28 +};
29 +
30 static struct bus_clock sdio1_ahb_clk = {
31 .clk = {
32 .name = "sdio1_ahb_clk",
33 @@ -541,6 +556,7 @@
34 CLK_LK(bsc2),
35 CLK_LK(bsc3),
36 /* Bus clocks */
37 + CLK_LK(usb_otg_ahb),
38 CLK_LK(sdio1_ahb),
39 CLK_LK(sdio2_ahb),
40 CLK_LK(sdio3_ahb),
41 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c u-boot/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
42 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c 1970-01-01 01:00:00.000000000 +0100
43 +++ u-boot/arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c 2015-01-01 17:34:32.005507318 +0100
44 @@ -0,0 +1,27 @@
45 +/*
46 + * Copyright 2014 Broadcom Corporation.
47 + *
48 + * SPDX-License-Identifier: GPL-2.0+
49 + */
50 +
51 +#include <common.h>
52 +#include <asm/errno.h>
53 +#include <asm/arch/sysmap.h>
54 +#include "clk-core.h"
55 +
56 +/* Enable appropriate clocks for the USB OTG port */
57 +int clk_usb_otg_enable(void *base)
58 +{
59 + char *ahbstr;
60 +
61 + switch ((u32) base) {
62 + case HSOTG_BASE_ADDR:
63 + ahbstr = "usb_otg_ahb_clk";
64 + break;
65 + default:
66 + printf("%s: base 0x%p not found\n", __func__, base);
67 + return -EINVAL;
68 + }
69 +
70 + return clk_get_and_enable(ahbstr);
71 +}
72 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/Makefile u-boot/arch/arm/cpu/armv7/bcm281xx/Makefile
73 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/bcm281xx/Makefile 2014-12-08 22:35:08.000000000 +0100
74 +++ u-boot/arch/arm/cpu/armv7/bcm281xx/Makefile 2015-01-01 17:34:32.005507318 +0100
75 @@ -10,3 +10,4 @@
76 obj-y += clk-sdio.o
77 obj-y += clk-bsc.o
78 obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
79 +obj-y += clk-usb-otg.o
80 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/kona-common/clk-stubs.c u-boot/arch/arm/cpu/armv7/kona-common/clk-stubs.c
81 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/kona-common/clk-stubs.c 2014-12-08 22:35:08.000000000 +0100
82 +++ u-boot/arch/arm/cpu/armv7/kona-common/clk-stubs.c 2015-01-01 17:34:32.009507252 +0100
83 @@ -19,3 +19,8 @@
84 {
85 return 0;
86 }
87 +
88 +int __weak clk_usb_otg_enable(void *base)
89 +{
90 + return 0;
91 +}
92 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/cpu.c u-boot/arch/arm/cpu/armv7/ls102xa/cpu.c
93 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/cpu.c 2014-12-08 22:35:08.000000000 +0100
94 +++ u-boot/arch/arm/cpu/armv7/ls102xa/cpu.c 2015-01-01 17:34:32.009507252 +0100
95 @@ -12,6 +12,8 @@
96 #include <netdev.h>
97 #include <fsl_esdhc.h>
98
99 +#include "fsl_epu.h"
100 +
101 DECLARE_GLOBAL_DATA_PTR;
102
103 #if defined(CONFIG_DISPLAY_CPUINFO)
104 @@ -101,3 +103,35 @@
105
106 return 0;
107 }
108 +
109 +int arch_cpu_init(void)
110 +{
111 + void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
112 +
113 + /*
114 + * After wakeup from deep sleep, Clear EPU registers
115 + * as early as possible to prevent from possible issue.
116 + * It's also safe to clear at normal boot.
117 + */
118 + fsl_epu_clean(epu_base);
119 +
120 + return 0;
121 +}
122 +
123 +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
124 +/* Set the address at which the secondary core starts from.*/
125 +void smp_set_core_boot_addr(unsigned long addr, int corenr)
126 +{
127 + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
128 +
129 + out_be32(&gur->scratchrw[0], addr);
130 +}
131 +
132 +/* Release the secondary core from holdoff state and kick it */
133 +void smp_kick_all_cpus(void)
134 +{
135 + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
136 +
137 + out_be32(&gur->brrl, 0x2);
138 +}
139 +#endif
140 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fdt.c u-boot/arch/arm/cpu/armv7/ls102xa/fdt.c
141 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fdt.c 2014-12-08 22:35:08.000000000 +0100
142 +++ u-boot/arch/arm/cpu/armv7/ls102xa/fdt.c 2015-01-01 17:34:32.009507252 +0100
143 @@ -91,7 +91,7 @@
144 }
145
146 do_fixup_by_prop_u32(blob, "device_type", "soc",
147 - 4, "bus-frequency", busclk / 2, 1);
148 + 4, "bus-frequency", busclk, 1);
149
150 ft_fixup_enet_phy_connect_type(blob);
151
152 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.c u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
153 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.c 1970-01-01 01:00:00.000000000 +0100
154 +++ u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.c 2015-01-01 17:34:32.009507252 +0100
155 @@ -0,0 +1,57 @@
156 +/*
157 + * Copyright 2014 Freescale Semiconductor, Inc.
158 + *
159 + * SPDX-License-Identifier: GPL-2.0+
160 + */
161 +
162 +#include <common.h>
163 +#include <asm/io.h>
164 +
165 +#include "fsl_epu.h"
166 +
167 +/**
168 + * fsl_epu_clean - Clear EPU registers
169 + */
170 +void fsl_epu_clean(void *epu_base)
171 +{
172 + u32 offset;
173 +
174 + /* follow the exact sequence to clear the registers */
175 + /* Clear EPACRn */
176 + for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
177 + out_be32(epu_base + offset, 0);
178 +
179 + /* Clear EPEVTCRn */
180 + for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
181 + out_be32(epu_base + offset, 0);
182 +
183 + /* Clear EPGCR */
184 + out_be32(epu_base + EPGCR, 0);
185 +
186 + /* Clear EPSMCRn */
187 + for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
188 + out_be32(epu_base + offset, 0);
189 +
190 + /* Clear EPCCRn */
191 + for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
192 + out_be32(epu_base + offset, 0);
193 +
194 + /* Clear EPCMPRn */
195 + for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
196 + out_be32(epu_base + offset, 0);
197 +
198 + /* Clear EPCTRn */
199 + for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
200 + out_be32(epu_base + offset, 0);
201 +
202 + /* Clear EPIMCRn */
203 + for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
204 + out_be32(epu_base + offset, 0);
205 +
206 + /* Clear EPXTRIGCRn */
207 + out_be32(epu_base + EPXTRIGCR, 0);
208 +
209 + /* Clear EPECRn */
210 + for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
211 + out_be32(epu_base + offset, 0);
212 +}
213 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.h u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
214 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/fsl_epu.h 1970-01-01 01:00:00.000000000 +0100
215 +++ u-boot/arch/arm/cpu/armv7/ls102xa/fsl_epu.h 2015-01-01 17:34:32.009507252 +0100
216 @@ -0,0 +1,68 @@
217 +/*
218 + * Copyright 2014 Freescale Semiconductor, Inc.
219 + *
220 + * SPDX-License-Identifier: GPL-2.0+
221 + */
222 +
223 +#ifndef __FSL_EPU_H
224 +#define __FSL_EPU_H
225 +
226 +#include <asm/types.h>
227 +
228 +#define FSL_STRIDE_4B 4
229 +#define FSL_STRIDE_8B 8
230 +
231 +/* Block offsets */
232 +#define EPU_BLOCK_OFFSET 0x00000000
233 +
234 +/* EPGCR (Event Processor Global Control Register) */
235 +#define EPGCR 0x000
236 +
237 +/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
238 +#define EPEVTCR0 0x050
239 +#define EPEVTCR9 0x074
240 +#define EPEVTCR_STRIDE FSL_STRIDE_4B
241 +
242 +/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
243 +#define EPXTRIGCR 0x090
244 +
245 +/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
246 +#define EPIMCR0 0x100
247 +#define EPIMCR31 0x17C
248 +#define EPIMCR_STRIDE FSL_STRIDE_4B
249 +
250 +/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
251 +#define EPSMCR0 0x200
252 +#define EPSMCR15 0x278
253 +#define EPSMCR_STRIDE FSL_STRIDE_8B
254 +
255 +/* EPECR0-15 (Event Processor Event Control Registers) */
256 +#define EPECR0 0x300
257 +#define EPECR15 0x33C
258 +#define EPECR_STRIDE FSL_STRIDE_4B
259 +
260 +/* EPACR0-15 (Event Processor Action Control Registers) */
261 +#define EPACR0 0x400
262 +#define EPACR15 0x43C
263 +#define EPACR_STRIDE FSL_STRIDE_4B
264 +
265 +/* EPCCRi0-15 (Event Processor Counter Control Registers) */
266 +#define EPCCR0 0x800
267 +#define EPCCR15 0x83C
268 +#define EPCCR31 0x87C
269 +#define EPCCR_STRIDE FSL_STRIDE_4B
270 +
271 +/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
272 +#define EPCMPR0 0x900
273 +#define EPCMPR15 0x93C
274 +#define EPCMPR31 0x97C
275 +#define EPCMPR_STRIDE FSL_STRIDE_4B
276 +
277 +/* EPCTR0-31 (Event Processor Counter Register) */
278 +#define EPCTR0 0xA00
279 +#define EPCTR31 0xA7C
280 +#define EPCTR_STRIDE FSL_STRIDE_4B
281 +
282 +void fsl_epu_clean(void *epu_base);
283 +
284 +#endif
285 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/Makefile u-boot/arch/arm/cpu/armv7/ls102xa/Makefile
286 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/Makefile 2014-12-08 22:35:08.000000000 +0100
287 +++ u-boot/arch/arm/cpu/armv7/ls102xa/Makefile 2015-01-01 17:34:32.009507252 +0100
288 @@ -7,6 +7,8 @@
289 obj-y += cpu.o
290 obj-y += clock.o
291 obj-y += timer.o
292 +obj-y += fsl_epu.o
293
294 obj-$(CONFIG_OF_LIBFDT) += fdt.o
295 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
296 +obj-$(CONFIG_SPL) += spl.o
297 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/spl.c u-boot/arch/arm/cpu/armv7/ls102xa/spl.c
298 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/ls102xa/spl.c 1970-01-01 01:00:00.000000000 +0100
299 +++ u-boot/arch/arm/cpu/armv7/ls102xa/spl.c 2015-01-01 17:34:32.009507252 +0100
300 @@ -0,0 +1,33 @@
301 +/*
302 + * Copyright 2014 Freescale Semiconductor, Inc.
303 + *
304 + * SPDX-License-Identifier: GPL-2.0+
305 + */
306 +
307 +#include <common.h>
308 +#include <spl.h>
309 +
310 +u32 spl_boot_device(void)
311 +{
312 +#ifdef CONFIG_SPL_MMC_SUPPORT
313 + return BOOT_DEVICE_MMC1;
314 +#endif
315 + return BOOT_DEVICE_NAND;
316 +}
317 +
318 +u32 spl_boot_mode(void)
319 +{
320 + switch (spl_boot_device()) {
321 + case BOOT_DEVICE_MMC1:
322 +#ifdef CONFIG_SPL_FAT_SUPPORT
323 + return MMCSD_MODE_FAT;
324 +#else
325 + return MMCSD_MODE_RAW;
326 +#endif
327 + case BOOT_DEVICE_NAND:
328 + return 0;
329 + default:
330 + puts("spl: error: unsupported device\n");
331 + hang();
332 + }
333 +}
334 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/Makefile u-boot/arch/arm/cpu/armv7/Makefile
335 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/Makefile 2014-12-08 22:35:08.000000000 +0100
336 +++ u-boot/arch/arm/cpu/armv7/Makefile 2015-01-01 17:34:32.001507383 +0100
337 @@ -56,6 +56,7 @@
338 obj-$(CONFIG_RMOBILE) += rmobile/
339 obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
340 obj-$(CONFIG_SOCFPGA) += socfpga/
341 +obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
342 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
343 obj-$(CONFIG_TEGRA20) += tegra20/
344 obj-$(CONFIG_U8500) += u8500/
345 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/mx6/clock.c u-boot/arch/arm/cpu/armv7/mx6/clock.c
346 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/mx6/clock.c 2014-12-08 22:35:08.000000000 +0100
347 +++ u-boot/arch/arm/cpu/armv7/mx6/clock.c 2015-01-01 17:34:32.009507252 +0100
348 @@ -443,7 +443,7 @@
349 struct anatop_regs __iomem *anatop =
350 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
351
352 - if (freq < ENET_25MHz || freq > ENET_125MHz)
353 + if (freq < ENET_25MHZ || freq > ENET_125MHZ)
354 return -EINVAL;
355
356 reg = readl(&anatop->pll_enet);
357 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/nonsec_virt.S u-boot/arch/arm/cpu/armv7/nonsec_virt.S
358 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/nonsec_virt.S 2014-12-08 22:35:08.000000000 +0100
359 +++ u-boot/arch/arm/cpu/armv7/nonsec_virt.S 2015-01-01 17:34:32.013507186 +0100
360 @@ -169,11 +169,11 @@
361 * we do this here instead.
362 * But first check if we have the generic timer.
363 */
364 -#ifdef CONFIG_SYS_CLK_FREQ
365 +#ifdef CONFIG_TIMER_CLK_FREQ
366 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
367 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits
368 cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT)
369 - ldreq r1, =CONFIG_SYS_CLK_FREQ
370 + ldreq r1, =CONFIG_TIMER_CLK_FREQ
371 mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ
372 #endif
373
374 @@ -191,6 +191,9 @@
375 wfi
376 ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address
377 ldr r1, [r1]
378 +#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN
379 + rev r1, r1
380 +#endif
381 cmp r0, r1 @ make sure we dont execute this code
382 beq smp_waitloop @ again (due to a spurious wakeup)
383 mov r0, r1
384 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/freeze_controller.c u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c
385 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/freeze_controller.c 2014-12-08 22:35:08.000000000 +0100
386 +++ u-boot/arch/arm/cpu/armv7/socfpga/freeze_controller.c 2015-01-01 17:34:32.021507054 +0100
387 @@ -38,8 +38,7 @@
388 /* Freeze channel 0 to 2 */
389 for (channel_id = 0; channel_id <= 2; channel_id++) {
390 ioctrl_reg_offset = (u32)(
391 - &freeze_controller_base->vioctrl +
392 - (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
393 + &freeze_controller_base->vioctrl + channel_id);
394
395 /*
396 * Assert active low enrnsl, plniotri
397 @@ -120,8 +119,7 @@
398 /* Thaw channel 0 to 2 */
399 for (channel_id = 0; channel_id <= 2; channel_id++) {
400 ioctrl_reg_offset
401 - = (u32)(&freeze_controller_base->vioctrl
402 - + (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
403 + = (u32)(&freeze_controller_base->vioctrl + channel_id);
404
405 /*
406 * Assert active low bhniotri signal and
407 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/reset_manager.c u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c
408 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/socfpga/reset_manager.c 2014-12-08 22:35:08.000000000 +0100
409 +++ u-boot/arch/arm/cpu/armv7/socfpga/reset_manager.c 2015-01-01 17:34:32.021507054 +0100
410 @@ -110,6 +110,6 @@
411 {
412 const void *reset = &reset_manager_base->per_mod_reset;
413
414 - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM0_LSB);
415 - clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SPIM1_LSB);
416 + clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
417 + (1 << RSTMGR_PERMODRST_SPIM1_LSB));
418 }
419 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/clock.c u-boot/arch/arm/cpu/armv7/stv0991/clock.c
420 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/clock.c 1970-01-01 01:00:00.000000000 +0100
421 +++ u-boot/arch/arm/cpu/armv7/stv0991/clock.c 2015-01-01 17:34:32.025506990 +0100
422 @@ -0,0 +1,41 @@
423 +/*
424 + * (C) Copyright 2014
425 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
426 + *
427 + * SPDX-License-Identifier: GPL-2.0+
428 + */
429 +
430 +#include <asm/io.h>
431 +#include <asm/arch/hardware.h>
432 +#include <asm/arch/stv0991_cgu.h>
433 +#include<asm/arch/stv0991_periph.h>
434 +
435 +static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
436 + (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
437 +
438 +void enable_pll1(void)
439 +{
440 + /* pll1 already configured for 1000Mhz, just need to enable it */
441 + writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01),
442 + &stv0991_cgu_regs->pll1_ctrl);
443 +}
444 +
445 +void clock_setup(int peripheral)
446 +{
447 + switch (peripheral) {
448 + case UART_CLOCK_CFG:
449 + writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq);
450 + break;
451 + case ETH_CLOCK_CFG:
452 + enable_pll1();
453 + writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq);
454 +
455 + /* Clock selection for ethernet tx_clk & rx_clk*/
456 + writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK)
457 + | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl);
458 +
459 + break;
460 + default:
461 + break;
462 + }
463 +}
464 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/lowlevel.S u-boot/arch/arm/cpu/armv7/stv0991/lowlevel.S
465 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/lowlevel.S 1970-01-01 01:00:00.000000000 +0100
466 +++ u-boot/arch/arm/cpu/armv7/stv0991/lowlevel.S 2015-01-01 17:34:32.025506990 +0100
467 @@ -0,0 +1,12 @@
468 +/*
469 + * (C) Copyright 2014 stmicroelectronics
470 + *
471 + * SPDX-License-Identifier: GPL-2.0+
472 + */
473 +
474 +#include <config.h>
475 +#include <linux/linkage.h>
476 +
477 +ENTRY(lowlevel_init)
478 + mov pc, lr
479 +ENDPROC(lowlevel_init)
480 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/Makefile u-boot/arch/arm/cpu/armv7/stv0991/Makefile
481 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/Makefile 1970-01-01 01:00:00.000000000 +0100
482 +++ u-boot/arch/arm/cpu/armv7/stv0991/Makefile 2015-01-01 17:34:32.025506990 +0100
483 @@ -0,0 +1,9 @@
484 +#
485 +# (C) Copyright 2014
486 +# Vikas Manocha, ST Microelectronics, vikas.manocha@stcom
487 +#
488 +# SPDX-License-Identifier: GPL-2.0+
489 +#
490 +
491 +obj-y := timer.o clock.o pinmux.o reset.o
492 +obj-y += lowlevel.o
493 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/pinmux.c u-boot/arch/arm/cpu/armv7/stv0991/pinmux.c
494 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/pinmux.c 1970-01-01 01:00:00.000000000 +0100
495 +++ u-boot/arch/arm/cpu/armv7/stv0991/pinmux.c 2015-01-01 17:34:32.025506990 +0100
496 @@ -0,0 +1,62 @@
497 +/*
498 + * (C) Copyright 2014
499 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
500 + *
501 + * SPDX-License-Identifier: GPL-2.0+
502 + */
503 +
504 +#include <asm/io.h>
505 +#include <asm/arch/stv0991_creg.h>
506 +#include <asm/arch/stv0991_periph.h>
507 +#include <asm/arch/hardware.h>
508 +
509 +static struct stv0991_creg *const stv0991_creg = \
510 + (struct stv0991_creg *)CREG_BASE_ADDR;
511 +
512 +int stv0991_pinmux_config(int peripheral)
513 +{
514 + switch (peripheral) {
515 + case UART_GPIOC_30_31:
516 + /* SSDA/SSCL pad muxing to UART Rx/Dx */
517 + writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) |
518 + CFG_GPIOC_31_UART_RX,
519 + &stv0991_creg->mux12);
520 + writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) |
521 + CFG_GPIOC_30_UART_TX,
522 + &stv0991_creg->mux12);
523 + /* SSDA/SSCL pad config to push pull*/
524 + writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) |
525 + CFG_GPIOC_31_MODE_PP,
526 + &stv0991_creg->cfg_pad6);
527 + writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) |
528 + CFG_GPIOC_30_MODE_HIGH,
529 + &stv0991_creg->cfg_pad6);
530 + break;
531 + case UART_GPIOB_16_17:
532 + /* ethernet rx_6/7 to UART Rx/Dx */
533 + writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) |
534 + CFG_GPIOB_17_UART_RX,
535 + &stv0991_creg->mux7);
536 + writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) |
537 + CFG_GPIOB_16_UART_TX,
538 + &stv0991_creg->mux7);
539 + break;
540 + case ETH_GPIOB_10_31_C_0_4:
541 + writel(readl(&stv0991_creg->mux6) & 0x000000FF,
542 + &stv0991_creg->mux6);
543 + writel(0x00000000, &stv0991_creg->mux7);
544 + writel(0x00000000, &stv0991_creg->mux8);
545 + writel(readl(&stv0991_creg->mux9) & 0xFFF00000,
546 + &stv0991_creg->mux9);
547 + /* Ethernet Voltage configuration to 1.8V*/
548 + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
549 + ETH_VDD_CFG, &stv0991_creg->vdd_pad1);
550 + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) |
551 + ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1);
552 +
553 + break;
554 + default:
555 + break;
556 + }
557 + return 0;
558 +}
559 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/reset.c u-boot/arch/arm/cpu/armv7/stv0991/reset.c
560 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/reset.c 1970-01-01 01:00:00.000000000 +0100
561 +++ u-boot/arch/arm/cpu/armv7/stv0991/reset.c 2015-01-01 17:34:32.025506990 +0100
562 @@ -0,0 +1,26 @@
563 +/*
564 + * (C) Copyright 2014
565 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
566 + *
567 + * SPDX-License-Identifier: GPL-2.0+
568 + */
569 +
570 +#include <common.h>
571 +#include <asm/io.h>
572 +#include <asm/arch/stv0991_wdru.h>
573 +void reset_cpu(ulong ignored)
574 +{
575 + puts("System is going to reboot ...\n");
576 + /*
577 + * This 1 second delay will allow the above message
578 + * to be printed before reset
579 + */
580 + udelay((1000 * 1000));
581 +
582 + /* Setting bit 1 of the WDRU unit will reset the SoC */
583 + writel(WDRU_RST_SYS, &stv0991_wd_ru_ptr->wdru_ctrl1);
584 +
585 + /* system will restart */
586 + while (1)
587 + ;
588 +}
589 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/timer.c u-boot/arch/arm/cpu/armv7/stv0991/timer.c
590 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/stv0991/timer.c 1970-01-01 01:00:00.000000000 +0100
591 +++ u-boot/arch/arm/cpu/armv7/stv0991/timer.c 2015-01-01 17:34:32.025506990 +0100
592 @@ -0,0 +1,114 @@
593 +/*
594 + * (C) Copyright 2014
595 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
596 + *
597 + * SPDX-License-Identifier: GPL-2.0+
598 + */
599 +
600 +#include <common.h>
601 +#include <asm/io.h>
602 +#include <asm/arch-stv0991/hardware.h>
603 +#include <asm/arch-stv0991/stv0991_cgu.h>
604 +#include <asm/arch-stv0991/stv0991_gpt.h>
605 +
606 +static struct stv0991_cgu_regs *const stv0991_cgu_regs = \
607 + (struct stv0991_cgu_regs *) (CGU_BASE_ADDR);
608 +
609 +#define READ_TIMER() (readl(&gpt1_regs_ptr->cnt) & GPT_FREE_RUNNING)
610 +#define GPT_RESOLUTION (CONFIG_STV0991_HZ_CLOCK / CONFIG_STV0991_HZ)
611 +
612 +DECLARE_GLOBAL_DATA_PTR;
613 +
614 +#define timestamp gd->arch.tbl
615 +#define lastdec gd->arch.lastinc
616 +
617 +int timer_init(void)
618 +{
619 + /* Timer1 clock configuration */
620 + writel(TIMER1_CLK_CFG, &stv0991_cgu_regs->tim_freq);
621 + writel(readl(&stv0991_cgu_regs->cgu_enable_2) |
622 + TIMER1_CLK_EN, &stv0991_cgu_regs->cgu_enable_2);
623 +
624 + /* Stop the timer */
625 + writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1);
626 + writel(GPT_PRESCALER_128, &gpt1_regs_ptr->psc);
627 + /* Configure timer for auto-reload */
628 + writel(readl(&gpt1_regs_ptr->cr1) | GPT_MODE_AUTO_RELOAD,
629 + &gpt1_regs_ptr->cr1);
630 +
631 + /* load value for free running */
632 + writel(GPT_FREE_RUNNING, &gpt1_regs_ptr->arr);
633 +
634 + /* start timer */
635 + writel(readl(&gpt1_regs_ptr->cr1) | GPT_CR1_CEN,
636 + &gpt1_regs_ptr->cr1);
637 +
638 + /* Reset the timer */
639 + lastdec = READ_TIMER();
640 + timestamp = 0;
641 +
642 + return 0;
643 +}
644 +
645 +/*
646 + * timer without interrupts
647 + */
648 +ulong get_timer(ulong base)
649 +{
650 + return (get_timer_masked() / GPT_RESOLUTION) - base;
651 +}
652 +
653 +void __udelay(unsigned long usec)
654 +{
655 + ulong tmo;
656 + ulong start = get_timer_masked();
657 + ulong tenudelcnt = CONFIG_STV0991_HZ_CLOCK / (1000 * 100);
658 + ulong rndoff;
659 +
660 + rndoff = (usec % 10) ? 1 : 0;
661 +
662 + /* tenudelcnt timer tick gives 10 microsecconds delay */
663 + tmo = ((usec / 10) + rndoff) * tenudelcnt;
664 +
665 + while ((ulong) (get_timer_masked() - start) < tmo)
666 + ;
667 +}
668 +
669 +ulong get_timer_masked(void)
670 +{
671 + ulong now = READ_TIMER();
672 +
673 + if (now >= lastdec) {
674 + /* normal mode */
675 + timestamp += now - lastdec;
676 + } else {
677 + /* we have an overflow ... */
678 + timestamp += now + GPT_FREE_RUNNING - lastdec;
679 + }
680 + lastdec = now;
681 +
682 + return timestamp;
683 +}
684 +
685 +void udelay_masked(unsigned long usec)
686 +{
687 + return udelay(usec);
688 +}
689 +
690 +/*
691 + * This function is derived from PowerPC code (read timebase as long long).
692 + * On ARM it just returns the timer value.
693 + */
694 +unsigned long long get_ticks(void)
695 +{
696 + return get_timer(0);
697 +}
698 +
699 +/*
700 + * This function is derived from PowerPC code (timebase clock frequency).
701 + * On ARM it returns the number of timer ticks per second.
702 + */
703 +ulong get_tbclk(void)
704 +{
705 + return CONFIG_STV0991_HZ;
706 +}
707 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/tegra124/Kconfig u-boot/arch/arm/cpu/armv7/tegra124/Kconfig
708 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/tegra124/Kconfig 2014-12-08 22:35:08.000000000 +0100
709 +++ u-boot/arch/arm/cpu/armv7/tegra124/Kconfig 2015-01-01 17:34:32.025506990 +0100
710 @@ -6,6 +6,15 @@
711 config TARGET_JETSON_TK1
712 bool "NVIDIA Tegra124 Jetson TK1 board"
713
714 +config TARGET_NYAN_BIG
715 + bool "Google/NVIDIA Nyan-big Chrombook"
716 + help
717 + Nyan Big is a Tegra124 clamshell board that is very similar
718 + to venice2, but it has a different panel, the sdcard CD and WP
719 + sense are flipped, and it has a different revision of the AS3722
720 + PMIC. The retail name is the Acer Chromebook 13 CB5-311-T7NN
721 + (13.3-inch HD, NVIDIA Tegra K1, 2GB).
722 +
723 config TARGET_VENICE2
724 bool "NVIDIA Tegra124 Venice2"
725
726 @@ -15,6 +24,7 @@
727 default "tegra124"
728
729 source "board/nvidia/jetson-tk1/Kconfig"
730 +source "board/nvidia/nyan-big/Kconfig"
731 source "board/nvidia/venice2/Kconfig"
732
733 endif
734 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/uniphier/init_page_table.c u-boot/arch/arm/cpu/armv7/uniphier/init_page_table.c
735 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/uniphier/init_page_table.c 2014-12-08 22:35:08.000000000 +0100
736 +++ u-boot/arch/arm/cpu/armv7/uniphier/init_page_table.c 2015-01-01 17:34:32.029506924 +0100
737 @@ -17,11 +17,7 @@
738 #define REG DEVICE /* IO Register: Device */
739 #define DDR DEVICE /* DDR SDRAM: Device */
740
741 -#ifdef CONFIG_SPL_BUILD
742 #define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SPL_TEXT_BASE) >> 20))
743 -#else
744 -#define IS_SPL_TEXT_AREA(x) ((x) == ((CONFIG_SYS_TEXT_BASE) >> 20))
745 -#endif
746
747 #define IS_INIT_STACK_AREA(x) ((x) == ((CONFIG_SYS_INIT_SP_ADDR) >> 20))
748
749 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/armv7/vf610/generic.c u-boot/arch/arm/cpu/armv7/vf610/generic.c
750 --- u-boot-2015.01-rc3/arch/arm/cpu/armv7/vf610/generic.c 2014-12-08 22:35:08.000000000 +0100
751 +++ u-boot/arch/arm/cpu/armv7/vf610/generic.c 2015-01-01 17:34:32.029506924 +0100
752 @@ -265,20 +265,21 @@
753
754 cause = readl(&src_regs->srsr);
755 writel(cause, &src_regs->srsr);
756 - cause &= 0xff;
757
758 - switch (cause) {
759 - case 0x08:
760 - return "WDOG";
761 - case 0x20:
762 + if (cause & SRC_SRSR_POR_RST)
763 + return "POWER ON RESET";
764 + else if (cause & SRC_SRSR_WDOG_A5)
765 + return "WDOG A5";
766 + else if (cause & SRC_SRSR_WDOG_M4)
767 + return "WDOG M4";
768 + else if (cause & SRC_SRSR_JTAG_RST)
769 return "JTAG HIGH-Z";
770 - case 0x80:
771 + else if (cause & SRC_SRSR_SW_RST)
772 + return "SW RESET";
773 + else if (cause & SRC_SRSR_RESETB)
774 return "EXTERNAL RESET";
775 - case 0xfd:
776 - return "POR";
777 - default:
778 + else
779 return "unknown reset";
780 - }
781 }
782
783 int print_cpuinfo(void)
784 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/tegra20-common/pmu.c u-boot/arch/arm/cpu/tegra20-common/pmu.c
785 --- u-boot-2015.01-rc3/arch/arm/cpu/tegra20-common/pmu.c 2014-12-08 22:35:08.000000000 +0100
786 +++ u-boot/arch/arm/cpu/tegra20-common/pmu.c 2015-01-01 17:34:32.037506793 +0100
787 @@ -6,6 +6,7 @@
788 */
789
790 #include <common.h>
791 +#include <i2c.h>
792 #include <tps6586x.h>
793 #include <asm/io.h>
794 #include <asm/arch/tegra.h>
795 @@ -23,9 +24,13 @@
796 #define VDD_TRANSITION_STEP 0x06 /* 150mv */
797 #define VDD_TRANSITION_RATE 0x06 /* 3.52mv/us */
798
799 +#define PMI_I2C_ADDRESS 0x34 /* chip requires this address */
800 +
801 int pmu_set_nominal(void)
802 {
803 - int core, cpu, bus;
804 + struct udevice *bus, *dev;
805 + int core, cpu;
806 + int ret;
807
808 /* by default, the table has been filled with T25 settings */
809 switch (tegra_get_chip_sku()) {
810 @@ -42,12 +47,18 @@
811 return -1;
812 }
813
814 - bus = tegra_i2c_get_dvc_bus_num();
815 - if (bus == -1) {
816 + ret = tegra_i2c_get_dvc_bus(&bus);
817 + if (ret) {
818 debug("%s: Cannot find DVC I2C bus\n", __func__);
819 - return -1;
820 + return ret;
821 }
822 - tps6586x_init(bus);
823 + ret = i2c_get_chip(bus, PMI_I2C_ADDRESS, &dev);
824 + if (ret) {
825 + debug("%s: Cannot find DVC I2C chip\n", __func__);
826 + return ret;
827 + }
828 +
829 + tps6586x_init(dev);
830 tps6586x_set_pwm_mode(TPS6586X_PWM_SM1);
831 return tps6586x_adjust_sm0_sm1(core, cpu, VDD_TRANSITION_STEP,
832 VDD_TRANSITION_RATE, VDD_RELATION);
833 diff -ruN u-boot-2015.01-rc3/arch/arm/cpu/u-boot-spl.lds u-boot/arch/arm/cpu/u-boot-spl.lds
834 --- u-boot-2015.01-rc3/arch/arm/cpu/u-boot-spl.lds 2014-12-08 22:35:08.000000000 +0100
835 +++ u-boot/arch/arm/cpu/u-boot-spl.lds 2015-01-01 17:34:32.037506793 +0100
836 @@ -32,6 +32,9 @@
837 }
838
839 . = ALIGN(4);
840 + .u_boot_list : {
841 + KEEP(*(SORT(.u_boot_list*_i2c_*)));
842 + }
843
844 . = .;
845 #ifdef CONFIG_SPL_DM
846 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/cros-ec-keyboard.dtsi u-boot/arch/arm/dts/cros-ec-keyboard.dtsi
847 --- u-boot-2015.01-rc3/arch/arm/dts/cros-ec-keyboard.dtsi 1970-01-01 01:00:00.000000000 +0100
848 +++ u-boot/arch/arm/dts/cros-ec-keyboard.dtsi 2015-01-01 17:34:32.037506793 +0100
849 @@ -0,0 +1,105 @@
850 +/*
851 + * Keyboard dts fragment for devices that use cros-ec-keyboard
852 + *
853 + * Copyright (c) 2014 Google, Inc
854 + *
855 + * This program is free software; you can redistribute it and/or modify
856 + * it under the terms of the GNU General Public License version 2 as
857 + * published by the Free Software Foundation.
858 +*/
859 +
860 +#include <dt-bindings/input/input.h>
861 +
862 +&cros_ec {
863 + keyboard-controller {
864 + compatible = "google,cros-ec-keyb";
865 + keypad,num-rows = <8>;
866 + keypad,num-columns = <13>;
867 + google,needs-ghost-filter;
868 +
869 + linux,keymap = <
870 + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
871 + MATRIX_KEY(0x00, 0x02, KEY_F1)
872 + MATRIX_KEY(0x00, 0x03, KEY_B)
873 + MATRIX_KEY(0x00, 0x04, KEY_F10)
874 + MATRIX_KEY(0x00, 0x06, KEY_N)
875 + MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
876 + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
877 +
878 + MATRIX_KEY(0x01, 0x01, KEY_ESC)
879 + MATRIX_KEY(0x01, 0x02, KEY_F4)
880 + MATRIX_KEY(0x01, 0x03, KEY_G)
881 + MATRIX_KEY(0x01, 0x04, KEY_F7)
882 + MATRIX_KEY(0x01, 0x06, KEY_H)
883 + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
884 + MATRIX_KEY(0x01, 0x09, KEY_F9)
885 + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
886 +
887 + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
888 + MATRIX_KEY(0x02, 0x01, KEY_TAB)
889 + MATRIX_KEY(0x02, 0x02, KEY_F3)
890 + MATRIX_KEY(0x02, 0x03, KEY_T)
891 + MATRIX_KEY(0x02, 0x04, KEY_F6)
892 + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
893 + MATRIX_KEY(0x02, 0x06, KEY_Y)
894 + MATRIX_KEY(0x02, 0x07, KEY_102ND)
895 + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
896 + MATRIX_KEY(0x02, 0x09, KEY_F8)
897 +
898 + MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
899 + MATRIX_KEY(0x03, 0x02, KEY_F2)
900 + MATRIX_KEY(0x03, 0x03, KEY_5)
901 + MATRIX_KEY(0x03, 0x04, KEY_F5)
902 + MATRIX_KEY(0x03, 0x06, KEY_6)
903 + MATRIX_KEY(0x03, 0x08, KEY_MINUS)
904 + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
905 +
906 + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
907 + MATRIX_KEY(0x04, 0x01, KEY_A)
908 + MATRIX_KEY(0x04, 0x02, KEY_D)
909 + MATRIX_KEY(0x04, 0x03, KEY_F)
910 + MATRIX_KEY(0x04, 0x04, KEY_S)
911 + MATRIX_KEY(0x04, 0x05, KEY_K)
912 + MATRIX_KEY(0x04, 0x06, KEY_J)
913 + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
914 + MATRIX_KEY(0x04, 0x09, KEY_L)
915 + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
916 + MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
917 +
918 + MATRIX_KEY(0x05, 0x01, KEY_Z)
919 + MATRIX_KEY(0x05, 0x02, KEY_C)
920 + MATRIX_KEY(0x05, 0x03, KEY_V)
921 + MATRIX_KEY(0x05, 0x04, KEY_X)
922 + MATRIX_KEY(0x05, 0x05, KEY_COMMA)
923 + MATRIX_KEY(0x05, 0x06, KEY_M)
924 + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
925 + MATRIX_KEY(0x05, 0x08, KEY_SLASH)
926 + MATRIX_KEY(0x05, 0x09, KEY_DOT)
927 + MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
928 +
929 + MATRIX_KEY(0x06, 0x01, KEY_1)
930 + MATRIX_KEY(0x06, 0x02, KEY_3)
931 + MATRIX_KEY(0x06, 0x03, KEY_4)
932 + MATRIX_KEY(0x06, 0x04, KEY_2)
933 + MATRIX_KEY(0x06, 0x05, KEY_8)
934 + MATRIX_KEY(0x06, 0x06, KEY_7)
935 + MATRIX_KEY(0x06, 0x08, KEY_0)
936 + MATRIX_KEY(0x06, 0x09, KEY_9)
937 + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
938 + MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
939 + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
940 +
941 + MATRIX_KEY(0x07, 0x01, KEY_Q)
942 + MATRIX_KEY(0x07, 0x02, KEY_E)
943 + MATRIX_KEY(0x07, 0x03, KEY_R)
944 + MATRIX_KEY(0x07, 0x04, KEY_W)
945 + MATRIX_KEY(0x07, 0x05, KEY_I)
946 + MATRIX_KEY(0x07, 0x06, KEY_U)
947 + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
948 + MATRIX_KEY(0x07, 0x08, KEY_P)
949 + MATRIX_KEY(0x07, 0x09, KEY_O)
950 + MATRIX_KEY(0x07, 0x0b, KEY_UP)
951 + MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
952 + >;
953 + };
954 +};
955 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h u-boot/arch/arm/dts/include/dt-bindings/pinctrl/pinctrl-tegra.h
956 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/include/dt-bindings/reset/altr,rst-mgr.h u-boot/arch/arm/dts/include/dt-bindings/reset/altr,rst-mgr.h
957 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/Makefile u-boot/arch/arm/dts/Makefile
958 --- u-boot-2015.01-rc3/arch/arm/dts/Makefile 2014-12-08 22:35:08.000000000 +0100
959 +++ u-boot/arch/arm/dts/Makefile 2015-01-01 17:34:32.037506793 +0100
960 @@ -31,6 +31,7 @@
961 tegra30-tec-ng.dtb \
962 tegra114-dalmore.dtb \
963 tegra124-jetson-tk1.dtb \
964 + tegra124-nyan-big.dtb \
965 tegra124-venice2.dtb
966 dtb-$(CONFIG_ARCH_UNIPHIER) += \
967 uniphier-ph1-sld3-ref.dtb \
968 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5.dtsi u-boot/arch/arm/dts/socfpga_cyclone5.dtsi
969 --- u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5.dtsi 2014-12-08 22:35:08.000000000 +0100
970 +++ u-boot/arch/arm/dts/socfpga_cyclone5.dtsi 2015-01-01 17:34:32.041506727 +0100
971 @@ -1,18 +1,7 @@
972 /*
973 * Copyright (C) 2012 Altera Corporation <www.altera.com>
974 *
975 - * This program is free software; you can redistribute it and/or modify
976 - * it under the terms of the GNU General Public License as published by
977 - * the Free Software Foundation; either version 2 of the License, or
978 - * (at your option) any later version.
979 - *
980 - * This program is distributed in the hope that it will be useful,
981 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
982 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
983 - * GNU General Public License for more details.
984 - *
985 - * You should have received a copy of the GNU General Public License
986 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
987 + * SPDX-License-Identifier: GPL-2.0+
988 */
989
990 /dts-v1/;
991 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5_socrates.dts u-boot/arch/arm/dts/socfpga_cyclone5_socrates.dts
992 --- u-boot-2015.01-rc3/arch/arm/dts/socfpga_cyclone5_socrates.dts 2014-12-08 22:35:08.000000000 +0100
993 +++ u-boot/arch/arm/dts/socfpga_cyclone5_socrates.dts 2015-01-01 17:34:32.041506727 +0100
994 @@ -1,18 +1,7 @@
995 /*
996 * Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
997 *
998 - * This program is free software; you can redistribute it and/or modify
999 - * it under the terms of the GNU General Public License as published by
1000 - * the Free Software Foundation; either version 2 of the License, or
1001 - * (at your option) any later version.
1002 - *
1003 - * This program is distributed in the hope that it will be useful,
1004 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1005 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1006 - * GNU General Public License for more details.
1007 - *
1008 - * You should have received a copy of the GNU General Public License
1009 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
1010 + * SPDX-License-Identifier: GPL-2.0+
1011 */
1012
1013 #include "socfpga_cyclone5.dtsi"
1014 @@ -25,6 +14,12 @@
1015 bootargs = "console=ttyS0,115200";
1016 };
1017
1018 + aliases {
1019 + spi0 = "/spi@ff705000"; /* QSPI */
1020 + spi1 = "/spi@fff00000";
1021 + spi2 = "/spi@fff01000";
1022 + };
1023 +
1024 memory {
1025 name = "memory";
1026 device_type = "memory";
1027 @@ -48,3 +43,23 @@
1028 &mmc {
1029 status = "okay";
1030 };
1031 +
1032 +&qspi {
1033 + status = "okay";
1034 +
1035 + flash0: n25q00@0 {
1036 + #address-cells = <1>;
1037 + #size-cells = <1>;
1038 + compatible = "n25q00";
1039 + reg = <0>; /* chip select */
1040 + spi-max-frequency = <50000000>;
1041 + m25p,fast-read;
1042 + page-size = <256>;
1043 + block-size = <16>; /* 2^16, 64KB */
1044 + read-delay = <4>; /* delay value in read data capture register */
1045 + tshsl-ns = <50>;
1046 + tsd2d-ns = <50>;
1047 + tchsh-ns = <4>;
1048 + tslch-ns = <4>;
1049 + };
1050 +};
1051 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/socfpga.dtsi u-boot/arch/arm/dts/socfpga.dtsi
1052 --- u-boot-2015.01-rc3/arch/arm/dts/socfpga.dtsi 2014-12-08 22:35:08.000000000 +0100
1053 +++ u-boot/arch/arm/dts/socfpga.dtsi 2015-01-01 17:34:32.041506727 +0100
1054 @@ -1,18 +1,7 @@
1055 /*
1056 * Copyright (C) 2012 Altera <www.altera.com>
1057 *
1058 - * This program is free software; you can redistribute it and/or modify
1059 - * it under the terms of the GNU General Public License as published by
1060 - * the Free Software Foundation; either version 2 of the License, or
1061 - * (at your option) any later version.
1062 - *
1063 - * This program is distributed in the hope that it will be useful,
1064 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1065 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1066 - * GNU General Public License for more details.
1067 - *
1068 - * You should have received a copy of the GNU General Public License
1069 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
1070 + * SPDX-License-Identifier: GPL-2.0+
1071 */
1072
1073 #include "skeleton.dtsi"
1074 @@ -639,6 +628,49 @@
1075 clock-names = "biu", "ciu";
1076 };
1077
1078 + qspi: spi@ff705000 {
1079 + compatible = "cadence,qspi";
1080 + #address-cells = <1>;
1081 + #size-cells = <0>;
1082 + reg = <0xff705000 0x1000>,
1083 + <0xffa00000 0x1000>;
1084 + interrupts = <0 151 4>;
1085 + clocks = <&qspi_clk>;
1086 + ext-decoder = <0>; /* external decoder */
1087 + num-chipselect = <4>;
1088 + fifo-depth = <128>;
1089 + bus-num = <2>;
1090 + status = "disabled";
1091 + };
1092 +
1093 + spi0: spi@fff00000 {
1094 + compatible = "snps,dw-spi-mmio";
1095 + #address-cells = <1>;
1096 + #size-cells = <0>;
1097 + reg = <0xfff00000 0x1000>;
1098 + interrupts = <0 154 4>;
1099 + num-chipselect = <4>;
1100 + bus-num = <0>;
1101 + tx-dma-channel = <&pdma 16>;
1102 + rx-dma-channel = <&pdma 17>;
1103 + clocks = <&per_base_clk>;
1104 + status = "disabled";
1105 + };
1106 +
1107 + spi1: spi@fff01000 {
1108 + compatible = "snps,dw-spi-mmio";
1109 + #address-cells = <1>;
1110 + #size-cells = <0>;
1111 + reg = <0xfff01000 0x1000>;
1112 + interrupts = <0 156 4>;
1113 + num-chipselect = <4>;
1114 + bus-num = <1>;
1115 + tx-dma-channel = <&pdma 20>;
1116 + rx-dma-channel = <&pdma 21>;
1117 + clocks = <&per_base_clk>;
1118 + status = "disabled";
1119 + };
1120 +
1121 /* Local timer */
1122 timer@fffec600 {
1123 compatible = "arm,cortex-a9-twd-timer";
1124 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra124.dtsi u-boot/arch/arm/dts/tegra124.dtsi
1125 --- u-boot-2015.01-rc3/arch/arm/dts/tegra124.dtsi 2014-12-08 22:35:08.000000000 +0100
1126 +++ u-boot/arch/arm/dts/tegra124.dtsi 2015-01-01 17:34:32.041506727 +0100
1127 @@ -1,5 +1,6 @@
1128 #include <dt-bindings/clock/tegra124-car.h>
1129 #include <dt-bindings/gpio/tegra-gpio.h>
1130 +#include <dt-bindings/pinctrl/pinctrl-tegra.h>
1131 #include <dt-bindings/interrupt-controller/arm-gic.h>
1132
1133 #include "skeleton.dtsi"
1134 @@ -192,6 +193,16 @@
1135 status = "disabled";
1136 };
1137
1138 + pwm: pwm@7000a000 {
1139 + compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
1140 + reg = <0x7000a000 0x100>;
1141 + #pwm-cells = <2>;
1142 + clocks = <&tegra_car TEGRA124_CLK_PWM>;
1143 + resets = <&tegra_car 17>;
1144 + reset-names = "pwm";
1145 + status = "disabled";
1146 + };
1147 +
1148 spi@7000d400 {
1149 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
1150 reg = <0x7000d400 0x200>;
1151 @@ -290,6 +301,109 @@
1152 status = "disabled";
1153 };
1154
1155 + ahub@70300000 {
1156 + compatible = "nvidia,tegra124-ahub";
1157 + reg = <0x70300000 0x200>,
1158 + <0x70300800 0x800>,
1159 + <0x70300200 0x600>;
1160 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1161 + clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
1162 + <&tegra_car TEGRA124_CLK_APBIF>;
1163 + clock-names = "d_audio", "apbif";
1164 + resets = <&tegra_car 106>, /* d_audio */
1165 + <&tegra_car 107>, /* apbif */
1166 + <&tegra_car 30>, /* i2s0 */
1167 + <&tegra_car 11>, /* i2s1 */
1168 + <&tegra_car 18>, /* i2s2 */
1169 + <&tegra_car 101>, /* i2s3 */
1170 + <&tegra_car 102>, /* i2s4 */
1171 + <&tegra_car 108>, /* dam0 */
1172 + <&tegra_car 109>, /* dam1 */
1173 + <&tegra_car 110>, /* dam2 */
1174 + <&tegra_car 10>, /* spdif */
1175 + <&tegra_car 153>, /* amx */
1176 + <&tegra_car 185>, /* amx1 */
1177 + <&tegra_car 154>, /* adx */
1178 + <&tegra_car 180>, /* adx1 */
1179 + <&tegra_car 186>, /* afc0 */
1180 + <&tegra_car 187>, /* afc1 */
1181 + <&tegra_car 188>, /* afc2 */
1182 + <&tegra_car 189>, /* afc3 */
1183 + <&tegra_car 190>, /* afc4 */
1184 + <&tegra_car 191>; /* afc5 */
1185 + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
1186 + "i2s3", "i2s4", "dam0", "dam1", "dam2",
1187 + "spdif", "amx", "amx1", "adx", "adx1",
1188 + "afc0", "afc1", "afc2", "afc3", "afc4", "afc5";
1189 + dmas = <&apbdma 1>, <&apbdma 1>,
1190 + <&apbdma 2>, <&apbdma 2>,
1191 + <&apbdma 3>, <&apbdma 3>,
1192 + <&apbdma 4>, <&apbdma 4>,
1193 + <&apbdma 6>, <&apbdma 6>,
1194 + <&apbdma 7>, <&apbdma 7>,
1195 + <&apbdma 12>, <&apbdma 12>,
1196 + <&apbdma 13>, <&apbdma 13>,
1197 + <&apbdma 14>, <&apbdma 14>,
1198 + <&apbdma 29>, <&apbdma 29>;
1199 + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
1200 + "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
1201 + "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
1202 + "rx9", "tx9";
1203 + ranges;
1204 + #address-cells = <1>;
1205 + #size-cells = <1>;
1206 +
1207 + tegra_i2s0: i2s@70301000 {
1208 + compatible = "nvidia,tegra124-i2s";
1209 + reg = <0x70301000 0x100>;
1210 + nvidia,ahub-cif-ids = <4 4>;
1211 + clocks = <&tegra_car TEGRA124_CLK_I2S0>;
1212 + resets = <&tegra_car 30>;
1213 + reset-names = "i2s";
1214 + status = "disabled";
1215 + };
1216 +
1217 + tegra_i2s1: i2s@70301100 {
1218 + compatible = "nvidia,tegra124-i2s";
1219 + reg = <0x70301100 0x100>;
1220 + nvidia,ahub-cif-ids = <5 5>;
1221 + clocks = <&tegra_car TEGRA124_CLK_I2S1>;
1222 + resets = <&tegra_car 11>;
1223 + reset-names = "i2s";
1224 + status = "disabled";
1225 + };
1226 +
1227 + tegra_i2s2: i2s@70301200 {
1228 + compatible = "nvidia,tegra124-i2s";
1229 + reg = <0x70301200 0x100>;
1230 + nvidia,ahub-cif-ids = <6 6>;
1231 + clocks = <&tegra_car TEGRA124_CLK_I2S2>;
1232 + resets = <&tegra_car 18>;
1233 + reset-names = "i2s";
1234 + status = "disabled";
1235 + };
1236 +
1237 + tegra_i2s3: i2s@70301300 {
1238 + compatible = "nvidia,tegra124-i2s";
1239 + reg = <0x70301300 0x100>;
1240 + nvidia,ahub-cif-ids = <7 7>;
1241 + clocks = <&tegra_car TEGRA124_CLK_I2S3>;
1242 + resets = <&tegra_car 101>;
1243 + reset-names = "i2s";
1244 + status = "disabled";
1245 + };
1246 +
1247 + tegra_i2s4: i2s@70301400 {
1248 + compatible = "nvidia,tegra124-i2s";
1249 + reg = <0x70301400 0x100>;
1250 + nvidia,ahub-cif-ids = <8 8>;
1251 + clocks = <&tegra_car TEGRA124_CLK_I2S4>;
1252 + resets = <&tegra_car 102>;
1253 + reset-names = "i2s";
1254 + status = "disabled";
1255 + };
1256 + };
1257 +
1258 usb@7d000000 {
1259 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci";
1260 reg = <0x7d000000 0x4000>;
1261 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra124-jetson-tk1.dts u-boot/arch/arm/dts/tegra124-jetson-tk1.dts
1262 --- u-boot-2015.01-rc3/arch/arm/dts/tegra124-jetson-tk1.dts 2014-12-08 22:35:08.000000000 +0100
1263 +++ u-boot/arch/arm/dts/tegra124-jetson-tk1.dts 2015-01-01 17:34:32.041506727 +0100
1264 @@ -16,7 +16,6 @@
1265 i2c2 = "/i2c@7000c400";
1266 i2c3 = "/i2c@7000c500";
1267 i2c4 = "/i2c@7000c700";
1268 - i2c5 = "/i2c@7000d100";
1269 sdhci0 = "/sdhci@700b0600";
1270 sdhci1 = "/sdhci@700b0400";
1271 spi0 = "/spi@7000d400";
1272 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra124-nyan-big.dts u-boot/arch/arm/dts/tegra124-nyan-big.dts
1273 --- u-boot-2015.01-rc3/arch/arm/dts/tegra124-nyan-big.dts 1970-01-01 01:00:00.000000000 +0100
1274 +++ u-boot/arch/arm/dts/tegra124-nyan-big.dts 2015-01-01 17:34:32.041506727 +0100
1275 @@ -0,0 +1,365 @@
1276 +/dts-v1/;
1277 +
1278 +#include <dt-bindings/input/input.h>
1279 +#include "tegra124.dtsi"
1280 +
1281 +/ {
1282 + model = "Acer Chromebook 13 CB5-311";
1283 + compatible = "google,nyan-big", "nvidia,tegra124";
1284 +
1285 + aliases {
1286 + console = &uarta;
1287 + i2c0 = "/i2c@7000d000";
1288 + i2c1 = "/i2c@7000c000";
1289 + i2c2 = "/i2c@7000c400";
1290 + i2c3 = "/i2c@7000c500";
1291 + i2c4 = "/i2c@7000c700";
1292 + i2c5 = "/i2c@7000d100";
1293 + rtc0 = "/i2c@0,7000d000/pmic@40";
1294 + rtc1 = "/rtc@0,7000e000";
1295 + sdhci0 = "/sdhci@700b0600";
1296 + sdhci1 = "/sdhci@700b0400";
1297 + spi0 = "/spi@7000d400";
1298 + spi1 = "/spi@7000da00";
1299 + usb0 = "/usb@7d000000";
1300 + usb1 = "/usb@7d008000";
1301 + };
1302 +
1303 + memory {
1304 + reg = <0x80000000 0x80000000>;
1305 + };
1306 +
1307 + serial@70006000 {
1308 + /* Debug connector on the bottom of the board near SD card. */
1309 + status = "okay";
1310 + };
1311 +
1312 + pwm@7000a000 {
1313 + status = "okay";
1314 + };
1315 +
1316 + i2c@7000c000 {
1317 + status = "okay";
1318 + clock-frequency = <100000>;
1319 +
1320 + acodec: audio-codec@10 {
1321 + compatible = "maxim,max98090";
1322 + reg = <0x10>;
1323 + interrupt-parent = <&gpio>;
1324 + interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
1325 + };
1326 +
1327 + temperature-sensor@4c {
1328 + compatible = "ti,tmp451";
1329 + reg = <0x4c>;
1330 + interrupt-parent = <&gpio>;
1331 + interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1332 +
1333 + #thermal-sensor-cells = <1>;
1334 + };
1335 + };
1336 +
1337 + i2c@7000c400 {
1338 + status = "okay";
1339 + clock-frequency = <100000>;
1340 + };
1341 +
1342 + i2c@7000c500 {
1343 + status = "okay";
1344 + clock-frequency = <400000>;
1345 +
1346 + tpm@20 {
1347 + compatible = "infineon,slb9645tt";
1348 + reg = <0x20>;
1349 + };
1350 + };
1351 +
1352 + hdmi_ddc: i2c@7000c700 {
1353 + status = "okay";
1354 + clock-frequency = <100000>;
1355 + };
1356 +
1357 + i2c@7000d000 {
1358 + status = "okay";
1359 + clock-frequency = <400000>;
1360 +
1361 + pmic: pmic@40 {
1362 + compatible = "ams,as3722";
1363 + reg = <0x40>;
1364 + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1365 +
1366 + ams,system-power-controller;
1367 +
1368 + #interrupt-cells = <2>;
1369 + interrupt-controller;
1370 +
1371 + gpio-controller;
1372 + #gpio-cells = <2>;
1373 +
1374 + pinctrl-names = "default";
1375 + pinctrl-0 = <&as3722_default>;
1376 +
1377 + as3722_default: pinmux {
1378 + gpio0 {
1379 + pins = "gpio0";
1380 + function = "gpio";
1381 + bias-pull-down;
1382 + };
1383 +
1384 + gpio1 {
1385 + pins = "gpio1";
1386 + function = "gpio";
1387 + bias-pull-up;
1388 + };
1389 +
1390 + gpio2_4_7 {
1391 + pins = "gpio2", "gpio4", "gpio7";
1392 + function = "gpio";
1393 + bias-pull-up;
1394 + };
1395 +
1396 + gpio3_6 {
1397 + pins = "gpio3", "gpio6";
1398 + bias-high-impedance;
1399 + };
1400 +
1401 + gpio5 {
1402 + pins = "gpio5";
1403 + function = "clk32k-out";
1404 + bias-pull-down;
1405 + };
1406 + };
1407 + };
1408 + };
1409 +
1410 + spi@7000d400 {
1411 + status = "okay";
1412 +
1413 + cros_ec: cros-ec@0 {
1414 + compatible = "google,cros-ec-spi";
1415 + spi-max-frequency = <3000000>;
1416 + interrupt-parent = <&gpio>;
1417 + interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
1418 + reg = <0>;
1419 +
1420 + google,cros-ec-spi-msg-delay = <2000>;
1421 +
1422 + i2c-tunnel {
1423 + compatible = "google,cros-ec-i2c-tunnel";
1424 + #address-cells = <1>;
1425 + #size-cells = <0>;
1426 +
1427 + google,remote-bus = <0>;
1428 +
1429 + charger: bq24735@9 {
1430 + compatible = "ti,bq24735";
1431 + reg = <0x9>;
1432 + interrupt-parent = <&gpio>;
1433 + interrupts = <TEGRA_GPIO(J, 0)
1434 + GPIO_ACTIVE_HIGH>;
1435 + ti,ac-detect-gpios = <&gpio
1436 + TEGRA_GPIO(J, 0)
1437 + GPIO_ACTIVE_HIGH>;
1438 + };
1439 +
1440 + battery: sbs-battery@b {
1441 + compatible = "sbs,sbs-battery";
1442 + reg = <0xb>;
1443 + sbs,i2c-retry-count = <2>;
1444 + sbs,poll-retry-count = <10>;
1445 + power-supplies = <&charger>;
1446 + };
1447 + };
1448 + };
1449 + };
1450 +
1451 + spi@7000da00 {
1452 + status = "okay";
1453 + spi-max-frequency = <25000000>;
1454 +
1455 + flash@0 {
1456 + compatible = "winbond,w25q32dw";
1457 + reg = <0>;
1458 + };
1459 + };
1460 +
1461 + pmc@7000e400 {
1462 + nvidia,invert-interrupt;
1463 + nvidia,suspend-mode = <0>;
1464 + nvidia,cpu-pwr-good-time = <500>;
1465 + nvidia,cpu-pwr-off-time = <300>;
1466 + nvidia,core-pwr-good-time = <641 3845>;
1467 + nvidia,core-pwr-off-time = <61036>;
1468 + nvidia,core-power-req-active-high;
1469 + nvidia,sys-clock-req-active-high;
1470 + };
1471 +
1472 + hda@70030000 {
1473 + status = "okay";
1474 + };
1475 +
1476 + sdhci@700b0000 { /* WiFi/BT on this bus */
1477 + status = "okay";
1478 + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
1479 + bus-width = <4>;
1480 + no-1-8-v;
1481 + non-removable;
1482 + };
1483 +
1484 + sdhci@700b0400 { /* SD Card on this bus */
1485 + status = "okay";
1486 + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
1487 + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
1488 + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
1489 + bus-width = <4>;
1490 + no-1-8-v;
1491 + };
1492 +
1493 + sdhci@700b0600 { /* eMMC on this bus */
1494 + status = "okay";
1495 + bus-width = <8>;
1496 + no-1-8-v;
1497 + non-removable;
1498 + };
1499 +
1500 + ahub@70300000 {
1501 + i2s@70301100 {
1502 + status = "okay";
1503 + };
1504 + };
1505 +
1506 + usb@7d000000 { /* Rear external USB port. */
1507 + status = "okay";
1508 + };
1509 +
1510 + usb-phy@7d000000 {
1511 + status = "okay";
1512 + };
1513 +
1514 + usb@7d004000 { /* Internal webcam. */
1515 + status = "okay";
1516 + };
1517 +
1518 + usb-phy@7d004000 {
1519 + status = "okay";
1520 + };
1521 +
1522 + usb@7d008000 { /* Left external USB port. */
1523 + status = "okay";
1524 + };
1525 +
1526 + usb-phy@7d008000 {
1527 + status = "okay";
1528 + };
1529 +
1530 + backlight: backlight {
1531 + compatible = "pwm-backlight";
1532 +
1533 + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1534 + pwms = <&pwm 1 1000000>;
1535 +
1536 + default-brightness-level = <224>;
1537 + brightness-levels =
1538 + < 0 1 2 3 4 5 6 7
1539 + 8 9 10 11 12 13 14 15
1540 + 16 17 18 19 20 21 22 23
1541 + 24 25 26 27 28 29 30 31
1542 + 32 33 34 35 36 37 38 39
1543 + 40 41 42 43 44 45 46 47
1544 + 48 49 50 51 52 53 54 55
1545 + 56 57 58 59 60 61 62 63
1546 + 64 65 66 67 68 69 70 71
1547 + 72 73 74 75 76 77 78 79
1548 + 80 81 82 83 84 85 86 87
1549 + 88 89 90 91 92 93 94 95
1550 + 96 97 98 99 100 101 102 103
1551 + 104 105 106 107 108 109 110 111
1552 + 112 113 114 115 116 117 118 119
1553 + 120 121 122 123 124 125 126 127
1554 + 128 129 130 131 132 133 134 135
1555 + 136 137 138 139 140 141 142 143
1556 + 144 145 146 147 148 149 150 151
1557 + 152 153 154 155 156 157 158 159
1558 + 160 161 162 163 164 165 166 167
1559 + 168 169 170 171 172 173 174 175
1560 + 176 177 178 179 180 181 182 183
1561 + 184 185 186 187 188 189 190 191
1562 + 192 193 194 195 196 197 198 199
1563 + 200 201 202 203 204 205 206 207
1564 + 208 209 210 211 212 213 214 215
1565 + 216 217 218 219 220 221 222 223
1566 + 224 225 226 227 228 229 230 231
1567 + 232 233 234 235 236 237 238 239
1568 + 240 241 242 243 244 245 246 247
1569 + 248 249 250 251 252 253 254 255
1570 + 256>;
1571 + };
1572 +
1573 + clocks {
1574 + compatible = "simple-bus";
1575 + #address-cells = <1>;
1576 + #size-cells = <0>;
1577 +
1578 + clk32k_in: clock@0 {
1579 + compatible = "fixed-clock";
1580 + reg = <0>;
1581 + #clock-cells = <0>;
1582 + clock-frequency = <32768>;
1583 + };
1584 + };
1585 +
1586 + gpio-keys {
1587 + compatible = "gpio-keys";
1588 +
1589 + lid {
1590 + label = "Lid";
1591 + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>;
1592 + linux,input-type = <5>;
1593 + linux,code = <KEY_RESERVED>;
1594 + debounce-interval = <1>;
1595 + gpio-key,wakeup;
1596 + };
1597 +
1598 + power {
1599 + label = "Power";
1600 + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1601 + linux,code = <KEY_POWER>;
1602 + debounce-interval = <30>;
1603 + gpio-key,wakeup;
1604 + };
1605 + };
1606 +
1607 + panel: panel {
1608 + compatible = "auo,b133xtn01";
1609 +
1610 + backlight = <&backlight>;
1611 + };
1612 +
1613 + sound {
1614 + compatible = "nvidia,tegra-audio-max98090-nyan-big",
1615 + "nvidia,tegra-audio-max98090";
1616 + nvidia,model = "Acer Chromebook 13";
1617 +
1618 + nvidia,audio-routing =
1619 + "Headphones", "HPR",
1620 + "Headphones", "HPL",
1621 + "Speakers", "SPKR",
1622 + "Speakers", "SPKL",
1623 + "Mic Jack", "MICBIAS",
1624 + "DMICL", "Int Mic",
1625 + "DMICR", "Int Mic",
1626 + "IN34", "Mic Jack";
1627 +
1628 + nvidia,i2s-controller = <&tegra_i2s1>;
1629 + nvidia,audio-codec = <&acodec>;
1630 +
1631 + clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1632 + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1633 + <&tegra_car TEGRA124_CLK_EXTERN1>;
1634 + clock-names = "pll_a", "pll_a_out0", "mclk";
1635 +
1636 + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>;
1637 + };
1638 +};
1639 +
1640 +#include "cros-ec-keyboard.dtsi"
1641 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/tegra30-tec-ng.dts u-boot/arch/arm/dts/tegra30-tec-ng.dts
1642 --- u-boot-2015.01-rc3/arch/arm/dts/tegra30-tec-ng.dts 2014-12-08 22:35:08.000000000 +0100
1643 +++ u-boot/arch/arm/dts/tegra30-tec-ng.dts 2015-01-01 17:34:32.045506662 +0100
1644 @@ -6,6 +6,10 @@
1645 model = "Avionic Design Tamonten™ NG Evaluation Carrier";
1646 compatible = "ad,tec-ng", "nvidia,tegra30";
1647
1648 + aliases {
1649 + i2c0 = "/i2c@7000c400";
1650 + };
1651 +
1652 /* GEN2 */
1653 i2c@7000c400 {
1654 status = "okay";
1655 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-ld4-ref.dts u-boot/arch/arm/dts/uniphier-ph1-ld4-ref.dts
1656 --- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-ld4-ref.dts 2014-12-08 22:35:08.000000000 +0100
1657 +++ u-boot/arch/arm/dts/uniphier-ph1-ld4-ref.dts 2015-01-01 17:34:32.045506662 +0100
1658 @@ -25,10 +25,10 @@
1659 };
1660
1661 aliases {
1662 - uart0 = &uart0;
1663 - uart1 = &uart1;
1664 - uart2 = &uart2;
1665 - uart3 = &uart3;
1666 + serial0 = &uart0;
1667 + serial1 = &uart1;
1668 + serial2 = &uart2;
1669 + serial3 = &uart3;
1670 i2c0 = &i2c0;
1671 i2c1 = &i2c1;
1672 i2c2 = &i2c2;
1673 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-pro4-ref.dts u-boot/arch/arm/dts/uniphier-ph1-pro4-ref.dts
1674 --- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-pro4-ref.dts 2014-12-08 22:35:08.000000000 +0100
1675 +++ u-boot/arch/arm/dts/uniphier-ph1-pro4-ref.dts 2015-01-01 17:34:32.045506662 +0100
1676 @@ -25,10 +25,10 @@
1677 };
1678
1679 aliases {
1680 - uart0 = &uart0;
1681 - uart1 = &uart1;
1682 - uart2 = &uart2;
1683 - uart3 = &uart3;
1684 + serial0 = &uart0;
1685 + serial1 = &uart1;
1686 + serial2 = &uart2;
1687 + serial3 = &uart3;
1688 i2c0 = &i2c0;
1689 i2c1 = &i2c1;
1690 i2c2 = &i2c2;
1691 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld3-ref.dts u-boot/arch/arm/dts/uniphier-ph1-sld3-ref.dts
1692 --- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld3-ref.dts 2014-12-08 22:35:08.000000000 +0100
1693 +++ u-boot/arch/arm/dts/uniphier-ph1-sld3-ref.dts 2015-01-01 17:34:32.045506662 +0100
1694 @@ -25,9 +25,9 @@
1695 };
1696
1697 aliases {
1698 - uart0 = &uart0;
1699 - uart1 = &uart1;
1700 - uart2 = &uart2;
1701 + serial0 = &uart0;
1702 + serial1 = &uart1;
1703 + serial2 = &uart2;
1704 i2c0 = &i2c0;
1705 i2c1 = &i2c1;
1706 i2c2 = &i2c2;
1707 diff -ruN u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld8-ref.dts u-boot/arch/arm/dts/uniphier-ph1-sld8-ref.dts
1708 --- u-boot-2015.01-rc3/arch/arm/dts/uniphier-ph1-sld8-ref.dts 2014-12-08 22:35:08.000000000 +0100
1709 +++ u-boot/arch/arm/dts/uniphier-ph1-sld8-ref.dts 2015-01-01 17:34:32.045506662 +0100
1710 @@ -25,10 +25,10 @@
1711 };
1712
1713 aliases {
1714 - uart0 = &uart0;
1715 - uart1 = &uart1;
1716 - uart2 = &uart2;
1717 - uart3 = &uart3;
1718 + serial0 = &uart0;
1719 + serial1 = &uart1;
1720 + serial2 = &uart2;
1721 + serial3 = &uart3;
1722 i2c0 = &i2c0;
1723 i2c1 = &i2c1;
1724 i2c2 = &i2c2;
1725 diff -ruN u-boot-2015.01-rc3/arch/arm/imx-common/cpu.c u-boot/arch/arm/imx-common/cpu.c
1726 --- u-boot-2015.01-rc3/arch/arm/imx-common/cpu.c 2014-12-08 22:35:08.000000000 +0100
1727 +++ u-boot/arch/arm/imx-common/cpu.c 2015-01-01 17:34:32.045506662 +0100
1728 @@ -206,6 +206,9 @@
1729 {
1730 #if defined(CONFIG_CMD_SATA)
1731 sata_stop();
1732 +#if defined(CONFIG_MX6)
1733 + disable_sata_clock();
1734 +#endif
1735 #endif
1736 #if defined(CONFIG_VIDEO_IPUV3)
1737 /* disable video before launching O/S */
1738 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm281xx/sysmap.h u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h
1739 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm281xx/sysmap.h 2014-12-08 22:35:08.000000000 +0100
1740 +++ u-boot/arch/arm/include/asm/arch-bcm281xx/sysmap.h 2015-01-01 17:34:32.053506531 +0100
1741 @@ -13,6 +13,8 @@
1742 #define ESUB_CLK_BASE_ADDR 0x38000000
1743 #define ESW_CONTRL_BASE_ADDR 0x38200000
1744 #define GPIO2_BASE_ADDR 0x35003000
1745 +#define HSOTG_BASE_ADDR 0x3f120000
1746 +#define HSOTG_CTRL_BASE_ADDR 0x3f130000
1747 #define KONA_MST_CLK_BASE_ADDR 0x3f001000
1748 #define KONA_SLV_CLK_BASE_ADDR 0x3e011000
1749 #define PMU_BSC_BASE_ADDR 0x3500d000
1750 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm2835/mbox.h u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h
1751 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-bcm2835/mbox.h 2014-12-08 22:35:08.000000000 +0100
1752 +++ u-boot/arch/arm/include/asm/arch-bcm2835/mbox.h 2015-01-01 17:34:32.053506531 +0100
1753 @@ -140,6 +140,7 @@
1754 #define BCM2835_BOARD_REV_B_REV2_f 0xf
1755 #define BCM2835_BOARD_REV_B_PLUS 0x10
1756 #define BCM2835_BOARD_REV_CM 0x11
1757 +#define BCM2835_BOARD_REV_A_PLUS 0x12
1758
1759 struct bcm2835_mbox_tag_get_board_rev {
1760 struct bcm2835_mbox_tag_hdr tag_hdr;
1761 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/config.h u-boot/arch/arm/include/asm/arch-ls102xa/config.h
1762 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/config.h 2014-12-08 22:35:08.000000000 +0100
1763 +++ u-boot/arch/arm/include/asm/arch-ls102xa/config.h 2015-01-01 17:34:32.065506333 +0100
1764 @@ -11,11 +11,17 @@
1765
1766 #define OCRAM_BASE_ADDR 0x10000000
1767 #define OCRAM_SIZE 0x00020000
1768 +#define OCRAM_BASE_S_ADDR 0x10010000
1769 +#define OCRAM_S_SIZE 0x00010000
1770
1771 #define CONFIG_SYS_IMMR 0x01000000
1772 +#define CONFIG_SYS_DCSRBAR 0x20000000
1773 +
1774 +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
1775
1776 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
1777 #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
1778 +#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
1779 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
1780 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
1781 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
1782 @@ -52,6 +58,9 @@
1783
1784 #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
1785
1786 +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
1787 +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
1788 +
1789 #ifdef CONFIG_DDR_SPD
1790 #define CONFIG_SYS_FSL_DDR_BE
1791 #define CONFIG_VERY_BIG_RAM
1792 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
1793 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 2014-12-08 22:35:08.000000000 +0100
1794 +++ u-boot/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 2015-01-01 17:34:32.065506333 +0100
1795 @@ -17,6 +17,9 @@
1796 #define SOC_VER_LS1021 0x11
1797 #define SOC_VER_LS1022 0x12
1798
1799 +#define CCSR_BRR_OFFSET 0xe4
1800 +#define CCSR_SCRATCHRW1_OFFSET 0x200
1801 +
1802 #define RCWSR0_SYS_PLL_RAT_SHIFT 25
1803 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f
1804 #define RCWSR0_MEM_PLL_RAT_SHIFT 16
1805 @@ -29,6 +32,11 @@
1806 #define ARCH_TIMER_CTRL_ENABLE (1 << 0)
1807 #define SYS_COUNTER_CTRL_ENABLE (1 << 24)
1808
1809 +#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000
1810 +#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000
1811 +
1812 +#define DCFG_DCSR_PORCR1 0
1813 +
1814 struct sys_info {
1815 unsigned long freq_processor[CONFIG_MAX_CPUS];
1816 unsigned long freq_systembus;
1817 @@ -98,6 +106,7 @@
1818 #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
1819 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
1820 #define SCFG_PIXCLKCR_PXCKEN 0x80000000
1821 +#define SCFG_QSPI_CLKSEL 0xc0100000
1822
1823 /* Supplemental Configuration Unit */
1824 struct ccsr_scfg {
1825 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
1826 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h 1970-01-01 01:00:00.000000000 +0100
1827 +++ u-boot/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h 2015-01-01 17:34:32.065506333 +0100
1828 @@ -0,0 +1,17 @@
1829 +/*
1830 + * Copyright 2014 Freescale Semiconductor, Inc.
1831 + *
1832 + * SPDX-License-Identifier: GPL-2.0+
1833 + */
1834 +
1835 +#ifndef __FSL_LS102XA_STREAM_ID_H_
1836 +#define __FSL_LS102XA_STREAM_ID_H_
1837 +
1838 +struct smmu_stream_id {
1839 + uint16_t offset;
1840 + uint16_t stream_id;
1841 + char dev_name[32];
1842 +};
1843 +
1844 +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num);
1845 +#endif
1846 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ns_access.h u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h
1847 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/ns_access.h 1970-01-01 01:00:00.000000000 +0100
1848 +++ u-boot/arch/arm/include/asm/arch-ls102xa/ns_access.h 2015-01-01 17:34:32.065506333 +0100
1849 @@ -0,0 +1,118 @@
1850 +/*
1851 + * Copyright 2014 Freescale Semiconductor, Inc.
1852 + *
1853 + * SPDX-License-Identifier: GPL-2.0+
1854 + */
1855 +
1856 +#ifndef __FSL_NS_ACCESS_H_
1857 +#define __FSL_NS_ACCESS_H_
1858 +
1859 +enum csu_cslx_access {
1860 + CSU_NS_SUP_R = 0x08,
1861 + CSU_NS_SUP_W = 0x80,
1862 + CSU_NS_SUP_RW = 0x88,
1863 + CSU_NS_USER_R = 0x04,
1864 + CSU_NS_USER_W = 0x40,
1865 + CSU_NS_USER_RW = 0x44,
1866 + CSU_S_SUP_R = 0x02,
1867 + CSU_S_SUP_W = 0x20,
1868 + CSU_S_SUP_RW = 0x22,
1869 + CSU_S_USER_R = 0x01,
1870 + CSU_S_USER_W = 0x10,
1871 + CSU_S_USER_RW = 0x11,
1872 + CSU_ALL_RW = 0xff,
1873 +};
1874 +
1875 +enum csu_cslx_ind {
1876 + CSU_CSLX_PCIE2_IO = 0,
1877 + CSU_CSLX_PCIE1_IO,
1878 + CSU_CSLX_MG2TPR_IP,
1879 + CSU_CSLX_IFC_MEM,
1880 + CSU_CSLX_OCRAM,
1881 + CSU_CSLX_GIC,
1882 + CSU_CSLX_PCIE1,
1883 + CSU_CSLX_OCRAM2,
1884 + CSU_CSLX_QSPI_MEM,
1885 + CSU_CSLX_PCIE2,
1886 + CSU_CSLX_SATA,
1887 + CSU_CSLX_USB3,
1888 + CSU_CSLX_SERDES = 32,
1889 + CSU_CSLX_QDMA,
1890 + CSU_CSLX_LPUART2,
1891 + CSU_CSLX_LPUART1,
1892 + CSU_CSLX_LPUART4,
1893 + CSU_CSLX_LPUART3,
1894 + CSU_CSLX_LPUART6,
1895 + CSU_CSLX_LPUART5,
1896 + CSU_CSLX_DSPI2 = 40,
1897 + CSU_CSLX_DSPI1,
1898 + CSU_CSLX_QSPI,
1899 + CSU_CSLX_ESDHC,
1900 + CSU_CSLX_2D_ACE,
1901 + CSU_CSLX_IFC,
1902 + CSU_CSLX_I2C1,
1903 + CSU_CSLX_USB2,
1904 + CSU_CSLX_I2C3,
1905 + CSU_CSLX_I2C2,
1906 + CSU_CSLX_DUART2 = 50,
1907 + CSU_CSLX_DUART1,
1908 + CSU_CSLX_WDT2,
1909 + CSU_CSLX_WDT1,
1910 + CSU_CSLX_EDMA,
1911 + CSU_CSLX_SYS_CNT,
1912 + CSU_CSLX_DMA_MUX2,
1913 + CSU_CSLX_DMA_MUX1,
1914 + CSU_CSLX_DDR,
1915 + CSU_CSLX_QUICC,
1916 + CSU_CSLX_DCFG_CCU_RCPM = 60,
1917 + CSU_CSLX_SECURE_BOOTROM,
1918 + CSU_CSLX_SFP,
1919 + CSU_CSLX_TMU,
1920 + CSU_CSLX_SECURE_MONITOR,
1921 + CSU_CSLX_RESERVED0,
1922 + CSU_CSLX_ETSEC1,
1923 + CSU_CSLX_SEC5_5,
1924 + CSU_CSLX_ETSEC3,
1925 + CSU_CSLX_ETSEC2,
1926 + CSU_CSLX_GPIO2 = 70,
1927 + CSU_CSLX_GPIO1,
1928 + CSU_CSLX_GPIO4,
1929 + CSU_CSLX_GPIO3,
1930 + CSU_CSLX_PLATFORM_CONT,
1931 + CSU_CSLX_CSU,
1932 + CSU_CSLX_ASRC,
1933 + CSU_CSLX_SPDIF,
1934 + CSU_CSLX_FLEXCAN2,
1935 + CSU_CSLX_FLEXCAN1,
1936 + CSU_CSLX_FLEXCAN4 = 80,
1937 + CSU_CSLX_FLEXCAN3,
1938 + CSU_CSLX_SAI2,
1939 + CSU_CSLX_SAI1,
1940 + CSU_CSLX_SAI4,
1941 + CSU_CSLX_SAI3,
1942 + CSU_CSLX_FTM2,
1943 + CSU_CSLX_FTM1,
1944 + CSU_CSLX_FTM4,
1945 + CSU_CSLX_FTM3,
1946 + CSU_CSLX_FTM6 = 90,
1947 + CSU_CSLX_FTM5,
1948 + CSU_CSLX_FTM8,
1949 + CSU_CSLX_FTM7,
1950 + CSU_CSLX_COP_DCSR,
1951 + CSU_CSLX_EPU,
1952 + CSU_CSLX_GDI,
1953 + CSU_CSLX_DDI,
1954 + CSU_CSLX_RESERVED1,
1955 + CSU_CSLX_USB3_PHY = 117,
1956 + CSU_CSLX_RESERVED2,
1957 + CSU_CSLX_MAX,
1958 +};
1959 +
1960 +struct csu_ns_dev {
1961 + unsigned long ind;
1962 + uint32_t val;
1963 +};
1964 +
1965 +void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
1966 +
1967 +#endif
1968 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/spl.h u-boot/arch/arm/include/asm/arch-ls102xa/spl.h
1969 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-ls102xa/spl.h 1970-01-01 01:00:00.000000000 +0100
1970 +++ u-boot/arch/arm/include/asm/arch-ls102xa/spl.h 2015-01-01 17:34:32.065506333 +0100
1971 @@ -0,0 +1,20 @@
1972 +/*
1973 + * Copyright 2014 Freescale Semiconductor, Inc.
1974 + *
1975 + * SPDX-License-Identifier: GPL-2.0+
1976 + */
1977 +
1978 +#ifndef __ASM_ARCH_SPL_H__
1979 +#define __ASM_ARCH_SPL_H__
1980 +
1981 +#define BOOT_DEVICE_NONE 0
1982 +#define BOOT_DEVICE_XIP 1
1983 +#define BOOT_DEVICE_XIPWAIT 2
1984 +#define BOOT_DEVICE_NAND 3
1985 +#define BOOT_DEVICE_ONENAND 4
1986 +#define BOOT_DEVICE_MMC1 5
1987 +#define BOOT_DEVICE_MMC2 6
1988 +#define BOOT_DEVICE_MMC2_2 7
1989 +#define BOOT_DEVICE_SPI 10
1990 +
1991 +#endif /* __ASM_ARCH_SPL_H__ */
1992 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/clock.h u-boot/arch/arm/include/asm/arch-mx6/clock.h
1993 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/clock.h 2014-12-08 22:35:08.000000000 +0100
1994 +++ u-boot/arch/arm/include/asm/arch-mx6/clock.h 2015-01-01 17:34:32.073506203 +0100
1995 @@ -43,10 +43,10 @@
1996 };
1997
1998 enum enet_freq {
1999 - ENET_25MHz,
2000 - ENET_50MHz,
2001 - ENET_100MHz,
2002 - ENET_125MHz,
2003 + ENET_25MHZ,
2004 + ENET_50MHZ,
2005 + ENET_100MHZ,
2006 + ENET_125MHZ,
2007 };
2008
2009 u32 imx_get_uartclk(void);
2010 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/mx6sl_pins.h u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
2011 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-mx6/mx6sl_pins.h 2014-12-08 22:35:08.000000000 +0100
2012 +++ u-boot/arch/arm/include/asm/arch-mx6/mx6sl_pins.h 2015-01-01 17:34:32.073506203 +0100
2013 @@ -53,5 +53,10 @@
2014 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT = IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
2015 MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0),
2016 MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0),
2017 +
2018 + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
2019 +
2020 + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
2021 + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
2022 };
2023 #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
2024 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/mmc.h u-boot/arch/arm/include/asm/arch-rmobile/mmc.h
2025 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/mmc.h 1970-01-01 01:00:00.000000000 +0100
2026 +++ u-boot/arch/arm/include/asm/arch-rmobile/mmc.h 2015-01-01 17:34:32.085506005 +0100
2027 @@ -0,0 +1,14 @@
2028 +/*
2029 + * Renesas SuperH MMCIF driver.
2030 + *
2031 + * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2032 + * Copyright (C) 2014 Renesas Electronics Corporation
2033 + *
2034 + * SPDX-License-Identifier: GPL-2.0
2035 + */
2036 +#ifndef _RMOBILE_MMC_H_
2037 +#define _RMOBILE_MMC_H_
2038 +
2039 +int mmcif_mmc_init(void);
2040 +
2041 +#endif /* _RMOBILE_MMC_H_ */
2042 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7790.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h
2043 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7790.h 2014-12-08 22:35:08.000000000 +0100
2044 +++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7790.h 2015-01-01 17:34:32.085506005 +0100
2045 @@ -15,6 +15,19 @@
2046 #define CONFIG_SYS_I2C_SH_BASE2 0xE6520000
2047 #define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000
2048
2049 +/* Module stop control/status register bits */
2050 +#define MSTP0_BITS 0x00640801
2051 +#define MSTP1_BITS 0xDB6E9BDF
2052 +#define MSTP2_BITS 0x300DA1FC
2053 +#define MSTP3_BITS 0xF08CF831
2054 +#define MSTP4_BITS 0x80000184
2055 +#define MSTP5_BITS 0x44C00046
2056 +#define MSTP7_BITS 0x07F30718
2057 +#define MSTP8_BITS 0x01F0FF84
2058 +#define MSTP9_BITS 0xF5979FCF
2059 +#define MSTP10_BITS 0xFFFEFFE0
2060 +#define MSTP11_BITS 0x00000000
2061 +
2062 #define R8A7790_CUT_ES2X 2
2063 #define IS_R8A7790_ES2() \
2064 (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X)
2065 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7791.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h
2066 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7791.h 2014-12-08 22:35:08.000000000 +0100
2067 +++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7791.h 2015-01-01 17:34:32.089505941 +0100
2068 @@ -51,6 +51,19 @@
2069 #define DBSC3_1_QOS_W15_BASE 0xE67A2F00
2070 #define DBSC3_1_DBADJ2 0xE67A00C8
2071
2072 +/* Module stop control/status register bits */
2073 +#define MSTP0_BITS 0x00640801
2074 +#define MSTP1_BITS 0x9B6C9B5A
2075 +#define MSTP2_BITS 0x100D21FC
2076 +#define MSTP3_BITS 0xF08CD810
2077 +#define MSTP4_BITS 0x800001C4
2078 +#define MSTP5_BITS 0x44C00046
2079 +#define MSTP7_BITS 0x05BFE618
2080 +#define MSTP8_BITS 0x40C0FE85
2081 +#define MSTP9_BITS 0xFF979FFF
2082 +#define MSTP10_BITS 0xFFFEFFE0
2083 +#define MSTP11_BITS 0x000001C0
2084 +
2085 #define R8A7791_CUT_ES2X 2
2086 #define IS_R8A7791_ES2() \
2087 (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)
2088 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7793.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7793.h
2089 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7793.h 2014-12-08 22:35:08.000000000 +0100
2090 +++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7793.h 2015-01-01 17:34:32.089505941 +0100
2091 @@ -56,6 +56,20 @@
2092 /*
2093 * R8A7793 I/O Product Information
2094 */
2095 +
2096 +/* Module stop control/status register bits */
2097 +#define MSTP0_BITS 0x00640801
2098 +#define MSTP1_BITS 0x9B6C9B5A
2099 +#define MSTP2_BITS 0x100D21FC
2100 +#define MSTP3_BITS 0xF08CD810
2101 +#define MSTP4_BITS 0x800001C4
2102 +#define MSTP5_BITS 0x44C00046
2103 +#define MSTP7_BITS 0x05BFE618
2104 +#define MSTP8_BITS 0x40C0FE85
2105 +#define MSTP9_BITS 0xFF979FFF
2106 +#define MSTP10_BITS 0xFFFEFFE0
2107 +#define MSTP11_BITS 0x000001C0
2108 +
2109 #define R8A7793_CUT_ES2X 2
2110 #define IS_R8A7793_ES2() \
2111 (rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X)
2112 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7794.h u-boot/arch/arm/include/asm/arch-rmobile/r8a7794.h
2113 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/r8a7794.h 2014-12-08 22:35:08.000000000 +0100
2114 +++ u-boot/arch/arm/include/asm/arch-rmobile/r8a7794.h 2015-01-01 17:34:32.089505941 +0100
2115 @@ -14,4 +14,17 @@
2116 /* SH-I2C */
2117 #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
2118
2119 +/* Module stop control/status register bits */
2120 +#define MSTP0_BITS 0x00440801
2121 +#define MSTP1_BITS 0x936899DA
2122 +#define MSTP2_BITS 0x100D21FC
2123 +#define MSTP3_BITS 0xE084D810
2124 +#define MSTP4_BITS 0x800001C4
2125 +#define MSTP5_BITS 0x40C00044
2126 +#define MSTP7_BITS 0x013FE618
2127 +#define MSTP8_BITS 0x40803C05
2128 +#define MSTP9_BITS 0xFB879FEE
2129 +#define MSTP10_BITS 0xFFFEFFE0
2130 +#define MSTP11_BITS 0x000001C0
2131 +
2132 #endif /* __ASM_ARCH_R8A7794_H */
2133 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-base.h u-boot/arch/arm/include/asm/arch-rmobile/rcar-base.h
2134 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-base.h 2014-12-08 22:35:08.000000000 +0100
2135 +++ u-boot/arch/arm/include/asm/arch-rmobile/rcar-base.h 2015-01-01 17:34:32.089505941 +0100
2136 @@ -29,6 +29,45 @@
2137 #define SCIF4_BASE 0xE6EE0000
2138 #define SCIF5_BASE 0xE6EE8000
2139
2140 +/* Module stop status register */
2141 +#define MSTPSR0 0xE6150030
2142 +#define MSTPSR1 0xE6150038
2143 +#define MSTPSR2 0xE6150040
2144 +#define MSTPSR3 0xE6150048
2145 +#define MSTPSR4 0xE615004C
2146 +#define MSTPSR5 0xE615003C
2147 +#define MSTPSR7 0xE61501C4
2148 +#define MSTPSR8 0xE61509A0
2149 +#define MSTPSR9 0xE61509A4
2150 +#define MSTPSR10 0xE61509A8
2151 +#define MSTPSR11 0xE61509AC
2152 +
2153 +/* Realtime module stop control register */
2154 +#define RMSTPCR0 0xE6150110
2155 +#define RMSTPCR1 0xE6150114
2156 +#define RMSTPCR2 0xE6150118
2157 +#define RMSTPCR3 0xE615011C
2158 +#define RMSTPCR4 0xE6150120
2159 +#define RMSTPCR5 0xE6150124
2160 +#define RMSTPCR7 0xE615012C
2161 +#define RMSTPCR8 0xE6150980
2162 +#define RMSTPCR9 0xE6150984
2163 +#define RMSTPCR10 0xE6150988
2164 +#define RMSTPCR11 0xE615098C
2165 +
2166 +/* System module stop control register */
2167 +#define SMSTPCR0 0xE6150130
2168 +#define SMSTPCR1 0xE6150134
2169 +#define SMSTPCR2 0xE6150138
2170 +#define SMSTPCR3 0xE615013C
2171 +#define SMSTPCR4 0xE6150140
2172 +#define SMSTPCR5 0xE6150144
2173 +#define SMSTPCR7 0xE615014C
2174 +#define SMSTPCR8 0xE6150990
2175 +#define SMSTPCR9 0xE6150994
2176 +#define SMSTPCR10 0xE6150998
2177 +#define SMSTPCR11 0xE615099C
2178 +
2179 /*
2180 * SH-I2C
2181 * Ch2 and ch3 are different address. These are defined
2182 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-mstp.h u-boot/arch/arm/include/asm/arch-rmobile/rcar-mstp.h
2183 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-rmobile/rcar-mstp.h 1970-01-01 01:00:00.000000000 +0100
2184 +++ u-boot/arch/arm/include/asm/arch-rmobile/rcar-mstp.h 2015-01-01 17:34:32.089505941 +0100
2185 @@ -0,0 +1,109 @@
2186 +/*
2187 + * arch/arm/include/asm/arch-rmobile/rcar-mstp.h
2188 + *
2189 + * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2190 + * Copyright (C) 2013, 2014 Renesas Electronics Corporation
2191 + *
2192 + * SPDX-License-Identifier: GPL-2.0
2193 + */
2194 +
2195 +#ifndef __ASM_ARCH_RCAR_MSTP_H
2196 +#define __ASM_ARCH_RCAR_MSTP_H
2197 +
2198 +#define mstp_setbits(type, addr, saddr, set) \
2199 + out_##type((saddr), in_##type(addr) | (set))
2200 +#define mstp_clrbits(type, addr, saddr, clear) \
2201 + out_##type((saddr), in_##type(addr) & ~(clear))
2202 +#define mstp_setclrbits(type, addr, set, clear) \
2203 + out_##type((addr), (in_##type(addr) | (set)) & ~(clear))
2204 +#define mstp_setbits_le32(addr, saddr, set) \
2205 + mstp_setbits(le32, addr, saddr, set)
2206 +#define mstp_clrbits_le32(addr, saddr, clear) \
2207 + mstp_clrbits(le32, addr, saddr, clear)
2208 +#define mstp_setclrbits_le32(addr, set, clear) \
2209 + mstp_setclrbits(le32, addr, set, clear)
2210 +
2211 +#ifndef CONFIG_SMSTP0_ENA
2212 +#define CONFIG_SMSTP0_ENA 0x00
2213 +#endif
2214 +#ifndef CONFIG_SMSTP1_ENA
2215 +#define CONFIG_SMSTP1_ENA 0x00
2216 +#endif
2217 +#ifndef CONFIG_SMSTP2_ENA
2218 +#define CONFIG_SMSTP2_ENA 0x00
2219 +#endif
2220 +#ifndef CONFIG_SMSTP3_ENA
2221 +#define CONFIG_SMSTP3_ENA 0x00
2222 +#endif
2223 +#ifndef CONFIG_SMSTP4_ENA
2224 +#define CONFIG_SMSTP4_ENA 0x00
2225 +#endif
2226 +#ifndef CONFIG_SMSTP5_ENA
2227 +#define CONFIG_SMSTP5_ENA 0x00
2228 +#endif
2229 +#ifndef CONFIG_SMSTP6_ENA
2230 +#define CONFIG_SMSTP6_ENA 0x00
2231 +#endif
2232 +#ifndef CONFIG_SMSTP7_ENA
2233 +#define CONFIG_SMSTP7_ENA 0x00
2234 +#endif
2235 +#ifndef CONFIG_SMSTP8_ENA
2236 +#define CONFIG_SMSTP8_ENA 0x00
2237 +#endif
2238 +#ifndef CONFIG_SMSTP9_ENA
2239 +#define CONFIG_SMSTP9_ENA 0x00
2240 +#endif
2241 +#ifndef CONFIG_SMSTP10_ENA
2242 +#define CONFIG_SMSTP10_ENA 0x00
2243 +#endif
2244 +#ifndef CONFIG_SMSTP11_ENA
2245 +#define CONFIG_SMSTP11_ENA 0x00
2246 +#endif
2247 +
2248 +#ifndef CONFIG_RMSTP0_ENA
2249 +#define CONFIG_RMSTP0_ENA 0x00
2250 +#endif
2251 +#ifndef CONFIG_RMSTP1_ENA
2252 +#define CONFIG_RMSTP1_ENA 0x00
2253 +#endif
2254 +#ifndef CONFIG_RMSTP2_ENA
2255 +#define CONFIG_RMSTP2_ENA 0x00
2256 +#endif
2257 +#ifndef CONFIG_RMSTP3_ENA
2258 +#define CONFIG_RMSTP3_ENA 0x00
2259 +#endif
2260 +#ifndef CONFIG_RMSTP4_ENA
2261 +#define CONFIG_RMSTP4_ENA 0x00
2262 +#endif
2263 +#ifndef CONFIG_RMSTP5_ENA
2264 +#define CONFIG_RMSTP5_ENA 0x00
2265 +#endif
2266 +#ifndef CONFIG_RMSTP6_ENA
2267 +#define CONFIG_RMSTP6_ENA 0x00
2268 +#endif
2269 +#ifndef CONFIG_RMSTP7_ENA
2270 +#define CONFIG_RMSTP7_ENA 0x00
2271 +#endif
2272 +#ifndef CONFIG_RMSTP8_ENA
2273 +#define CONFIG_RMSTP8_ENA 0x00
2274 +#endif
2275 +#ifndef CONFIG_RMSTP9_ENA
2276 +#define CONFIG_RMSTP9_ENA 0x00
2277 +#endif
2278 +#ifndef CONFIG_RMSTP10_ENA
2279 +#define CONFIG_RMSTP10_ENA 0x00
2280 +#endif
2281 +#ifndef CONFIG_RMSTP11_ENA
2282 +#define CONFIG_RMSTP11_ENA 0x00
2283 +#endif
2284 +
2285 +struct mstp_ctl {
2286 + u32 s_addr;
2287 + u32 s_dis;
2288 + u32 s_ena;
2289 + u32 r_addr;
2290 + u32 r_dis;
2291 + u32 r_ena;
2292 +};
2293 +
2294 +#endif /* __ASM_ARCH_RCAR_MSTP_H */
2295 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/clock_manager.h u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h
2296 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/clock_manager.h 2014-12-08 22:35:08.000000000 +0100
2297 +++ u-boot/arch/arm/include/asm/arch-socfpga/clock_manager.h 2015-01-01 17:34:32.089505941 +0100
2298 @@ -14,6 +14,7 @@
2299 unsigned int cm_get_l4_sp_clk_hz(void);
2300 unsigned int cm_get_mmc_controller_clk_hz(void);
2301 unsigned int cm_get_qspi_controller_clk_hz(void);
2302 +unsigned int cm_get_spi_controller_clk_hz(void);
2303 #endif
2304
2305 typedef struct {
2306 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/freeze_controller.h u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h
2307 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/freeze_controller.h 2014-12-08 22:35:08.000000000 +0100
2308 +++ u-boot/arch/arm/include/asm/arch-socfpga/freeze_controller.h 2015-01-01 17:34:32.089505941 +0100
2309 @@ -42,7 +42,6 @@
2310 #define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
2311 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
2312 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
2313 -#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
2314
2315 void sys_mgr_frzctrl_freeze_req(void);
2316 void sys_mgr_frzctrl_thaw_req(void);
2317 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/scan_manager.h u-boot/arch/arm/include/asm/arch-socfpga/scan_manager.h
2318 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-socfpga/scan_manager.h 2014-12-08 22:35:08.000000000 +0100
2319 +++ u-boot/arch/arm/include/asm/arch-socfpga/scan_manager.h 2015-01-01 17:34:32.089505941 +0100
2320 @@ -13,6 +13,7 @@
2321 u32 padding[2];
2322 u32 fifo_single_byte;
2323 u32 fifo_double_byte;
2324 + u32 fifo_triple_byte;
2325 u32 fifo_quad_byte;
2326 };
2327
2328 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/gpio.h u-boot/arch/arm/include/asm/arch-stv0991/gpio.h
2329 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/gpio.h 1970-01-01 01:00:00.000000000 +0100
2330 +++ u-boot/arch/arm/include/asm/arch-stv0991/gpio.h 2015-01-01 17:34:32.093505875 +0100
2331 @@ -0,0 +1,22 @@
2332 +/*
2333 + * (C) Copyright 2014
2334 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
2335 + *
2336 + * SPDX-License-Identifier: GPL-2.0+
2337 + */
2338 +
2339 +#ifndef __ASM_ARCH_STV0991_GPIO_H
2340 +#define __ASM_ARCH_STV0991_GPIO_H
2341 +
2342 +enum gpio_direction {
2343 + GPIO_DIRECTION_IN,
2344 + GPIO_DIRECTION_OUT,
2345 +};
2346 +
2347 +struct gpio_regs {
2348 + u32 data; /* offset 0x0 */
2349 + u32 reserved[0xff]; /* 0x4--0x3fc */
2350 + u32 dir; /* offset 0x400 */
2351 +};
2352 +
2353 +#endif /* __ASM_ARCH_STV0991_GPIO_H */
2354 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/hardware.h u-boot/arch/arm/include/asm/arch-stv0991/hardware.h
2355 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/hardware.h 1970-01-01 01:00:00.000000000 +0100
2356 +++ u-boot/arch/arm/include/asm/arch-stv0991/hardware.h 2015-01-01 17:34:32.093505875 +0100
2357 @@ -0,0 +1,73 @@
2358 +/*
2359 + * (C) Copyright 2014
2360 + * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com>
2361 + *
2362 + * SPDX-License-Identifier: GPL-2.0+
2363 + */
2364 +
2365 +#ifndef _ASM_ARCH_HARDWARE_H
2366 +#define _ASM_ARCH_HARDWARE_H
2367 +
2368 +/* STV0991 */
2369 +#define SRAM0_BASE_ADDR 0x00000000UL
2370 +#define SRAM1_BASE_ADDR 0x00068000UL
2371 +#define SRAM2_BASE_ADDR 0x000D0000UL
2372 +#define SRAM3_BASE_ADDR 0x00138000UL
2373 +#define CFS_SRAM0_BASE_ADDR 0x00198000UL
2374 +#define CFS_SRAM1_BASE_ADDR 0x001B8000UL
2375 +#define FAST_SRAM_BASE_ADDR 0x001D8000UL
2376 +#define FLASH_BASE_ADDR 0x40000000UL
2377 +#define PL310_BASE_ADDR 0x70000000UL
2378 +#define HSAXIM_BASE_ADDR 0x70100000UL
2379 +#define IMGSS_BASE_ADDR 0x70200000UL
2380 +#define ADC_BASE_ADDR 0x80000000UL
2381 +#define GPIOA_BASE_ADDR 0x80001000UL
2382 +#define GPIOB_BASE_ADDR 0x80002000UL
2383 +#define GPIOC_BASE_ADDR 0x80003000UL
2384 +#define HDM_BASE_ADDR 0x80004000UL
2385 +#define THSENS_BASE_ADDR 0x80200000UL
2386 +#define GPTIMER2_BASE_ADDR 0x80201000UL
2387 +#define GPTIMER1_BASE_ADDR 0x80202000UL
2388 +#define QSPI_BASE_ADDR 0x80203000UL
2389 +#define CGU_BASE_ADDR 0x80204000UL
2390 +#define CREG_BASE_ADDR 0x80205000UL
2391 +#define PEC_BASE_ADDR 0x80206000UL
2392 +#define WDRU_BASE_ADDR 0x80207000UL
2393 +#define BSEC_BASE_ADDR 0x80208000UL
2394 +#define DAP_ROM_BASE_ADDR 0x80210000UL
2395 +#define SOC_CTI_BASE_ADDR 0x80211000UL
2396 +#define TPIU_BASE_ADDR 0x80212000UL
2397 +#define TMC_ETF_BASE_ADDR 0x80213000UL
2398 +#define R4_ETM_BASE_ADDR 0x80214000UL
2399 +#define R4_CTI_BASE_ADDR 0x80215000UL
2400 +#define R4_DBG_BASE_ADDR 0x80216000UL
2401 +#define GMAC_BASE_ADDR 0x80300000UL
2402 +#define RNSS_BASE_ADDR 0x80302000UL
2403 +#define CRYP_BASE_ADDR 0x80303000UL
2404 +#define HASH_BASE_ADDR 0x80304000UL
2405 +#define GPDMA_BASE_ADDR 0x80305000UL
2406 +#define ISA_BASE_ADDR 0x8032A000UL
2407 +#define HCI_BASE_ADDR 0x80400000UL
2408 +#define I2C1_BASE_ADDR 0x80401000UL
2409 +#define I2C2_BASE_ADDR 0x80402000UL
2410 +#define SAI_BASE_ADDR 0x80403000UL
2411 +#define USI_BASE_ADDR 0x80404000UL
2412 +#define SPI1_BASE_ADDR 0x80405000UL
2413 +#define UART_BASE_ADDR 0x80406000UL
2414 +#define SPI2_BASE_ADDR 0x80500000UL
2415 +#define CAN_BASE_ADDR 0x80501000UL
2416 +#define USART1_BASE_ADDR 0x80502000UL
2417 +#define USART2_BASE_ADDR 0x80503000UL
2418 +#define USART3_BASE_ADDR 0x80504000UL
2419 +#define USART4_BASE_ADDR 0x80505000UL
2420 +#define USART5_BASE_ADDR 0x80506000UL
2421 +#define USART6_BASE_ADDR 0x80507000UL
2422 +#define SDI2_BASE_ADDR 0x80600000UL
2423 +#define SDI1_BASE_ADDR 0x80601000UL
2424 +#define VICA_BASE_ADDR 0x81000000UL
2425 +#define VICB_BASE_ADDR 0x81001000UL
2426 +#define STM_CHANNELS_BASE_ADDR 0x81100000UL
2427 +#define STM_BASE_ADDR 0x81110000UL
2428 +#define SROM_BASE_ADDR 0xFFFF0000UL
2429 +
2430 +#endif /* _ASM_ARCH_HARDWARE_H */
2431 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h
2432 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h 1970-01-01 01:00:00.000000000 +0100
2433 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_cgu.h 2015-01-01 17:34:32.093505875 +0100
2434 @@ -0,0 +1,116 @@
2435 +/*
2436 + * (C) Copyright 2014
2437 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
2438 + *
2439 + * SPDX-License-Identifier: GPL-2.0+
2440 + */
2441 +
2442 +#ifndef _STV0991_CGU_H
2443 +#define _STV0991_CGU_H
2444 +
2445 +struct stv0991_cgu_regs {
2446 + u32 cpu_freq; /* offset 0x0 */
2447 + u32 icn2_freq; /* offset 0x4 */
2448 + u32 dma_freq; /* offset 0x8 */
2449 + u32 isp_freq; /* offset 0xc */
2450 + u32 h264_freq; /* offset 0x10 */
2451 + u32 osif_freq; /* offset 0x14 */
2452 + u32 ren_freq; /* offset 0x18 */
2453 + u32 tim_freq; /* offset 0x1c */
2454 + u32 sai_freq; /* offset 0x20 */
2455 + u32 eth_freq; /* offset 0x24 */
2456 + u32 i2c_freq; /* offset 0x28 */
2457 + u32 spi_freq; /* offset 0x2c */
2458 + u32 uart_freq; /* offset 0x30 */
2459 + u32 qspi_freq; /* offset 0x34 */
2460 + u32 sdio_freq; /* offset 0x38 */
2461 + u32 usi_freq; /* offset 0x3c */
2462 + u32 can_line_freq; /* offset 0x40 */
2463 + u32 debug_freq; /* offset 0x44 */
2464 + u32 trace_freq; /* offset 0x48 */
2465 + u32 stm_freq; /* offset 0x4c */
2466 + u32 eth_ctrl; /* offset 0x50 */
2467 + u32 reserved[3]; /* offset 0x54 */
2468 + u32 osc_ctrl; /* offset 0x60 */
2469 + u32 pll1_ctrl; /* offset 0x64 */
2470 + u32 pll1_freq; /* offset 0x68 */
2471 + u32 pll1_fract; /* offset 0x6c */
2472 + u32 pll1_spread; /* offset 0x70 */
2473 + u32 pll1_status; /* offset 0x74 */
2474 + u32 pll2_ctrl; /* offset 0x78 */
2475 + u32 pll2_freq; /* offset 0x7c */
2476 + u32 pll2_fract; /* offset 0x80 */
2477 + u32 pll2_spread; /* offset 0x84 */
2478 + u32 pll2_status; /* offset 0x88 */
2479 + u32 cgu_enable_1; /* offset 0x8c */
2480 + u32 cgu_enable_2; /* offset 0x90 */
2481 + u32 cgu_isp_pulse; /* offset 0x94 */
2482 + u32 cgu_h264_pulse; /* offset 0x98 */
2483 + u32 cgu_osif_pulse; /* offset 0x9c */
2484 + u32 cgu_ren_pulse; /* offset 0xa0 */
2485 +
2486 +};
2487 +
2488 +/* CGU Timer */
2489 +#define CLK_TMR_OSC 0
2490 +#define CLK_TMR_MCLK 1
2491 +#define CLK_TMR_PLL1 2
2492 +#define CLK_TMR_PLL2 3
2493 +#define MDIV_SHIFT_TMR 3
2494 +#define DIV_SHIFT_TMR 6
2495 +
2496 +#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \
2497 + | 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
2498 +
2499 +/* Clock Enable/Disable */
2500 +
2501 +#define TIMER1_CLK_EN (1 << 15)
2502 +
2503 +/* CGU Uart config */
2504 +#define CLK_UART_MCLK 0
2505 +#define CLK_UART_PLL1 1
2506 +#define CLK_UART_PLL2 2
2507 +
2508 +#define MDIV_SHIFT_UART 3
2509 +#define DIV_SHIFT_UART 6
2510 +
2511 +#define UART_CLK_CFG (4 << DIV_SHIFT_UART \
2512 + | 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
2513 +
2514 +/* CGU Ethernet clock config */
2515 +#define CLK_ETH_MCLK 0
2516 +#define CLK_ETH_PLL1 1
2517 +#define CLK_ETH_PLL2 2
2518 +
2519 +#define MDIV_SHIFT_ETH 3
2520 +#define DIV_SHIFT_ETH 6
2521 +#define DIV_ETH_125 9
2522 +#define DIV_ETH_50 12
2523 +#define DIV_ETH_P2P 15
2524 +
2525 +#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
2526 + | 1 << DIV_ETH_125 \
2527 + | 0 << DIV_SHIFT_ETH \
2528 + | 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
2529 + /* CGU Ethernet control */
2530 +
2531 +#define ETH_CLK_TX_EXT_PHY 0
2532 +#define ETH_CLK_TX_125M 1
2533 +#define ETH_CLK_TX_25M 2
2534 +#define ETH_CLK_TX_2M5 3
2535 +#define ETH_CLK_TX_DIS 7
2536 +
2537 +#define ETH_CLK_RX_EXT_PHY 0
2538 +#define ETH_CLK_RX_25M 1
2539 +#define ETH_CLK_RX_2M5 2
2540 +#define ETH_CLK_RX_DIS 3
2541 +#define RX_CLK_SHIFT 3
2542 +#define ETH_CLK_MASK ~(0x1F)
2543 +
2544 +#define ETH_PHY_MODE_GMII 0
2545 +#define ETH_PHY_MODE_RMII 1
2546 +#define ETH_PHY_CLK_DIS 1
2547 +
2548 +#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
2549 + | ETH_CLK_TX_EXT_PHY)
2550 +#endif
2551 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_creg.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_creg.h
2552 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_creg.h 1970-01-01 01:00:00.000000000 +0100
2553 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_creg.h 2015-01-01 17:34:32.093505875 +0100
2554 @@ -0,0 +1,95 @@
2555 +/*
2556 + * (C) Copyright 2014
2557 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
2558 + *
2559 + * SPDX-License-Identifier: GPL-2.0+
2560 + */
2561 +
2562 +#ifndef _STV0991_CREG_H
2563 +#define _STV0991_CREG_H
2564 +
2565 +struct stv0991_creg {
2566 + u32 version; /* offset 0x0 */
2567 + u32 hdpctl; /* offset 0x4 */
2568 + u32 hdpval; /* offset 0x8 */
2569 + u32 hdpgposet; /* offset 0xc */
2570 + u32 hdpgpoclr; /* offset 0x10 */
2571 + u32 hdpgpoval; /* offset 0x14 */
2572 + u32 stm_mux; /* offset 0x18 */
2573 + u32 sysctrl_1; /* offset 0x1c */
2574 + u32 sysctrl_2; /* offset 0x20 */
2575 + u32 sysctrl_3; /* offset 0x24 */
2576 + u32 sysctrl_4; /* offset 0x28 */
2577 + u32 reserved_1[0x35]; /* offset 0x2C-0xFC */
2578 + u32 mux1; /* offset 0x100 */
2579 + u32 mux2; /* offset 0x104 */
2580 + u32 mux3; /* offset 0x108 */
2581 + u32 mux4; /* offset 0x10c */
2582 + u32 mux5; /* offset 0x110 */
2583 + u32 mux6; /* offset 0x114 */
2584 + u32 mux7; /* offset 0x118 */
2585 + u32 mux8; /* offset 0x11c */
2586 + u32 mux9; /* offset 0x120 */
2587 + u32 mux10; /* offset 0x124 */
2588 + u32 mux11; /* offset 0x128 */
2589 + u32 mux12; /* offset 0x12c */
2590 + u32 mux13; /* offset 0x130 */
2591 + u32 reserved_2[0x33]; /* offset 0x134-0x1FC */
2592 + u32 cfg_pad1; /* offset 0x200 */
2593 + u32 cfg_pad2; /* offset 0x204 */
2594 + u32 cfg_pad3; /* offset 0x208 */
2595 + u32 cfg_pad4; /* offset 0x20c */
2596 + u32 cfg_pad5; /* offset 0x210 */
2597 + u32 cfg_pad6; /* offset 0x214 */
2598 + u32 cfg_pad7; /* offset 0x218 */
2599 + u32 reserved_3[0x39]; /* offset 0x21C-0x2FC */
2600 + u32 vdd_pad1; /* offset 0x300 */
2601 + u32 vdd_pad2; /* offset 0x304 */
2602 + u32 reserved_4[0x3e]; /* offset 0x308-0x3FC */
2603 + u32 vdd_comp1; /* offset 0x400 */
2604 +};
2605 +
2606 +/* CREG MUX 12 register */
2607 +#define GPIOC_30_MUX_SHIFT 24
2608 +#define GPIOC_30_MUX_MASK ~(1 << GPIOC_30_MUX_SHIFT)
2609 +#define CFG_GPIOC_30_UART_TX (1 << GPIOC_30_MUX_SHIFT)
2610 +
2611 +#define GPIOC_31_MUX_SHIFT 28
2612 +#define GPIOC_31_MUX_MASK ~(1 << GPIOC_31_MUX_SHIFT)
2613 +#define CFG_GPIOC_31_UART_RX (1 << GPIOC_31_MUX_SHIFT)
2614 +
2615 +/* CREG MUX 7 register */
2616 +#define GPIOB_16_MUX_SHIFT 0
2617 +#define GPIOB_16_MUX_MASK ~(1 << GPIOB_16_MUX_SHIFT)
2618 +#define CFG_GPIOB_16_UART_TX (1 << GPIOB_16_MUX_SHIFT)
2619 +
2620 +#define GPIOB_17_MUX_SHIFT 4
2621 +#define GPIOB_17_MUX_MASK ~(1 << GPIOB_17_MUX_SHIFT)
2622 +#define CFG_GPIOB_17_UART_RX (1 << GPIOB_17_MUX_SHIFT)
2623 +
2624 +/* CREG CFG_PAD6 register */
2625 +
2626 +#define GPIOC_31_MODE_SHIFT 30
2627 +#define GPIOC_31_MODE_MASK ~(1 << GPIOC_31_MODE_SHIFT)
2628 +#define CFG_GPIOC_31_MODE_OD (0 << GPIOC_31_MODE_SHIFT)
2629 +#define CFG_GPIOC_31_MODE_PP (1 << GPIOC_31_MODE_SHIFT)
2630 +
2631 +#define GPIOC_30_MODE_SHIFT 28
2632 +#define GPIOC_30_MODE_MASK ~(1 << GPIOC_30_MODE_SHIFT)
2633 +#define CFG_GPIOC_30_MODE_LOW (0 << GPIOC_30_MODE_SHIFT)
2634 +#define CFG_GPIOC_30_MODE_HIGH (1 << GPIOC_30_MODE_SHIFT)
2635 +
2636 +/* CREG Ethernet pad config */
2637 +
2638 +#define VDD_ETH_PS_1V8 0
2639 +#define VDD_ETH_PS_2V5 2
2640 +#define VDD_ETH_PS_3V3 3
2641 +#define VDD_ETH_PS_MASK 0x3
2642 +
2643 +#define VDD_ETH_PS_SHIFT 12
2644 +#define ETH_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_PS_SHIFT)
2645 +
2646 +#define VDD_ETH_M_PS_SHIFT 28
2647 +#define ETH_M_VDD_CFG (VDD_ETH_PS_1V8 << VDD_ETH_M_PS_SHIFT)
2648 +
2649 +#endif
2650 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_defs.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_defs.h
2651 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_defs.h 1970-01-01 01:00:00.000000000 +0100
2652 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_defs.h 2015-01-01 17:34:32.093505875 +0100
2653 @@ -0,0 +1,16 @@
2654 +/*
2655 + * (C) Copyright 2014
2656 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
2657 + *
2658 + * SPDX-License-Identifier: GPL-2.0+
2659 + */
2660 +
2661 +#ifndef __STV0991_DEFS_H__
2662 +#define __STV0991_DEFS_H__
2663 +#include <asm/arch/stv0991_periph.h>
2664 +
2665 +extern int stv0991_pinmux_config(enum periph_id);
2666 +extern int clock_setup(enum periph_clock);
2667 +
2668 +#endif
2669 +
2670 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h
2671 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h 1970-01-01 01:00:00.000000000 +0100
2672 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_gpt.h 2015-01-01 17:34:32.093505875 +0100
2673 @@ -0,0 +1,43 @@
2674 +/*
2675 + * (C) Copyright 2014
2676 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
2677 + *
2678 + * SPDX-License-Identifier: GPL-2.0+
2679 + */
2680 +
2681 +#ifndef _STV0991_GPT_H
2682 +#define _STV0991_GPT_H
2683 +
2684 +#include <asm/arch-stv0991/hardware.h>
2685 +
2686 +struct gpt_regs {
2687 + u32 cr1;
2688 + u32 cr2;
2689 + u32 reserved_1;
2690 + u32 dier; /* dma_int_en */
2691 + u32 sr; /* status reg */
2692 + u32 egr; /* event gen */
2693 + u32 reserved_2[3]; /* offset 0x18--0x20*/
2694 + u32 cnt;
2695 + u32 psc;
2696 + u32 arr;
2697 +};
2698 +
2699 +struct gpt_regs *const gpt1_regs_ptr =
2700 + (struct gpt_regs *) GPTIMER1_BASE_ADDR;
2701 +
2702 +/* Timer control1 register */
2703 +#define GPT_CR1_CEN 0x0001
2704 +#define GPT_MODE_AUTO_RELOAD (1 << 7)
2705 +
2706 +/* Timer prescalar reg */
2707 +#define GPT_PRESCALER_128 0x128
2708 +
2709 +/* Auto reload register for free running config */
2710 +#define GPT_FREE_RUNNING 0xFFFF
2711 +
2712 +/* Timer, HZ specific defines */
2713 +#define CONFIG_STV0991_HZ 1000
2714 +#define CONFIG_STV0991_HZ_CLOCK (27*1000*1000)/GPT_PRESCALER_128
2715 +
2716 +#endif
2717 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_periph.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_periph.h
2718 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_periph.h 1970-01-01 01:00:00.000000000 +0100
2719 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_periph.h 2015-01-01 17:34:32.093505875 +0100
2720 @@ -0,0 +1,44 @@
2721 +/*
2722 + * (C) Copyright 2014
2723 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
2724 + *
2725 + * SPDX-License-Identifier: GPL-2.0+
2726 + */
2727 +
2728 +#ifndef __ASM_ARM_ARCH_PERIPH_H
2729 +#define __ASM_ARM_ARCH_PERIPH_H
2730 +
2731 +/*
2732 + * Peripherals required for pinmux configuration. List will
2733 + * grow with support for more devices getting added.
2734 + * Numbering based on interrupt table.
2735 + *
2736 + */
2737 +enum periph_id {
2738 + UART_GPIOC_30_31 = 0,
2739 + UART_GPIOB_16_17,
2740 + ETH_GPIOB_10_31_C_0_4,
2741 + PERIPH_ID_I2C0,
2742 + PERIPH_ID_I2C1,
2743 + PERIPH_ID_I2C2,
2744 + PERIPH_ID_I2C3,
2745 + PERIPH_ID_I2C4,
2746 + PERIPH_ID_I2C5,
2747 + PERIPH_ID_I2C6,
2748 + PERIPH_ID_I2C7,
2749 + PERIPH_ID_SPI0,
2750 + PERIPH_ID_SPI1,
2751 + PERIPH_ID_SPI2,
2752 + PERIPH_ID_SDMMC0,
2753 + PERIPH_ID_SDMMC1,
2754 + PERIPH_ID_SDMMC2,
2755 + PERIPH_ID_SDMMC3,
2756 + PERIPH_ID_I2S1,
2757 +};
2758 +
2759 +enum periph_clock {
2760 + UART_CLOCK_CFG = 0,
2761 + ETH_CLOCK_CFG,
2762 +};
2763 +
2764 +#endif /* __ASM_ARM_ARCH_PERIPH_H */
2765 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h u-boot/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h
2766 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h 1970-01-01 01:00:00.000000000 +0100
2767 +++ u-boot/arch/arm/include/asm/arch-stv0991/stv0991_wdru.h 2015-01-01 17:34:32.093505875 +0100
2768 @@ -0,0 +1,28 @@
2769 +/*
2770 + * (C) Copyright 2014
2771 + * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com
2772 + *
2773 + * SPDX-License-Identifier: GPL-2.0+
2774 + */
2775 +
2776 +#ifndef _STV0991_WD_RST_H
2777 +#define _STV0991_WD_RST_H
2778 +#include <asm/arch-stv0991/hardware.h>
2779 +
2780 +struct stv0991_wd_ru {
2781 + u32 wdru_config;
2782 + u32 wdru_ctrl1;
2783 + u32 wdru_ctrl2;
2784 + u32 wdru_tim;
2785 + u32 wdru_count;
2786 + u32 wdru_stat;
2787 + u32 wdru_wrlock;
2788 +};
2789 +
2790 +struct stv0991_wd_ru *const stv0991_wd_ru_ptr = \
2791 + (struct stv0991_wd_ru *)WDRU_BASE_ADDR;
2792 +
2793 +/* Watchdog control register */
2794 +#define WDRU_RST_SYS 0x1
2795 +
2796 +#endif
2797 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-tegra/tegra_i2c.h u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h
2798 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-tegra/tegra_i2c.h 2014-12-08 22:35:08.000000000 +0100
2799 +++ u-boot/arch/arm/include/asm/arch-tegra/tegra_i2c.h 2015-01-01 17:34:32.097505809 +0100
2800 @@ -167,6 +167,6 @@
2801 *
2802 * @return number of bus, or -1 if there is no DVC active
2803 */
2804 -int tegra_i2c_get_dvc_bus_num(void);
2805 +int tegra_i2c_get_dvc_bus(struct udevice **busp);
2806
2807 #endif /* _TEGRA_I2C_H_ */
2808 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/arch-vf610/imx-regs.h u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h
2809 --- u-boot-2015.01-rc3/arch/arm/include/asm/arch-vf610/imx-regs.h 2014-12-08 22:35:08.000000000 +0100
2810 +++ u-boot/arch/arm/include/asm/arch-vf610/imx-regs.h 2015-01-01 17:34:32.109505612 +0100
2811 @@ -256,6 +256,14 @@
2812 #define DDRMC_CR161_TODTH_RD(v) (((v) & 0xf) << 8)
2813 #define DDRMC_CR161_TODTH_WR(v) ((v) & 0xf)
2814
2815 +/* System Reset Controller (SRC) */
2816 +#define SRC_SRSR_SW_RST (0x1 << 18)
2817 +#define SRC_SRSR_RESETB (0x1 << 7)
2818 +#define SRC_SRSR_JTAG_RST (0x1 << 5)
2819 +#define SRC_SRSR_WDOG_M4 (0x1 << 4)
2820 +#define SRC_SRSR_WDOG_A5 (0x1 << 3)
2821 +#define SRC_SRSR_POR_RST (0x1 << 0)
2822 +
2823 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
2824 #include <asm/types.h>
2825
2826 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/kona-common/clk.h u-boot/arch/arm/include/asm/kona-common/clk.h
2827 --- u-boot-2015.01-rc3/arch/arm/include/asm/kona-common/clk.h 2014-12-08 22:35:08.000000000 +0100
2828 +++ u-boot/arch/arm/include/asm/kona-common/clk.h 2015-01-01 17:34:32.113505547 +0100
2829 @@ -25,5 +25,6 @@
2830 struct clk *clk_get_parent(struct clk *clk);
2831 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
2832 int clk_bsc_enable(void *base);
2833 +int clk_usb_otg_enable(void *base);
2834
2835 #endif
2836 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/pcie_layerscape.h u-boot/arch/arm/include/asm/pcie_layerscape.h
2837 --- u-boot-2015.01-rc3/arch/arm/include/asm/pcie_layerscape.h 1970-01-01 01:00:00.000000000 +0100
2838 +++ u-boot/arch/arm/include/asm/pcie_layerscape.h 2015-01-01 17:34:32.125505350 +0100
2839 @@ -0,0 +1,13 @@
2840 +/*
2841 + * Copyright 2014 Freescale Semiconductor, Inc.
2842 + *
2843 + * SPDX-License-Identifier: GPL-2.0+
2844 + */
2845 +
2846 +#ifndef __PCIE_LAYERSCAPE_H_
2847 +#define __PCIE_LAYERSCAPE_H_
2848 +
2849 +void pci_init_board(void);
2850 +void ft_pcie_setup(void *blob, bd_t *bd);
2851 +
2852 +#endif
2853 diff -ruN u-boot-2015.01-rc3/arch/arm/include/asm/semihosting.h u-boot/arch/arm/include/asm/semihosting.h
2854 --- u-boot-2015.01-rc3/arch/arm/include/asm/semihosting.h 2014-12-08 22:35:08.000000000 +0100
2855 +++ u-boot/arch/arm/include/asm/semihosting.h 2015-01-01 17:34:32.125505350 +0100
2856 @@ -12,10 +12,6 @@
2857 * code for more information.
2858 */
2859 int smh_load(const char *fname, void *memp, int avail, int verbose);
2860 -int smh_read(int fd, void *memp, int len);
2861 -int smh_open(const char *fname, char *modestr);
2862 -int smh_close(int fd);
2863 -int smh_len_fd(int fd);
2864 -int smh_len(const char *fname);
2865 +long smh_len(const char *fname);
2866
2867 #endif /* __SEMIHOSTING_H__ */
2868 diff -ruN u-boot-2015.01-rc3/arch/arm/Kconfig u-boot/arch/arm/Kconfig
2869 --- u-boot-2015.01-rc3/arch/arm/Kconfig 2014-12-08 22:35:08.000000000 +0100
2870 +++ u-boot/arch/arm/Kconfig 2015-01-01 17:34:31.989507580 +0100
2871 @@ -341,6 +341,10 @@
2872 bool "Support spear600"
2873 select CPU_ARM926EJS
2874
2875 +config TARGET_STV0991
2876 + bool "Support stv0991"
2877 + select CPU_V7
2878 +
2879 config TARGET_X600
2880 bool "Support x600"
2881 select CPU_ARM926EJS
2882 @@ -650,6 +654,7 @@
2883
2884 config TARGET_TBS2910
2885 bool "Support tbs2910"
2886 + select CPU_V7
2887
2888 config TARGET_TQMA6
2889 bool "TQ Systems TQMa6 board"
2890 @@ -728,12 +733,14 @@
2891 select ARM64
2892
2893 config TARGET_LS1021AQDS
2894 - bool "Support ls1021aqds_nor"
2895 + bool "Support ls1021aqds"
2896 select CPU_V7
2897 + select SUPPORT_SPL
2898
2899 config TARGET_LS1021ATWR
2900 - bool "Support ls1021atwr_nor"
2901 + bool "Support ls1021atwr"
2902 select CPU_V7
2903 + select SUPPORT_SPL
2904
2905 config TARGET_BALLOON3
2906 bool "Support balloon3"
2907 @@ -793,6 +800,7 @@
2908 bool "Panasonic UniPhier platform"
2909 select CPU_V7
2910 select SUPPORT_SPL
2911 + select SPL
2912 select OF_CONTROL if !SPL_BUILD
2913
2914 endchoice
2915 @@ -953,6 +961,7 @@
2916 source "board/spear/x600/Kconfig"
2917 source "board/st-ericsson/snowball/Kconfig"
2918 source "board/st-ericsson/u8500/Kconfig"
2919 +source "board/st/stv0991/Kconfig"
2920 source "board/sunxi/Kconfig"
2921 source "board/syteco/jadecpu/Kconfig"
2922 source "board/syteco/zmx25/Kconfig"
2923 diff -ruN u-boot-2015.01-rc3/arch/arm/lib/semihosting.c u-boot/arch/arm/lib/semihosting.c
2924 --- u-boot-2015.01-rc3/arch/arm/lib/semihosting.c 2014-12-08 22:35:08.000000000 +0100
2925 +++ u-boot/arch/arm/lib/semihosting.c 2015-01-01 17:34:32.133505219 +0100
2926 @@ -26,9 +26,9 @@
2927 /*
2928 * Call the handler
2929 */
2930 -static int smh_trap(unsigned int sysnum, void *addr)
2931 +static long smh_trap(unsigned int sysnum, void *addr)
2932 {
2933 - register int result asm("r0");
2934 + register long result asm("r0");
2935 #if defined(CONFIG_ARM64)
2936 asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
2937 #else
2938 @@ -39,167 +39,164 @@
2939 }
2940
2941 /*
2942 - * Open, load a file into memory, and close it. Check that the available space
2943 - * is sufficient to store the entire file. Return the bytes actually read from
2944 - * the file as seen by the read function. The verbose flag enables some extra
2945 - * printing of successful read status.
2946 + * Open a file on the host. Mode is "r" or "rb" currently. Returns a file
2947 + * descriptor or -1 on error.
2948 */
2949 -int smh_load(const char *fname, void *memp, int avail, int verbose)
2950 +static long smh_open(const char *fname, char *modestr)
2951 {
2952 - int ret, fd, len;
2953 -
2954 - ret = -1;
2955 -
2956 - debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname,
2957 - avail, memp);
2958 -
2959 - /* Open the file */
2960 - fd = smh_open(fname, "rb");
2961 - if (fd == -1)
2962 - return ret;
2963 + long fd;
2964 + unsigned long mode;
2965 + struct smh_open_s {
2966 + const char *fname;
2967 + unsigned long mode;
2968 + size_t len;
2969 + } open;
2970
2971 - /* Get the file length */
2972 - ret = smh_len_fd(fd);
2973 - if (ret == -1) {
2974 - smh_close(fd);
2975 - return ret;
2976 - }
2977 + debug("%s: file \'%s\', mode \'%s\'\n", __func__, fname, modestr);
2978
2979 - /* Check that the file will fit in the supplied buffer */
2980 - if (ret > avail) {
2981 - printf("%s: ERROR ret %d, avail %u\n", __func__, ret,
2982 - avail);
2983 - smh_close(fd);
2984 - return ret;
2985 + /* Check the file mode */
2986 + if (!(strcmp(modestr, "r"))) {
2987 + mode = MODE_READ;
2988 + } else if (!(strcmp(modestr, "rb"))) {
2989 + mode = MODE_READBIN;
2990 + } else {
2991 + printf("%s: ERROR mode \'%s\' not supported\n", __func__,
2992 + modestr);
2993 + return -1;
2994 }
2995
2996 - len = ret;
2997 -
2998 - /* Read the file into the buffer */
2999 - ret = smh_read(fd, memp, len);
3000 - if (ret == 0) {
3001 - /* Print successful load information if requested */
3002 - if (verbose) {
3003 - printf("\n%s\n", fname);
3004 - printf(" 0x%8p dest\n", memp);
3005 - printf(" 0x%08x size\n", len);
3006 - printf(" 0x%08x avail\n", avail);
3007 - }
3008 - }
3009 + open.fname = fname;
3010 + open.len = strlen(fname);
3011 + open.mode = mode;
3012
3013 - /* Close the file */
3014 - smh_close(fd);
3015 + /* Open the file on the host */
3016 + fd = smh_trap(SYSOPEN, &open);
3017 + if (fd == -1)
3018 + printf("%s: ERROR fd %ld for file \'%s\'\n", __func__, fd,
3019 + fname);
3020
3021 - return ret;
3022 + return fd;
3023 }
3024
3025 /*
3026 * Read 'len' bytes of file into 'memp'. Returns 0 on success, else failure
3027 */
3028 -int smh_read(int fd, void *memp, int len)
3029 +static long smh_read(long fd, void *memp, size_t len)
3030 {
3031 - int ret;
3032 + long ret;
3033 struct smh_read_s {
3034 - int fd;
3035 + long fd;
3036 void *memp;
3037 - int len;
3038 + size_t len;
3039 } read;
3040
3041 - debug("%s: fd %d, memp %p, len %d\n", __func__, fd, memp, len);
3042 + debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len);
3043
3044 read.fd = fd;
3045 read.memp = memp;
3046 read.len = len;
3047
3048 ret = smh_trap(SYSREAD, &read);
3049 - if (ret == 0) {
3050 - return 0;
3051 - } else {
3052 + if (ret < 0) {
3053 /*
3054 * The ARM handler allows for returning partial lengths,
3055 * but in practice this never happens so rather than create
3056 * hard to maintain partial read loops and such, just fail
3057 * with an error message.
3058 */
3059 - printf("%s: ERROR ret %d, fd %d, len %u memp %p\n",
3060 + printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n",
3061 __func__, ret, fd, len, memp);
3062 + return -1;
3063 }
3064 - return ret;
3065 +
3066 + return 0;
3067 }
3068
3069 /*
3070 - * Open a file on the host. Mode is "r" or "rb" currently. Returns a file
3071 - * descriptor or -1 on error.
3072 + * Close the file using the file descriptor
3073 */
3074 -int smh_open(const char *fname, char *modestr)
3075 +static long smh_close(long fd)
3076 {
3077 - int ret, fd, mode;
3078 - struct smh_open_s {
3079 - const char *fname;
3080 - unsigned int mode;
3081 - unsigned int len;
3082 - } open;
3083 + long ret;
3084
3085 - debug("%s: file \'%s\', mode \'%s\'\n", __func__, fname, modestr);
3086 -
3087 - ret = -1;
3088 + debug("%s: fd %ld\n", __func__, fd);
3089
3090 - /* Check the file mode */
3091 - if (!(strcmp(modestr, "r"))) {
3092 - mode = MODE_READ;
3093 - } else if (!(strcmp(modestr, "rb"))) {
3094 - mode = MODE_READBIN;
3095 - } else {
3096 - printf("%s: ERROR mode \'%s\' not supported\n", __func__,
3097 - modestr);
3098 - return ret;
3099 - }
3100 -
3101 - open.fname = fname;
3102 - open.len = strlen(fname);
3103 - open.mode = mode;
3104 -
3105 - /* Open the file on the host */
3106 - fd = smh_trap(SYSOPEN, &open);
3107 - if (fd == -1)
3108 - printf("%s: ERROR fd %d for file \'%s\'\n", __func__, fd,
3109 - fname);
3110 + ret = smh_trap(SYSCLOSE, &fd);
3111 + if (ret == -1)
3112 + printf("%s: ERROR fd %ld\n", __func__, fd);
3113
3114 - return fd;
3115 + return ret;
3116 }
3117
3118 /*
3119 - * Close the file using the file descriptor
3120 + * Get the file length from the file descriptor
3121 */
3122 -int smh_close(int fd)
3123 +static long smh_len_fd(long fd)
3124 {
3125 - int ret;
3126 - long fdlong;
3127 + long ret;
3128
3129 - debug("%s: fd %d\n", __func__, fd);
3130 + debug("%s: fd %ld\n", __func__, fd);
3131
3132 - fdlong = (long)fd;
3133 - ret = smh_trap(SYSCLOSE, &fdlong);
3134 + ret = smh_trap(SYSFLEN, &fd);
3135 if (ret == -1)
3136 - printf("%s: ERROR fd %d\n", __func__, fd);
3137 + printf("%s: ERROR ret %ld, fd %ld\n", __func__, ret, fd);
3138
3139 return ret;
3140 }
3141
3142 /*
3143 - * Get the file length from the file descriptor
3144 + * Open, load a file into memory, and close it. Check that the available space
3145 + * is sufficient to store the entire file. Return the bytes actually read from
3146 + * the file as seen by the read function. The verbose flag enables some extra
3147 + * printing of successful read status.
3148 */
3149 -int smh_len_fd(int fd)
3150 +int smh_load(const char *fname, void *memp, int avail, int verbose)
3151 {
3152 - int ret;
3153 - long fdlong;
3154 + long ret;
3155 + long fd;
3156 + size_t len;
3157
3158 - debug("%s: fd %d\n", __func__, fd);
3159 + ret = -1;
3160
3161 - fdlong = (long)fd;
3162 - ret = smh_trap(SYSFLEN, &fdlong);
3163 - if (ret == -1)
3164 - printf("%s: ERROR ret %d\n", __func__, ret);
3165 + debug("%s: fname \'%s\', avail %u, memp %p\n", __func__, fname,