projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ramips: add preliminary Archer C20i support
[openwrt/openwrt.git] / package / boot / uboot-sunxi / patches / 001-uboot-sunxi-509d96d4f1f602d62d36db660973249e16f9d088.patch
1 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/cmd_boot.c u-boot-sunxi/arch/arm/cpu/armv7/cmd_boot.c
2 --- u-boot-2014.04/arch/arm/cpu/armv7/cmd_boot.c 1970-01-01 01:00:00.000000000 +0100
3 +++ u-boot-sunxi/arch/arm/cpu/armv7/cmd_boot.c 2014-09-06 16:58:35.193953144 +0200
4 @@ -0,0 +1,20 @@
5 +/*
6 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
7 + *
8 + * SPDX-License-Identifier: GPL-2.0+
9 + */
10 +
11 +/*
12 + * Misc boot support
13 + */
14 +#include <common.h>
15 +#include <command.h>
16 +
17 +#ifdef CONFIG_CMD_GO
18 +unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
19 + char * const argv[])
20 +{
21 + invalidate_icache_all();
22 + return entry(argc, argv);
23 +}
24 +#endif
25 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/Makefile u-boot-sunxi/arch/arm/cpu/armv7/Makefile
26 --- u-boot-2014.04/arch/arm/cpu/armv7/Makefile 2014-04-14 21:19:24.000000000 +0200
27 +++ u-boot-sunxi/arch/arm/cpu/armv7/Makefile 2014-09-06 16:58:35.185953145 +0200
28 @@ -11,8 +11,9 @@
29
30 obj-y += cpu.o
31 obj-y += syslib.o
32 +obj-y += cmd_boot.o
33
34 -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
35 +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
36 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
37 obj-y += lowlevel_init.o
38 endif
39 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/board.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/board.c
40 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/board.c 1970-01-01 01:00:00.000000000 +0100
41 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/board.c 2014-09-06 16:58:35.317953141 +0200
42 @@ -0,0 +1,166 @@
43 +/*
44 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
45 + *
46 + * (C) Copyright 2007-2011
47 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
48 + * Tom Cubie <tangliang@allwinnertech.com>
49 + *
50 + * Some init for sunxi platform.
51 + *
52 + * SPDX-License-Identifier: GPL-2.0+
53 + */
54 +
55 +#include <common.h>
56 +#include <i2c.h>
57 +#include <netdev.h>
58 +#include <miiphy.h>
59 +#include <serial.h>
60 +#ifdef CONFIG_SPL_BUILD
61 +#include <spl.h>
62 +#endif
63 +#include <asm/gpio.h>
64 +#include <asm/io.h>
65 +#include <asm/arch/clock.h>
66 +#include <asm/arch/gpio.h>
67 +#include <asm/arch/sys_proto.h>
68 +#include <asm/arch/timer.h>
69 +#include <asm/arch/watchdog.h>
70 +
71 +#ifdef CONFIG_SPL_BUILD
72 +/* Pointer to the global data structure for SPL */
73 +DECLARE_GLOBAL_DATA_PTR;
74 +
75 +/* The sunxi internal brom will try to loader external bootloader
76 + * from mmc0, nand flash, mmc2.
77 + * Unfortunately we can't check how SPL was loaded so assume
78 + * it's always the first SD/MMC controller
79 + */
80 +u32 spl_boot_device(void)
81 +{
82 + return BOOT_DEVICE_MMC1;
83 +}
84 +
85 +/* No confirmation data available in SPL yet. Hardcode bootmode */
86 +u32 spl_boot_mode(void)
87 +{
88 + return MMCSD_MODE_RAW;
89 +}
90 +#endif
91 +
92 +int gpio_init(void)
93 +{
94 +#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
95 +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
96 + /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
97 + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
98 + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
99 +#endif
100 + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
101 + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
102 + sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
103 +#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I))
104 + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
105 + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
106 + sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
107 +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I)
108 + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), 2);
109 + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), 2);
110 + sunxi_gpio_set_pull(SUNXI_GPH(21), 1);
111 +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I)
112 + sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
113 + sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
114 + sunxi_gpio_set_pull(SUNXI_GPB(20), 1);
115 +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I)
116 + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
117 + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
118 + sunxi_gpio_set_pull(SUNXI_GPG(4), 1);
119 +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_SUN8I)
120 + sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
121 + sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
122 + sunxi_gpio_set_pull(SUNXI_GPL(3), 1);
123 +#else
124 +#error Unsupported console port number. Please fix pin mux settings in board.c
125 +#endif
126 +
127 + return 0;
128 +}
129 +
130 +void reset_cpu(ulong addr)
131 +{
132 + watchdog_set(0);
133 + while (1);
134 +}
135 +
136 +/* do some early init */
137 +void s_init(void)
138 +{
139 +#if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
140 + /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
141 + asm volatile(
142 + "mrc p15, 0, r0, c1, c0, 1\n"
143 + "orr r0, r0, #1 << 6\n"
144 + "mcr p15, 0, r0, c1, c0, 1\n");
145 +#endif
146 +
147 + watchdog_init();
148 + clock_init();
149 + timer_init();
150 + gpio_init();
151 + i2c_init_board();
152 +
153 +#ifdef CONFIG_SPL_BUILD
154 + gd = &gdata;
155 + preloader_console_init();
156 +
157 +#ifdef CONFIG_SPL_I2C_SUPPORT
158 + /* Needed early by sunxi_board_init if PMU is enabled */
159 + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
160 +#endif
161 +#endif
162 +/* No SPL on sun6i, so we do sunxi_board_init() from non spl there */
163 +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
164 + sunxi_board_init();
165 +#endif
166 +}
167 +
168 +#ifndef CONFIG_SYS_DCACHE_OFF
169 +void enable_caches(void)
170 +{
171 + /* Enable D-cache. I-cache is already enabled in start.S */
172 + dcache_enable();
173 +}
174 +#endif
175 +
176 +#ifdef CONFIG_CMD_NET
177 +/*
178 + * Initializes on-chip ethernet controllers.
179 + * to override, implement board_eth_init()
180 + */
181 +int cpu_eth_init(bd_t *bis)
182 +{
183 + __maybe_unused int rc;
184 +
185 +#ifdef CONFIG_MACPWR
186 + gpio_direction_output(CONFIG_MACPWR, 1);
187 + mdelay(200);
188 +#endif
189 +
190 +#ifdef CONFIG_SUNXI_EMAC
191 + rc = sunxi_emac_initialize(bis);
192 + if (rc < 0) {
193 + printf("sunxi: failed to initialize emac\n");
194 + return rc;
195 + }
196 +#endif
197 +
198 +#ifdef CONFIG_SUNXI_GMAC
199 + rc = sunxi_gmac_initialize(bis);
200 + if (rc < 0) {
201 + printf("sunxi: failed to initialize gmac\n");
202 + return rc;
203 + }
204 +#endif
205 +
206 + return 0;
207 +}
208 +#endif
209 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock.c
210 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock.c 1970-01-01 01:00:00.000000000 +0100
211 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock.c 2014-09-06 16:58:35.317953141 +0200
212 @@ -0,0 +1,25 @@
213 +/*
214 + * (C) Copyright 2007-2012
215 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
216 + * Tom Cubie <tangliang@allwinnertech.com>
217 + *
218 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
219 + *
220 + * SPDX-License-Identifier: GPL-2.0+
221 + */
222 +
223 +#include <common.h>
224 +#include <asm/io.h>
225 +#include <asm/arch/clock.h>
226 +#include <asm/arch/gpio.h>
227 +#include <asm/arch/sys_proto.h>
228 +
229 +int clock_init(void)
230 +{
231 +#ifdef CONFIG_SPL_BUILD
232 + clock_init_safe();
233 +#endif
234 + clock_init_uart();
235 +
236 + return 0;
237 +}
238 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock_sun4i.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock_sun4i.c
239 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock_sun4i.c 1970-01-01 01:00:00.000000000 +0100
240 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock_sun4i.c 2014-09-06 16:58:35.317953141 +0200
241 @@ -0,0 +1,188 @@
242 +/*
243 + * sun4i, sun5i and sun7i specific clock code
244 + *
245 + * (C) Copyright 2007-2012
246 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
247 + * Tom Cubie <tangliang@allwinnertech.com>
248 + *
249 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
250 + *
251 + * SPDX-License-Identifier: GPL-2.0+
252 + */
253 +
254 +#include <common.h>
255 +#include <asm/io.h>
256 +#include <asm/arch/clock.h>
257 +#include <asm/arch/gpio.h>
258 +#include <asm/arch/sys_proto.h>
259 +
260 +#ifdef CONFIG_SPL_BUILD
261 +void clock_init_safe(void)
262 +{
263 + struct sunxi_ccm_reg * const ccm =
264 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
265 +
266 + /* Set safe defaults until PMU is configured */
267 + writel(AXI_DIV_1 << AXI_DIV_SHIFT |
268 + AHB_DIV_2 << AHB_DIV_SHIFT |
269 + APB0_DIV_1 << APB0_DIV_SHIFT |
270 + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
271 + &ccm->cpu_ahb_apb0_cfg);
272 + writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
273 + sdelay(200);
274 + writel(AXI_DIV_1 << AXI_DIV_SHIFT |
275 + AHB_DIV_2 << AHB_DIV_SHIFT |
276 + APB0_DIV_1 << APB0_DIV_SHIFT |
277 + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
278 + &ccm->cpu_ahb_apb0_cfg);
279 +#ifdef CONFIG_SUN7I
280 + writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
281 + &ccm->ahb_gate0);
282 +#endif
283 + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
284 +}
285 +#endif
286 +
287 +void clock_init_uart(void)
288 +{
289 + struct sunxi_ccm_reg *const ccm =
290 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
291 +
292 + /* uart clock source is apb1 */
293 + writel(APB1_CLK_SRC_OSC24M|
294 + APB1_CLK_RATE_N_1|
295 + APB1_CLK_RATE_M(1),
296 + &ccm->apb1_clk_div_cfg);
297 +
298 + /* open the clock for uart */
299 + setbits_le32(&ccm->apb1_gate,
300 + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
301 +}
302 +
303 +int clock_twi_onoff(int port, int state)
304 +{
305 + struct sunxi_ccm_reg *const ccm =
306 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
307 +
308 + if (port > 2)
309 + return -1;
310 +
311 + /* set the apb clock gate for twi */
312 + if (state)
313 + setbits_le32(&ccm->apb1_gate,
314 + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
315 + else
316 + clrbits_le32(&ccm->apb1_gate,
317 + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT+port));
318 +
319 + return 0;
320 +}
321 +
322 +#ifdef CONFIG_SPL_BUILD
323 +#define PLL1_CFG(N, K, M, P) ( 1 << CCM_PLL1_CFG_ENABLE_SHIFT | \
324 + 0 << CCM_PLL1_CFG_VCO_RST_SHIFT | \
325 + 8 << CCM_PLL1_CFG_VCO_BIAS_SHIFT | \
326 + 0 << CCM_PLL1_CFG_PLL4_EXCH_SHIFT | \
327 + 16 << CCM_PLL1_CFG_BIAS_CUR_SHIFT | \
328 + (P)<< CCM_PLL1_CFG_DIVP_SHIFT | \
329 + 2 << CCM_PLL1_CFG_LCK_TMR_SHIFT | \
330 + (N)<< CCM_PLL1_CFG_FACTOR_N_SHIFT | \
331 + (K)<< CCM_PLL1_CFG_FACTOR_K_SHIFT | \
332 + 0 << CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT | \
333 + 0 << CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT | \
334 + (M)<< CCM_PLL1_CFG_FACTOR_M_SHIFT)
335 +
336 +static struct {
337 + u32 pll1_cfg;
338 + unsigned int freq;
339 +} pll1_para[] = {
340 + /* This array must be ordered by frequency. */
341 + { PLL1_CFG(16, 0, 0, 0), 384000000 },
342 + { PLL1_CFG(16, 1, 0, 0), 768000000 },
343 + { PLL1_CFG(20, 1, 0, 0), 960000000 },
344 + { PLL1_CFG(21, 1, 0, 0), 1008000000},
345 + { PLL1_CFG(22, 1, 0, 0), 1056000000},
346 + { PLL1_CFG(23, 1, 0, 0), 1104000000},
347 + { PLL1_CFG(24, 1, 0, 0), 1152000000},
348 + { PLL1_CFG(25, 1, 0, 0), 1200000000},
349 + { PLL1_CFG(26, 1, 0, 0), 1248000000},
350 + { PLL1_CFG(27, 1, 0, 0), 1296000000},
351 + { PLL1_CFG(28, 1, 0, 0), 1344000000},
352 + { PLL1_CFG(29, 1, 0, 0), 1392000000},
353 + { PLL1_CFG(30, 1, 0, 0), 1440000000},
354 + { PLL1_CFG(31, 1, 0, 0), 1488000000},
355 + /* Final catchall entry */
356 + { PLL1_CFG(31, 1, 0, 0), ~0},
357 +};
358 +
359 +void clock_set_pll1(unsigned int hz)
360 +{
361 + int i = 0;
362 + int axi, ahb, apb0;
363 + struct sunxi_ccm_reg * const ccm =
364 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
365 +
366 + /* Find target frequency */
367 + while (pll1_para[i].freq < hz)
368 + i++;
369 +
370 + hz = pll1_para[i].freq;
371 +
372 + /* Calculate system clock divisors */
373 + axi = DIV_ROUND_UP(hz, 432000000); /* Max 450MHz */
374 + ahb = DIV_ROUND_UP(hz/axi, 204000000); /* Max 250MHz */
375 + apb0 = 2; /* Max 150MHz */
376 +
377 + printf("CPU: %uHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0);
378 +
379 + /* Map divisors to register values */
380 + axi = axi - 1;
381 + if (ahb > 4)
382 + ahb = 3;
383 + else if (ahb > 2)
384 + ahb = 2;
385 + else if (ahb > 1)
386 + ahb = 1;
387 + else
388 + ahb = 0;
389 +
390 + apb0 = apb0 - 1;
391 +
392 + /* Switch to 24MHz clock while changing PLL1 */
393 + writel(AXI_DIV_1 << AXI_DIV_SHIFT |
394 + AHB_DIV_2 << AHB_DIV_SHIFT |
395 + APB0_DIV_1 << APB0_DIV_SHIFT |
396 + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
397 + &ccm->cpu_ahb_apb0_cfg);
398 + sdelay(20);
399 +
400 + /* Configure sys clock divisors */
401 + writel(axi << AXI_DIV_SHIFT |
402 + ahb << AHB_DIV_SHIFT |
403 + apb0 << APB0_DIV_SHIFT |
404 + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
405 + &ccm->cpu_ahb_apb0_cfg);
406 +
407 + /* Configure PLL1 at the desired frequency */
408 + writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg);
409 + sdelay(200);
410 +
411 + /* Switch CPU to PLL1 */
412 + writel(axi << AXI_DIV_SHIFT |
413 + ahb << AHB_DIV_SHIFT |
414 + apb0 << APB0_DIV_SHIFT |
415 + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
416 + &ccm->cpu_ahb_apb0_cfg);
417 + sdelay(20);
418 +}
419 +#endif
420 +
421 +unsigned int clock_get_pll6(void)
422 +{
423 + struct sunxi_ccm_reg *const ccm =
424 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
425 + uint32_t rval = readl(&ccm->pll6_cfg);
426 + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
427 + int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
428 + return 24000000 * n * k / 2;
429 +}
430 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock_sun6i.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
431 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/clock_sun6i.c 1970-01-01 01:00:00.000000000 +0100
432 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/clock_sun6i.c 2014-09-06 16:58:35.317953141 +0200
433 @@ -0,0 +1,110 @@
434 +/*
435 + * sun6i specific clock code
436 + *
437 + * (C) Copyright 2007-2012
438 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
439 + * Tom Cubie <tangliang@allwinnertech.com>
440 + *
441 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
442 + *
443 + * SPDX-License-Identifier: GPL-2.0+
444 + */
445 +
446 +#include <common.h>
447 +#include <asm/io.h>
448 +#include <asm/arch/clock.h>
449 +#include <asm/arch/gpio.h>
450 +#include <asm/arch/prcm.h>
451 +#include <asm/arch/sys_proto.h>
452 +
453 +#ifdef CONFIG_SPL_BUILD
454 +void clock_init_safe(void)
455 +{
456 + struct sunxi_ccm_reg * const ccm =
457 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
458 + struct sunxi_prcm_reg * const prcm =
459 + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
460 +
461 + /* Set PLL ldo voltage without this PLL6 does not work properly */
462 + writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
463 + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
464 + PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
465 + writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
466 + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140) |
467 + PRCM_PLL_CTRL_LDO_KEY, &prcm->pll_ctrl1);
468 + writel(PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
469 + PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140),
470 + &prcm->pll_ctrl1);
471 +
472 + /* AXI and PLL1 settings from boot0 / boot1, PLL1 set to 486 Mhz */
473 + writel(AXI_DIV_3 << AXI_DIV_SHIFT |
474 + ATB_DIV_2 << ATB_DIV_SHIFT |
475 + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
476 + &ccm->cpu_axi_cfg);
477 + writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
478 + sdelay(200);
479 + writel(AXI_DIV_3 << AXI_DIV_SHIFT |
480 + ATB_DIV_2 << ATB_DIV_SHIFT |
481 + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
482 + &ccm->cpu_axi_cfg);
483 +
484 + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
485 +}
486 +#endif
487 +
488 +void clock_init_uart(void)
489 +{
490 + struct sunxi_ccm_reg *const ccm =
491 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
492 +
493 +#if CONFIG_CONS_INDEX < 5
494 + /* uart clock source is apb2 */
495 + writel(APB2_CLK_SRC_OSC24M|
496 + APB2_CLK_RATE_N_1|
497 + APB2_CLK_RATE_M(1),
498 + &ccm->apb2_div);
499 +
500 + /* open the clock for uart */
501 + setbits_le32(&ccm->apb2_gate,
502 + CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1));
503 +
504 + /* deassert uart reset */
505 + setbits_le32(&ccm->apb2_reset_cfg,
506 + 1 << (APB2_RESET_UART_SHIFT+CONFIG_CONS_INDEX-1));
507 +#else
508 + /* enable R_PIO and R_UART clocks, and de-assert resets */
509 + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
510 +#endif
511 +
512 + /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
513 + writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
514 +}
515 +
516 +int clock_twi_onoff(int port, int state)
517 +{
518 + struct sunxi_ccm_reg *const ccm =
519 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
520 +
521 + if (port > 3)
522 + return -1;
523 +
524 + /* set the apb clock gate for twi */
525 + if (state)
526 + setbits_le32(&ccm->apb2_gate,
527 + CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
528 + else
529 + clrbits_le32(&ccm->apb2_gate,
530 + CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
531 +
532 + return 0;
533 +}
534 +
535 +unsigned int clock_get_pll6(void)
536 +{
537 + struct sunxi_ccm_reg *const ccm =
538 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
539 + uint32_t rval = readl(&ccm->pll6_cfg);
540 + int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
541 + int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
542 + return 24000000 * n * k / 2;
543 +}
544 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c
545 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c 1970-01-01 01:00:00.000000000 +0100
546 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cmd_watchdog.c 2014-09-06 16:58:35.317953141 +0200
547 @@ -0,0 +1,29 @@
548 +/*
549 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
550 + *
551 + * SPDX-License-Identifier: GPL-2.0+
552 + */
553 +
554 +#include <common.h>
555 +#include <asm/io.h>
556 +#include <asm/arch/watchdog.h>
557 +
558 +int do_sunxi_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, const char *argv[])
559 +{
560 + unsigned long interval;
561 +
562 + if (argc < 2) {
563 + printf("usage: watchdog seconds\n");
564 + printf("over %d to disable watchdog\n", WDT_MAX_TIMEOUT);
565 + }
566 + interval = simple_strtoul(argv[1], NULL, 10);
567 + watchdog_set((unsigned int)interval);
568 +
569 + return 0;
570 +}
571 +
572 +U_BOOT_CMD(
573 + watchdog, 2, 1, do_sunxi_watchdog,
574 + "Set watchdog [0 - 16]. [17+} disables",
575 + ""
576 +);
577 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/config.mk u-boot-sunxi/arch/arm/cpu/armv7/sunxi/config.mk
578 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/config.mk 1970-01-01 01:00:00.000000000 +0100
579 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/config.mk 2014-09-06 16:58:35.317953141 +0200
580 @@ -0,0 +1,8 @@
581 +# Build a combined spl + u-boot image
582 +ifdef CONFIG_SPL
583 +ifndef CONFIG_SPL_BUILD
584 +ifndef CONFIG_SPL_FEL
585 +ALL-y += u-boot-sunxi-with-spl.bin
586 +endif
587 +endif
588 +endif
589 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/cpu_info.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cpu_info.c
590 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/cpu_info.c 1970-01-01 01:00:00.000000000 +0100
591 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/cpu_info.c 2014-09-06 16:58:35.317953141 +0200
592 @@ -0,0 +1,38 @@
593 +/*
594 + * (C) Copyright 2007-2011
595 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
596 + * Tom Cubie <tangliang@allwinnertech.com>
597 + *
598 + * SPDX-License-Identifier: GPL-2.0+
599 + */
600 +
601 +#include <common.h>
602 +#include <asm/io.h>
603 +#include <asm/arch/cpu.h>
604 +
605 +#ifdef CONFIG_DISPLAY_CPUINFO
606 +int print_cpuinfo(void)
607 +{
608 +#ifdef CONFIG_SUN4I
609 + puts("CPU: Allwinner A10 (SUN4I)\n");
610 +#elif defined CONFIG_SUN5I
611 + u32 val = readl(SUNXI_SID_BASE + 0x08);
612 + switch ((val >> 12) & 0xf) {
613 + case 0: puts("CPU: Allwinner A12 (SUN5I)\n"); break;
614 + case 3: puts("CPU: Allwinner A13 (SUN5I)\n"); break;
615 + case 7: puts("CPU: Allwinner A10s (SUN5I)\n"); break;
616 + default: puts("CPU: Allwinner A1X (SUN5I)\n");
617 + }
618 +#elif defined CONFIG_SUN6I
619 + puts("CPU: Allwinner A31 (SUN6I)\n");
620 +#elif defined CONFIG_SUN7I
621 + puts("CPU: Allwinner A20 (SUN7I)\n");
622 +#elif defined CONFIG_SUN8I
623 + puts("CPU: Allwinner A23 (SUN8I)\n");
624 +#else
625 +#warning Please update cpu_info.c with correct CPU information
626 + puts("CPU: SUNXI Family\n");
627 +#endif
628 + return 0;
629 +}
630 +#endif
631 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/dram.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/dram.c
632 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/dram.c 1970-01-01 01:00:00.000000000 +0100
633 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/dram.c 2014-09-06 16:58:35.317953141 +0200
634 @@ -0,0 +1,693 @@
635 +/*
636 + * sunxi DRAM controller initialization
637 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
638 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
639 + *
640 + * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
641 + * and earlier U-Boot Allwiner A10 SPL work
642 + *
643 + * (C) Copyright 2007-2012
644 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
645 + * Berg Xing <bergxing@allwinnertech.com>
646 + * Tom Cubie <tangliang@allwinnertech.com>
647 + *
648 + * SPDX-License-Identifier: GPL-2.0+
649 + */
650 +
651 +/*
652 + * Unfortunately the only documentation we have on the sun7i DRAM
653 + * controller is Allwinner boot0 + boot1 code, and that code uses
654 + * magic numbers & shifts with no explanations. Hence this code is
655 + * rather undocumented and full of magic.
656 + */
657 +
658 +#include <common.h>
659 +#include <asm/io.h>
660 +#include <asm/arch/clock.h>
661 +#include <asm/arch/dram.h>
662 +#include <asm/arch/timer.h>
663 +#include <asm/arch/sys_proto.h>
664 +
665 +#define CPU_CFG_CHIP_VER(n) ((n) << 6)
666 +#define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
667 +#define CPU_CFG_CHIP_REV_A 0x0
668 +#define CPU_CFG_CHIP_REV_C1 0x1
669 +#define CPU_CFG_CHIP_REV_C2 0x2
670 +#define CPU_CFG_CHIP_REV_B 0x3
671 +
672 +/*
673 + * Wait up to 1s for mask to be clear in given reg.
674 + */
675 +static void await_completion(u32 *reg, u32 mask)
676 +{
677 + unsigned long tmo = timer_get_us() + 1000000;
678 +
679 + while (readl(reg) & mask) {
680 + if (timer_get_us() > tmo)
681 + panic("Timeout initialising DRAM\n");
682 + }
683 +}
684 +
685 +static void mctl_ddr3_reset(void)
686 +{
687 + struct sunxi_dram_reg *dram =
688 + (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
689 +
690 +#ifdef CONFIG_SUN4I
691 + struct sunxi_timer_reg *timer =
692 + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
693 + u32 reg_val;
694 +
695 + writel(0, &timer->cpu_cfg);
696 + reg_val = readl(&timer->cpu_cfg);
697 +
698 + if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
699 + CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
700 + setbits_le32(&dram->mcr, DRAM_MCR_RESET);
701 + udelay(2);
702 + clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
703 + } else
704 +#endif
705 + {
706 + clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
707 + udelay(2);
708 + setbits_le32(&dram->mcr, DRAM_MCR_RESET);
709 + }
710 +}
711 +
712 +static void mctl_set_drive(void)
713 +{
714 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
715 +
716 +#ifdef CONFIG_SUN7I
717 + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
718 +#else
719 + clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
720 +#endif
721 + DRAM_MCR_MODE_EN(0x3) |
722 + 0xffc);
723 +}
724 +
725 +static void mctl_itm_disable(void)
726 +{
727 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
728 +
729 + clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);
730 +}
731 +
732 +static void mctl_itm_enable(void)
733 +{
734 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
735 +
736 + clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
737 +}
738 +
739 +static void mctl_enable_dll0(u32 phase)
740 +{
741 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
742 +
743 + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
744 + ((phase >> 16) & 0x3f) << 6);
745 + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);
746 + udelay(2);
747 +
748 + clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);
749 + udelay(22);
750 +
751 + clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);
752 + udelay(22);
753 +}
754 +
755 +/*
756 + * Note: This differs from pm/standby in that it checks the bus width
757 + */
758 +static void mctl_enable_dllx(u32 phase)
759 +{
760 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
761 + u32 i, n, bus_width;
762 +
763 + bus_width = readl(&dram->dcr);
764 +
765 + if ((bus_width & DRAM_DCR_BUS_WIDTH_MASK) ==
766 + DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
767 + n = DRAM_DCR_NR_DLLCR_32BIT;
768 + else
769 + n = DRAM_DCR_NR_DLLCR_16BIT;
770 +
771 + for (i = 1; i < n; i++) {
772 + clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
773 + (phase & 0xf) << 14);
774 + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
775 + DRAM_DLLCR_DISABLE);
776 + phase >>= 4;
777 + }
778 + udelay(2);
779 +
780 + for (i = 1; i < n; i++)
781 + clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
782 + DRAM_DLLCR_DISABLE);
783 + udelay(22);
784 +
785 + for (i = 1; i < n; i++)
786 + clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
787 + DRAM_DLLCR_NRESET);
788 + udelay(22);
789 +}
790 +
791 +static u32 hpcr_value[32] = {
792 +#ifdef CONFIG_SUN5I
793 + 0, 0, 0, 0,
794 + 0, 0, 0, 0,
795 + 0, 0, 0, 0,
796 + 0, 0, 0, 0,
797 + 0x1031, 0x1031, 0x0735, 0x1035,
798 + 0x1035, 0x0731, 0x1031, 0,
799 + 0x0301, 0x0301, 0x0301, 0x0301,
800 + 0x0301, 0x0301, 0x0301, 0
801 +#endif
802 +#ifdef CONFIG_SUN4I
803 + 0x0301, 0x0301, 0x0301, 0x0301,
804 + 0x0301, 0x0301, 0, 0,
805 + 0, 0, 0, 0,
806 + 0, 0, 0, 0,
807 + 0x1031, 0x1031, 0x0735, 0x5031,
808 + 0x1035, 0x0731, 0x1031, 0x0735,
809 + 0x1035, 0x1031, 0x0731, 0x1035,
810 + 0x1031, 0x0301, 0x0301, 0x0731
811 +#endif
812 +#ifdef CONFIG_SUN7I
813 + 0x0301, 0x0301, 0x0301, 0x0301,
814 + 0x0301, 0x0301, 0x0301, 0x0301,
815 + 0, 0, 0, 0,
816 + 0, 0, 0, 0,
817 + 0x1031, 0x1031, 0x0735, 0x1035,
818 + 0x1035, 0x0731, 0x1031, 0x0735,
819 + 0x1035, 0x1031, 0x0731, 0x1035,
820 + 0x0001, 0x1031, 0, 0x1031
821 + /* last row differs from boot0 source table
822 + * 0x1031, 0x0301, 0x0301, 0x0731
823 + * but boot0 code skips #28 and #30, and sets #29 and #31 to the
824 + * value from #28 entry (0x1031)
825 + */
826 +#endif
827 +};
828 +
829 +static void mctl_configure_hostport(void)
830 +{
831 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
832 + u32 i;
833 +
834 + for (i = 0; i < 32; i++)
835 + writel(hpcr_value[i], &dram->hpcr[i]);
836 +}
837 +
838 +static void mctl_setup_dram_clock(u32 clk)
839 +{
840 + u32 reg_val;
841 + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
842 +
843 + /* setup DRAM PLL */
844 + reg_val = readl(&ccm->pll5_cfg);
845 + reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */
846 + reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */
847 + reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
848 + reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
849 + if (clk >= 540 && clk < 552) {
850 + /* dram = 540MHz, pll5p = 540MHz */
851 + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
852 + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
853 + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
854 + reg_val |= CCM_PLL5_CTRL_P(1);
855 + } else if (clk >= 512 && clk < 528) {
856 + /* dram = 512MHz, pll5p = 384MHz */
857 + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
858 + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
859 + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
860 + reg_val |= CCM_PLL5_CTRL_P(2);
861 + } else if (clk >= 496 && clk < 504) {
862 + /* dram = 496MHz, pll5p = 372MHz */
863 + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
864 + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
865 + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
866 + reg_val |= CCM_PLL5_CTRL_P(2);
867 + } else if (clk >= 468 && clk < 480) {
868 + /* dram = 468MHz, pll5p = 468MHz */
869 + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
870 + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
871 + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
872 + reg_val |= CCM_PLL5_CTRL_P(1);
873 + } else if (clk >= 396 && clk < 408) {
874 + /* dram = 396MHz, pll5p = 396MHz */
875 + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
876 + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
877 + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
878 + reg_val |= CCM_PLL5_CTRL_P(1);
879 + } else {
880 + /* any other frequency that is a multiple of 24 */
881 + reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
882 + reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
883 + reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
884 + reg_val |= CCM_PLL5_CTRL_P(CCM_PLL5_CTRL_P_X(2));
885 + }
886 + reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */
887 + reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */
888 + writel(reg_val, &ccm->pll5_cfg);
889 + udelay(5500);
890 +
891 + setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
892 +
893 +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN7I)
894 + /* reset GPS */
895 + clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
896 + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
897 + udelay(1);
898 + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
899 +#endif
900 +
901 +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
902 + /* setup MBUS clock */
903 + reg_val = CCM_MBUS_CTRL_GATE |
904 +#if defined(CONFIG_SUN7I) && defined(CONFIG_FAST_MBUS)
905 + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
906 + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
907 + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(3));
908 +#elif defined(CONFIG_SUN7I) && !defined(CONFIG_FAST_MBUS)
909 + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
910 + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(2)) |
911 + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
912 +#else /* defined(CONFIG_SUN5I) */
913 + CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
914 + CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
915 + CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(2));
916 +#endif
917 + writel(reg_val, &ccm->mbus_clk_cfg);
918 +#endif
919 +
920 + /*
921 + * open DRAMC AHB & DLL register clock
922 + * close it first
923 + */
924 +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
925 + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
926 +#else
927 + clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
928 +#endif
929 + udelay(22);
930 +
931 + /* then open it */
932 +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
933 + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
934 +#else
935 + setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
936 +#endif
937 + udelay(22);
938 +}
939 +
940 +static int dramc_scan_readpipe(void)
941 +{
942 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
943 + u32 reg_val;
944 +
945 + /* data training trigger */
946 +#ifdef CONFIG_SUN7I
947 + clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
948 +#endif
949 + setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
950 +
951 + /* check whether data training process has completed */
952 + await_completion(&dram->ccr, DRAM_CCR_DATA_TRAINING);
953 +
954 + /* check data training result */
955 + reg_val = readl(&dram->csr);
956 + if (reg_val & DRAM_CSR_FAILED)
957 + return -1;
958 +
959 + return 0;
960 +}
961 +
962 +static int dramc_scan_dll_para(void)
963 +{
964 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
965 + const u32 dqs_dly[7] = {0x3, 0x2, 0x1, 0x0, 0xe, 0xd, 0xc};
966 + const u32 clk_dly[15] = {0x07, 0x06, 0x05, 0x04, 0x03,
967 + 0x02, 0x01, 0x00, 0x08, 0x10,
968 + 0x18, 0x20, 0x28, 0x30, 0x38};
969 + u32 clk_dqs_count[15];
970 + u32 dqs_i, clk_i, cr_i;
971 + u32 max_val, min_val;
972 + u32 dqs_index, clk_index;
973 +
974 + /* Find DQS_DLY Pass Count for every CLK_DLY */
975 + for (clk_i = 0; clk_i < 15; clk_i++) {
976 + clk_dqs_count[clk_i] = 0;
977 + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
978 + (clk_dly[clk_i] & 0x3f) << 6);
979 + for (dqs_i = 0; dqs_i < 7; dqs_i++) {
980 + for (cr_i = 1; cr_i < 5; cr_i++) {
981 + clrsetbits_le32(&dram->dllcr[cr_i],
982 + 0x4f << 14,
983 + (dqs_dly[dqs_i] & 0x4f) << 14);
984 + }
985 + udelay(2);
986 + if (dramc_scan_readpipe() == 0)
987 + clk_dqs_count[clk_i]++;
988 + }
989 + }
990 + /* Test DQS_DLY Pass Count for every CLK_DLY from up to down */
991 + for (dqs_i = 15; dqs_i > 0; dqs_i--) {
992 + max_val = 15;
993 + min_val = 15;
994 + for (clk_i = 0; clk_i < 15; clk_i++) {
995 + if (clk_dqs_count[clk_i] == dqs_i) {
996 + max_val = clk_i;
997 + if (min_val == 15)
998 + min_val = clk_i;
999 + }
1000 + }
1001 + if (max_val < 15)
1002 + break;
1003 + }
1004 +
1005 + /* Check if Find a CLK_DLY failed */
1006 + if (!dqs_i)
1007 + goto fail;
1008 +
1009 + /* Find the middle index of CLK_DLY */
1010 + clk_index = (max_val + min_val) >> 1;
1011 + if ((max_val == (15 - 1)) && (min_val > 0))
1012 + /* if CLK_DLY[MCTL_CLK_DLY_COUNT] is very good, then the middle
1013 + * value can be more close to the max_val
1014 + */
1015 + clk_index = (15 + clk_index) >> 1;
1016 + else if ((max_val < (15 - 1)) && (min_val == 0))
1017 + /* if CLK_DLY[0] is very good, then the middle value can be more
1018 + * close to the min_val
1019 + */
1020 + clk_index >>= 1;
1021 + if (clk_dqs_count[clk_index] < dqs_i)
1022 + clk_index = min_val;
1023 +
1024 + /* Find the middle index of DQS_DLY for the CLK_DLY got above, and Scan
1025 + * read pipe again
1026 + */
1027 + clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
1028 + (clk_dly[clk_index] & 0x3f) << 6);
1029 + max_val = 7;
1030 + min_val = 7;
1031 + for (dqs_i = 0; dqs_i < 7; dqs_i++) {
1032 + clk_dqs_count[dqs_i] = 0;
1033 + for (cr_i = 1; cr_i < 5; cr_i++) {
1034 + clrsetbits_le32(&dram->dllcr[cr_i],
1035 + 0x4f << 14,
1036 + (dqs_dly[dqs_i] & 0x4f) << 14);
1037 + }
1038 + udelay(2);
1039 + if (dramc_scan_readpipe() == 0) {
1040 + clk_dqs_count[dqs_i] = 1;
1041 + max_val = dqs_i;
1042 + if (min_val == 7)
1043 + min_val = dqs_i;
1044 + }
1045 + }
1046 +
1047 + if (max_val < 7) {
1048 + dqs_index = (max_val + min_val) >> 1;
1049 + if ((max_val == (7-1)) && (min_val > 0))
1050 + dqs_index = (7 + dqs_index) >> 1;
1051 + else if ((max_val < (7-1)) && (min_val == 0))
1052 + dqs_index >>= 1;
1053 + if (!clk_dqs_count[dqs_index])
1054 + dqs_index = min_val;
1055 + for (cr_i = 1; cr_i < 5; cr_i++) {
1056 + clrsetbits_le32(&dram->dllcr[cr_i],
1057 + 0x4f << 14,
1058 + (dqs_dly[dqs_index] & 0x4f) << 14);
1059 + }
1060 + udelay(2);
1061 + return dramc_scan_readpipe();
1062 + }
1063 +
1064 +fail:
1065 + clrbits_le32(&dram->dllcr[0], 0x3f << 6);
1066 + for (cr_i = 1; cr_i < 5; cr_i++)
1067 + clrbits_le32(&dram->dllcr[cr_i], 0x4f << 14);
1068 + udelay(2);
1069 +
1070 + return dramc_scan_readpipe();
1071 +}
1072 +
1073 +static void dramc_clock_output_en(u32 on)
1074 +{
1075 +#if defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I)
1076 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1077 +
1078 + if (on)
1079 + setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
1080 + else
1081 + clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
1082 +#endif
1083 +#ifdef CONFIG_SUN4I
1084 + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
1085 + if (on)
1086 + setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
1087 + else
1088 + clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
1089 +#endif
1090 +}
1091 +
1092 +static const u16 tRFC_table[2][6] = {
1093 + /* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */
1094 + /* DDR2 75ns 105ns 127.5ns 195ns 327.5ns invalid */
1095 + { 77, 108, 131, 200, 336, 336 },
1096 + /* DDR3 invalid 90ns 110ns 160ns 300ns 350ns */
1097 + { 93, 93, 113, 164, 308, 359 }
1098 +};
1099 +
1100 +static void dramc_set_autorefresh_cycle(u32 clk, u32 type, u32 density)
1101 +{
1102 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1103 + u32 tRFC, tREFI;
1104 +
1105 + tRFC = (tRFC_table[type][density] * clk + 1023) >> 10;
1106 + tREFI = (7987 * clk) >> 10; /* <= 7.8us */
1107 +
1108 + writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
1109 +}
1110 +
1111 +unsigned long dramc_init(struct dram_para *para)
1112 +{
1113 + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
1114 + u32 reg_val;
1115 + u32 density;
1116 + int ret_val;
1117 +
1118 + /* check input dram parameter structure */
1119 + if (!para)
1120 + return 0;
1121 +
1122 + /* setup DRAM relative clock */
1123 + mctl_setup_dram_clock(para->clock);
1124 +
1125 +#ifdef CONFIG_SUN5I
1126 + /* Disable any pad power save control */
1127 + writel(0, &dram->ppwrsctl);
1128 +#endif
1129 +
1130 + /* reset external DRAM */
1131 +#ifndef CONFIG_SUN7I
1132 + mctl_ddr3_reset();
1133 +#endif
1134 + mctl_set_drive();
1135 +
1136 + /* dram clock off */
1137 + dramc_clock_output_en(0);
1138 +
1139 +#ifdef CONFIG_SUN4I
1140 + /* select dram controller 1 */
1141 + writel(DRAM_CSEL_MAGIC, &dram->csel);
1142 +#endif
1143 +
1144 + mctl_itm_disable();
1145 + mctl_enable_dll0(para->tpr3);
1146 +
1147 + /* configure external DRAM */
1148 + reg_val = 0x0;
1149 + if (para->type == DRAM_MEMORY_TYPE_DDR3)
1150 + reg_val |= DRAM_DCR_TYPE_DDR3;
1151 + reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
1152 +
1153 + if (para->density == 256)
1154 + density = DRAM_DCR_CHIP_DENSITY_256M;
1155 + else if (para->density == 512)
1156 + density = DRAM_DCR_CHIP_DENSITY_512M;
1157 + else if (para->density == 1024)
1158 + density = DRAM_DCR_CHIP_DENSITY_1024M;
1159 + else if (para->density == 2048)
1160 + density = DRAM_DCR_CHIP_DENSITY_2048M;
1161 + else if (para->density == 4096)
1162 + density = DRAM_DCR_CHIP_DENSITY_4096M;
1163 + else if (para->density == 8192)
1164 + density = DRAM_DCR_CHIP_DENSITY_8192M;
1165 + else
1166 + density = DRAM_DCR_CHIP_DENSITY_256M;
1167 +
1168 + reg_val |= DRAM_DCR_CHIP_DENSITY(density);
1169 + reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
1170 + reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
1171 + reg_val |= DRAM_DCR_CMD_RANK_ALL;
1172 + reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
1173 + writel(reg_val, &dram->dcr);
1174 +
1175 +#ifdef CONFIG_SUN7I
1176 + setbits_le32(&dram->zqcr1, (0x1 << 24) | (0x1 << 1));
1177 + if (para->tpr4 & 0x2)
1178 + clrsetbits_le32(&dram->zqcr1, (0x1 << 24), (0x1 << 1));
1179 + dramc_clock_output_en(1);
1180 +#endif
1181 +
1182 +#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
1183 + /* set odt impendance divide ratio */
1184 + reg_val = ((para->zq) >> 8) & 0xfffff;
1185 + reg_val |= ((para->zq) & 0xff) << 20;
1186 + reg_val |= (para->zq) & 0xf0000000;
1187 + writel(reg_val, &dram->zqcr0);
1188 +#endif
1189 +
1190 +#ifdef CONFIG_SUN7I
1191 + /* Set CKE Delay to about 1ms */
1192 + setbits_le32(&dram->idcr, 0x1ffff);
1193 +#endif
1194 +
1195 +#ifdef CONFIG_SUN7I
1196 + if ((readl(&dram->ppwrsctl) & 0x1) != 0x1)
1197 + mctl_ddr3_reset();
1198 + else
1199 + setbits_le32(&dram->mcr, DRAM_MCR_RESET);
1200 +#else
1201 + /* dram clock on */
1202 + dramc_clock_output_en(1);
1203 +#endif
1204 +
1205 + udelay(1);
1206 +
1207 + await_completion(&dram->ccr, DRAM_CCR_INIT);
1208 +
1209 + mctl_enable_dllx(para->tpr3);
1210 +
1211 +#ifdef CONFIG_SUN4I
1212 + /* set odt impedance divide ratio */
1213 + reg_val = ((para->zq) >> 8) & 0xfffff;
1214 + reg_val |= ((para->zq) & 0xff) << 20;
1215 + reg_val |= (para->zq) & 0xf0000000;
1216 + writel(reg_val, &dram->zqcr0);
1217 +#endif
1218 +
1219 +#ifdef CONFIG_SUN4I
1220 + /* set I/O configure register */
1221 + reg_val = 0x00cc0000;
1222 + reg_val |= (para->odt_en) & 0x3;
1223 + reg_val |= ((para->odt_en) & 0x3) << 30;
1224 + writel(reg_val, &dram->iocr);
1225 +#endif
1226 +
1227 + /* set refresh period */
1228 + dramc_set_autorefresh_cycle(para->clock, para->type - 2, density);
1229 +
1230 + /* set timing parameters */
1231 + writel(para->tpr0, &dram->tpr0);
1232 + writel(para->tpr1, &dram->tpr1);
1233 + writel(para->tpr2, &dram->tpr2);
1234 +
1235 + if (para->type == DRAM_MEMORY_TYPE_DDR3) {
1236 + reg_val = DRAM_MR_BURST_LENGTH(0x0);
1237 +#if (defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I))
1238 + reg_val |= DRAM_MR_POWER_DOWN;
1239 +#endif
1240 + reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
1241 + reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
1242 + } else if (para->type == DRAM_MEMORY_TYPE_DDR2) {
1243 + reg_val = DRAM_MR_BURST_LENGTH(0x2);
1244 + reg_val |= DRAM_MR_CAS_LAT(para->cas);
1245 + reg_val |= DRAM_MR_WRITE_RECOVERY(0x5);
1246 + }
1247 + writel(reg_val, &dram->mr);
1248 +
1249 + writel(para->emr1, &dram->emr);
1250 + writel(para->emr2, &dram->emr2);
1251 + writel(para->emr3, &dram->emr3);
1252 +
1253 + /* set DQS window mode */
1254 + clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
1255 +
1256 +#ifdef CONFIG_SUN7I
1257 + /* Command rate timing mode 2T & 1T */
1258 + if (para->tpr4 & 0x1)
1259 + setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
1260 +#endif
1261 + /* reset external DRAM */
1262 + setbits_le32(&dram->ccr, DRAM_CCR_INIT);
1263 + await_completion(&dram->ccr, DRAM_CCR_INIT);
1264 +
1265 +#ifdef CONFIG_SUN7I
1266 + /* setup zq calibration manual */
1267 + reg_val = readl(&dram->ppwrsctl);
1268 + if ((reg_val & 0x1) == 1) {
1269 + /* super_standby_flag = 1 */
1270 +
1271 + reg_val = readl(0x01c20c00 + 0x120); /* rtc */
1272 + reg_val &= 0x000fffff;
1273 + reg_val |= 0x17b00000;
1274 + writel(reg_val, &dram->zqcr0);
1275 +
1276 + /* exit self-refresh state */
1277 + clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
1278 + /* check whether command has been executed */
1279 + await_completion(&dram->dcr, 0x1 << 31);
1280 +
1281 + udelay(2);
1282 +
1283 + /* dram pad hold off */
1284 + setbits_le32(&dram->ppwrsctl, 0x16510000);
1285 +
1286 + await_completion(&dram->ppwrsctl, 0x1);
1287 +
1288 + /* exit self-refresh state */
1289 + clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x12 << 27);
1290 +
1291 + /* check whether command has been executed */
1292 + await_completion(&dram->dcr, 0x1 << 31);
1293 +
1294 + udelay(2);
1295 +
1296 + /* issue a refresh command */
1297 + clrsetbits_le32(&dram->dcr, 0x1f << 27, 0x13 << 27);
1298 + await_completion(&dram->dcr, 0x1 << 31);
1299 +
1300 + udelay(2);
1301 + }
1302 +#endif
1303 +
1304 + /* scan read pipe value */
1305 + mctl_itm_enable();
1306 + if (para->tpr3 & (0x1 << 31)) {
1307 + ret_val = dramc_scan_dll_para();
1308 + if (ret_val == 0)
1309 + para->tpr3 =
1310 + (((readl(&dram->dllcr[0]) >> 6) & 0x3f) << 16) |
1311 + (((readl(&dram->dllcr[1]) >> 14) & 0xf) << 0) |
1312 + (((readl(&dram->dllcr[2]) >> 14) & 0xf) << 4) |
1313 + (((readl(&dram->dllcr[3]) >> 14) & 0xf) << 8) |
1314 + (((readl(&dram->dllcr[4]) >> 14) & 0xf) << 12
1315 + );
1316 + } else {
1317 + ret_val = dramc_scan_readpipe();
1318 + }
1319 +
1320 + if (ret_val < 0)
1321 + return 0;
1322 +
1323 + /* configure all host port */
1324 + mctl_configure_hostport();
1325 +
1326 + return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
1327 +}
1328 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/early_print.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/early_print.c
1329 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/early_print.c 1970-01-01 01:00:00.000000000 +0100
1330 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/early_print.c 2014-09-06 16:58:35.317953141 +0200
1331 @@ -0,0 +1,55 @@
1332 +/*
1333 + * (C) Copyright 2007-2012
1334 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
1335 + * Tom Cubie <tangliang@allwinnertech.com>
1336 + *
1337 + * Early uart print for debugging.
1338 + *
1339 + * SPDX-License-Identifier: GPL-2.0+
1340 + */
1341 +
1342 +#include <common.h>
1343 +#include <asm/io.h>
1344 +#include <asm/arch/cpu.h>
1345 +#include <asm/arch/early_print.h>
1346 +#include <asm/arch/gpio.h>
1347 +#include <asm/arch/sys_proto.h>
1348 +
1349 +static int uart_initialized = 0;
1350 +
1351 +#if CONFIG_CONS_INDEX < 5
1352 +#define UART CONFIG_CONS_INDEX-1
1353 +#else
1354 +/* SUNXI_R_UART_BASE */
1355 +#define UART 2922
1356 +#endif
1357 +
1358 +void uart_init(void) {
1359 +
1360 + /* select dll dlh */
1361 + writel(UART_LCR_DLAB, UART_LCR(UART));
1362 + /* set baudrate */
1363 + writel(0, UART_DLH(UART));
1364 + writel(BAUD_115200, UART_DLL(UART));
1365 + /* set line control */
1366 + writel(LC_8_N_1, UART_LCR(UART));
1367 +
1368 + uart_initialized = 1;
1369 +}
1370 +
1371 +#define TX_READY (readl(UART_LSR(UART)) & UART_LSR_TEMT)
1372 +
1373 +void uart_putc(char c) {
1374 +
1375 + while (!TX_READY)
1376 + ;
1377 + writel(c, UART_THR(UART));
1378 +}
1379 +
1380 +void uart_puts(const char *s) {
1381 +
1382 + while (*s)
1383 + uart_putc(*s++);
1384 +}
1385 +
1386 +
1387 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/Makefile u-boot-sunxi/arch/arm/cpu/armv7/sunxi/Makefile
1388 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/Makefile 1970-01-01 01:00:00.000000000 +0100
1389 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/Makefile 2014-09-06 16:58:35.317953141 +0200
1390 @@ -0,0 +1,44 @@
1391 +#
1392 +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
1393 +#
1394 +# Based on some other Makefile
1395 +# (C) Copyright 2000-2003
1396 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
1397 +#
1398 +# SPDX-License-Identifier: GPL-2.0+
1399 +#
1400 +obj-y += timer.o
1401 +obj-y += board.o
1402 +obj-y += clock.o
1403 +obj-y += pinmux.o
1404 +obj-y += watchdog.o
1405 +obj-$(CONFIG_SUN6I) += prcm.o
1406 +obj-$(CONFIG_SUN8I) += prcm.o
1407 +obj-$(CONFIG_SUN6I) += p2wi.o
1408 +obj-$(CONFIG_SUN4I) += clock_sun4i.o
1409 +obj-$(CONFIG_SUN5I) += clock_sun4i.o
1410 +obj-$(CONFIG_SUN6I) += clock_sun6i.o
1411 +obj-$(CONFIG_SUN7I) += clock_sun4i.o
1412 +obj-$(CONFIG_SUN8I) += clock_sun6i.o
1413 +ifdef DEBUG
1414 +obj-y += early_print.o
1415 +endif
1416 +obj-$(CONFIG_BOARD_POSTCLK_INIT) += postclk_init.o
1417 +obj-$(CONFIG_SYS_SECONDARY_ON) += secondary_init.o
1418 +obj-$(CONFIG_SYS_SECONDARY_ON) += smp.o
1419 +
1420 +ifndef CONFIG_SPL_BUILD
1421 +obj-y += cpu_info.o
1422 +ifdef CONFIG_CMD_WATCHDOG
1423 +obj-$(CONFIG_CMD_WATCHDOG) += cmd_watchdog.o
1424 +endif
1425 +endif
1426 +
1427 +ifdef CONFIG_SPL_BUILD
1428 +obj-$(CONFIG_SUN4I) += dram.o
1429 +obj-$(CONFIG_SUN5I) += dram.o
1430 +obj-$(CONFIG_SUN7I) += dram.o
1431 +ifdef CONFIG_SPL_FEL
1432 +obj-y += start.o
1433 +endif
1434 +endif
1435 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/p2wi.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/p2wi.c
1436 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/p2wi.c 1970-01-01 01:00:00.000000000 +0100
1437 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/p2wi.c 2014-09-06 16:58:35.317953141 +0200
1438 @@ -0,0 +1,120 @@
1439 +/*
1440 + * Sunxi A31 Power Management Unit
1441 + *
1442 + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
1443 + * http://linux-sunxi.org
1444 + *
1445 + * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
1446 + *
1447 + * (C) Copyright 2006-2013
1448 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
1449 + * Berg Xing <bergxing@allwinnertech.com>
1450 + * Tom Cubie <tangliang@allwinnertech.com>
1451 + *
1452 + * SPDX-License-Identifier: GPL-2.0+
1453 + */
1454 +
1455 +#include <common.h>
1456 +#include <errno.h>
1457 +#include <asm/io.h>
1458 +#include <asm/arch/cpu.h>
1459 +#include <asm/arch/gpio.h>
1460 +#include <asm/arch/p2wi.h>
1461 +#include <asm/arch/prcm.h>
1462 +#include <asm/arch/clock.h>
1463 +#include <asm/arch/sys_proto.h>
1464 +
1465 +void p2wi_init(void)
1466 +{
1467 + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
1468 +
1469 + /* Enable p2wi and PIO clk, and de-assert their resets */
1470 + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
1471 +
1472 + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
1473 + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
1474 +
1475 + /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
1476 + writel(P2WI_CTRL_RESET, &p2wi->ctrl);
1477 + sdelay(0x100);
1478 + writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
1479 + &p2wi->cc);
1480 +}
1481 +
1482 +int p2wi_set_pmu_address(u8 slave_addr, u8 ctrl_reg, u8 init_data)
1483 +{
1484 + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
1485 + int i;
1486 +
1487 + writel(P2WI_PM_DEV_ADDR(slave_addr) |
1488 + P2WI_PM_CTRL_ADDR(ctrl_reg) |
1489 + P2WI_PM_INIT_DATA(init_data) |
1490 + P2WI_PM_INIT_SEND,
1491 + &p2wi->pm);
1492 + for (i = 0xffffff; i != 0; i--)
1493 + if (!(readl(&p2wi->pm) & P2WI_PM_INIT_SEND))
1494 + break;
1495 + if (readl(&p2wi->pm) & P2WI_PM_INIT_SEND)
1496 + return -EFAULT;
1497 +
1498 + return 0;
1499 +}
1500 +
1501 +int p2wi_read(const u8 addr, u8 *data)
1502 +{
1503 + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
1504 + int i, ret = 0;
1505 + u8 reg;
1506 +
1507 + writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
1508 + writel(P2WI_DATA_NUM_BYTES(1) |
1509 + P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
1510 + writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
1511 + writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
1512 +
1513 + for (i = 0xffffff; i != 0; i--) {
1514 + reg = readl(&p2wi->status);
1515 + if (reg & P2WI_STAT_TRANS_ERR) {
1516 + ret = -EIO;
1517 + break;
1518 + }
1519 + if (reg & P2WI_STAT_TRANS_DONE)
1520 + break;
1521 + }
1522 +
1523 + if (i == 0)
1524 + ret = -ETIME;
1525 +
1526 + *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
1527 + writel(reg, &p2wi->status); /* Clear status bits */
1528 + return ret;
1529 +}
1530 +
1531 +int p2wi_write(const u8 addr, u8 data)
1532 +{
1533 + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
1534 + int i, ret = 0;
1535 + u8 reg;
1536 +
1537 + writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
1538 + writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
1539 + writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
1540 + writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
1541 + writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
1542 +
1543 + for (i = 0xffffff; i != 0; i--) {
1544 + reg = readl(&p2wi->status);
1545 + if (reg & P2WI_STAT_TRANS_ERR) {
1546 + ret = -EIO;
1547 + break;
1548 + }
1549 + if (reg & P2WI_STAT_TRANS_DONE)
1550 + break;
1551 + }
1552 +
1553 + if (i == 0)
1554 + ret = -ETIME;
1555 +
1556 + writel(reg, &p2wi->status); /* Clear status bits */
1557 + return ret;
1558 +}
1559 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/pinmux.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/pinmux.c
1560 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/pinmux.c 1970-01-01 01:00:00.000000000 +0100
1561 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/pinmux.c 2014-09-06 16:58:35.317953141 +0200
1562 @@ -0,0 +1,61 @@
1563 +/*
1564 + * (C) Copyright 2007-2011
1565 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
1566 + * Tom Cubie <tangliang@allwinnertech.com>
1567 + *
1568 + * SPDX-License-Identifier: GPL-2.0+
1569 + */
1570 +
1571 +#include <common.h>
1572 +#include <asm/io.h>
1573 +#include <asm/arch/gpio.h>
1574 +
1575 +int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
1576 +{
1577 + u32 bank = GPIO_BANK(pin);
1578 + u32 index = GPIO_CFG_INDEX(pin);
1579 + u32 offset = GPIO_CFG_OFFSET(pin);
1580 + struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
1581 +
1582 + clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
1583 +
1584 + return 0;
1585 +}
1586 +
1587 +int sunxi_gpio_get_cfgpin(u32 pin)
1588 +{
1589 + u32 cfg;
1590 + u32 bank = GPIO_BANK(pin);
1591 + u32 index = GPIO_CFG_INDEX(pin);
1592 + u32 offset = GPIO_CFG_OFFSET(pin);
1593 + struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
1594 +
1595 + cfg = readl(&pio->cfg[0] + index);
1596 + cfg >>= offset;
1597 +
1598 + return cfg & 0xf;
1599 +}
1600 +
1601 +int sunxi_gpio_set_drv(u32 pin, u32 val)
1602 +{
1603 + u32 bank = GPIO_BANK(pin);
1604 + u32 index = GPIO_DRV_INDEX(pin);
1605 + u32 offset = GPIO_DRV_OFFSET(pin);
1606 + struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
1607 +
1608 + clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
1609 +
1610 + return 0;
1611 +}
1612 +
1613 +int sunxi_gpio_set_pull(u32 pin, u32 val)
1614 +{
1615 + u32 bank = GPIO_BANK(pin);
1616 + u32 index = GPIO_PULL_INDEX(pin);
1617 + u32 offset = GPIO_PULL_OFFSET(pin);
1618 + struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
1619 +
1620 + clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
1621 +
1622 + return 0;
1623 +}
1624 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/postclk_init.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/postclk_init.c
1625 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/postclk_init.c 1970-01-01 01:00:00.000000000 +0100
1626 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/postclk_init.c 2014-09-06 16:58:35.317953141 +0200
1627 @@ -0,0 +1,20 @@
1628 +/*
1629 + * (C) Copyright 2013
1630 + * Carl van Schaik <carl@ok-labs.com>
1631 + *
1632 + * SPDX-License-Identifier: GPL-2.0+
1633 + */
1634 +
1635 +#include <common.h>
1636 +#if defined(CONFIG_SYS_SECONDARY_ON)
1637 +#include <asm/arch/smp.h>
1638 +#endif
1639 +
1640 +
1641 +int board_postclk_init(void)
1642 +{
1643 +#if defined(CONFIG_SYS_SECONDARY_ON)
1644 + startup_secondaries();
1645 +#endif
1646 + return 0;
1647 +}
1648 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/prcm.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/prcm.c
1649 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/prcm.c 1970-01-01 01:00:00.000000000 +0100
1650 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/prcm.c 2014-09-06 16:58:35.317953141 +0200
1651 @@ -0,0 +1,35 @@
1652 +/*
1653 + * Sunxi A31 Power Management Unit
1654 + *
1655 + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
1656 + * http://linux-sunxi.org
1657 + *
1658 + * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
1659 + *
1660 + * (C) Copyright 2006-2013
1661 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
1662 + * Berg Xing <bergxing@allwinnertech.com>
1663 + * Tom Cubie <tangliang@allwinnertech.com>
1664 + *
1665 + * SPDX-License-Identifier: GPL-2.0+
1666 + */
1667 +
1668 +#include <common.h>
1669 +#include <errno.h>
1670 +#include <asm/io.h>
1671 +#include <asm/arch/cpu.h>
1672 +#include <asm/arch/prcm.h>
1673 +#include <asm/arch/sys_proto.h>
1674 +
1675 +/* APB0 clock gate and reset bit offsets are the same. */
1676 +void prcm_apb0_enable(u32 flags)
1677 +{
1678 + struct sunxi_prcm_reg *prcm =
1679 + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
1680 +
1681 + /* open the clock for module */
1682 + setbits_le32(&prcm->apb0_gate, flags);
1683 +
1684 + /* deassert reset for module */
1685 + setbits_le32(&prcm->apb0_reset, flags);
1686 +}
1687 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/secondary_init.S u-boot-sunxi/arch/arm/cpu/armv7/sunxi/secondary_init.S
1688 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/secondary_init.S 1970-01-01 01:00:00.000000000 +0100
1689 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/secondary_init.S 2014-09-06 16:58:35.317953141 +0200
1690 @@ -0,0 +1,31 @@
1691 +/*
1692 + * A lowlevel_init function that sets up the stack to call a C function to
1693 + * perform further init.
1694 + *
1695 + * (C) Copyright 2013
1696 + * Carl van Schaik <carl@ok-labs.com>
1697 + *
1698 + * SPDX-License-Identifier: GPL-2.0+
1699 + */
1700 +#include <asm-offsets.h>
1701 +#include <config.h>
1702 +#include <linux/linkage.h>
1703 +
1704 +ENTRY(secondary_init)
1705 + /* Get cpu number : r5 */
1706 + mrc p15, 0, r5, c0, c0, 5
1707 + and r5, r5, #0xff
1708 +
1709 + /*
1710 + * Setup a secondary stack, each core gets 128 bytes.
1711 + */
1712 + ldr sp, =secondary_stack
1713 + mov r0, #0x80
1714 + add sp, sp, r0, lsl r5
1715 +
1716 + /*
1717 + * Jump to C
1718 + */
1719 + bl secondary_start
1720 +ENDPROC(secondary_init)
1721 +
1722 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/smp.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/smp.c
1723 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/smp.c 1970-01-01 01:00:00.000000000 +0100
1724 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/smp.c 2014-09-06 16:58:35.317953141 +0200
1725 @@ -0,0 +1,80 @@
1726 +/*
1727 + * (C) Copyright 2013
1728 + * Carl van Schaik <carl@ok-labs.com>
1729 + *
1730 + * SPDX-License-Identifier: GPL-2.0+
1731 + */
1732 +
1733 +#include <common.h>
1734 +#include <asm/io.h>
1735 +#include <asm/arch/smp.h>
1736 +#include <asm/arch/cpucfg.h>
1737 +
1738 +/* Right now we assume only a single secondary as in sun7i */
1739 +#if defined(CONFIG_SUN7I)
1740 +#define NUM_CORES 2
1741 +#else
1742 +#error unsupported SoC
1743 +#endif
1744 +
1745 +static void secondary_pen(void)
1746 +{
1747 + struct sunxi_cpucfg *cpucfg = (struct sunxi_cpucfg *)SUNXI_CPUCFG_BASE;
1748 +
1749 + while (1) {
1750 + __asm__ __volatile__("wfe" ::: "memory");
1751 +
1752 + unsigned long boot_addr = readl(&cpucfg->boot_addr);
1753 +
1754 + __asm__ __volatile__(
1755 + "mov r14, %0 \n"
1756 + "bx r14 \n"
1757 + : : "r" (boot_addr)
1758 + );
1759 + };
1760 +}
1761 +
1762 +u32 secondary_stack[32*(NUM_CORES-1)];
1763 +
1764 +void secondary_start(void)
1765 +{
1766 + secondary_pen();
1767 +}
1768 +
1769 +/* Power on secondaries */
1770 +void startup_secondaries(void)
1771 +{
1772 + int i;
1773 + struct sunxi_cpucfg *cpucfg = (struct sunxi_cpucfg *)SUNXI_CPUCFG_BASE;
1774 +
1775 + writel((u32)secondary_init, &cpucfg->boot_addr);
1776 +
1777 + for (i = 1; i < NUM_CORES; i++) {
1778 + /* Assert CPU reset just in case */
1779 + writel(CPU_RESET_SET, &cpucfg->cpu[i].reset_ctrl);
1780 + /* Ensure CPU reset also invalidates L1 caches */
1781 + clrbits_le32(&cpucfg->general_ctrl,
1782 + GENERAL_CTRL_NO_L1_RESET_CPU(i));
1783 + /* Lock CPU */
1784 + clrbits_le32(&cpucfg->debug1_ctrl, 1 << i);
1785 +
1786 + /* Ramp up power to CPU1 */
1787 + assert(i == 1);
1788 + u32 j = 0xff << 1;
1789 + do {
1790 + j = j >> 1;
1791 + writel(j, &cpucfg->cpu1_power_clamp);
1792 + } while (j != 0);
1793 +
1794 + udelay(10*1000); /* 10ms */
1795 +
1796 + clrbits_le32(&cpucfg->cpu1_power_off, 1);
1797 + /* Release CPU reset */
1798 + writel(CPU_RESET_CLEAR, &cpucfg->cpu[i].reset_ctrl);
1799 +
1800 + /* Unlock CPU */
1801 + setbits_le32(&cpucfg->debug1_ctrl, 1 << i);
1802 +
1803 + printf("Secondary CPU%d power-on\n", i);
1804 + }
1805 +}
1806 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/start.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/start.c
1807 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/start.c 1970-01-01 01:00:00.000000000 +0100
1808 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/start.c 2014-09-06 16:58:35.317953141 +0200
1809 @@ -0,0 +1 @@
1810 +/* Intentionally empty. Only needed to get FEL SPL link line right */
1811 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/timer.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/timer.c
1812 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/timer.c 1970-01-01 01:00:00.000000000 +0100
1813 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/timer.c 2014-09-06 16:58:35.317953141 +0200
1814 @@ -0,0 +1,113 @@
1815 +/*
1816 + * (C) Copyright 2007-2011
1817 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
1818 + * Tom Cubie <tangliang@allwinnertech.com>
1819 + *
1820 + * SPDX-License-Identifier: GPL-2.0+
1821 + */
1822 +
1823 +#include <common.h>
1824 +#include <asm/io.h>
1825 +#include <asm/arch/timer.h>
1826 +
1827 +DECLARE_GLOBAL_DATA_PTR;
1828 +
1829 +#define TIMER_MODE (0x0 << 7) /* continuous mode */
1830 +#define TIMER_DIV (0x0 << 4) /* pre scale 1 */
1831 +#define TIMER_SRC (0x1 << 2) /* osc24m */
1832 +#define TIMER_RELOAD (0x1 << 1) /* reload internal value */
1833 +#define TIMER_EN (0x1 << 0) /* enable timer */
1834 +
1835 +#define TIMER_CLOCK (24 * 1000 * 1000)
1836 +#define COUNT_TO_USEC(x) ((x) / 24)
1837 +#define USEC_TO_COUNT(x) ((x) * 24)
1838 +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
1839 +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
1840 +
1841 +#define TIMER_LOAD_VAL 0xffffffff
1842 +
1843 +#define TIMER_NUM 0 /* we use timer 0 */
1844 +
1845 +/* read the 32-bit timer */
1846 +static ulong read_timer(void)
1847 +{
1848 + struct sunxi_timer_reg *timers =
1849 + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
1850 + struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
1851 +
1852 + /*
1853 + * The hardware timer counts down, therefore we invert to
1854 + * produce an incrementing timer.
1855 + */
1856 + return ~readl(&timer->val);
1857 +}
1858 +
1859 +/* init timer register */
1860 +int timer_init(void)
1861 +{
1862 + struct sunxi_timer_reg *timers =
1863 + (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
1864 + struct sunxi_timer *timer = &timers->timer[TIMER_NUM];
1865 + writel(TIMER_LOAD_VAL, &timer->inter);
1866 + writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN,
1867 + &timer->ctl);
1868 +
1869 + return 0;
1870 +}
1871 +
1872 +/* timer without interrupts */
1873 +ulong get_timer(ulong base)
1874 +{
1875 + return get_timer_masked() - base;
1876 +}
1877 +
1878 +ulong get_timer_masked(void)
1879 +{
1880 + /* current tick value */
1881 + ulong now = TICKS_TO_HZ(read_timer());
1882 +
1883 + if (now >= gd->arch.lastinc) /* normal (non rollover) */
1884 + gd->arch.tbl += (now - gd->arch.lastinc);
1885 + else {
1886 + /* rollover */
1887 + gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL)
1888 + - gd->arch.lastinc) + now;
1889 + }
1890 + gd->arch.lastinc = now;
1891 +
1892 + return gd->arch.tbl;
1893 +}
1894 +
1895 +/* delay x useconds */
1896 +void __udelay(unsigned long usec)
1897 +{
1898 + long tmo = USEC_TO_COUNT(usec);
1899 + ulong now, last = read_timer();
1900 +
1901 + while (tmo > 0) {
1902 + now = read_timer();
1903 + if (now > last) /* normal (non rollover) */
1904 + tmo -= now - last;
1905 + else /* rollover */
1906 + tmo -= TIMER_LOAD_VAL - last + now;
1907 + last = now;
1908 + }
1909 +}
1910 +
1911 +/*
1912 + * This function is derived from PowerPC code (read timebase as long long).
1913 + * On ARM it just returns the timer value.
1914 + */
1915 +unsigned long long get_ticks(void)
1916 +{
1917 + return get_timer(0);
1918 +}
1919 +
1920 +/*
1921 + * This function is derived from PowerPC code (timebase clock frequency).
1922 + * On ARM it returns the number of timer ticks per second.
1923 + */
1924 +ulong get_tbclk(void)
1925 +{
1926 + return CONFIG_SYS_HZ;
1927 +}
1928 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
1929 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds 1970-01-01 01:00:00.000000000 +0100
1930 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds 2014-09-06 16:58:35.317953141 +0200
1931 @@ -0,0 +1,77 @@
1932 +/*
1933 + * (C) Copyright 2013
1934 + * Henrik Nordstrom <henrik@henriknordstrom.net>
1935 + *
1936 + * SPDX-License-Identifier: GPL-2.0+
1937 + */
1938 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
1939 +OUTPUT_ARCH(arm)
1940 +ENTRY(s_init)
1941 +SECTIONS
1942 +{
1943 + . = 0x00002000;
1944 +
1945 + . = ALIGN(4);
1946 + .text :
1947 + {
1948 + *(.text.s_init)
1949 + *(.text*)
1950 + }
1951 +
1952 + . = ALIGN(4);
1953 + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
1954 +
1955 + . = ALIGN(4);
1956 + .data : {
1957 + *(.data*)
1958 + }
1959 +
1960 + . = ALIGN(4);
1961 + . = .;
1962 +
1963 + . = ALIGN(4);
1964 + .rel.dyn : {
1965 + __rel_dyn_start = .;
1966 + *(.rel*)
1967 + __rel_dyn_end = .;
1968 + }
1969 +
1970 + .dynsym : {
1971 + __dynsym_start = .;
1972 + *(.dynsym)
1973 + }
1974 +
1975 + . = ALIGN(4);
1976 + .note.gnu.build-id :
1977 + {
1978 + *(.note.gnu.build-id)
1979 + }
1980 + _end = .;
1981 +
1982 + . = ALIGN(4096);
1983 + .mmutable : {
1984 + *(.mmutable)
1985 + }
1986 +
1987 + .bss_start __rel_dyn_start (OVERLAY) : {
1988 + KEEP(*(.__bss_start));
1989 + __bss_base = .;
1990 + }
1991 +
1992 + .bss __bss_base (OVERLAY) : {
1993 + *(.bss*)
1994 + . = ALIGN(4);
1995 + __bss_limit = .;
1996 + }
1997 +
1998 + .bss_end __bss_limit (OVERLAY) : {
1999 + KEEP(*(.__bss_end));
2000 + }
2001 +
2002 + /DISCARD/ : { *(.dynstr*) }
2003 + /DISCARD/ : { *(.dynamic*) }
2004 + /DISCARD/ : { *(.plt*) }
2005 + /DISCARD/ : { *(.interp*) }
2006 + /DISCARD/ : { *(.gnu*) }
2007 + /DISCARD/ : { *(.note*) }
2008 +}
2009 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds
2010 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds 1970-01-01 01:00:00.000000000 +0100
2011 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds 2014-09-06 16:58:35.317953141 +0200
2012 @@ -0,0 +1,52 @@
2013 +/*
2014 + * (C) Copyright 2012
2015 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
2016 + * Tom Cubie <tangliang@allwinnertech.com>
2017 + *
2018 + * Based on omap-common/u-boot-spl.lds:
2019 + *
2020 + * (C) Copyright 2002
2021 + * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
2022 + *
2023 + * (C) Copyright 2010
2024 + * Texas Instruments, <www.ti.com>
2025 + * Aneesh V <aneesh@ti.com>
2026 + *
2027 + * SPDX-License-Identifier: GPL-2.0+
2028 + */
2029 +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\
2030 + LENGTH = CONFIG_SPL_MAX_SIZE }
2031 +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
2032 + LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
2033 +
2034 +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
2035 +OUTPUT_ARCH(arm)
2036 +ENTRY(_start)
2037 +SECTIONS
2038 +{
2039 + .text :
2040 + {
2041 + __start = .;
2042 + arch/arm/cpu/armv7/start.o (.text)
2043 + *(.text*)
2044 + } > .sram
2045 +
2046 + . = ALIGN(4);
2047 + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
2048 +
2049 + . = ALIGN(4);
2050 + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
2051 +
2052 + . = ALIGN(4);
2053 + __image_copy_end = .;
2054 + _end = .;
2055 +
2056 + .bss :
2057 + {
2058 + . = ALIGN(4);
2059 + __bss_start = .;
2060 + *(.bss*)
2061 + . = ALIGN(4);
2062 + __bss_end = .;
2063 + } > .sdram
2064 +}
2065 diff -ruN u-boot-2014.04/arch/arm/cpu/armv7/sunxi/watchdog.c u-boot-sunxi/arch/arm/cpu/armv7/sunxi/watchdog.c
2066 --- u-boot-2014.04/arch/arm/cpu/armv7/sunxi/watchdog.c 1970-01-01 01:00:00.000000000 +0100
2067 +++ u-boot-sunxi/arch/arm/cpu/armv7/sunxi/watchdog.c 2014-09-06 16:58:35.317953141 +0200
2068 @@ -0,0 +1,83 @@
2069 +/*
2070 + * Watchdog driver for the Allwinner sunxi platform.
2071 + * Copyright (C) 2013 Oliver Schinagl <oliver@schinagl.nl>
2072 + * http://www.linux-sunxi.org/
2073 + *
2074 + * SPDX-License-Identifier: GPL-2.0+
2075 + */
2076 +
2077 +#include <asm/io.h>
2078 +#include <asm/arch/timer.h>
2079 +#include <asm/arch/watchdog.h>
2080 +#include <common.h>
2081 +#include <watchdog.h>
2082 +
2083 +
2084 +#define WDT_CTRL_RESTART (0x1 << 0)
2085 +#define WDT_CTRL_KEY (0x0a57 << 1)
2086 +
2087 +#define WDT_MODE_EN (0x1 << 0)
2088 +#define WDT_MODE_RESET_EN (0x1 << 1)
2089 +#define WDT_MAX_TIMEOUT 16
2090 +#define WDT_MODE_TIMEOUT(n) \
2091 + (wdt_timeout_map[(n) < WDT_MAX_TIMEOUT ? (n) : WDT_MAX_TIMEOUT] << 3)
2092 +
2093 +
2094 +/*
2095 + * Watchdog timeout table. The sunxi cores only use 4 bits for the watchdog as
2096 + * set by the table below. The gaps are filled by rounding up to the next
2097 + * second up.
2098 + */
2099 +const unsigned int wdt_timeout_map[] = {
2100 + [0] = 0b0000, /* 0.5s*/
2101 + [1] = 0b0001, /* 1s */
2102 + [2] = 0b0010, /* 2s */
2103 + [3] = 0b0011, /* 3s */
2104 + [4] = 0b0100, /* 4s */
2105 + [5] = 0b0101, /* 5s */
2106 + [6] = 0b0110, /* 6s */
2107 + [7] = 0b0111, /* 8s */
2108 + [8] = 0b0111, /* 8s */
2109 + [9] = 0b1000, /* 10s */
2110 + [10] = 0b1000, /* 10s */
2111 + [11] = 0b1001, /* 12s */
2112 + [12] = 0b1001, /* 12s */
2113 + [13] = 0b1010, /* 14s */
2114 + [14] = 0b1010, /* 14s */
2115 + [15] = 0b1011, /* 16s */
2116 + [16] = 0b1011, /* 16s */
2117 +};
2118 +
2119 +
2120 +void watchdog_reset(void)
2121 +{
2122 + static const struct sunxi_wdog *wdog =
2123 + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
2124 +
2125 + writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
2126 +}
2127 +
2128 +void watchdog_set(int timeout)
2129 +{
2130 + static struct sunxi_wdog *const wdog =
2131 + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
2132 +
2133 + /* Set timeout, reset & enable */
2134 + if (timeout >= 0) {
2135 + writel(WDT_MODE_TIMEOUT(timeout) |
2136 + WDT_MODE_RESET_EN | WDT_MODE_EN,
2137 + &wdog->mode);
2138 + } else {
2139 + writel(0, &wdog->mode);
2140 + }
2141 + watchdog_reset();
2142 +}
2143 +
2144 +void watchdog_init(void)
2145 +{
2146 +#ifdef CONFIG_WATCHDOG
2147 + watchdog_set(WDT_MAX_TIMEOUT);
2148 +#else
2149 + watchdog_set(WDT_OFF); /* no timeout */
2150 +#endif
2151 +}
2152 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock.h
2153 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock.h 1970-01-01 01:00:00.000000000 +0100
2154 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock.h 2014-09-06 16:58:35.381953139 +0200
2155 @@ -0,0 +1,33 @@
2156 +/*
2157 + * (C) Copyright 2007-2011
2158 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
2159 + * Tom Cubie <tangliang@allwinnertech.com>
2160 + *
2161 + * SPDX-License-Identifier: GPL-2.0+
2162 + */
2163 +
2164 +#ifndef _SUNXI_CLOCK_H
2165 +#define _SUNXI_CLOCK_H
2166 +
2167 +#include <linux/types.h>
2168 +
2169 +#define CLK_GATE_OPEN 0x1
2170 +#define CLK_GATE_CLOSE 0x0
2171 +
2172 +/* clock control module regs definition */
2173 +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
2174 +#include <asm/arch/clock_sun6i.h>
2175 +#else
2176 +#include <asm/arch/clock_sun4i.h>
2177 +#endif
2178 +
2179 +#ifndef __ASSEMBLY__
2180 +int clock_init(void);
2181 +int clock_twi_onoff(int port, int state);
2182 +void clock_set_pll1(unsigned int hz);
2183 +unsigned int clock_get_pll6(void);
2184 +void clock_init_safe(void);
2185 +void clock_init_uart(void);
2186 +#endif
2187 +
2188 +#endif /* _SUNXI_CLOCK_H */
2189 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock_sun4i.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
2190 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock_sun4i.h 1970-01-01 01:00:00.000000000 +0100
2191 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock_sun4i.h 2014-09-06 16:58:35.381953139 +0200
2192 @@ -0,0 +1,256 @@
2193 +/*
2194 + * sun4i, sun5i and sun7i clock register definitions
2195 + *
2196 + * (C) Copyright 2007-2011
2197 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
2198 + * Tom Cubie <tangliang@allwinnertech.com>
2199 + *
2200 + * SPDX-License-Identifier: GPL-2.0+
2201 + */
2202 +
2203 +#ifndef _SUNXI_CLOCK_SUN4I_H
2204 +#define _SUNXI_CLOCK_SUN4I_H
2205 +
2206 +struct sunxi_ccm_reg {
2207 + u32 pll1_cfg; /* 0x00 pll1 control */
2208 + u32 pll1_tun; /* 0x04 pll1 tuning */
2209 + u32 pll2_cfg; /* 0x08 pll2 control */
2210 + u32 pll2_tun; /* 0x0c pll2 tuning */
2211 + u32 pll3_cfg; /* 0x10 pll3 control */
2212 + u8 res0[0x4];
2213 + u32 pll4_cfg; /* 0x18 pll4 control */
2214 + u8 res1[0x4];
2215 + u32 pll5_cfg; /* 0x20 pll5 control */
2216 + u32 pll5_tun; /* 0x24 pll5 tuning */
2217 + u32 pll6_cfg; /* 0x28 pll6 control */
2218 + u32 pll6_tun; /* 0x2c pll6 tuning */
2219 + u32 pll7_cfg; /* 0x30 pll7 control */
2220 + u32 pll1_tun2; /* 0x34 pll5 tuning2 */
2221 + u8 res2[0x4];
2222 + u32 pll5_tun2; /* 0x3c pll5 tuning2 */
2223 + u8 res3[0xc];
2224 + u32 pll_lock_dbg; /* 0x4c pll lock time debug */
2225 + u32 osc24m_cfg; /* 0x50 osc24m control */
2226 + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */
2227 + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */
2228 + u32 axi_gate; /* 0x5c axi module clock gating */
2229 + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
2230 + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
2231 + u32 apb0_gate; /* 0x68 apb0 module clock gating */
2232 + u32 apb1_gate; /* 0x6c apb1 module clock gating */
2233 + u8 res4[0x10];
2234 + u32 nand_sclk_cfg; /* 0x80 nand sub clock control */
2235 + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */
2236 + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
2237 + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
2238 + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
2239 + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
2240 + u32 ts_clk_cfg; /* 0x98 transport stream clock control */
2241 + u32 ss_clk_cfg; /* 0x9c */
2242 + u32 spi0_clk_cfg; /* 0xa0 */
2243 + u32 spi1_clk_cfg; /* 0xa4 */
2244 + u32 spi2_clk_cfg; /* 0xa8 */
2245 + u32 pata_clk_cfg; /* 0xac */
2246 + u32 ir0_clk_cfg; /* 0xb0 */
2247 + u32 ir1_clk_cfg; /* 0xb4 */
2248 + u32 iis_clk_cfg; /* 0xb8 */
2249 + u32 ac97_clk_cfg; /* 0xbc */
2250 + u32 spdif_clk_cfg; /* 0xc0 */
2251 + u32 keypad_clk_cfg; /* 0xc4 */
2252 + u32 sata_clk_cfg; /* 0xc8 */
2253 + u32 usb_clk_cfg; /* 0xcc */
2254 + u32 gps_clk_cfg; /* 0xd0 */
2255 + u32 spi3_clk_cfg; /* 0xd4 */
2256 + u8 res5[0x28];
2257 + u32 dram_clk_cfg; /* 0x100 */
2258 + u32 be0_clk_cfg; /* 0x104 */
2259 + u32 be1_clk_cfg; /* 0x108 */
2260 + u32 fe0_clk_cfg; /* 0x10c */
2261 + u32 fe1_clk_cfg; /* 0x110 */
2262 + u32 mp_clk_cfg; /* 0x114 */
2263 + u32 lcd0_ch0_clk_cfg; /* 0x118 */
2264 + u32 lcd1_ch0_clk_cfg; /* 0x11c */
2265 + u32 csi_isp_clk_cfg; /* 0x120 */
2266 + u8 res6[0x4];
2267 + u32 tvd_clk_reg; /* 0x128 */
2268 + u32 lcd0_ch1_clk_cfg; /* 0x12c */
2269 + u32 lcd1_ch1_clk_cfg; /* 0x130 */
2270 + u32 csi0_clk_cfg; /* 0x134 */
2271 + u32 csi1_clk_cfg; /* 0x138 */
2272 + u32 ve_clk_cfg; /* 0x13c */
2273 + u32 audio_codec_clk_cfg; /* 0x140 */
2274 + u32 avs_clk_cfg; /* 0x144 */
2275 + u32 ace_clk_cfg; /* 0x148 */
2276 + u32 lvds_clk_cfg; /* 0x14c */
2277 + u32 hdmi_clk_cfg; /* 0x150 */
2278 + u32 mali_clk_cfg; /* 0x154 */
2279 + u8 res7[0x4];
2280 + u32 mbus_clk_cfg; /* 0x15c */
2281 + u8 res8[0x4];
2282 + u32 gmac_clk_cfg; /* 0x164 */
2283 +};
2284 +
2285 +/* apb1 bit field */
2286 +#define APB1_CLK_SRC_OSC24M (0x0 << 24)
2287 +#define APB1_CLK_SRC_PLL6 (0x1 << 24)
2288 +#define APB1_CLK_SRC_LOSC (0x2 << 24)
2289 +#define APB1_CLK_SRC_MASK (0x3 << 24)
2290 +#define APB1_CLK_RATE_N_1 (0x0 << 16)
2291 +#define APB1_CLK_RATE_N_2 (0x1 << 16)
2292 +#define APB1_CLK_RATE_N_4 (0x2 << 16)
2293 +#define APB1_CLK_RATE_N_8 (0x3 << 16)
2294 +#define APB1_CLK_RATE_N_MASK (3 << 16)
2295 +#define APB1_CLK_RATE_M(m) (((m)-1) << 0)
2296 +#define APB1_CLK_RATE_M_MASK (0x1f << 0)
2297 +
2298 +/* apb1 gate field */
2299 +#define APB1_GATE_UART_SHIFT (16)
2300 +#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT)
2301 +#define APB1_GATE_TWI_SHIFT (0)
2302 +#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT)
2303 +
2304 +/* clock divide */
2305 +#define AXI_DIV_SHIFT (0)
2306 +#define AXI_DIV_1 0
2307 +#define AXI_DIV_2 1
2308 +#define AXI_DIV_3 2
2309 +#define AXI_DIV_4 3
2310 +#define AHB_DIV_SHIFT (4)
2311 +#define AHB_DIV_1 0
2312 +#define AHB_DIV_2 1
2313 +#define AHB_DIV_4 2
2314 +#define AHB_DIV_8 3
2315 +#define APB0_DIV_SHIFT (8)
2316 +#define APB0_DIV_1 0
2317 +#define APB0_DIV_2 1
2318 +#define APB0_DIV_4 2
2319 +#define APB0_DIV_8 3
2320 +#define CPU_CLK_SRC_SHIFT (16)
2321 +#define CPU_CLK_SRC_OSC24M 1
2322 +#define CPU_CLK_SRC_PLL1 2
2323 +
2324 +#define CCM_PLL1_CFG_ENABLE_SHIFT 31
2325 +#define CCM_PLL1_CFG_VCO_RST_SHIFT 30
2326 +#define CCM_PLL1_CFG_VCO_BIAS_SHIFT 26
2327 +#define CCM_PLL1_CFG_PLL4_EXCH_SHIFT 25
2328 +#define CCM_PLL1_CFG_BIAS_CUR_SHIFT 20
2329 +#define CCM_PLL1_CFG_DIVP_SHIFT 16
2330 +#define CCM_PLL1_CFG_LCK_TMR_SHIFT 13
2331 +#define CCM_PLL1_CFG_FACTOR_N_SHIFT 8
2332 +#define CCM_PLL1_CFG_FACTOR_K_SHIFT 4
2333 +#define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT 3
2334 +#define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT 2
2335 +#define CCM_PLL1_CFG_FACTOR_M_SHIFT 0
2336 +
2337 +#define PLL1_CFG_DEFAULT 0xa1005000
2338 +
2339 +#define PLL6_CFG_DEFAULT 0xa1009911
2340 +
2341 +/* nand clock */
2342 +#define NAND_CLK_SRC_OSC24 0
2343 +#define NAND_CLK_DIV_N 0
2344 +#define NAND_CLK_DIV_M 0
2345 +
2346 +/* gps clock */
2347 +#define GPS_SCLK_GATING_OFF 0
2348 +#define GPS_RESET 0
2349 +
2350 +/* ahb clock gate bit offset */
2351 +#define AHB_GATE_OFFSET_GPS 26
2352 +#define AHB_GATE_OFFSET_SATA 25
2353 +#define AHB_GATE_OFFSET_PATA 24
2354 +#define AHB_GATE_OFFSET_SPI3 23
2355 +#define AHB_GATE_OFFSET_SPI2 22
2356 +#define AHB_GATE_OFFSET_SPI1 21
2357 +#define AHB_GATE_OFFSET_SPI0 20
2358 +#define AHB_GATE_OFFSET_TS0 18
2359 +#define AHB_GATE_OFFSET_EMAC 17
2360 +#define AHB_GATE_OFFSET_ACE 16
2361 +#define AHB_GATE_OFFSET_DLL 15
2362 +#define AHB_GATE_OFFSET_SDRAM 14
2363 +#define AHB_GATE_OFFSET_NAND 13
2364 +#define AHB_GATE_OFFSET_MS 12
2365 +#define AHB_GATE_OFFSET_MMC3 11
2366 +#define AHB_GATE_OFFSET_MMC2 10
2367 +#define AHB_GATE_OFFSET_MMC1 9
2368 +#define AHB_GATE_OFFSET_MMC0 8
2369 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
2370 +#define AHB_GATE_OFFSET_BIST 7
2371 +#define AHB_GATE_OFFSET_DMA 6
2372 +#define AHB_GATE_OFFSET_SS 5
2373 +#define AHB_GATE_OFFSET_USB_OHCI1 4
2374 +#define AHB_GATE_OFFSET_USB_EHCI1 3
2375 +#define AHB_GATE_OFFSET_USB_OHCI0 2
2376 +#define AHB_GATE_OFFSET_USB_EHCI0 1
2377 +#define AHB_GATE_OFFSET_USB 0
2378 +
2379 +/* ahb clock gate bit offset (second register) */
2380 +#define AHB_GATE_OFFSET_GMAC 17
2381 +
2382 +#define CCM_AHB_GATE_GPS (0x1 << 26)
2383 +#define CCM_AHB_GATE_SDRAM (0x1 << 14)
2384 +#define CCM_AHB_GATE_DLL (0x1 << 15)
2385 +#define CCM_AHB_GATE_ACE (0x1 << 16)
2386 +
2387 +#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0)
2388 +#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3)
2389 +#define CCM_PLL5_CTRL_M_X(n) ((n) - 1)
2390 +#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2)
2391 +#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3)
2392 +#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1)
2393 +#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4)
2394 +#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3)
2395 +#define CCM_PLL5_CTRL_K_X(n) ((n) - 1)
2396 +#define CCM_PLL5_CTRL_LDO (0x1 << 7)
2397 +#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8)
2398 +#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f)
2399 +#define CCM_PLL5_CTRL_N_X(n) (n)
2400 +#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16)
2401 +#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3)
2402 +#define CCM_PLL5_CTRL_P_X(n) ((n) - 1)
2403 +#define CCM_PLL5_CTRL_BW (0x1 << 18)
2404 +#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19)
2405 +#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20)
2406 +#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f)
2407 +#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1)
2408 +#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25)
2409 +#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29)
2410 +#define CCM_PLL5_CTRL_BYPASS (0x1 << 30)
2411 +#define CCM_PLL5_CTRL_EN (0x1 << 31)
2412 +
2413 +#define CCM_PLL6_CTRL_N_SHIFT 8
2414 +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
2415 +#define CCM_PLL6_CTRL_K_SHIFT 4
2416 +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
2417 +
2418 +#define CCM_GPS_CTRL_RESET (0x1 << 0)
2419 +#define CCM_GPS_CTRL_GATE (0x1 << 1)
2420 +
2421 +#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15)
2422 +
2423 +#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0)
2424 +#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf)
2425 +#define CCM_MBUS_CTRL_M_X(n) ((n) - 1)
2426 +#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16)
2427 +#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf)
2428 +#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0)))
2429 +#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24)
2430 +#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3)
2431 +#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0
2432 +#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1
2433 +#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2
2434 +#define CCM_MBUS_CTRL_GATE (0x1 << 31)
2435 +
2436 +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
2437 +#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
2438 +#define CCM_MMC_CTRL_PLL5 (0x2 << 24)
2439 +
2440 +#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
2441 +
2442 +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
2443 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
2444 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
2445 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
2446 +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
2447 +
2448 +#endif /* _SUNXI_CLOCK_SUN4I_H */
2449 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock_sun6i.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
2450 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 1970-01-01 01:00:00.000000000 +0100
2451 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/clock_sun6i.h 2014-09-06 16:58:35.381953139 +0200
2452 @@ -0,0 +1,205 @@
2453 +/*
2454 + * sun6i clock register definitions
2455 + *
2456 + * (C) Copyright 2007-2011
2457 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
2458 + * Tom Cubie <tangliang@allwinnertech.com>
2459 + *
2460 + * SPDX-License-Identifier: GPL-2.0+
2461 + */
2462 +
2463 +#ifndef _SUNXI_CLOCK_SUN6I_H
2464 +#define _SUNXI_CLOCK_SUN6I_H
2465 +
2466 +struct sunxi_ccm_reg {
2467 + u32 pll1_cfg; /* 0x00 pll1 control */
2468 + u32 reserved0;
2469 + u32 pll2_cfg; /* 0x08 pll2 control */
2470 + u32 reserved1;
2471 + u32 pll3_cfg; /* 0x10 pll3 control */
2472 + u32 reserved2;
2473 + u32 pll4_cfg; /* 0x18 pll4 control */
2474 + u32 reserved3;
2475 + u32 pll5_cfg; /* 0x20 pll5 control */
2476 + u32 reserved4;
2477 + u32 pll6_cfg; /* 0x28 pll6 control */
2478 + u32 reserved5;
2479 + u32 pll7_cfg; /* 0x30 pll7 control */
2480 + u32 reserved6;
2481 + u32 pll8_cfg; /* 0x38 pll8 control */
2482 + u32 reserved7;
2483 + u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
2484 + u32 pll9_cfg; /* 0x44 pll9 control */
2485 + u32 pll10_cfg; /* 0x48 pll10 control */
2486 + u32 reserved8;
2487 + u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
2488 + u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
2489 + u32 apb2_div; /* 0x58 APB2 divide ratio */
2490 + u32 axi_gate; /* 0x5c axi module clock gating */
2491 + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */
2492 + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
2493 + u32 apb1_gate; /* 0x68 apb1 module clock gating */
2494 + u32 apb2_gate; /* 0x6c apb2 module clock gating */
2495 + u32 reserved9[4];
2496 + u32 nand0_clk_cfg; /* 0x80 nand0 clock control */
2497 + u32 nand1_clk_cfg; /* 0x84 nand1 clock control */
2498 + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
2499 + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */
2500 + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */
2501 + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */
2502 + u32 ts_clk_cfg; /* 0x98 transport stream clock control */
2503 + u32 ss_clk_cfg; /* 0x9c security system clock control */
2504 + u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */
2505 + u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */
2506 + u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */
2507 + u32 spi3_clk_cfg; /* 0xac spi3 clock control */
2508 + u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/
2509 + u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */
2510 + u32 reserved10[2];
2511 + u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */
2512 + u32 reserved11[2];
2513 + u32 usb_clk_cfg; /* 0xcc USB clock control */
2514 + u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */
2515 + u32 reserved12[7];
2516 + u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
2517 + u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
2518 + u32 reserved13[2];
2519 + u32 dram_clk_gate; /* 0x100 DRAM module gating */
2520 + u32 be0_clk_cfg; /* 0x104 BE0 module clock */
2521 + u32 be1_clk_cfg; /* 0x108 BE1 module clock */
2522 + u32 fe0_clk_cfg; /* 0x10c FE0 module clock */
2523 + u32 fe1_clk_cfg; /* 0x110 FE1 module clock */
2524 + u32 mp_clk_cfg; /* 0x114 MP module clock */
2525 + u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */
2526 + u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */
2527 + u32 reserved14[3];
2528 + u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */
2529 + u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */
2530 + u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */
2531 + u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */
2532 + u32 ve_clk_cfg; /* 0x13c VE module clock */
2533 + u32 adda_clk_cfg; /* 0x140 ADDA module clock */
2534 + u32 avs_clk_cfg; /* 0x144 AVS module clock */
2535 + u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/
2536 + u32 reserved15;
2537 + u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */
2538 + u32 ps_clk_cfg; /* 0x154 PS module clock */
2539 + u32 mtc_clk_cfg; /* 0x158 MTC module clock */
2540 + u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */
2541 + u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */
2542 + u32 reserved16;
2543 + u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */
2544 + u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */
2545 + u32 reserved17[4];
2546 + u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */
2547 + u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */
2548 + u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */
2549 + u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */
2550 + u32 reserved18[4];
2551 + u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */
2552 + u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */
2553 + u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */
2554 + u32 reserved19[21];
2555 + u32 pll_lock; /* 0x200 PLL Lock Time */
2556 + u32 pll1_lock; /* 0x204 PLL1 Lock Time */
2557 + u32 reserved20[6];
2558 + u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */
2559 + u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */
2560 + u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */
2561 + u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */
2562 + u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */
2563 + u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */
2564 + u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */
2565 + u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */
2566 + u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */
2567 + u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */
2568 + u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */
2569 + u32 reserved21[13];
2570 + u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */
2571 + u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */
2572 + u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */
2573 + u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */
2574 + u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */
2575 + u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */
2576 + u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */
2577 + u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */
2578 + u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
2579 + u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
2580 + u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
2581 + u32 reserved22[5];
2582 + u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
2583 + u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
2584 + u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
2585 + u32 reserved23;
2586 + u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
2587 + u32 reserved24;
2588 + u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
2589 +};
2590 +
2591 +/* apb2 bit field */
2592 +#define APB2_CLK_SRC_LOSC (0x0 << 24)
2593 +#define APB2_CLK_SRC_OSC24M (0x1 << 24)
2594 +#define APB2_CLK_SRC_PLL6 (0x2 << 24)
2595 +#define APB2_CLK_SRC_MASK (0x3 << 24)
2596 +#define APB2_CLK_RATE_N_1 (0x0 << 16)
2597 +#define APB2_CLK_RATE_N_2 (0x1 << 16)
2598 +#define APB2_CLK_RATE_N_4 (0x2 << 16)
2599 +#define APB2_CLK_RATE_N_8 (0x3 << 16)
2600 +#define APB2_CLK_RATE_N_MASK (3 << 16)
2601 +#define APB2_CLK_RATE_M(m) (((m)-1) << 0)
2602 +#define APB2_CLK_RATE_M_MASK (0x1f << 0)
2603 +
2604 +/* apb2 gate field */
2605 +#define APB2_GATE_UART_SHIFT (16)
2606 +#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT)
2607 +#define APB2_GATE_TWI_SHIFT (0)
2608 +#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT)
2609 +
2610 +/* cpu_axi_cfg bits */
2611 +#define AXI_DIV_SHIFT 0
2612 +#define ATB_DIV_SHIFT 8
2613 +#define CPU_CLK_SRC_SHIFT 16
2614 +
2615 +#define AXI_DIV_1 0
2616 +#define AXI_DIV_2 1
2617 +#define AXI_DIV_3 2
2618 +#define AXI_DIV_4 3
2619 +#define ATB_DIV_1 0
2620 +#define ATB_DIV_2 1
2621 +#define ATB_DIV_4 2
2622 +#define CPU_CLK_SRC_OSC24M 1
2623 +#define CPU_CLK_SRC_PLL1 2
2624 +
2625 +#define PLL1_CFG_DEFAULT 0x90011b21
2626 +
2627 +#define PLL6_CFG_DEFAULT 0x90041811
2628 +
2629 +#define CCM_PLL6_CTRL_N_SHIFT 8
2630 +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
2631 +#define CCM_PLL6_CTRL_K_SHIFT 4
2632 +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
2633 +
2634 +#define AHB_GATE_OFFSET_MMC3 11
2635 +#define AHB_GATE_OFFSET_MMC2 10
2636 +#define AHB_GATE_OFFSET_MMC1 9
2637 +#define AHB_GATE_OFFSET_MMC0 8
2638 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
2639 +
2640 +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24)
2641 +#define CCM_MMC_CTRL_PLL6 (0x1 << 24)
2642 +
2643 +#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
2644 +
2645 +#define AHB_RESET_OFFSET_MMC3 11
2646 +#define AHB_RESET_OFFSET_MMC2 10
2647 +#define AHB_RESET_OFFSET_MMC1 9
2648 +#define AHB_RESET_OFFSET_MMC0 8
2649 +#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n))
2650 +
2651 +/* apb2 reset */
2652 +#define APB2_RESET_UART_SHIFT (16)
2653 +#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
2654 +#define APB2_RESET_TWI_SHIFT (0)
2655 +#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT)
2656 +
2657 +#endif /* _SUNXI_CLOCK_SUN6I_H */
2658 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/cpucfg.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpucfg.h
2659 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/cpucfg.h 1970-01-01 01:00:00.000000000 +0100
2660 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpucfg.h 2014-09-06 16:58:35.381953139 +0200
2661 @@ -0,0 +1,55 @@
2662 +/*
2663 + * (C) Copyright 2013
2664 + * Carl van Schaik <carl@ok-labs.com>
2665 + *
2666 + * CPU configuration registers for the sun7i (A20).
2667 + *
2668 + * SPDX-License-Identifier: GPL-2.0+
2669 + */
2670 +
2671 +#ifndef _SUNXI_CPUCFG_H_
2672 +#define _SUNXI_CPUCFG_H_
2673 +
2674 +#ifndef __ASSEMBLY__
2675 +
2676 +struct sunxi_cpu_ctrl {
2677 + u32 reset_ctrl;
2678 + u32 cpu_ctrl;
2679 + u32 status;
2680 + u32 _res[13];
2681 +};
2682 +
2683 +#define CPU_RESET_SET 0
2684 +#define CPU_RESET_CLEAR 3
2685 +
2686 +#define CPU_STATUS_SMP (1 << 0)
2687 +#define CPU_STATUS_WFE (1 << 1)
2688 +#define CPU_STATUS_WFI (1 << 2)
2689 +
2690 +struct sunxi_cpucfg {
2691 + u32 _res1[16]; /* 0x000 */
2692 + struct sunxi_cpu_ctrl cpu[2]; /* 0x040 */
2693 + u32 _res2[48]; /* 0x0c0 */
2694 + u32 _res3; /* 0x180 */
2695 + u32 general_ctrl; /* 0x184 */
2696 + u32 _res4[2]; /* 0x188 */
2697 + u32 event_input; /* 0x190 */
2698 + u32 _res5[4]; /* 0x194 */
2699 + u32 boot_addr; /* 0x1a4 - also known as PRIVATE_REG */
2700 + u32 _res6[2]; /* 0x1a8 */
2701 + u32 cpu1_power_clamp; /* 0x1b0 */
2702 + u32 cpu1_power_off; /* 0x1b4 */
2703 + u32 _res7[10]; /* 0x1b8 */
2704 + u32 debug0_ctrl; /* 0x1e0 */
2705 + u32 debug1_ctrl; /* 0x1e4 */
2706 +};
2707 +
2708 +#define GENERAL_CTRL_NO_L1_RESET_CPU(x) (1UL << (x))
2709 +#define GENERAL_CTRL_NO_L2_AUTO_RESET (1UL << 4)
2710 +#define GENERAL_CTRL_L2_RESET_SET (0UL << 5)
2711 +#define GENERAL_CTRL_L2_RESET_CLEAR (1UL << 5)
2712 +#define GENERAL_CTRL_CFGSDISABLE (1UL << 8)
2713 +
2714 +#endif /* __ASSEMBLY__ */
2715 +
2716 +#endif /* _SUNXI_CPUCFG_H_ */
2717 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/cpu.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpu.h
2718 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/cpu.h 1970-01-01 01:00:00.000000000 +0100
2719 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/cpu.h 2014-09-06 16:58:35.381953139 +0200
2720 @@ -0,0 +1,141 @@
2721 +/*
2722 + * (C) Copyright 2007-2011
2723 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
2724 + * Tom Cubie <tangliang@allwinnertech.com>
2725 + *
2726 + * SPDX-License-Identifier: GPL-2.0+
2727 + */
2728 +
2729 +#ifndef _SUNXI_CPU_H
2730 +#define _SUNXI_CPU_H
2731 +
2732 +#define SUNXI_SRAM_A1_BASE 0x00000000
2733 +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
2734 +
2735 +#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
2736 +#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
2737 +#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
2738 +#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
2739 +#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
2740 +
2741 +#define SUNXI_SRAMC_BASE 0x01c00000
2742 +#define SUNXI_DRAMC_BASE 0x01c01000
2743 +#define SUNXI_DMA_BASE 0x01c02000
2744 +#define SUNXI_NFC_BASE 0x01c03000
2745 +#define SUNXI_TS_BASE 0x01c04000
2746 +#define SUNXI_SPI0_BASE 0x01c05000
2747 +#define SUNXI_SPI1_BASE 0x01c06000
2748 +#define SUNXI_MS_BASE 0x01c07000
2749 +#define SUNXI_TVD_BASE 0x01c08000
2750 +#define SUNXI_CSI0_BASE 0x01c09000
2751 +#define SUNXI_TVE0_BASE 0x01c0a000
2752 +#define SUNXI_EMAC_BASE 0x01c0b000
2753 +#define SUNXI_LCD0_BASE 0x01c0C000
2754 +#define SUNXI_LCD1_BASE 0x01c0d000
2755 +#define SUNXI_VE_BASE 0x01c0e000
2756 +#define SUNXI_MMC0_BASE 0x01c0f000
2757 +#define SUNXI_MMC1_BASE 0x01c10000
2758 +#define SUNXI_MMC2_BASE 0x01c11000
2759 +#define SUNXI_MMC3_BASE 0x01c12000
2760 +#define SUNXI_USB0_BASE 0x01c13000
2761 +#define SUNXI_USB1_BASE 0x01c14000
2762 +#define SUNXI_SS_BASE 0x01c15000
2763 +#define SUNXI_HDMI_BASE 0x01c16000
2764 +#define SUNXI_SPI2_BASE 0x01c17000
2765 +#define SUNXI_SATA_BASE 0x01c18000
2766 +#define SUNXI_PATA_BASE 0x01c19000
2767 +#define SUNXI_ACE_BASE 0x01c1a000
2768 +#define SUNXI_TVE1_BASE 0x01c1b000
2769 +#define SUNXI_USB2_BASE 0x01c1c000
2770 +#define SUNXI_CSI1_BASE 0x01c1d000
2771 +#define SUNXI_TZASC_BASE 0x01c1e000
2772 +#define SUNXI_SPI3_BASE 0x01c1f000
2773 +
2774 +#define SUNXI_CCM_BASE 0x01c20000
2775 +#define SUNXI_INTC_BASE 0x01c20400
2776 +#define SUNXI_PIO_BASE 0x01c20800
2777 +#define SUNXI_TIMER_BASE 0x01c20c00
2778 +#define SUNXI_SPDIF_BASE 0x01c21000
2779 +#define SUNXI_AC97_BASE 0x01c21400
2780 +#define SUNXI_IR0_BASE 0x01c21800
2781 +#define SUNXI_IR1_BASE 0x01c21c00
2782 +
2783 +#define SUNXI_IIS_BASE 0x01c22400
2784 +#define SUNXI_LRADC_BASE 0x01c22800
2785 +#define SUNXI_AD_DA_BASE 0x01c22c00
2786 +#define SUNXI_KEYPAD_BASE 0x01c23000
2787 +#define SUNXI_TZPC_BASE 0x01c23400
2788 +#define SUNXI_SID_BASE 0x01c23800
2789 +#define SUNXI_SJTAG_BASE 0x01c23c00
2790 +
2791 +#define SUNXI_TP_BASE 0x01c25000
2792 +#define SUNXI_PMU_BASE 0x01c25400
2793 +#define SUNXI_CPUCFG_BASE 0x01c25c00 /* sun7i only ? */
2794 +
2795 +#define SUNXI_UART0_BASE 0x01c28000
2796 +#define SUNXI_UART1_BASE 0x01c28400
2797 +#define SUNXI_UART2_BASE 0x01c28800
2798 +#define SUNXI_UART3_BASE 0x01c28c00
2799 +#define SUNXI_UART4_BASE 0x01c29000
2800 +#define SUNXI_UART5_BASE 0x01c29400
2801 +#define SUNXI_UART6_BASE 0x01c29800
2802 +#define SUNXI_UART7_BASE 0x01c29c00
2803 +#define SUNXI_PS2_0_BASE 0x01c2a000
2804 +#define SUNXI_PS2_1_BASE 0x01c2a400
2805 +
2806 +#define SUNXI_TWI0_BASE 0x01c2ac00
2807 +#define SUNXI_TWI1_BASE 0x01c2b000
2808 +#define SUNXI_TWI2_BASE 0x01c2b400
2809 +
2810 +#define SUNXI_CAN_BASE 0x01c2bc00
2811 +
2812 +#define SUNXI_SCR_BASE 0x01c2c400
2813 +
2814 +#define SUNXI_GPS_BASE 0x01c30000
2815 +#define SUNXI_MALI400_BASE 0x01c40000
2816 +#define SUNXI_GMAC_BASE 0x01c50000
2817 +
2818 +#define SUNXI_DRAM_COM_BASE 0x01c62000
2819 +#define SUNXI_DRAM_CTL_BASE 0x01c63000
2820 +#define SUNXI_DRAM_PHY_CH1_BASE 0x01c65000
2821 +#define SUNXI_DRAM_PHY_CH2_BASE 0x01c66000
2822 +
2823 +/* module sram */
2824 +#define SUNXI_SRAM_C_BASE 0x01d00000
2825 +
2826 +#define SUNXI_DE_FE0_BASE 0x01e00000
2827 +#define SUNXI_DE_FE1_BASE 0x01e20000
2828 +#define SUNXI_DE_BE0_BASE 0x01e60000
2829 +#define SUNXI_DE_BE1_BASE 0x01e40000
2830 +#define SUNXI_MP_BASE 0x01e80000
2831 +#define SUNXI_AVG_BASE 0x01ea0000
2832 +
2833 +#define SUNXI_PRCM_BASE 0x01f01400
2834 +#define SUNXI_R_UART_BASE 0x01f02800
2835 +#define SUNXI_R_PIO_BASE 0x01f02c00
2836 +#define SUNXI_P2WI_BASE 0x01f03400
2837 +
2838 +/* CoreSight Debug Module */
2839 +#define SUNXI_CSDM_BASE 0x3f500000
2840 +
2841 +#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
2842 +
2843 +#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
2844 +
2845 +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
2846 +
2847 +#ifndef __ASSEMBLY__
2848 +/* boot type */
2849 +enum sunxi_boot_type_t {
2850 + SUNXI_BOOT_TYPE_NULL,
2851 + SUNXI_BOOT_TYPE_MMC0,
2852 + SUNXI_BOOT_TYPE_NAND,
2853 + SUNXI_BOOT_TYPE_MMC2,
2854 + SUNXI_BOOT_TYPE_SPI
2855 +};
2856 +
2857 +void sunxi_board_init(void);
2858 +void sunxi_reset(void);
2859 +#endif /* __ASSEMBLY__ */
2860 +
2861 +#endif /* _CPU_H */
2862 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/dram.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/dram.h
2863 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/dram.h 1970-01-01 01:00:00.000000000 +0100
2864 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/dram.h 2014-09-06 16:58:35.381953139 +0200
2865 @@ -0,0 +1,179 @@
2866 +/*
2867 + * (C) Copyright 2007-2012
2868 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
2869 + * Berg Xing <bergxing@allwinnertech.com>
2870 + * Tom Cubie <tangliang@allwinnertech.com>
2871 + *
2872 + * Sunxi platform dram register definition.
2873 + *
2874 + * SPDX-License-Identifier: GPL-2.0+
2875 + */
2876 +
2877 +#ifndef _SUNXI_DRAM_H
2878 +#define _SUNXI_DRAM_H
2879 +
2880 +#include <linux/types.h>
2881 +
2882 +struct sunxi_dram_reg {
2883 + u32 ccr; /* 0x00 controller configuration register */
2884 + u32 dcr; /* 0x04 dram configuration register */
2885 + u32 iocr; /* 0x08 i/o configuration register */
2886 + u32 csr; /* 0x0c controller status register */
2887 + u32 drr; /* 0x10 dram refresh register */
2888 + u32 tpr0; /* 0x14 dram timing parameters register 0 */
2889 + u32 tpr1; /* 0x18 dram timing parameters register 1 */
2890 + u32 tpr2; /* 0x1c dram timing parameters register 2 */
2891 + u32 gdllcr; /* 0x20 global dll control register */
2892 + u8 res0[0x28];
2893 + u32 rslr0; /* 0x4c rank system latency register */
2894 + u32 rslr1; /* 0x50 rank system latency register */
2895 + u8 res1[0x8];
2896 + u32 rdgr0; /* 0x5c rank dqs gating register */
2897 + u32 rdgr1; /* 0x60 rank dqs gating register */
2898 + u8 res2[0x34];
2899 + u32 odtcr; /* 0x98 odt configuration register */
2900 + u32 dtr0; /* 0x9c data training register 0 */
2901 + u32 dtr1; /* 0xa0 data training register 1 */
2902 + u32 dtar; /* 0xa4 data training address register */
2903 + u32 zqcr0; /* 0xa8 zq control register 0 */
2904 + u32 zqcr1; /* 0xac zq control register 1 */
2905 + u32 zqsr; /* 0xb0 zq status register */
2906 + u32 idcr; /* 0xb4 initializaton delay configure reg */
2907 + u8 res3[0x138];
2908 + u32 mr; /* 0x1f0 mode register */
2909 + u32 emr; /* 0x1f4 extended mode register */
2910 + u32 emr2; /* 0x1f8 extended mode register */
2911 + u32 emr3; /* 0x1fc extended mode register */
2912 + u32 dllctr; /* 0x200 dll control register */
2913 + u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */
2914 + /* 0x208 dll control register 1(byte 1) */
2915 + /* 0x20c dll control register 2(byte 2) */
2916 + /* 0x210 dll control register 3(byte 3) */
2917 + /* 0x214 dll control register 4(byte 4) */
2918 + u32 dqtr0; /* 0x218 dq timing register */
2919 + u32 dqtr1; /* 0x21c dq timing register */
2920 + u32 dqtr2; /* 0x220 dq timing register */
2921 + u32 dqtr3; /* 0x224 dq timing register */
2922 + u32 dqstr; /* 0x228 dqs timing register */
2923 + u32 dqsbtr; /* 0x22c dqsb timing register */
2924 + u32 mcr; /* 0x230 mode configure register */
2925 + u8 res[0x8];
2926 + u32 ppwrsctl; /* 0x23c pad power save control */
2927 + u32 apr; /* 0x240 arbiter period register */
2928 + u32 pldtr; /* 0x244 priority level data threshold reg */
2929 + u8 res5[0x8];
2930 + u32 hpcr[32]; /* 0x250 host port configure register */
2931 + u8 res6[0x10];
2932 + u32 csel; /* 0x2e0 controller select register */
2933 +};
2934 +
2935 +struct dram_para {
2936 + u32 clock;
2937 + u32 type;
2938 + u32 rank_num;
2939 + u32 density;
2940 + u32 io_width;
2941 + u32 bus_width;
2942 + u32 cas;
2943 + u32 zq;
2944 + u32 odt_en;
2945 + u32 size;
2946 + u32 tpr0;
2947 + u32 tpr1;
2948 + u32 tpr2;
2949 + u32 tpr3;
2950 + u32 tpr4;
2951 + u32 tpr5;
2952 + u32 emr1;
2953 + u32 emr2;
2954 + u32 emr3;
2955 +};
2956 +
2957 +#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5)
2958 +#define DRAM_CCR_DQS_GATE (0x1 << 14)
2959 +#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17)
2960 +#define DRAM_CCR_ITM_OFF (0x1 << 28)
2961 +#define DRAM_CCR_DATA_TRAINING (0x1 << 30)
2962 +#define DRAM_CCR_INIT (0x1 << 31)
2963 +
2964 +#define DRAM_MEMORY_TYPE_DDR1 1
2965 +#define DRAM_MEMORY_TYPE_DDR2 2
2966 +#define DRAM_MEMORY_TYPE_DDR3 3
2967 +#define DRAM_MEMORY_TYPE_LPDDR2 4
2968 +#define DRAM_MEMORY_TYPE_LPDDR 5
2969 +#define DRAM_DCR_TYPE (0x1 << 0)
2970 +#define DRAM_DCR_TYPE_DDR2 0x0
2971 +#define DRAM_DCR_TYPE_DDR3 0x1
2972 +#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1)
2973 +#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3)
2974 +#define DRAM_DCR_IO_WIDTH_8BIT 0x0
2975 +#define DRAM_DCR_IO_WIDTH_16BIT 0x1
2976 +#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3)
2977 +#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7)
2978 +#define DRAM_DCR_CHIP_DENSITY_256M 0x0
2979 +#define DRAM_DCR_CHIP_DENSITY_512M 0x1
2980 +#define DRAM_DCR_CHIP_DENSITY_1024M 0x2
2981 +#define DRAM_DCR_CHIP_DENSITY_2048M 0x3
2982 +#define DRAM_DCR_CHIP_DENSITY_4096M 0x4
2983 +#define DRAM_DCR_CHIP_DENSITY_8192M 0x5
2984 +#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6)
2985 +#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7)
2986 +#define DRAM_DCR_BUS_WIDTH_32BIT 0x3
2987 +#define DRAM_DCR_BUS_WIDTH_16BIT 0x1
2988 +#define DRAM_DCR_BUS_WIDTH_8BIT 0x0
2989 +#define DRAM_DCR_NR_DLLCR_32BIT 5
2990 +#define DRAM_DCR_NR_DLLCR_16BIT 3
2991 +#define DRAM_DCR_NR_DLLCR_8BIT 2
2992 +#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10)
2993 +#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3)
2994 +#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12)
2995 +#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13)
2996 +#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3)
2997 +#define DRAM_DCR_MODE_SEQ 0x0
2998 +#define DRAM_DCR_MODE_INTERLEAVE 0x1
2999 +
3000 +#define DRAM_CSR_FAILED (0x1 << 20)
3001 +
3002 +#define DRAM_DRR_TRFC(n) ((n) & 0xff)
3003 +#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8)
3004 +#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24)
3005 +
3006 +#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0)
3007 +#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3)
3008 +#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2)
3009 +#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3)
3010 +#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4)
3011 +#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3)
3012 +#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6)
3013 +#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3)
3014 +#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8)
3015 +#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7)
3016 +#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11)
3017 +#define DRAM_MCR_RESET (0x1 << 12)
3018 +#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13)
3019 +#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3)
3020 +#define DRAM_MCR_DCLK_OUT (0x1 << 16)
3021 +
3022 +#define DRAM_DLLCR_NRESET (0x1 << 30)
3023 +#define DRAM_DLLCR_DISABLE (0x1 << 31)
3024 +
3025 +#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20)
3026 +#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff)
3027 +
3028 +#define DRAM_IOCR_ODT_EN(n) ((((n) & 0x3) << 30) | ((n) & 0x3) << 0)
3029 +#define DRAM_IOCR_ODT_EN_MASK DRAM_IOCR_ODT_EN(0x3)
3030 +
3031 +#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0)
3032 +#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7)
3033 +#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4)
3034 +#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7)
3035 +#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9)
3036 +#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7)
3037 +#define DRAM_MR_POWER_DOWN (0x1 << 12)
3038 +
3039 +#define DRAM_CSEL_MAGIC 0x16237495
3040 +
3041 +unsigned long sunxi_dram_init(void);
3042 +unsigned long dramc_init(struct dram_para *para);
3043 +
3044 +#endif /* _SUNXI_DRAM_H */
3045 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/early_print.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/early_print.h
3046 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/early_print.h 1970-01-01 01:00:00.000000000 +0100
3047 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/early_print.h 2014-09-06 16:58:35.381953139 +0200
3048 @@ -0,0 +1,58 @@
3049 +/*
3050 + * (C) Copyright 2007-2012
3051 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3052 + * Tom Cubie <tangliang@allwinnertech.com>
3053 + *
3054 + * Early uart print for debugging.
3055 + *
3056 + * SPDX-License-Identifier: GPL-2.0+
3057 + */
3058 +
3059 +#ifndef _SUNXI_EARLY_PRINT_H
3060 +#define _SUNXI_EARLY_PRINT_H
3061 +
3062 +#include <asm/arch/cpu.h>
3063 +
3064 +#define SUNXI_UART_BASE SUNXI_UART0_BASE
3065 +
3066 +#define UART_OFFSET 0x400
3067 +
3068 +/* receive buffer register */
3069 +#define UART_RBR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x0)
3070 +/* transmit holding register */
3071 +#define UART_THR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x0)
3072 +/* divisor latch low register */
3073 +#define UART_DLL(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x0)
3074 +
3075 +/* divisor latch high register */
3076 +#define UART_DLH(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x4)
3077 +/* interrupt enable reigster */
3078 +#define UART_IER(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x4)
3079 +
3080 +/* interrupt identity register */
3081 +#define UART_IIR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x8)
3082 +/* fifo control register */
3083 +#define UART_FCR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x8)
3084 +
3085 +/* line control register */
3086 +#define UART_LCR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0xc)
3087 +#define UART_LCR_DLAB (0x1 << 7)
3088 +
3089 +/* line status register */
3090 +#define UART_LSR(n) (SUNXI_UART_BASE + (n) * UART_OFFSET + 0x14)
3091 +#define UART_LSR_TEMT (0x1 << 6)
3092 +
3093 +
3094 +#define BAUD_115200 (0xd) /* 24 * 1000 * 1000 / 16 / 115200 = 13 */
3095 +#define NO_PARITY (0)
3096 +#define ONE_STOP_BIT (0)
3097 +#define DAT_LEN_8_BITS (3)
3098 +#define LC_8_N_1 (NO_PARITY << 3 | ONE_STOP_BIT << 2 | DAT_LEN_8_BITS)
3099 +
3100 +#ifndef __ASSEMBLY__
3101 +void uart_init(void);
3102 +void uart_putc(char c);
3103 +void uart_puts(const char *s);
3104 +#endif /* __ASSEMBLY__ */
3105 +
3106 +#endif /* _SUNXI_EARLY_PRINT_H */
3107 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/gpio.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/gpio.h
3108 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/gpio.h 1970-01-01 01:00:00.000000000 +0100
3109 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/gpio.h 2014-09-06 16:58:35.381953139 +0200
3110 @@ -0,0 +1,174 @@
3111 +/*
3112 + * (C) Copyright 2007-2012
3113 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3114 + * Tom Cubie <tangliang@allwinnertech.com>
3115 + *
3116 + * SPDX-License-Identifier: GPL-2.0+
3117 + */
3118 +
3119 +#ifndef _SUNXI_GPIO_H
3120 +#define _SUNXI_GPIO_H
3121 +
3122 +#include <linux/types.h>
3123 +#include <asm/arch/cpu.h>
3124 +
3125 +/*
3126 + * sunxi has 9 banks of gpio, they are:
3127 + * PA0 - PA17 | PB0 - PB23 | PC0 - PC24
3128 + * PD0 - PD27 | PE0 - PE31 | PF0 - PF5
3129 + * PG0 - PG9 | PH0 - PH27 | PI0 - PI12
3130 + */
3131 +
3132 +#define SUNXI_GPIO_A 0
3133 +#define SUNXI_GPIO_B 1
3134 +#define SUNXI_GPIO_C 2
3135 +#define SUNXI_GPIO_D 3
3136 +#define SUNXI_GPIO_E 4
3137 +#define SUNXI_GPIO_F 5
3138 +#define SUNXI_GPIO_G 6
3139 +#define SUNXI_GPIO_H 7
3140 +#define SUNXI_GPIO_I 8
3141 +#define SUNXI_GPIO_BANKS 9
3142 +
3143 +/*
3144 + * sun6i has atleast 1 additional bank, note banks J K don't exist!
3145 + * PL0 - PL1 at the very least is known.
3146 + *
3147 + * Note this bank is at a different register offset!
3148 + */
3149 +#define SUNXI_GPIO_L 9
3150 +
3151 +struct sunxi_gpio {
3152 + u32 cfg[4];
3153 + u32 dat;
3154 + u32 drv[2];
3155 + u32 pull[2];
3156 +};
3157 +
3158 +/* gpio interrupt control */
3159 +struct sunxi_gpio_int {
3160 + u32 cfg[3];
3161 + u32 ctl;
3162 + u32 sta;
3163 + u32 deb; /* interrupt debounce */
3164 +};
3165 +
3166 +struct sunxi_gpio_reg {
3167 + struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS];
3168 + u8 res[0xbc];
3169 + struct sunxi_gpio_int gpio_int;
3170 +};
3171 +
3172 +#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_BANKS) ? \
3173 + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
3174 + (struct sunxi_gpio *)SUNXI_R_PIO_BASE)
3175 +
3176 +#define GPIO_BANK(pin) ((pin) >> 5)
3177 +#define GPIO_NUM(pin) ((pin) & 0x1f)
3178 +
3179 +#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3)
3180 +#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2)
3181 +
3182 +#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4)
3183 +#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
3184 +
3185 +#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4)
3186 +#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
3187 +
3188 +/* GPIO bank sizes */
3189 +#define SUNXI_GPIO_A_NR 32
3190 +#define SUNXI_GPIO_B_NR 32
3191 +#define SUNXI_GPIO_C_NR 32
3192 +#define SUNXI_GPIO_D_NR 32
3193 +#define SUNXI_GPIO_E_NR 32
3194 +#define SUNXI_GPIO_F_NR 32
3195 +#define SUNXI_GPIO_G_NR 32
3196 +#define SUNXI_GPIO_H_NR 32
3197 +#define SUNXI_GPIO_I_NR 32
3198 +#define SUNXI_GPIO_L_NR 32
3199 +
3200 +#define SUNXI_GPIO_NEXT(__gpio) \
3201 + ((__gpio##_START) + (__gpio##_NR) + 0)
3202 +
3203 +enum sunxi_gpio_number {
3204 + SUNXI_GPIO_A_START = 0,
3205 + SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A),
3206 + SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B),
3207 + SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C),
3208 + SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D),
3209 + SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E),
3210 + SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F),
3211 + SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G),
3212 + SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H),
3213 + SUNXI_GPIO_L_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_I),
3214 +};
3215 +
3216 +/* SUNXI GPIO number definitions */
3217 +#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr))
3218 +#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr))
3219 +#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr))
3220 +#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr))
3221 +#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr))
3222 +#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr))
3223 +#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr))
3224 +#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr))
3225 +#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
3226 +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr))
3227 +
3228 +/* GPIO pin function config */
3229 +#define SUNXI_GPIO_INPUT 0
3230 +#define SUNXI_GPIO_OUTPUT 1
3231 +
3232 +#define SUNXI_GPA0_EMAC 2
3233 +#define SUN7I_GPA0_GMAC 5
3234 +
3235 +#define SUNXI_GPB0_TWI0 2
3236 +
3237 +#define SUN4I_GPB22_UART0_TX 2
3238 +#define SUN4I_GPB23_UART0_RX 2
3239 +
3240 +#define SUN5I_GPB19_UART0_TX 2
3241 +#define SUN5I_GPB20_UART0_RX 2
3242 +
3243 +#define SUN5I_GPG3_UART1_TX 4
3244 +#define SUN5I_GPG4_UART1_RX 4
3245 +
3246 +#define SUNXI_GPC6_SDC2 3
3247 +
3248 +#define SUNXI_GPF0_SDC0 2
3249 +
3250 +#define SUNXI_GPF2_SDC0 2
3251 +
3252 +#ifdef CONFIG_SUN8I
3253 +#define SUNXI_GPF2_UART0_TX 3
3254 +#define SUNXI_GPF4_UART0_RX 3
3255 +#else
3256 +#define SUNXI_GPF2_UART0_TX 4
3257 +#define SUNXI_GPF4_UART0_RX 4
3258 +#endif
3259 +
3260 +#define SUN4I_GPG0_SDC1 4
3261 +
3262 +#define SUN4I_GPH22_SDC1 5
3263 +
3264 +#define SUN4I_GPI4_SDC3 2
3265 +
3266 +/* GPIO pin pull-up/down config */
3267 +#define SUNXI_GPIO_PULL_DISABLE 0
3268 +#define SUNXI_GPIO_PULL_UP 1
3269 +#define SUNXI_GPIO_PULL_DOWN 2
3270 +
3271 +#define SUNXI_GPL0_R_P2WI_SCK 3
3272 +#define SUNXI_GPL1_R_P2WI_SDA 3
3273 +
3274 +#define SUN8I_GPL2_R_UART_TX 2
3275 +#define SUN8I_GPL3_R_UART_RX 2
3276 +
3277 +int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
3278 +int sunxi_gpio_get_cfgpin(u32 pin);
3279 +int sunxi_gpio_set_drv(u32 pin, u32 val);
3280 +int sunxi_gpio_set_pull(u32 pin, u32 val);
3281 +int sunxi_name_to_gpio(const char *name);
3282 +#define name_to_gpio(name) sunxi_name_to_gpio(name)
3283 +
3284 +#endif /* _SUNXI_GPIO_H */
3285 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/i2c.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/i2c.h
3286 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/i2c.h 1970-01-01 01:00:00.000000000 +0100
3287 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/i2c.h 2014-09-06 16:58:35.381953139 +0200
3288 @@ -0,0 +1,15 @@
3289 +/*
3290 + * Copyright 2014 - Hans de Goede <hdegoede@redhat.com>
3291 + *
3292 + * SPDX-License-Identifier: GPL-2.0+
3293 + */
3294 +#ifndef _SUNXI_I2C_H_
3295 +#define _SUNXI_I2C_H_
3296 +
3297 +#include <asm/arch/cpu.h>
3298 +
3299 +#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE
3300 +/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
3301 +#define CONFIG_SYS_TCLK 24000000
3302 +
3303 +#endif
3304 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/mmc.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/mmc.h
3305 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/mmc.h 1970-01-01 01:00:00.000000000 +0100
3306 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/mmc.h 2014-09-06 16:58:35.381953139 +0200
3307 @@ -0,0 +1,122 @@
3308 +/*
3309 + * (C) Copyright 2007-2011
3310 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3311 + * Aaron <leafy.myeh@allwinnertech.com>
3312 + *
3313 + * MMC register definition for allwinner sunxi platform.
3314 + *
3315 + * SPDX-License-Identifier: GPL-2.0+
3316 + */
3317 +
3318 +#ifndef _SUNXI_MMC_H
3319 +#define _SUNXI_MMC_H
3320 +
3321 +#include <linux/types.h>
3322 +
3323 +struct sunxi_mmc {
3324 + u32 gctrl; /* 0x00 global control */
3325 + u32 clkcr; /* 0x04 clock control */
3326 + u32 timeout; /* 0x08 time out */
3327 + u32 width; /* 0x0c bus width */
3328 + u32 blksz; /* 0x10 block size */
3329 + u32 bytecnt; /* 0x14 byte count */
3330 + u32 cmd; /* 0x18 command */
3331 + u32 arg; /* 0x1c argument */
3332 + u32 resp0; /* 0x20 response 0 */
3333 + u32 resp1; /* 0x24 response 1 */
3334 + u32 resp2; /* 0x28 response 2 */
3335 + u32 resp3; /* 0x2c response 3 */
3336 + u32 imask; /* 0x30 interrupt mask */
3337 + u32 mint; /* 0x34 masked interrupt status */
3338 + u32 rint; /* 0x38 raw interrupt status */
3339 + u32 status; /* 0x3c status */
3340 + u32 ftrglevel; /* 0x40 FIFO threshold watermark*/
3341 + u32 funcsel; /* 0x44 function select */
3342 + u32 cbcr; /* 0x48 CIU byte count */
3343 + u32 bbcr; /* 0x4c BIU byte count */
3344 + u32 dbgc; /* 0x50 debug enable */
3345 + u32 res0[11];
3346 + u32 dmac; /* 0x80 internal DMA control */
3347 + u32 dlba; /* 0x84 internal DMA descr list base address */
3348 + u32 idst; /* 0x88 internal DMA status */
3349 + u32 idie; /* 0x8c internal DMA interrupt enable */
3350 + u32 chda; /* 0x90 */
3351 + u32 cbda; /* 0x94 */
3352 +};
3353 +
3354 +#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17)
3355 +#define SUNXI_MMC_CLK_ENABLE (0x1 << 16)
3356 +#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff)
3357 +
3358 +#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0)
3359 +#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1)
3360 +#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2)
3361 +#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\
3362 + SUNXI_MMC_GCTRL_FIFO_RESET|\
3363 + SUNXI_MMC_GCTRL_DMA_RESET)
3364 +#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5)
3365 +#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31)
3366 +
3367 +#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6)
3368 +#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7)
3369 +#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8)
3370 +#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9)
3371 +#define SUNXI_MMC_CMD_WRITE (0x1 << 10)
3372 +#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12)
3373 +#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13)
3374 +#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15)
3375 +#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21)
3376 +#define SUNXI_MMC_CMD_START (0x1 << 31)
3377 +
3378 +#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1)
3379 +#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2)
3380 +#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3)
3381 +#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4)
3382 +#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5)
3383 +#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6)
3384 +#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7)
3385 +#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8)
3386 +#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9)
3387 +#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10)
3388 +#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11)
3389 +#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12)
3390 +#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13)
3391 +#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14)
3392 +#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15)
3393 +#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16)
3394 +#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30)
3395 +#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31)
3396 +#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \
3397 + (SUNXI_MMC_RINT_RESP_ERROR | \
3398 + SUNXI_MMC_RINT_RESP_CRC_ERROR | \
3399 + SUNXI_MMC_RINT_DATA_CRC_ERROR | \
3400 + SUNXI_MMC_RINT_RESP_TIMEOUT | \
3401 + SUNXI_MMC_RINT_DATA_TIMEOUT | \
3402 + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \
3403 + SUNXI_MMC_RINT_FIFO_RUN_ERROR | \
3404 + SUNXI_MMC_RINT_HARD_WARE_LOCKED | \
3405 + SUNXI_MMC_RINT_START_BIT_ERROR | \
3406 + SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */
3407 +#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \
3408 + (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \
3409 + SUNXI_MMC_RINT_DATA_OVER | \
3410 + SUNXI_MMC_RINT_COMMAND_DONE | \
3411 + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE)
3412 +
3413 +#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0)
3414 +#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1)
3415 +#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2)
3416 +#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3)
3417 +#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8)
3418 +#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9)
3419 +#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10)
3420 +
3421 +#define SUNXI_MMC_IDMAC_RESET (0x1 << 0)
3422 +#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1)
3423 +#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7)
3424 +
3425 +#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0)
3426 +#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1)
3427 +
3428 +int sunxi_mmc_init(int sdc_no);
3429 +#endif /* _SUNXI_MMC_H */
3430 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/p2wi.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/p2wi.h
3431 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/p2wi.h 1970-01-01 01:00:00.000000000 +0100
3432 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/p2wi.h 2014-09-06 16:58:35.381953139 +0200
3433 @@ -0,0 +1,142 @@
3434 +/*
3435 + * Sunxi platform Push-Push i2c register definition.
3436 + *
3437 + * (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
3438 + * http://linux-sunxi.org
3439 + *
3440 + * (c)Copyright 2006-2013
3441 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3442 + * Berg Xing <bergxing@allwinnertech.com>
3443 + * Tom Cubie <tangliang@allwinnertech.com>
3444 + *
3445 + * SPDX-License-Identifier: GPL-2.0+
3446 + */
3447 +
3448 +#ifndef _SUNXI_P2WI_H
3449 +#define _SUNXI_P2WI_H
3450 +
3451 +#include <linux/types.h>
3452 +
3453 +#define P2WI_CTRL_RESET (0x1 << 0)
3454 +#define P2WI_CTRL_IRQ_EN (0x1 << 1)
3455 +#define P2WI_CTRL_TRANS_ABORT (0x1 << 6)
3456 +#define P2WI_CTRL_TRANS_START (0x1 << 7)
3457 +
3458 +#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0)
3459 +#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff)
3460 +#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1)
3461 +#define P2WI_CC_CLK_DIV(n) \
3462 + __P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n))
3463 +#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8)
3464 +#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7)
3465 +
3466 +#define P2WI_IRQ_TRANS_DONE (0x1 << 0)
3467 +#define P2WI_IRQ_TRANS_ERR (0x1 << 1)
3468 +#define P2WI_IRQ_LOAD_BUSY (0x1 << 2)
3469 +
3470 +#define P2WI_STAT_TRANS_DONE (0x1 << 0)
3471 +#define P2WI_STAT_TRANS_ERR (0x1 << 1)
3472 +#define P2WI_STAT_LOAD_BUSY (0x1 << 2)
3473 +#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8)
3474 +#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff)
3475 +#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01
3476 +#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02
3477 +#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04
3478 +#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08
3479 +#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10
3480 +#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20
3481 +#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40
3482 +#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80
3483 +#define P2WI_STAT_TRANS_ERR_BYTE_1 \
3484 + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1)
3485 +#define P2WI_STAT_TRANS_ERR_BYTE_2 \
3486 + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2)
3487 +#define P2WI_STAT_TRANS_ERR_BYTE_3 \
3488 + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3)
3489 +#define P2WI_STAT_TRANS_ERR_BYTE_4 \
3490 + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4)
3491 +#define P2WI_STAT_TRANS_ERR_BYTE_5 \
3492 + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5)
3493 +#define P2WI_STAT_TRANS_ERR_BYTE_6 \
3494 + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6)
3495 +#define P2WI_STAT_TRANS_ERR_BYTE_7 \
3496 + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7)
3497 +#define P2WI_STAT_TRANS_ERR_BYTE_8 \
3498 + __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8)
3499 +
3500 +#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0)
3501 +#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff)
3502 +#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8)
3503 +#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff)
3504 +#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16)
3505 +#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff)
3506 +#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24)
3507 +#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff)
3508 +#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0)
3509 +#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff)
3510 +#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8)
3511 +#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff)
3512 +#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16)
3513 +#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff)
3514 +#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24)
3515 +#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff)
3516 +
3517 +#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0)
3518 +#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7)
3519 +#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1)
3520 +#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4)
3521 +
3522 +#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0)
3523 +#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff)
3524 +#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8)
3525 +#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff)
3526 +#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16)
3527 +#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff)
3528 +#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24)
3529 +#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff)
3530 +#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0)
3531 +#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff)
3532 +#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8)
3533 +#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff)
3534 +#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16)
3535 +#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff)
3536 +#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24)
3537 +#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff)
3538 +
3539 +#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0)
3540 +#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1)
3541 +#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2)
3542 +#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3)
3543 +#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4)
3544 +#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5)
3545 +
3546 +#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0)
3547 +#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff)
3548 +#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8)
3549 +#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff)
3550 +#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16)
3551 +#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff)
3552 +#define P2WI_PM_INIT_SEND (0x1 << 31)
3553 +
3554 +#ifndef __ASSEMBLY__
3555 +struct sunxi_p2wi_reg {
3556 + u32 ctrl; /* 0x00 control */
3557 + u32 cc; /* 0x04 clock control */
3558 + u32 irq; /* 0x08 interrupt */
3559 + u32 status; /* 0x0c status */
3560 + u32 dataddr0; /* 0x10 data address 0 */
3561 + u32 dataddr1; /* 0x14 data address 1 */
3562 + u32 numbytes; /* 0x18 num bytes */
3563 + u32 data0; /* 0x1c data buffer 0 */
3564 + u32 data1; /* 0x20 data buffer 1 */
3565 + u32 linectrl; /* 0x24 line control */
3566 + u32 pm; /* 0x28 power management */
3567 +};
3568 +
3569 +void p2wi_init(void);
3570 +int p2wi_set_pmu_address(u8 slave_addr, u8 ctrl_reg, u8 init_data);
3571 +int p2wi_read(const u8 addr, u8 *data);
3572 +int p2wi_write(const u8 addr, u8 data);
3573 +
3574 +#endif /* __ASSEMBLY__ */
3575 +#endif /* _SUNXI_P2WI_H */
3576 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/prcm.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/prcm.h
3577 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/prcm.h 1970-01-01 01:00:00.000000000 +0100
3578 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/prcm.h 2014-09-06 16:58:35.381953139 +0200
3579 @@ -0,0 +1,238 @@
3580 +/*
3581 + * Sunxi A31 Power Management Unit register definition.
3582 + *
3583 + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
3584 + * http://linux-sunxi.org
3585 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3586 + * Berg Xing <bergxing@allwinnertech.com>
3587 + * Tom Cubie <tangliang@allwinnertech.com>
3588 + *
3589 + * SPDX-License-Identifier: GPL-2.0+
3590 + */
3591 +
3592 +#ifndef _SUNXI_PRCM_H
3593 +#define _SUNXI_PRCM_H
3594 +
3595 +#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)
3596 +#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
3597 +#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)
3598 +#define PRCM_CPUS_CFG_PRE_DIV(n) \
3599 + __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
3600 +#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)
3601 +#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
3602 +#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
3603 +#define PRCM_CPUS_CFG_POST_DIV(n) \
3604 + __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
3605 +#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)
3606 +#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
3607 +#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
3608 +#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
3609 +#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
3610 +#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
3611 +#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
3612 + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
3613 +#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
3614 + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
3615 +#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
3616 + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
3617 +#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
3618 + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
3619 +
3620 +#define __PRCM_APB0_RATIO(n) (((n) & 0x3) <<0)
3621 +#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
3622 +#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)
3623 +#define PRCM_APB0_RATIO_DIV(n) \
3624 + __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
3625 +
3626 +#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)
3627 +#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)
3628 +
3629 +#define PRCM_APB0_GATE_PIO (0x1 << 0)
3630 +#define PRCM_APB0_GATE_IR (0x1 << 1)
3631 +#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
3632 +#define PRCM_APB0_GATE_P2WI (0x1 << 3)
3633 +#define PRCM_APB0_GATE_UART (0x1 << 4)
3634 +#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
3635 +#define PRCM_APB0_GATE_I2C (0x1 << 6)
3636 +
3637 +#define PRCM_APB0_RESET_PIO (0x1 << 0)
3638 +#define PRCM_APB0_RESET_IR (0x1 << 1)
3639 +#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
3640 +#define PRCM_APB0_RESET_P2WI (0x1 << 3)
3641 +#define PRCM_APB0_RESET_UART (0x1 << 4)
3642 +#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
3643 +#define PRCM_APB0_RESET_I2C (0x1 << 6)
3644 +
3645 +#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)
3646 +#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)
3647 +#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)
3648 +#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \
3649 + __PRCM_PLL_CTRL_USB_CLK_SRC(0x3)
3650 +#define __PRCM_PLL_CTRL_USB_CLK_0 0x0
3651 +#define __PRCM_PLL_CTRL_USB_CLK_1 0x1
3652 +#define __PRCM_PLL_CTRL_USB_CLK_2 0x2
3653 +#define __PRCM_PLL_CTRL_USB_CLK_3 0x3
3654 +#define PRCM_PLL_CTRL_USB_CLK_0 \
3655 + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)
3656 +#define PRCM_PLL_CTRL_USB_CLK_1 \
3657 + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)
3658 +#define PRCM_PLL_CTRL_USB_CLK_2 \
3659 + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)
3660 +#define PRCM_PLL_CTRL_USB_CLK_3 \
3661 + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3)
3662 +#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12)
3663 +#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \
3664 + __PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3)
3665 +#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \
3666 + __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n)
3667 +#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20)
3668 +#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \
3669 + __PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3)
3670 +#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0
3671 +#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1
3672 +#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2
3673 +#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3
3674 +#define PRCM_PLL_CTRL_HOSC_CLK_0 \
3675 + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0)
3676 +#define PRCM_PLL_CTRL_HOSC_CLK_1 \
3677 + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1)
3678 +#define PRCM_PLL_CTRL_HOSC_CLK_2 \
3679 + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2)
3680 +#define PRCM_PLL_CTRL_HOSC_CLK_3 \
3681 + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3)
3682 +#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24)
3683 +#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0)
3684 +#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1)
3685 +#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2)
3686 +#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3)
3687 +#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */
3688 +#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16)
3689 +#define PRCM_PLL_CTRL_LDO_OUT_MASK \
3690 + __PRCM_PLL_CTRL_LDO_OUT(0x7)
3691 +/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */
3692 +#define PRCM_PLL_CTRL_LDO_OUT_L(n) \
3693 + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7)
3694 +#define PRCM_PLL_CTRL_LDO_OUT_H(n) \
3695 + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7)
3696 +#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \
3697 + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000)
3698 +#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \
3699 + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160)
3700 +#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24)
3701 +
3702 +#define PRCM_CLK_1WIRE_GATE (0x1 << 31)
3703 +
3704 +#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0)
3705 +#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf)
3706 +#define __PRCM_CLK_MOD0_M_X(n) (n - 1)
3707 +#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n))
3708 +#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8)
3709 +#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7)
3710 +#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16)
3711 +#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3)
3712 +#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) -1)
3713 +#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n))
3714 +#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20)
3715 +#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7)
3716 +#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24)
3717 +#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7)
3718 +#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31)
3719 +
3720 +#define PRCM_APB0_RESET_PIO (0x1 << 0)
3721 +#define PRCM_APB0_RESET_IR (0x1 << 1)
3722 +#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
3723 +#define PRCM_APB0_RESET_P2WI (0x1 << 3)
3724 +#define PRCM_APB0_RESET_UART (0x1 << 4)
3725 +#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
3726 +#define PRCM_APB0_RESET_I2C (0x1 << 6)
3727 +
3728 +#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8)
3729 +#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7)
3730 +#define __PRCM_CLK_OUTD_M_X() ((n) - 1)
3731 +#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n))
3732 +#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20)
3733 +#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7)
3734 +#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1)
3735 +#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n)
3736 +#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24)
3737 +#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3)
3738 +#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0
3739 +#define __PRCM_CLK_OUTD_SRC_LOSC 0x1
3740 +#define __PRCM_CLK_OUTD_SRC_HOSC 0x2
3741 +#define __PRCM_CLK_OUTD_SRC_ERR 0x3
3742 +#define PRCM_CLK_OUTD_SRC_LOSC2 \
3743 +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2)
3744 +#define PRCM_CLK_OUTD_SRC_LOSC \
3745 +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC)
3746 +#define PRCM_CLK_OUTD_SRC_HOSC \
3747 +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC)
3748 +#define PRCM_CLK_OUTD_SRC_ERR \
3749 +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR)
3750 +#define PRCM_CLK_OUTD_EN (0x1 << 31)
3751 +
3752 +#define PRCM_CPU0_PWROFF (0x1 << 0)
3753 +#define PRCM_CPU1_PWROFF (0x1 << 1)
3754 +#define PRCM_CPU2_PWROFF (0x1 << 2)
3755 +#define PRCM_CPU3_PWROFF (0x1 << 3)
3756 +#define PRCM_CPU_ALL_PWROFF (0xf << 0)
3757 +
3758 +#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0)
3759 +#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1)
3760 +#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2)
3761 +#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3)
3762 +
3763 +#define PRCM_VDD_GPU_PWROFF (0x1 << 0)
3764 +
3765 +#define PRCM_VDD_SYS_RESET (0x1 << 0)
3766 +
3767 +#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0)
3768 +#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff)
3769 +
3770 +#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0)
3771 +#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff)
3772 +
3773 +#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0)
3774 +#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff)
3775 +
3776 +#ifndef __ASSEMBLY__
3777 +struct sunxi_prcm_reg {
3778 + u32 cpus_cfg; /* 0x000 */
3779 + u8 res0[0x8]; /* 0x004 */
3780 + u32 apb0_ratio; /* 0x00c */
3781 + u32 cpu0_cfg; /* 0x010 */
3782 + u32 cpu1_cfg; /* 0x014 */
3783 + u32 cpu2_cfg; /* 0x018 */
3784 + u32 cpu3_cfg; /* 0x01c */
3785 + u8 res1[0x8]; /* 0x020 */
3786 + u32 apb0_gate; /* 0x028 */
3787 + u8 res2[0x14]; /* 0x02c */
3788 + u32 pll_ctrl0; /* 0x040 */
3789 + u32 pll_ctrl1; /* 0x044 */
3790 + u8 res3[0x8]; /* 0x048 */
3791 + u32 clk_1wire; /* 0x050 */
3792 + u32 clk_ir; /* 0x054 */
3793 + u8 res4[0x58]; /* 0x058 */
3794 + u32 apb0_reset; /* 0x0b0 */
3795 + u8 res5[0x3c]; /* 0x0b4 */
3796 + u32 clk_outd; /* 0x0f0 */
3797 + u8 res6[0xc]; /* 0x0f4 */
3798 + u32 cpu_pwroff; /* 0x100 */
3799 + u8 res7[0xc]; /* 0x104 */
3800 + u32 vdd_sys_pwroff; /* 0x110 */
3801 + u8 res8[0x4]; /* 0x114 */
3802 + u32 gpu_pwroff; /* 0x118 */
3803 + u8 res9[0x4]; /* 0x11c */
3804 + u32 vdd_pwr_reset; /* 0x120 */
3805 + u8 res10[0x20]; /* 0x124 */
3806 + u32 cpu1_pwr_clamp; /* 0x144 */
3807 + u32 cpu2_pwr_clamp; /* 0x148 */
3808 + u32 cpu3_pwr_clamp; /* 0x14c */
3809 + u8 res11[0x30]; /* 0x150 */
3810 + u32 dram_pwr; /* 0x180 */
3811 + u8 res12[0xc]; /* 0x184 */
3812 + u32 dram_tst; /* 0x190 */
3813 +};
3814 +
3815 +void prcm_apb0_enable(u32 flags);
3816 +#endif /* __ASSEMBLY__ */
3817 +#endif /* _PRCM_H */
3818 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/smp.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/smp.h
3819 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/smp.h 1970-01-01 01:00:00.000000000 +0100
3820 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/smp.h 2014-09-06 16:58:35.381953139 +0200
3821 @@ -0,0 +1,22 @@
3822 +/*
3823 + * (C) Copyright 2013
3824 + * Carl van Schaik <carl@ok-labs.com>
3825 + *
3826 + * CPU configuration registers for the sun7i (A20).
3827 + *
3828 + * SPDX-License-Identifier: GPL-2.0+
3829 + */
3830 +
3831 +#ifndef _SUNXI_SMP_H_
3832 +#define _SUNXI_SMP_H_
3833 +
3834 +#ifndef __ASSEMBLY__
3835 +
3836 +void startup_secondaries(void);
3837 +
3838 +/* Assembly entry point */
3839 +extern void secondary_init(void);
3840 +
3841 +#endif /* __ASSEMBLY__ */
3842 +
3843 +#endif /* _SUNXI_SMP_H_ */
3844 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/spl.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/spl.h
3845 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/spl.h 1970-01-01 01:00:00.000000000 +0100
3846 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/spl.h 2014-09-06 16:58:35.381953139 +0200
3847 @@ -0,0 +1,20 @@
3848 +/*
3849 + * This is a copy of omap3/spl.h:
3850 + *
3851 + * (C) Copyright 2012
3852 + * Texas Instruments, <www.ti.com>
3853 + *
3854 + * SPDX-License-Identifier: GPL-2.0+
3855 + */
3856 +#ifndef _ASM_ARCH_SPL_H_
3857 +#define _ASM_SPL_H_
3858 +
3859 +#define BOOT_DEVICE_NONE 0
3860 +#define BOOT_DEVICE_XIP 1
3861 +#define BOOT_DEVICE_NAND 2
3862 +#define BOOT_DEVICE_ONE_NAND 3
3863 +#define BOOT_DEVICE_MMC2 5 /*emmc*/
3864 +#define BOOT_DEVICE_MMC1 6
3865 +#define BOOT_DEVICE_XIPWAIT 7
3866 +#define BOOT_DEVICE_MMC2_2 0xff
3867 +#endif
3868 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/sys_proto.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/sys_proto.h
3869 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/sys_proto.h 1970-01-01 01:00:00.000000000 +0100
3870 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/sys_proto.h 2014-09-06 16:58:35.381953139 +0200
3871 @@ -0,0 +1,16 @@
3872 +/*
3873 + * (C) Copyright 2007-2012
3874 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3875 + * Tom Cubie <tangliang@allwinnertech.com>
3876 + *
3877 + * SPDX-License-Identifier: GPL-2.0+
3878 + */
3879 +
3880 +#ifndef _SYS_PROTO_H_
3881 +#define _SYS_PROTO_H_
3882 +
3883 +#include <linux/types.h>
3884 +
3885 +void sdelay(unsigned long);
3886 +
3887 +#endif
3888 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/timer.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/timer.h
3889 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/timer.h 1970-01-01 01:00:00.000000000 +0100
3890 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/timer.h 2014-09-06 16:58:35.381953139 +0200
3891 @@ -0,0 +1,88 @@
3892 +/*
3893 + * (C) Copyright 2007-2011
3894 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
3895 + * Tom Cubie <tangliang@allwinnertech.com>
3896 + *
3897 + * Configuration settings for the Allwinner A10-evb board.
3898 + *
3899 + * SPDX-License-Identifier: GPL-2.0+
3900 + */
3901 +
3902 +#ifndef _SUNXI_TIMER_H_
3903 +#define _SUNXI_TIMER_H_
3904 +
3905 +#ifndef __ASSEMBLY__
3906 +
3907 +#include <linux/types.h>
3908 +
3909 +/* General purpose timer */
3910 +struct sunxi_timer {
3911 + u32 ctl;
3912 + u32 inter;
3913 + u32 val;
3914 + u8 res[4];
3915 +};
3916 +
3917 +/* Audio video sync*/
3918 +struct sunxi_avs {
3919 + u32 ctl; /* 0x80 */
3920 + u32 cnt0; /* 0x84 */
3921 + u32 cnt1; /* 0x88 */
3922 + u32 div; /* 0x8c */
3923 +};
3924 +
3925 +/* 64 bit counter */
3926 +struct sunxi_64cnt {
3927 + u32 ctl; /* 0xa0 */
3928 + u32 lo; /* 0xa4 */
3929 + u32 hi; /* 0xa8 */
3930 +};
3931 +
3932 +/* Watchdog */
3933 +struct sunxi_wdog {
3934 + u32 ctl; /* 0x90 */
3935 + u32 mode; /* 0x94 */
3936 +};
3937 +
3938 +/* Rtc */
3939 +struct sunxi_rtc {
3940 + u32 ctl; /* 0x100 */
3941 + u32 yymmdd; /* 0x104 */
3942 + u32 hhmmss; /* 0x108 */
3943 +};
3944 +
3945 +/* Alarm */
3946 +struct sunxi_alarm {
3947 + u32 ddhhmmss; /* 0x10c */
3948 + u32 hhmmss; /* 0x110 */
3949 + u32 en; /* 0x114 */
3950 + u32 irqen; /* 0x118 */
3951 + u32 irqsta; /* 0x11c */
3952 +};
3953 +
3954 +/* Timer general purpose register */
3955 +struct sunxi_tgp {
3956 + u32 tgpd;
3957 +};
3958 +
3959 +struct sunxi_timer_reg {
3960 + u32 tirqen; /* 0x00 */
3961 + u32 tirqsta; /* 0x04 */
3962 + u8 res1[8];
3963 + struct sunxi_timer timer[6]; /* We have 6 timers */
3964 + u8 res2[16];
3965 + struct sunxi_avs avs;
3966 + struct sunxi_wdog wdog;
3967 + u8 res3[8];
3968 + struct sunxi_64cnt cnt64;
3969 + u8 res4[0x58];
3970 + struct sunxi_rtc rtc;
3971 + struct sunxi_alarm alarm;
3972 + struct sunxi_tgp tgp[4];
3973 + u8 res5[8];
3974 + u32 cpu_cfg;
3975 +};
3976 +
3977 +#endif /* __ASSEMBLY__ */
3978 +
3979 +#endif
3980 diff -ruN u-boot-2014.04/arch/arm/include/asm/arch-sunxi/watchdog.h u-boot-sunxi/arch/arm/include/asm/arch-sunxi/watchdog.h
3981 --- u-boot-2014.04/arch/arm/include/asm/arch-sunxi/watchdog.h 1970-01-01 01:00:00.000000000 +0100
3982 +++ u-boot-sunxi/arch/arm/include/asm/arch-sunxi/watchdog.h 2014-09-06 16:58:35.381953139 +0200
3983 @@ -0,0 +1,22 @@
3984 +/*
3985 + * Watchdog driver for the Allwinner sunxi platform.
3986 + * Copyright (C) 2013 Oliver Schinagl <oliver@schinagl.nl>
3987 + * http://www.linux-sunxi.org/
3988 + *
3989 + * SPDX-License-Identifier: GPL-2.0+
3990 + */
3991 +
3992 +#ifndef _SUNXI_WATCHDOG_H_
3993 +#define _SUNXI_WATCHDOG_H_
3994 +
3995 +/* Timeout limits */
3996 +#define WDT_MAX_TIMEOUT 16
3997 +#define WDT_OFF -1
3998 +
3999 +#ifndef __ASSEMBLY__
4000 +void watchdog_reset(void);
4001 +void watchdog_set(int timeout);
4002 +void watchdog_init(void);
4003 +#endif /* __ASSEMBLY__ */
4004 +
4005 +#endif
4006 diff -ruN u-boot-2014.04/board/sunxi/board.c u-boot-sunxi/board/sunxi/board.c
4007 --- u-boot-2014.04/board/sunxi/board.c 1970-01-01 01:00:00.000000000 +0100
4008 +++ u-boot-sunxi/board/sunxi/board.c 2014-09-06 16:58:36.161953116 +0200
4009 @@ -0,0 +1,239 @@
4010 +/*
4011 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4012 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
4013 + *
4014 + * (C) Copyright 2007-2011
4015 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4016 + * Tom Cubie <tangliang@allwinnertech.com>
4017 + *
4018 + * Some board init for the Allwinner A10-evb board.
4019 + *
4020 + * SPDX-License-Identifier: GPL-2.0+
4021 + */
4022 +
4023 +#include <common.h>
4024 +#ifdef CONFIG_AXP152_POWER
4025 +#include <axp152.h>
4026 +#endif
4027 +#ifdef CONFIG_AXP209_POWER
4028 +#include <axp209.h>
4029 +#endif
4030 +#ifdef CONFIG_AXP221_POWER
4031 +#include <axp221.h>
4032 +#endif
4033 +#include <asm/arch/clock.h>
4034 +#include <asm/arch/cpu.h>
4035 +#include <asm/arch/dram.h>
4036 +#include <asm/arch/gpio.h>
4037 +#include <asm/arch/mmc.h>
4038 +#include <asm/io.h>
4039 +#include <net.h>
4040 +
4041 +DECLARE_GLOBAL_DATA_PTR;
4042 +
4043 +/* add board specific code here */
4044 +int board_init(void)
4045 +{
4046 + int id_pfr1;
4047 +
4048 + gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
4049 +
4050 + asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
4051 + debug("id_pfr1: 0x%08x\n", id_pfr1);
4052 + /* Generic Timer Extension available? */
4053 + if ((id_pfr1 >> 16) & 0xf) {
4054 + debug("Setting CNTFRQ\n");
4055 + /* CNTFRQ == 24 MHz */
4056 + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
4057 + }
4058 +
4059 +#ifdef CONFIG_STATUS_LED
4060 + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
4061 +#endif
4062 + return 0;
4063 +}
4064 +
4065 +#ifdef CONFIG_DISPLAY_BOARDINFO
4066 +int checkboard(void)
4067 +{
4068 + printf("Board: %s\n", CONFIG_SYS_BOARD_NAME);
4069 +
4070 + return 0;
4071 +}
4072 +#endif
4073 +
4074 +int dram_init(void)
4075 +{
4076 + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
4077 +
4078 + return 0;
4079 +}
4080 +
4081 +#ifdef CONFIG_GENERIC_MMC
4082 +static void mmc_pinmux_setup(int sdc)
4083 +{
4084 + unsigned int pin;
4085 +
4086 + switch (sdc) {
4087 + case 0:
4088 + /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
4089 + for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
4090 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0);
4091 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
4092 + sunxi_gpio_set_drv(pin, 2);
4093 + }
4094 + break;
4095 +
4096 + case 1:
4097 + /* CMD-PH22, CLK-PH23, D0~D3-PH24~27 : 5 */
4098 + for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
4099 + sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1);
4100 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
4101 + sunxi_gpio_set_drv(pin, 2);
4102 + }
4103 + break;
4104 +
4105 + case 2:
4106 + /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
4107 + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
4108 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2);
4109 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
4110 + sunxi_gpio_set_drv(pin, 2);
4111 + }
4112 + break;
4113 +
4114 + case 3:
4115 + /* CMD-PI4, CLK-PI5, D0~D3-PI6~9 : 2 */
4116 + for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
4117 + sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3);
4118 + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
4119 + sunxi_gpio_set_drv(pin, 2);
4120 + }
4121 + break;
4122 +
4123 + default:
4124 + printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
4125 + break;
4126 + }
4127 +}
4128 +
4129 +int board_mmc_init(bd_t *bis)
4130 +{
4131 + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
4132 + sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
4133 +#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)
4134 + mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
4135 + sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
4136 +#endif
4137 +
4138 + return 0;
4139 +}
4140 +#endif
4141 +
4142 +void i2c_init_board(void)
4143 +{
4144 + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0);
4145 + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0);
4146 + clock_twi_onoff(0, 1);
4147 +}
4148 +
4149 +#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
4150 +void sunxi_board_init(void)
4151 +{
4152 + int power_failed = 0;
4153 +#if !defined(CONFIG_SUN6I) && !defined(CONFIG_SUN8I)
4154 + unsigned long ramsize;
4155 +#endif
4156 +
4157 +#ifdef CONFIG_AXP152_POWER
4158 + power_failed = axp152_init();
4159 + power_failed |= axp152_set_dcdc2(1400);
4160 + power_failed |= axp152_set_dcdc3(1500);
4161 + power_failed |= axp152_set_dcdc4(1250);
4162 + power_failed |= axp152_set_ldo2(3000);
4163 +#endif
4164 +#ifdef CONFIG_AXP209_POWER
4165 + power_failed |= axp209_init();
4166 + power_failed |= axp209_set_dcdc2(1400);
4167 +#ifdef CONFIG_FAST_MBUS
4168 + power_failed |= axp209_set_dcdc3(1300);
4169 +#else
4170 + power_failed |= axp209_set_dcdc3(1250);
4171 +#endif
4172 + power_failed |= axp209_set_ldo2(3000);
4173 + power_failed |= axp209_set_ldo3(2800);
4174 + power_failed |= axp209_set_ldo4(2800);
4175 +#endif
4176 +#ifdef CONFIG_AXP221_POWER
4177 + power_failed = axp221_init();
4178 + power_failed |= axp221_set_dcdc1(3300);
4179 + power_failed |= axp221_set_dcdc2(1200);
4180 + power_failed |= axp221_set_dcdc3(1260);
4181 + power_failed |= axp221_set_dcdc4(1200);
4182 + power_failed |= axp221_set_dcdc5(1500);
4183 +#ifdef CONFIG_ENABLE_DLDO1_POWER
4184 + power_failed |= axp221_set_dldo1(3300);
4185 +#endif
4186 +#endif
4187 +
4188 +#if !defined(CONFIG_SUN6I) && !defined(CONFIG_SUN8I)
4189 + printf("DRAM:");
4190 + ramsize = sunxi_dram_init();
4191 + printf(" %lu MiB\n", ramsize >> 20);
4192 + if (!ramsize)
4193 + hang();
4194 +
4195 + /*
4196 + * Only clock up the CPU to full speed if we are reasonably
4197 + * assured it's being powered with suitable core voltage
4198 + */
4199 + if (!power_failed)
4200 + clock_set_pll1(CONFIG_CLK_FULL_SPEED);
4201 + else
4202 + printf("Failed to set core voltage! Can't set CPU frequency\n");
4203 +#endif
4204 +}
4205 +#endif
4206 +
4207 +#if defined(CONFIG_SPL_OS_BOOT) && defined(CONFIG_AXP209_POWER)
4208 +int spl_start_uboot(void)
4209 +{
4210 + if (axp209_poweron_by_dc())
4211 + return 0;
4212 + axp209_power_button(); /* Clear any pending button event */
4213 + mdelay(100);
4214 + return axp209_power_button();
4215 +}
4216 +#endif
4217 +
4218 +#ifdef CONFIG_SPL_DISPLAY_PRINT
4219 +void spl_display_print(void)
4220 +{
4221 + printf("Board: %s\n", CONFIG_SYS_BOARD_NAME);
4222 +}
4223 +#endif
4224 +
4225 +#ifdef CONFIG_MISC_INIT_R
4226 +int misc_init_r(void)
4227 +{
4228 + if (!getenv("ethaddr")) {
4229 + uint32_t reg_val = readl(SUNXI_SID_BASE);
4230 +
4231 + if (reg_val) {
4232 + uint8_t mac_addr[6];
4233 +
4234 + mac_addr[0] = 0x02; /* Non OUI / registered MAC address */
4235 + mac_addr[1] = (reg_val >> 0) & 0xff;
4236 + reg_val = readl(SUNXI_SID_BASE + 0x0c);
4237 + mac_addr[2] = (reg_val >> 24) & 0xff;
4238 + mac_addr[3] = (reg_val >> 16) & 0xff;
4239 + mac_addr[4] = (reg_val >> 8) & 0xff;
4240 + mac_addr[5] = (reg_val >> 0) & 0xff;
4241 +
4242 + eth_setenv_enetaddr("ethaddr", mac_addr);
4243 + }
4244 + }
4245 +
4246 + return 0;
4247 +}
4248 +#endif
4249 diff -ruN u-boot-2014.04/board/sunxi/dram_a10_olinuxino_l.c u-boot-sunxi/board/sunxi/dram_a10_olinuxino_l.c
4250 --- u-boot-2014.04/board/sunxi/dram_a10_olinuxino_l.c 1970-01-01 01:00:00.000000000 +0100
4251 +++ u-boot-sunxi/board/sunxi/dram_a10_olinuxino_l.c 2014-09-06 16:58:36.161953116 +0200
4252 @@ -0,0 +1,31 @@
4253 +/* this file is generated, don't edit it yourself */
4254 +
4255 +#include <common.h>
4256 +#include <asm/arch/dram.h>
4257 +
4258 +static struct dram_para dram_para = {
4259 + .clock = 480,
4260 + .type = 3,
4261 + .rank_num = 1,
4262 + .density = 4096,
4263 + .io_width = 16,
4264 + .bus_width = 16,
4265 + .cas = 6,
4266 + .zq = 123,
4267 + .odt_en = 0,
4268 + .size = 512,
4269 + .tpr0 = 0x30926692,
4270 + .tpr1 = 0x1090,
4271 + .tpr2 = 0x1a0c8,
4272 + .tpr3 = 0,
4273 + .tpr4 = 0,
4274 + .tpr5 = 0,
4275 + .emr1 = 0x4,
4276 + .emr2 = 0,
4277 + .emr3 = 0,
4278 +};
4279 +
4280 +unsigned long sunxi_dram_init(void)
4281 +{
4282 + return dramc_init(&dram_para);
4283 +}
4284 diff -ruN u-boot-2014.04/board/sunxi/dram_a13_oli_micro.c u-boot-sunxi/board/sunxi/dram_a13_oli_micro.c
4285 --- u-boot-2014.04/board/sunxi/dram_a13_oli_micro.c 1970-01-01 01:00:00.000000000 +0100
4286 +++ u-boot-sunxi/board/sunxi/dram_a13_oli_micro.c 2014-09-06 16:58:36.161953116 +0200
4287 @@ -0,0 +1,32 @@
4288 +/* this file is generated, don't edit it yourself */
4289 +
4290 +#include <common.h>
4291 +#include <asm/arch/dram.h>
4292 +
4293 +static struct dram_para dram_para = {
4294 + .clock = 408,
4295 + .type = 3,
4296 + .rank_num = 1,
4297 + .density = 2048,
4298 + .io_width = 16,
4299 + .bus_width = 16,
4300 + .cas = 9,
4301 + .zq = 123,
4302 + .odt_en = 0,
4303 + .size = 256,
4304 + .tpr0 = 0x42d899b7,
4305 + .tpr1 = 0xa090,
4306 + .tpr2 = 0x22a00,
4307 + .tpr3 = 0,
4308 + .tpr4 = 0,
4309 + .tpr5 = 0,
4310 + .emr1 = 0,
4311 + .emr2 = 0x10,
4312 + .emr3 = 0,
4313 +
4314 +};
4315 +
4316 +unsigned long sunxi_dram_init(void)
4317 +{
4318 + return dramc_init(&dram_para);
4319 +}
4320 diff -ruN u-boot-2014.04/board/sunxi/dram_a13_olinuxino.c u-boot-sunxi/board/sunxi/dram_a13_olinuxino.c
4321 --- u-boot-2014.04/board/sunxi/dram_a13_olinuxino.c 1970-01-01 01:00:00.000000000 +0100
4322 +++ u-boot-sunxi/board/sunxi/dram_a13_olinuxino.c 2014-09-06 16:58:36.161953116 +0200
4323 @@ -0,0 +1,31 @@
4324 +/* this file is generated, don't edit it yourself */
4325 +
4326 +#include <common.h>
4327 +#include <asm/arch/dram.h>
4328 +
4329 +static struct dram_para dram_para = {
4330 + .clock = 408,
4331 + .type = 3,
4332 + .rank_num = 1,
4333 + .density = 2048,
4334 + .io_width = 8,
4335 + .bus_width = 16,
4336 + .cas = 9,
4337 + .zq = 123,
4338 + .odt_en = 0,
4339 + .size = 512,
4340 + .tpr0 = 0x42d899b7,
4341 + .tpr1 = 0xa090,
4342 + .tpr2 = 0x22a00,
4343 + .tpr3 = 0,
4344 + .tpr4 = 0,
4345 + .tpr5 = 0,
4346 + .emr1 = 0,
4347 + .emr2 = 0x10,
4348 + .emr3 = 0,
4349 +};
4350 +
4351 +unsigned long sunxi_dram_init(void)
4352 +{
4353 + return dramc_init(&dram_para);
4354 +}
4355 diff -ruN u-boot-2014.04/board/sunxi/dram_a20_olinuxino_l2.c u-boot-sunxi/board/sunxi/dram_a20_olinuxino_l2.c
4356 --- u-boot-2014.04/board/sunxi/dram_a20_olinuxino_l2.c 1970-01-01 01:00:00.000000000 +0100
4357 +++ u-boot-sunxi/board/sunxi/dram_a20_olinuxino_l2.c 2014-09-06 16:58:36.161953116 +0200
4358 @@ -0,0 +1,31 @@
4359 +/* this file is generated, don't edit it yourself */
4360 +
4361 +#include "common.h"
4362 +#include <asm/arch/dram.h>
4363 +
4364 +static struct dram_para dram_para = {
4365 + .clock = 480,
4366 + .type = 3,
4367 + .rank_num = 1,
4368 + .density = 4096,
4369 + .io_width = 16,
4370 + .bus_width = 32,
4371 + .cas = 9,
4372 + .zq = 0x7f,
4373 + .odt_en = 0,
4374 + .size = 1024,
4375 + .tpr0 = 0x42d899b7,
4376 + .tpr1 = 0xa090,
4377 + .tpr2 = 0x22a00,
4378 + .tpr3 = 0,
4379 + .tpr4 = 0,
4380 + .tpr5 = 0,
4381 + .emr1 = 0x4,
4382 + .emr2 = 0x10,
4383 + .emr3 = 0,
4384 +};
4385 +
4386 +unsigned long sunxi_dram_init(void)
4387 +{
4388 + return dramc_init(&dram_para);
4389 +}
4390 diff -ruN u-boot-2014.04/board/sunxi/dram_a20_olinuxino_l.c u-boot-sunxi/board/sunxi/dram_a20_olinuxino_l.c
4391 --- u-boot-2014.04/board/sunxi/dram_a20_olinuxino_l.c 1970-01-01 01:00:00.000000000 +0100
4392 +++ u-boot-sunxi/board/sunxi/dram_a20_olinuxino_l.c 2014-09-06 16:58:36.161953116 +0200
4393 @@ -0,0 +1,31 @@
4394 +/* this file is generated, don't edit it yourself */
4395 +
4396 +#include "common.h"
4397 +#include <asm/arch/dram.h>
4398 +
4399 +static struct dram_para dram_para = {
4400 + .clock = 480,
4401 + .type = 3,
4402 + .rank_num = 1,
4403 + .density = 4096,
4404 + .io_width = 16,
4405 + .bus_width = 16,
4406 + .cas = 9,
4407 + .zq = 0x7f,
4408 + .odt_en = 0,
4409 + .size = 512,
4410 + .tpr0 = 0x42d899b7,
4411 + .tpr1 = 0xa090,
4412 + .tpr2 = 0x22a00,
4413 + .tpr3 = 0,
4414 + .tpr4 = 0,
4415 + .tpr5 = 0,
4416 + .emr1 = 0x4,
4417 + .emr2 = 0x10,
4418 + .emr3 = 0,
4419 +};
4420 +
4421 +unsigned long sunxi_dram_init(void)
4422 +{
4423 + return dramc_init(&dram_para);
4424 +}
4425 diff -ruN u-boot-2014.04/board/sunxi/dram_ainol_aw1.c u-boot-sunxi/board/sunxi/dram_ainol_aw1.c
4426 --- u-boot-2014.04/board/sunxi/dram_ainol_aw1.c 1970-01-01 01:00:00.000000000 +0100
4427 +++ u-boot-sunxi/board/sunxi/dram_ainol_aw1.c 2014-09-06 16:58:36.161953116 +0200
4428 @@ -0,0 +1,31 @@
4429 +/* this file is generated, don't edit it yourself */
4430 +
4431 +#include "common.h"
4432 +#include <asm/arch/dram.h>
4433 +
4434 +static struct dram_para dram_para = {
4435 + .clock = 432,
4436 + .type = 3,
4437 + .rank_num = 1,
4438 + .density = 2048,
4439 + .io_width = 16,
4440 + .bus_width = 32,
4441 + .cas = 9,
4442 + .zq = 0x7b,
4443 + .odt_en = 0,
4444 + .size = 512,
4445 + .tpr0 = 0x42d899b7,
4446 + .tpr1 = 0xa090,
4447 + .tpr2 = 0x22a00,
4448 + .tpr3 = 0,
4449 + .tpr4 = 1,
4450 + .tpr5 = 0,
4451 + .emr1 = 0x4,
4452 + .emr2 = 0x10,
4453 + .emr3 = 0,
4454 +};
4455 +
4456 +unsigned long sunxi_dram_init(void)
4457 +{
4458 + return dramc_init(&dram_para);
4459 +}
4460 diff -ruN u-boot-2014.04/board/sunxi/dram_auxtek_t003.c u-boot-sunxi/board/sunxi/dram_auxtek_t003.c
4461 --- u-boot-2014.04/board/sunxi/dram_auxtek_t003.c 1970-01-01 01:00:00.000000000 +0100
4462 +++ u-boot-sunxi/board/sunxi/dram_auxtek_t003.c 2014-09-06 16:58:36.161953116 +0200
4463 @@ -0,0 +1,31 @@
4464 +/* this file is generated, don't edit it yourself */
4465 +
4466 +#include <common.h>
4467 +#include <asm/arch/dram.h>
4468 +
4469 +static struct dram_para dram_para = {
4470 + .clock = 408,
4471 + .type = 3,
4472 + .rank_num = 1,
4473 + .density = 2048,
4474 + .io_width = 8,
4475 + .bus_width = 32,
4476 + .cas = 9,
4477 + .zq = 123,
4478 + .odt_en = 0,
4479 + .size = 1024,
4480 + .tpr0 = 0x42d899b7,
4481 + .tpr1 = 0xa090,
4482 + .tpr2 = 0x22a00,
4483 + .tpr3 = 0,
4484 + .tpr4 = 0,
4485 + .tpr5 = 0,
4486 + .emr1 = 0,
4487 + .emr2 = 0x10,
4488 + .emr3 = 0,
4489 +};
4490 +
4491 +unsigned long sunxi_dram_init(void)
4492 +{
4493 + return dramc_init(&dram_para);
4494 +}
4495 diff -ruN u-boot-2014.04/board/sunxi/dram_cubieboard.c u-boot-sunxi/board/sunxi/dram_cubieboard.c
4496 --- u-boot-2014.04/board/sunxi/dram_cubieboard.c 1970-01-01 01:00:00.000000000 +0100
4497 +++ u-boot-sunxi/board/sunxi/dram_cubieboard.c 2014-09-06 16:58:36.161953116 +0200
4498 @@ -0,0 +1,31 @@
4499 +/* this file is generated, don't edit it yourself */
4500 +
4501 +#include <common.h>
4502 +#include <asm/arch/dram.h>
4503 +
4504 +static struct dram_para dram_para = {
4505 + .clock = 480,
4506 + .type = 3,
4507 + .rank_num = 1,
4508 + .density = 4096,
4509 + .io_width = 16,
4510 + .bus_width = 32,
4511 + .cas = 6,
4512 + .zq = 123,
4513 + .odt_en = 0,
4514 + .size = 1024,
4515 + .tpr0 = 0x30926692,
4516 + .tpr1 = 0x1090,
4517 + .tpr2 = 0x1a0c8,
4518 + .tpr3 = 0,
4519 + .tpr4 = 0,
4520 + .tpr5 = 0,
4521 + .emr1 = 0,
4522 + .emr2 = 0,
4523 + .emr3 = 0,
4524 +};
4525 +
4526 +unsigned long sunxi_dram_init(void)
4527 +{
4528 + return dramc_init(&dram_para);
4529 +}
4530 diff -ruN u-boot-2014.04/board/sunxi/dram_cubietruck.c u-boot-sunxi/board/sunxi/dram_cubietruck.c
4531 --- u-boot-2014.04/board/sunxi/dram_cubietruck.c 1970-01-01 01:00:00.000000000 +0100
4532 +++ u-boot-sunxi/board/sunxi/dram_cubietruck.c 2014-09-06 16:58:36.161953116 +0200
4533 @@ -0,0 +1,31 @@
4534 +/* this file is generated, don't edit it yourself */
4535 +
4536 +#include <common.h>
4537 +#include <asm/arch/dram.h>
4538 +
4539 +static struct dram_para dram_para = {
4540 + .clock = 432,
4541 + .type = 3,
4542 + .rank_num = 1,
4543 + .density = 4096,
4544 + .io_width = 8,
4545 + .bus_width = 32,
4546 + .cas = 9,
4547 + .zq = 0x7f,
4548 + .odt_en = 0,
4549 + .size = 2048,
4550 + .tpr0 = 0x42d899b7,
4551 + .tpr1 = 0xa090,
4552 + .tpr2 = 0x22a00,
4553 + .tpr3 = 0x0,
4554 + .tpr4 = 0x1,
4555 + .tpr5 = 0x0,
4556 + .emr1 = 0x4,
4557 + .emr2 = 0x10,
4558 + .emr3 = 0x0,
4559 +};
4560 +
4561 +unsigned long sunxi_dram_init(void)
4562 +{
4563 + return dramc_init(&dram_para);
4564 +}
4565 diff -ruN u-boot-2014.04/board/sunxi/dram_eu3000.c u-boot-sunxi/board/sunxi/dram_eu3000.c
4566 --- u-boot-2014.04/board/sunxi/dram_eu3000.c 1970-01-01 01:00:00.000000000 +0100
4567 +++ u-boot-sunxi/board/sunxi/dram_eu3000.c 2014-09-06 16:58:36.161953116 +0200
4568 @@ -0,0 +1,31 @@
4569 +/* this file is generated, don't edit it yourself */
4570 +
4571 +#include "common.h"
4572 +#include <asm/arch/dram.h>
4573 +
4574 +static struct dram_para dram_para = {
4575 + .clock = 432,
4576 + .type = 3,
4577 + .rank_num = 1,
4578 + .density = 4096,
4579 + .io_width = 16,
4580 + .bus_width = 32,
4581 + .cas = 9,
4582 + .zq = 0x7b,
4583 + .odt_en = 0,
4584 + .size = 1024,
4585 + .tpr0 = 0x42d899b7,
4586 + .tpr1 = 0xa090,
4587 + .tpr2 = 0x22a00,
4588 + .tpr3 = 0,
4589 + .tpr4 = 1,
4590 + .tpr5 = 0,
4591 + .emr1 = 0x4,
4592 + .emr2 = 0x10,
4593 + .emr3 = 0,
4594 +};
4595 +
4596 +unsigned long sunxi_dram_init(void)
4597 +{
4598 + return dramc_init(&dram_para);
4599 +}
4600 diff -ruN u-boot-2014.04/board/sunxi/dram_forfun_q88db.c u-boot-sunxi/board/sunxi/dram_forfun_q88db.c
4601 --- u-boot-2014.04/board/sunxi/dram_forfun_q88db.c 1970-01-01 01:00:00.000000000 +0100
4602 +++ u-boot-sunxi/board/sunxi/dram_forfun_q88db.c 2014-09-06 16:58:36.161953116 +0200
4603 @@ -0,0 +1,31 @@
4604 +/* this file is generated, don't edit it yourself */
4605 +
4606 +#include "common.h"
4607 +#include <asm/arch/dram.h>
4608 +
4609 +static struct dram_para dram_para = {
4610 + .clock = 384,
4611 + .type = 3,
4612 + .rank_num = 1,
4613 + .density = 4096,
4614 + .io_width = 16,
4615 + .bus_width = 16,
4616 + .cas = 9,
4617 + .zq = 0x7b,
4618 + .odt_en = 0,
4619 + .size = 512,
4620 + .tpr0 = 0x42d899b7,
4621 + .tpr1 = 0xa090,
4622 + .tpr2 = 0x22a00,
4623 + .tpr3 = 0,
4624 + .tpr4 = 0,
4625 + .tpr5 = 0,
4626 + .emr1 = 0x4,
4627 + .emr2 = 0x10,
4628 + .emr3 = 0,
4629 +};
4630 +
4631 +unsigned long sunxi_dram_init(void)
4632 +{
4633 + return dramc_init(&dram_para);
4634 +}
4635 diff -ruN u-boot-2014.04/board/sunxi/dram_gooseberry_a721.c u-boot-sunxi/board/sunxi/dram_gooseberry_a721.c
4636 --- u-boot-2014.04/board/sunxi/dram_gooseberry_a721.c 1970-01-01 01:00:00.000000000 +0100
4637 +++ u-boot-sunxi/board/sunxi/dram_gooseberry_a721.c 2014-09-06 16:58:36.161953116 +0200
4638 @@ -0,0 +1,31 @@
4639 +/* this file is generated, don't edit it yourself */
4640 +
4641 +#include <common.h>
4642 +#include <asm/arch/dram.h>
4643 +
4644 +static struct dram_para dram_para = {
4645 + .clock = 360,
4646 + .type = 3,
4647 + .rank_num = 1,
4648 + .density = 1024,
4649 + .io_width = 8,
4650 + .bus_width = 32,
4651 + .cas = 6,
4652 + .zq = 123,
4653 + .odt_en = 0,
4654 + .size = 512,
4655 + .tpr0 = 0x30926692,
4656 + .tpr1 = 0x1090,
4657 + .tpr2 = 0x1a0c8,
4658 + .tpr3 = 0,
4659 + .tpr4 = 0,
4660 + .tpr5 = 0,
4661 + .emr1 = 0x4,
4662 + .emr2 = 0,
4663 + .emr3 = 0,
4664 +};
4665 +
4666 +unsigned long sunxi_dram_init(void)
4667 +{
4668 + return dramc_init(&dram_para);
4669 +}
4670 diff -ruN u-boot-2014.04/board/sunxi/dram_h6.c u-boot-sunxi/board/sunxi/dram_h6.c
4671 --- u-boot-2014.04/board/sunxi/dram_h6.c 1970-01-01 01:00:00.000000000 +0100
4672 +++ u-boot-sunxi/board/sunxi/dram_h6.c 2014-09-06 16:58:36.161953116 +0200
4673 @@ -0,0 +1,31 @@
4674 +/* this file is generated, don't edit it yourself */
4675 +
4676 +#include <common.h>
4677 +#include <asm/arch/dram.h>
4678 +
4679 +static struct dram_para dram_para = {
4680 + .clock = 360,
4681 + .type = 3,
4682 + .rank_num = 1,
4683 + .density = 4096,
4684 + .io_width = 16,
4685 + .bus_width = 32,
4686 + .cas = 6,
4687 + .zq = 123,
4688 + .odt_en = 0,
4689 + .size = 1024,
4690 + .tpr0 = 0x30926692,
4691 + .tpr1 = 0x1090,
4692 + .tpr2 = 0x1a0c8,
4693 + .tpr3 = 0,
4694 + .tpr4 = 0,
4695 + .tpr5 = 0,
4696 + .emr1 = 0x4,
4697 + .emr2 = 0,
4698 + .emr3 = 0,
4699 +};
4700 +
4701 +unsigned long sunxi_dram_init(void)
4702 +{
4703 + return dramc_init(&dram_para);
4704 +}
4705 diff -ruN u-boot-2014.04/board/sunxi/dram_hackberry.c u-boot-sunxi/board/sunxi/dram_hackberry.c
4706 --- u-boot-2014.04/board/sunxi/dram_hackberry.c 1970-01-01 01:00:00.000000000 +0100
4707 +++ u-boot-sunxi/board/sunxi/dram_hackberry.c 2014-09-06 16:58:36.161953116 +0200
4708 @@ -0,0 +1,31 @@
4709 +/* this file is generated, don't edit it yourself */
4710 +
4711 +#include <common.h>
4712 +#include <asm/arch/dram.h>
4713 +
4714 +static struct dram_para dram_para = {
4715 + .clock = 408,
4716 + .type = 3,
4717 + .rank_num = 1,
4718 + .density = 4096,
4719 + .io_width = 16,
4720 + .bus_width = 32,
4721 + .cas = 6,
4722 + .zq = 123,
4723 + .odt_en = 1,
4724 + .size = 1024,
4725 + .tpr0 = 0x30926692,
4726 + .tpr1 = 0x1090,
4727 + .tpr2 = 0x1a0c8,
4728 + .tpr3 = 0,
4729 + .tpr4 = 0,
4730 + .tpr5 = 0,
4731 + .emr1 = 0,
4732 + .emr2 = 0,
4733 + .emr3 = 0,
4734 +};
4735 +
4736 +unsigned long sunxi_dram_init(void)
4737 +{
4738 + return dramc_init(&dram_para);
4739 +}
4740 diff -ruN u-boot-2014.04/board/sunxi/dram_icou_fatty_i.c u-boot-sunxi/board/sunxi/dram_icou_fatty_i.c
4741 --- u-boot-2014.04/board/sunxi/dram_icou_fatty_i.c 1970-01-01 01:00:00.000000000 +0100
4742 +++ u-boot-sunxi/board/sunxi/dram_icou_fatty_i.c 2014-09-06 16:58:36.161953116 +0200
4743 @@ -0,0 +1,31 @@
4744 +/* this file is generated, don't edit it yourself */
4745 +
4746 +#include "common.h"
4747 +#include <asm/arch/dram.h>
4748 +
4749 +static struct dram_para dram_para = {
4750 + .clock = 384,
4751 + .type = 3,
4752 + .rank_num = 1,
4753 + .density = 4096,
4754 + .io_width = 16,
4755 + .bus_width = 32,
4756 + .cas = 9,
4757 + .zq = 0x7f,
4758 + .odt_en = 0,
4759 + .size = 1024,
4760 + .tpr0 = 0x42d899b7,
4761 + .tpr1 = 0xa090,
4762 + .tpr2 = 0x22a00,
4763 + .tpr3 = 0,
4764 + .tpr4 = 1,
4765 + .tpr5 = 0,
4766 + .emr1 = 0x4,
4767 + .emr2 = 0x10,
4768 + .emr3 = 0,
4769 +};
4770 +
4771 +unsigned long sunxi_dram_init(void)
4772 +{
4773 + return dramc_init(&dram_para);
4774 +}
4775 diff -ruN u-boot-2014.04/board/sunxi/dram_inet_k70hc.c u-boot-sunxi/board/sunxi/dram_inet_k70hc.c
4776 --- u-boot-2014.04/board/sunxi/dram_inet_k70hc.c 1970-01-01 01:00:00.000000000 +0100
4777 +++ u-boot-sunxi/board/sunxi/dram_inet_k70hc.c 2014-09-06 16:58:36.161953116 +0200
4778 @@ -0,0 +1,31 @@
4779 +/* this file is generated, don't edit it yourself */
4780 +
4781 +#include <common.h>
4782 +#include <asm/arch/dram.h>
4783 +
4784 +static struct dram_para dram_para = {
4785 + .clock = 384,
4786 + .type = 3,
4787 + .rank_num = 1,
4788 + .density = 4096,
4789 + .io_width = 16,
4790 + .bus_width = 32,
4791 + .cas = 9,
4792 + .zq = 0x12331a7f,
4793 + .odt_en = 0,
4794 + .size = 1024,
4795 + .tpr0 = 0x42d899b7,
4796 + .tpr1 = 0xa090,
4797 + .tpr2 = 0x22a00,
4798 + .tpr3 = 0,
4799 + .tpr4 = 1,
4800 + .tpr5 = 0,
4801 + .emr1 = 0x4,
4802 + .emr2 = 0x10,
4803 + .emr3 = 0,
4804 +};
4805 +
4806 +unsigned long sunxi_dram_init(void)
4807 +{
4808 + return dramc_init(&dram_para);
4809 +}
4810 diff -ruN u-boot-2014.04/board/sunxi/dram_linksprite_pcduino3.c u-boot-sunxi/board/sunxi/dram_linksprite_pcduino3.c
4811 --- u-boot-2014.04/board/sunxi/dram_linksprite_pcduino3.c 1970-01-01 01:00:00.000000000 +0100
4812 +++ u-boot-sunxi/board/sunxi/dram_linksprite_pcduino3.c 2014-09-06 16:58:36.161953116 +0200
4813 @@ -0,0 +1,31 @@
4814 +/* this file is generated, don't edit it yourself */
4815 +
4816 +#include <common.h>
4817 +#include <asm/arch/dram.h>
4818 +
4819 +static struct dram_para dram_para = {
4820 + .clock = 480,
4821 + .type = 3,
4822 + .rank_num = 1,
4823 + .density = 4096,
4824 + .io_width = 16,
4825 + .bus_width = 32,
4826 + .cas = 9,
4827 + .zq = 0x7a,
4828 + .odt_en = 0,
4829 + .size = 1024,
4830 + .tpr0 = 0x42d899b7,
4831 + .tpr1 = 0xa090,
4832 + .tpr2 = 0x22a00,
4833 + .tpr3 = 0,
4834 + .tpr4 = 0,
4835 + .tpr5 = 0,
4836 + .emr1 = 0x4,
4837 + .emr2 = 0x10,
4838 + .emr3 = 0x0,
4839 +};
4840 +
4841 +unsigned long sunxi_dram_init(void)
4842 +{
4843 + return dramc_init(&dram_para);
4844 +}
4845 diff -ruN u-boot-2014.04/board/sunxi/dram_megafeis_a08.c u-boot-sunxi/board/sunxi/dram_megafeis_a08.c
4846 --- u-boot-2014.04/board/sunxi/dram_megafeis_a08.c 1970-01-01 01:00:00.000000000 +0100
4847 +++ u-boot-sunxi/board/sunxi/dram_megafeis_a08.c 2014-09-06 16:58:36.161953116 +0200
4848 @@ -0,0 +1,31 @@
4849 +/* this file is generated, don't edit it yourself */
4850 +
4851 +#include <common.h>
4852 +#include <asm/arch/dram.h>
4853 +
4854 +static struct dram_para dram_para = {
4855 + .clock = 432,
4856 + .type = 3,
4857 + .rank_num = 1,
4858 + .density = 4096,
4859 + .io_width = 16,
4860 + .bus_width = 16,
4861 + .cas = 9,
4862 + .zq = 123,
4863 + .odt_en = 0,
4864 + .size = 512,
4865 + .tpr0 = 0x42d899b7,
4866 + .tpr1 = 0xa090,
4867 + .tpr2 = 0x22a00,
4868 + .tpr3 = 0,
4869 + .tpr4 = 0,
4870 + .tpr5 = 0,
4871 + .emr1 = 0,
4872 + .emr2 = 0x10,
4873 + .emr3 = 0,
4874 +};
4875 +
4876 +unsigned long sunxi_dram_init(void)
4877 +{
4878 + return dramc_init(&dram_para);
4879 +}
4880 diff -ruN u-boot-2014.04/board/sunxi/dram_merrii_m2.c u-boot-sunxi/board/sunxi/dram_merrii_m2.c
4881 --- u-boot-2014.04/board/sunxi/dram_merrii_m2.c 1970-01-01 01:00:00.000000000 +0100
4882 +++ u-boot-sunxi/board/sunxi/dram_merrii_m2.c 2014-09-06 16:58:36.161953116 +0200
4883 @@ -0,0 +1,31 @@
4884 +/* this file is generated, don't edit it yourself */
4885 +
4886 +#include <common.h>
4887 +#include <asm/arch/dram.h>
4888 +
4889 +static struct dram_para dram_para = {
4890 + .clock = 432,
4891 + .type = 3,
4892 + .rank_num = 1,
4893 + .density = 4096,
4894 + .io_width = 16,
4895 + .bus_width = 32,
4896 + .cas = 9,
4897 + .zq = 127,
4898 + .odt_en = 0,
4899 + .size = 1024,
4900 + .tpr0 = 0x42d899b7,
4901 + .tpr1 = 0xa090,
4902 + .tpr2 = 0x22a00,
4903 + .tpr3 = 0x0,
4904 + .tpr4 = 0x0,
4905 + .tpr5 = 0x0,
4906 + .emr1 = 0x4,
4907 + .emr2 = 0x10,
4908 + .emr3 = 0x0,
4909 +};
4910 +
4911 +unsigned long sunxi_dram_init(void)
4912 +{
4913 + return dramc_init(&dram_para);
4914 +}
4915 diff -ruN u-boot-2014.04/board/sunxi/dram_mini_x_a10s.c u-boot-sunxi/board/sunxi/dram_mini_x_a10s.c
4916 --- u-boot-2014.04/board/sunxi/dram_mini_x_a10s.c 1970-01-01 01:00:00.000000000 +0100
4917 +++ u-boot-sunxi/board/sunxi/dram_mini_x_a10s.c 2014-09-06 16:58:36.161953116 +0200
4918 @@ -0,0 +1,31 @@
4919 +/* this file is generated, don't edit it yourself */
4920 +
4921 +#include <common.h>
4922 +#include <asm/arch/dram.h>
4923 +
4924 +static struct dram_para dram_para = {
4925 + .clock = 432,
4926 + .type = 3,
4927 + .rank_num = 1,
4928 + .density = 2048,
4929 + .io_width = 16,
4930 + .bus_width = 32,
4931 + .cas = 9,
4932 + .zq = 123,
4933 + .odt_en = 0,
4934 + .size = 1024,
4935 + .tpr0 = 0x42d899b7,
4936 + .tpr1 = 0xa090,
4937 + .tpr2 = 0x22a00,
4938 + .tpr3 = 0,
4939 + .tpr4 = 0,
4940 + .tpr5 = 0,
4941 + .emr1 = 0,
4942 + .emr2 = 0x10,
4943 + .emr3 = 0,
4944 +};
4945 +
4946 +unsigned long sunxi_dram_init(void)
4947 +{
4948 + return dramc_init(&dram_para);
4949 +}
4950 diff -ruN u-boot-2014.04/board/sunxi/dram_mk802_a10s.c u-boot-sunxi/board/sunxi/dram_mk802_a10s.c
4951 --- u-boot-2014.04/board/sunxi/dram_mk802_a10s.c 1970-01-01 01:00:00.000000000 +0100
4952 +++ u-boot-sunxi/board/sunxi/dram_mk802_a10s.c 2014-09-06 16:58:36.161953116 +0200
4953 @@ -0,0 +1,31 @@
4954 +/* this file is generated, don't edit it yourself */
4955 +
4956 +#include <common.h>
4957 +#include <asm/arch/dram.h>
4958 +
4959 +static struct dram_para dram_para = {
4960 + .clock = 432,
4961 + .type = 3,
4962 + .rank_num = 1,
4963 + .density = 2048,
4964 + .io_width = 8,
4965 + .bus_width = 32,
4966 + .cas = 9,
4967 + .zq = 123,
4968 + .odt_en = 0,
4969 + .size = 1024,
4970 + .tpr0 = 0x42d899b7,
4971 + .tpr1 = 0xa090,
4972 + .tpr2 = 0x22a00,
4973 + .tpr3 = 0,
4974 + .tpr4 = 0,
4975 + .tpr5 = 0,
4976 + .emr1 = 0,
4977 + .emr2 = 0x10,
4978 + .emr3 = 0,
4979 +};
4980 +
4981 +unsigned long sunxi_dram_init(void)
4982 +{
4983 + return dramc_init(&dram_para);
4984 +}
4985 diff -ruN u-boot-2014.04/board/sunxi/dram_mk802ii_a20.c u-boot-sunxi/board/sunxi/dram_mk802ii_a20.c
4986 --- u-boot-2014.04/board/sunxi/dram_mk802ii_a20.c 1970-01-01 01:00:00.000000000 +0100
4987 +++ u-boot-sunxi/board/sunxi/dram_mk802ii_a20.c 2014-09-06 16:58:36.161953116 +0200
4988 @@ -0,0 +1,31 @@
4989 +/* this file is generated, don't edit it yourself */
4990 +
4991 +#include "common.h"
4992 +#include <asm/arch/dram.h>
4993 +
4994 +static struct dram_para dram_para = {
4995 + .clock = 360,
4996 + .type = 3,
4997 + .rank_num = 1,
4998 + .density = 4096,
4999 + .io_width = 16,
5000 + .bus_width = 32,
5001 + .cas = 9,
5002 + .zq = 0x7f,
5003 + .odt_en = 0,
5004 + .size = 1024,
5005 + .tpr0 = 0x42d899b7,
5006 + .tpr1 = 0xa090,
5007 + .tpr2 = 0x22a00,
5008 + .tpr3 = 0,
5009 + .tpr4 = 0,
5010 + .tpr5 = 0,
5011 + .emr1 = 0x4,
5012 + .emr2 = 0x10,
5013 + .emr3 = 0,
5014 +};
5015 +
5016 +unsigned long sunxi_dram_init(void)
5017 +{
5018 + return dramc_init(&dram_para);
5019 +}
5020 diff -ruN u-boot-2014.04/board/sunxi/dram_olimex_a13_som.c u-boot-sunxi/board/sunxi/dram_olimex_a13_som.c
5021 --- u-boot-2014.04/board/sunxi/dram_olimex_a13_som.c 1970-01-01 01:00:00.000000000 +0100
5022 +++ u-boot-sunxi/board/sunxi/dram_olimex_a13_som.c 2014-09-06 16:58:36.161953116 +0200
5023 @@ -0,0 +1,32 @@
5024 +/* this file is generated, don't edit it yourself */
5025 +
5026 +#include <common.h>
5027 +#include <asm/arch/dram.h>
5028 +
5029 +static struct dram_para dram_para = {
5030 + .clock = 408,
5031 + .type = 3,
5032 + .rank_num = 1,
5033 + .density = 4096,
5034 + .io_width = 16,
5035 + .bus_width = 16,
5036 + .cas = 9,
5037 + .zq = 123,
5038 + .odt_en = 0,
5039 + .size = 512,
5040 + .tpr0 = 0x42d899b7,
5041 + .tpr1 = 0xa090,
5042 + .tpr2 = 0x22a00,
5043 + .tpr3 = 0,
5044 + .tpr4 = 0,
5045 + .tpr5 = 0,
5046 + .emr1 = 0,
5047 + .emr2 = 0x10,
5048 + .emr3 = 0,
5049 +
5050 +};
5051 +
5052 +unsigned long sunxi_dram_init(void)
5053 +{
5054 + return dramc_init(&dram_para);
5055 +}
5056 diff -ruN u-boot-2014.04/board/sunxi/dram_pov_protab2.c u-boot-sunxi/board/sunxi/dram_pov_protab2.c
5057 --- u-boot-2014.04/board/sunxi/dram_pov_protab2.c 1970-01-01 01:00:00.000000000 +0100
5058 +++ u-boot-sunxi/board/sunxi/dram_pov_protab2.c 2014-09-06 16:58:36.161953116 +0200
5059 @@ -0,0 +1,31 @@
5060 +/* this file is generated, don't edit it yourself */
5061 +
5062 +#include <common.h>
5063 +#include <asm/arch/dram.h>
5064 +
5065 +static struct dram_para dram_para = {
5066 + .clock = 432,
5067 + .type = 3,
5068 + .rank_num = 1,
5069 + .density = 4096,
5070 + .io_width = 16,
5071 + .bus_width = 32,
5072 + .cas = 6,
5073 + .zq = 123,
5074 + .odt_en = 0,
5075 + .size = 1024,
5076 + .tpr0 = 0x30926692,
5077 + .tpr1 = 0x1090,
5078 + .tpr2 = 0x1a0c8,
5079 + .tpr3 = 0,
5080 + .tpr4 = 0,
5081 + .tpr5 = 0,
5082 + .emr1 = 0,
5083 + .emr2 = 0,
5084 + .emr3 = 0,
5085 +};
5086 +
5087 +unsigned long sunxi_dram_init(void)
5088 +{
5089 + return dramc_init(&dram_para);
5090 +}
5091 diff -ruN u-boot-2014.04/board/sunxi/dram_pov_protab2_xxl.c u-boot-sunxi/board/sunxi/dram_pov_protab2_xxl.c
5092 --- u-boot-2014.04/board/sunxi/dram_pov_protab2_xxl.c 1970-01-01 01:00:00.000000000 +0100
5093 +++ u-boot-sunxi/board/sunxi/dram_pov_protab2_xxl.c 2014-09-06 16:58:36.161953116 +0200
5094 @@ -0,0 +1,31 @@
5095 +/* this file is generated, don't edit it yourself */
5096 +
5097 +#include <common.h>
5098 +#include <asm/arch/dram.h>
5099 +
5100 +static struct dram_para dram_para = {
5101 + .clock = 432,
5102 + .type = 3,
5103 + .rank_num = 1,
5104 + .density = 2048,
5105 + .io_width = 16,
5106 + .bus_width = 32,
5107 + .cas = 6,
5108 + .zq = 123,
5109 + .odt_en = 0,
5110 + .size = 512,
5111 + .tpr0 = 0x30926692,
5112 + .tpr1 = 0x1090,
5113 + .tpr2 = 0x1a0c8,
5114 + .tpr3 = 0,
5115 + .tpr4 = 0,
5116 + .tpr5 = 0,
5117 + .emr1 = 0,
5118 + .emr2 = 0,
5119 + .emr3 = 0,
5120 +};
5121 +
5122 +unsigned long sunxi_dram_init(void)
5123 +{
5124 + return dramc_init(&dram_para);
5125 +}
5126 diff -ruN u-boot-2014.04/board/sunxi/dram_pov_tab_p703.c u-boot-sunxi/board/sunxi/dram_pov_tab_p703.c
5127 --- u-boot-2014.04/board/sunxi/dram_pov_tab_p703.c 1970-01-01 01:00:00.000000000 +0100
5128 +++ u-boot-sunxi/board/sunxi/dram_pov_tab_p703.c 2014-09-06 16:58:36.161953116 +0200
5129 @@ -0,0 +1,31 @@
5130 +/* this file is generated, don't edit it yourself */
5131 +
5132 +#include <common.h>
5133 +#include <asm/arch/dram.h>
5134 +
5135 +static struct dram_para dram_para = {
5136 + .clock = 360,
5137 + .type = 3,
5138 + .rank_num = 1,
5139 + .density = 4096,
5140 + .io_width = 16,
5141 + .bus_width = 16,
5142 + .cas = 9,
5143 + .zq = 0x56b9697b,
5144 + .odt_en = 0,
5145 + .size = 512,
5146 + .tpr0 = 0x42d899b7,
5147 + .tpr1 = 0xa090,
5148 + .tpr2 = 0x22a00,
5149 + .tpr3 = 0,
5150 + .tpr4 = 0,
5151 + .tpr5 = 0,
5152 + .emr1 = 0x4,
5153 + .emr2 = 0x10,
5154 + .emr3 = 0,
5155 +};
5156 +
5157 +unsigned long sunxi_dram_init(void)
5158 +{
5159 + return dramc_init(&dram_para);
5160 +}
5161 diff -ruN u-boot-2014.04/board/sunxi/dram_r7dongle.c u-boot-sunxi/board/sunxi/dram_r7dongle.c
5162 --- u-boot-2014.04/board/sunxi/dram_r7dongle.c 1970-01-01 01:00:00.000000000 +0100
5163 +++ u-boot-sunxi/board/sunxi/dram_r7dongle.c 2014-09-06 16:58:36.161953116 +0200
5164 @@ -0,0 +1,31 @@
5165 +/* this file is generated, don't edit it yourself */
5166 +
5167 +#include <common.h>
5168 +#include <asm/arch/dram.h>
5169 +
5170 +static struct dram_para dram_para = {
5171 + .clock = 384,
5172 + .type = 3,
5173 + .rank_num = 1,
5174 + .density = 2048,
5175 + .io_width = 8,
5176 + .bus_width = 32,
5177 + .cas = 9,
5178 + .zq = 123,
5179 + .odt_en = 0,
5180 + .size = 1024,
5181 + .tpr0 = 0x42d899b7,
5182 + .tpr1 = 0xa090,
5183 + .tpr2 = 0x22a00,
5184 + .tpr3 = 0,
5185 + .tpr4 = 0,
5186 + .tpr5 = 0,
5187 + .emr1 = 0x04,
5188 + .emr2 = 0x10,
5189 + .emr3 = 0,
5190 +};
5191 +
5192 +unsigned long sunxi_dram_init(void)
5193 +{
5194 + return dramc_init(&dram_para);
5195 +}
5196 diff -ruN u-boot-2014.04/board/sunxi/dram_sanei_n90.c u-boot-sunxi/board/sunxi/dram_sanei_n90.c
5197 --- u-boot-2014.04/board/sunxi/dram_sanei_n90.c 1970-01-01 01:00:00.000000000 +0100
5198 +++ u-boot-sunxi/board/sunxi/dram_sanei_n90.c 2014-09-06 16:58:36.161953116 +0200
5199 @@ -0,0 +1,30 @@
5200 +/* this file is generated, don't edit it yourself */
5201 +
5202 +#include <common.h>
5203 +#include <asm/arch/dram.h>
5204 +
5205 +static struct dram_para dram_para = {
5206 + .clock = 456,
5207 + .type = 3,
5208 + .rank_num = 1,
5209 + .density = 4096,
5210 + .io_width = 8,
5211 + .bus_width = 32,
5212 + .cas = 6,
5213 + .zq = 123,
5214 + .odt_en = 1,
5215 + .size = 1024,
5216 + .tpr0 = 0x30926692,
5217 + .tpr1 = 0x1090,
5218 + .tpr2 = 0x1a0c8,
5219 + .tpr3 = 0,
5220 + .tpr4 = 0,
5221 + .tpr5 = 0,
5222 + .emr1 = 0x4,
5223 + .emr2 = 0,
5224 + .emr3 = 0,
5225 +};
5226 +unsigned long sunxi_dram_init(void)
5227 +{
5228 + return dramc_init(&dram_para);
5229 +}
5230 diff -ruN u-boot-2014.04/board/sunxi/dram_semitime_g2.c u-boot-sunxi/board/sunxi/dram_semitime_g2.c
5231 --- u-boot-2014.04/board/sunxi/dram_semitime_g2.c 1970-01-01 01:00:00.000000000 +0100
5232 +++ u-boot-sunxi/board/sunxi/dram_semitime_g2.c 2014-09-06 16:58:36.165953115 +0200
5233 @@ -0,0 +1,31 @@
5234 +/* this file is generated, don't edit it yourself */
5235 +
5236 +#include "common.h"
5237 +#include <asm/arch/dram.h>
5238 +
5239 +static struct dram_para dram_para = {
5240 + .clock = 432,
5241 + .type = 3,
5242 + .rank_num = 1,
5243 + .density = 4096,
5244 + .io_width = 16,
5245 + .bus_width = 32,
5246 + .cas = 9,
5247 + .zq = 0x7b,
5248 + .odt_en = 0,
5249 + .size = 1024, /* in MiB */
5250 + .tpr0 = 0x42d899b7,
5251 + .tpr1 = 0xa090,
5252 + .tpr2 = 0x22a00,
5253 + .tpr3 = 0x00,
5254 + .tpr4 = 0x00,
5255 + .tpr5 = 0x00,
5256 + .emr1 = 0x00,
5257 + .emr2 = 0x10,
5258 + .emr3 = 0x00,
5259 +};
5260 +
5261 +unsigned long sunxi_dram_init(void)
5262 +{
5263 + return dramc_init(&dram_para);
5264 +}
5265 diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_312_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_312_1024_iow8.c
5266 --- u-boot-2014.04/board/sunxi/dram_sun4i_312_1024_iow8.c 1970-01-01 01:00:00.000000000 +0100
5267 +++ u-boot-sunxi/board/sunxi/dram_sun4i_312_1024_iow8.c 2014-09-06 16:58:36.165953115 +0200
5268 @@ -0,0 +1,31 @@
5269 +/* this file is generated, don't edit it yourself */
5270 +
5271 +#include <common.h>
5272 +#include <asm/arch/dram.h>
5273 +
5274 +static struct dram_para dram_para = {
5275 + .clock = 312,
5276 + .type = 3,
5277 + .rank_num = 1,
5278 + .density = 2048,
5279 + .io_width = 8,
5280 + .bus_width = 32,
5281 + .cas = 6,
5282 + .zq = 123,
5283 + .odt_en = 0,
5284 + .size = 1024,
5285 + .tpr0 = 0x30926692,
5286 + .tpr1 = 0x1090,
5287 + .tpr2 = 0x1a0c8,
5288 + .tpr3 = 0,
5289 + .tpr4 = 0,
5290 + .tpr5 = 0,
5291 + .emr1 = 0,
5292 + .emr2 = 0,
5293 + .emr3 = 0,
5294 +};
5295 +
5296 +unsigned long sunxi_dram_init(void)
5297 +{
5298 + return dramc_init(&dram_para);
5299 +}
5300 diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_360_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow16.c
5301 --- u-boot-2014.04/board/sunxi/dram_sun4i_360_1024_iow16.c 1970-01-01 01:00:00.000000000 +0100
5302 +++ u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow16.c 2014-09-06 16:58:36.165953115 +0200
5303 @@ -0,0 +1,31 @@
5304 +/* this file is generated, don't edit it yourself */
5305 +
5306 +#include <common.h>
5307 +#include <asm/arch/dram.h>
5308 +
5309 +static struct dram_para dram_para = {
5310 + .clock = 360,
5311 + .type = 3,
5312 + .rank_num = 1,
5313 + .density = 4096,
5314 + .io_width = 16,
5315 + .bus_width = 32,
5316 + .cas = 6,
5317 + .zq = 123,
5318 + .odt_en = 0,
5319 + .size = 1024,
5320 + .tpr0 = 0x30926692,
5321 + .tpr1 = 0x1090,
5322 + .tpr2 = 0x1a0c8,
5323 + .tpr3 = 0,
5324 + .tpr4 = 0,
5325 + .tpr5 = 0,
5326 + .emr1 = 0,
5327 + .emr2 = 0,
5328 + .emr3 = 0,
5329 +};
5330 +
5331 +unsigned long sunxi_dram_init(void)
5332 +{
5333 + return dramc_init(&dram_para);
5334 +}
5335 diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_360_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow8.c
5336 --- u-boot-2014.04/board/sunxi/dram_sun4i_360_1024_iow8.c 1970-01-01 01:00:00.000000000 +0100
5337 +++ u-boot-sunxi/board/sunxi/dram_sun4i_360_1024_iow8.c 2014-09-06 16:58:36.165953115 +0200
5338 @@ -0,0 +1,31 @@
5339 +/* this file is generated, don't edit it yourself */
5340 +
5341 +#include <common.h>
5342 +#include <asm/arch/dram.h>
5343 +
5344 +static struct dram_para dram_para = {
5345 + .clock = 360,
5346 + .type = 3,
5347 + .rank_num = 1,
5348 + .density = 2048,
5349 + .io_width = 8,
5350 + .bus_width = 32,
5351 + .cas = 6,
5352 + .zq = 123,
5353 + .odt_en = 0,
5354 + .size = 1024,
5355 + .tpr0 = 0x30926692,
5356 + .tpr1 = 0x1090,
5357 + .tpr2 = 0x1a0c8,
5358 + .tpr3 = 0,
5359 + .tpr4 = 0,
5360 + .tpr5 = 0,
5361 + .emr1 = 0,
5362 + .emr2 = 0,
5363 + .emr3 = 0,
5364 +};
5365 +
5366 +unsigned long sunxi_dram_init(void)
5367 +{
5368 + return dramc_init(&dram_para);
5369 +}
5370 diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_360_512.c u-boot-sunxi/board/sunxi/dram_sun4i_360_512.c
5371 --- u-boot-2014.04/board/sunxi/dram_sun4i_360_512.c 1970-01-01 01:00:00.000000000 +0100
5372 +++ u-boot-sunxi/board/sunxi/dram_sun4i_360_512.c 2014-09-06 16:58:36.165953115 +0200
5373 @@ -0,0 +1,31 @@
5374 +/* this file is generated, don't edit it yourself */
5375 +
5376 +#include <common.h>
5377 +#include <asm/arch/dram.h>
5378 +
5379 +static struct dram_para dram_para = {
5380 + .clock = 360,
5381 + .type = 3,
5382 + .rank_num = 1,
5383 + .density = 2048,
5384 + .io_width = 16,
5385 + .bus_width = 32,
5386 + .cas = 6,
5387 + .zq = 123,
5388 + .odt_en = 0,
5389 + .size = 512,
5390 + .tpr0 = 0x30926692,
5391 + .tpr1 = 0x1090,
5392 + .tpr2 = 0x1a0c8,
5393 + .tpr3 = 0,
5394 + .tpr4 = 0,
5395 + .tpr5 = 0,
5396 + .emr1 = 0,
5397 + .emr2 = 0,
5398 + .emr3 = 0,
5399 +};
5400 +
5401 +unsigned long sunxi_dram_init(void)
5402 +{
5403 + return dramc_init(&dram_para);
5404 +}
5405 diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_384_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow16.c
5406 --- u-boot-2014.04/board/sunxi/dram_sun4i_384_1024_iow16.c 1970-01-01 01:00:00.000000000 +0100
5407 +++ u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow16.c 2014-09-06 16:58:36.165953115 +0200
5408 @@ -0,0 +1,31 @@
5409 +/* this file is generated, don't edit it yourself */
5410 +
5411 +#include <common.h>
5412 +#include <asm/arch/dram.h>
5413 +
5414 +static struct dram_para dram_para = {
5415 + .clock = 384,
5416 + .type = 3,
5417 + .rank_num = 1,
5418 + .density = 4096,
5419 + .io_width = 16,
5420 + .bus_width = 32,
5421 + .cas = 6,
5422 + .zq = 123,
5423 + .odt_en = 0,
5424 + .size = 1024,
5425 + .tpr0 = 0x30926692,
5426 + .tpr1 = 0x1090,
5427 + .tpr2 = 0x1a0c8,
5428 + .tpr3 = 0,
5429 + .tpr4 = 0,
5430 + .tpr5 = 0,
5431 + .emr1 = 0x4,
5432 + .emr2 = 0,
5433 + .emr3 = 0,
5434 +};
5435 +
5436 +unsigned long sunxi_dram_init(void)
5437 +{
5438 + return dramc_init(&dram_para);
5439 +}
5440 diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_384_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow8.c
5441 --- u-boot-2014.04/board/sunxi/dram_sun4i_384_1024_iow8.c 1970-01-01 01:00:00.000000000 +0100
5442 +++ u-boot-sunxi/board/sunxi/dram_sun4i_384_1024_iow8.c 2014-09-06 16:58:36.165953115 +0200
5443 @@ -0,0 +1,31 @@
5444 +/* this file is generated, don't edit it yourself */
5445 +
5446 +#include <common.h>
5447 +#include <asm/arch/dram.h>
5448 +
5449 +static struct dram_para dram_para = {
5450 + .clock = 384,
5451 + .type = 3,
5452 + .rank_num = 1,
5453 + .density = 2048,
5454 + .io_width = 8,
5455 + .bus_width = 32,
5456 + .cas = 6,
5457 + .zq = 123,
5458 + .odt_en = 0,
5459 + .size = 1024,
5460 + .tpr0 = 0x30926692,
5461 + .tpr1 = 0x1090,
5462 + .tpr2 = 0x1a0c8,
5463 + .tpr3 = 0,
5464 + .tpr4 = 0,
5465 + .tpr5 = 0,
5466 + .emr1 = 0x4,
5467 + .emr2 = 0,
5468 + .emr3 = 0,
5469 +};
5470 +
5471 +unsigned long sunxi_dram_init(void)
5472 +{
5473 + return dramc_init(&dram_para);
5474 +}
5475 diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_408_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow16.c
5476 --- u-boot-2014.04/board/sunxi/dram_sun4i_408_1024_iow16.c 1970-01-01 01:00:00.000000000 +0100
5477 +++ u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow16.c 2014-09-06 16:58:36.165953115 +0200
5478 @@ -0,0 +1,31 @@
5479 +/* this file is generated, don't edit it yourself */
5480 +
5481 +#include <common.h>
5482 +#include <asm/arch/dram.h>
5483 +
5484 +static struct dram_para dram_para = {
5485 + .clock = 408,
5486 + .type = 3,
5487 + .rank_num = 1,
5488 + .density = 4096,
5489 + .io_width = 16,
5490 + .bus_width = 32,
5491 + .cas = 6,
5492 + .zq = 123,
5493 + .odt_en = 0,
5494 + .size = 1024,
5495 + .tpr0 = 0x30926692,
5496 + .tpr1 = 0x1090,
5497 + .tpr2 = 0x1a0c8,
5498 + .tpr3 = 0,
5499 + .tpr4 = 0,
5500 + .tpr5 = 0,
5501 + .emr1 = 0x4,
5502 + .emr2 = 0,
5503 + .emr3 = 0,
5504 +};
5505 +
5506 +unsigned long sunxi_dram_init(void)
5507 +{
5508 + return dramc_init(&dram_para);
5509 +}
5510 diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_408_1024_iow8.c u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow8.c
5511 --- u-boot-2014.04/board/sunxi/dram_sun4i_408_1024_iow8.c 1970-01-01 01:00:00.000000000 +0100
5512 +++ u-boot-sunxi/board/sunxi/dram_sun4i_408_1024_iow8.c 2014-09-06 16:58:36.165953115 +0200
5513 @@ -0,0 +1,31 @@
5514 +/* this file is generated, don't edit it yourself */
5515 +
5516 +#include <common.h>
5517 +#include <asm/arch/dram.h>
5518 +
5519 +static struct dram_para dram_para = {
5520 + .clock = 408,
5521 + .type = 3,
5522 + .rank_num = 1,
5523 + .density = 2048,
5524 + .io_width = 8,
5525 + .bus_width = 32,
5526 + .cas = 6,
5527 + .zq = 123,
5528 + .odt_en = 0,
5529 + .size = 1024,
5530 + .tpr0 = 0x30926692,
5531 + .tpr1 = 0x1090,
5532 + .tpr2 = 0x1a0c8,
5533 + .tpr3 = 0,
5534 + .tpr4 = 0,
5535 + .tpr5 = 0,
5536 + .emr1 = 0x4,
5537 + .emr2 = 0,
5538 + .emr3 = 0,
5539 +};
5540 +
5541 +unsigned long sunxi_dram_init(void)
5542 +{
5543 + return dramc_init(&dram_para);
5544 +}
5545 diff -ruN u-boot-2014.04/board/sunxi/dram_sun4i_408_512.c u-boot-sunxi/board/sunxi/dram_sun4i_408_512.c
5546 --- u-boot-2014.04/board/sunxi/dram_sun4i_408_512.c 1970-01-01 01:00:00.000000000 +0100
5547 +++ u-boot-sunxi/board/sunxi/dram_sun4i_408_512.c 2014-09-06 16:58:36.165953115 +0200
5548 @@ -0,0 +1,31 @@
5549 +/* this file is generated, don't edit it yourself */
5550 +
5551 +#include <common.h>
5552 +#include <asm/arch/dram.h>
5553 +
5554 +static struct dram_para dram_para = {
5555 + .clock = 408,
5556 + .type = 3,
5557 + .rank_num = 1,
5558 + .density = 2048,
5559 + .io_width = 16,
5560 + .bus_width = 32,
5561 + .cas = 6,
5562 + .zq = 0x7b,
5563 + .odt_en = 0,
5564 + .size = 512,
5565 + .tpr0 = 0x30926692,
5566 + .tpr1 = 0x1090,
5567 + .tpr2 = 0x1a0c8,
5568 + .tpr3 = 0,
5569 + .tpr4 = 0,
5570 + .tpr5 = 0,
5571 + .emr1 = 0x4,
5572 + .emr2 = 0,
5573 + .emr3 = 0,
5574 +};
5575 +
5576 +unsigned long sunxi_dram_init(void)
5577 +{
5578 + return dramc_init(&dram_para);
5579 +}
5580 diff -ruN u-boot-2014.04/board/sunxi/dram_sun5i_408_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun5i_408_1024_iow16.c
5581 --- u-boot-2014.04/board/sunxi/dram_sun5i_408_1024_iow16.c 1970-01-01 01:00:00.000000000 +0100
5582 +++ u-boot-sunxi/board/sunxi/dram_sun5i_408_1024_iow16.c 2014-09-06 16:58:36.165953115 +0200
5583 @@ -0,0 +1,31 @@
5584 +/* this file is generated, don't edit it yourself */
5585 +
5586 +#include <common.h>
5587 +#include <asm/arch/dram.h>
5588 +
5589 +static struct dram_para dram_para = {
5590 + .clock = 408,
5591 + .type = 3,
5592 + .rank_num = 1,
5593 + .density = 4096,
5594 + .io_width = 16,
5595 + .bus_width = 32,
5596 + .cas = 9,
5597 + .zq = 0x7b,
5598 + .odt_en = 0,
5599 + .size = 1024,
5600 + .tpr0 = 0x42d899b7,
5601 + .tpr1 = 0xa090,
5602 + .tpr2 = 0x22a00,
5603 + .tpr3 = 0,
5604 + .tpr4 = 0,
5605 + .tpr5 = 0,
5606 + .emr1 = 0x4,
5607 + .emr2 = 0x10,
5608 + .emr3 = 0,
5609 +};
5610 +
5611 +unsigned long sunxi_dram_init(void)
5612 +{
5613 + return dramc_init(&dram_para);
5614 +}
5615 diff -ruN u-boot-2014.04/board/sunxi/dram_sun5i_408_512_busw16_iow8.c u-boot-sunxi/board/sunxi/dram_sun5i_408_512_busw16_iow8.c
5616 --- u-boot-2014.04/board/sunxi/dram_sun5i_408_512_busw16_iow8.c 1970-01-01 01:00:00.000000000 +0100
5617 +++ u-boot-sunxi/board/sunxi/dram_sun5i_408_512_busw16_iow8.c 2014-09-06 16:58:36.165953115 +0200
5618 @@ -0,0 +1,31 @@
5619 +/* this file is generated, don't edit it yourself */
5620 +
5621 +#include <common.h>
5622 +#include <asm/arch/dram.h>
5623 +
5624 +static struct dram_para dram_para = {
5625 + .clock = 408,
5626 + .type = 3,
5627 + .rank_num = 1,
5628 + .density = 2048,
5629 + .io_width = 8,
5630 + .bus_width = 16,
5631 + .cas = 9,
5632 + .zq = 123,
5633 + .odt_en = 1,
5634 + .size = 512,
5635 + .tpr0 = 0x42d899b7,
5636 + .tpr1 = 0xa090,
5637 + .tpr2 = 0x22a00,
5638 + .tpr3 = 0,
5639 + .tpr4 = 0,
5640 + .tpr5 = 0,
5641 + .emr1 = 0x4,
5642 + .emr2 = 0x10,
5643 + .emr3 = 0,
5644 +};
5645 +
5646 +unsigned long sunxi_dram_init(void)
5647 +{
5648 + return dramc_init(&dram_para);
5649 +}
5650 diff -ruN u-boot-2014.04/board/sunxi/dram_sun5i_432_512_busw16_iow16.c u-boot-sunxi/board/sunxi/dram_sun5i_432_512_busw16_iow16.c
5651 --- u-boot-2014.04/board/sunxi/dram_sun5i_432_512_busw16_iow16.c 1970-01-01 01:00:00.000000000 +0100
5652 +++ u-boot-sunxi/board/sunxi/dram_sun5i_432_512_busw16_iow16.c 2014-09-06 16:58:36.165953115 +0200
5653 @@ -0,0 +1,31 @@
5654 +/* this file is generated, don't edit it yourself */
5655 +
5656 +#include <common.h>
5657 +#include <asm/arch/dram.h>
5658 +
5659 +static struct dram_para dram_para = {
5660 + .clock = 432,
5661 + .type = 3,
5662 + .rank_num = 1,
5663 + .density = 4096,
5664 + .io_width = 16,
5665 + .bus_width = 16,
5666 + .cas = 9,
5667 + .zq = 123,
5668 + .odt_en = 0,
5669 + .size = 512,
5670 + .tpr0 = 0x42d899b7,
5671 + .tpr1 = 0xa090,
5672 + .tpr2 = 0x22a00,
5673 + .tpr3 = 0,
5674 + .tpr4 = 0,
5675 + .tpr5 = 0,
5676 + .emr1 = 0x4,
5677 + .emr2 = 0x10,
5678 + .emr3 = 0,
5679 +};
5680 +
5681 +unsigned long sunxi_dram_init(void)
5682 +{
5683 + return dramc_init(&dram_para);
5684 +}
5685 diff -ruN u-boot-2014.04/board/sunxi/dram_sun7i_360_512_busw16_iow16.c u-boot-sunxi/board/sunxi/dram_sun7i_360_512_busw16_iow16.c
5686 --- u-boot-2014.04/board/sunxi/dram_sun7i_360_512_busw16_iow16.c 1970-01-01 01:00:00.000000000 +0100
5687 +++ u-boot-sunxi/board/sunxi/dram_sun7i_360_512_busw16_iow16.c 2014-09-06 16:58:36.165953115 +0200
5688 @@ -0,0 +1,31 @@
5689 +/* this file is generated, don't edit it yourself */
5690 +
5691 +#include "common.h"
5692 +#include <asm/arch/dram.h>
5693 +
5694 +static struct dram_para dram_para = {
5695 + .clock = 360,
5696 + .type = 3,
5697 + .rank_num = 1,
5698 + .density = 4096,
5699 + .io_width = 16,
5700 + .bus_width = 16,
5701 + .cas = 9,
5702 + .zq = 0x7f,
5703 + .odt_en = 0,
5704 + .size = 512,
5705 + .tpr0 = 0x42d899b7,
5706 + .tpr1 = 0xa090,
5707 + .tpr2 = 0x22a00,
5708 + .tpr3 = 0,
5709 + .tpr4 = 0,
5710 + .tpr5 = 0,
5711 + .emr1 = 0x4,
5712 + .emr2 = 0x10,
5713 + .emr3 = 0,
5714 +};
5715 +
5716 +unsigned long sunxi_dram_init(void)
5717 +{
5718 + return dramc_init(&dram_para);
5719 +}
5720 diff -ruN u-boot-2014.04/board/sunxi/dram_sun7i_384_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun7i_384_1024_iow16.c
5721 --- u-boot-2014.04/board/sunxi/dram_sun7i_384_1024_iow16.c 1970-01-01 01:00:00.000000000 +0100
5722 +++ u-boot-sunxi/board/sunxi/dram_sun7i_384_1024_iow16.c 2014-09-06 16:58:36.165953115 +0200
5723 @@ -0,0 +1,31 @@
5724 +/* this file is generated, don't edit it yourself */
5725 +
5726 +#include "common.h"
5727 +#include <asm/arch/dram.h>
5728 +
5729 +static struct dram_para dram_para = {
5730 + .clock = 384,
5731 + .type = 3,
5732 + .rank_num = 1,
5733 + .density = 4096,
5734 + .io_width = 16,
5735 + .bus_width = 32,
5736 + .cas = 9,
5737 + .zq = 0x7f,
5738 + .odt_en = 0,
5739 + .size = 1024,
5740 + .tpr0 = 0x42d899b7,
5741 + .tpr1 = 0xa090,
5742 + .tpr2 = 0x22a00,
5743 + .tpr3 = 0,
5744 + .tpr4 = 0,
5745 + .tpr5 = 0,
5746 + .emr1 = 0x4,
5747 + .emr2 = 0x10,
5748 + .emr3 = 0,
5749 +};
5750 +
5751 +unsigned long sunxi_dram_init(void)
5752 +{
5753 + return dramc_init(&dram_para);
5754 +}
5755 diff -ruN u-boot-2014.04/board/sunxi/dram_sun7i_384_512_busw16_iow16.c u-boot-sunxi/board/sunxi/dram_sun7i_384_512_busw16_iow16.c
5756 --- u-boot-2014.04/board/sunxi/dram_sun7i_384_512_busw16_iow16.c 1970-01-01 01:00:00.000000000 +0100
5757 +++ u-boot-sunxi/board/sunxi/dram_sun7i_384_512_busw16_iow16.c 2014-09-06 16:58:36.165953115 +0200
5758 @@ -0,0 +1,31 @@
5759 +/* this file is generated, don't edit it yourself */
5760 +
5761 +#include "common.h"
5762 +#include <asm/arch/dram.h>
5763 +
5764 +static struct dram_para dram_para = {
5765 + .clock = 384,
5766 + .type = 3,
5767 + .rank_num = 1,
5768 + .density = 4096,
5769 + .io_width = 16,
5770 + .bus_width = 16,
5771 + .cas = 9,
5772 + .zq = 0x7f,
5773 + .odt_en = 0,
5774 + .size = 512,
5775 + .tpr0 = 0x42d899b7,
5776 + .tpr1 = 0xa090,
5777 + .tpr2 = 0x22a00,
5778 + .tpr3 = 0,
5779 + .tpr4 = 0,
5780 + .tpr5 = 0,
5781 + .emr1 = 0x4,
5782 + .emr2 = 0x10,
5783 + .emr3 = 0,
5784 +};
5785 +
5786 +unsigned long sunxi_dram_init(void)
5787 +{
5788 + return dramc_init(&dram_para);
5789 +}
5790 diff -ruN u-boot-2014.04/board/sunxi/dram_sun7i_432_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun7i_432_1024_iow16.c
5791 --- u-boot-2014.04/board/sunxi/dram_sun7i_432_1024_iow16.c 1970-01-01 01:00:00.000000000 +0100
5792 +++ u-boot-sunxi/board/sunxi/dram_sun7i_432_1024_iow16.c 2014-09-06 16:58:36.165953115 +0200
5793 @@ -0,0 +1,31 @@
5794 +/* this file is generated, don't edit it yourself */
5795 +
5796 +#include "common.h"
5797 +#include <asm/arch/dram.h>
5798 +
5799 +static struct dram_para dram_para = {
5800 + .clock = 432,
5801 + .type = 3,
5802 + .rank_num = 1,
5803 + .density = 4096,
5804 + .io_width = 16,
5805 + .bus_width = 32,
5806 + .cas = 9,
5807 + .zq = 0x7f,
5808 + .odt_en = 0,
5809 + .size = 1024,
5810 + .tpr0 = 0x42d899b7,
5811 + .tpr1 = 0xa090,
5812 + .tpr2 = 0x22a00,
5813 + .tpr3 = 0,
5814 + .tpr4 = 1,
5815 + .tpr5 = 0,
5816 + .emr1 = 0x4,
5817 + .emr2 = 0x10,
5818 + .emr3 = 0,
5819 +};
5820 +
5821 +unsigned long sunxi_dram_init(void)
5822 +{
5823 + return dramc_init(&dram_para);
5824 +}
5825 diff -ruN u-boot-2014.04/board/sunxi/dram_sun7i_460_1024_iow16.c u-boot-sunxi/board/sunxi/dram_sun7i_460_1024_iow16.c
5826 --- u-boot-2014.04/board/sunxi/dram_sun7i_460_1024_iow16.c 1970-01-01 01:00:00.000000000 +0100
5827 +++ u-boot-sunxi/board/sunxi/dram_sun7i_460_1024_iow16.c 2014-09-06 16:58:36.165953115 +0200
5828 @@ -0,0 +1,31 @@
5829 +/* this file is generated, don't edit it yourself */
5830 +
5831 +#include <common.h>
5832 +#include <asm/arch/dram.h>
5833 +
5834 +static struct dram_para dram_para = {
5835 + .clock = 480,
5836 + .type = 3,
5837 + .rank_num = 1,
5838 + .density = 4096,
5839 + .io_width = 16,
5840 + .bus_width = 32,
5841 + .cas = 9,
5842 + .zq = 0x7f,
5843 + .odt_en = 0,
5844 + .size = 1024,
5845 + .tpr0 = 0x42d899b7,
5846 + .tpr1 = 0xa090,
5847 + .tpr2 = 0x22a00,
5848 + .tpr3 = 0x0,
5849 + .tpr4 = 0x1,
5850 + .tpr5 = 0x0,
5851 + .emr1 = 0x4,
5852 + .emr2 = 0x10,
5853 + .emr3 = 0x0,
5854 +};
5855 +
5856 +unsigned long sunxi_dram_init(void)
5857 +{
5858 + return dramc_init(&dram_para);
5859 +}
5860 diff -ruN u-boot-2014.04/board/sunxi/dram_wexler_tab_7200.c u-boot-sunxi/board/sunxi/dram_wexler_tab_7200.c
5861 --- u-boot-2014.04/board/sunxi/dram_wexler_tab_7200.c 1970-01-01 01:00:00.000000000 +0100
5862 +++ u-boot-sunxi/board/sunxi/dram_wexler_tab_7200.c 2014-09-06 16:58:36.165953115 +0200
5863 @@ -0,0 +1,31 @@
5864 +/* this file is generated, don't edit it yourself */
5865 +
5866 +#include "common.h"
5867 +#include <asm/arch/dram.h>
5868 +
5869 +static struct dram_para dram_para = {
5870 + .clock = 384,
5871 + .type = 3,
5872 + .rank_num = 1,
5873 + .density = 4096,
5874 + .io_width = 16,
5875 + .bus_width = 32,
5876 + .cas = 9,
5877 + .zq = 0x7f,
5878 + .odt_en = 1,
5879 + .size = 1024,
5880 + .tpr0 = 0x42d899b7,
5881 + .tpr1 = 0xa090,
5882 + .tpr2 = 0x22a00,
5883 + .tpr3 = 0,
5884 + .tpr4 = 1,
5885 + .tpr5 = 0,
5886 + .emr1 = 0x4,
5887 + .emr2 = 0x10,
5888 + .emr3 = 0,
5889 +};
5890 +
5891 +unsigned long sunxi_dram_init(void)
5892 +{
5893 + return dramc_init(&dram_para);
5894 +}
5895 diff -ruN u-boot-2014.04/board/sunxi/dram_wobo_i5.c u-boot-sunxi/board/sunxi/dram_wobo_i5.c
5896 --- u-boot-2014.04/board/sunxi/dram_wobo_i5.c 1970-01-01 01:00:00.000000000 +0100
5897 +++ u-boot-sunxi/board/sunxi/dram_wobo_i5.c 2014-09-06 16:58:36.165953115 +0200
5898 @@ -0,0 +1,31 @@
5899 +/* this file is generated, don't edit it yourself */
5900 +
5901 +#include <common.h>
5902 +#include <asm/arch/dram.h>
5903 +
5904 +static struct dram_para dram_para = {
5905 + .clock = 432,
5906 + .type = 3,
5907 + .rank_num = 1,
5908 + .density = 2048,
5909 + .io_width = 8,
5910 + .bus_width = 32,
5911 + .cas = 9,
5912 + .zq = 123,
5913 + .odt_en = 0,
5914 + .size = 1024,
5915 + .tpr0 = 0x42d899b7,
5916 + .tpr1 = 0xa090,
5917 + .tpr2 = 0x22a00,
5918 + .tpr3 = 0,
5919 + .tpr4 = 0,
5920 + .tpr5 = 0,
5921 + .emr1 = 0x04,
5922 + .emr2 = 0x10,
5923 + .emr3 = 0,
5924 +};
5925 +
5926 +unsigned long sunxi_dram_init(void)
5927 +{
5928 + return dramc_init(&dram_para);
5929 +}
5930 diff -ruN u-boot-2014.04/board/sunxi/dram_xzpad700.c u-boot-sunxi/board/sunxi/dram_xzpad700.c
5931 --- u-boot-2014.04/board/sunxi/dram_xzpad700.c 1970-01-01 01:00:00.000000000 +0100
5932 +++ u-boot-sunxi/board/sunxi/dram_xzpad700.c 2014-09-06 16:58:36.165953115 +0200
5933 @@ -0,0 +1,31 @@
5934 +/* this file is generated, don't edit it yourself */
5935 +
5936 +#include <common.h>
5937 +#include <asm/arch/dram.h>
5938 +
5939 +static struct dram_para dram_para = {
5940 + .clock = 408,
5941 + .type = 3,
5942 + .rank_num = 1,
5943 + .density = 4096,
5944 + .io_width = 16,
5945 + .bus_width = 16,
5946 + .cas = 9,
5947 + .zq = 0x56b9487b,
5948 + .odt_en = 0,
5949 + .size = 512,
5950 + .tpr0 = 0x42d899b7,
5951 + .tpr1 = 0xa090,
5952 + .tpr2 = 0x22a00,
5953 + .tpr3 = 0,
5954 + .tpr4 = 0,
5955 + .tpr5 = 0,
5956 + .emr1 = 0x4,
5957 + .emr2 = 0x10,
5958 + .emr3 = 0,
5959 +};
5960 +
5961 +unsigned long sunxi_dram_init(void)
5962 +{
5963 + return dramc_init(&dram_para);
5964 +}
5965 diff -ruN u-boot-2014.04/board/sunxi/dram_zatab.c u-boot-sunxi/board/sunxi/dram_zatab.c
5966 --- u-boot-2014.04/board/sunxi/dram_zatab.c 1970-01-01 01:00:00.000000000 +0100
5967 +++ u-boot-sunxi/board/sunxi/dram_zatab.c 2014-09-06 16:58:36.165953115 +0200
5968 @@ -0,0 +1,31 @@
5969 +/* this file is generated, don't edit it yourself */
5970 +
5971 +#include <common.h>
5972 +#include <asm/arch/dram.h>
5973 +
5974 +static struct dram_para dram_para = {
5975 + .clock = 432,
5976 + .type = 3,
5977 + .rank_num = 1,
5978 + .density = 2048,
5979 + .io_width = 8,
5980 + .bus_width = 32,
5981 + .cas = 6,
5982 + .zq = 123,
5983 + .odt_en = 0,
5984 + .size = 1024,
5985 + .tpr0 = 0x30926692,
5986 + .tpr1 = 0x1090,
5987 + .tpr2 = 0x1a0c8,
5988 + .tpr3 = 0,
5989 + .tpr4 = 0,
5990 + .tpr5 = 0,
5991 + .emr1 = 0x4,
5992 + .emr2 = 0,
5993 + .emr3 = 0,
5994 +};
5995 +
5996 +unsigned long sunxi_dram_init(void)
5997 +{
5998 + return dramc_init(&dram_para);
5999 +}
6000 diff -ruN u-boot-2014.04/board/sunxi/gmac.c u-boot-sunxi/board/sunxi/gmac.c
6001 --- u-boot-2014.04/board/sunxi/gmac.c 1970-01-01 01:00:00.000000000 +0100
6002 +++ u-boot-sunxi/board/sunxi/gmac.c 2014-09-06 16:58:36.165953115 +0200
6003 @@ -0,0 +1,43 @@
6004 +#include <common.h>
6005 +#include <netdev.h>
6006 +#include <miiphy.h>
6007 +#include <asm/gpio.h>
6008 +#include <asm/io.h>
6009 +#include <asm/arch/clock.h>
6010 +#include <asm/arch/gpio.h>
6011 +
6012 +int sunxi_gmac_initialize(bd_t *bis)
6013 +{
6014 + int pin;
6015 + struct sunxi_ccm_reg *const ccm =
6016 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
6017 +
6018 + /* Set up clock gating */
6019 + setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
6020 +
6021 + /* Set MII clock */
6022 +#ifdef CONFIG_RGMII
6023 + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
6024 + CCM_GMAC_CTRL_GPIT_RGMII);
6025 +#else
6026 + setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
6027 + CCM_GMAC_CTRL_GPIT_MII);
6028 +#endif
6029 +
6030 + /* Configure pin mux settings for GMAC */
6031 + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
6032 +#ifdef CONFIG_RGMII
6033 + /* skip unused pins in RGMII mode */
6034 + if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))
6035 + continue;
6036 +#endif
6037 + sunxi_gpio_set_cfgpin(pin, SUN7I_GPA0_GMAC);
6038 + sunxi_gpio_set_drv(pin, 3);
6039 + }
6040 +
6041 +#ifdef CONFIG_RGMII
6042 + return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_RGMII);
6043 +#else
6044 + return designware_initialize(SUNXI_GMAC_BASE, PHY_INTERFACE_MODE_MII);
6045 +#endif
6046 +}
6047 diff -ruN u-boot-2014.04/board/sunxi/Makefile u-boot-sunxi/board/sunxi/Makefile
6048 --- u-boot-2014.04/board/sunxi/Makefile 1970-01-01 01:00:00.000000000 +0100
6049 +++ u-boot-sunxi/board/sunxi/Makefile 2014-09-06 16:58:36.161953116 +0200
6050 @@ -0,0 +1,95 @@
6051 +#
6052 +# (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
6053 +#
6054 +# Based on some other board Makefile
6055 +#
6056 +# (C) Copyright 2000-2003
6057 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6058 +#
6059 +# SPDX-License-Identifier: GPL-2.0+
6060 +#
6061 +obj-y += board.o
6062 +obj-$(CONFIG_SUNXI_GMAC) += gmac.o
6063 +obj-$(CONFIG_A10_MID_1GB) += dram_sun4i_360_1024_iow16.o
6064 +obj-$(CONFIG_A10_OLINUXINO_L) += dram_a10_olinuxino_l.o
6065 +obj-$(CONFIG_A10S_OLINUXINO_M) += dram_sun5i_432_512_busw16_iow16.o
6066 +obj-$(CONFIG_A13_OLINUXINO) += dram_a13_olinuxino.o
6067 +obj-$(CONFIG_A13_OLINUXINOM) += dram_a13_oli_micro.o
6068 +obj-$(CONFIG_A13_MID) += dram_sun5i_408_512_busw16_iow8.o
6069 +obj-$(CONFIG_A20_OLINUXINO_L) += dram_a20_olinuxino_l.o
6070 +obj-$(CONFIG_A20_OLINUXINO_L2) += dram_a20_olinuxino_l2.o
6071 +obj-$(CONFIG_A20_OLINUXINO_M) += dram_sun7i_384_1024_iow16.o
6072 +obj-$(CONFIG_A20_SOM) += dram_sun7i_384_1024_iow16.o
6073 +obj-$(CONFIG_AINOL_AW1) += dram_ainol_aw1.o
6074 +obj-$(CONFIG_AMPE_A76) += dram_sun5i_432_512_busw16_iow16.o
6075 +obj-$(CONFIG_AUXTEK_T003) += dram_auxtek_t003.o
6076 +obj-$(CONFIG_AUXTEK_T004) += dram_sun5i_432_512_busw16_iow16.o
6077 +obj-$(CONFIG_BA10_TV_BOX) += dram_sun4i_384_1024_iow8.o
6078 +obj-$(CONFIG_COBY_MID7042) += dram_sun4i_408_1024_iow16.o
6079 +obj-$(CONFIG_COBY_MID8042) += dram_sun4i_360_1024_iow16.o
6080 +obj-$(CONFIG_COBY_MID9742) += dram_sun4i_408_1024_iow16.o
6081 +obj-$(CONFIG_MARSBOARD_A10) += dram_sun4i_360_1024_iow16.o
6082 +obj-$(CONFIG_MARSBOARD_A20) += dram_sun4i_360_1024_iow16.o
6083 +obj-$(CONFIG_CUBIEBOARD) += dram_cubieboard.o
6084 +obj-$(CONFIG_CUBIEBOARD2) += dram_sun7i_460_1024_iow16.o
6085 +obj-$(CONFIG_BANANAPI) += dram_sun7i_432_1024_iow16.o
6086 +obj-$(CONFIG_CUBIETRUCK) += dram_cubietruck.o
6087 +obj-$(CONFIG_DNS_M82) += dram_sun4i_360_1024_iow16.o
6088 +obj-$(CONFIG_EOMA68_A10) += dram_sun4i_360_1024_iow8.o
6089 +obj-$(CONFIG_EOMA68_A20) += dram_sun7i_384_1024_iow16.o
6090 +obj-$(CONFIG_EU3000) += dram_eu3000.o
6091 +obj-$(CONFIG_FORFUN_Q88DB) += dram_forfun_q88db.o
6092 +obj-$(CONFIG_GOOSEBERRY_A721) += dram_gooseberry_a721.o
6093 +obj-$(CONFIG_H6) += dram_h6.o
6094 +obj-$(CONFIG_HACKBERRY) += dram_hackberry.o
6095 +obj-$(CONFIG_HBD_MID_S906) += dram_sun7i_432_1024_iow16.o
6096 +obj-$(CONFIG_HCORE_HC860) += dram_sun4i_384_1024_iow16.o
6097 +obj-$(CONFIG_HYUNDAI_A7) += dram_sun4i_360_512.o
6098 +obj-$(CONFIG_A7HD) += dram_sun4i_360_1024_iow8.o
6099 +obj-$(CONFIG_I12_TVBOX) += dram_sun7i_384_1024_iow16.o
6100 +obj-$(CONFIG_ICOU_FATTY_I) += dram_icou_fatty_i.o
6101 +obj-$(CONFIG_INTERRA3) += dram_mk802ii_a20.o
6102 +obj-$(CONFIG_INET_86VZ) += dram_sun5i_432_512_busw16_iow16.o
6103 +obj-$(CONFIG_INET97F_II) += dram_sun4i_408_512.o
6104 +obj-$(CONFIG_INET_K70HC) += dram_inet_k70hc.o
6105 +obj-$(CONFIG_ITEADA10) += dram_cubieboard.o
6106 +obj-$(CONFIG_ITEADA20) += dram_sun7i_460_1024_iow16.o
6107 +obj-$(CONFIG_JESURUN_Q5) += dram_sun4i_312_1024_iow8.o
6108 +obj-$(CONFIG_K1001L1C) += dram_sun7i_384_1024_iow16.o
6109 +obj-$(CONFIG_KURIO_7S) += dram_sun7i_432_1024_iow16.o
6110 +obj-$(CONFIG_LANGCENT_H6S) += dram_sun7i_360_512_busw16_iow16.o
6111 +obj-$(CONFIG_LINKSPRITE_PCDUINO3) += dram_linksprite_pcduino3.o
6112 +obj-$(CONFIG_MEFAFEIS_A08) += dram_megafeis_a08.o
6113 +obj-$(CONFIG_MELE_A1000) += dram_sun4i_360_512.o
6114 +obj-$(CONFIG_MELE_A1000G) += dram_sun4i_360_1024_iow8.o
6115 +obj-$(CONFIG_MELE_A3700) += dram_sun4i_360_1024_iow8.o
6116 +obj-$(CONFIG_MERRII_HUMMINGBIRD_A20) += dram_sun7i_460_1024_iow16.o
6117 +obj-$(CONFIG_MINI_X) += dram_sun4i_360_512.o
6118 +obj-$(CONFIG_MINI_X_1GB) += dram_sun4i_360_1024_iow16.o
6119 +obj-$(CONFIG_MINI_X_A10S) += dram_mini_x_a10s.o
6120 +obj-$(CONFIG_MK802) += dram_sun4i_360_512.o
6121 +obj-$(CONFIG_MK802_1GB) += dram_sun4i_360_1024_iow16.o
6122 +obj-$(CONFIG_MK802_A10S) += dram_mk802_a10s.o
6123 +obj-$(CONFIG_MK802II) += dram_sun4i_408_1024_iow8.o
6124 +obj-$(CONFIG_MK802II_A20) += dram_mk802ii_a20.o
6125 +obj-$(CONFIG_MK808C_A20) += dram_sun7i_384_1024_iow16.o
6126 +obj-$(CONFIG_OLIMEX_A13_SOM) += dram_olimex_a13_som.o
6127 +obj-$(CONFIG_PCDUINO) += dram_sun4i_408_1024_iow8.o
6128 +obj-$(CONFIG_PENGPOD700) += dram_sun4i_384_1024_iow8.o
6129 +obj-$(CONFIG_PENGPOD1000) += dram_sun4i_408_1024_iow16.o
6130 +obj-$(CONFIG_PINERIVER-H25) += dram_sun5i_408_1024_iow16.o
6131 +obj-$(CONFIG_POV_TAB_P703) += dram_pov_tab_p703.o
6132 +obj-$(CONFIG_POV_PROTAB2) += dram_pov_protab2.o
6133 +obj-$(CONFIG_POV_PROTAB2_XXL) += dram_pov_protab2_xxl.o
6134 +obj-$(CONFIG_QT840A) += dram_sun7i_384_512_busw16_iow16.o
6135 +obj-$(CONFIG_R7DONGLE) += dram_r7dongle.o
6136 +obj-$(CONFIG_SANEI_N90) += dram_sanei_n90.o
6137 +obj-$(CONFIG_SEMITIME_G2) += dram_semitime_g2.o
6138 +obj-$(CONFIG_TZX_Q8_713B6) += dram_sun5i_408_512_busw16_iow8.o
6139 +obj-$(CONFIG_TZX_Q8_713B7) += dram_sun5i_408_512_busw16_iow8.o
6140 +obj-$(CONFIG_UHOST_U1A) += dram_sun4i_360_1024_iow8.o
6141 +obj-$(CONFIG_WEXLER_TAB_7200) += dram_wexler_tab_7200.o
6142 +obj-$(CONFIG_WOBO_I5) += dram_wobo_i5.o
6143 +obj-$(CONFIG_XZPAD700) += dram_xzpad700.o
6144 +obj-$(CONFIG_ZATAB) += dram_zatab.o
6145 +obj-$(CONFIG_MERRII_M2) += dram_merrii_m2.o
6146 diff -ruN u-boot-2014.04/boards.cfg u-boot-sunxi/boards.cfg
6147 --- u-boot-2014.04/boards.cfg 2014-04-14 21:19:24.000000000 +0200
6148 +++ u-boot-sunxi/boards.cfg 2014-09-06 16:58:36.185953115 +0200
6149 @@ -371,6 +371,111 @@
6150 Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega@samsung.com>
6151 Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
6152 Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
6153 +Active arm armv7 sunxi - sunxi A10_MID_1GB sun4i:A10_MID_1GB,SPL -
6154 +Active arm armv7 sunxi - sunxi A10-OLinuXino-Lime sun4i:A10_OLINUXINO_L,STATUSLED=226,SPL,SUNXI_EMAC -
6155 +Active arm armv7 sunxi - sunxi A10s-OLinuXino-M sun5i:A10S_OLINUXINO_M,STATUSLED=131,AXP152_POWER,CONS_INDEX=1,SPL,SUNXI_EMAC -
6156 +Active arm armv7 sunxi - sunxi A10s-OLinuXino-M_FEL sun5i:A10S_OLINUXINO_M,STATUSLED=131,AXP152_POWER,CONS_INDEX=1,SPL_FEL,SUNXI_EMAC -
6157 +Active arm armv7 sunxi - sunxi A13-OLinuXino sun5i:A13_OLINUXINO,SPL,STATUSLED=201,CONS_INDEX=2 -
6158 +Active arm armv7 sunxi - sunxi A13-OLinuXino_FEL sun5i:A13_OLINUXINO,SPL_FEL,STATUSLED=201,CONS_INDEX=2 -
6159 +Active arm armv7 sunxi - sunxi A13-OLinuXino_FEL_sdcon sun5i:A13_OLINUXINO,SPL_FEL,STATUSLED=201,UART0_PORT_F -
6160 +Active arm armv7 sunxi - sunxi A13-OLinuXinoM sun5i:A13_OLINUXINOM,SPL,NO_AXP,STATUSLED=201,CONS_INDEX=2 -
6161 +Active arm armv7 sunxi - sunxi A13-OLinuXinoM_FEL sun5i:A13_OLINUXINOM,SPL_FEL,NO_AXP,STATUSLED=201,CONS_INDEX=2 -
6162 +Active arm armv7 sunxi - sunxi A13_MID sun5i:A13_MID,SPL,CONS_INDEX=2 -
6163 +Active arm armv7 sunxi - sunxi A20-OLinuXino_Lime sun7i:A20_OLINUXINO_L,CONS_INDEX=1,STATUSLED=226,SPL,SUNXI_EMAC -
6164 +Active arm armv7 sunxi - sunxi A20-OLinuXino_Lime2 sun7i:A20_OLINUXINO_L2,CONS_INDEX=1,STATUSLED=226,SPL,SUNXI_GMAC -
6165 +Active arm armv7 sunxi - sunxi A20-OLinuXino_MICRO sun7i:A20_OLINUXINO_M,CONS_INDEX=1,STATUSLED=226,SPL,SUNXI_EMAC -
6166 +Active arm armv7 sunxi - sunxi A20-OLinuXino_MICRO_FEL sun7i:A20_OLINUXINO_M,CONS_INDEX=1,STATUSLED=226,SPL_FEL,SUNXI_EMAC -
6167 +Active arm armv7 sunxi - sunxi A20-SOM sun7i:A20_SOM,SPL,SUNXI_GMAC,RGMII,STATUSLED1=245,FAST_MBUS -
6168 +Active arm armv7 sunxi - sunxi Ainol_AW1 sun7i:AINOL_AW1,SPL -
6169 +Active arm armv7 sunxi - sunxi Ampe_A76 sun5i:AMPE_A76,SPL,CONS_INDEX=2 -
6170 +Active arm armv7 sunxi - sunxi Auxtek-T003 sun5i:AUXTEK_T003,SPL,AXP152_POWER,STATUSLED=34 -
6171 +Active arm armv7 sunxi - sunxi Auxtek-T004 sun5i:AUXTEK_T004,SPL,AXP152_POWER,STATUSLED=34 -
6172 +Active arm armv7 sunxi - sunxi ba10_tv_box sun4i:BA10_TV_BOX,SPL,SUNXI_EMAC -
6173 +Active arm armv7 sunxi - sunxi Bananapi sun7i:BANANAPI,SPL,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),STATUSLED=244,STATUSLED1=245,FAST_MBUS -
6174 +Active arm armv7 sunxi - sunxi Bananapi_FEL sun7i:BANANAPI,SPL_FEL,SUNXI_GMAC,RGMII,MACPWR=SUNXI_GPH(23),STATUSLED=244,STATUSLED1=245,FAST_MBUS -
6175 +Active arm armv7 sunxi - sunxi Coby_MID7042 sun4i:COBY_MID7042,SPL -
6176 +Active arm armv7 sunxi - sunxi Coby_MID8042 sun4i:COBY_MID8042,SPL -
6177 +Active arm armv7 sunxi - sunxi Coby_MID9742 sun4i:COBY_MID9742,SPL -
6178 +Active arm armv7 sunxi - sunxi Iteaduino_Plus_A10 sun4i:ITEADA10,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 -
6179 +Active arm armv7 sunxi - sunxi Iteaduino_Plus_A20 sun7i:ITEADA20,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 -
6180 +Active arm armv7 sunxi - sunxi Colombus sun6i:COLOMBUS,AXP221_POWER,ENABLE_DLDO1_POWER -
6181 +Active arm armv7 sunxi - sunxi Ippo_q8h sun8i:IPPO_Q8H,NO_AXP,CONS_INDEX=5 -
6182 +Active arm armv7 sunxi - sunxi Cubieboard sun4i:CUBIEBOARD,SPL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 -
6183 +Active arm armv7 sunxi - sunxi Cubieboard2 sun7i:CUBIEBOARD2,SPL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS -
6184 +Active arm armv7 sunxi - sunxi Cubieboard2_FEL sun7i:CUBIEBOARD2,SPL_FEL,SUNXI_GMAC,STATUSLED=244,STATUSLED1=245,FAST_MBUS -
6185 +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS -
6186 +Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII,STATUSLED=245,STATUSLED1=244,STATUSLED2=235,STATUSLED3=231,FAST_MBUS -
6187 +Active arm armv7 sunxi - sunxi Cubieboard_FEL sun4i:CUBIEBOARD,SPL_FEL,SUNXI_EMAC,STATUSLED=244,STATUSLED1=245 -
6188 +Active arm armv7 sunxi - sunxi DNS_M82 sun4i:DNS_M82,SPL -
6189 +Active arm armv7 sunxi - sunxi EOMA68_A10 sun4i:EOMA68_A10,SPL,MMC_SUNXI_SLOT=3,SUNXI_EMAC -
6190 +Active arm armv7 sunxi - sunxi EOMA68_A10_FEL sun4i:EOMA68_A10,SPL_FEL,MMC_SUNXI_SLOT=3,SUNXI_EMAC -
6191 +Active arm armv7 sunxi - sunxi EOMA68_A20 sun7i:EOMA68_A20,SPL,MMC_SUNXI_SLOT=3,SUNXI_EMAC -
6192 +Active arm armv7 sunxi - sunxi EOMA68_A20_FEL sun7i:EOMA68_A20,SPL_FEL,MMC_SUNXI_SLOT=3,SUNXI_EMAC -
6193 +Active arm armv7 sunxi - sunxi EU3000 sun7i:EU3000,SPL -
6194 +Active arm armv7 sunxi - sunxi Forfun_Q88DB sun7i:FORFUN_Q88DB,SPL -
6195 +Active arm armv7 sunxi - sunxi Gooseberry_A721 sun4i:GOOSEBERRY_A721,SPL -
6196 +Active arm armv7 sunxi - sunxi H6 sun4i:H6,SPL -
6197 +Active arm armv7 sunxi - sunxi Hackberry sun4i:HACKBERRY,SPL,SUNXI_EMAC,MACPWR=SUNXI_GPH(19) -
6198 +Active arm armv7 sunxi - sunxi HBD_MID_S906 sun7i:HBD_MID_S906,SPL -
6199 +Active arm armv7 sunxi - sunxi HCore_HC860 sun4i:HCORE_HC860,SPL -
6200 +Active arm armv7 sunxi - sunxi Hyundai_A7 sun4i:HYUNDAI_A7,SPL -
6201 +Active arm armv7 sunxi - sunxi Hyundai_A7HD sun4i:A7HD,SPL -
6202 +Active arm armv7 sunxi - sunxi i12-tvbox sun7i:I12_TVBOX,SPL,FAST_MBUS,STATUSLED=244 -
6203 +Active arm armv7 sunxi - sunxi ICOU_Fatty_I sun7i:ICOU_FATTY_I,SPL -
6204 +Active arm armv7 sunxi - sunxi Interra-3 sun7i:INTERRA3,SPL,SUNXI_GMAC,FAST_MBUS,MMC_SUNXI_SLOT=2 -
6205 +Active arm armv7 sunxi - sunxi INet_86VZ sun5i:INET_86VZ,SPL -
6206 +Active arm armv7 sunxi - sunxi INet_86VZ_FEL sun5i:INET_86VZ,SPL_FEL,UART0_PORT_F -
6207 +Active arm armv7 sunxi - sunxi INet97F-II sun4i:INET97F_II,SPL -
6208 +Active arm armv7 sunxi - sunxi INet_K70HC sun7i:INET_K70HC,SPL -
6209 +Active arm armv7 sunxi - sunxi Jesurun-Q5 sun4i:JESURUN_Q5,SPL,SUNXI_EMAC,STATUSLED=244 -
6210 +Active arm armv7 sunxi - sunxi K1001L1C sun7i:K1001L1C,SPL -
6211 +Active arm armv7 sunxi - sunxi Kurio_7S sun7i:KURIO_7S,SPL -
6212 +Active arm armv7 sunxi - sunxi Langcent_H6S sun7i:LANGCENT_H6S,SPL -
6213 +Active arm armv7 sunxi - sunxi Linksprite_pcDuino3 sun7i:LINKSPRITE_PCDUINO3,SPL,SUNXI_GMAC,FAST_MBUS -
6214 +Active arm armv7 sunxi - sunxi Marsboard_A10 sun4i:MARSBOARD_A10,SPL,SUNXI_EMAC,NO_AXP -
6215 +Active arm armv7 sunxi - sunxi Marsboard_A20 sun7i:MARSBOARD_A20,SPL,SUNXI_EMAC,NO_AXP -
6216 +Active arm armv7 sunxi - sunxi Marsboard_A20_debug sun7i:MARSBOARD_A20,SPL,SUNXI_EMAC,NO_AXP,SYS_SECONDARY_ON -
6217 +Active arm armv7 sunxi - sunxi Megafeis_A08 sun5i:MEFAFEIS_A08,SPL -
6218 +Active arm armv7 sunxi - sunxi Mele_A1000 sun4i:MELE_A1000,SPL,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),STATUSLED=234 -
6219 +Active arm armv7 sunxi - sunxi Mele_A1000_FEL sun4i:MELE_A1000,SPL_FEL,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),STATUSLED=234 -
6220 +Active arm armv7 sunxi - sunxi Mele_A1000G sun4i:MELE_A1000G,SPL,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),STATUSLED=234 -
6221 +Active arm armv7 sunxi - sunxi Mele_A3700 sun4i:MELE_A3700,SPL,SUNXI_EMAC,MACPWR=SUNXI_GPH(15),STATUSLED=234 -
6222 +Active arm armv7 sunxi - sunxi Merrii_Hummingbird_A20 sun7i:MERRII_HUMMINGBIRD_A20,SPL -
6223 +Active arm armv7 sunxi - sunxi merrii_m2 sun7i:MERRII_M2,SPL,SUNXI_EMAC -
6224 +Active arm armv7 sunxi - sunxi Mini-X sun4i:MINI_X,SPL -
6225 +Active arm armv7 sunxi - sunxi Mini-X-1Gb sun4i:MINI_X_1GB,SPL -
6226 +Active arm armv7 sunxi - sunxi Mini-X_A10s sun5i:MINI_X_A10S,SPL -
6227 +Active arm armv7 sunxi - sunxi mk802 sun4i:MK802,SPL,NO_AXP -
6228 +Active arm armv7 sunxi - sunxi mk802-1gb sun4i:MK802_1GB,SPL,NO_AXP -
6229 +Active arm armv7 sunxi - sunxi mk802_a10s sun5i:MK802_A10S,SPL,AXP152_POWER,STATUSLED=34 -
6230 +Active arm armv7 sunxi - sunxi mk802ii_A20 sun7i:MK802II_A20,SPL -
6231 +Active arm armv7 sunxi - sunxi mk802ii sun4i:MK802II,SPL -
6232 +Active arm armv7 sunxi - sunxi mk808c_A20 sun7i:MK808C_A20,SPL -
6233 +Active arm armv7 sunxi - sunxi OLIMEX-A13-SOM sun5i:OLIMEX_A13_SOM,SPL,NO_AXP,STATUSLED=201,CONS_INDEX=2 -
6234 +Active arm armv7 sunxi - sunxi pcDuino sun4i:PCDUINO,SPL,SUNXI_EMAC -
6235 +Active arm armv7 sunxi - sunxi pengpod1000 sun4i:PENGPOD1000,SPL -
6236 +Active arm armv7 sunxi - sunxi pengpod700 sun4i:PENGPOD700,SPL -
6237 +Active arm armv7 suxni - sunxi pineriver-h25 sun5i:PINERIVER-H25,SPL
6238 +Active arm armv7 sunxi - sunxi POV_TAB_P703 sun5i:POV_TAB_P703,SPL -
6239 +Active arm armv7 sunxi - sunxi PoV_ProTab2_IPS9 sun4i:POV_PROTAB2,SPL -
6240 +Active arm armv7 sunxi - sunxi PoV_ProTab2_IPS_3g sun4i:POV_PROTAB2,SPL -
6241 +Active arm armv7 sunxi - sunxi PoV_ProTab2_XXL sun4i:POV_PROTAB2_XXL,SPL -
6242 +Active arm armv7 sunxi - sunxi qt840a sun7i:QT840A,SPL,FAST_MBUS,STATUSLED=244 -
6243 +Active arm armv7 sunxi - sunxi r7-tv-dongle sun5i:R7DONGLE,SPL,AXP152_POWER,STATUSLED=34 -
6244 +Active arm armv7 sunxi - sunxi Sanei_N90 sun4i:SANEI_N90,SPL -
6245 +Active arm armv7 sunxi - sunxi Semitime_G2 sun5i:SEMITIME_G2,SPL,AXP152_POWER,STATUSLED=34 -
6246 +Active arm armv7 sunxi - sunxi sun4i sun4i:SUNXI_EMAC -
6247 +Active arm armv7 sunxi - sunxi sun4i_sdcon sun4i:UART0_PORT_F,SUNXI_EMAC -
6248 +Active arm armv7 sunxi - sunxi sun5i sun5i:SUNXI_EMAC -
6249 +Active arm armv7 sunxi - sunxi sun5i_sdcon sun5i:UART0_PORT_F,SUNXI_EMAC -
6250 +Active arm armv7 sunxi - sunxi sun5i_uart1 sun5i:CONS_INDEX=2,SUNXI_EMAC -
6251 +Active arm armv7 sunxi - sunxi TZX-Q8-713B6 sun5i:TZX_Q8_713B6,SPL,CONS_INDEX=2 -
6252 +Active arm armv7 sunxi - sunxi TZX-Q8-713B7 sun5i:TZX_Q8_713B7,SPL,CONS_INDEX=2 -
6253 +Active arm armv7 sunxi - sunxi uhost_u1a sun4i:UHOST_U1A,SPL,STATUSLED=34 -
6254 +Active arm armv7 sunxi - sunxi Wexler_TAB_7200 sun7i:WEXLER_TAB_7200,SPL -
6255 +Active arm armv7 sunxi - sunxi wobo-i5 sun5i:WOBO_I5,SPL,STATUSLED=34 -
6256 +Active arm armv7 sunxi - sunxi xzpad700 sun5i:XZPAD700,SPL -
6257 +Active arm armv7 sunxi - sunxi zatab sun4i:ZATAB,SPL -
6258 Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
6259 Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
6260 Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
6261 diff -ruN u-boot-2014.04/common/spl/spl_mmc.c u-boot-sunxi/common/spl/spl_mmc.c
6262 --- u-boot-2014.04/common/spl/spl_mmc.c 2014-04-14 21:19:24.000000000 +0200
6263 +++ u-boot-sunxi/common/spl/spl_mmc.c 2014-09-06 16:58:36.205953114 +0200
6264 @@ -29,8 +29,10 @@
6265 if (err == 0)
6266 goto end;
6267
6268 - if (image_get_magic(header) != IH_MAGIC)
6269 + if (image_get_magic(header) != IH_MAGIC) {
6270 + printf("spl: not an uImage at %lu\n", sector);
6271 return -1;
6272 + }
6273
6274 spl_parse_image_header(header);
6275
6276 diff -ruN u-boot-2014.04/drivers/gpio/Makefile u-boot-sunxi/drivers/gpio/Makefile
6277 --- u-boot-2014.04/drivers/gpio/Makefile 2014-04-14 21:19:24.000000000 +0200
6278 +++ u-boot-sunxi/drivers/gpio/Makefile 2014-09-06 16:58:36.253953113 +0200
6279 @@ -34,3 +34,4 @@
6280 obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
6281 obj-$(CONFIG_TCA642X) += tca642x.o
6282 oby-$(CONFIG_SX151X) += sx151x.o
6283 +obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
6284 diff -ruN u-boot-2014.04/drivers/gpio/sunxi_gpio.c u-boot-sunxi/drivers/gpio/sunxi_gpio.c
6285 --- u-boot-2014.04/drivers/gpio/sunxi_gpio.c 1970-01-01 01:00:00.000000000 +0100
6286 +++ u-boot-sunxi/drivers/gpio/sunxi_gpio.c 2014-09-06 16:58:36.253953113 +0200
6287 @@ -0,0 +1,102 @@
6288 +/*
6289 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
6290 + *
6291 + * Based on earlier arch/arm/cpu/armv7/sunxi/gpio.c:
6292 + *
6293 + * (C) Copyright 2007-2011
6294 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6295 + * Tom Cubie <tangliang@allwinnertech.com>
6296 + *
6297 + * SPDX-License-Identifier: GPL-2.0+
6298 + */
6299 +
6300 +#include <common.h>
6301 +#include <asm/io.h>
6302 +#include <asm/gpio.h>
6303 +
6304 +static int sunxi_gpio_output(u32 pin, u32 val)
6305 +{
6306 + u32 dat;
6307 + u32 bank = GPIO_BANK(pin);
6308 + u32 num = GPIO_NUM(pin);
6309 + struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
6310 +
6311 + dat = readl(&pio->dat);
6312 + if (val)
6313 + dat |= 0x1 << num;
6314 + else
6315 + dat &= ~(0x1 << num);
6316 +
6317 + writel(dat, &pio->dat);
6318 +
6319 + return 0;
6320 +}
6321 +
6322 +static int sunxi_gpio_input(u32 pin)
6323 +{
6324 + u32 dat;
6325 + u32 bank = GPIO_BANK(pin);
6326 + u32 num = GPIO_NUM(pin);
6327 + struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
6328 +
6329 + dat = readl(&pio->dat);
6330 + dat >>= num;
6331 +
6332 + return dat & 0x1;
6333 +}
6334 +
6335 +int gpio_request(unsigned gpio, const char *label)
6336 +{
6337 + return 0;
6338 +}
6339 +
6340 +int gpio_free(unsigned gpio)
6341 +{
6342 + return 0;
6343 +}
6344 +
6345 +int gpio_direction_input(unsigned gpio)
6346 +{
6347 + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT);
6348 +
6349 + return sunxi_gpio_input(gpio);
6350 +}
6351 +
6352 +int gpio_direction_output(unsigned gpio, int value)
6353 +{
6354 + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT);
6355 +
6356 + return sunxi_gpio_output(gpio, value);
6357 +}
6358 +
6359 +int gpio_get_value(unsigned gpio)
6360 +{
6361 + return sunxi_gpio_input(gpio);
6362 +}
6363 +
6364 +int gpio_set_value(unsigned gpio, int value)
6365 +{
6366 + return sunxi_gpio_output(gpio, value);
6367 +}
6368 +
6369 +int sunxi_name_to_gpio(const char *name)
6370 +{
6371 + int group = 0;
6372 + int groupsize = 9 * 32;
6373 + long pin;
6374 + char *eptr;
6375 + if (*name == 'P' || *name == 'p')
6376 + name++;
6377 + if (*name >= 'A') {
6378 + group = *name - (*name > 'a' ? 'a' : 'A');
6379 + groupsize = 32;
6380 + name++;
6381 + }
6382 +
6383 + pin = simple_strtol(name, &eptr, 10);
6384 + if (!*name || *eptr)
6385 + return -1;
6386 + if (pin < 0 || pin > groupsize || group >= 9)
6387 + return -1;
6388 + return group * 32 + pin;
6389 +}
6390 diff -ruN u-boot-2014.04/drivers/i2c/Makefile u-boot-sunxi/drivers/i2c/Makefile
6391 --- u-boot-2014.04/drivers/i2c/Makefile 2014-04-14 21:19:24.000000000 +0200
6392 +++ u-boot-sunxi/drivers/i2c/Makefile 2014-09-06 16:58:36.265953112 +0200
6393 @@ -27,5 +27,6 @@
6394 obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
6395 obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
6396 obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
6397 +obj-$(CONFIG_SYS_I2C_SUNXI) += mvtwsi.o
6398 obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
6399 obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o
6400 diff -ruN u-boot-2014.04/drivers/i2c/mvtwsi.c u-boot-sunxi/drivers/i2c/mvtwsi.c
6401 --- u-boot-2014.04/drivers/i2c/mvtwsi.c 2014-04-14 21:19:24.000000000 +0200
6402 +++ u-boot-sunxi/drivers/i2c/mvtwsi.c 2014-09-06 16:58:36.265953112 +0200
6403 @@ -22,6 +22,8 @@
6404 #include <asm/arch/orion5x.h>
6405 #elif defined(CONFIG_KIRKWOOD)
6406 #include <asm/arch/kirkwood.h>
6407 +#elif defined(CONFIG_SUNXI)
6408 +#include <asm/arch/i2c.h>
6409 #else
6410 #error Driver mvtwsi not supported by SoC or board
6411 #endif
6412 @@ -30,6 +32,20 @@
6413 * TWSI register structure
6414 */
6415
6416 +#ifdef CONFIG_SUNXI
6417 +
6418 +struct mvtwsi_registers {
6419 + u32 slave_address;
6420 + u32 xtnd_slave_addr;
6421 + u32 data;
6422 + u32 control;
6423 + u32 status;
6424 + u32 baudrate;
6425 + u32 soft_reset;
6426 +};
6427 +
6428 +#else
6429 +
6430 struct mvtwsi_registers {
6431 u32 slave_address;
6432 u32 data;
6433 @@ -43,6 +59,8 @@
6434 u32 soft_reset;
6435 };
6436
6437 +#endif
6438 +
6439 /*
6440 * Control register fields
6441 */
6442 @@ -216,21 +234,7 @@
6443 */
6444
6445 #define TWSI_FREQUENCY(m, n) \
6446 - ((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n))))
6447 -
6448 -/*
6449 - * These are required to be reprogrammed before enabling the controller
6450 - * because a reset loses them.
6451 - * Default values come from the spec, but a twsi_reset will change them.
6452 - * twsi_slave_address left uninitialized lest checkpatch.pl complains.
6453 - */
6454 -
6455 -/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */
6456 -static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */
6457 -/* Default frequency corresponding to default m=4, n=4 */
6458 -static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4);
6459 -/* Default slave address is 0 (so is an uninitialized static) */
6460 -static u8 twsi_slave_address;
6461 + (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)))
6462
6463 /*
6464 * Reset controller.
6465 @@ -238,7 +242,7 @@
6466 * Controller reset also resets the baud rate and slave address, so
6467 * re-establish them.
6468 */
6469 -static void twsi_reset(void)
6470 +static void twsi_reset(u8 baud_rate, u8 slave_address)
6471 {
6472 /* ensure controller will be enabled by any twsi*() function */
6473 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
6474 @@ -247,9 +251,9 @@
6475 /* wait 2 ms -- this is what the Marvell LSP does */
6476 udelay(20000);
6477 /* set baud rate */
6478 - writel(twsi_baud_rate, &twsi->baudrate);
6479 + writel(baud_rate, &twsi->baudrate);
6480 /* set slave address even though we don't use it */
6481 - writel(twsi_slave_address, &twsi->slave_address);
6482 + writel(slave_address, &twsi->slave_address);
6483 writel(0, &twsi->xtnd_slave_addr);
6484 /* assert STOP but don't care for the result */
6485 (void) twsi_stop(0);
6486 @@ -277,12 +281,8 @@
6487 }
6488 }
6489 }
6490 - /* save baud rate and slave for later calls to twsi_reset */
6491 - twsi_baud_rate = baud;
6492 - twsi_actual_speed = highest_speed;
6493 - twsi_slave_address = slaveadd;
6494 /* reset controller */
6495 - twsi_reset();
6496 + twsi_reset(baud, slaveadd);
6497 }
6498
6499 /*
6500 diff -ruN u-boot-2014.04/drivers/mmc/Makefile u-boot-sunxi/drivers/mmc/Makefile
6501 --- u-boot-2014.04/drivers/mmc/Makefile 2014-04-14 21:19:24.000000000 +0200
6502 +++ u-boot-sunxi/drivers/mmc/Makefile 2014-09-06 16:58:36.281953112 +0200
6503 @@ -28,6 +28,7 @@
6504 obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
6505 obj-$(CONFIG_DWMMC) += dw_mmc.o
6506 obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o
6507 +obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o
6508 obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
6509 obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o
6510 ifdef CONFIG_SPL_BUILD
6511 diff -ruN u-boot-2014.04/drivers/mmc/sunxi_mmc.c u-boot-sunxi/drivers/mmc/sunxi_mmc.c
6512 --- u-boot-2014.04/drivers/mmc/sunxi_mmc.c 1970-01-01 01:00:00.000000000 +0100
6513 +++ u-boot-sunxi/drivers/mmc/sunxi_mmc.c 2014-09-06 16:58:36.281953112 +0200
6514 @@ -0,0 +1,385 @@
6515 +/*
6516 + * (C) Copyright 2007-2011
6517 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6518 + * Aaron <leafy.myeh@allwinnertech.com>
6519 + *
6520 + * MMC driver for allwinner sunxi platform.
6521 + *
6522 + * SPDX-License-Identifier: GPL-2.0+
6523 + */
6524 +
6525 +#include <common.h>
6526 +#include <malloc.h>
6527 +#include <mmc.h>
6528 +#include <asm/io.h>
6529 +#include <asm/arch/clock.h>
6530 +#include <asm/arch/cpu.h>
6531 +#include <asm/arch/mmc.h>
6532 +
6533 +struct sunxi_mmc_host {
6534 + unsigned mmc_no;
6535 + uint32_t *mclkreg;
6536 + unsigned database;
6537 + unsigned fatal_err;
6538 + unsigned mod_clk;
6539 + struct sunxi_mmc *reg;
6540 + struct mmc_config cfg;
6541 +};
6542 +
6543 +/* support 4 mmc hosts */
6544 +struct sunxi_mmc_host mmc_host[4];
6545 +
6546 +static int mmc_resource_init(int sdc_no)
6547 +{
6548 + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
6549 + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
6550 +
6551 + debug("init mmc %d resource\n", sdc_no);
6552 +
6553 + switch (sdc_no) {
6554 + case 0:
6555 + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
6556 + mmchost->mclkreg = &ccm->sd0_clk_cfg;
6557 + break;
6558 + case 1:
6559 + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
6560 + mmchost->mclkreg = &ccm->sd1_clk_cfg;
6561 + break;
6562 + case 2:
6563 + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
6564 + mmchost->mclkreg = &ccm->sd2_clk_cfg;
6565 + break;
6566 + case 3:
6567 + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
6568 + mmchost->mclkreg = &ccm->sd3_clk_cfg;
6569 + break;
6570 + default:
6571 + printf("Wrong mmc number %d\n", sdc_no);
6572 + return -1;
6573 + }
6574 +#ifdef CONFIG_SUN6I
6575 + mmchost->database = (unsigned int)mmchost->reg + 0x200;
6576 +#else
6577 + mmchost->database = (unsigned int)mmchost->reg + 0x100;
6578 +#endif
6579 + mmchost->mmc_no = sdc_no;
6580 +
6581 + return 0;
6582 +}
6583 +
6584 +static int mmc_clk_io_on(int sdc_no)
6585 +{
6586 + unsigned int pll_clk;
6587 + unsigned int divider;
6588 + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
6589 + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
6590 +
6591 + debug("init mmc %d clock and io\n", sdc_no);
6592 +
6593 + /* config ahb clock */
6594 + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
6595 +
6596 +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I)
6597 + /* unassert reset */
6598 + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
6599 +#endif
6600 +
6601 + /* config mod clock */
6602 + pll_clk = clock_get_pll6();
6603 + /* should be close to 100 MHz but no more, so round up */
6604 + divider = ((pll_clk + 99999999) / 100000000) - 1;
6605 + writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL6 | divider,
6606 + mmchost->mclkreg);
6607 + mmchost->mod_clk = pll_clk / (divider + 1);
6608 +
6609 + return 0;
6610 +}
6611 +
6612 +static int mmc_update_clk(struct mmc *mmc)
6613 +{
6614 + struct sunxi_mmc_host *mmchost = mmc->priv;
6615 + unsigned int cmd;
6616 + unsigned timeout_msecs = 2000;
6617 +
6618 + cmd = SUNXI_MMC_CMD_START |
6619 + SUNXI_MMC_CMD_UPCLK_ONLY |
6620 + SUNXI_MMC_CMD_WAIT_PRE_OVER;
6621 + writel(cmd, &mmchost->reg->cmd);
6622 + while (readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) {
6623 + if (!timeout_msecs--)
6624 + return -1;
6625 + udelay(1000);
6626 + }
6627 +
6628 + /* clock update sets various irq status bits, clear these */
6629 + writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);
6630 +
6631 + return 0;
6632 +}
6633 +
6634 +static int mmc_config_clock(struct mmc *mmc, unsigned div)
6635 +{
6636 + struct sunxi_mmc_host *mmchost = mmc->priv;
6637 + unsigned rval = readl(&mmchost->reg->clkcr);
6638 +
6639 + /* Disable Clock */
6640 + rval &= ~SUNXI_MMC_CLK_ENABLE;
6641 + writel(rval, &mmchost->reg->clkcr);
6642 + if (mmc_update_clk(mmc))
6643 + return -1;
6644 +
6645 + /* Change Divider Factor */
6646 + rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
6647 + rval |= div;
6648 + writel(rval, &mmchost->reg->clkcr);
6649 + if (mmc_update_clk(mmc))
6650 + return -1;
6651 + /* Re-enable Clock */
6652 + rval |= SUNXI_MMC_CLK_ENABLE;
6653 + writel(rval, &mmchost->reg->clkcr);
6654 +
6655 + if (mmc_update_clk(mmc))
6656 + return -1;
6657 +
6658 + return 0;
6659 +}
6660 +
6661 +static void mmc_set_ios(struct mmc *mmc)
6662 +{
6663 + struct sunxi_mmc_host *mmchost = mmc->priv;
6664 + unsigned int clkdiv = 0;
6665 +
6666 + debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n",
6667 + mmc->bus_width, mmc->clock, mmchost->mod_clk);
6668 +
6669 + /* Change clock first */
6670 + clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2;
6671 + if (mmc->clock) {
6672 + if (mmc_config_clock(mmc, clkdiv)) {
6673 + mmchost->fatal_err = 1;
6674 + return;
6675 + }
6676 + }
6677 +
6678 + /* Change bus width */
6679 + if (mmc->bus_width == 8)
6680 + writel(0x2, &mmchost->reg->width);
6681 + else if (mmc->bus_width == 4)
6682 + writel(0x1, &mmchost->reg->width);
6683 + else
6684 + writel(0x0, &mmchost->reg->width);
6685 +}
6686 +
6687 +static int mmc_core_init(struct mmc *mmc)
6688 +{
6689 + struct sunxi_mmc_host *mmchost = mmc->priv;
6690 +
6691 + /* Reset controller */
6692 + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
6693 + udelay(1000);
6694 +
6695 + return 0;
6696 +}
6697 +
6698 +static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data)
6699 +{
6700 + struct sunxi_mmc_host *mmchost = mmc->priv;
6701 + const int reading = !!(data->flags & MMC_DATA_READ);
6702 + const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
6703 + SUNXI_MMC_STATUS_FIFO_FULL;
6704 + unsigned i;
6705 + unsigned byte_cnt = data->blocksize * data->blocks;
6706 + unsigned timeout_msecs = 2000;
6707 + unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
6708 +
6709 + /* Always read / write data through the CPU */
6710 + setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
6711 +
6712 + for (i = 0; i < (byte_cnt >> 2); i++) {
6713 + while (readl(&mmchost->reg->status) & status_bit) {
6714 + if (!timeout_msecs--)
6715 + return -1;
6716 + udelay(1000);
6717 + }
6718 +
6719 + if (reading)
6720 + buff[i] = readl(mmchost->database);
6721 + else
6722 + writel(buff[i], mmchost->database);
6723 + }
6724 +
6725 + return 0;
6726 +}
6727 +
6728 +static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs,
6729 + unsigned int done_bit, const char *what)
6730 +{
6731 + struct sunxi_mmc_host *mmchost = mmc->priv;
6732 + unsigned int status;
6733 +
6734 + do {
6735 + status = readl(&mmchost->reg->rint);
6736 + if (!timeout_msecs-- ||
6737 + (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
6738 + debug("%s timeout %x\n", what,
6739 + status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
6740 + return TIMEOUT;
6741 + }
6742 + udelay(1000);
6743 + } while (!(status & done_bit));
6744 +
6745 + return 0;
6746 +}
6747 +
6748 +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
6749 + struct mmc_data *data)
6750 +{
6751 + struct sunxi_mmc_host *mmchost = mmc->priv;
6752 + unsigned int cmdval = SUNXI_MMC_CMD_START;
6753 + unsigned int timeout_msecs;
6754 + int error = 0;
6755 + unsigned int status = 0;
6756 + unsigned int bytecnt = 0;
6757 +
6758 + if (mmchost->fatal_err)
6759 + return -1;
6760 + if (cmd->resp_type & MMC_RSP_BUSY)
6761 + debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
6762 + if (cmd->cmdidx == 12)
6763 + return 0;
6764 +
6765 + if (!cmd->cmdidx)
6766 + cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
6767 + if (cmd->resp_type & MMC_RSP_PRESENT)
6768 + cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
6769 + if (cmd->resp_type & MMC_RSP_136)
6770 + cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
6771 + if (cmd->resp_type & MMC_RSP_CRC)
6772 + cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
6773 +
6774 + if (data) {
6775 + if ((u32) data->dest & 0x3) {
6776 + error = -1;
6777 + goto out;
6778 + }
6779 +
6780 + cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
6781 + if (data->flags & MMC_DATA_WRITE)
6782 + cmdval |= SUNXI_MMC_CMD_WRITE;
6783 + if (data->blocks > 1)
6784 + cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
6785 + writel(data->blocksize, &mmchost->reg->blksz);
6786 + writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
6787 + }
6788 +
6789 + debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,
6790 + cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
6791 + writel(cmd->cmdarg, &mmchost->reg->arg);
6792 +
6793 + if (!data)
6794 + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
6795 +
6796 + /*
6797 + * transfer data and check status
6798 + * STATREG[2] : FIFO empty
6799 + * STATREG[3] : FIFO full
6800 + */
6801 + if (data) {
6802 + int ret = 0;
6803 +
6804 + bytecnt = data->blocksize * data->blocks;
6805 + debug("trans data %d bytes\n", bytecnt);
6806 + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
6807 + ret = mmc_trans_data_by_cpu(mmc, data);
6808 + if (ret) {
6809 + error = readl(&mmchost->reg->rint) & \
6810 + SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
6811 + error = TIMEOUT;
6812 + goto out;
6813 + }
6814 + }
6815 +
6816 + error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
6817 + if (error)
6818 + goto out;
6819 +
6820 + if (data) {
6821 + timeout_msecs = 120;
6822 + debug("cacl timeout %x msec\n", timeout_msecs);
6823 + error = mmc_rint_wait(mmc, timeout_msecs,
6824 + data->blocks > 1 ?
6825 + SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
6826 + SUNXI_MMC_RINT_DATA_OVER,
6827 + "data");
6828 + if (error)
6829 + goto out;
6830 + }
6831 +
6832 + if (cmd->resp_type & MMC_RSP_BUSY) {
6833 + timeout_msecs = 2000;
6834 + do {
6835 + status = readl(&mmchost->reg->status);
6836 + if (!timeout_msecs--) {
6837 + debug("busy timeout\n");
6838 + error = TIMEOUT;
6839 + goto out;
6840 + }
6841 + udelay(1000);
6842 + } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
6843 + }
6844 +
6845 + if (cmd->resp_type & MMC_RSP_136) {
6846 + cmd->response[0] = readl(&mmchost->reg->resp3);
6847 + cmd->response[1] = readl(&mmchost->reg->resp2);
6848 + cmd->response[2] = readl(&mmchost->reg->resp1);
6849 + cmd->response[3] = readl(&mmchost->reg->resp0);
6850 + debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
6851 + cmd->response[3], cmd->response[2],
6852 + cmd->response[1], cmd->response[0]);
6853 + } else {
6854 + cmd->response[0] = readl(&mmchost->reg->resp0);
6855 + debug("mmc resp 0x%08x\n", cmd->response[0]);
6856 + }
6857 +out:
6858 + if (error < 0) {
6859 + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl);
6860 + mmc_update_clk(mmc);
6861 + }
6862 + writel(0xffffffff, &mmchost->reg->rint);
6863 + writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
6864 + &mmchost->reg->gctrl);
6865 +
6866 + return error;
6867 +}
6868 +
6869 +static const struct mmc_ops sunxi_mmc_ops = {
6870 + .send_cmd = mmc_send_cmd,
6871 + .set_ios = mmc_set_ios,
6872 + .init = mmc_core_init,
6873 +};
6874 +
6875 +int sunxi_mmc_init(int sdc_no)
6876 +{
6877 + struct mmc_config *cfg = &mmc_host[sdc_no].cfg;
6878 +
6879 + memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
6880 +
6881 + cfg->name = "SUNXI SD/MMC";
6882 + cfg->ops = &sunxi_mmc_ops;
6883 +
6884 + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
6885 + cfg->host_caps = MMC_MODE_4BIT;
6886 + cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
6887 + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
6888 +
6889 + cfg->f_min = 400000;
6890 + cfg->f_max = 52000000;
6891 +
6892 + mmc_resource_init(sdc_no);
6893 + mmc_clk_io_on(sdc_no);
6894 +
6895 + if (mmc_create(cfg, &mmc_host[sdc_no]) == NULL)
6896 + return -1;
6897 +
6898 + return 0;
6899 +}
6900 diff -ruN u-boot-2014.04/drivers/net/designware.c u-boot-sunxi/drivers/net/designware.c
6901 --- u-boot-2014.04/drivers/net/designware.c 2014-04-14 21:19:24.000000000 +0200
6902 +++ u-boot-sunxi/drivers/net/designware.c 2014-09-06 16:58:36.301953111 +0200
6903 @@ -249,7 +249,7 @@
6904 rx_descs_init(dev);
6905 tx_descs_init(dev);
6906
6907 - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode);
6908 + writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
6909
6910 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
6911 &dma_p->opmode);
6912 @@ -280,10 +280,18 @@
6913 u32 desc_num = priv->tx_currdescnum;
6914 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
6915
6916 - /* Invalidate only "status" field for the following check */
6917 - invalidate_dcache_range((unsigned long)&desc_p->txrx_status,
6918 - (unsigned long)&desc_p->txrx_status +
6919 - sizeof(desc_p->txrx_status));
6920 + /*
6921 + * Strictly we only need to invalidate the "txrx_status" field
6922 + * for the following check, but on some platforms we cannot
6923 + * invalidate only 4 bytes, so roundup to
6924 + * ARCH_DMA_MINALIGN. This is safe because the individual
6925 + * descriptors in the array are each aligned to
6926 + * ARCH_DMA_MINALIGN.
6927 + */
6928 + invalidate_dcache_range(
6929 + (unsigned long)desc_p,
6930 + (unsigned long)desc_p +
6931 + roundup(sizeof(desc_p->txrx_status), ARCH_DMA_MINALIGN));
6932
6933 /* Check if the descriptor is owned by CPU */
6934 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
6935 @@ -351,7 +359,7 @@
6936 /* Invalidate received data */
6937 invalidate_dcache_range((unsigned long)desc_p->dmamac_addr,
6938 (unsigned long)desc_p->dmamac_addr +
6939 - length);
6940 + roundup(length, ARCH_DMA_MINALIGN));
6941
6942 NetReceive(desc_p->dmamac_addr, length);
6943
6944 @@ -390,6 +398,8 @@
6945 if (!phydev)
6946 return -1;
6947
6948 + phy_connect_dev(phydev, dev);
6949 +
6950 phydev->supported &= PHY_GBIT_FEATURES;
6951 phydev->advertising = phydev->supported;
6952
6953 @@ -412,7 +422,8 @@
6954 * Since the priv structure contains the descriptors which need a strict
6955 * buswidth alignment, memalign is used to allocate memory
6956 */
6957 - priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
6958 + priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
6959 + sizeof(struct dw_eth_dev));
6960 if (!priv) {
6961 free(dev);
6962 return -ENOMEM;
6963 diff -ruN u-boot-2014.04/drivers/net/designware.h u-boot-sunxi/drivers/net/designware.h
6964 --- u-boot-2014.04/drivers/net/designware.h 2014-04-14 21:19:24.000000000 +0200
6965 +++ u-boot-sunxi/drivers/net/designware.h 2014-09-06 16:58:36.301953111 +0200
6966 @@ -77,18 +77,18 @@
6967
6968 #define DW_DMA_BASE_OFFSET (0x1000)
6969
6970 +/* Default DMA Burst length */
6971 +#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
6972 +#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
6973 +#endif
6974 +
6975 /* Bus mode register definitions */
6976 #define FIXEDBURST (1 << 16)
6977 #define PRIORXTX_41 (3 << 14)
6978 #define PRIORXTX_31 (2 << 14)
6979 #define PRIORXTX_21 (1 << 14)
6980 #define PRIORXTX_11 (0 << 14)
6981 -#define BURST_1 (1 << 8)
6982 -#define BURST_2 (2 << 8)
6983 -#define BURST_4 (4 << 8)
6984 -#define BURST_8 (8 << 8)
6985 -#define BURST_16 (16 << 8)
6986 -#define BURST_32 (32 << 8)
6987 +#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
6988 #define RXHIGHPRIO (1 << 1)
6989 #define DMAMAC_SRST (1 << 0)
6990
6991 @@ -215,15 +215,14 @@
6992 #endif
6993
6994 struct dw_eth_dev {
6995 - u32 interface;
6996 - u32 tx_currdescnum;
6997 - u32 rx_currdescnum;
6998 -
6999 struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
7000 struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
7001 + char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
7002 + char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
7003
7004 - char txbuffs[TX_TOTAL_BUFSIZE];
7005 - char rxbuffs[RX_TOTAL_BUFSIZE];
7006 + u32 interface;
7007 + u32 tx_currdescnum;
7008 + u32 rx_currdescnum;
7009
7010 struct eth_mac_regs *mac_regs_p;
7011 struct eth_dma_regs *dma_regs_p;
7012 diff -ruN u-boot-2014.04/drivers/net/Makefile u-boot-sunxi/drivers/net/Makefile
7013 --- u-boot-2014.04/drivers/net/Makefile 2014-04-14 21:19:24.000000000 +0200
7014 +++ u-boot-sunxi/drivers/net/Makefile 2014-09-06 16:58:36.297953112 +0200
7015 @@ -50,7 +50,7 @@
7016 obj-$(CONFIG_SH_ETHER) += sh_eth.o
7017 obj-$(CONFIG_SMC91111) += smc91111.o
7018 obj-$(CONFIG_SMC911X) += smc911x.o
7019 -obj-$(CONFIG_SUNXI_WEMAC) += sunxi_wemac.o
7020 +obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o
7021 obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
7022 obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
7023 obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o
7024 diff -ruN u-boot-2014.04/drivers/net/sunxi_emac.c u-boot-sunxi/drivers/net/sunxi_emac.c
7025 --- u-boot-2014.04/drivers/net/sunxi_emac.c 1970-01-01 01:00:00.000000000 +0100
7026 +++ u-boot-sunxi/drivers/net/sunxi_emac.c 2014-09-06 16:58:36.317953111 +0200
7027 @@ -0,0 +1,521 @@
7028 +/*
7029 + * sunxi_emac.c -- Allwinner A10 ethernet driver
7030 + *
7031 + * (C) Copyright 2012, Stefan Roese <sr@denx.de>
7032 + *
7033 + * SPDX-License-Identifier: GPL-2.0+
7034 + */
7035 +
7036 +#include <common.h>
7037 +#include <linux/err.h>
7038 +#include <malloc.h>
7039 +#include <miiphy.h>
7040 +#include <net.h>
7041 +#include <asm/io.h>
7042 +#include <asm/arch/clock.h>
7043 +#include <asm/arch/gpio.h>
7044 +
7045 +/* EMAC register */
7046 +struct emac_regs {
7047 + u32 ctl; /* 0x00 */
7048 + u32 tx_mode; /* 0x04 */
7049 + u32 tx_flow; /* 0x08 */
7050 + u32 tx_ctl0; /* 0x0c */
7051 + u32 tx_ctl1; /* 0x10 */
7052 + u32 tx_ins; /* 0x14 */
7053 + u32 tx_pl0; /* 0x18 */
7054 + u32 tx_pl1; /* 0x1c */
7055 + u32 tx_sta; /* 0x20 */
7056 + u32 tx_io_data; /* 0x24 */
7057 + u32 tx_io_data1;/* 0x28 */
7058 + u32 tx_tsvl0; /* 0x2c */
7059 + u32 tx_tsvh0; /* 0x30 */
7060 + u32 tx_tsvl1; /* 0x34 */
7061 + u32 tx_tsvh1; /* 0x38 */
7062 + u32 rx_ctl; /* 0x3c */
7063 + u32 rx_hash0; /* 0x40 */
7064 + u32 rx_hash1; /* 0x44 */
7065 + u32 rx_sta; /* 0x48 */
7066 + u32 rx_io_data; /* 0x4c */
7067 + u32 rx_fbc; /* 0x50 */
7068 + u32 int_ctl; /* 0x54 */
7069 + u32 int_sta; /* 0x58 */
7070 + u32 mac_ctl0; /* 0x5c */
7071 + u32 mac_ctl1; /* 0x60 */
7072 + u32 mac_ipgt; /* 0x64 */
7073 + u32 mac_ipgr; /* 0x68 */
7074 + u32 mac_clrt; /* 0x6c */
7075 + u32 mac_maxf; /* 0x70 */
7076 + u32 mac_supp; /* 0x74 */
7077 + u32 mac_test; /* 0x78 */
7078 + u32 mac_mcfg; /* 0x7c */
7079 + u32 mac_mcmd; /* 0x80 */
7080 + u32 mac_madr; /* 0x84 */
7081 + u32 mac_mwtd; /* 0x88 */
7082 + u32 mac_mrdd; /* 0x8c */
7083 + u32 mac_mind; /* 0x90 */
7084 + u32 mac_ssrr; /* 0x94 */
7085 + u32 mac_a0; /* 0x98 */
7086 + u32 mac_a1; /* 0x9c */
7087 +};
7088 +
7089 +/* SRAMC register */
7090 +struct sunxi_sramc_regs {
7091 + u32 ctrl0;
7092 + u32 ctrl1;
7093 +};
7094 +
7095 +/* 0: Disable 1: Aborted frame enable(default) */
7096 +#define EMAC_TX_AB_M (0x1 << 0)
7097 +/* 0: CPU 1: DMA(default) */
7098 +#define EMAC_TX_TM (0x1 << 1)
7099 +
7100 +#define EMAC_TX_SETUP (0)
7101 +
7102 +/* 0: DRQ asserted 1: DRQ automatically(default) */
7103 +#define EMAC_RX_DRQ_MODE (0x1 << 1)
7104 +/* 0: CPU 1: DMA(default) */
7105 +#define EMAC_RX_TM (0x1 << 2)
7106 +/* 0: Normal(default) 1: Pass all Frames */
7107 +#define EMAC_RX_PA (0x1 << 4)
7108 +/* 0: Normal(default) 1: Pass Control Frames */
7109 +#define EMAC_RX_PCF (0x1 << 5)
7110 +/* 0: Normal(default) 1: Pass Frames with CRC Error */
7111 +#define EMAC_RX_PCRCE (0x1 << 6)
7112 +/* 0: Normal(default) 1: Pass Frames with Length Error */
7113 +#define EMAC_RX_PLE (0x1 << 7)
7114 +/* 0: Normal 1: Pass Frames length out of range(default) */
7115 +#define EMAC_RX_POR (0x1 << 8)
7116 +/* 0: Not accept 1: Accept unicast Packets(default) */
7117 +#define EMAC_RX_UCAD (0x1 << 16)
7118 +/* 0: Normal(default) 1: DA Filtering */
7119 +#define EMAC_RX_DAF (0x1 << 17)
7120 +/* 0: Not accept 1: Accept multicast Packets(default) */
7121 +#define EMAC_RX_MCO (0x1 << 20)
7122 +/* 0: Disable(default) 1: Enable Hash filter */
7123 +#define EMAC_RX_MHF (0x1 << 21)
7124 +/* 0: Not accept 1: Accept Broadcast Packets(default) */
7125 +#define EMAC_RX_BCO (0x1 << 22)
7126 +/* 0: Disable(default) 1: Enable SA Filtering */
7127 +#define EMAC_RX_SAF (0x1 << 24)
7128 +/* 0: Normal(default) 1: Inverse Filtering */
7129 +#define EMAC_RX_SAIF (0x1 << 25)
7130 +
7131 +#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
7132 + EMAC_RX_MCO | EMAC_RX_BCO)
7133 +
7134 +/* 0: Disable 1: Enable Receive Flow Control(default) */
7135 +#define EMAC_MAC_CTL0_RFC (0x1 << 2)
7136 +/* 0: Disable 1: Enable Transmit Flow Control(default) */
7137 +#define EMAC_MAC_CTL0_TFC (0x1 << 3)
7138 +
7139 +#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
7140 +
7141 +/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
7142 +#define EMAC_MAC_CTL1_FLC (0x1 << 1)
7143 +/* 0: Disable(default) 1: Enable Huge Frame */
7144 +#define EMAC_MAC_CTL1_HF (0x1 << 2)
7145 +/* 0: Disable(default) 1: Enable MAC Delayed CRC */
7146 +#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
7147 +/* 0: Disable 1: Enable MAC CRC(default) */
7148 +#define EMAC_MAC_CTL1_CRC (0x1 << 4)
7149 +/* 0: Disable 1: Enable MAC PAD Short frames(default) */
7150 +#define EMAC_MAC_CTL1_PC (0x1 << 5)
7151 +/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
7152 +#define EMAC_MAC_CTL1_VC (0x1 << 6)
7153 +/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
7154 +#define EMAC_MAC_CTL1_ADP (0x1 << 7)
7155 +/* 0: Disable(default) 1: Enable */
7156 +#define EMAC_MAC_CTL1_PRE (0x1 << 8)
7157 +/* 0: Disable(default) 1: Enable */
7158 +#define EMAC_MAC_CTL1_LPE (0x1 << 9)
7159 +/* 0: Disable(default) 1: Enable no back off */
7160 +#define EMAC_MAC_CTL1_NB (0x1 << 12)
7161 +/* 0: Disable(default) 1: Enable */
7162 +#define EMAC_MAC_CTL1_BNB (0x1 << 13)
7163 +/* 0: Disable(default) 1: Enable */
7164 +#define EMAC_MAC_CTL1_ED (0x1 << 14)
7165 +
7166 +#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
7167 + EMAC_MAC_CTL1_PC)
7168 +
7169 +#define EMAC_MAC_IPGT 0x15
7170 +
7171 +#define EMAC_MAC_NBTB_IPG1 0xc
7172 +#define EMAC_MAC_NBTB_IPG2 0x12
7173 +
7174 +#define EMAC_MAC_CW 0x37
7175 +#define EMAC_MAC_RM 0xf
7176 +
7177 +#define EMAC_MAC_MFL 0x0600
7178 +
7179 +/* Receive status */
7180 +#define EMAC_CRCERR (0x1 << 4)
7181 +#define EMAC_LENERR (0x3 << 5)
7182 +
7183 +#define DMA_CPU_TRRESHOLD 2000
7184 +
7185 +struct emac_eth_dev {
7186 + u32 speed;
7187 + u32 duplex;
7188 + u32 phy_configured;
7189 + int link_printed;
7190 +};
7191 +
7192 +struct emac_rxhdr {
7193 + s16 rx_len;
7194 + u16 rx_status;
7195 +};
7196 +
7197 +static void emac_inblk_32bit(void *reg, void *data, int count)
7198 +{
7199 + int cnt = (count + 3) >> 2;
7200 +
7201 + if (cnt) {
7202 + u32 *buf = data;
7203 +
7204 + do {
7205 + u32 x = readl(reg);
7206 + *buf++ = x;
7207 + } while (--cnt);
7208 + }
7209 +}
7210 +
7211 +static void emac_outblk_32bit(void *reg, void *data, int count)
7212 +{
7213 + int cnt = (count + 3) >> 2;
7214 +
7215 + if (cnt) {
7216 + const u32 *buf = data;
7217 +
7218 + do {
7219 + writel(*buf++, reg);
7220 + } while (--cnt);
7221 + }
7222 +}
7223 +
7224 +/* Read a word from phyxcer */
7225 +static int emac_phy_read(const char *devname, unsigned char addr,
7226 + unsigned char reg, unsigned short *value)
7227 +{
7228 + struct eth_device *dev = eth_get_dev_by_name(devname);
7229 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7230 +
7231 + /* issue the phy address and reg */
7232 + writel(addr << 8 | reg, &regs->mac_madr);
7233 +
7234 + /* pull up the phy io line */
7235 + writel(0x1, &regs->mac_mcmd);
7236 +
7237 + /* Wait read complete */
7238 + mdelay(1);
7239 +
7240 + /* push down the phy io line */
7241 + writel(0x0, &regs->mac_mcmd);
7242 +
7243 + /* and write data */
7244 + *value = readl(&regs->mac_mrdd);
7245 +
7246 + return 0;
7247 +}
7248 +
7249 +/* Write a word to phyxcer */
7250 +static int emac_phy_write(const char *devname, unsigned char addr,
7251 + unsigned char reg, unsigned short value)
7252 +{
7253 + struct eth_device *dev = eth_get_dev_by_name(devname);
7254 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7255 +
7256 + /* issue the phy address and reg */
7257 + writel(addr << 8 | reg, &regs->mac_madr);
7258 +
7259 + /* pull up the phy io line */
7260 + writel(0x1, &regs->mac_mcmd);
7261 +
7262 + /* Wait write complete */
7263 + mdelay(1);
7264 +
7265 + /* push down the phy io line */
7266 + writel(0x0, &regs->mac_mcmd);
7267 +
7268 + /* and write data */
7269 + writel(value, &regs->mac_mwtd);
7270 +
7271 + return 0;
7272 +}
7273 +
7274 +static void emac_setup(struct eth_device *dev)
7275 +{
7276 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7277 + u32 reg_val;
7278 + u16 phy_val;
7279 + u32 duplex_flag;
7280 +
7281 + /* Set up TX */
7282 + writel(EMAC_TX_SETUP, &regs->tx_mode);
7283 +
7284 + /* Set up RX */
7285 + writel(EMAC_RX_SETUP, &regs->rx_ctl);
7286 +
7287 + /* Set MAC */
7288 + /* Set MAC CTL0 */
7289 + writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);
7290 +
7291 + /* Set MAC CTL1 */
7292 + emac_phy_read(dev->name, 1, 0, &phy_val);
7293 + debug("PHY SETUP, reg 0 value: %x\n", phy_val);
7294 + duplex_flag = !!(phy_val & (1 << 8));
7295 +
7296 + reg_val = 0;
7297 + if (duplex_flag)
7298 + reg_val = (0x1 << 0);
7299 + writel(EMAC_MAC_CTL1_SETUP | reg_val, &regs->mac_ctl1);
7300 +
7301 + /* Set up IPGT */
7302 + writel(EMAC_MAC_IPGT, &regs->mac_ipgt);
7303 +
7304 + /* Set up IPGR */
7305 + writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);
7306 +
7307 + /* Set up Collison window */
7308 + writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), &regs->mac_clrt);
7309 +
7310 + /* Set up Max Frame Length */
7311 + writel(EMAC_MAC_MFL, &regs->mac_maxf);
7312 +}
7313 +
7314 +static void emac_reset(struct eth_device *dev)
7315 +{
7316 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7317 +
7318 + debug("resetting device\n");
7319 +
7320 + /* RESET device */
7321 + writel(0, &regs->ctl);
7322 + udelay(200);
7323 +
7324 + writel(1, &regs->ctl);
7325 + udelay(200);
7326 +}
7327 +
7328 +static int sunxi_emac_eth_init(struct eth_device *dev, bd_t *bd)
7329 +{
7330 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7331 + struct emac_eth_dev *priv = dev->priv;
7332 + u16 phy_reg;
7333 +
7334 + /* Init EMAC */
7335 +
7336 + /* Flush RX FIFO */
7337 + setbits_le32(&regs->rx_ctl, 0x8);
7338 + udelay(1);
7339 +
7340 + /* Init MAC */
7341 +
7342 + /* Soft reset MAC */
7343 + clrbits_le32(&regs->mac_ctl0, 0x1 << 15);
7344 +
7345 + /* Clear RX counter */
7346 + writel(0x0, &regs->rx_fbc);
7347 + udelay(1);
7348 +
7349 + /* Set up EMAC */
7350 + emac_setup(dev);
7351 +
7352 + writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 |
7353 + dev->enetaddr[2], &regs->mac_a1);
7354 + writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 |
7355 + dev->enetaddr[5], &regs->mac_a0);
7356 +
7357 + mdelay(1);
7358 +
7359 + emac_reset(dev);
7360 +
7361 + /* PHY POWER UP */
7362 + emac_phy_read(dev->name, 1, 0, &phy_reg);
7363 + emac_phy_write(dev->name, 1, 0, phy_reg & (~(0x1 << 11)));
7364 + mdelay(1);
7365 +
7366 + emac_phy_read(dev->name, 1, 0, &phy_reg);
7367 +
7368 + priv->speed = miiphy_speed(dev->name, 0);
7369 + priv->duplex = miiphy_duplex(dev->name, 0);
7370 +
7371 + /* Print link status only once */
7372 + if (!priv->link_printed) {
7373 + printf("ENET Speed is %d Mbps - %s duplex connection\n",
7374 + priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
7375 + priv->link_printed = 1;
7376 + }
7377 +
7378 + /* Set EMAC SPEED depend on PHY */
7379 + clrsetbits_le32(&regs->mac_supp, 1 << 8,
7380 + ((phy_reg & (0x1 << 13)) >> 13) << 8);
7381 +
7382 + /* Set duplex depend on phy */
7383 + clrsetbits_le32(&regs->mac_ctl1, 1 << 0,
7384 + ((phy_reg & (0x1 << 8)) >> 8) << 0);
7385 +
7386 + /* Enable RX/TX */
7387 + setbits_le32(&regs->ctl, 0x7);
7388 +
7389 + return 0;
7390 +}
7391 +
7392 +static void sunxi_emac_eth_halt(struct eth_device *dev)
7393 +{
7394 + /* Nothing to do here */
7395 +}
7396 +
7397 +static int sunxi_emac_eth_recv(struct eth_device *dev)
7398 +{
7399 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7400 + struct emac_rxhdr rxhdr;
7401 + u32 rxcount;
7402 + u32 reg_val;
7403 + int rx_len;
7404 + int rx_status;
7405 + int good_packet;
7406 +
7407 + /* Check packet ready or not */
7408 +
7409 + /* Race warning: The first packet might arrive with
7410 + * the interrupts disabled, but the second will fix
7411 + */
7412 + rxcount = readl(&regs->rx_fbc);
7413 + if (!rxcount) {
7414 + /* Had one stuck? */
7415 + rxcount = readl(&regs->rx_fbc);
7416 + if (!rxcount)
7417 + return 0;
7418 + }
7419 +
7420 + reg_val = readl(&regs->rx_io_data);
7421 + if (reg_val != 0x0143414d) {
7422 + /* Disable RX */
7423 + clrbits_le32(&regs->ctl, 0x1 << 2);
7424 +
7425 + /* Flush RX FIFO */
7426 + setbits_le32(&regs->rx_ctl, 0x1 << 3);
7427 + while (readl(&regs->rx_ctl) & (0x1 << 3))
7428 + ;
7429 +
7430 + /* Enable RX */
7431 + setbits_le32(&regs->ctl, 0x1 << 2);
7432 +
7433 + return 0;
7434 + }
7435 +
7436 + /* A packet ready now
7437 + * Get status/length
7438 + */
7439 + good_packet = 1;
7440 +
7441 + emac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
7442 +
7443 + rx_len = rxhdr.rx_len;
7444 + rx_status = rxhdr.rx_status;
7445 +
7446 + /* Packet Status check */
7447 + if (rx_len < 0x40) {
7448 + good_packet = 0;
7449 + debug("RX: Bad Packet (runt)\n");
7450 + }
7451 +
7452 + /* rx_status is identical to RSR register. */
7453 + if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
7454 + good_packet = 0;
7455 + if (rx_status & EMAC_CRCERR)
7456 + printf("crc error\n");
7457 + if (rx_status & EMAC_LENERR)
7458 + printf("length error\n");
7459 + }
7460 +
7461 + /* Move data from EMAC */
7462 + if (good_packet) {
7463 + if (rx_len > DMA_CPU_TRRESHOLD) {
7464 + printf("Received packet is too big (len=%d)\n", rx_len);
7465 + } else {
7466 + emac_inblk_32bit((void *)&regs->rx_io_data,
7467 + NetRxPackets[0], rx_len);
7468 +
7469 + /* Pass to upper layer */
7470 + NetReceive(NetRxPackets[0], rx_len);
7471 + return rx_len;
7472 + }
7473 + }
7474 +
7475 + return 0;
7476 +}
7477 +
7478 +static int sunxi_emac_eth_send(struct eth_device *dev, void *packet, int len)
7479 +{
7480 + struct emac_regs *regs = (struct emac_regs *)dev->iobase;
7481 +
7482 + /* Select channel 0 */
7483 + writel(0, &regs->tx_ins);
7484 +
7485 + /* Write packet */
7486 + emac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
7487 +
7488 + /* Set TX len */
7489 + writel(len, &regs->tx_pl0);
7490 +
7491 + /* Start translate from fifo to phy */
7492 + setbits_le32(&regs->tx_ctl0, 1);
7493 +
7494 + return 0;
7495 +}
7496 +
7497 +int sunxi_emac_initialize(void)
7498 +{
7499 + struct sunxi_ccm_reg *const ccm =
7500 + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
7501 + struct sunxi_sramc_regs *sram =
7502 + (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
7503 + struct emac_regs *regs =
7504 + (struct emac_regs *)SUNXI_EMAC_BASE;
7505 + struct eth_device *dev;
7506 + struct emac_eth_dev *priv;
7507 + int pin;
7508 +
7509 + dev = malloc(sizeof(*dev));
7510 + if (dev == NULL)
7511 + return -ENOMEM;
7512 +
7513 + priv = (struct emac_eth_dev *)malloc(sizeof(struct emac_eth_dev));
7514 + if (!priv) {
7515 + free(dev);
7516 + return -ENOMEM;
7517 + }
7518 +
7519 + memset(dev, 0, sizeof(*dev));
7520 + memset(priv, 0, sizeof(struct emac_eth_dev));
7521 +
7522 + /* Map SRAM to EMAC */
7523 + setbits_le32(&sram->ctrl1, 0x5 << 2);
7524 +
7525 + /* Configure pin mux settings for MII Ethernet */
7526 + for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
7527 + sunxi_gpio_set_cfgpin(pin, SUNXI_GPA0_EMAC);
7528 +
7529 + /* Set up clock gating */
7530 + setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
7531 +
7532 + /* Set MII clock */
7533 + clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
7534 +
7535 + dev->iobase = (int)regs;
7536 + dev->priv = priv;
7537 + dev->init = sunxi_emac_eth_init;
7538 + dev->halt = sunxi_emac_eth_halt;
7539 + dev->send = sunxi_emac_eth_send;
7540 + dev->recv = sunxi_emac_eth_recv;
7541 + strcpy(dev->name, "emac");
7542 +
7543 + eth_register(dev);
7544 +
7545 + miiphy_register(dev->name, emac_phy_read, emac_phy_write);
7546 +
7547 + return 0;
7548 +}
7549 diff -ruN u-boot-2014.04/drivers/net/sunxi_wemac.c u-boot-sunxi/drivers/net/sunxi_wemac.c
7550 --- u-boot-2014.04/drivers/net/sunxi_wemac.c 2014-04-14 21:19:24.000000000 +0200
7551 +++ u-boot-sunxi/drivers/net/sunxi_wemac.c 1970-01-01 01:00:00.000000000 +0100
7552 @@ -1,525 +0,0 @@
7553 -/*
7554 - * sunxi_wemac.c -- Allwinner A10 ethernet driver
7555 - *
7556 - * (C) Copyright 2012, Stefan Roese <sr@denx.de>
7557 - *
7558 - * SPDX-License-Identifier: GPL-2.0+
7559 - */
7560 -
7561 -#include <common.h>
7562 -#include <malloc.h>
7563 -#include <net.h>
7564 -#include <miiphy.h>
7565 -#include <linux/err.h>
7566 -#include <asm/io.h>
7567 -#include <asm/arch/clock.h>
7568 -#include <asm/arch/gpio.h>
7569 -
7570 -/* EMAC register */
7571 -struct wemac_regs {
7572 - u32 ctl; /* 0x00 */
7573 - u32 tx_mode; /* 0x04 */
7574 - u32 tx_flow; /* 0x08 */
7575 - u32 tx_ctl0; /* 0x0c */
7576 - u32 tx_ctl1; /* 0x10 */
7577 - u32 tx_ins; /* 0x14 */
7578 - u32 tx_pl0; /* 0x18 */
7579 - u32 tx_pl1; /* 0x1c */
7580 - u32 tx_sta; /* 0x20 */
7581 - u32 tx_io_data; /* 0x24 */
7582 - u32 tx_io_data1; /* 0x28 */
7583 - u32 tx_tsvl0; /* 0x2c */
7584 - u32 tx_tsvh0; /* 0x30 */
7585 - u32 tx_tsvl1; /* 0x34 */
7586 - u32 tx_tsvh1; /* 0x38 */
7587 - u32 rx_ctl; /* 0x3c */
7588 - u32 rx_hash0; /* 0x40 */
7589 - u32 rx_hash1; /* 0x44 */
7590 - u32 rx_sta; /* 0x48 */
7591 - u32 rx_io_data; /* 0x4c */
7592 - u32 rx_fbc; /* 0x50 */
7593 - u32 int_ctl; /* 0x54 */
7594 - u32 int_sta; /* 0x58 */
7595 - u32 mac_ctl0; /* 0x5c */
7596 - u32 mac_ctl1; /* 0x60 */
7597 - u32 mac_ipgt; /* 0x64 */
7598 - u32 mac_ipgr; /* 0x68 */
7599 - u32 mac_clrt; /* 0x6c */
7600 - u32 mac_maxf; /* 0x70 */
7601 - u32 mac_supp; /* 0x74 */
7602 - u32 mac_test; /* 0x78 */
7603 - u32 mac_mcfg; /* 0x7c */
7604 - u32 mac_mcmd; /* 0x80 */
7605 - u32 mac_madr; /* 0x84 */
7606 - u32 mac_mwtd; /* 0x88 */
7607 - u32 mac_mrdd; /* 0x8c */
7608 - u32 mac_mind; /* 0x90 */
7609 - u32 mac_ssrr; /* 0x94 */
7610 - u32 mac_a0; /* 0x98 */
7611 - u32 mac_a1; /* 0x9c */
7612 -};
7613 -
7614 -/* SRAMC register */
7615 -struct sunxi_sramc_regs {
7616 - u32 ctrl0;
7617 - u32 ctrl1;
7618 -};
7619 -
7620 -/* 0: Disable 1: Aborted frame enable(default) */
7621 -#define EMAC_TX_AB_M (0x1 << 0)
7622 -/* 0: CPU 1: DMA(default) */
7623 -#define EMAC_TX_TM (0x1 << 1)
7624 -
7625 -#define EMAC_TX_SETUP (0)
7626 -
7627 -/* 0: DRQ asserted 1: DRQ automatically(default) */
7628 -#define EMAC_RX_DRQ_MODE (0x1 << 1)
7629 -/* 0: CPU 1: DMA(default) */
7630 -#define EMAC_RX_TM (0x1 << 2)
7631 -/* 0: Normal(default) 1: Pass all Frames */
7632 -#define EMAC_RX_PA (0x1 << 4)
7633 -/* 0: Normal(default) 1: Pass Control Frames */
7634 -#define EMAC_RX_PCF (0x1 << 5)
7635 -/* 0: Normal(default) 1: Pass Frames with CRC Error */
7636 -#define EMAC_RX_PCRCE (0x1 << 6)
7637 -/* 0: Normal(default) 1: Pass Frames with Length Error */
7638 -#define EMAC_RX_PLE (0x1 << 7)
7639 -/* 0: Normal 1: Pass Frames length out of range(default) */
7640 -#define EMAC_RX_POR (0x1 << 8)
7641 -/* 0: Not accept 1: Accept unicast Packets(default) */
7642 -#define EMAC_RX_UCAD (0x1 << 16)
7643 -/* 0: Normal(default) 1: DA Filtering */
7644 -#define EMAC_RX_DAF (0x1 << 17)
7645 -/* 0: Not accept 1: Accept multicast Packets(default) */
7646 -#define EMAC_RX_MCO (0x1 << 20)
7647 -/* 0: Disable(default) 1: Enable Hash filter */
7648 -#define EMAC_RX_MHF (0x1 << 21)
7649 -/* 0: Not accept 1: Accept Broadcast Packets(default) */
7650 -#define EMAC_RX_BCO (0x1 << 22)
7651 -/* 0: Disable(default) 1: Enable SA Filtering */
7652 -#define EMAC_RX_SAF (0x1 << 24)
7653 -/* 0: Normal(default) 1: Inverse Filtering */
7654 -#define EMAC_RX_SAIF (0x1 << 25)
7655 -
7656 -#define EMAC_RX_SETUP (EMAC_RX_POR | EMAC_RX_UCAD | EMAC_RX_DAF | \
7657 - EMAC_RX_MCO | EMAC_RX_BCO)
7658 -
7659 -/* 0: Disable 1: Enable Receive Flow Control(default) */
7660 -#define EMAC_MAC_CTL0_RFC (0x1 << 2)
7661 -/* 0: Disable 1: Enable Transmit Flow Control(default) */
7662 -#define EMAC_MAC_CTL0_TFC (0x1 << 3)
7663 -
7664 -#define EMAC_MAC_CTL0_SETUP (EMAC_MAC_CTL0_RFC | EMAC_MAC_CTL0_TFC)
7665 -
7666 -/* 0: Disable 1: Enable MAC Frame Length Checking(default) */
7667 -#define EMAC_MAC_CTL1_FLC (0x1 << 1)
7668 -/* 0: Disable(default) 1: Enable Huge Frame */
7669 -#define EMAC_MAC_CTL1_HF (0x1 << 2)
7670 -/* 0: Disable(default) 1: Enable MAC Delayed CRC */
7671 -#define EMAC_MAC_CTL1_DCRC (0x1 << 3)
7672 -/* 0: Disable 1: Enable MAC CRC(default) */
7673 -#define EMAC_MAC_CTL1_CRC (0x1 << 4)
7674 -/* 0: Disable 1: Enable MAC PAD Short frames(default) */
7675 -#define EMAC_MAC_CTL1_PC (0x1 << 5)
7676 -/* 0: Disable(default) 1: Enable MAC PAD Short frames and append CRC */
7677 -#define EMAC_MAC_CTL1_VC (0x1 << 6)
7678 -/* 0: Disable(default) 1: Enable MAC auto detect Short frames */
7679 -#define EMAC_MAC_CTL1_ADP (0x1 << 7)
7680 -/* 0: Disable(default) 1: Enable */
7681 -#define EMAC_MAC_CTL1_PRE (0x1 << 8)
7682 -/* 0: Disable(default) 1: Enable */
7683 -#define EMAC_MAC_CTL1_LPE (0x1 << 9)
7684 -/* 0: Disable(default) 1: Enable no back off */
7685 -#define EMAC_MAC_CTL1_NB (0x1 << 12)
7686 -/* 0: Disable(default) 1: Enable */
7687 -#define EMAC_MAC_CTL1_BNB (0x1 << 13)
7688 -/* 0: Disable(default) 1: Enable */
7689 -#define EMAC_MAC_CTL1_ED (0x1 << 14)
7690 -
7691 -#define EMAC_MAC_CTL1_SETUP (EMAC_MAC_CTL1_FLC | EMAC_MAC_CTL1_CRC | \
7692 - EMAC_MAC_CTL1_PC)
7693 -
7694 -#define EMAC_MAC_IPGT 0x15
7695 -
7696 -#define EMAC_MAC_NBTB_IPG1 0xC
7697 -#define EMAC_MAC_NBTB_IPG2 0x12
7698 -
7699 -#define EMAC_MAC_CW 0x37
7700 -#define EMAC_MAC_RM 0xF
7701 -
7702 -#define EMAC_MAC_MFL 0x0600
7703 -
7704 -/* Receive status */
7705 -#define EMAC_CRCERR (1 << 4)
7706 -#define EMAC_LENERR (3 << 5)
7707 -
7708 -#define DMA_CPU_TRRESHOLD 2000
7709 -
7710 -struct wemac_eth_dev {
7711 - u32 speed;
7712 - u32 duplex;
7713 - u32 phy_configured;
7714 - int link_printed;
7715 -};
7716 -
7717 -struct wemac_rxhdr {
7718 - s16 rx_len;
7719 - u16 rx_status;
7720 -};
7721 -
7722 -static void wemac_inblk_32bit(void *reg, void *data, int count)
7723 -{
7724 - int cnt = (count + 3) >> 2;
7725 -
7726 - if (cnt) {
7727 - u32 *buf = data;
7728 -
7729 - do {
7730 - u32 x = readl(reg);
7731 - *buf++ = x;
7732 - } while (--cnt);
7733 - }
7734 -}
7735 -
7736 -static void wemac_outblk_32bit(void *reg, void *data, int count)
7737 -{
7738 - int cnt = (count + 3) >> 2;
7739 -
7740 - if (cnt) {
7741 - const u32 *buf = data;
7742 -
7743 - do {
7744 - writel(*buf++, reg);
7745 - } while (--cnt);
7746 - }
7747 -}
7748 -
7749 -/*
7750 - * Read a word from phyxcer
7751 - */
7752 -static int wemac_phy_read(const char *devname, unsigned char addr,
7753 - unsigned char reg, unsigned short *value)
7754 -{
7755 - struct eth_device *dev = eth_get_dev_by_name(devname);
7756 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
7757 -
7758 - /* issue the phy address and reg */
7759 - writel(addr << 8 | reg, &regs->mac_madr);
7760 -
7761 - /* pull up the phy io line */
7762 - writel(0x1, &regs->mac_mcmd);
7763 -
7764 - /* Wait read complete */
7765 - mdelay(1);
7766 -
7767 - /* push down the phy io line */
7768 - writel(0x0, &regs->mac_mcmd);
7769 -
7770 - /* and write data */
7771 - *value = readl(&regs->mac_mrdd);
7772 -
7773 - return 0;
7774 -}
7775 -
7776 -/*
7777 - * Write a word to phyxcer
7778 - */
7779 -static int wemac_phy_write(const char *devname, unsigned char addr,
7780 - unsigned char reg, unsigned short value)
7781 -{
7782 - struct eth_device *dev = eth_get_dev_by_name(devname);
7783 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
7784 -
7785 - /* issue the phy address and reg */
7786 - writel(addr << 8 | reg, &regs->mac_madr);
7787 -
7788 - /* pull up the phy io line */
7789 - writel(0x1, &regs->mac_mcmd);
7790 -
7791 - /* Wait write complete */
7792 - mdelay(1);
7793 -
7794 - /* push down the phy io line */
7795 - writel(0x0, &regs->mac_mcmd);
7796 -
7797 - /* and write data */
7798 - writel(value, &regs->mac_mwtd);
7799 -
7800 - return 0;
7801 -}
7802 -
7803 -static void emac_setup(struct eth_device *dev)
7804 -{
7805 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
7806 - u32 reg_val;
7807 - u16 phy_val;
7808 - u32 duplex_flag;
7809 -
7810 - /* Set up TX */
7811 - writel(EMAC_TX_SETUP, &regs->tx_mode);
7812 -
7813 - /* Set up RX */
7814 - writel(EMAC_RX_SETUP, &regs->rx_ctl);
7815 -
7816 - /* Set MAC */
7817 - /* Set MAC CTL0 */
7818 - writel(EMAC_MAC_CTL0_SETUP, &regs->mac_ctl0);
7819 -
7820 - /* Set MAC CTL1 */
7821 - wemac_phy_read(dev->name, 1, 0, &phy_val);
7822 - debug("PHY SETUP, reg 0 value: %x\n", phy_val);
7823 - duplex_flag = !!(phy_val & (1 << 8));
7824 -
7825 - reg_val = 0;
7826 - if (duplex_flag)
7827 - reg_val = (0x1 << 0);
7828 - writel(EMAC_MAC_CTL1_SETUP | reg_val, &regs->mac_ctl1);
7829 -
7830 - /* Set up IPGT */
7831 - writel(EMAC_MAC_IPGT, &regs->mac_ipgt);
7832 -
7833 - /* Set up IPGR */
7834 - writel(EMAC_MAC_NBTB_IPG2 | (EMAC_MAC_NBTB_IPG1 << 8), &regs->mac_ipgr);
7835 -
7836 - /* Set up Collison window */
7837 - writel(EMAC_MAC_RM | (EMAC_MAC_CW << 8), &regs->mac_clrt);
7838 -
7839 - /* Set up Max Frame Length */
7840 - writel(EMAC_MAC_MFL, &regs->mac_maxf);
7841 -}
7842 -
7843 -static void wemac_reset(struct eth_device *dev)
7844 -{
7845 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
7846 -
7847 - debug("resetting device\n");
7848 -
7849 - /* RESET device */
7850 - writel(0, &regs->ctl);
7851 - udelay(200);
7852 -
7853 - writel(1, &regs->ctl);
7854 - udelay(200);
7855 -}
7856 -
7857 -static int sunxi_wemac_eth_init(struct eth_device *dev, bd_t *bd)
7858 -{
7859 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
7860 - struct wemac_eth_dev *priv = dev->priv;
7861 - u16 phy_reg;
7862 -
7863 - /* Init EMAC */
7864 -
7865 - /* Flush RX FIFO */
7866 - setbits_le32(&regs->rx_ctl, 0x8);
7867 - udelay(1);
7868 -
7869 - /* Init MAC */
7870 -
7871 - /* Soft reset MAC */
7872 - clrbits_le32(&regs->mac_ctl0, 1 << 15);
7873 -
7874 - /* Set MII clock */
7875 - clrsetbits_le32(&regs->mac_mcfg, 0xf << 2, 0xd << 2);
7876 -
7877 - /* Clear RX counter */
7878 - writel(0x0, &regs->rx_fbc);
7879 - udelay(1);
7880 -
7881 - /* Set up EMAC */
7882 - emac_setup(dev);
7883 -
7884 - writel(dev->enetaddr[0] << 16 | dev->enetaddr[1] << 8 |
7885 - dev->enetaddr[2], &regs->mac_a1);
7886 - writel(dev->enetaddr[3] << 16 | dev->enetaddr[4] << 8 |
7887 - dev->enetaddr[5], &regs->mac_a0);
7888 -
7889 - mdelay(1);
7890 -
7891 - wemac_reset(dev);
7892 -
7893 - /* PHY POWER UP */
7894 - wemac_phy_read(dev->name, 1, 0, &phy_reg);
7895 - wemac_phy_write(dev->name, 1, 0, phy_reg & (~(1 << 11)));
7896 - mdelay(1);
7897 -
7898 - wemac_phy_read(dev->name, 1, 0, &phy_reg);
7899 -
7900 - priv->speed = miiphy_speed(dev->name, 0);
7901 - priv->duplex = miiphy_duplex(dev->name, 0);
7902 -
7903 - /* Print link status only once */
7904 - if (!priv->link_printed) {
7905 - printf("ENET Speed is %d Mbps - %s duplex connection\n",
7906 - priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL");
7907 - priv->link_printed = 1;
7908 - }
7909 -
7910 - /* Set EMAC SPEED depend on PHY */
7911 - clrsetbits_le32(&regs->mac_supp, 1 << 8,
7912 - ((phy_reg & (1 << 13)) >> 13) << 8);
7913 -
7914 - /* Set duplex depend on phy */
7915 - clrsetbits_le32(&regs->mac_ctl1, 1 << 0,
7916 - ((phy_reg & (1 << 8)) >> 8) << 0);
7917 -
7918 - /* Enable RX/TX */
7919 - setbits_le32(&regs->ctl, 0x7);
7920 -
7921 - return 0;
7922 -}
7923 -
7924 -static void sunxi_wemac_eth_halt(struct eth_device *dev)
7925 -{
7926 - /* Nothing to do here */
7927 -}
7928 -
7929 -static int sunxi_wemac_eth_recv(struct eth_device *dev)
7930 -{
7931 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
7932 - struct wemac_rxhdr rxhdr;
7933 - u32 rxcount;
7934 - u32 reg_val;
7935 - int rx_len;
7936 - int rx_status;
7937 - int good_packet;
7938 -
7939 - /* Check packet ready or not */
7940 -
7941 - /*
7942 - * Race warning: The first packet might arrive with
7943 - * the interrupts disabled, but the second will fix
7944 - */
7945 - rxcount = readl(&regs->rx_fbc);
7946 - if (!rxcount) {
7947 - /* Had one stuck? */
7948 - rxcount = readl(&regs->rx_fbc);
7949 - if (!rxcount)
7950 - return 0;
7951 - }
7952 -
7953 - reg_val = readl(&regs->rx_io_data);
7954 - if (reg_val != 0x0143414d) {
7955 - /* Disable RX */
7956 - clrbits_le32(&regs->ctl, 1 << 2);
7957 -
7958 - /* Flush RX FIFO */
7959 - setbits_le32(&regs->rx_ctl, 1 << 3);
7960 - while (readl(&regs->rx_ctl) & (1 << 3))
7961 - ;
7962 -
7963 - /* Enable RX */
7964 - setbits_le32(&regs->ctl, 1 << 2);
7965 -
7966 - return 0;
7967 - }
7968 -
7969 - /*
7970 - * A packet ready now
7971 - * Get status/length
7972 - */
7973 - good_packet = 1;
7974 -
7975 - wemac_inblk_32bit(&regs->rx_io_data, &rxhdr, sizeof(rxhdr));
7976 -
7977 - rx_len = rxhdr.rx_len;
7978 - rx_status = rxhdr.rx_status;
7979 -
7980 - /* Packet Status check */
7981 - if (rx_len < 0x40) {
7982 - good_packet = 0;
7983 - debug("RX: Bad Packet (runt)\n");
7984 - }
7985 -
7986 - /* rx_status is identical to RSR register. */
7987 - if (0 & rx_status & (EMAC_CRCERR | EMAC_LENERR)) {
7988 - good_packet = 0;
7989 - if (rx_status & EMAC_CRCERR)
7990 - printf("crc error\n");
7991 - if (rx_status & EMAC_LENERR)
7992 - printf("length error\n");
7993 - }
7994 -
7995 - /* Move data from WEMAC */
7996 - if (good_packet) {
7997 - if (rx_len > DMA_CPU_TRRESHOLD) {
7998 - printf("Received packet is too big (len=%d)\n", rx_len);
7999 - } else {
8000 - wemac_inblk_32bit((void *)&regs->rx_io_data,
8001 - NetRxPackets[0], rx_len);
8002 -
8003 - /* Pass to upper layer */
8004 - NetReceive(NetRxPackets[0], rx_len);
8005 - return rx_len;
8006 - }
8007 - }
8008 -
8009 - return 0;
8010 -}
8011 -
8012 -static int sunxi_wemac_eth_send(struct eth_device *dev, void *packet, int len)
8013 -{
8014 - struct wemac_regs *regs = (struct wemac_regs *)dev->iobase;
8015 -
8016 - /* Select channel 0 */
8017 - writel(0, &regs->tx_ins);
8018 -
8019 - /* Write packet */
8020 - wemac_outblk_32bit((void *)&regs->tx_io_data, packet, len);
8021 -
8022 - /* Set TX len */
8023 - writel(len, &regs->tx_pl0);
8024 -
8025 - /* Start translate from fifo to phy */
8026 - setbits_le32(&regs->tx_ctl0, 1);
8027 -
8028 - return 0;
8029 -}
8030 -
8031 -int sunxi_wemac_initialize(void)
8032 -{
8033 - struct sunxi_ccm_reg *const ccm =
8034 - (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
8035 - struct sunxi_sramc_regs *sram =
8036 - (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
8037 - struct eth_device *dev;
8038 - struct wemac_eth_dev *priv;
8039 - int pin;
8040 -
8041 - dev = malloc(sizeof(*dev));
8042 - if (dev == NULL)
8043 - return -ENOMEM;
8044 -
8045 - priv = (struct wemac_eth_dev *)malloc(sizeof(struct wemac_eth_dev));
8046 - if (!priv) {
8047 - free(dev);
8048 - return -ENOMEM;
8049 - }
8050 -
8051 - memset(dev, 0, sizeof(*dev));
8052 - memset(priv, 0, sizeof(struct wemac_eth_dev));
8053 -
8054 - /* Map SRAM to EMAC */
8055 - setbits_le32(&sram->ctrl1, 0x5 << 2);
8056 -
8057 - /* Configure pin mux settings for MII Ethernet */
8058 - for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++)
8059 - sunxi_gpio_set_cfgpin(pin, 2);
8060 -
8061 - /* Set up clock gating */
8062 - setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_EMAC);
8063 -
8064 - dev->iobase = SUNXI_EMAC_BASE;
8065 - dev->priv = priv;
8066 - dev->init = sunxi_wemac_eth_init;
8067 - dev->halt = sunxi_wemac_eth_halt;
8068 - dev->send = sunxi_wemac_eth_send;
8069 - dev->recv = sunxi_wemac_eth_recv;
8070 - strcpy(dev->name, "wemac");
8071 -
8072 - eth_register(dev);
8073 -
8074 - miiphy_register(dev->name, wemac_phy_read, wemac_phy_write);
8075 -
8076 - return 0;
8077 -}
8078 diff -ruN u-boot-2014.04/drivers/power/axp152.c u-boot-sunxi/drivers/power/axp152.c
8079 --- u-boot-2014.04/drivers/power/axp152.c 1970-01-01 01:00:00.000000000 +0100
8080 +++ u-boot-sunxi/drivers/power/axp152.c 2014-09-06 16:58:36.321953111 +0200
8081 @@ -0,0 +1,112 @@
8082 +/*
8083 + * (C) Copyright 2012
8084 + * Henrik Nordstrom <henrik@henriknordstrom.net>
8085 + *
8086 + * SPDX-License-Identifier: GPL-2.0+
8087 + */
8088 +#include <common.h>
8089 +#include <i2c.h>
8090 +#include <axp152.h>
8091 +
8092 +enum axp152_reg {
8093 + AXP152_CHIP_VERSION = 0x3,
8094 + AXP152_DCDC2_VOLTAGE = 0x23,
8095 + AXP152_DCDC3_VOLTAGE = 0x27,
8096 + AXP152_DCDC4_VOLTAGE = 0x2B,
8097 + AXP152_LDO2_VOLTAGE = 0x2A,
8098 + AXP152_SHUTDOWN = 0x32,
8099 +};
8100 +
8101 +#define AXP152_POWEROFF (1 << 7)
8102 +
8103 +static int axp152_write(enum axp152_reg reg, u8 val)
8104 +{
8105 + return i2c_write(0x30, reg, 1, &val, 1);
8106 +}
8107 +
8108 +static int axp152_read(enum axp152_reg reg, u8 *val)
8109 +{
8110 + return i2c_read(0x30, reg, 1, val, 1);
8111 +}
8112 +
8113 +static int axp152_mvolt_to_target(int mvolt, int min, int max, int div)
8114 +{
8115 + if (mvolt < min)
8116 + mvolt = min;
8117 + else if (mvolt > max)
8118 + mvolt = max;
8119 +
8120 + return (mvolt - min) / div;
8121 +}
8122 +
8123 +int axp152_set_dcdc2(int mvolt)
8124 +{
8125 + int rc, target;
8126 + u8 current;
8127 +
8128 + target = axp152_mvolt_to_target(mvolt, 700, 2275, 25);
8129 +
8130 + /* Do we really need to be this gentle? It has built-in voltage slope */
8131 + while ((rc = axp152_read(AXP152_DCDC2_VOLTAGE, &current)) == 0 &&
8132 + current != target) {
8133 + if (current < target)
8134 + current++;
8135 + else
8136 + current--;
8137 + rc = axp152_write(AXP152_DCDC2_VOLTAGE, current);
8138 + if (rc)
8139 + break;
8140 + }
8141 + return rc;
8142 +}
8143 +
8144 +int axp152_set_dcdc3(int mvolt)
8145 +{
8146 + int target = axp152_mvolt_to_target(mvolt, 700, 3500, 25);
8147 +
8148 + return axp152_write(AXP152_DCDC3_VOLTAGE, target);
8149 +}
8150 +
8151 +int axp152_set_dcdc4(int mvolt)
8152 +{
8153 + int target = axp152_mvolt_to_target(mvolt, 700, 3500, 25);
8154 +
8155 + return axp152_write(AXP152_DCDC4_VOLTAGE, target);
8156 +}
8157 +
8158 +int axp152_set_ldo2(int mvolt)
8159 +{
8160 + int target = axp152_mvolt_to_target(mvolt, 700, 3500, 100);
8161 +
8162 + return axp152_write(AXP152_LDO2_VOLTAGE, target);
8163 +}
8164 +
8165 +void axp152_poweroff(void)
8166 +{
8167 + u8 val;
8168 +
8169 + if (axp152_read(AXP152_SHUTDOWN, &val) != 0)
8170 + return;
8171 +
8172 + val |= AXP152_POWEROFF;
8173 +
8174 + if (axp152_write(AXP152_SHUTDOWN, val) != 0)
8175 + return;
8176 +
8177 + udelay(10000); /* wait for power to drain */
8178 +}
8179 +
8180 +int axp152_init(void)
8181 +{
8182 + u8 ver;
8183 + int rc;
8184 +
8185 + rc = axp152_read(AXP152_CHIP_VERSION, &ver);
8186 + if (rc)
8187 + return rc;
8188 +
8189 + if (ver != 0x05)
8190 + return -1;
8191 +
8192 + return 0;
8193 +}
8194 diff -ruN u-boot-2014.04/drivers/power/axp209.c u-boot-sunxi/drivers/power/axp209.c
8195 --- u-boot-2014.04/drivers/power/axp209.c 1970-01-01 01:00:00.000000000 +0100
8196 +++ u-boot-sunxi/drivers/power/axp209.c 2014-09-06 16:58:36.321953111 +0200
8197 @@ -0,0 +1,180 @@
8198 +/*
8199 + * (C) Copyright 2012
8200 + * Henrik Nordstrom <henrik@henriknordstrom.net>
8201 + *
8202 + * SPDX-License-Identifier: GPL-2.0+
8203 + */
8204 +
8205 +#include <common.h>
8206 +#include <i2c.h>
8207 +#include <axp209.h>
8208 +
8209 +enum axp209_reg {
8210 + AXP209_POWER_STATUS = 0x00,
8211 + AXP209_CHIP_VERSION = 0x03,
8212 + AXP209_DCDC2_VOLTAGE = 0x23,
8213 + AXP209_DCDC3_VOLTAGE = 0x27,
8214 + AXP209_LDO24_VOLTAGE = 0x28,
8215 + AXP209_LDO3_VOLTAGE = 0x29,
8216 + AXP209_IRQ_STATUS5 = 0x4c,
8217 + AXP209_SHUTDOWN = 0x32,
8218 +};
8219 +
8220 +#define AXP209_POWER_STATUS_ON_BY_DC (1 << 0)
8221 +
8222 +#define AXP209_IRQ5_PEK_UP (1 << 6)
8223 +#define AXP209_IRQ5_PEK_DOWN (1 << 5)
8224 +
8225 +#define AXP209_POWEROFF (1 << 7)
8226 +
8227 +static int axp209_write(enum axp209_reg reg, u8 val)
8228 +{
8229 + return i2c_write(0x34, reg, 1, &val, 1);
8230 +}
8231 +
8232 +static int axp209_read(enum axp209_reg reg, u8 *val)
8233 +{
8234 + return i2c_read(0x34, reg, 1, val, 1);
8235 +}
8236 +
8237 +static int axp209_mvolt_to_cfg(int mvolt, int min, int max, int div)
8238 +{
8239 + if (mvolt < min)
8240 + mvolt = min;
8241 + else if (mvolt > max)
8242 + mvolt = max;
8243 +
8244 + return (mvolt - min) / div;
8245 +}
8246 +
8247 +int axp209_set_dcdc2(int mvolt)
8248 +{
8249 + int cfg, rc;
8250 + u8 current;
8251 +
8252 + cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
8253 +
8254 + /* Do we really need to be this gentle? It has built-in voltage slope */
8255 + while ((rc = axp209_read(AXP209_DCDC2_VOLTAGE, &current)) == 0 &&
8256 + current != cfg) {
8257 + if (current < cfg)
8258 + current++;
8259 + else
8260 + current--;
8261 +
8262 + rc = axp209_write(AXP209_DCDC2_VOLTAGE, current);
8263 + if (rc)
8264 + break;
8265 + }
8266 +
8267 + return rc;
8268 +}
8269 +
8270 +int axp209_set_dcdc3(int mvolt)
8271 +{
8272 + int cfg = axp209_mvolt_to_cfg(mvolt, 700, 3500, 25);
8273 +
8274 + return axp209_write(AXP209_DCDC3_VOLTAGE, cfg);
8275 +}
8276 +
8277 +int axp209_set_ldo2(int mvolt)
8278 +{
8279 + int rc, cfg;
8280 + u8 reg;
8281 +
8282 + cfg = axp209_mvolt_to_cfg(mvolt, 1800, 3300, 100);
8283 +
8284 + rc = axp209_read(AXP209_LDO24_VOLTAGE, &reg);
8285 + if (rc)
8286 + return rc;
8287 +
8288 + /* LDO2 configuration is in upper 4 bits */
8289 + reg = (reg & 0x0f) | (cfg << 4);
8290 + return axp209_write(AXP209_LDO24_VOLTAGE, reg);
8291 +}
8292 +
8293 +int axp209_set_ldo3(int mvolt)
8294 +{
8295 + int cfg = axp209_mvolt_to_cfg(mvolt, 700, 2275, 25);
8296 +
8297 + if (mvolt == -1)
8298 + cfg = 0x80; /* determined by LDO3IN pin */
8299 +
8300 + return axp209_write(AXP209_LDO3_VOLTAGE, cfg);
8301 +}
8302 +
8303 +int axp209_set_ldo4(int mvolt)
8304 +{
8305 + int cfg, rc;
8306 + static const int vindex[] = {
8307 + 1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500,
8308 + 2700, 2800, 3000, 3100, 3200, 3300
8309 + };
8310 + u8 reg;
8311 +
8312 + /* Translate mvolt to register cfg value, requested <= selected */
8313 + for (cfg = 15; vindex[cfg] > mvolt && cfg > 0; cfg--);
8314 +
8315 + rc = axp209_read(AXP209_LDO24_VOLTAGE, &reg);
8316 + if (rc)
8317 + return rc;
8318 +
8319 + /* LDO4 configuration is in lower 4 bits */
8320 + reg = (reg & 0xf0) | (cfg << 0);
8321 + return axp209_write(AXP209_LDO24_VOLTAGE, reg);
8322 +}
8323 +
8324 +void axp209_poweroff(void)
8325 +{
8326 + u8 val;
8327 +
8328 + if (axp209_read(AXP209_SHUTDOWN, &val) != 0)
8329 + return;
8330 +
8331 + val |= AXP209_POWEROFF;
8332 +
8333 + if (axp209_write(AXP209_SHUTDOWN, val) != 0)
8334 + return;
8335 +
8336 + udelay(10000); /* wait for power to drain */
8337 +}
8338 +
8339 +int axp209_init(void)
8340 +{
8341 + u8 ver;
8342 + int rc;
8343 +
8344 + rc = axp209_read(AXP209_CHIP_VERSION, &ver);
8345 + if (rc)
8346 + return rc;
8347 +
8348 + /* Low 4 bits is chip version */
8349 + ver &= 0x0f;
8350 +
8351 + if (ver != 0x1)
8352 + return -1;
8353 +
8354 + return 0;
8355 +}
8356 +
8357 +int axp209_poweron_by_dc(void)
8358 +{
8359 + u8 v;
8360 +
8361 + if (axp209_read(AXP209_POWER_STATUS, &v))
8362 + return 0;
8363 +
8364 + return (v & AXP209_POWER_STATUS_ON_BY_DC);
8365 +}
8366 +
8367 +int axp209_power_button(void)
8368 +{
8369 + u8 v;
8370 +
8371 + if (axp209_read(AXP209_IRQ_STATUS5, &v))
8372 + return 0;
8373 +
8374 + axp209_write(AXP209_IRQ_STATUS5, AXP209_IRQ5_PEK_DOWN);
8375 +
8376 + return v & AXP209_IRQ5_PEK_DOWN;
8377 +}
8378 diff -ruN u-boot-2014.04/drivers/power/axp221.c u-boot-sunxi/drivers/power/axp221.c
8379 --- u-boot-2014.04/drivers/power/axp221.c 1970-01-01 01:00:00.000000000 +0100
8380 +++ u-boot-sunxi/drivers/power/axp221.c 2014-09-06 16:58:36.321953111 +0200
8381 @@ -0,0 +1,73 @@
8382 +/*
8383 + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
8384 + *
8385 + * SPDX-License-Identifier: GPL-2.0+
8386 + */
8387 +
8388 +#include <common.h>
8389 +#include <errno.h>
8390 +#include <asm/arch/p2wi.h>
8391 +#include <axp221.h>
8392 +
8393 +int axp221_set_dcdc1(unsigned int mvolt)
8394 +{
8395 + return p2wi_write(AXP221_DCDC1_CTRL, (mvolt - 1600) / 100);
8396 +}
8397 +
8398 +int axp221_set_dcdc2(unsigned int mvolt)
8399 +{
8400 + return p2wi_write(AXP221_DCDC2_CTRL, (mvolt - 600) / 20);
8401 +}
8402 +
8403 +int axp221_set_dcdc3(unsigned int mvolt)
8404 +{
8405 + return p2wi_write(AXP221_DCDC3_CTRL, (mvolt - 600) / 20);
8406 +}
8407 +
8408 +int axp221_set_dcdc4(unsigned int mvolt)
8409 +{
8410 + return p2wi_write(AXP221_DCDC4_CTRL, (mvolt - 600) / 20);
8411 +}
8412 +
8413 +int axp221_set_dcdc5(unsigned int mvolt)
8414 +{
8415 + return p2wi_write(AXP221_DCDC5_CTRL, (mvolt - 600) / 20);
8416 +}
8417 +
8418 +int axp221_set_dldo1(unsigned int mvolt)
8419 +{
8420 + int ret;
8421 + u8 val;
8422 +
8423 + ret = p2wi_write(AXP221_DLDO1_CTRL, (mvolt - 700) / 100);
8424 + if (ret)
8425 + return ret;
8426 +
8427 + ret = p2wi_read(AXP221_OUTPUT_CTRL2, &val);
8428 + if (ret)
8429 + return ret;
8430 +
8431 + val |= 1 << 3;
8432 + return p2wi_write(AXP221_OUTPUT_CTRL2, val);
8433 +}
8434 +
8435 +int axp221_init(void)
8436 +{
8437 + u8 axp_chip_id;
8438 + int ret;
8439 +
8440 + p2wi_init();
8441 + ret = p2wi_set_pmu_address(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,
8442 + AXP221_INIT_DATA);
8443 + if (ret)
8444 + return ret;
8445 +
8446 + ret = p2wi_read(AXP221_CHIP_ID, &axp_chip_id);
8447 + if (ret)
8448 + return ret;
8449 +
8450 + if (!(axp_chip_id == 0x6 || axp_chip_id == 0x7 || axp_chip_id == 0x17))
8451 + return -ENODEV;
8452 +
8453 + return 0;
8454 +}
8455 diff -ruN u-boot-2014.04/drivers/power/Makefile u-boot-sunxi/drivers/power/Makefile
8456 --- u-boot-2014.04/drivers/power/Makefile 2014-04-14 21:19:24.000000000 +0200
8457 +++ u-boot-sunxi/drivers/power/Makefile 2014-09-06 16:58:36.321953111 +0200
8458 @@ -5,6 +5,9 @@
8459 # SPDX-License-Identifier: GPL-2.0+
8460 #
8461
8462 +obj-$(CONFIG_AXP152_POWER) += axp152.o
8463 +obj-$(CONFIG_AXP209_POWER) += axp209.o
8464 +obj-$(CONFIG_AXP221_POWER) += axp221.o
8465 obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
8466 obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
8467 obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o
8468 diff -ruN u-boot-2014.04/drivers/serial/arm_dcc.c u-boot-sunxi/drivers/serial/arm_dcc.c
8469 --- u-boot-2014.04/drivers/serial/arm_dcc.c 2014-04-14 21:19:24.000000000 +0200
8470 +++ u-boot-sunxi/drivers/serial/arm_dcc.c 2014-09-06 16:58:36.329953111 +0200
8471 @@ -29,7 +29,7 @@
8472 #include <common.h>
8473 #include <serial.h>
8474
8475 -#if defined(CONFIG_CPU_V6)
8476 +#if defined(CONFIG_CPU_V6) || 1
8477 /*
8478 * ARMV6
8479 */
8480 diff -ruN u-boot-2014.04/.git/config u-boot-sunxi/.git/config
8481 --- u-boot-2014.04/.git/config 1970-01-01 01:00:00.000000000 +0100
8482 +++ u-boot-sunxi/.git/config 2014-09-06 16:58:35.001953150 +0200
8483 @@ -0,0 +1,11 @@
8484 +[core]
8485 + repositoryformatversion = 0
8486 + filemode = true
8487 + bare = false
8488 + logallrefupdates = true
8489 +[remote "origin"]
8490 + fetch = +refs/heads/*:refs/remotes/origin/*
8491 + url = https://github.com/linux-sunxi/u-boot-sunxi
8492 +[branch "sunxi"]
8493 + remote = origin
8494 + merge = refs/heads/sunxi
8495 diff -ruN u-boot-2014.04/.git/description u-boot-sunxi/.git/description
8496 --- u-boot-2014.04/.git/description 1970-01-01 01:00:00.000000000 +0100
8497 +++ u-boot-sunxi/.git/description 2014-09-06 16:58:09.553953909 +0200
8498 @@ -0,0 +1 @@
8499 +Unnamed repository; edit this file 'description' to name the repository.
8500 diff -ruN u-boot-2014.04/.git/HEAD u-boot-sunxi/.git/HEAD
8501 --- u-boot-2014.04/.git/HEAD 1970-01-01 01:00:00.000000000 +0100
8502 +++ u-boot-sunxi/.git/HEAD 2014-09-06 16:58:35.001953150 +0200
8503 @@ -0,0 +1 @@
8504 +ref: refs/heads/sunxi
8505 diff -ruN u-boot-2014.04/.git/hooks/applypatch-msg.sample u-boot-sunxi/.git/hooks/applypatch-msg.sample
8506 --- u-boot-2014.04/.git/hooks/applypatch-msg.sample 1970-01-01 01:00:00.000000000 +0100
8507 +++ u-boot-sunxi/.git/hooks/applypatch-msg.sample 2014-09-06 16:58:09.553953909 +0200
8508 @@ -0,0 +1,15 @@
8509 +#!/bin/sh
8510 +#
8511 +# An example hook script to check the commit log message taken by
8512 +# applypatch from an e-mail message.
8513 +#
8514 +# The hook should exit with non-zero status after issuing an
8515 +# appropriate message if it wants to stop the commit. The hook is
8516 +# allowed to edit the commit message file.
8517 +#
8518 +# To enable this hook, rename this file to "applypatch-msg".
8519 +
8520 +. git-sh-setup
8521 +test -x "$GIT_DIR/hooks/commit-msg" &&
8522 + exec "$GIT_DIR/hooks/commit-msg" ${1+"$@"}
8523 +:
8524 diff -ruN u-boot-2014.04/.git/hooks/commit-msg.sample u-boot-sunxi/.git/hooks/commit-msg.sample
8525 --- u-boot-2014.04/.git/hooks/commit-msg.sample 1970-01-01 01:00:00.000000000 +0100
8526 +++ u-boot-sunxi/.git/hooks/commit-msg.sample 2014-09-06 16:58:09.553953909 +0200
8527 @@ -0,0 +1,24 @@
8528 +#!/bin/sh
8529 +#
8530 +# An example hook script to check the commit log message.
8531 +# Called by "git commit" with one argument, the name of the file
8532 +# that has the commit message. The hook should exit with non-zero
8533 +# status after issuing an appropriate message if it wants to stop the
8534 +# commit. The hook is allowed to edit the commit message file.
8535 +#
8536 +# To enable this hook, rename this file to "commit-msg".
8537 +
8538 +# Uncomment the below to add a Signed-off-by line to the message.
8539 +# Doing this in a hook is a bad idea in general, but the prepare-commit-msg
8540 +# hook is more suited to it.
8541 +#
8542 +# SOB=$(git var GIT_AUTHOR_IDENT | sed -n 's/^\(.*>\).*$/Signed-off-by: \1/p')
8543 +# grep -qs "^$SOB" "$1" || echo "$SOB" >> "$1"
8544 +
8545 +# This example catches duplicate Signed-off-by lines.
8546 +
8547 +test "" = "$(grep '^Signed-off-by: ' "$1" |
8548 + sort | uniq -c | sed -e '/^[ ]*1[ ]/d')" || {
8549 + echo >&2 Duplicate Signed-off-by lines.
8550 + exit 1
8551 +}
8552 diff -ruN u-boot-2014.04/.git/hooks/post-update.sample u-boot-sunxi/.git/hooks/post-update.sample
8553 --- u-boot-2014.04/.git/hooks/post-update.sample 1970-01-01 01:00:00.000000000 +0100
8554 +++ u-boot-sunxi/.git/hooks/post-update.sample 2014-09-06 16:58:09.553953909 +0200
8555 @@ -0,0 +1,8 @@
8556 +#!/bin/sh
8557 +#
8558 +# An example hook script to prepare a packed repository for use over
8559 +# dumb transports.
8560 +#
8561 +# To enable this hook, rename this file to "post-update".
8562 +
8563 +exec git update-server-info
8564 diff -ruN u-boot-2014.04/.git/hooks/pre-applypatch.sample u-boot-sunxi/.git/hooks/pre-applypatch.sample
8565 --- u-boot-2014.04/.git/hooks/pre-applypatch.sample 1970-01-01 01:00:00.000000000 +0100
8566 +++ u-boot-sunxi/.git/hooks/pre-applypatch.sample 2014-09-06 16:58:09.553953909 +0200
8567 @@ -0,0 +1,14 @@
8568 +#!/bin/sh
8569 +#
8570 +# An example hook script to verify what is about to be committed
8571 +# by applypatch from an e-mail message.
8572 +#
8573 +# The hook should exit with non-zero status after issuing an
8574 +# appropriate message if it wants to stop the commit.
8575 +#
8576 +# To enable this hook, rename this file to "pre-applypatch".
8577 +
8578 +. git-sh-setup
8579 +test -x "$GIT_DIR/hooks/pre-commit" &&
8580 + exec "$GIT_DIR/hooks/pre-commit" ${1+"$@"}
8581 +:
8582 diff -ruN u-boot-2014.04/.git/hooks/pre-commit.sample u-boot-sunxi/.git/hooks/pre-commit.sample
8583 --- u-boot-2014.04/.git/hooks/pre-commit.sample 1970-01-01 01:00:00.000000000 +0100
8584 +++ u-boot-sunxi/.git/hooks/pre-commit.sample 2014-09-06 16:58:09.553953909 +0200
8585 @@ -0,0 +1,50 @@
8586 +#!/bin/sh
8587 +#
8588 +# An example hook script to verify what is about to be committed.
8589 +# Called by "git commit" with no arguments. The hook should
8590 +# exit with non-zero status after issuing an appropriate message if
8591 +# it wants to stop the commit.
8592 +#
8593 +# To enable this hook, rename this file to "pre-commit".
8594 +
8595 +if git rev-parse --verify HEAD >/dev/null 2>&1
8596 +then
8597 + against=HEAD
8598 +else
8599 + # Initial commit: diff against an empty tree object
8600 + against=4b825dc642cb6eb9a060e54bf8d69288fbee4904
8601 +fi
8602 +
8603 +# If you want to allow non-ascii filenames set this variable to true.
8604 +allownonascii=$(git config hooks.allownonascii)
8605 +
8606 +# Redirect output to stderr.
8607 +exec 1>&2
8608 +
8609 +# Cross platform projects tend to avoid non-ascii filenames; prevent
8610 +# them from being added to the repository. We exploit the fact that the
8611 +# printable range starts at the space character and ends with tilde.
8612 +if [ "$allownonascii" != "true" ] &&
8613 + # Note that the use of brackets around a tr range is ok here, (it's
8614 + # even required, for portability to Solaris 10's /usr/bin/tr), since
8615 + # the square bracket bytes happen to fall in the designated range.
8616 + test $(git diff --cached --name-only --diff-filter=A -z $against |
8617 + LC_ALL=C tr -d '[ -~]\0' | wc -c) != 0
8618 +then
8619 + echo "Error: Attempt to add a non-ascii file name."
8620 + echo
8621 + echo "This can cause problems if you want to work"
8622 + echo "with people on other platforms."
8623 + echo
8624 + echo "To be portable it is advisable to rename the file ..."
8625 + echo
8626 + echo "If you know what you are doing you can disable this"
8627 + echo "check using:"
8628 + echo
8629 + echo " git config hooks.allownonascii true"
8630 + echo
8631 + exit 1
8632 +fi
8633 +
8634 +# If there are whitespace errors, print the offending file names and fail.
8635 +exec git diff-index --check --cached $against --
8636 diff -ruN u-boot-2014.04/.git/hooks/prepare-commit-msg.sample u-boot-sunxi/.git/hooks/prepare-commit-msg.sample
8637 --- u-boot-2014.04/.git/hooks/prepare-commit-msg.sample 1970-01-01 01:00:00.000000000 +0100
8638 +++ u-boot-sunxi/.git/hooks/prepare-commit-msg.sample 2014-09-06 16:58:09.553953909 +0200
8639 @@ -0,0 +1,36 @@
8640 +#!/bin/sh
8641 +#
8642 +# An example hook script to prepare the commit log message.
8643 +# Called by "git commit" with the name of the file that has the
8644 +# commit message, followed by the description of the commit
8645 +# message's source. The hook's purpose is to edit the commit
8646 +# message file. If the hook fails with a non-zero status,
8647 +# the commit is aborted.
8648 +#
8649 +# To enable this hook, rename this file to "prepare-commit-msg".
8650 +
8651 +# This hook includes three examples. The first comments out the
8652 +# "Conflicts:" part of a merge commit.
8653 +#
8654 +# The second includes the output of "git diff --name-status -r"
8655 +# into the message, just before the "git status" output. It is
8656 +# commented because it doesn't cope with --amend or with squashed
8657 +# commits.
8658 +#
8659 +# The third example adds a Signed-off-by line to the message, that can
8660 +# still be edited. This is rarely a good idea.
8661 +
8662 +case "$2,$3" in
8663 + merge,)
8664 + /usr/bin/perl -i.bak -ne 's/^/# /, s/^# #/#/ if /^Conflicts/ .. /#/; print' "$1" ;;
8665 +
8666 +# ,|template,)
8667 +# /usr/bin/perl -i.bak -pe '
8668 +# print "\n" . `git diff --cached --name-status -r`
8669 +# if /^#/ && $first++ == 0' "$1" ;;
8670 +
8671 + *) ;;
8672 +esac
8673 +
8674 +# SOB=$(git var GIT_AUTHOR_IDENT | sed -n 's/^\(.*>\).*$/Signed-off-by: \1/p')
8675 +# grep -qs "^$SOB" "$1" || echo "$SOB" >> "$1"
8676 diff -ruN u-boot-2014.04/.git/hooks/pre-rebase.sample u-boot-sunxi/.git/hooks/pre-rebase.sample
8677 --- u-boot-2014.04/.git/hooks/pre-rebase.sample 1970-01-01 01:00:00.000000000 +0100
8678 +++ u-boot-sunxi/.git/hooks/pre-rebase.sample 2014-09-06 16:58:09.553953909 +0200
8679 @@ -0,0 +1,169 @@
8680 +#!/bin/sh
8681 +#
8682 +# Copyright (c) 2006, 2008 Junio C Hamano
8683 +#
8684 +# The "pre-rebase" hook is run just before "git rebase" starts doing
8685 +# its job, and can prevent the command from running by exiting with
8686 +# non-zero status.
8687 +#
8688 +# The hook is called with the following parameters:
8689 +#
8690 +# $1 -- the upstream the series was forked from.
8691 +# $2 -- the branch being rebased (or empty when rebasing the current branch).
8692 +#
8693 +# This sample shows how to prevent topic branches that are already
8694 +# merged to 'next' branch from getting rebased, because allowing it
8695 +# would result in rebasing already published history.
8696 +
8697 +publish=next
8698 +basebranch="$1"
8699 +if test "$#" = 2
8700 +then
8701 + topic="refs/heads/$2"
8702 +else
8703 + topic=`git symbolic-ref HEAD` ||
8704 + exit 0 ;# we do not interrupt rebasing detached HEAD
8705 +fi
8706 +
8707 +case "$topic" in
8708 +refs/heads/??/*)
8709 + ;;
8710 +*)
8711 + exit 0 ;# we do not interrupt others.
8712 + ;;
8713 +esac
8714 +
8715 +# Now we are dealing with a topic branch being rebased
8716 +# on top of master. Is it OK to rebase it?
8717 +
8718 +# Does the topic really exist?
8719 +git show-ref -q "$topic" || {
8720 + echo >&2 "No such branch $topic"
8721 + exit 1
8722 +}
8723 +
8724 +# Is topic fully merged to master?
8725 +not_in_master=`git rev-list --pretty=oneline ^master "$topic"`
8726 +if test -z "$not_in_master"
8727 +then
8728 + echo >&2 "$topic is fully merged to master; better remove it."
8729 + exit 1 ;# we could allow it, but there is no point.
8730 +fi
8731 +
8732 +# Is topic ever merged to next? If so you should not be rebasing it.
8733 +only_next_1=`git rev-list ^master "^$topic" ${publish} | sort`
8734 +only_next_2=`git rev-list ^master ${publish} | sort`
8735 +if test "$only_next_1" = "$only_next_2"
8736 +then
8737 + not_in_topic=`git rev-list "^$topic" master`
8738 + if test -z "$not_in_topic"
8739 + then
8740 + echo >&2 "$topic is already up-to-date with master"
8741 + exit 1 ;# we could allow it, but there is no point.
8742 + else
8743 + exit 0
8744 + fi
8745 +else
8746 + not_in_next=`git rev-list --pretty=oneline ^${publish} "$topic"`
8747 + /usr/bin/perl -e '
8748 + my $topic = $ARGV[0];
8749 + my $msg = "* $topic has commits already merged to public branch:\n";
8750 + my (%not_in_next) = map {
8751 + /^([0-9a-f]+) /;
8752 + ($1 => 1);
8753 + } split(/\n/, $ARGV[1]);
8754 + for my $elem (map {
8755 + /^([0-9a-f]+) (.*)$/;
8756 + [$1 => $2];
8757 + } split(/\n/, $ARGV[2])) {
8758 + if (!exists $not_in_next{$elem->[0]}) {
8759 + if ($msg) {
8760 + print STDERR $msg;
8761 + undef $msg;
8762 + }
8763 + print STDERR " $elem->[1]\n";
8764 + }
8765 + }
8766 + ' "$topic" "$not_in_next" "$not_in_master"
8767 + exit 1
8768 +fi
8769 +
8770 +<<\DOC_END
8771 +
8772 +This sample hook safeguards topic branches that have been
8773 +published from being rewound.
8774 +
8775 +The workflow assumed here is:
8776 +
8777 + * Once a topic branch forks from "master", "master" is never
8778 + merged into it again (either directly or indirectly).
8779 +
8780 + * Once a topic branch is fully cooked and merged into "master",
8781 + it is deleted. If you need to build on top of it to correct
8782 + earlier mistakes, a new topic branch is created by forking at
8783 + the tip of the "master". This is not strictly necessary, but
8784 + it makes it easier to keep your history simple.
8785 +
8786 + * Whenever you need to test or publish your changes to topic
8787 + branches, merge them into "next" branch.
8788 +
8789 +The script, being an example, hardcodes the publish branch name
8790 +to be "next", but it is trivial to make it configurable via
8791 +$GIT_DIR/config mechanism.
8792 +
8793 +With this workflow, you would want to know:
8794 +
8795 +(1) ... if a topic branch has ever been merged to "next". Young
8796 + topic branches can have stupid mistakes you would rather
8797 + clean up before publishing, and things that have not been
8798 + merged into other branches can be easily rebased without
8799 + affecting other people. But once it is published, you would
8800 + not want to rewind it.
8801 +
8802 +(2) ... if a topic branch has been fully merged to "master".
8803 + Then you can delete it. More importantly, you should not
8804 + build on top of it -- other people may already want to
8805 + change things related to the topic as patches against your
8806 + "master", so if you need further changes, it is better to
8807 + fork the topic (perhaps with the same name) afresh from the
8808 + tip of "master".
8809 +
8810 +Let's look at this example:
8811 +
8812 + o---o---o---o---o---o---o---o---o---o "next"
8813 + / / / /
8814 + / a---a---b A / /
8815 + / / / /
8816 + / / c---c---c---c B /
8817 + / / / \ /
8818 + / / / b---b C \ /
8819 + / / / / \ /
8820 + ---o---o---o---o---o---o---o---o---o---o---o "master"
8821 +
8822 +
8823 +A, B and C are topic branches.
8824 +
8825 + * A has one fix since it was merged up to "next".
8826 +
8827 + * B has finished. It has been fully merged up to "master" and "next",
8828 + and is ready to be deleted.
8829 +
8830 + * C has not merged to "next" at all.
8831 +
8832 +We would want to allow C to be rebased, refuse A, and encourage
8833 +B to be deleted.
8834 +
8835 +To compute (1):
8836 +
8837 + git rev-list ^master ^topic next
8838 + git rev-list ^master next
8839 +
8840 + if these match, topic has not merged in next at all.
8841 +
8842 +To compute (2):
8843 +
8844 + git rev-list master..topic
8845 +
8846 + if this is empty, it is fully merged to "master".
8847 +
8848 +DOC_END
8849 diff -ruN u-boot-2014.04/.git/hooks/update.sample u-boot-sunxi/.git/hooks/update.sample
8850 --- u-boot-2014.04/.git/hooks/update.sample 1970-01-01 01:00:00.000000000 +0100
8851 +++ u-boot-sunxi/.git/hooks/update.sample 2014-09-06 16:58:09.553953909 +0200
8852 @@ -0,0 +1,128 @@
8853 +#!/bin/sh
8854 +#
8855 +# An example hook script to blocks unannotated tags from entering.
8856 +# Called by "git receive-pack" with arguments: refname sha1-old sha1-new
8857 +#
8858 +# To enable this hook, rename this file to "update".
8859 +#
8860 +# Config
8861 +# ------
8862 +# hooks.allowunannotated
8863 +# This boolean sets whether unannotated tags will be allowed into the
8864 +# repository. By default they won't be.
8865 +# hooks.allowdeletetag
8866 +# This boolean sets whether deleting tags will be allowed in the
8867 +# repository. By default they won't be.
8868 +# hooks.allowmodifytag
8869 +# This boolean sets whether a tag may be modified after creation. By default
8870 +# it won't be.
8871 +# hooks.allowdeletebranch
8872 +# This boolean sets whether deleting branches will be allowed in the
8873 +# repository. By default they won't be.
8874 +# hooks.denycreatebranch
8875 +# This boolean sets whether remotely creating branches will be denied
8876 +# in the repository. By default this is allowed.
8877 +#
8878 +
8879 +# --- Command line
8880 +refname="$1"
8881 +oldrev="$2"
8882 +newrev="$3"
8883 +
8884 +# --- Safety check
8885 +if [ -z "$GIT_DIR" ]; then
8886 + echo "Don't run this script from the command line." >&2
8887 + echo " (if you want, you could supply GIT_DIR then run" >&2
8888 + echo " $0 <ref> <oldrev> <newrev>)" >&2
8889 + exit 1
8890 +fi
8891 +
8892 +if [ -z "$refname" -o -z "$oldrev" -o -z "$newrev" ]; then
8893 + echo "Usage: $0 <ref> <oldrev> <newrev>" >&2
8894 + exit 1
8895 +fi
8896 +
8897 +# --- Config
8898 +allowunannotated=$(git config --bool hooks.allowunannotated)
8899 +allowdeletebranch=$(git config --bool hooks.allowdeletebranch)
8900 +denycreatebranch=$(git config --bool hooks.denycreatebranch)
8901 +allowdeletetag=$(git config --bool hooks.allowdeletetag)
8902 +allowmodifytag=$(git config --bool hooks.allowmodifytag)
8903 +
8904 +# check for no description
8905 +projectdesc=$(sed -e '1q' "$GIT_DIR/description")
8906 +case "$projectdesc" in
8907 +"Unnamed repository"* | "")
8908 + echo "*** Project description file hasn't been set" >&2
8909 + exit 1
8910 + ;;
8911 +esac
8912 +
8913 +# --- Check types
8914 +# if $newrev is 0000...0000, it's a commit to delete a ref.
8915 +zero="0000000000000000000000000000000000000000"
8916 +if [ "$newrev" = "$zero" ]; then
8917 + newrev_type=delete
8918 +else
8919 + newrev_type=$(git cat-file -t $newrev)
8920 +fi
8921 +
8922 +case "$refname","$newrev_type" in
8923 + refs/tags/*,commit)
8924 + # un-annotated tag
8925 + short_refname=${refname##refs/tags/}
8926 + if [ "$allowunannotated" != "true" ]; then
8927 + echo "*** The un-annotated tag, $short_refname, is not allowed in this repository" >&2
8928 + echo "*** Use 'git tag [ -a | -s ]' for tags you want to propagate." >&2
8929 + exit 1
8930 + fi
8931 + ;;
8932 + refs/tags/*,delete)
8933 + # delete tag
8934 + if [ "$allowdeletetag" != "true" ]; then
8935 + echo "*** Deleting a tag is not allowed in this repository" >&2
8936 + exit 1
8937 + fi
8938 + ;;
8939 + refs/tags/*,tag)
8940 + # annotated tag
8941 + if [ "$allowmodifytag" != "true" ] && git rev-parse $refname > /dev/null 2>&1
8942 + then
8943 + echo "*** Tag '$refname' already exists." >&2
8944 + echo "*** Modifying a tag is not allowed in this repository." >&2
8945 + exit 1
8946 + fi
8947 + ;;
8948 + refs/heads/*,commit)
8949 + # branch
8950 + if [ "$oldrev" = "$zero" -a "$denycreatebranch" = "true" ]; then
8951 + echo "*** Creating a branch is not allowed in this repository" >&2
8952 + exit 1
8953 + fi
8954 + ;;
8955 + refs/heads/*,delete)
8956 + # delete branch
8957 + if [ "$allowdeletebranch" != "true" ]; then
8958 + echo "*** Deleting a branch is not allowed in this repository" >&2
8959 + exit 1
8960 + fi
8961 + ;;
8962 + refs/remotes/*,commit)
8963 + # tracking branch
8964 + ;;
8965 + refs/remotes/*,delete)
8966 + # delete tracking branch
8967 + if [ "$allowdeletebranch" != "true" ]; then
8968 + echo "*** Deleting a tracking branch is not allowed in this repository" >&2
8969 + exit 1
8970 + fi
8971 + ;;
8972 + *)
8973 + # Anything else (is there anything else?)
8974 + echo "*** Update hook: unknown type of update to ref $refname of type $newrev_type" >&2
8975 + exit 1
8976 + ;;
8977 +esac
8978 +
8979 +# --- Finished
8980 +exit 0
8981 Binary files u-boot-2014.04/.git/index and u-boot-sunxi/.git/index differ
8982 diff -ruN u-boot-2014.04/.git/info/exclude u-boot-sunxi/.git/info/exclude
8983 --- u-boot-2014.04/.git/info/exclude 1970-01-01 01:00:00.000000000 +0100
8984 +++ u-boot-sunxi/.git/info/exclude 2014-09-06 16:58:09.553953909 +0200
8985 @@ -0,0 +1,6 @@
8986 +# git ls-files --others --exclude-from=.git/info/exclude
8987 +# Lines that start with '#' are comments.
8988 +# For a project mostly in C, the following would be a good set of
8989 +# exclude patterns (uncomment them if you want to use them):
8990 +# *.[oa]
8991 +# *~
8992 diff -ruN u-boot-2014.04/.git/logs/HEAD u-boot-sunxi/.git/logs/HEAD
8993 --- u-boot-2014.04/.git/logs/HEAD 1970-01-01 01:00:00.000000000 +0100
8994 +++ u-boot-sunxi/.git/logs/HEAD 2014-09-06 16:58:35.001953150 +0200
8995 @@ -0,0 +1 @@
8996 +0000000000000000000000000000000000000000 509d96d4f1f602d62d36db660973249e16f9d088 Zoltan HERPAI <wigyori@uid0.hu> 1410015515 +0200 clone: from https://github.com/linux-sunxi/u-boot-sunxi
8997 diff -ruN u-boot-2014.04/.git/logs/refs/heads/sunxi u-boot-sunxi/.git/logs/refs/heads/sunxi
8998 --- u-boot-2014.04/.git/logs/refs/heads/sunxi 1970-01-01 01:00:00.000000000 +0100
8999 +++ u-boot-sunxi/.git/logs/refs/heads/sunxi 2014-09-06 16:58:35.001953150 +0200
9000 @@ -0,0 +1 @@
9001 +0000000000000000000000000000000000000000 509d96d4f1f602d62d36db660973249e16f9d088 Zoltan HERPAI <wigyori@uid0.hu> 1410015515 +0200 clone: from https://github.com/linux-sunxi/u-boot-sunxi
9002 diff -ruN u-boot-2014.04/.git/logs/refs/remotes/origin/HEAD u-boot-sunxi/.git/logs/refs/remotes/origin/HEAD
9003 --- u-boot-2014.04/.git/logs/refs/remotes/origin/HEAD 1970-01-01 01:00:00.000000000 +0100
9004 +++ u-boot-sunxi/.git/logs/refs/remotes/origin/HEAD 2014-09-06 16:58:35.001953150 +0200
9005 @@ -0,0 +1 @@
9006 +0000000000000000000000000000000000000000 509d96d4f1f602d62d36db660973249e16f9d088 Zoltan HERPAI <wigyori@uid0.hu> 1410015515 +0200 clone: from https://github.com/linux-sunxi/u-boot-sunxi
9007 Binary files u-boot-2014.04/.git/objects/pack/pack-67611423d2b8399a45fe3205d396caff441c8135.idx and u-boot-sunxi/.git/objects/pack/pack-67611423d2b8399a45fe3205d396caff441c8135.idx differ
9008 Binary files u-boot-2014.04/.git/objects/pack/pack-67611423d2b8399a45fe3205d396caff441c8135.pack and u-boot-sunxi/.git/objects/pack/pack-67611423d2b8399a45fe3205d396caff441c8135.pack differ
9009 diff -ruN u-boot-2014.04/.git/packed-refs u-boot-sunxi/.git/packed-refs
9010 --- u-boot-2014.04/.git/packed-refs 1970-01-01 01:00:00.000000000 +0100
9011 +++ u-boot-sunxi/.git/packed-refs 2014-09-06 16:58:35.001953150 +0200
9012 @@ -0,0 +1,25 @@
9013 +# pack-refs with: peeled
9014 +3212c6fd4beaa14a21a57e5241022702c986f82e refs/remotes/origin/lichee-dev
9015 +c0860ba179bc0cf016831ceeeacd0dd4e287a860 refs/remotes/origin/lichee-dev-a20
9016 +1076d3bdd67db39f34bc91857c636525874441ae refs/remotes/origin/lichee/lichee-dev
9017 +40b4fba701c1824cc60c7ab966f4a5dd674e947d refs/remotes/origin/lichee/lichee-dev-ICS
9018 +cf54463fd782c690cf790ca35b5a15504b57c287 refs/remotes/origin/lichee/lichee-dev-mmc
9019 +218f643881c0dabd7e40cdb21a757416fa80afb2 refs/remotes/origin/old/sunxi-current
9020 +509d96d4f1f602d62d36db660973249e16f9d088 refs/remotes/origin/sunxi
9021 +43fb1236c3330676f49220cc1dfc235eb0558e4c refs/remotes/origin/sunxi-patchqueue
9022 +80fd9a5c5b87ba2f48f4a71b666839870e780be6 refs/remotes/origin/wip/a20
9023 +27113637710a574d1fb6325817ffa9ced7afe019 refs/tags/v2011.09-sun4i
9024 +^22b38fa5c0348ac4f285f038999f9a617f98e73a
9025 +9ba56441491542cd06b30c514e544d96b29ef801 refs/tags/v2011.09-sun4i-20120808
9026 +88eacf3372855579760ba6bc8fa3e0d4e53fdef8 refs/tags/v2012.10-sunxi
9027 +1ae18d97d24c5d6dd4cb7949d8e5fb602728601c refs/tags/v2013.01-sunxi
9028 +fc40799c144d035c595c4abe3032a03be8f0e2c4 refs/tags/v2013.01.01-sunxi
9029 +90c8c0c88362d1e39bb1433f04b9a21bb1c74e45 refs/tags/v2013.04-sunxi
9030 +57ff4519ba0f47f1647f7def5864ae4c9ef3e6a0 refs/tags/v2013.07-rc1-sunxi
9031 +c416374795b584f025a80b1f81db215456567155 refs/tags/v2013.07-sunxi
9032 +8969c6f654248ececdfcf05eb51de9a8bc0a8703 refs/tags/v2013.07-sunxi.2
9033 +88b1df7ee9c15c821a2209791f513b21596f21b4 refs/tags/v2013.07-sunxi.3
9034 +569c37da7dfd4ed93b6e8b5993df760b9ed18c8d refs/tags/v2013.07-sunxi.4
9035 +7a63a6882876b76e47746c1254e8cd1120a52b0d refs/tags/v2013.10-rc1-sunxi
9036 +951e509384822e39149c22f44cde6a01f5105c40 refs/tags/v2013.10-rc2-sunxi
9037 +09ef3a640a3eb58e66eedcf239193e2ab548e730 refs/tags/v2013.10-sunxi
9038 diff -ruN u-boot-2014.04/.git/refs/heads/sunxi u-boot-sunxi/.git/refs/heads/sunxi
9039 --- u-boot-2014.04/.git/refs/heads/sunxi 1970-01-01 01:00:00.000000000 +0100
9040 +++ u-boot-sunxi/.git/refs/heads/sunxi 2014-09-06 16:58:35.001953150 +0200
9041 @@ -0,0 +1 @@
9042 +509d96d4f1f602d62d36db660973249e16f9d088
9043 diff -ruN u-boot-2014.04/.git/refs/remotes/origin/HEAD u-boot-sunxi/.git/refs/remotes/origin/HEAD
9044 --- u-boot-2014.04/.git/refs/remotes/origin/HEAD 1970-01-01 01:00:00.000000000 +0100
9045 +++ u-boot-sunxi/.git/refs/remotes/origin/HEAD 2014-09-06 16:58:35.001953150 +0200
9046 @@ -0,0 +1 @@
9047 +ref: refs/remotes/origin/sunxi
9048 diff -ruN u-boot-2014.04/include/axp152.h u-boot-sunxi/include/axp152.h
9049 --- u-boot-2014.04/include/axp152.h 1970-01-01 01:00:00.000000000 +0100
9050 +++ u-boot-sunxi/include/axp152.h 2014-09-06 16:58:36.397953109 +0200
9051 @@ -0,0 +1,11 @@
9052 +/*
9053 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
9054 + *
9055 + * SPDX-License-Identifier: GPL-2.0+
9056 + */
9057 +int axp152_set_dcdc2(int mvolt);
9058 +int axp152_set_dcdc3(int mvolt);
9059 +int axp152_set_dcdc4(int mvolt);
9060 +int axp152_set_ldo2(int mvolt);
9061 +void axp152_poweroff(void);
9062 +int axp152_init(void);
9063 diff -ruN u-boot-2014.04/include/axp209.h u-boot-sunxi/include/axp209.h
9064 --- u-boot-2014.04/include/axp209.h 1970-01-01 01:00:00.000000000 +0100
9065 +++ u-boot-sunxi/include/axp209.h 2014-09-06 16:58:36.397953109 +0200
9066 @@ -0,0 +1,15 @@
9067 +/*
9068 + * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
9069 + *
9070 + * SPDX-License-Identifier: GPL-2.0+
9071 + */
9072 +
9073 +extern int axp209_set_dcdc2(int mvolt);
9074 +extern int axp209_set_dcdc3(int mvolt);
9075 +extern int axp209_set_ldo2(int mvolt);
9076 +extern int axp209_set_ldo3(int mvolt);
9077 +extern int axp209_set_ldo4(int mvolt);
9078 +extern void axp209_poweroff(void);
9079 +extern int axp209_init(void);
9080 +extern int axp209_poweron_by_dc(void);
9081 +extern int axp209_power_button(void);
9082 diff -ruN u-boot-2014.04/include/axp221.h u-boot-sunxi/include/axp221.h
9083 --- u-boot-2014.04/include/axp221.h 1970-01-01 01:00:00.000000000 +0100
9084 +++ u-boot-sunxi/include/axp221.h 2014-09-06 16:58:36.397953109 +0200
9085 @@ -0,0 +1,30 @@
9086 +/*
9087 + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
9088 + *
9089 + * X-Powers AXP221 Power Management IC driver
9090 + *
9091 + * SPDX-License-Identifier: GPL-2.0+
9092 + */
9093 +
9094 +#define AXP221_CHIP_ADDR 0x68
9095 +#define AXP221_CTRL_ADDR 0x3e
9096 +#define AXP221_INIT_DATA 0x3e
9097 +
9098 +#define AXP221_CHIP_ID 0x03
9099 +#define AXP221_OUTPUT_CTRL1 0x10
9100 +#define AXP221_OUTPUT_CTRL2 0x12
9101 +#define AXP221_OUTPUT_CTRL3 0x13
9102 +#define AXP221_DLDO1_CTRL 0x15
9103 +#define AXP221_DCDC1_CTRL 0x21
9104 +#define AXP221_DCDC2_CTRL 0x22
9105 +#define AXP221_DCDC3_CTRL 0x23
9106 +#define AXP221_DCDC4_CTRL 0x24
9107 +#define AXP221_DCDC5_CTRL 0x25
9108 +
9109 +int axp221_set_dcdc1(unsigned int mvolt);
9110 +int axp221_set_dcdc2(unsigned int mvolt);
9111 +int axp221_set_dcdc3(unsigned int mvolt);
9112 +int axp221_set_dcdc4(unsigned int mvolt);
9113 +int axp221_set_dcdc5(unsigned int mvolt);
9114 +int axp221_set_dldo1(unsigned int mvolt);
9115 +int axp221_init(void);
9116 diff -ruN u-boot-2014.04/include/config_fallbacks.h u-boot-sunxi/include/config_fallbacks.h
9117 --- u-boot-2014.04/include/config_fallbacks.h 2014-04-14 21:19:24.000000000 +0200
9118 +++ u-boot-sunxi/include/config_fallbacks.h 2014-09-06 16:58:36.401953108 +0200
9119 @@ -55,6 +55,10 @@
9120 #define HAVE_BLOCK_DEVICE
9121 #endif
9122
9123 +#ifndef CONFIG_SYS_BOARD_NAME
9124 +#define CONFIG_SYS_BOARD_NAME CONFIG_SYS_TARGET
9125 +#endif
9126 +
9127 #if (defined(CONFIG_PARTITION_UUIDS) || \
9128 defined(CONFIG_EFI_PARTITION) || \
9129 defined(CONFIG_RANDOM_UUID) || \
9130 diff -ruN u-boot-2014.04/include/configs/sun4i.h u-boot-sunxi/include/configs/sun4i.h
9131 --- u-boot-2014.04/include/configs/sun4i.h 1970-01-01 01:00:00.000000000 +0100
9132 +++ u-boot-sunxi/include/configs/sun4i.h 2014-09-06 16:58:36.461953107 +0200
9133 @@ -0,0 +1,25 @@
9134 +/*
9135 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
9136 + *
9137 + * Configuration settings for the Allwinner A10 (sun4i) CPU
9138 + *
9139 + * SPDX-License-Identifier: GPL-2.0+
9140 + */
9141 +#ifndef __CONFIG_H
9142 +#define __CONFIG_H
9143 +
9144 +/*
9145 + * A10 specific configuration
9146 + */
9147 +#define CONFIG_SUN4I /* sun4i SoC generation */
9148 +#define CONFIG_CLK_FULL_SPEED 1008000000
9149 +
9150 +#define CONFIG_SYS_PROMPT "sun4i# "
9151 +#define CONFIG_MACH_TYPE 4104
9152 +
9153 +/*
9154 + * Include common sunxi configuration where most the settings are
9155 + */
9156 +#include <configs/sunxi-common.h>
9157 +
9158 +#endif /* __CONFIG_H */
9159 diff -ruN u-boot-2014.04/include/configs/sun5i.h u-boot-sunxi/include/configs/sun5i.h
9160 --- u-boot-2014.04/include/configs/sun5i.h 1970-01-01 01:00:00.000000000 +0100
9161 +++ u-boot-sunxi/include/configs/sun5i.h 2014-09-06 16:58:36.461953107 +0200
9162 @@ -0,0 +1,25 @@
9163 +/*
9164 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
9165 + *
9166 + * Configuration settings for the Allwinner A13 (sun5i) CPU
9167 + *
9168 + * SPDX-License-Identifier: GPL-2.0+
9169 + */
9170 +#ifndef __CONFIG_H
9171 +#define __CONFIG_H
9172 +
9173 +/*
9174 + * High Level Configuration Options
9175 + */
9176 +#define CONFIG_SUN5I /* sun5i SoC generation */
9177 +#define CONFIG_CLK_FULL_SPEED 1008000000
9178 +
9179 +#define CONFIG_SYS_PROMPT "sun5i# "
9180 +#define CONFIG_MACH_TYPE 4138
9181 +
9182 +/*
9183 + * Include common sunxi configuration where most the settings are
9184 + */
9185 +#include <configs/sunxi-common.h>
9186 +
9187 +#endif /* __CONFIG_H */
9188 diff -ruN u-boot-2014.04/include/configs/sun6i.h u-boot-sunxi/include/configs/sun6i.h
9189 --- u-boot-2014.04/include/configs/sun6i.h 1970-01-01 01:00:00.000000000 +0100
9190 +++ u-boot-sunxi/include/configs/sun6i.h 2014-09-06 16:58:36.461953107 +0200
9191 @@ -0,0 +1,43 @@
9192 +/*
9193 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
9194 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
9195 + * (C) Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
9196 + *
9197 + * Configuration settings for the Allwinner A31 (sun6i) CPU
9198 + *
9199 + * See file CREDITS for list of people who contributed to this
9200 + * project.
9201 + *
9202 + * This program is free software; you can redistribute it and/or
9203 + * modify it under the terms of the GNU General Public License as
9204 + * published by the Free Software Foundation; either version 2 of
9205 + * the License, or (at your option) any later version.
9206 + *
9207 + * This program is distributed in the hope that it will be useful,
9208 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
9209 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9210 + * GNU General Public License for more details.
9211 + *
9212 + * You should have received a copy of the GNU General Public License
9213 + * along with this program; if not, write to the Free Software
9214 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
9215 + * MA 02111-1307 USA
9216 + */
9217 +
9218 +#ifndef __CONFIG_H
9219 +#define __CONFIG_H
9220 +
9221 +/*
9222 + * A31 specific configuration
9223 + */
9224 +#define CONFIG_SUN6I /* sun6i SoC generation */
9225 +
9226 +#define CONFIG_SYS_PROMPT "sun6i# "
9227 +#define CONFIG_MACH_TYPE 3892
9228 +
9229 +/*
9230 + * Include common sunxi configuration where most the settings are
9231 + */
9232 +#include <configs/sunxi-common.h>
9233 +
9234 +#endif /* __CONFIG_H */
9235 diff -ruN u-boot-2014.04/include/configs/sun7i.h u-boot-sunxi/include/configs/sun7i.h
9236 --- u-boot-2014.04/include/configs/sun7i.h 1970-01-01 01:00:00.000000000 +0100
9237 +++ u-boot-sunxi/include/configs/sun7i.h 2014-09-06 16:58:36.461953107 +0200
9238 @@ -0,0 +1,30 @@
9239 +/*
9240 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
9241 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
9242 + *
9243 + * Configuration settings for the Allwinner A20 (sun7i) CPU
9244 + *
9245 + * SPDX-License-Identifier: GPL-2.0+
9246 + */
9247 +#ifndef __CONFIG_H
9248 +#define __CONFIG_H
9249 +
9250 +/*
9251 + * A20 specific configuration
9252 + */
9253 +#define CONFIG_SUN7I /* sun7i SoC generation */
9254 +#define CONFIG_CLK_FULL_SPEED 912000000
9255 +
9256 +#define CONFIG_SYS_PROMPT "sun7i# "
9257 +#define CONFIG_MACH_TYPE 4283
9258 +
9259 +#if defined(CONFIG_SYS_SECONDARY_ON)
9260 +#define CONFIG_BOARD_POSTCLK_INIT 1
9261 +#endif
9262 +
9263 +/*
9264 + * Include common sunxi configuration where most the settings are
9265 + */
9266 +#include <configs/sunxi-common.h>
9267 +
9268 +#endif /* __CONFIG_H */
9269 diff -ruN u-boot-2014.04/include/configs/sun8i.h u-boot-sunxi/include/configs/sun8i.h
9270 --- u-boot-2014.04/include/configs/sun8i.h 1970-01-01 01:00:00.000000000 +0100
9271 +++ u-boot-sunxi/include/configs/sun8i.h 2014-09-06 16:58:36.461953107 +0200
9272 @@ -0,0 +1,28 @@
9273 +/*
9274 + * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
9275 + * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
9276 + * (C) Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
9277 + * (C) Copyright 2014 Chen-Yu Tsai <wens@csie.org>
9278 + *
9279 + * Configuration settings for the Allwinner A23 (sun8i) CPU
9280 + *
9281 + * SPDX-License-Identifier: GPL-2.0+
9282 + */
9283 +
9284 +#ifndef __CONFIG_H
9285 +#define __CONFIG_H
9286 +
9287 +/*
9288 + * A23 specific configuration
9289 + */
9290 +#define CONFIG_SUN8I /* sun8i SoC generation */
9291 +
9292 +#define CONFIG_SYS_PROMPT "sun8i# "
9293 +#define CONFIG_MACH_TYPE 4137
9294 +
9295 +/*
9296 + * Include common sunxi configuration where most the settings are
9297 + */
9298 +#include <configs/sunxi-common.h>
9299 +
9300 +#endif /* __CONFIG_H */
9301 diff -ruN u-boot-2014.04/include/configs/sunxi-common.h u-boot-sunxi/include/configs/sunxi-common.h
9302 --- u-boot-2014.04/include/configs/sunxi-common.h 1970-01-01 01:00:00.000000000 +0100
9303 +++ u-boot-sunxi/include/configs/sunxi-common.h 2014-09-06 16:58:36.461953107 +0200
9304 @@ -0,0 +1,427 @@
9305 +/*
9306 + * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
9307 + *
9308 + * (C) Copyright 2007-2011
9309 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
9310 + * Tom Cubie <tangliang@allwinnertech.com>
9311 + *
9312 + * Configuration settings for the Allwinner sunxi series of boards.
9313 + *
9314 + * SPDX-License-Identifier: GPL-2.0+
9315 + */
9316 +
9317 +#ifndef _SUNXI_COMMON_CONFIG_H
9318 +#define _SUNXI_COMMON_CONFIG_H
9319 +
9320 +/*
9321 + * High Level Configuration Options
9322 + */
9323 +#define CONFIG_SUNXI /* sunxi family */
9324 +#ifdef CONFIG_SPL_BUILD
9325 +#ifndef CONFIG_SPL_FEL
9326 +#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
9327 +#endif
9328 +#endif
9329 +
9330 +#include <asm/arch/cpu.h> /* get chip and board defs */
9331 +
9332 +#define CONFIG_SYS_TEXT_BASE 0x4a000000
9333 +
9334 +/*
9335 + * Display CPU and Board information
9336 + */
9337 +#define CONFIG_DISPLAY_CPUINFO
9338 +#define CONFIG_DISPLAY_BOARDINFO
9339 +
9340 +/* Serial & console */
9341 +#define CONFIG_SYS_NS16550
9342 +#define CONFIG_SYS_NS16550_SERIAL
9343 +/* ns16550 reg in the low bits of cpu reg */
9344 +#define CONFIG_SYS_NS16550_REG_SIZE -4
9345 +#define CONFIG_SYS_NS16550_CLK 24000000
9346 +#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
9347 +#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
9348 +#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
9349 +#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
9350 +#define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
9351 +
9352 +/* DRAM Base */
9353 +#define CONFIG_SYS_SDRAM_BASE 0x40000000
9354 +#define CONFIG_SYS_INIT_RAM_ADDR 0x0
9355 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
9356 +
9357 +#define CONFIG_SYS_INIT_SP_OFFSET \
9358 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
9359 +#define CONFIG_SYS_INIT_SP_ADDR \
9360 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
9361 +
9362 +/* A10 has 1 banks of DRAM, we use only bank 1 in U-Boot */
9363 +#define CONFIG_NR_DRAM_BANKS 1
9364 +#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
9365 +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN7I)
9366 +#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
9367 +#else
9368 +#define PHYS_SDRAM_0_SIZE 0x40000000 /* 1 GiB */
9369 +#endif
9370 +#if 0
9371 +/* Nand config */
9372 +#define CONFIG_NAND
9373 +#define CONFIG_NAND_SUNXI
9374 +#define CONFIG_CMD_NAND /* NAND support */
9375 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
9376 +#define CONFIG_SYS_NAND_BASE 0x00
9377 +#endif
9378 +
9379 +#define CONFIG_CMD_MEMORY
9380 +#define CONFIG_CMD_SETEXPR
9381 +
9382 +#define CONFIG_SETUP_MEMORY_TAGS
9383 +#define CONFIG_CMDLINE_TAG
9384 +#define CONFIG_INITRD_TAG
9385 +
9386 +/* mmc config */
9387 +/* Can't use MMC slot 0 if the UART is directed there */
9388 +#if !defined CONFIG_UART0_PORT_F || CONFIG_MMC_SUNXI_SLOT != 0
9389 +#define CONFIG_MMC
9390 +#define CONFIG_GENERIC_MMC
9391 +#define CONFIG_CMD_MMC
9392 +#define CONFIG_MMC_SUNXI
9393 +#ifndef CONFIG_MMC_SUNXI_SLOT
9394 +#define CONFIG_MMC_SUNXI_SLOT 0
9395 +#endif
9396 +#define CONFIG_ENV_IS_IN_MMC
9397 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
9398 +#endif
9399 +
9400 +/* 4MB of malloc() pool */
9401 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
9402 +
9403 +/*
9404 + * Miscellaneous configurable options
9405 + */
9406 +#define CONFIG_CMD_ECHO
9407 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
9408 +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
9409 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
9410 +#define CONFIG_SYS_GENERIC_BOARD
9411 +
9412 +/* Boot Argument Buffer Size */
9413 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
9414 +
9415 +#define CONFIG_SYS_LOAD_ADDR 0x48000000 /* default load address */
9416 +
9417 +/* standalone support */
9418 +#define CONFIG_STANDALONE_LOAD_ADDR 0x48000000
9419 +
9420 +#define CONFIG_SYS_HZ 1000
9421 +
9422 +/* baudrate */
9423 +#define CONFIG_BAUDRATE 115200
9424 +
9425 +/* The stack sizes are set up in start.S using the settings below */
9426 +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
9427 +
9428 +/* FLASH and environment organization */
9429 +
9430 +#define CONFIG_SYS_NO_FLASH
9431 +
9432 +#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */
9433 +#define CONFIG_IDENT_STRING " Allwinner Technology"
9434 +
9435 +#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */
9436 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
9437 +
9438 +#ifdef CONFIG_SPL_FEL
9439 +#define RUN_BOOT_RAM "run boot_ram;"
9440 +#else
9441 +#define RUN_BOOT_RAM ""
9442 +#endif
9443 +
9444 +#define CONFIG_BOOTCOMMAND \
9445 + RUN_BOOT_RAM \
9446 + "if run loadbootenv; then " \
9447 + "echo Loaded environment from ${bootenv};" \
9448 + "env import -t ${scriptaddr} ${filesize};" \
9449 + "fi;" \
9450 + "if test -n \\\"${uenvcmd}\\\"; then " \
9451 + "echo Running uenvcmd ...;" \
9452 + "run uenvcmd;" \
9453 + "fi;" \
9454 + "if run loadbootscr; then "\
9455 + "echo Jumping to ${bootscr};" \
9456 + "source ${scriptaddr};" \
9457 + "fi;" \
9458 + "run autoboot;" \
9459 + ""
9460 +
9461 +#ifdef CONFIG_CMD_WATCHDOG
9462 +#define RESET_WATCHDOG "watchdog 0"
9463 +#else
9464 +#define RESET_WATCHDOG "true"
9465 +#endif
9466 +
9467 +#define CONFIG_EXTRA_ENV_SETTINGS \
9468 + "bootm_size=0x10000000\0" \
9469 + "console=ttyS0,115200\0" \
9470 + "panicarg=panic=10\0" \
9471 + "extraargs=\0" \
9472 + "loglevel=8\0" \
9473 + "scriptaddr=0x44000000\0" \
9474 + "device=mmc\0" \
9475 + "partition=0:1\0" \
9476 + "setargs=" \
9477 + "if test -z \\\\\"$root\\\\\"; then"\
9478 + " if test \\\\\"$bootpath\\\\\" = \"/boot/\"; then"\
9479 + " root=\"/dev/mmcblk0p1 rootwait\";"\
9480 + " else" \
9481 + " root=\"/dev/mmcblk0p2 rootwait\";"\
9482 + " fi;"\
9483 + " fi;"\
9484 + " setenv bootargs console=${console} root=${root}" \
9485 + " loglevel=${loglevel} ${panicarg} ${extraargs}" \
9486 + "\0" \
9487 + "kernel=uImage\0" \
9488 + "bootenv=uEnv.txt\0" \
9489 + "bootscr=boot.scr\0" \
9490 + "script=script.bin\0" \
9491 + "loadbootscr=" \
9492 + "fatload $device $partition $scriptaddr ${bootscr}" \
9493 + " || " \
9494 + "ext2load $device $partition $scriptaddr boot/${bootscr}" \
9495 + " ||" \
9496 + "ext2load $device $partition $scriptaddr ${bootscr}" \
9497 + "\0" \
9498 + "loadbootenv=" \
9499 + "fatload $device $partition $scriptaddr ${bootenv}" \
9500 + " || " \
9501 + "ext2load $device $partition $scriptaddr boot/${bootenv}" \
9502 + " || " \
9503 + "ext2load $device $partition $scriptaddr ${bootenv}" \
9504 + "\0" \
9505 + "loadkernel=" \
9506 + "if "\
9507 + "bootpath=/boot/" \
9508 + " && " \
9509 + "ext2load $device $partition 0x43000000 ${bootpath}${script}" \
9510 + " && " \
9511 + "ext2load $device $partition 0x48000000 ${bootpath}${kernel}" \
9512 + ";then true; elif " \
9513 + "bootpath=/" \
9514 + " && " \
9515 + "fatload $device $partition 0x43000000 ${script}" \
9516 + " && " \
9517 + "fatload $device $partition 0x48000000 ${kernel}" \
9518 + ";then true; elif " \
9519 + "bootpath=/" \
9520 + " && " \
9521 + "ext2load $device $partition 0x43000000 ${bootpath}${script}" \
9522 + " && " \
9523 + "ext2load $device $partition 0x48000000 ${bootpath}${kernel}" \
9524 + ";then true; else "\
9525 + "false" \
9526 + ";fi" \
9527 + "\0" \
9528 + "autoboot=" \
9529 + "run loadkernel" \
9530 + " && " \
9531 + "run setargs" \
9532 + " && " \
9533 + RESET_WATCHDOG \
9534 + " && " \
9535 + "bootm 0x48000000" \
9536 + "\0" \
9537 + "boot_ram=" \
9538 + "saved_stdout=$stdout;setenv stdout nc;"\
9539 + "if iminfo 0x41000000; then" \
9540 + " " RESET_WATCHDOG ";"\
9541 + " setenv stdout $saved_stdout;" \
9542 + " source 0x41000000;" \
9543 + "else" \
9544 + " setenv stdout $saved_stdout;" \
9545 + "fi" \
9546 + "\0" \
9547 + ""
9548 +
9549 +#define CONFIG_SYS_BOOT_GET_CMDLINE
9550 +
9551 +#include <config_cmd_default.h>
9552 +
9553 +#define CONFIG_FAT_WRITE /* enable write access */
9554 +
9555 +#define CONFIG_SPL_FRAMEWORK
9556 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
9557 +#define CONFIG_SPL_SERIAL_SUPPORT
9558 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
9559 +#define CONFIG_SPL_DISPLAY_PRINT
9560 +
9561 +/* Falcon boot mode support */
9562 +/* Disabled by default on sun4i/sun7i. Many GCC versions produces a too
9563 + * large SPL for A10/A20 with this on. sun5i however accepts a much larger
9564 + * SPL
9565 + */
9566 +#if defined( CONFIG_SUN5I ) || defined ( CONFIG_SYS_THUMB_BUILD )
9567 +#define CONFIG_SPL_OS_BOOT
9568 +#endif
9569 +
9570 +#ifdef CONFIG_SPL_FEL
9571 +
9572 +#define CONFIG_SPL
9573 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds"
9574 +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi"
9575 +#define CONFIG_SPL_TEXT_BASE 0x2000
9576 +#define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */
9577 +
9578 +#else /* CONFIG_SPL */
9579 +
9580 +#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000
9581 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */
9582 +
9583 +#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */
9584 +#ifdef CONFIG_SUN5I
9585 +#define CONFIG_SPL_MAX_SIZE 0x75e0 /* 7748+ is used */
9586 +#else
9587 +#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */
9588 +#endif
9589 +
9590 +#define CONFIG_SPL_LIBDISK_SUPPORT
9591 +#define CONFIG_SPL_MMC_SUPPORT
9592 +
9593 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
9594 +
9595 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */
9596 +#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
9597 +
9598 +#endif /* CONFIG_SPL */
9599 +/* end of 32 KiB in sram */
9600 +#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
9601 +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
9602 +#define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000
9603 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */
9604 +
9605 +#ifdef CONFIG_SPL_OS_BOOT
9606 +#define CONFIG_CMD_SPL
9607 +#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_0 + 0x100)
9608 +#ifdef CONFIG_SPL_MMC_SUPPORT
9609 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 1344
9610 +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 256
9611 +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 1600
9612 +#endif
9613 +#endif
9614 +
9615 +#undef CONFIG_CMD_FPGA
9616 +#undef CONFIG_CMD_NET
9617 +#undef CONFIG_CMD_NFS
9618 +
9619 +/* I2C */
9620 +#if !defined CONFIG_SUN6I && !defined CONFIG_SUN8I
9621 +#define CONFIG_SPL_I2C_SUPPORT
9622 +#endif
9623 +/* No CONFIG_SYS_I2C as we use the non converted mvtwsi driver */
9624 +#define CONFIG_HARD_I2C
9625 +#define CONFIG_SYS_I2C_SUNXI
9626 +#define CONFIG_SYS_I2C_SPEED 400000
9627 +#define CONFIG_SYS_I2C_SLAVE 0x7f
9628 +#define CONFIG_CMD_I2C
9629 +
9630 +/* Watchdog */
9631 +#if 0
9632 +#define CONFIG_WATCHDOG /* automatic watchdog support */
9633 +#define CONFIG_CMD_WATCHDOG /* watchdog command setting the watchdog timeout */
9634 +#endif
9635 +
9636 +/* GPIO */
9637 +#define CONFIG_SUNXI_GPIO
9638 +#define CONFIG_CMD_GPIO
9639 +
9640 +/* PMU */
9641 +#if !defined CONFIG_AXP152_POWER && !defined CONFIG_AXP221_POWER && !defined CONFIG_NO_AXP
9642 +#define CONFIG_AXP209_POWER
9643 +#endif
9644 +#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
9645 +#define CONFIG_SPL_POWER_SUPPORT
9646 +#endif
9647 +
9648 +#ifdef CONFIG_STATUSLED
9649 +#define STATUS_LED_BIT CONFIG_STATUSLED
9650 +#endif
9651 +#ifdef CONFIG_STATUSLED1
9652 +#define STATUS_LED_BIT1 CONFIG_STATUSLED1
9653 +#endif
9654 +#ifdef CONFIG_STATUSLED2
9655 +#define STATUS_LED_BIT2 CONFIG_STATUSLED2
9656 +#endif
9657 +#ifdef CONFIG_STATUSLED3
9658 +#define STATUS_LED_BIT3 CONFIG_STATUSLED3
9659 +#endif
9660 +
9661 +#ifndef CONFIG_SPL_BUILD
9662 +#ifdef STATUS_LED_BIT
9663 +#define CONFIG_GPIO_LED
9664 +#define CONFIG_STATUS_LED
9665 +#ifndef STATUS_LED_BOOT
9666 +#define STATUS_LED_BOOT 0
9667 +#endif
9668 +#ifndef STATUS_LED_STATE
9669 +#define STATUS_LED_STATE STATUS_LED_ON
9670 +#define STATUS_LED_PERIOD 1
9671 +#endif
9672 +#ifndef STATUS_LED_STATE1
9673 +#define STATUS_LED_STATE1 STATUS_LED_OFF
9674 +#define STATUS_LED_PERIOD1 1
9675 +#endif
9676 +#ifndef STATUS_LED_STATE2
9677 +#define STATUS_LED_STATE2 STATUS_LED_OFF
9678 +#define STATUS_LED_PERIOD2 1
9679 +#endif
9680 +#ifndef STATUS_LED_STATE3
9681 +#define STATUS_LED_STATE3 STATUS_LED_OFF
9682 +#define STATUS_LED_PERIOD3 1
9683 +#endif
9684 +#define CONFIG_BOARD_SPECIFIC_LED
9685 +#define CONFIG_CMD_LED
9686 +#endif
9687 +#endif
9688 +
9689 +/* Define this to have serial channel 1 (UART0) redirected to SD port */
9690 +/* #define CONFIG_UART0_PORT_F */
9691 +
9692 +#ifndef CONFIG_CONS_INDEX
9693 +#define CONFIG_CONS_INDEX 1 /* UART0 */
9694 +#endif
9695 +
9696 +/* Ethernet support */
9697 +#ifdef CONFIG_SUNXI_EMAC
9698 +#define CONFIG_MII /* MII PHY management */
9699 +#endif
9700 +
9701 +#ifdef CONFIG_SUNXI_GMAC
9702 +#define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */
9703 +#define CONFIG_DW_AUTONEG
9704 +#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
9705 +#define CONFIG_PHY_ADDR 1
9706 +#define CONFIG_MII /* MII PHY management */
9707 +#define CONFIG_PHYLIB
9708 +#endif
9709 +
9710 +#ifdef CONFIG_CMD_NET
9711 +#define CONFIG_CMD_NFS
9712 +#define CONFIG_CMD_DNS
9713 +#define CONFIG_NETCONSOLE
9714 +#define CONFIG_BOOTP_DNS2
9715 +#define CONFIG_BOOTP_SEND_HOSTNAME
9716 +#endif
9717 +
9718 +#if !defined CONFIG_ENV_IS_IN_MMC && \
9719 + !defined CONFIG_ENV_IS_IN_NAND && \
9720 + !defined CONFIG_ENV_IS_IN_FAT && \
9721 + !defined CONFIG_ENV_IS_IN_SPI_FLASH
9722 +#define CONFIG_ENV_IS_NOWHERE
9723 +#endif
9724 +
9725 +#define CONFIG_MISC_INIT_R
9726 +
9727 +#ifndef CONFIG_SPL_BUILD
9728 +#include <config_distro_defaults.h>
9729 +#endif
9730 +
9731 +#endif /* _SUNXI_COMMON_CONFIG_H */
9732 diff -ruN u-boot-2014.04/include/netdev.h u-boot-sunxi/include/netdev.h
9733 --- u-boot-2014.04/include/netdev.h 2014-04-14 21:19:24.000000000 +0200
9734 +++ u-boot-sunxi/include/netdev.h 2014-09-06 16:58:36.485953106 +0200
9735 @@ -79,7 +79,8 @@
9736 int skge_initialize(bd_t *bis);
9737 int smc91111_initialize(u8 dev_num, int base_addr);
9738 int smc911x_initialize(u8 dev_num, int base_addr);
9739 -int sunxi_wemac_initialize(bd_t *bis);
9740 +int sunxi_emac_initialize(bd_t *bis);
9741 +int sunxi_gmac_initialize(bd_t *bis);
9742 int tsi108_eth_initialize(bd_t *bis);
9743 int uec_standard_init(bd_t *bis);
9744 int uli526x_initialize(bd_t *bis);
9745 diff -ruN u-boot-2014.04/Makefile u-boot-sunxi/Makefile
9746 --- u-boot-2014.04/Makefile 2014-04-14 21:19:24.000000000 +0200
9747 +++ u-boot-sunxi/Makefile 2014-09-06 16:58:35.065953148 +0200
9748 @@ -870,6 +870,13 @@
9749 u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
9750 $(call if_changed,pad_cat)
9751
9752 +ifneq ($(CONFIG_SUNXI),)
9753 +OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
9754 + --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
9755 +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
9756 + $(call if_changed,pad_cat)
9757 +endif
9758 +
9759 ifneq ($(CONFIG_TEGRA),)
9760 OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE)
9761 u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE
9762 @@ -1081,6 +1088,9 @@
9763 spl/u-boot-spl: tools prepare
9764 $(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all
9765
9766 +spl/sunxi-spl.bin: spl/u-boot-spl
9767 + @:
9768 +
9769 tpl/u-boot-tpl.bin: tools prepare
9770 $(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y
9771
9772 diff -ruN u-boot-2014.04/mkconfig u-boot-sunxi/mkconfig
9773 --- u-boot-2014.04/mkconfig 2014-04-14 21:19:24.000000000 +0200
9774 +++ u-boot-sunxi/mkconfig 2014-09-06 16:58:36.509953105 +0200
9775 @@ -174,6 +174,7 @@
9776 echo "#define CONFIG_SYS_ARCH \"${arch}\"" >> config.h
9777 echo "#define CONFIG_SYS_CPU \"${cpu}\"" >> config.h
9778 echo "#define CONFIG_SYS_BOARD \"${board}\"" >> config.h
9779 +echo "#define CONFIG_SYS_TARGET \"${BOARD_NAME}\"" >> config.h
9780
9781 [ "${vendor}" ] && echo "#define CONFIG_SYS_VENDOR \"${vendor}\"" >> config.h
9782
9783 diff -ruN u-boot-2014.04/snapshot.commit u-boot-sunxi/snapshot.commit
9784 --- u-boot-2014.04/snapshot.commit 2014-04-14 21:19:24.000000000 +0200
9785 +++ u-boot-sunxi/snapshot.commit 2014-09-06 16:58:36.521953105 +0200
9786 @@ -1 +1 @@
9787 -dda0dbfc69f3d560c87f5be85f127ed862ea6721 Mon, 14 Apr 2014 15:19:24 -0400
9788 +$Format:%H %cD$
9789 diff -ruN u-boot-2014.04/spl/Makefile u-boot-sunxi/spl/Makefile
9790 --- u-boot-2014.04/spl/Makefile 2014-04-14 21:19:24.000000000 +0200
9791 +++ u-boot-sunxi/spl/Makefile 2014-09-06 16:58:36.521953105 +0200
9792 @@ -188,6 +188,12 @@
9793 ALL-y += $(obj)/$(BOARD)-spl.bin
9794 endif
9795
9796 +ifdef CONFIG_SUNXI
9797 +ifndef CONFIG_SPL_FEL
9798 +ALL-y += $(obj)/sunxi-spl.bin
9799 +endif
9800 +endif
9801 +
9802 all: $(ALL-y)
9803
9804 ifdef CONFIG_SAMSUNG
9805 @@ -215,6 +221,13 @@
9806 LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
9807 endif
9808
9809 +ifdef CONFIG_SUNXI
9810 +quiet_cmd_mksunxiboot = MKSUNXI $@
9811 +cmd_mksunxiboot = $(objtree)/tools/mksunxiboot $< $@
9812 +$(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin
9813 + $(call if_changed,mksunxiboot)
9814 +endif
9815 +
9816 quiet_cmd_u-boot-spl = LD $@
9817 cmd_u-boot-spl = cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
9818 $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \
9819 diff -ruN u-boot-2014.04/tools/.gitignore u-boot-sunxi/tools/.gitignore
9820 --- u-boot-2014.04/tools/.gitignore 2014-04-14 21:19:24.000000000 +0200
9821 +++ u-boot-sunxi/tools/.gitignore 2014-09-06 16:58:36.521953105 +0200
9822 @@ -9,6 +9,7 @@
9823 /mkexynosspl
9824 /mpc86x_clk
9825 /mxsboot
9826 +/mksunxiboot
9827 /ncb
9828 /proftool
9829 /relocate-rela
9830 diff -ruN u-boot-2014.04/tools/Makefile u-boot-sunxi/tools/Makefile
9831 --- u-boot-2014.04/tools/Makefile 2014-04-14 21:19:24.000000000 +0200
9832 +++ u-boot-sunxi/tools/Makefile 2014-09-06 16:58:36.521953105 +0200
9833 @@ -120,6 +120,8 @@
9834 hostprogs-$(CONFIG_MX28) += mxsboot$(SFX)
9835 HOSTCFLAGS_mxsboot$(SFX).o := -pedantic
9836
9837 +hostprogs-$(CONFIG_SUNXI) += mksunxiboot$(SFX)
9838 +
9839 hostprogs-$(CONFIG_NETCONSOLE) += ncb$(SFX)
9840 hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
9841
9842 diff -ruN u-boot-2014.04/tools/mksunxiboot.c u-boot-sunxi/tools/mksunxiboot.c
9843 --- u-boot-2014.04/tools/mksunxiboot.c 1970-01-01 01:00:00.000000000 +0100
9844 +++ u-boot-sunxi/tools/mksunxiboot.c 2014-09-06 16:58:36.529953105 +0200
9845 @@ -0,0 +1,140 @@
9846 +/*
9847 + * (C) Copyright 2007-2011
9848 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
9849 + * Tom Cubie <tangliang@allwinnertech.com>
9850 + *
9851 + * a simple tool to generate bootable image for sunxi platform.
9852 + *
9853 + * SPDX-License-Identifier: GPL-2.0+
9854 + */
9855 +#include <fcntl.h>
9856 +#include <stdio.h>
9857 +#include <unistd.h>
9858 +#include <stdlib.h>
9859 +#include <string.h>
9860 +#include <errno.h>
9861 +#include <sys/types.h>
9862 +#include <sys/stat.h>
9863 +
9864 +/* boot head definition from sun4i boot code */
9865 +struct boot_file_head {
9866 + uint32_t b_instruction; /* one intruction jumping to real code */
9867 + uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */
9868 + uint32_t check_sum; /* generated by PC */
9869 + uint32_t length; /* generated by PC */
9870 + /*
9871 + * We use a simplified header, only filling in what is needed
9872 + * by the boot ROM. To be compatible with Allwinner tools we
9873 + * would need to implement the proper fields here instead of
9874 + * padding.
9875 + */
9876 + uint8_t pad[12]; /* align to 32 bytes */
9877 +};
9878 +
9879 +#define BOOT0_MAGIC "eGON.BT0"
9880 +#define STAMP_VALUE 0x5F0A6C39
9881 +
9882 +/* check sum functon from sun4i boot code */
9883 +int gen_check_sum(struct boot_file_head *head_p)
9884 +{
9885 + uint32_t length;
9886 + uint32_t *buf;
9887 + uint32_t loop;
9888 + uint32_t i;
9889 + uint32_t sum;
9890 +
9891 + length = head_p->length;
9892 + if ((length & 0x3) != 0) /* must 4-byte-aligned */
9893 + return -1;
9894 + buf = (uint32_t *)head_p;
9895 + head_p->check_sum = STAMP_VALUE; /* fill stamp */
9896 + loop = length >> 2;
9897 +
9898 + /* calculate the sum */
9899 + for (i = 0, sum = 0; i < loop; i++)
9900 + sum += buf[i];
9901 +
9902 + /* write back check sum */
9903 + head_p->check_sum = sum;
9904 +
9905 + return 0;
9906 +}
9907 +
9908 +#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1)
9909 +#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))
9910 +
9911 +#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */
9912 +#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head))
9913 +#define BLOCK_SIZE 512
9914 +
9915 +struct boot_img {
9916 + struct boot_file_head header;
9917 + char code[SRAM_LOAD_MAX_SIZE];
9918 + char pad[BLOCK_SIZE];
9919 +};
9920 +
9921 +int main(int argc, char *argv[])
9922 +{
9923 + int fd_in, fd_out;
9924 + struct boot_img img;
9925 + unsigned file_size;
9926 + int count;
9927 +
9928 + if (argc < 2) {
9929 + printf("\tThis program makes an input bin file to sun4i " \
9930 + "bootable image.\n" \
9931 + "\tUsage: %s input_file out_putfile\n", argv[0]);
9932 + return EXIT_FAILURE;
9933 + }
9934 +
9935 + fd_in = open(argv[1], O_RDONLY);
9936 + if (fd_in < 0) {
9937 + perror("Open input file");
9938 + return EXIT_FAILURE;
9939 + }
9940 +
9941 + memset(img.pad, 0, BLOCK_SIZE);
9942 +
9943 + /* get input file size */
9944 + file_size = lseek(fd_in, 0, SEEK_END);
9945 +
9946 + if (file_size > SRAM_LOAD_MAX_SIZE) {
9947 + fprintf(stderr, "ERROR: File too large!\n");
9948 + return EXIT_FAILURE;
9949 + }
9950 +
9951 + fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666);
9952 + if (fd_out < 0) {
9953 + perror("Open output file");
9954 + return EXIT_FAILURE;
9955 + }
9956 +
9957 + /* read file to buffer to calculate checksum */
9958 + lseek(fd_in, 0, SEEK_SET);
9959 + count = read(fd_in, img.code, file_size);
9960 + if (count != file_size) {
9961 + perror("Reading input image");
9962 + return EXIT_FAILURE;
9963 + }
9964 +
9965 + /* fill the header */
9966 + img.header.b_instruction = /* b instruction */
9967 + 0xEA000000 | /* jump to the first instr after the header */
9968 + ((sizeof(struct boot_file_head) / sizeof(int) - 2)
9969 + & 0x00FFFFFF);
9970 + memcpy(img.header.magic, BOOT0_MAGIC, 8); /* no '0' termination */
9971 + img.header.length =
9972 + ALIGN(file_size + sizeof(struct boot_file_head), BLOCK_SIZE);
9973 + gen_check_sum(&img.header);
9974 +
9975 + count = write(fd_out, &img, img.header.length);
9976 + if (count != img.header.length) {
9977 + perror("Writing output");
9978 + return EXIT_FAILURE;
9979 + }
9980 +
9981 + close(fd_in);
9982 + close(fd_out);
9983 +
9984 + return EXIT_SUCCESS;
9985 +}
9986 diff -ruN u-boot-2014.04/tools/mksunxiboot.README u-boot-sunxi/tools/mksunxiboot.README
9987 --- u-boot-2014.04/tools/mksunxiboot.README 1970-01-01 01:00:00.000000000 +0100
9988 +++ u-boot-sunxi/tools/mksunxiboot.README 2014-09-06 16:58:36.529953105 +0200
9989 @@ -0,0 +1,13 @@
9990 +This program make a arm binary file can be loaded by Allwinner A10 and related
9991 +chips from storage media such as nand and mmc.
9992 +
9993 +More information about A10 boot, please refer to
9994 +http://rhombus-tech.net/allwinner_a10/a10_boot_process/
9995 +
9996 +To compile this program, just type make, you will get 'mksunxiboot'.
9997 +
9998 +To use it,
9999 +$./mksunxiboot u-boot.bin u-boot-mmc.bin
10000 +then you can write it to a mmc card with dd.
10001 +$sudo dd if=u-boot-mmc.bin of=/dev/sdb bs=1024 seek=8
10002 +then insert your mmc card to your A10 tablet, you can boot from mmc card.
OpenWrt Source Repository