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lantiq: ltq-adsl: Do not leak user space CFLAGS into kernel space
[openwrt/openwrt.git] / package / kernel / lantiq / ltq-adsl / patches / 100-dsl_compat.patch
1 --- a/src/include/drv_dsl_cpe_device_danube.h
2 +++ b/src/include/drv_dsl_cpe_device_danube.h
3 @@ -24,7 +24,7 @@
4 #include "drv_dsl_cpe_simulator_danube.h"
5 #else
6 /* Include for the low level driver interface header file */
7 -#include "asm/ifx/ifx_mei_bsp.h"
8 +#include "ifxmips_mei_interface.h"
9 #endif /* defined(DSL_CPE_SIMULATOR_DRIVER) && defined(WIN32)*/
10
11 #define DSL_MAX_LINE_NUMBER 1
12 --- a/src/common/drv_dsl_cpe_os_linux.c
13 +++ b/src/common/drv_dsl_cpe_os_linux.c
14 @@ -11,6 +11,7 @@
15 #ifdef __LINUX__
16
17 #define DSL_INTERN
18 +#include <linux/device.h>
19
20 #include "drv_dsl_cpe_api.h"
21 #include "drv_dsl_cpe_api_ioctl.h"
22 @@ -34,9 +35,13 @@ static const char* dsl_cpe_api_version =
23 static DSL_ssize_t DSL_DRV_Write(DSL_DRV_file_t *pFile, const DSL_char_t * pBuf,
24 DSL_DRV_size_t nSize, DSL_DRV_offset_t * pLoff);
25
26 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
27 static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode, DSL_DRV_file_t * pFile,
28 DSL_uint_t nCommand, unsigned long nArg);
29 -
30 +#else
31 +static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_file_t * pFile,
32 + DSL_uint_t nCommand, unsigned long nArg);
33 +#endif
34 static int DSL_DRV_Open(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);
35
36 static int DSL_DRV_Release(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);
37 @@ -72,7 +77,11 @@ static struct file_operations dslCpeApiO
38 open: DSL_DRV_Open,
39 release: DSL_DRV_Release,
40 write: DSL_DRV_Write,
41 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
42 ioctl: DSL_DRV_Ioctls,
43 +#else
44 + unlocked_ioctl: DSL_DRV_Ioctls,
45 +#endif
46 poll: DSL_DRV_Poll
47 };
48 #else
49 @@ -168,10 +177,17 @@ static DSL_ssize_t DSL_DRV_Write(DSL_DRV
50 \return Success or failure.
51 \ingroup Internal
52 */
53 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
54 static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_inode_t * pINode,
55 DSL_DRV_file_t * pFile,
56 DSL_uint_t nCommand,
57 unsigned long nArg)
58 +#else
59 +static DSL_int_t DSL_DRV_Ioctls(
60 + DSL_DRV_file_t * pFile,
61 + DSL_uint_t nCommand,
62 + unsigned long nArg)
63 +#endif
64 {
65 DSL_int_t nErr=0;
66 DSL_boolean_t bIsInKernel;
67 @@ -216,16 +232,7 @@ static DSL_int_t DSL_DRV_Ioctls(DSL_DRV_
68 }
69 }
70 }
71 -
72 - if (pINode == DSL_NULL)
73 - {
74 - bIsInKernel = DSL_TRUE;
75 - }
76 - else
77 - {
78 - bIsInKernel = DSL_FALSE;
79 - }
80 -
81 + bIsInKernel = DSL_FALSE;
82 if ( (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API) ||
83 (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_G997) ||
84 (_IOC_TYPE(nCommand) == DSL_IOC_MAGIC_CPE_API_PM) ||
85 @@ -1058,6 +1065,7 @@ static void DSL_DRV_DebugInit(void)
86 /* Entry point of driver */
87 int __init DSL_ModuleInit(void)
88 {
89 + struct class *dsl_class;
90 DSL_int_t i;
91
92 printk(DSL_DRV_CRLF DSL_DRV_CRLF "Infineon CPE API Driver version: %s" DSL_DRV_CRLF,
93 @@ -1104,7 +1112,8 @@ int __init DSL_ModuleInit(void)
94 }
95
96 DSL_DRV_DevNodeInit();
97 -
98 + dsl_class = class_create(THIS_MODULE, "dsl_cpe_api");
99 + device_create(dsl_class, NULL, MKDEV(DRV_DSL_CPE_API_DEV_MAJOR, 0), NULL, "dsl_cpe_api");
100 return 0;
101 }
102
103 --- a/src/include/drv_dsl_cpe_os_linux.h
104 +++ b/src/include/drv_dsl_cpe_os_linux.h
105 @@ -16,18 +16,18 @@
106 extern "C" {
107 #endif
108
109 -#include <asm/ioctl.h>
110 -#include <linux/autoconf.h>
111 #include <linux/module.h>
112 #include <linux/kernel.h>
113 #include <linux/init.h>
114 #include <linux/ctype.h>
115 #include <linux/version.h>
116 #include <linux/spinlock.h>
117 +#include <linux/sched.h>
118
119 -
120 -#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,17))
121 - #include <linux/utsrelease.h>
122 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))
123 +#include <linux/utsrelease.h>
124 +#else
125 +#include <generated/utsrelease.h>
126 #endif
127
128 #include <linux/types.h>
129 @@ -39,7 +39,8 @@
130 #include <linux/delay.h>
131 #include <linux/poll.h>
132 #include <asm/uaccess.h>
133 -#include <linux/smp_lock.h>
134 +//#include <linux/smp_lock.h>
135 +#include <asm/ioctl.h>
136
137 #ifdef INCLUDE_DSL_CPE_API_IFXOS_SUPPORT
138 /** IFXOS includes*/
139 --- /dev/null
140 +++ b/src/ifxmips_mei_interface.h
141 @@ -0,0 +1,702 @@
142 +/******************************************************************************
143 +
144 + Copyright (c) 2009
145 + Infineon Technologies AG
146 + Am Campeon 1-12; 81726 Munich, Germany
147 +
148 + For licensing information, see the file 'LICENSE' in the root folder of
149 + this software module.
150 +
151 +******************************************************************************/
152 +
153 +#ifndef IFXMIPS_MEI_H
154 +#define IFXMIPS_MEI_H
155 +
156 +//#define CONFIG_AMAZON_SE 1
157 +//#define CONFIG_DANUBE 1
158 +//#define CONFIG_AR9 1
159 +
160 +#if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9)
161 +#error Platform undefined!!!
162 +#endif
163 +
164 +#ifdef IFX_MEI_BSP
165 +/** This is the character datatype. */
166 +typedef char DSL_char_t;
167 +/** This is the unsigned 8-bit datatype. */
168 +typedef unsigned char DSL_uint8_t;
169 +/** This is the signed 8-bit datatype. */
170 +typedef signed char DSL_int8_t;
171 +/** This is the unsigned 16-bit datatype. */
172 +typedef unsigned short DSL_uint16_t;
173 +/** This is the signed 16-bit datatype. */
174 +typedef signed short DSL_int16_t;
175 +/** This is the unsigned 32-bit datatype. */
176 +typedef unsigned long DSL_uint32_t;
177 +/** This is the signed 32-bit datatype. */
178 +typedef signed long DSL_int32_t;
179 +/** This is the float datatype. */
180 +typedef float DSL_float_t;
181 +/** This is the void datatype. */
182 +typedef void DSL_void_t;
183 +/** integer type, width is depending on processor arch */
184 +typedef int DSL_int_t;
185 +/** unsigned integer type, width is depending on processor arch */
186 +typedef unsigned int DSL_uint_t;
187 +typedef struct file DSL_DRV_file_t;
188 +typedef struct inode DSL_DRV_inode_t;
189 +
190 +/**
191 + * Defines all possible CMV groups
192 + * */
193 +typedef enum {
194 + DSL_CMV_GROUP_CNTL = 1,
195 + DSL_CMV_GROUP_STAT = 2,
196 + DSL_CMV_GROUP_INFO = 3,
197 + DSL_CMV_GROUP_TEST = 4,
198 + DSL_CMV_GROUP_OPTN = 5,
199 + DSL_CMV_GROUP_RATE = 6,
200 + DSL_CMV_GROUP_PLAM = 7,
201 + DSL_CMV_GROUP_CNFG = 8
202 +} DSL_CmvGroup_t;
203 +/**
204 + * Defines all opcode types
205 + * */
206 +typedef enum {
207 + H2D_CMV_READ = 0x00,
208 + H2D_CMV_WRITE = 0x04,
209 + H2D_CMV_INDICATE_REPLY = 0x10,
210 + H2D_ERROR_OPCODE_UNKNOWN =0x20,
211 + H2D_ERROR_CMV_UNKNOWN =0x30,
212 +
213 + D2H_CMV_READ_REPLY =0x01,
214 + D2H_CMV_WRITE_REPLY = 0x05,
215 + D2H_CMV_INDICATE = 0x11,
216 + D2H_ERROR_OPCODE_UNKNOWN = 0x21,
217 + D2H_ERROR_CMV_UNKNOWN = 0x31,
218 + D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41,
219 + D2H_ERROR_CMV_WRITE_ONLY = 0x51,
220 + D2H_ERROR_CMV_READ_ONLY = 0x61,
221 +
222 + H2D_DEBUG_READ_DM = 0x02,
223 + H2D_DEBUG_READ_PM = 0x06,
224 + H2D_DEBUG_WRITE_DM = 0x0a,
225 + H2D_DEBUG_WRITE_PM = 0x0e,
226 +
227 + D2H_DEBUG_READ_DM_REPLY = 0x03,
228 + D2H_DEBUG_READ_FM_REPLY = 0x07,
229 + D2H_DEBUG_WRITE_DM_REPLY = 0x0b,
230 + D2H_DEBUG_WRITE_FM_REPLY = 0x0f,
231 + D2H_ERROR_ADDR_UNKNOWN = 0x33,
232 +
233 + D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1
234 +} DSL_CmvOpcode_t;
235 +
236 +/* mutex macros */
237 +#define MEI_MUTEX_INIT(id,flag) \
238 + sema_init(&id,flag)
239 +#define MEI_MUTEX_LOCK(id) \
240 + down_interruptible(&id)
241 +#define MEI_MUTEX_UNLOCK(id) \
242 + up(&id)
243 +#define MEI_WAIT(ms) \
244 + {\
245 + set_current_state(TASK_INTERRUPTIBLE);\
246 + schedule_timeout(ms);\
247 + }
248 +#define MEI_INIT_WAKELIST(name,queue) \
249 + init_waitqueue_head(&queue)
250 +
251 +/* wait for an event, timeout is measured in ms */
252 +#define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
253 + interruptible_sleep_on_timeout(&ev,timeout * HZ / 1000)
254 +#define MEI_WAKEUP_EVENT(ev)\
255 + wake_up_interruptible(&ev)
256 +#endif /* IFX_MEI_BSP */
257 +
258 +/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
259 +#define ME_DX_DATA (0x0000)
260 +#define ME_VERSION (0x0004)
261 +#define ME_ARC_GP_STAT (0x0008)
262 +#define ME_DX_STAT (0x000C)
263 +#define ME_DX_AD (0x0010)
264 +#define ME_DX_MWS (0x0014)
265 +#define ME_ME2ARC_INT (0x0018)
266 +#define ME_ARC2ME_STAT (0x001C)
267 +#define ME_ARC2ME_MASK (0x0020)
268 +#define ME_DBG_WR_AD (0x0024)
269 +#define ME_DBG_RD_AD (0x0028)
270 +#define ME_DBG_DATA (0x002C)
271 +#define ME_DBG_DECODE (0x0030)
272 +#define ME_CONFIG (0x0034)
273 +#define ME_RST_CTRL (0x0038)
274 +#define ME_DBG_MASTER (0x003C)
275 +#define ME_CLK_CTRL (0x0040)
276 +#define ME_BIST_CTRL (0x0044)
277 +#define ME_BIST_STAT (0x0048)
278 +#define ME_XDATA_BASE_SH (0x004c)
279 +#define ME_XDATA_BASE (0x0050)
280 +#define ME_XMEM_BAR_BASE (0x0054)
281 +#define ME_XMEM_BAR0 (0x0054)
282 +#define ME_XMEM_BAR1 (0x0058)
283 +#define ME_XMEM_BAR2 (0x005C)
284 +#define ME_XMEM_BAR3 (0x0060)
285 +#define ME_XMEM_BAR4 (0x0064)
286 +#define ME_XMEM_BAR5 (0x0068)
287 +#define ME_XMEM_BAR6 (0x006C)
288 +#define ME_XMEM_BAR7 (0x0070)
289 +#define ME_XMEM_BAR8 (0x0074)
290 +#define ME_XMEM_BAR9 (0x0078)
291 +#define ME_XMEM_BAR10 (0x007C)
292 +#define ME_XMEM_BAR11 (0x0080)
293 +#define ME_XMEM_BAR12 (0x0084)
294 +#define ME_XMEM_BAR13 (0x0088)
295 +#define ME_XMEM_BAR14 (0x008C)
296 +#define ME_XMEM_BAR15 (0x0090)
297 +#define ME_XMEM_BAR16 (0x0094)
298 +
299 +#define WHILE_DELAY 20000
300 +/*
301 +** Define where in ME Processor's memory map the Stratify chip lives
302 +*/
303 +
304 +#define MAXSWAPSIZE (8 * 1024) //8k *(32bits)
305 +
306 +// Mailboxes
307 +#define MSG_LENGTH 16 // x16 bits
308 +#define YES_REPLY 1
309 +#define NO_REPLY 0
310 +
311 +#define CMV_TIMEOUT 1000 //jiffies
312 +
313 +// Block size per BAR
314 +#define SDRAM_SEGMENT_SIZE (64*1024)
315 +// Number of Bar registers
316 +#define MAX_BAR_REGISTERS (17)
317 +
318 +#define XDATA_REGISTER (15)
319 +
320 +// ARC register addresss
321 +#define ARC_STATUS 0x0
322 +#define ARC_LP_START 0x2
323 +#define ARC_LP_END 0x3
324 +#define ARC_DEBUG 0x5
325 +#define ARC_INT_MASK 0x10A
326 +
327 +#define IRAM0_BASE (0x00000)
328 +#define IRAM1_BASE (0x04000)
329 +#if defined(CONFIG_DANUBE)
330 +#define BRAM_BASE (0x0A000)
331 +#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
332 +#define BRAM_BASE (0x08000)
333 +#endif
334 +#define XRAM_BASE (0x18000)
335 +#define YRAM_BASE (0x1A000)
336 +#define EXT_MEM_BASE (0x80000)
337 +#define ARC_GPIO_CTRL (0xC030)
338 +#define ARC_GPIO_DATA (0xC034)
339 +
340 +#define IRAM0_SIZE (16*1024)
341 +#define IRAM1_SIZE (16*1024)
342 +#define BRAM_SIZE (12*1024)
343 +#define XRAM_SIZE (8*1024)
344 +#define YRAM_SIZE (8*1024)
345 +#define EXT_MEM_SIZE (1536*1024)
346 +
347 +#define ADSL_BASE (0x20000)
348 +#define CRI_BASE (ADSL_BASE + 0x11F00)
349 +#define CRI_CCR0 (CRI_BASE + 0x00)
350 +#define CRI_RST (CRI_BASE + 0x04*4)
351 +#define ADSL_DILV_BASE (ADSL_BASE+0x20000)
352 +
353 +//
354 +#define IRAM0_ADDR_BIT_MASK 0xFFF
355 +#define IRAM1_ADDR_BIT_MASK 0xFFF
356 +#define BRAM_ADDR_BIT_MASK 0xFFF
357 +#define RX_DILV_ADDR_BIT_MASK 0x1FFF
358 +
359 +/*** Bit definitions ***/
360 +#define ARC_AUX_HALT (1 << 25)
361 +#define ARC_DEBUG_HALT (1 << 1)
362 +#define FALSE 0
363 +#define TRUE 1
364 +#define BIT0 (1<<0)
365 +#define BIT1 (1<<1)
366 +#define BIT2 (1<<2)
367 +#define BIT3 (1<<3)
368 +#define BIT4 (1<<4)
369 +#define BIT5 (1<<5)
370 +#define BIT6 (1<<6)
371 +#define BIT7 (1<<7)
372 +#define BIT8 (1<<8)
373 +#define BIT9 (1<<9)
374 +#define BIT10 (1<<10)
375 +#define BIT11 (1<<11)
376 +#define BIT12 (1<<12)
377 +#define BIT13 (1<<13)
378 +#define BIT14 (1<<14)
379 +#define BIT15 (1<<15)
380 +#define BIT16 (1<<16)
381 +#define BIT17 (1<<17)
382 +#define BIT18 (1<<18)
383 +#define BIT19 (1<<19)
384 +#define BIT20 (1<<20)
385 +#define BIT21 (1<<21)
386 +#define BIT22 (1<<22)
387 +#define BIT23 (1<<23)
388 +#define BIT24 (1<<24)
389 +#define BIT25 (1<<25)
390 +#define BIT26 (1<<26)
391 +#define BIT27 (1<<27)
392 +#define BIT28 (1<<28)
393 +#define BIT29 (1<<29)
394 +#define BIT30 (1<<30)
395 +#define BIT31 (1<<31)
396 +
397 +// CRI_CCR0 Register definitions
398 +#define CLK_2M_MODE_ENABLE BIT6
399 +#define ACL_CLK_MODE_ENABLE BIT4
400 +#define FDF_CLK_MODE_ENABLE BIT2
401 +#define STM_CLK_MODE_ENABLE BIT0
402 +
403 +// CRI_RST Register definitions
404 +#define FDF_SRST BIT3
405 +#define MTE_SRST BIT2
406 +#define FCI_SRST BIT1
407 +#define AAI_SRST BIT0
408 +
409 +// MEI_TO_ARC_INTERRUPT Register definitions
410 +#define MEI_TO_ARC_INT1 BIT3
411 +#define MEI_TO_ARC_INT0 BIT2
412 +#define MEI_TO_ARC_CS_DONE BIT1 //need to check
413 +#define MEI_TO_ARC_MSGAV BIT0
414 +
415 +// ARC_TO_MEI_INTERRUPT Register definitions
416 +#define ARC_TO_MEI_INT1 BIT8
417 +#define ARC_TO_MEI_INT0 BIT7
418 +#define ARC_TO_MEI_CS_REQ BIT6
419 +#define ARC_TO_MEI_DBG_DONE BIT5
420 +#define ARC_TO_MEI_MSGACK BIT4
421 +#define ARC_TO_MEI_NO_ACCESS BIT3
422 +#define ARC_TO_MEI_CHECK_AAITX BIT2
423 +#define ARC_TO_MEI_CHECK_AAIRX BIT1
424 +#define ARC_TO_MEI_MSGAV BIT0
425 +
426 +// ARC_TO_MEI_INTERRUPT_MASK Register definitions
427 +#define GP_INT1_EN BIT8
428 +#define GP_INT0_EN BIT7
429 +#define CS_REQ_EN BIT6
430 +#define DBG_DONE_EN BIT5
431 +#define MSGACK_EN BIT4
432 +#define NO_ACC_EN BIT3
433 +#define AAITX_EN BIT2
434 +#define AAIRX_EN BIT1
435 +#define MSGAV_EN BIT0
436 +
437 +#define MEI_SOFT_RESET BIT0
438 +
439 +#define HOST_MSTR BIT0
440 +
441 +#define JTAG_MASTER_MODE 0x0
442 +#define MEI_MASTER_MODE HOST_MSTR
443 +
444 +// MEI_DEBUG_DECODE Register definitions
445 +#define MEI_DEBUG_DEC_MASK (0x3)
446 +#define MEI_DEBUG_DEC_AUX_MASK (0x0)
447 +#define ME_DBG_DECODE_DMP1_MASK (0x1)
448 +#define MEI_DEBUG_DEC_DMP2_MASK (0x2)
449 +#define MEI_DEBUG_DEC_CORE_MASK (0x3)
450 +
451 +#define AUX_STATUS (0x0)
452 +#define AUX_ARC_GPIO_CTRL (0x10C)
453 +#define AUX_ARC_GPIO_DATA (0x10D)
454 +// ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
455 +// page swap requests.
456 +#if defined(CONFIG_DANUBE)
457 +#define OMBOX_BASE 0xDF80
458 +#define ARC_TO_MEI_MAILBOX 0xDFA0
459 +#define IMBOX_BASE 0xDFC0
460 +#define MEI_TO_ARC_MAILBOX 0xDFD0
461 +#elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
462 +#define OMBOX_BASE 0xAF80
463 +#define ARC_TO_MEI_MAILBOX 0xAFA0
464 +#define IMBOX_BASE 0xAFC0
465 +#define MEI_TO_ARC_MAILBOX 0xAFD0
466 +#endif
467 +
468 +#define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
469 +#define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
470 +#define OMBOX1 (OMBOX_BASE+0x4)
471 +
472 +// Codeswap request messages are indicated by setting BIT31
473 +#define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
474 +
475 +// Clear Eoc messages received are indicated by setting BIT17
476 +#define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
477 +#define OMB_REBOOT_INTERRUPT_CODE (1 << 18)
478 +
479 +/*
480 +** Swap page header
481 +*/
482 +// Page must be loaded at boot time if size field has BIT31 set
483 +#define BOOT_FLAG (BIT31)
484 +#define BOOT_FLAG_MASK ~BOOT_FLAG
485 +
486 +#define FREE_RELOAD 1
487 +#define FREE_SHOWTIME 2
488 +#define FREE_ALL 3
489 +
490 +// marcos
491 +#define IFX_MEI_WRITE_REGISTER_L(data,addr) *((volatile u32*)(addr)) = (u32)(data)
492 +#define IFX_MEI_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
493 +#define SET_BIT(reg, mask) reg |= (mask)
494 +#define CLEAR_BIT(reg, mask) reg &= (~mask)
495 +#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
496 +//#define SET_BITS(reg, mask) SET_BIT(reg, mask)
497 +#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
498 +
499 +#define ALIGN_SIZE ( 1L<<10 ) //1K size align
500 +#define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
501 +
502 +// swap marco
503 +#define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
504 +#define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
505 +
506 +
507 +#ifdef CONFIG_PROC_FS
508 +typedef struct reg_entry
509 +{
510 + int *flag;
511 + char name[30]; /* big enough to hold names */
512 + char description[100]; /* big enough to hold description */
513 + unsigned short low_ino;
514 +} reg_entry_t;
515 +#endif
516 +// Swap page header describes size in 32-bit words, load location, and image offset
517 +// for program and/or data segments
518 +typedef struct _arc_swp_page_hdr {
519 + u32 p_offset; //Offset bytes of progseg from beginning of image
520 + u32 p_dest; //Destination addr of progseg on processor
521 + u32 p_size; //Size in 32-bitwords of program segment
522 + u32 d_offset; //Offset bytes of dataseg from beginning of image
523 + u32 d_dest; //Destination addr of dataseg on processor
524 + u32 d_size; //Size in 32-bitwords of data segment
525 +} ARC_SWP_PAGE_HDR;
526 +
527 +/*
528 +** Swap image header
529 +*/
530 +#define GET_PROG 0 // Flag used for program mem segment
531 +#define GET_DATA 1 // Flag used for data mem segment
532 +
533 +// Image header contains size of image, checksum for image, and count of
534 +// page headers. Following that are 'count' page headers followed by
535 +// the code and/or data segments to be loaded
536 +typedef struct _arc_img_hdr {
537 + u32 size; // Size of binary image in bytes
538 + u32 checksum; // Checksum for image
539 + u32 count; // Count of swp pages in image
540 + ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
541 +} ARC_IMG_HDR;
542 +
543 +typedef struct smmu_mem_info {
544 + int type;
545 + int boot;
546 + unsigned long nCopy;
547 + unsigned long size;
548 + unsigned char *address;
549 + unsigned char *org_address;
550 +} smmu_mem_info_t;
551 +
552 +#ifdef __KERNEL__
553 +typedef struct ifx_mei_device_private {
554 + int modem_ready;
555 + int arcmsgav;
556 + int cmv_reply;
557 + int cmv_waiting;
558 + // Mei to ARC CMV count, reply count, ARC Indicator count
559 + int modem_ready_cnt;
560 + int cmv_count;
561 + int reply_count;
562 + unsigned long image_size;
563 + int nBar;
564 + u16 Recent_indicator[MSG_LENGTH];
565 +
566 + u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
567 +
568 + smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
569 + ARC_IMG_HDR *img_hdr;
570 + // to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
571 + wait_queue_head_t wait_queue_arcmsgav;
572 + wait_queue_head_t wait_queue_modemready;
573 + struct semaphore mei_cmv_sema;
574 +} ifx_mei_device_private_t;
575 +#endif
576 +typedef struct winhost_message {
577 + union {
578 + u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
579 + u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
580 + } msg;
581 +} DSL_DEV_WinHost_Message_t;
582 +/********************************************************************************************************
583 + * DSL CPE API Driver Stack Interface Definitions
584 + * *****************************************************************************************************/
585 +/** IOCTL codes for bsp driver */
586 +#define DSL_IOC_MEI_BSP_MAGIC 's'
587 +
588 +#define DSL_FIO_BSP_DSL_START _IO (DSL_IOC_MEI_BSP_MAGIC, 0)
589 +#define DSL_FIO_BSP_RUN _IO (DSL_IOC_MEI_BSP_MAGIC, 1)
590 +#define DSL_FIO_BSP_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 2)
591 +#define DSL_FIO_BSP_RESET _IO (DSL_IOC_MEI_BSP_MAGIC, 3)
592 +#define DSL_FIO_BSP_REBOOT _IO (DSL_IOC_MEI_BSP_MAGIC, 4)
593 +#define DSL_FIO_BSP_HALT _IO (DSL_IOC_MEI_BSP_MAGIC, 5)
594 +#define DSL_FIO_BSP_BOOTDOWNLOAD _IO (DSL_IOC_MEI_BSP_MAGIC, 6)
595 +#define DSL_FIO_BSP_JTAG_ENABLE _IO (DSL_IOC_MEI_BSP_MAGIC, 7)
596 +#define DSL_FIO_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 8)
597 +#define DSL_FIO_ARC_MUX_TEST _IO (DSL_IOC_MEI_BSP_MAGIC, 9)
598 +#define DSL_FIO_BSP_REMOTE _IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32)
599 +#define DSL_FIO_BSP_GET_BASE_ADDRESS _IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32)
600 +#define DSL_FIO_BSP_IS_MODEM_READY _IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32)
601 +#define DSL_FIO_BSP_GET_VERSION _IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t)
602 +#define DSL_FIO_BSP_CMV_WINHOST _IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t)
603 +#define DSL_FIO_BSP_CMV_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t)
604 +#define DSL_FIO_BSP_CMV_WRITE _IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t)
605 +#define DSL_FIO_BSP_DEBUG_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t)
606 +#define DSL_FIO_BSP_DEBUG_WRITE _IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t)
607 +#define DSL_FIO_BSP_GET_CHIP_INFO _IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t)
608 +
609 +#define DSL_DEV_MEIDEBUG_BUFFER_SIZES 512
610 +
611 +typedef struct DSL_DEV_MeiDebug
612 +{
613 + DSL_uint32_t iAddress;
614 + DSL_uint32_t iCount;
615 + DSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES];
616 +} DSL_DEV_MeiDebug_t; /* meidebug */
617 +
618 +/**
619 + * Structure is used for debug access only.
620 + * Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */
621 +typedef struct struct_meireg
622 +{
623 + /*
624 + * Specifies that address for debug access */
625 + unsigned long iAddress;
626 + /*
627 + * Specifies the pointer to the data that has to be written or returns a
628 + * pointer to the data that has been read out*/
629 + unsigned long iData;
630 +} DSL_DEV_MeiReg_t; /* meireg */
631 +
632 +typedef struct DSL_DEV_Device
633 +{
634 + DSL_int_t nInUse; /* modem state, update by bsp driver, */
635 + DSL_void_t *pPriv;
636 + DSL_uint32_t base_address; /* mei base address */
637 + DSL_int_t nIrq[2]; /* irq number */
638 +#define IFX_DFEIR 0
639 +#define IFX_DYING_GASP 1
640 + DSL_DEV_MeiDebug_t lop_debugwr; /* dying gasp */
641 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0))
642 + struct module *owner;
643 +#endif
644 +} DSL_DEV_Device_t; /* ifx_adsl_device_t */
645 +
646 +#define DSL_DEV_PRIVATE(dev) ((ifx_mei_device_private_t*)(dev->pPriv))
647 +
648 +typedef struct DSL_DEV_Version /* ifx_adsl_bsp_version */
649 +{
650 + unsigned long major;
651 + unsigned long minor;
652 + unsigned long revision;
653 +} DSL_DEV_Version_t; /* ifx_adsl_bsp_version_t */
654 +
655 +typedef struct DSL_DEV_ChipInfo
656 +{
657 + unsigned long major;
658 + unsigned long minor;
659 +} DSL_DEV_HwVersion_t;
660 +
661 +typedef struct
662 +{
663 + DSL_uint8_t dummy;
664 +} DSL_DEV_DeviceConfig_t;
665 +
666 +/** error code definitions */
667 +typedef enum DSL_DEV_MeiError
668 +{
669 + DSL_DEV_MEI_ERR_SUCCESS = 0,
670 + DSL_DEV_MEI_ERR_FAILURE = -1,
671 + DSL_DEV_MEI_ERR_MAILBOX_FULL = -2,
672 + DSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3,
673 + DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4
674 +} DSL_DEV_MeiError_t; /* MEI_ERROR */
675 +
676 +typedef enum {
677 + DSL_BSP_MEMORY_READ=0,
678 + DSL_BSP_MEMORY_WRITE,
679 +} DSL_BSP_MemoryAccessType_t; /* ifx_adsl_memory_access_type_t */
680 +
681 +typedef enum
682 +{
683 + DSL_LED_LINK_ID=0,
684 + DSL_LED_DATA_ID
685 +} DSL_DEV_LedId_t; /* ifx_adsl_led_id_t */
686 +
687 +typedef enum
688 +{
689 + DSL_LED_LINK_TYPE=0,
690 + DSL_LED_DATA_TYPE
691 +} DSL_DEV_LedType_t; /* ifx_adsl_led_type_t */
692 +
693 +typedef enum
694 +{
695 + DSL_LED_HD_CPU=0,
696 + DSL_LED_HD_FW
697 +} DSL_DEV_LedHandler_t; /* ifx_adsl_led_handler_t */
698 +
699 +typedef enum {
700 + DSL_LED_ON=0,
701 + DSL_LED_OFF,
702 + DSL_LED_FLASH,
703 +} DSL_DEV_LedMode_t; /* ifx_adsl_led_mode_t */
704 +
705 +typedef enum {
706 + DSL_CPU_HALT=0,
707 + DSL_CPU_RUN,
708 + DSL_CPU_RESET,
709 +} DSL_DEV_CpuMode_t; /* ifx_adsl_cpu_mode_t */
710 +
711 +#if 0
712 +typedef enum {
713 + DSL_BSP_EVENT_DYING_GASP = 0,
714 + DSL_BSP_EVENT_CEOC_IRQ,
715 +} DSL_BSP_Event_id_t; /* ifx_adsl_event_id_t */
716 +
717 +typedef union DSL_BSP_CB_Param
718 +{
719 + DSL_uint32_t nIrqMessage;
720 +} DSL_BSP_CB_Param_t; /* ifx_adsl_cbparam_t */
721 +
722 +typedef struct DSL_BSP_CB_Event
723 +{
724 + DSL_BSP_Event_id_t nID;
725 + DSL_DEV_Device_t *pDev;
726 + DSL_BSP_CB_Param_t *pParam;
727 +} DSL_BSP_CB_Event_t; /* ifx_adsl_cb_event_t */
728 +#endif
729 +
730 +/* external functions (from the BSP Driver) */
731 +extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int);
732 +extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *);
733 +extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *);
734 +extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long);
735 +extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *);
736 +extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
737 +extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
738 +extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void));
739 +extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t);
740 +extern volatile DSL_DEV_Device_t *adsl_dev;
741 +
742 +/**
743 + * Dummy structure by now to show mechanism of extended data that will be
744 + * provided within event callback itself.
745 + * */
746 +typedef struct
747 +{
748 + /**
749 + * Dummy value */
750 + DSL_uint32_t nDummy1;
751 +} DSL_BSP_CB_Event1DataDummy_t;
752 +
753 +/**
754 + * Dummy structure by now to show mechanism of extended data that will be
755 + * provided within event callback itself.
756 + * */
757 +typedef struct
758 +{
759 + /**
760 + * Dummy value */
761 + DSL_uint32_t nDummy2;
762 +} DSL_BSP_CB_Event2DataDummy_t;
763 +
764 +/**
765 + * encapsulate all data structures that are necessary for status event
766 + * callbacks.
767 + * */
768 +typedef union
769 +{
770 + DSL_BSP_CB_Event1DataDummy_t dataEvent1;
771 + DSL_BSP_CB_Event2DataDummy_t dataEvent2;
772 +} DSL_BSP_CB_DATA_Union_t;
773 +
774 +
775 +typedef enum
776 +{
777 + /**
778 + * Informs the upper layer driver (DSL CPE API) about a reboot request from the
779 + * firmware.
780 + * \note This event does NOT include any additional data.
781 + * More detailed information upon reboot reason has to be requested from
782 + * upper layer software via CMV (INFO 109) if necessary. */
783 + DSL_BSP_CB_FIRST = 0,
784 + DSL_BSP_CB_DYING_GASP,
785 + DSL_BSP_CB_CEOC_IRQ,
786 + DSL_BSP_CB_FIRMWARE_REBOOT,
787 + /**
788 + * Delimiter only */
789 + DSL_BSP_CB_LAST
790 +} DSL_BSP_CB_Type_t;
791 +
792 +/**
793 + * Specifies the common event type that has to be used for registering and
794 + * signalling of interrupts/autonomous status events from MEI BSP Driver.
795 + *
796 + * \param pDev
797 + * Context pointer from MEI BSP Driver.
798 + *
799 + * \param IFX_ADSL_BSP_CallbackType_t
800 + * Specifies the event callback type (reason of callback). Regrading to the
801 + * setting of this value the data which is included in the following union
802 + * might have different meanings.
803 + * Please refer to the description of the union to get information about the
804 + * meaning of the included data.
805 + *
806 + * \param pData
807 + * Data according to \ref DSL_BSP_CB_DATA_Union_t.
808 + * If this pointer is NULL there is no additional data available.
809 + *
810 + * \return depending on event
811 + */
812 +typedef int (*DSL_BSP_EventCallback_t)
813 +(
814 + DSL_DEV_Device_t *pDev,
815 + DSL_BSP_CB_Type_t nCallbackType,
816 + DSL_BSP_CB_DATA_Union_t *pData
817 +);
818 +
819 +typedef struct {
820 + DSL_BSP_EventCallback_t function;
821 + DSL_BSP_CB_Type_t event;
822 + DSL_BSP_CB_DATA_Union_t *pData;
823 +} DSL_BSP_EventCallBack_t;
824 +
825 +extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *);
826 +extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *);
827 +
828 +/** Modem states */
829 +#define DSL_DEV_STAT_InitState 0x0000
830 +#define DSL_DEV_STAT_ReadyState 0x0001
831 +#define DSL_DEV_STAT_FailState 0x0002
832 +#define DSL_DEV_STAT_IdleState 0x0003
833 +#define DSL_DEV_STAT_QuietState 0x0004
834 +#define DSL_DEV_STAT_GhsState 0x0005
835 +#define DSL_DEV_STAT_FullInitState 0x0006
836 +#define DSL_DEV_STAT_ShowTimeState 0x0007
837 +#define DSL_DEV_STAT_FastRetrainState 0x0008
838 +#define DSL_DEV_STAT_LoopDiagMode 0x0009
839 +#define DSL_DEV_STAT_ShortInit 0x000A /* Bis short initialization */
840 +
841 +#define DSL_DEV_STAT_CODESWAP_COMPLETE 0x0002
842 +
843 +#endif //IFXMIPS_MEI_H
844 --- a/configure.in
845 +++ b/configure.in
846 @@ -310,7 +310,7 @@ dnl Set kernel build path
847 AC_ARG_ENABLE(kernelbuild,
848 AC_HELP_STRING(--enable-kernel-build=x,Set the target kernel build path),
849 [
850 - if test -e $enableval/include/linux/autoconf.h; then
851 + if test -e $enableval/include/linux/autoconf.h -o -e $enableval/include/generated/autoconf.h; then
852 AC_SUBST([KERNEL_BUILD_PATH],[$enableval])
853 else
854 AC_MSG_ERROR([The kernel build directory is not valid or not configured!])
855 @@ -333,12 +333,12 @@ AC_ARG_ENABLE(ifxos-include,
856 echo Set the lib_ifxos include path $enableval
857 AC_SUBST([IFXOS_INCLUDE_PATH],[$enableval])
858 else
859 - echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
860 + echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
861 AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
862 fi
863 ],
864 [
865 - echo -e Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
866 + echo Set the default lib_ifxos include path $DEFAULT_IFXOS_INCLUDE_PATH
867 AC_SUBST([IFXOS_INCLUDE_PATH],[$DEFAULT_IFXOS_INCLUDE_PATH])
868 ]
869 )
870 @@ -1702,73 +1702,73 @@ dnl Set the configure params for dist ch
871 AC_SUBST([DISTCHECK_CONFIGURE_PARAMS],[$CONFIGURE_OPTIONS])
872
873 AC_CONFIG_COMMANDS_PRE([
874 -echo -e "------------------------------------------------------------------------"
875 -echo -e " Configuration for drv_dsl_cpe_api:"
876 -echo -e " Configure model type: $DSL_CONFIG_MODEL_TYPE"
877 -echo -e " Source code location: $srcdir"
878 -echo -e " Compiler: $CC"
879 -echo -e " Compiler c-flags: $CFLAGS"
880 -echo -e " Extra compiler c-flags: $EXTRA_DRV_CFLAGS"
881 -echo -e " Host System Type: $host"
882 -echo -e " Install path: $prefix"
883 -echo -e " Linux kernel include path: $KERNEL_INCL_PATH"
884 -echo -e " Linux kernel build path: $KERNEL_BUILD_PATH"
885 -echo -e " Linux kernel architecture: $KERNEL_ARCH"
886 -echo -e " Include IFXOS: $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
887 -echo -e " IFXOS include path: $IFXOS_INCLUDE_PATH"
888 -echo -e " Driver Include Path $DSL_DRIVER_INCL_PATH"
889 -echo -e " DSL device: $DSL_DEVICE_NAME"
890 -echo -e " Max device number: $DSL_DRV_MAX_DEVICE_NUMBER"
891 -echo -e " Channels per line: $DSL_CHANNELS_PER_LINE"
892 -echo -e " Build lib (only for kernel 2.6) $DSL_CPE_API_LIBRARY_BUILD_2_6"
893 -echo -e " DSL data led flash frequency: $DSL_DATA_LED_FLASH_FREQUENCY Hz"
894 -echo -e " Disable debug prints: $DSL_DEBUG_DISABLE"
895 -echo -e " Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
896 -echo -e " Preselected max. debug level: $DSL_DBG_MAX_LEVEL_PRE"
897 -echo -e " Include deprecated functions: $INCLUDE_DEPRECATED"
898 -echo -e " Include Device Exception Codes: $INCLUDE_DEVICE_EXCEPTION_CODES"
899 -echo -e " Include FW request support: $INCLUDE_FW_REQUEST_SUPPORT"
900 -echo -e " Include ADSL trace buffer: $INCLUDE_DSL_CPE_TRACE_BUFFER"
901 -echo -e " Include ADSL MIB: $INCLUDE_DSL_ADSL_MIB"
902 -echo -e " Include ADSL LED: $INCLUDE_ADSL_LED"
903 -echo -e " Include CEOC: $INCLUDE_DSL_CEOC"
904 -echo -e " Include config get support: $INCLUDE_DSL_CONFIG_GET"
905 -echo -e " Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
906 -echo -e " Include Resource Statistics: $INCLUDE_DSL_RESOURCE_STATISTICS"
907 -echo -e " Include Framing Parameters: $INCLUDE_DSL_FRAMING_PARAMETERS"
908 -echo -e " Include G997 Line Inventory: $INCLUDE_DSL_G997_LINE_INVENTORY"
909 -echo -e " Include G997 Framing Parameters: $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
910 -echo -e " Include G997 per tone data: $INCLUDE_DSL_G997_PER_TONE"
911 -echo -e " Include G997 status: $INCLUDE_DSL_G997_STATUS"
912 -echo -e " Include G997 alarm: $INCLUDE_DSL_G997_ALARM"
913 -echo -e " Include DSL Bonding: $INCLUDE_DSL_BONDING"
914 -echo -e " Include Misc Line Status $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
915 -echo -e " Include DELT: $INCLUDE_DSL_DELT"
916 -echo -e " Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
917 -echo -e " Include PM: $INCLUDE_DSL_PM"
918 -echo -e " Include PM config: $INCLUDE_DSL_CPE_PM_CONFIG"
919 -echo -e " Include PM total: $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
920 -echo -e " Include PM history: $INCLUDE_DSL_CPE_PM_HISTORY"
921 -echo -e " Include PM showtime: $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
922 -echo -e " Include PM optional: $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
923 -echo -e " Include PM line: $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
924 -echo -e " Include PM line event showtime: $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
925 -echo -e " Include PM channel: $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
926 -echo -e " Include PM channel extended: $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
927 -echo -e " Include PM data path: $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
928 -echo -e " Include PM data path failure: $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
929 -echo -e " Include PM ReTx: $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
930 -echo -e " Include PM line threshold: $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
931 -echo -e " Include PM channel threshold: $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
932 -echo -e " Include PM data path threshold: $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
933 -echo -e " Include PM ReTx threshold: $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
934 -echo -e " Include FW memory free support: $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
935 -echo -e "----------------------- deprectated ! ----------------------------------"
936 -echo -e " Include PM line failure: $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
937 -echo -e ""
938 -echo -e " Settings:"
939 -echo -e " Configure options: $CONFIGURE_OPTIONS"
940 -echo -e "------------------------------------------------------------------------"
941 +echo "------------------------------------------------------------------------"
942 +echo " Configuration for drv_dsl_cpe_api:"
943 +echo " Configure model type: $DSL_CONFIG_MODEL_TYPE"
944 +echo " Source code location: $srcdir"
945 +echo " Compiler: $CC"
946 +echo " Compiler c-flags: $CFLAGS"
947 +echo " Extra compiler c-flags: $EXTRA_DRV_CFLAGS"
948 +echo " Host System Type: $host"
949 +echo " Install path: $prefix"
950 +echo " Linux kernel include path: $KERNEL_INCL_PATH"
951 +echo " Linux kernel build path: $KERNEL_BUILD_PATH"
952 +echo " Linux kernel architecture: $KERNEL_ARCH"
953 +echo " Include IFXOS: $INCLUDE_DSL_CPE_API_IFXOS_SUPPORT"
954 +echo " IFXOS include path: $IFXOS_INCLUDE_PATH"
955 +echo " Driver Include Path $DSL_DRIVER_INCL_PATH"
956 +echo " DSL device: $DSL_DEVICE_NAME"
957 +echo " Max device number: $DSL_DRV_MAX_DEVICE_NUMBER"
958 +echo " Channels per line: $DSL_CHANNELS_PER_LINE"
959 +echo " Build lib (only for kernel 2.6) $DSL_CPE_API_LIBRARY_BUILD_2_6"
960 +echo " DSL data led flash frequency: $DSL_DATA_LED_FLASH_FREQUENCY Hz"
961 +echo " Disable debug prints: $DSL_DEBUG_DISABLE"
962 +echo " Preselection of max. debug level: $DSL_DBG_MAX_LEVEL_SET"
963 +echo " Preselected max. debug level: $DSL_DBG_MAX_LEVEL_PRE"
964 +echo " Include deprecated functions: $INCLUDE_DEPRECATED"
965 +echo " Include Device Exception Codes: $INCLUDE_DEVICE_EXCEPTION_CODES"
966 +echo " Include FW request support: $INCLUDE_FW_REQUEST_SUPPORT"
967 +echo " Include ADSL trace buffer: $INCLUDE_DSL_CPE_TRACE_BUFFER"
968 +echo " Include ADSL MIB: $INCLUDE_DSL_ADSL_MIB"
969 +echo " Include ADSL LED: $INCLUDE_ADSL_LED"
970 +echo " Include CEOC: $INCLUDE_DSL_CEOC"
971 +echo " Include config get support: $INCLUDE_DSL_CONFIG_GET"
972 +echo " Include System i/f configuration: $INCLUDE_DSL_SYSTEM_INTERFACE"
973 +echo " Include Resource Statistics: $INCLUDE_DSL_RESOURCE_STATISTICS"
974 +echo " Include Framing Parameters: $INCLUDE_DSL_FRAMING_PARAMETERS"
975 +echo " Include G997 Line Inventory: $INCLUDE_DSL_G997_LINE_INVENTORY"
976 +echo " Include G997 Framing Parameters: $INCLUDE_DSL_G997_FRAMING_PARAMETERS"
977 +echo " Include G997 per tone data: $INCLUDE_DSL_G997_PER_TONE"
978 +echo " Include G997 status: $INCLUDE_DSL_G997_STATUS"
979 +echo " Include G997 alarm: $INCLUDE_DSL_G997_ALARM"
980 +echo " Include DSL Bonding: $INCLUDE_DSL_BONDING"
981 +echo " Include Misc Line Status $INCLUDE_DSL_CPE_MISC_LINE_STATUS"
982 +echo " Include DELT: $INCLUDE_DSL_DELT"
983 +echo " Include DELT data static storage: $DSL_CPE_STATIC_DELT_DATA"
984 +echo " Include PM: $INCLUDE_DSL_PM"
985 +echo " Include PM config: $INCLUDE_DSL_CPE_PM_CONFIG"
986 +echo " Include PM total: $INCLUDE_DSL_CPE_PM_TOTAL_COUNTERS"
987 +echo " Include PM history: $INCLUDE_DSL_CPE_PM_HISTORY"
988 +echo " Include PM showtime: $INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS"
989 +echo " Include PM optional: $INCLUDE_DSL_CPE_PM_OPTIONAL_PARAMETERS"
990 +echo " Include PM line: $INCLUDE_DSL_CPE_PM_LINE_COUNTERS"
991 +echo " Include PM line event showtime: $INCLUDE_DSL_CPE_PM_LINE_EVENT_SHOWTIME_COUNTERS"
992 +echo " Include PM channel: $INCLUDE_DSL_CPE_PM_CHANNEL_COUNTERS"
993 +echo " Include PM channel extended: $INCLUDE_DSL_CPE_PM_CHANNEL_EXT_COUNTERS"
994 +echo " Include PM data path: $INCLUDE_DSL_CPE_PM_DATA_PATH_COUNTERS"
995 +echo " Include PM data path failure: $INCLUDE_DSL_CPE_PM_DATA_PATH_FAILURE_COUNTERS"
996 +echo " Include PM ReTx: $INCLUDE_DSL_CPE_PM_RETX_COUNTERS"
997 +echo " Include PM line threshold: $INCLUDE_DSL_CPE_PM_LINE_THRESHOLDS"
998 +echo " Include PM channel threshold: $INCLUDE_DSL_CPE_PM_CHANNEL_THRESHOLDS"
999 +echo " Include PM data path threshold: $INCLUDE_DSL_CPE_PM_DATA_PATH_THRESHOLDS"
1000 +echo " Include PM ReTx threshold: $INCLUDE_DSL_CPE_PM_RETX_THRESHOLDS"
1001 +echo " Include FW memory free support: $INCLUDE_DSL_FIRMWARE_MEMORY_FREE"
1002 +echo "----------------------- deprectated ! ----------------------------------"
1003 +echo " Include PM line failure: $INCLUDE_DSL_CPE_PM_LINE_FAILURE_COUNTERS"
1004 +echo ""
1005 +echo " Settings:"
1006 +echo " Configure options: $CONFIGURE_OPTIONS"
1007 +echo "------------------------------------------------------------------------"
1008 ])
1009
1010 AC_CONFIG_FILES([Makefile src/Makefile])
1011 --- a/src/Makefile.am
1012 +++ b/src/Makefile.am
1013 @@ -300,7 +300,7 @@ if KERNEL_2_6
1014 drv_dsl_cpe_api_OBJS = "$(subst .c,.o,$(filter %.c,$(drv_dsl_cpe_api_SOURCES)))"
1015
1016 drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SOURCES)
1017 - @echo -e "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
1018 + @echo "drv_dsl_cpe_api: Making Linux 2.6.x kernel object"
1019 if test ! -e common/drv_dsl_cpe_api.c ; then \
1020 echo "copy source files (as links only!)"; \
1021 for f in $(filter %.c,$(drv_dsl_cpe_api_SOURCES)); do \
1022 @@ -308,10 +308,10 @@ drv_dsl_cpe_api.ko: $(drv_dsl_cpe_api_SO
1023 cp -s $(addprefix @abs_srcdir@/,$$f) $(PWD)/`dirname $$f`/ ; \
1024 done \
1025 fi
1026 - @echo -e "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
1027 - @echo -e "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild
1028 - @echo -e "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)" >> $(PWD)/Kbuild
1029 - @echo -e "EXTRA_CFLAGS := -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild
1030 + @echo "# drv_dsl_cpe_api: Generated to build Linux 2.6.x kernel object" > $(PWD)/Kbuild
1031 + @echo "obj-m := $(subst .ko,.o,$@)" >> $(PWD)/Kbuild
1032 + @echo "$(subst .ko,,$@)-y := $(drv_dsl_cpe_api_OBJS)" >> $(PWD)/Kbuild
1033 + @echo "EXTRA_CFLAGS := -DHAVE_CONFIG_H $(drv_dsl_cpe_api_CFLAGS) $(DSL_DRIVER_INCL_PATH) $(IFXOS_INCLUDE_PATH) -I@abs_srcdir@/include -I$(PWD)/include" >> $(PWD)/Kbuild
1034 $(MAKE) ARCH=@KERNEL_ARCH@ -C @KERNEL_BUILD_PATH@ O=@KERNEL_BUILD_PATH@ M=$(PWD) modules
1035
1036 clean-generic:
OpenWrt Source Repository