package/kernel/lantiq/ltq-atm/src/ifxmips_atm_amazon_se.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_amazon_se.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <linux/platform_device.h>
  44 #include <asm/delay.h>
  45
  46 /*
  47  *  Chip Specific Head File
  48  */
  49 #include "ifxmips_atm_core.h"
  50 #include "ifxmips_atm_fw_amazon_se.h"
  51
  52 #include <lantiq_soc.h>
  53
  54
  55 /*
  56  * ####################################
  57  *              Definition
  58  * ####################################
  59  */
  60
  61 /*
  62  *  EMA Settings
  63  */
  64 #define EMA_CMD_BUF_LEN      0x0040
  65 #define EMA_CMD_BASE_ADDR    (0x00001580 << 2)
  66 #define EMA_DATA_BUF_LEN     0x0100
  67 #define EMA_DATA_BASE_ADDR   (0x00000B00 << 2)
  68 #define EMA_WRITE_BURST      0x2
  69 #define EMA_READ_BURST       0x2
  70
  71
  72
  73 /*
  74  * ####################################
  75  *             Declaration
  76  * ####################################
  77  */
  78
  79 /*
  80  *  Hardware Init/Uninit Functions
  81  */
  82 static inline void init_pmu(void);
  83 static inline void uninit_pmu(void);
  84 static inline void reset_ppe(struct platform_device *pdev);
  85 static inline void init_ema(void);
  86 static inline void init_mailbox(void);
  87 static inline void init_atm_tc(void);
  88 static inline void clear_share_buffer(void);
  89
  90
  91
  92 /*
  93  * ####################################
  94  *            Local Variable
  95  * ####################################
  96  */
  97
  98
  99
 100 /*
 101  * ####################################
 102  *            Local Function
 103  * ####################################
 104  */
 105 #define IFX_PMU_MODULE_PPE_SLL01  BIT(19)
 106 #define IFX_PMU_MODULE_PPE_TC     BIT(21)
 107 #define IFX_PMU_MODULE_PPE_EMA    BIT(22)
 108 #define IFX_PMU_MODULE_PPE_QSB    BIT(18)
 109 #define IFX_PMU_MODULE_TPE       BIT(13)
 110 #define IFX_PMU_MODULE_DSL_DFE    BIT(9)
 111
 112 static inline void init_pmu(void)
 113 {
 114     //*(unsigned long *)0xBF10201C &= ~((1 << 15) | (1 << 13) | (1 << 9));
 115     //PPE_TOP_PMU_SETUP(IFX_PMU_ENABLE);
 116 /*    PPE_SLL01_PMU_SETUP(IFX_PMU_ENABLE);
 117     PPE_TC_PMU_SETUP(IFX_PMU_ENABLE);
 118     PPE_EMA_PMU_SETUP(IFX_PMU_ENABLE);
 119     //PPE_QSB_PMU_SETUP(IFX_PMU_ENABLE);
 120     PPE_TPE_PMU_SETUP(IFX_PMU_ENABLE);
 121     DSL_DFE_PMU_SETUP(IFX_PMU_ENABLE);*/
 122         ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
 123                 IFX_PMU_MODULE_PPE_TC |
 124                 IFX_PMU_MODULE_PPE_EMA |
 125                 IFX_PMU_MODULE_TPE |
 126                 IFX_PMU_MODULE_DSL_DFE);
 127 }
 128
 129 static inline void uninit_pmu(void)
 130 {
 131     /*PPE_SLL01_PMU_SETUP(IFX_PMU_DISABLE);
 132     PPE_TC_PMU_SETUP(IFX_PMU_DISABLE);
 133     PPE_EMA_PMU_SETUP(IFX_PMU_DISABLE);
 134     //PPE_QSB_PMU_SETUP(IFX_PMU_DISABLE);
 135     PPE_TPE_PMU_SETUP(IFX_PMU_DISABLE);
 136     DSL_DFE_PMU_SETUP(IFX_PMU_DISABLE);
 137     //PPE_TOP_PMU_SETUP(IFX_PMU_DISABLE);*/
 138 }
 139
 140 static inline void reset_ppe(struct platform_device *pdev)
 141 {
 142 #if 0 //MODULE
 143     unsigned int etop_cfg;
 144     unsigned int etop_mdio_cfg;
 145     unsigned int etop_ig_plen_ctrl;
 146     unsigned int enet_mac_cfg;
 147
 148     etop_cfg            = *IFX_PP32_ETOP_CFG;
 149     etop_mdio_cfg       = *IFX_PP32_ETOP_MDIO_CFG;
 150     etop_ig_plen_ctrl   = *IFX_PP32_ETOP_IG_PLEN_CTRL;
 151     enet_mac_cfg        = *IFX_PP32_ENET_MAC_CFG;
 152
 153     *IFX_PP32_ETOP_CFG  = (*IFX_PP32_ETOP_CFG & ~0x03C0) | 0x0001;
 154
 155     //  reset PPE
 156     ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
 157
 158     *IFX_PP32_ETOP_MDIO_CFG     = etop_mdio_cfg;
 159     *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
 160     *IFX_PP32_ENET_MAC_CFG      = enet_mac_cfg;
 161     *IFX_PP32_ETOP_CFG          = etop_cfg;
 162 #endif
 163 }
 164
 165 static inline void init_ema(void)
 166 {
 167     IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
 168     IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
 169     IFX_REG_W32(0x000000FF, EMA_IER);
 170     IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
 171 }
 172
 173 static inline void init_mailbox(void)
 174 {
 175     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 176     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 177     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 178     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 179 }
 180
 181 static inline void init_atm_tc(void)
 182 {
 183     IFX_REG_W32(0x0000,     DREG_AT_CTRL);
 184     IFX_REG_W32(0x0000,     DREG_AR_CTRL);
 185     IFX_REG_W32(0x0,        DREG_AT_IDLE0);
 186     IFX_REG_W32(0x0,        DREG_AT_IDLE1);
 187     IFX_REG_W32(0x0,        DREG_AR_IDLE0);
 188     IFX_REG_W32(0x0,        DREG_AR_IDLE1);
 189     IFX_REG_W32(0x40,       RFBI_CFG);
 190     IFX_REG_W32(0x0700,     SFSM_DBA0);
 191     IFX_REG_W32(0x0818,     SFSM_DBA1);
 192     IFX_REG_W32(0x0930,     SFSM_CBA0);
 193     IFX_REG_W32(0x0944,     SFSM_CBA1);
 194     IFX_REG_W32(0x14014,    SFSM_CFG0);
 195     IFX_REG_W32(0x14014,    SFSM_CFG1);
 196     IFX_REG_W32(0x0958,     FFSM_DBA0);
 197     IFX_REG_W32(0x09AC,     FFSM_DBA1);
 198     IFX_REG_W32(0x10006,    FFSM_CFG0);
 199     IFX_REG_W32(0x10006,    FFSM_CFG1);
 200     IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
 201     IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
 202 }
 203
 204 static inline void clear_share_buffer(void)
 205 {
 206     volatile u32 *p = SB_RAM0_ADDR(0);
 207     unsigned int i;
 208
 209     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN; i++ )
 210         IFX_REG_W32(0, p++);
 211 }
 212
 213 /*
 214  *  Description:
 215  *    Download PPE firmware binary code.
 216  *  Input:
 217  *    src       --- u32 *, binary code buffer
 218  *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
 219  *  Output:
 220  *    int       --- 0:    Success
 221  *                  else:           Error Code
 222  */
 223 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 224 {
 225     volatile u32 *dest;
 226
 227     if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 228         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 229         return -1;
 230
 231     if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 232         IFX_REG_W32(0x00, CDM_CFG);
 233     else
 234         IFX_REG_W32(0x04, CDM_CFG);
 235
 236     /*  copy code   */
 237     dest = CDM_CODE_MEMORY(0, 0);
 238     while ( code_dword_len-- > 0 )
 239         IFX_REG_W32(*code_src++, dest++);
 240
 241     /*  copy data   */
 242     dest = CDM_DATA_MEMORY(0, 0);
 243     while ( data_dword_len-- > 0 )
 244         IFX_REG_W32(*data_src++, dest++);
 245
 246     return 0;
 247 }
 248
 249
 250
 251 /*
 252  * ####################################
 253  *           Global Function
 254  * ####################################
 255  */
 256
 257 extern void ase_fw_ver(unsigned int *major, unsigned int *minor)
 258 {
 259     ASSERT(major != NULL, "pointer is NULL");
 260     ASSERT(minor != NULL, "pointer is NULL");
 261
 262     *major = FW_VER_ID->major;
 263     *minor = FW_VER_ID->minor;
 264 }
 265
 266 void ase_init(struct platform_device *pdev)
 267 {
 268     init_pmu();
 269
 270     reset_ppe(pdev);
 271
 272     init_ema();
 273
 274     init_mailbox();
 275
 276     init_atm_tc();
 277
 278     clear_share_buffer();
 279 }
 280
 281 void ase_shutdown(void)
 282 {
 283     uninit_pmu();
 284 }
 285
 286 /*
 287  *  Description:
 288  *    Initialize and start up PP32.
 289  *  Input:
 290  *    none
 291  *  Output:
 292  *    int  --- 0: Success
 293  *             else:        Error Code
 294  */
 295 int ase_start(int pp32)
 296 {
 297     int ret;
 298
 299     /*  download firmware   */
 300     ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
 301     if ( ret != 0 )
 302         return ret;
 303
 304     /*  run PP32    */
 305     IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL);
 306
 307     /*  idle for a while to let PP32 init itself    */
 308     udelay(10);
 309
 310     return 0;
 311 }
 312
 313 /*
 314  *  Description:
 315  *    Halt PP32.
 316  *  Input:
 317  *    none
 318  *  Output:
 319  *    none
 320  */
 321 void ase_stop(int pp32)
 322 {
 323     /*  halt PP32   */
 324     IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL);
 325 }
 326
 327 struct ltq_atm_ops ase_ops = {
 328         .init = ase_init,
 329         .shutdown = ase_shutdown,
 330         .start = ase_start,
 331         .stop = ase_stop,
 332         .fw_ver = ase_fw_ver,
 333 };
 334