ltq-atm/ltq-ptm: re-enable/fix reset_ppe() functionality for VR9
[openwrt/openwrt.git] / package / kernel / lantiq / ltq-atm / src / ifxmips_atm_danube.c
1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_atm_danube.c
4 ** PROJECT : UEIP
5 ** MODULES : ATM
6 **
7 ** DATE : 7 Jul 2009
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
23
24
25
26 /*
27 * ####################################
28 * Head File
29 * ####################################
30 */
31
32 /*
33 * Common Head File
34 */
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <linux/platform_device.h>
44 #include <linux/delay.h>
45
46 /*
47 * Chip Specific Head File
48 */
49 #include "ifxmips_atm_core.h"
50
51 #ifdef CONFIG_DANUBE
52
53 #include "ifxmips_atm_fw_danube.h"
54 #include "ifxmips_atm_fw_regs_danube.h"
55
56 #include <lantiq_soc.h>
57
58 #define EMA_CMD_BUF_LEN 0x0040
59 #define EMA_CMD_BASE_ADDR (0x00001580 << 2)
60 #define EMA_DATA_BUF_LEN 0x0100
61 #define EMA_DATA_BASE_ADDR (0x00001900 << 2)
62 #define EMA_WRITE_BURST 0x2
63 #define EMA_READ_BURST 0x2
64
65 static inline void reset_ppe(struct platform_device *pdev);
66
67 #define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
68 #define IFX_PMU_MODULE_PPE_TC BIT(21)
69 #define IFX_PMU_MODULE_PPE_EMA BIT(22)
70 #define IFX_PMU_MODULE_PPE_QSB BIT(18)
71 #define IFX_PMU_MODULE_TPE BIT(13)
72 #define IFX_PMU_MODULE_DSL_DFE BIT(9)
73
74 static inline void reset_ppe(struct platform_device *pdev)
75 {
76 /*#ifdef MODULE
77 unsigned int etop_cfg;
78 unsigned int etop_mdio_cfg;
79 unsigned int etop_ig_plen_ctrl;
80 unsigned int enet_mac_cfg;
81
82 etop_cfg = *IFX_PP32_ETOP_CFG;
83 etop_mdio_cfg = *IFX_PP32_ETOP_MDIO_CFG;
84 etop_ig_plen_ctrl = *IFX_PP32_ETOP_IG_PLEN_CTRL;
85 enet_mac_cfg = *IFX_PP32_ENET_MAC_CFG;
86
87 *IFX_PP32_ETOP_CFG &= ~0x03C0;
88
89 // reset PPE
90 ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_ATM);
91
92 *IFX_PP32_ETOP_MDIO_CFG = etop_mdio_cfg;
93 *IFX_PP32_ETOP_IG_PLEN_CTRL = etop_ig_plen_ctrl;
94 *IFX_PP32_ENET_MAC_CFG = enet_mac_cfg;
95 *IFX_PP32_ETOP_CFG = etop_cfg;
96 #endif*/
97 }
98
99 /*
100 * Description:
101 * Download PPE firmware binary code.
102 * Input:
103 * src --- u32 *, binary code buffer
104 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
105 * Output:
106 * int --- 0: Success
107 * else: Error Code
108 */
109 static inline int danube_pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
110 {
111 volatile u32 *dest;
112
113 if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
114 || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
115 return -1;
116
117 if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
118 IFX_REG_W32(0x00, CDM_CFG);
119 else
120 IFX_REG_W32(0x04, CDM_CFG);
121
122 /* copy code */
123 dest = CDM_CODE_MEMORY(0, 0);
124 while ( code_dword_len-- > 0 )
125 IFX_REG_W32(*code_src++, dest++);
126
127 /* copy data */
128 dest = CDM_DATA_MEMORY(0, 0);
129 while ( data_dword_len-- > 0 )
130 IFX_REG_W32(*data_src++, dest++);
131
132 return 0;
133 }
134
135 static void danube_fw_ver(unsigned int *major, unsigned int *minor)
136 {
137 ASSERT(major != NULL, "pointer is NULL");
138 ASSERT(minor != NULL, "pointer is NULL");
139
140 *major = FW_VER_ID->major;
141 *minor = FW_VER_ID->minor;
142 }
143
144 static void danube_init(struct platform_device *pdev)
145 {
146 volatile u32 *p = SB_RAM0_ADDR(0);
147 unsigned int i;
148
149 ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
150 IFX_PMU_MODULE_PPE_TC |
151 IFX_PMU_MODULE_PPE_EMA |
152 IFX_PMU_MODULE_PPE_QSB |
153 IFX_PMU_MODULE_TPE |
154 IFX_PMU_MODULE_DSL_DFE);
155
156 reset_ppe(pdev);
157
158 /* init ema */
159 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
160 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
161 IFX_REG_W32(0x000000FF, EMA_IER);
162 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
163
164 /* init mailbox */
165 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
166 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
167 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
168 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
169
170 /* init atm tc */
171 IFX_REG_W32(0x0000, DREG_AT_CTRL);
172 IFX_REG_W32(0x0000, DREG_AR_CTRL);
173 IFX_REG_W32(0x0, DREG_AT_IDLE0);
174 IFX_REG_W32(0x0, DREG_AT_IDLE1);
175 IFX_REG_W32(0x0, DREG_AR_IDLE0);
176 IFX_REG_W32(0x0, DREG_AR_IDLE1);
177 IFX_REG_W32(0x40, RFBI_CFG);
178 IFX_REG_W32(0x1600, SFSM_DBA0);
179 IFX_REG_W32(0x1718, SFSM_DBA1);
180 IFX_REG_W32(0x1830, SFSM_CBA0);
181 IFX_REG_W32(0x1844, SFSM_CBA1);
182 IFX_REG_W32(0x14014, SFSM_CFG0);
183 IFX_REG_W32(0x14014, SFSM_CFG1);
184 IFX_REG_W32(0x1858, FFSM_DBA0);
185 IFX_REG_W32(0x18AC, FFSM_DBA1);
186 IFX_REG_W32(0x10006, FFSM_CFG0);
187 IFX_REG_W32(0x10006, FFSM_CFG1);
188 IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC0);
189 IFX_REG_W32(0x00000001, FFSM_IDLE_HEAD_BC1);
190
191 for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN; i++ )
192 IFX_REG_W32(0, p++);
193 }
194
195 static void danube_shutdown(void)
196 {
197 }
198
199 int danube_start(int pp32)
200 {
201 int ret;
202
203 /* download firmware */
204 ret = danube_pp32_download_code(
205 danube_fw_bin, sizeof(danube_fw_bin) / sizeof(*danube_fw_bin),
206 danube_fw_data, sizeof(danube_fw_data) / sizeof(*danube_fw_data));
207 if ( ret != 0 )
208 return ret;
209
210 /* run PP32 */
211 IFX_REG_W32(DBG_CTRL_START_SET(1), PP32_DBG_CTRL);
212
213 /* idle for a while to let PP32 init itself */
214 udelay(10);
215
216 return 0;
217 }
218
219 void danube_stop(int pp32)
220 {
221 IFX_REG_W32(DBG_CTRL_STOP_SET(1), PP32_DBG_CTRL);
222 }
223
224 struct ltq_atm_ops danube_ops = {
225 .init = danube_init,
226 .shutdown = danube_shutdown,
227 .start = danube_start,
228 .stop = danube_stop,
229 .fw_ver = danube_fw_ver,
230 };
231
232 #endif