package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ppe_amazon_se.h

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_atm_ppe_amazon_se.h
   4 ** PROJECT      : UEIP
   5 ** MODULES      : ATM (ADSL)
   6 **
   7 ** DATE         : 1 AUG 2005
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : ATM Driver (PPE Registers)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 **  4 AUG 2005  Xu Liang        Initiate Version
  22 ** 23 OCT 2006  Xu Liang        Add GPL header.
  23 **  9 JAN 2007  Xu Liang        First version got from Anand (IC designer)
  24 *******************************************************************************/
  25
  26
  27
  28 #ifndef IFXMIPS_ATM_PPE_AMAZON_SE_H
  29 #define IFXMIPS_ATM_PPE_AMAZON_SE_H
  30
  31
  32
  33 /*
  34  *  FPI Configuration Bus Register and Memory Address Mapping
  35  */
  36 #define IFX_PPE                         (KSEG1 | 0x1E180000)
  37 #define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))
  38 #define PPM_INT_REG_ADDR(i, x)          ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))
  39 #define PP32_INTERNAL_RES_ADDR(i, x)    ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))
  40 #define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))
  41 #define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))
  42 #define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))
  43 #define PPM_INT_UNIT_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))
  44 #define PPM_TIMER0_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))
  45 #define PPM_TASK_IND_REG_ADDR(x)        ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))
  46 #define PPS_BRK_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))
  47 #define PPM_TIMER1_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))
  48 #define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8200) << 2)))
  49 #define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8C00) << 2)))
  50 #define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))
  51
  52 /*
  53  *  DWORD-Length of Memory Blocks
  54  */
  55 #define PP32_DEBUG_REG_DWLEN            0x0030
  56 #define PPM_INT_REG_DWLEN               0x0010
  57 #define PP32_INTERNAL_RES_DWLEN         0x00C0
  58 #define CDM_CODE_MEMORYn_DWLEN(n)       ((n) == 0 ? 0x1000 : 0x0800)
  59 #define PPE_REG_DWLEN                   0x1000
  60 #define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)
  61 #define PPM_INT_UNIT_DWLEN              0x0100
  62 #define PPM_TIMER0_DWLEN                0x0100
  63 #define PPM_TASK_IND_REG_DWLEN          0x0100
  64 #define PPS_BRK_DWLEN                   0x0100
  65 #define PPM_TIMER1_DWLEN                0x0100
  66 #define SB_RAM0_DWLEN                   0x0A00
  67 #define SB_RAM1_DWLEN                   0x0A00
  68 #define QSB_CONF_REG_DWLEN              0x0100
  69
  70 /*
  71  *  PP32 to FPI Address Mapping
  72  */
  73 #define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x2200) && ((__sb_addr) <= 0x2BFF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2200) :   \
  74                                                                    (((__sb_addr) >= 0x2C00) && ((__sb_addr) <= 0x35FF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2C00) :   \
  75                                                                 0))
  76
  77 /*
  78  *  PP32 Debug Control Register
  79  */
  80 #define PP32_DBG_CTRL                   PP32_DEBUG_REG_ADDR(0, 0x0000)
  81
  82 #define DBG_CTRL_RESTART                0
  83 #define DBG_CTRL_STOP                   1
  84
  85 #define PP32_HALT_STAT                  PP32_DEBUG_REG_ADDR(0, 0x0D00)
  86 #define PP32_BREAKPOINT_REASONS         PP32_DEBUG_REG_ADDR(0, 0x0A00)
  87
  88 #define PP32_BRK_SRC                    PP32_DEBUG_REG_ADDR(0, 0x0F00)
  89
  90 #define PP32_DBG_CUR_PC                 PP32_DEBUG_REG_ADDR(0, 0x0F80)
  91
  92 #define PP32_DBG_TASK_NO                PP32_DEBUG_REG_ADDR(0, 0x0F81)
  93
  94 /*
  95  *  Share Buffer
  96  */
  97 #define SB_MST_PRI0                     PPE_REG_ADDR(0x0300)
  98 #define SB_MST_PRI1                     PPE_REG_ADDR(0x0301)
  99
 100 /*
 101  *  EMA Registers
 102  */
 103 #define EMA_CMDCFG                      PPE_REG_ADDR(0x0A00)
 104 #define EMA_DATACFG                     PPE_REG_ADDR(0x0A01)
 105 #define EMA_CMDCNT                      PPE_REG_ADDR(0x0A02)
 106 #define EMA_DATACNT                     PPE_REG_ADDR(0x0A03)
 107 #define EMA_ISR                         PPE_REG_ADDR(0x0A04)
 108 #define EMA_IER                         PPE_REG_ADDR(0x0A05)
 109 #define EMA_CFG                         PPE_REG_ADDR(0x0A06)
 110 #define EMA_SUBID                       PPE_REG_ADDR(0x0A07)
 111
 112 #define EMA_ALIGNMENT                   4
 113
 114 /*
 115  *  Mailbox IGU1 Interrupt
 116  */
 117 #define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL13
 118
 119
 120
 121 #endif  //  IFXMIPS_ATM_PPE_AMAZON_SE_H