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[openwrt/openwrt.git] / package / kernel / lantiq / ltq-atm / src / ltq_atm.c
1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_atm_core.c
4 ** PROJECT : UEIP
5 ** MODULES : ATM
6 **
7 ** DATE : 7 Jul 2009
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : ATM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 **
23 ** Copyright 2017 Alexander Couzens <lynxis@fe80.eu>
24 *******************************************************************************/
25
26 #define IFX_ATM_VER_MAJOR 1
27 #define IFX_ATM_VER_MID 0
28 #define IFX_ATM_VER_MINOR 26
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/version.h>
33 #include <linux/types.h>
34 #include <linux/errno.h>
35 #include <linux/proc_fs.h>
36 #include <linux/init.h>
37 #include <linux/ioctl.h>
38 #include <linux/atmdev.h>
39 #include <linux/platform_device.h>
40 #include <linux/of_device.h>
41 #include <linux/atm.h>
42 #include <linux/clk.h>
43 #include <linux/interrupt.h>
44 #ifdef CONFIG_XFRM
45 #include <net/xfrm.h>
46 #endif
47
48 #include <lantiq_soc.h>
49
50 #include "ifxmips_atm_core.h"
51
52 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
53 #define MODULE_PARM(a, b) module_param(a, int, 0)
54
55 /*!
56 \brief QSB cell delay variation due to concurrency
57 */
58 static int qsb_tau = 1; /* QSB cell delay variation due to concurrency */
59 /*!
60 \brief QSB scheduler burst length
61 */
62 static int qsb_srvm = 0x0F; /* QSB scheduler burst length */
63 /*!
64 \brief QSB time step, all legal values are 1, 2, 4
65 */
66 static int qsb_tstep = 4 ; /* QSB time step, all legal values are 1, 2, 4 */
67
68 /*!
69 \brief Write descriptor delay
70 */
71 static int write_descriptor_delay = 0x20; /* Write descriptor delay */
72
73 /*!
74 \brief AAL5 padding byte ('~')
75 */
76 static int aal5_fill_pattern = 0x007E; /* AAL5 padding byte ('~') */
77 /*!
78 \brief Max frame size for RX
79 */
80 static int aal5r_max_packet_size = 0x0700; /* Max frame size for RX */
81 /*!
82 \brief Min frame size for RX
83 */
84 static int aal5r_min_packet_size = 0x0000; /* Min frame size for RX */
85 /*!
86 \brief Max frame size for TX
87 */
88 static int aal5s_max_packet_size = 0x0700; /* Max frame size for TX */
89 /*!
90 \brief Min frame size for TX
91 */
92 static int aal5s_min_packet_size = 0x0000; /* Min frame size for TX */
93 /*!
94 \brief Drop error packet in RX path
95 */
96 static int aal5r_drop_error_packet = 1; /* Drop error packet in RX path */
97
98 /*!
99 \brief Number of descriptors per DMA RX channel
100 */
101 static int dma_rx_descriptor_length = 128; /* Number of descriptors per DMA RX channel */
102 /*!
103 \brief Number of descriptors per DMA TX channel
104 */
105 static int dma_tx_descriptor_length = 64; /* Number of descriptors per DMA TX channel */
106 /*!
107 \brief PPE core clock cycles between descriptor write and effectiveness in external RAM
108 */
109 static int dma_rx_clp1_descriptor_threshold = 38;
110 /*@}*/
111
112 MODULE_PARM(qsb_tau, "i");
113 MODULE_PARM_DESC(qsb_tau, "Cell delay variation. Value must be > 0");
114 MODULE_PARM(qsb_srvm, "i");
115 MODULE_PARM_DESC(qsb_srvm, "Maximum burst size");
116 MODULE_PARM(qsb_tstep, "i");
117 MODULE_PARM_DESC(qsb_tstep, "n*32 cycles per sbs cycles n=1,2,4");
118
119 MODULE_PARM(write_descriptor_delay, "i");
120 MODULE_PARM_DESC(write_descriptor_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
121
122 MODULE_PARM(aal5_fill_pattern, "i");
123 MODULE_PARM_DESC(aal5_fill_pattern, "Filling pattern (PAD) for AAL5 frames");
124 MODULE_PARM(aal5r_max_packet_size, "i");
125 MODULE_PARM_DESC(aal5r_max_packet_size, "Max packet size in byte for downstream AAL5 frames");
126 MODULE_PARM(aal5r_min_packet_size, "i");
127 MODULE_PARM_DESC(aal5r_min_packet_size, "Min packet size in byte for downstream AAL5 frames");
128 MODULE_PARM(aal5s_max_packet_size, "i");
129 MODULE_PARM_DESC(aal5s_max_packet_size, "Max packet size in byte for upstream AAL5 frames");
130 MODULE_PARM(aal5s_min_packet_size, "i");
131 MODULE_PARM_DESC(aal5s_min_packet_size, "Min packet size in byte for upstream AAL5 frames");
132 MODULE_PARM(aal5r_drop_error_packet, "i");
133 MODULE_PARM_DESC(aal5r_drop_error_packet, "Non-zero value to drop error packet for downstream");
134
135 MODULE_PARM(dma_rx_descriptor_length, "i");
136 MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
137 MODULE_PARM(dma_tx_descriptor_length, "i");
138 MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
139 MODULE_PARM(dma_rx_clp1_descriptor_threshold, "i");
140 MODULE_PARM_DESC(dma_rx_clp1_descriptor_threshold, "Descriptor threshold for cells with cell loss priority 1");
141
142
143
144 /*
145 * ####################################
146 * Definition
147 * ####################################
148 */
149
150 #ifdef CONFIG_AMAZON_SE
151 #define ENABLE_LESS_CACHE_INV 1
152 #define LESS_CACHE_INV_LEN 96
153 #endif
154
155 #define DUMP_SKB_LEN ~0
156
157
158
159 /*
160 * ####################################
161 * Declaration
162 * ####################################
163 */
164
165 /*
166 * Network Operations
167 */
168 static int ppe_ioctl(struct atm_dev *, unsigned int, void *);
169 static int ppe_open(struct atm_vcc *);
170 static void ppe_close(struct atm_vcc *);
171 static int ppe_send(struct atm_vcc *, struct sk_buff *);
172 static int ppe_send_oam(struct atm_vcc *, void *, int);
173 static int ppe_change_qos(struct atm_vcc *, struct atm_qos *, int);
174
175 /*
176 * ADSL LED
177 */
178 static inline void adsl_led_flash(void);
179
180 /*
181 * 64-bit operation used by MIB calculation
182 */
183 static inline void u64_add_u32(ppe_u64_t, unsigned int, ppe_u64_t *);
184
185 /*
186 * buffer manage functions
187 */
188 static inline struct sk_buff* alloc_skb_rx(void);
189 static inline struct sk_buff* alloc_skb_tx(unsigned int);
190 struct sk_buff* atm_alloc_tx(struct atm_vcc *, unsigned int);
191 static inline void atm_free_tx_skb_vcc(struct sk_buff *, struct atm_vcc *);
192 static inline struct sk_buff *get_skb_rx_pointer(unsigned int);
193 static inline int get_tx_desc(unsigned int);
194 static struct sk_buff* skb_duplicate(struct sk_buff *);
195 static struct sk_buff* skb_break_away_from_protocol(struct sk_buff *);
196
197 /*
198 * mailbox handler and signal function
199 */
200 static inline void mailbox_oam_rx_handler(void);
201 static inline void mailbox_aal_rx_handler(void);
202 static irqreturn_t mailbox_irq_handler(int, void *);
203 static inline void mailbox_signal(unsigned int, int);
204 static void do_ppe_tasklet(unsigned long);
205 DECLARE_TASKLET(g_dma_tasklet, do_ppe_tasklet, 0);
206
207 /*
208 * QSB & HTU setting functions
209 */
210 static void set_qsb(struct atm_vcc *, struct atm_qos *, unsigned int);
211 static void qsb_global_set(void);
212 static inline void set_htu_entry(unsigned int, unsigned int, unsigned int, int, int);
213 static inline void clear_htu_entry(unsigned int);
214 static void validate_oam_htu_entry(void);
215 static void invalidate_oam_htu_entry(void);
216
217 /*
218 * look up for connection ID
219 */
220 static inline int find_vpi(unsigned int);
221 static inline int find_vpivci(unsigned int, unsigned int);
222 static inline int find_vcc(struct atm_vcc *);
223
224 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *);
225
226 /*
227 * Init & clean-up functions
228 */
229 static inline void check_parameters(void);
230 static inline int init_priv_data(void);
231 static inline void clear_priv_data(void);
232 static inline void init_rx_tables(void);
233 static inline void init_tx_tables(void);
234
235 /*
236 * Exteranl Function
237 */
238 #if defined(CONFIG_IFX_OAM) || defined(CONFIG_IFX_OAM_MODULE)
239 extern void ifx_push_oam(unsigned char *);
240 #else
241 static inline void ifx_push_oam(unsigned char *dummy) {}
242 #endif
243
244 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
245 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
246 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
247
248 extern int (*ifx_mei_atm_showtime_exit)(void);
249 extern int ifx_mei_atm_led_blink(void);
250 #else
251 static inline int ifx_mei_atm_led_blink(void) { return 0; }
252 static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
253 {
254 if ( is_showtime != NULL )
255 *is_showtime = 0;
256 return 0;
257 }
258 int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
259 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
260
261 int (*ifx_mei_atm_showtime_exit)(void) = NULL;
262 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
263
264 #endif
265
266 static struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
267
268 static struct atm_priv_data g_atm_priv_data;
269
270 static struct atmdev_ops g_ifx_atm_ops = {
271 .open = ppe_open,
272 .close = ppe_close,
273 .ioctl = ppe_ioctl,
274 .send = ppe_send,
275 .send_oam = ppe_send_oam,
276 .change_qos = ppe_change_qos,
277 .owner = THIS_MODULE,
278 };
279
280 static int g_showtime = 0;
281 static void *g_xdata_addr = NULL;
282
283 static int ppe_ioctl(struct atm_dev *dev, unsigned int cmd, void *arg)
284 {
285 int ret = 0;
286 atm_cell_ifEntry_t mib_cell;
287 atm_aal5_ifEntry_t mib_aal5;
288 atm_aal5_vcc_x_t mib_vcc;
289 unsigned int value;
290 int conn;
291
292 if ( _IOC_TYPE(cmd) != PPE_ATM_IOC_MAGIC
293 || _IOC_NR(cmd) >= PPE_ATM_IOC_MAXNR )
294 return -ENOTTY;
295
296 if ( _IOC_DIR(cmd) & _IOC_READ )
297 ret = !access_ok(VERIFY_WRITE, arg, _IOC_SIZE(cmd));
298 else if ( _IOC_DIR(cmd) & _IOC_WRITE )
299 ret = !access_ok(VERIFY_READ, arg, _IOC_SIZE(cmd));
300 if ( ret )
301 return -EFAULT;
302
303 switch (cmd) {
304 case PPE_ATM_MIB_CELL: /* cell level MIB */
305 /* These MIB should be read at ARC side, now put zero only. */
306 mib_cell.ifHCInOctets_h = 0;
307 mib_cell.ifHCInOctets_l = 0;
308 mib_cell.ifHCOutOctets_h = 0;
309 mib_cell.ifHCOutOctets_l = 0;
310 mib_cell.ifInErrors = 0;
311 mib_cell.ifInUnknownProtos = WAN_MIB_TABLE->wrx_drophtu_cell;
312 mib_cell.ifOutErrors = 0;
313
314 ret = sizeof(mib_cell) - copy_to_user(arg, &mib_cell, sizeof(mib_cell));
315 break;
316
317 case PPE_ATM_MIB_AAL5: /* AAL5 MIB */
318 value = WAN_MIB_TABLE->wrx_total_byte;
319 u64_add_u32(g_atm_priv_data.wrx_total_byte, value - g_atm_priv_data.prev_wrx_total_byte, &g_atm_priv_data.wrx_total_byte);
320 g_atm_priv_data.prev_wrx_total_byte = value;
321 mib_aal5.ifHCInOctets_h = g_atm_priv_data.wrx_total_byte.h;
322 mib_aal5.ifHCInOctets_l = g_atm_priv_data.wrx_total_byte.l;
323
324 value = WAN_MIB_TABLE->wtx_total_byte;
325 u64_add_u32(g_atm_priv_data.wtx_total_byte, value - g_atm_priv_data.prev_wtx_total_byte, &g_atm_priv_data.wtx_total_byte);
326 g_atm_priv_data.prev_wtx_total_byte = value;
327 mib_aal5.ifHCOutOctets_h = g_atm_priv_data.wtx_total_byte.h;
328 mib_aal5.ifHCOutOctets_l = g_atm_priv_data.wtx_total_byte.l;
329
330 mib_aal5.ifInUcastPkts = g_atm_priv_data.wrx_pdu;
331 mib_aal5.ifOutUcastPkts = WAN_MIB_TABLE->wtx_total_pdu;
332 mib_aal5.ifInErrors = WAN_MIB_TABLE->wrx_err_pdu;
333 mib_aal5.ifInDiscards = WAN_MIB_TABLE->wrx_dropdes_pdu + g_atm_priv_data.wrx_drop_pdu;
334 mib_aal5.ifOutErros = g_atm_priv_data.wtx_err_pdu;
335 mib_aal5.ifOutDiscards = g_atm_priv_data.wtx_drop_pdu;
336
337 ret = sizeof(mib_aal5) - copy_to_user(arg, &mib_aal5, sizeof(mib_aal5));
338 break;
339
340 case PPE_ATM_MIB_VCC: /* VCC related MIB */
341 copy_from_user(&mib_vcc, arg, sizeof(mib_vcc));
342 conn = find_vpivci(mib_vcc.vpi, mib_vcc.vci);
343 if (conn >= 0) {
344 mib_vcc.mib_vcc.aal5VccCrcErrors = g_atm_priv_data.conn[conn].aal5_vcc_crc_err;
345 mib_vcc.mib_vcc.aal5VccOverSizedSDUs = g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu;
346 mib_vcc.mib_vcc.aal5VccSarTimeOuts = 0; /* no timer support */
347 ret = sizeof(mib_vcc) - copy_to_user(arg, &mib_vcc, sizeof(mib_vcc));
348 } else
349 ret = -EINVAL;
350 break;
351
352 default:
353 ret = -ENOIOCTLCMD;
354 }
355
356 return ret;
357 }
358
359 static int ppe_open(struct atm_vcc *vcc)
360 {
361 int ret;
362 short vpi = vcc->vpi;
363 int vci = vcc->vci;
364 struct port *port = &g_atm_priv_data.port[(int)vcc->dev->dev_data];
365 int conn;
366 int f_enable_irq = 0;
367
368 if ( vcc->qos.aal != ATM_AAL5 && vcc->qos.aal != ATM_AAL0 )
369 return -EPROTONOSUPPORT;
370
371 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
372 /* check bandwidth */
373 if ( (vcc->qos.txtp.traffic_class == ATM_CBR && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
374 || (vcc->qos.txtp.traffic_class == ATM_VBR_RT && vcc->qos.txtp.max_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
375 #if 0
376 || (vcc->qos.txtp.traffic_class == ATM_VBR_NRT && vcc->qos.txtp.scr > (port->tx_max_cell_rate - port->tx_current_cell_rate))
377 #endif
378 || (vcc->qos.txtp.traffic_class == ATM_UBR_PLUS && vcc->qos.txtp.min_pcr > (port->tx_max_cell_rate - port->tx_current_cell_rate)) )
379 {
380 ret = -EINVAL;
381 goto PPE_OPEN_EXIT;
382 }
383 #endif
384
385 /* check existing vpi,vci */
386 conn = find_vpivci(vpi, vci);
387 if ( conn >= 0 ) {
388 ret = -EADDRINUSE;
389 goto PPE_OPEN_EXIT;
390 }
391
392 /* check whether it need to enable irq */
393 if ( g_atm_priv_data.conn_table == 0 )
394 f_enable_irq = 1;
395
396 /* allocate connection */
397 for ( conn = 0; conn < MAX_PVC_NUMBER; conn++ ) {
398 if ( test_and_set_bit(conn, &g_atm_priv_data.conn_table) == 0 ) {
399 g_atm_priv_data.conn[conn].vcc = vcc;
400 break;
401 }
402 }
403 if ( conn == MAX_PVC_NUMBER ) {
404 ret = -EINVAL;
405 goto PPE_OPEN_EXIT;
406 }
407
408 /* reserve bandwidth */
409 switch ( vcc->qos.txtp.traffic_class ) {
410 case ATM_CBR:
411 case ATM_VBR_RT:
412 port->tx_current_cell_rate += vcc->qos.txtp.max_pcr;
413 break;
414 case ATM_VBR_NRT:
415 #if 0
416 port->tx_current_cell_rate += vcc->qos.txtp.scr;
417 #endif
418 break;
419 case ATM_UBR_PLUS:
420 port->tx_current_cell_rate += vcc->qos.txtp.min_pcr;
421 break;
422 }
423
424 /* set qsb */
425 set_qsb(vcc, &vcc->qos, conn);
426
427 /* update atm_vcc structure */
428 vcc->itf = (int)vcc->dev->dev_data;
429 vcc->vpi = vpi;
430 vcc->vci = vci;
431 set_bit(ATM_VF_READY, &vcc->flags);
432
433 /* enable irq */
434 if ( f_enable_irq ) {
435 ifx_atm_alloc_tx = atm_alloc_tx;
436
437 *MBOX_IGU1_ISRC = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
438 *MBOX_IGU1_IER = (1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM);
439
440 enable_irq(PPE_MAILBOX_IGU1_INT);
441 }
442
443 /* set port */
444 WTX_QUEUE_CONFIG(conn + FIRST_QSB_QID)->sbid = (int)vcc->dev->dev_data;
445
446 /* set htu entry */
447 set_htu_entry(vpi, vci, conn, vcc->qos.aal == ATM_AAL5 ? 1 : 0, 0);
448
449 *MBOX_IGU1_ISRC |= (1 << (conn + FIRST_QSB_QID + 16));
450 *MBOX_IGU1_IER |= (1 << (conn + FIRST_QSB_QID + 16));
451
452 ret = 0;
453
454 PPE_OPEN_EXIT:
455 return ret;
456 }
457
458 static void ppe_close(struct atm_vcc *vcc)
459 {
460 int conn;
461 struct port *port;
462 struct connection *connection;
463 if ( vcc == NULL )
464 return;
465
466 /* get connection id */
467 conn = find_vcc(vcc);
468 if ( conn < 0 ) {
469 pr_err("can't find vcc\n");
470 goto PPE_CLOSE_EXIT;
471 }
472 connection = &g_atm_priv_data.conn[conn];
473 port = &g_atm_priv_data.port[connection->port];
474
475 /* clear htu */
476 clear_htu_entry(conn);
477
478 /* release connection */
479 connection->vcc = NULL;
480 connection->aal5_vcc_crc_err = 0;
481 connection->aal5_vcc_oversize_sdu = 0;
482 clear_bit(conn, &g_atm_priv_data.conn_table);
483
484 /* disable irq */
485 if ( g_atm_priv_data.conn_table == 0 ) {
486 disable_irq(PPE_MAILBOX_IGU1_INT);
487 ifx_atm_alloc_tx = NULL;
488 }
489
490 /* release bandwidth */
491 switch ( vcc->qos.txtp.traffic_class )
492 {
493 case ATM_CBR:
494 case ATM_VBR_RT:
495 port->tx_current_cell_rate -= vcc->qos.txtp.max_pcr;
496 break;
497 case ATM_VBR_NRT:
498 #if 0
499 port->tx_current_cell_rate -= vcc->qos.txtp.scr;
500 #endif
501 break;
502 case ATM_UBR_PLUS:
503 port->tx_current_cell_rate -= vcc->qos.txtp.min_pcr;
504 break;
505 }
506
507 /* wait for incoming packets to be processed by upper layers */
508 tasklet_unlock_wait(&g_dma_tasklet);
509
510 PPE_CLOSE_EXIT:
511 return;
512 }
513
514 static int ppe_send(struct atm_vcc *vcc, struct sk_buff *skb)
515 {
516 int ret;
517 int conn;
518 int desc_base;
519 int byteoff;
520 int required;
521 /* the len of the data without offset and header */
522 int datalen;
523 unsigned long flags;
524 struct tx_descriptor reg_desc = {0};
525 struct tx_inband_header *header;
526 struct sk_buff *new_skb;
527
528 if ( vcc == NULL || skb == NULL )
529 return -EINVAL;
530
531
532 conn = find_vcc(vcc);
533 if ( conn < 0 ) {
534 ret = -EINVAL;
535 goto FIND_VCC_FAIL;
536 }
537
538 if ( !g_showtime ) {
539 pr_debug("not in showtime\n");
540 ret = -EIO;
541 goto PPE_SEND_FAIL;
542 }
543
544 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
545 required = sizeof(*header) + byteoff;
546 if (!skb_clone_writable(skb, required)) {
547 int expand_by = 0;
548 int ret;
549
550 if (skb_headroom(skb) < required)
551 expand_by = required - skb_headroom(skb);
552
553 ret = pskb_expand_head(skb, expand_by, 0, GFP_ATOMIC);
554 if (ret) {
555 printk("pskb_expand_head failed.\n");
556 atm_free_tx_skb_vcc(skb, vcc);
557 return ret;
558 }
559 }
560
561 datalen = skb->len;
562 header = (void *)skb_push(skb, byteoff + TX_INBAND_HEADER_LENGTH);
563
564
565 if ( vcc->qos.aal == ATM_AAL5 ) {
566 /* setup inband trailer */
567 header->uu = 0;
568 header->cpi = 0;
569 header->pad = aal5_fill_pattern;
570 header->res1 = 0;
571
572 /* setup cell header */
573 header->clp = (vcc->atm_options & ATM_ATMOPT_CLP) ? 1 : 0;
574 header->pti = ATM_PTI_US0;
575 header->vci = vcc->vci;
576 header->vpi = vcc->vpi;
577 header->gfc = 0;
578
579 /* setup descriptor */
580 reg_desc.dataptr = (unsigned int)skb->data >> 2;
581 reg_desc.datalen = datalen;
582 reg_desc.byteoff = byteoff;
583 reg_desc.iscell = 0;
584 } else {
585 reg_desc.dataptr = (unsigned int)skb->data >> 2;
586 reg_desc.datalen = skb->len;
587 reg_desc.byteoff = byteoff;
588 reg_desc.iscell = 1;
589 }
590
591 reg_desc.own = 1;
592 reg_desc.c = 1;
593 reg_desc.sop = reg_desc.eop = 1;
594
595 spin_lock_irqsave(&g_atm_priv_data.conn[conn].lock, flags);
596 desc_base = get_tx_desc(conn);
597 if ( desc_base < 0 ) {
598 spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
599 pr_debug("ALLOC_TX_CONNECTION_FAIL\n");
600 ret = -EIO;
601 goto PPE_SEND_FAIL;
602 }
603 /* update descriptor send pointer */
604 if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
605 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
606 g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
607
608 spin_unlock_irqrestore(&g_atm_priv_data.conn[conn].lock, flags);
609
610 if ( vcc->stats )
611 atomic_inc(&vcc->stats->tx);
612 if ( vcc->qos.aal == ATM_AAL5 )
613 g_atm_priv_data.wtx_pdu++;
614 /* write discriptor to memory and write back cache */
615 g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
616 dma_cache_wback((unsigned long)skb->data, skb->len);
617
618 mailbox_signal(conn, 1);
619
620 adsl_led_flash();
621
622 return 0;
623
624 FIND_VCC_FAIL:
625 pr_err("FIND_VCC_FAIL\n");
626 g_atm_priv_data.wtx_err_pdu++;
627 dev_kfree_skb_any(skb);
628 return ret;
629
630 PPE_SEND_FAIL:
631 if ( vcc->qos.aal == ATM_AAL5 )
632 g_atm_priv_data.wtx_drop_pdu++;
633 if ( vcc->stats )
634 atomic_inc(&vcc->stats->tx_err);
635 dev_kfree_skb_any(skb);
636 return ret;
637 }
638
639 /* operation and maintainance */
640 static int ppe_send_oam(struct atm_vcc *vcc, void *cell, int flags)
641 {
642 int conn;
643 struct uni_cell_header *uni_cell_header = (struct uni_cell_header *)cell;
644 int desc_base;
645 struct sk_buff *skb;
646 struct tx_descriptor reg_desc = {0};
647
648 if ( ((uni_cell_header->pti == ATM_PTI_SEGF5 || uni_cell_header->pti == ATM_PTI_E2EF5)
649 && find_vpivci(uni_cell_header->vpi, uni_cell_header->vci) < 0)
650 || ((uni_cell_header->vci == 0x03 || uni_cell_header->vci == 0x04)
651 && find_vpi(uni_cell_header->vpi) < 0) )
652 {
653 g_atm_priv_data.wtx_err_oam++;
654 return -EINVAL;
655 }
656
657 if ( !g_showtime ) {
658 pr_err("not in showtime\n");
659 g_atm_priv_data.wtx_drop_oam++;
660 return -EIO;
661 }
662
663 conn = find_vcc(vcc);
664 if ( conn < 0 ) {
665 pr_err("FIND_VCC_FAIL\n");
666 g_atm_priv_data.wtx_drop_oam++;
667 return -EINVAL;
668 }
669
670 skb = alloc_skb_tx(CELL_SIZE);
671 if ( skb == NULL ) {
672 pr_err("ALLOC_SKB_TX_FAIL\n");
673 g_atm_priv_data.wtx_drop_oam++;
674 return -ENOMEM;
675 }
676 skb_put(skb, CELL_SIZE);
677 memcpy(skb->data, cell, CELL_SIZE);
678
679 reg_desc.dataptr = (unsigned int)skb->data >> 2;
680 reg_desc.datalen = CELL_SIZE;
681 reg_desc.byteoff = 0;
682 reg_desc.iscell = 1;
683
684 reg_desc.own = 1;
685 reg_desc.c = 1;
686 reg_desc.sop = reg_desc.eop = 1;
687
688 desc_base = get_tx_desc(conn);
689 if ( desc_base < 0 ) {
690 dev_kfree_skb_any(skb);
691 pr_err("ALLOC_TX_CONNECTION_FAIL\n");
692 g_atm_priv_data.wtx_drop_oam++;
693 return -EIO;
694 }
695
696 if ( vcc->stats )
697 atomic_inc(&vcc->stats->tx);
698
699 /* update descriptor send pointer */
700 if ( g_atm_priv_data.conn[conn].tx_skb[desc_base] != NULL )
701 dev_kfree_skb_any(g_atm_priv_data.conn[conn].tx_skb[desc_base]);
702 g_atm_priv_data.conn[conn].tx_skb[desc_base] = skb;
703
704 /* write discriptor to memory and write back cache */
705 g_atm_priv_data.conn[conn].tx_desc[desc_base] = reg_desc;
706 dma_cache_wback((unsigned long)skb->data, CELL_SIZE);
707
708 mailbox_signal(conn, 1);
709
710 g_atm_priv_data.wtx_oam++;
711 adsl_led_flash();
712
713 return 0;
714 }
715
716 static int ppe_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
717 {
718 int conn;
719
720 if ( vcc == NULL || qos == NULL )
721 return -EINVAL;
722
723 conn = find_vcc(vcc);
724 if ( conn < 0 )
725 return -EINVAL;
726
727 set_qsb(vcc, qos, conn);
728
729 return 0;
730 }
731
732 static inline void adsl_led_flash(void)
733 {
734 ifx_mei_atm_led_blink();
735 }
736
737 /*
738 * Description:
739 * Add a 32-bit value to 64-bit value, and put result in a 64-bit variable.
740 * Input:
741 * opt1 --- ppe_u64_t, first operand, a 64-bit unsigned integer value
742 * opt2 --- unsigned int, second operand, a 32-bit unsigned integer value
743 * ret --- ppe_u64_t, pointer to a variable to hold result
744 * Output:
745 * none
746 */
747 static inline void u64_add_u32(ppe_u64_t opt1, unsigned int opt2, ppe_u64_t *ret)
748 {
749 ret->l = opt1.l + opt2;
750 if ( ret->l < opt1.l || ret->l < opt2 )
751 ret->h++;
752 }
753
754 static inline struct sk_buff* alloc_skb_rx(void)
755 {
756 struct sk_buff *skb;
757
758 skb = dev_alloc_skb(RX_DMA_CH_AAL_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
759 if ( skb != NULL ) {
760 /* must be burst length alignment */
761 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
762 skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
763 /* pub skb in reserved area "skb->data - 4" */
764 *((struct sk_buff **)skb->data - 1) = skb;
765 /* write back and invalidate cache */
766 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
767 /* invalidate cache */
768 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
769 dma_cache_inv((unsigned long)skb->data, LESS_CACHE_INV_LEN);
770 #else
771 dma_cache_inv((unsigned long)skb->data, RX_DMA_CH_AAL_BUF_SIZE);
772 #endif
773 }
774 return skb;
775 }
776
777 static inline struct sk_buff* alloc_skb_tx(unsigned int size)
778 {
779 struct sk_buff *skb;
780
781 /* allocate memory including header and padding */
782 size += TX_INBAND_HEADER_LENGTH + MAX_TX_PACKET_ALIGN_BYTES + MAX_TX_PACKET_PADDING_BYTES;
783 size &= ~(DATA_BUFFER_ALIGNMENT - 1);
784 skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
785 /* must be burst length alignment */
786 if ( skb != NULL )
787 skb_reserve(skb, (~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1)) + TX_INBAND_HEADER_LENGTH);
788 return skb;
789 }
790
791 struct sk_buff* atm_alloc_tx(struct atm_vcc *vcc, unsigned int size)
792 {
793 int conn;
794 struct sk_buff *skb;
795
796 /* oversize packet */
797 if ( size > aal5s_max_packet_size ) {
798 pr_err("atm_alloc_tx: oversize packet\n");
799 return NULL;
800 }
801 /* send buffer overflow */
802 if ( sk_wmem_alloc_get(sk_atm(vcc)) && !atm_may_send(vcc, size) ) {
803 pr_err("atm_alloc_tx: send buffer overflow\n");
804 return NULL;
805 }
806 conn = find_vcc(vcc);
807 if ( conn < 0 ) {
808 pr_err("atm_alloc_tx: unknown VCC\n");
809 return NULL;
810 }
811
812 skb = dev_alloc_skb(size);
813 if ( skb == NULL ) {
814 pr_err("atm_alloc_tx: sk buffer is used up\n");
815 return NULL;
816 }
817
818 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
819
820 return skb;
821 }
822
823 static inline void atm_free_tx_skb_vcc(struct sk_buff *skb, struct atm_vcc *vcc)
824 {
825 if ( vcc->pop != NULL )
826 vcc->pop(vcc, skb);
827 else
828 dev_kfree_skb_any(skb);
829 }
830
831 static inline struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
832 {
833 unsigned int skb_dataptr;
834 struct sk_buff *skb;
835
836 skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
837 skb = *(struct sk_buff **)skb_dataptr;
838
839 ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
840 ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
841
842 return skb;
843 }
844
845 static inline int get_tx_desc(unsigned int conn)
846 {
847 int desc_base = -1;
848 struct connection *p_conn = &g_atm_priv_data.conn[conn];
849
850 if ( p_conn->tx_desc[p_conn->tx_desc_pos].own == 0 ) {
851 desc_base = p_conn->tx_desc_pos;
852 if ( ++(p_conn->tx_desc_pos) == dma_tx_descriptor_length )
853 p_conn->tx_desc_pos = 0;
854 }
855
856 return desc_base;
857 }
858
859 static struct sk_buff* skb_duplicate(struct sk_buff *skb)
860 {
861 struct sk_buff *new_skb;
862
863 new_skb = alloc_skb_tx(skb->len);
864 if ( new_skb == NULL )
865 return NULL;
866
867 skb_put(new_skb, skb->len);
868 memcpy(new_skb->data, skb->data, skb->len);
869
870 return new_skb;
871 }
872
873 static struct sk_buff* skb_break_away_from_protocol(struct sk_buff *skb)
874 {
875 struct sk_buff *new_skb;
876
877 if ( skb_shared(skb) ) {
878 new_skb = skb_clone(skb, GFP_ATOMIC);
879 if ( new_skb == NULL )
880 return NULL;
881 } else
882 new_skb = skb_get(skb);
883
884 skb_dst_drop(new_skb);
885 #if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
886 nf_conntrack_put(new_skb->nfct);
887 new_skb->nfct = NULL;
888 #ifdef CONFIG_BRIDGE_NETFILTER
889 nf_bridge_put(new_skb->nf_bridge);
890 new_skb->nf_bridge = NULL;
891 #endif
892 #endif
893
894 return new_skb;
895 }
896
897 static void free_tx_ring(unsigned int queue)
898 {
899 unsigned long flags;
900 int i;
901 struct connection *conn = &g_atm_priv_data.conn[queue];
902 struct sk_buff *skb;
903
904 if (!conn)
905 return;
906
907 spin_lock_irqsave(&conn->lock, flags);
908
909 for (i = 0; i < dma_tx_descriptor_length; i++) {
910 if (conn->tx_desc[i].own == 0 && conn->tx_skb[i] != NULL) {
911 skb = conn->tx_skb[i];
912 conn->tx_skb[i] = NULL;
913 atm_free_tx_skb_vcc(skb, ATM_SKB(skb)->vcc);
914 }
915 }
916 spin_unlock_irqrestore(&conn->lock, flags);
917 }
918
919 static void mailbox_tx_handler(unsigned int queue_bitmap)
920 {
921 int i;
922 int bit;
923
924 /* only get valid queues */
925 queue_bitmap &= g_atm_priv_data.conn_table;
926
927 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
928 if (queue_bitmap & bit)
929 free_tx_ring(i);
930 }
931 }
932
933 static inline void mailbox_oam_rx_handler(void)
934 {
935 unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM)->vlddes;
936 struct rx_descriptor reg_desc;
937 struct uni_cell_header *header;
938 int conn;
939 struct atm_vcc *vcc;
940 unsigned int i;
941
942 for ( i = 0; i < vlddes; i++ ) {
943 unsigned int loop_count = 0;
944
945 do {
946 reg_desc = g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos];
947 if ( ++loop_count == 1000 )
948 break;
949 } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready
950 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, oam_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.oam_desc_pos);
951
952 header = (struct uni_cell_header *)&g_atm_priv_data.oam_buf[g_atm_priv_data.oam_desc_pos * RX_DMA_CH_OAM_BUF_SIZE];
953
954 if ( header->pti == ATM_PTI_SEGF5 || header->pti == ATM_PTI_E2EF5 )
955 conn = find_vpivci(header->vpi, header->vci);
956 else if ( header->vci == 0x03 || header->vci == 0x04 )
957 conn = find_vpi(header->vpi);
958 else
959 conn = -1;
960
961 if ( conn >= 0 && g_atm_priv_data.conn[conn].vcc != NULL ) {
962 vcc = g_atm_priv_data.conn[conn].vcc;
963
964 if ( vcc->push_oam != NULL )
965 vcc->push_oam(vcc, header);
966 else
967 ifx_push_oam((unsigned char *)header);
968
969 g_atm_priv_data.wrx_oam++;
970
971 adsl_led_flash();
972 } else
973 g_atm_priv_data.wrx_drop_oam++;
974
975 reg_desc.byteoff = 0;
976 reg_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
977 reg_desc.own = 1;
978 reg_desc.c = 0;
979
980 g_atm_priv_data.oam_desc[g_atm_priv_data.oam_desc_pos] = reg_desc;
981 if ( ++g_atm_priv_data.oam_desc_pos == RX_DMA_CH_OAM_DESC_LEN )
982 g_atm_priv_data.oam_desc_pos = 0;
983
984 dma_cache_inv((unsigned long)header, CELL_SIZE);
985 mailbox_signal(RX_DMA_CH_OAM, 0);
986 }
987 }
988
989 static inline void mailbox_aal_rx_handler(void)
990 {
991 unsigned int vlddes = WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL)->vlddes;
992 struct rx_descriptor reg_desc;
993 int conn;
994 struct atm_vcc *vcc;
995 struct sk_buff *skb, *new_skb;
996 struct rx_inband_trailer *trailer;
997 unsigned int i;
998
999 for ( i = 0; i < vlddes; i++ ) {
1000 unsigned int loop_count = 0;
1001
1002 do {
1003 reg_desc = g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos];
1004 if ( ++loop_count == 1000 )
1005 break;
1006 } while ( reg_desc.own || !reg_desc.c ); // keep test OWN and C bit until data is ready
1007 ASSERT(loop_count == 1, "loop_count = %u, own = %d, c = %d, aal_desc_pos = %u", loop_count, (int)reg_desc.own, (int)reg_desc.c, g_atm_priv_data.aal_desc_pos);
1008
1009 conn = reg_desc.id;
1010
1011 if ( g_atm_priv_data.conn[conn].vcc != NULL ) {
1012 vcc = g_atm_priv_data.conn[conn].vcc;
1013
1014 skb = get_skb_rx_pointer(reg_desc.dataptr);
1015
1016 if ( reg_desc.err ) {
1017 if ( vcc->qos.aal == ATM_AAL5 ) {
1018 trailer = (struct rx_inband_trailer *)((unsigned int)skb->data + ((reg_desc.byteoff + reg_desc.datalen + MAX_RX_PACKET_PADDING_BYTES) & ~MAX_RX_PACKET_PADDING_BYTES));
1019 if ( trailer->stw_crc )
1020 g_atm_priv_data.conn[conn].aal5_vcc_crc_err++;
1021 if ( trailer->stw_ovz )
1022 g_atm_priv_data.conn[conn].aal5_vcc_oversize_sdu++;
1023 g_atm_priv_data.wrx_drop_pdu++;
1024 }
1025 if ( vcc->stats ) {
1026 atomic_inc(&vcc->stats->rx_drop);
1027 atomic_inc(&vcc->stats->rx_err);
1028 }
1029 reg_desc.err = 0;
1030 } else if ( atm_charge(vcc, skb->truesize) ) {
1031 new_skb = alloc_skb_rx();
1032 if ( new_skb != NULL ) {
1033 #if defined(ENABLE_LESS_CACHE_INV) && ENABLE_LESS_CACHE_INV
1034 if ( reg_desc.byteoff + reg_desc.datalen > LESS_CACHE_INV_LEN )
1035 dma_cache_inv((unsigned long)skb->data + LESS_CACHE_INV_LEN, reg_desc.byteoff + reg_desc.datalen - LESS_CACHE_INV_LEN);
1036 #endif
1037
1038 skb_reserve(skb, reg_desc.byteoff);
1039 skb_put(skb, reg_desc.datalen);
1040 ATM_SKB(skb)->vcc = vcc;
1041
1042 vcc->push(vcc, skb);
1043
1044 if ( vcc->qos.aal == ATM_AAL5 )
1045 g_atm_priv_data.wrx_pdu++;
1046 if ( vcc->stats )
1047 atomic_inc(&vcc->stats->rx);
1048 adsl_led_flash();
1049
1050 reg_desc.dataptr = (unsigned int)new_skb->data >> 2;
1051 } else {
1052 atm_return(vcc, skb->truesize);
1053 if ( vcc->qos.aal == ATM_AAL5 )
1054 g_atm_priv_data.wrx_drop_pdu++;
1055 if ( vcc->stats )
1056 atomic_inc(&vcc->stats->rx_drop);
1057 }
1058 } else {
1059 if ( vcc->qos.aal == ATM_AAL5 )
1060 g_atm_priv_data.wrx_drop_pdu++;
1061 if ( vcc->stats )
1062 atomic_inc(&vcc->stats->rx_drop);
1063 }
1064 } else {
1065 g_atm_priv_data.wrx_drop_pdu++;
1066 }
1067
1068 reg_desc.byteoff = 0;
1069 reg_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1070 reg_desc.own = 1;
1071 reg_desc.c = 0;
1072
1073 g_atm_priv_data.aal_desc[g_atm_priv_data.aal_desc_pos] = reg_desc;
1074 if ( ++g_atm_priv_data.aal_desc_pos == dma_rx_descriptor_length )
1075 g_atm_priv_data.aal_desc_pos = 0;
1076
1077 mailbox_signal(RX_DMA_CH_AAL, 0);
1078 }
1079 }
1080
1081 static void do_ppe_tasklet(unsigned long data)
1082 {
1083 unsigned int irqs = *MBOX_IGU1_ISR;
1084 *MBOX_IGU1_ISRC = *MBOX_IGU1_ISR;
1085
1086 if (irqs & (1 << RX_DMA_CH_AAL))
1087 mailbox_aal_rx_handler();
1088 if (irqs & (1 << RX_DMA_CH_OAM))
1089 mailbox_oam_rx_handler();
1090
1091 /* any valid tx irqs */
1092 if ((irqs >> (FIRST_QSB_QID + 16)) & g_atm_priv_data.conn_table)
1093 mailbox_tx_handler(irqs >> (FIRST_QSB_QID + 16));
1094
1095 if ((*MBOX_IGU1_ISR & ((1 << RX_DMA_CH_AAL) | (1 << RX_DMA_CH_OAM))) != 0)
1096 tasklet_schedule(&g_dma_tasklet);
1097 else if (*MBOX_IGU1_ISR >> (FIRST_QSB_QID + 16)) /* TX queue */
1098 tasklet_schedule(&g_dma_tasklet);
1099 else
1100 enable_irq(PPE_MAILBOX_IGU1_INT);
1101 }
1102
1103 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
1104 {
1105 if ( !*MBOX_IGU1_ISR )
1106 return IRQ_HANDLED;
1107
1108 disable_irq_nosync(PPE_MAILBOX_IGU1_INT);
1109 tasklet_schedule(&g_dma_tasklet);
1110
1111 return IRQ_HANDLED;
1112 }
1113
1114 static inline void mailbox_signal(unsigned int queue, int is_tx)
1115 {
1116 int count = 1000;
1117
1118 if ( is_tx ) {
1119 while ( MBOX_IGU3_ISR_ISR(queue + FIRST_QSB_QID + 16) && count > 0 )
1120 count--;
1121 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue + FIRST_QSB_QID + 16);
1122 } else {
1123 while ( MBOX_IGU3_ISR_ISR(queue) && count > 0 )
1124 count--;
1125 *MBOX_IGU3_ISRS = MBOX_IGU3_ISRS_SET(queue);
1126 }
1127
1128 ASSERT(count > 0, "queue = %u, is_tx = %d, MBOX_IGU3_ISR = 0x%08x", queue, is_tx, IFX_REG_R32(MBOX_IGU3_ISR));
1129 }
1130
1131 static void set_qsb(struct atm_vcc *vcc, struct atm_qos *qos, unsigned int queue)
1132 {
1133 struct clk *fpi_clk = clk_get_fpi();
1134 unsigned int qsb_clk = clk_get_rate(fpi_clk);
1135 unsigned int qsb_qid = queue + FIRST_QSB_QID;
1136 union qsb_queue_parameter_table qsb_queue_parameter_table = {{0}};
1137 union qsb_queue_vbr_parameter_table qsb_queue_vbr_parameter_table = {{0}};
1138 unsigned int tmp;
1139
1140
1141 /*
1142 * Peak Cell Rate (PCR) Limiter
1143 */
1144 if ( qos->txtp.max_pcr == 0 )
1145 qsb_queue_parameter_table.bit.tp = 0; /* disable PCR limiter */
1146 else {
1147 /* peak cell rate would be slightly lower than requested [maximum_rate / pcr = (qsb_clock / 8) * (time_step / 4) / pcr] */
1148 tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.max_pcr + 1;
1149 /* check if overflow takes place */
1150 qsb_queue_parameter_table.bit.tp = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1151 }
1152
1153 #if !defined(DISABLE_QOS_WORKAROUND) || !DISABLE_QOS_WORKAROUND
1154 // A funny issue. Create two PVCs, one UBR and one UBR with max_pcr.
1155 // Send packets to these two PVCs at same time, it trigger strange behavior.
1156 // In A1, RAM from 0x80000000 to 0x0x8007FFFF was corrupted with fixed pattern 0x00000000 0x40000000.
1157 // In A4, PPE firmware keep emiting unknown cell and do not respond to driver.
1158 // To work around, create UBR always with max_pcr.
1159 // If user want to create UBR without max_pcr, we give a default one larger than line-rate.
1160 if ( qos->txtp.traffic_class == ATM_UBR && qsb_queue_parameter_table.bit.tp == 0 ) {
1161 int port = g_atm_priv_data.conn[queue].port;
1162 unsigned int max_pcr = g_atm_priv_data.port[port].tx_max_cell_rate + 1000;
1163
1164 tmp = ((qsb_clk * qsb_tstep) >> 5) / max_pcr + 1;
1165 if ( tmp > QSB_TP_TS_MAX )
1166 tmp = QSB_TP_TS_MAX;
1167 else if ( tmp < 1 )
1168 tmp = 1;
1169 qsb_queue_parameter_table.bit.tp = tmp;
1170 }
1171 #endif
1172
1173 /*
1174 * Weighted Fair Queueing Factor (WFQF)
1175 */
1176 switch ( qos->txtp.traffic_class ) {
1177 case ATM_CBR:
1178 case ATM_VBR_RT:
1179 /* real time queue gets weighted fair queueing bypass */
1180 qsb_queue_parameter_table.bit.wfqf = 0;
1181 break;
1182 case ATM_VBR_NRT:
1183 case ATM_UBR_PLUS:
1184 /* WFQF calculation here is based on virtual cell rates, to reduce granularity for high rates */
1185 /* WFQF is maximum cell rate / garenteed cell rate */
1186 /* wfqf = qsb_minimum_cell_rate * QSB_WFQ_NONUBR_MAX / requested_minimum_peak_cell_rate */
1187 if ( qos->txtp.min_pcr == 0 )
1188 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1189 else {
1190 tmp = QSB_GCR_MIN * QSB_WFQ_NONUBR_MAX / qos->txtp.min_pcr;
1191 if ( tmp == 0 )
1192 qsb_queue_parameter_table.bit.wfqf = 1;
1193 else if ( tmp > QSB_WFQ_NONUBR_MAX )
1194 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_NONUBR_MAX;
1195 else
1196 qsb_queue_parameter_table.bit.wfqf = tmp;
1197 }
1198 break;
1199 default:
1200 case ATM_UBR:
1201 qsb_queue_parameter_table.bit.wfqf = QSB_WFQ_UBR_BYPASS;
1202 }
1203
1204 /*
1205 * Sustained Cell Rate (SCR) Leaky Bucket Shaper VBR.0/VBR.1
1206 */
1207 if ( qos->txtp.traffic_class == ATM_VBR_RT || qos->txtp.traffic_class == ATM_VBR_NRT ) {
1208 #if 0
1209 if ( qos->txtp.scr == 0 ) {
1210 #endif
1211 /* disable shaper */
1212 qsb_queue_vbr_parameter_table.bit.taus = 0;
1213 qsb_queue_vbr_parameter_table.bit.ts = 0;
1214 #if 0
1215 } else {
1216 /* Cell Loss Priority (CLP) */
1217 if ( (vcc->atm_options & ATM_ATMOPT_CLP) )
1218 /* CLP1 */
1219 qsb_queue_parameter_table.bit.vbr = 1;
1220 else
1221 /* CLP0 */
1222 qsb_queue_parameter_table.bit.vbr = 0;
1223 /* Rate Shaper Parameter (TS) and Burst Tolerance Parameter for SCR (tauS) */
1224 tmp = ((qsb_clk * qsb_tstep) >> 5) / qos->txtp.scr + 1;
1225 qsb_queue_vbr_parameter_table.bit.ts = tmp > QSB_TP_TS_MAX ? QSB_TP_TS_MAX : tmp;
1226 tmp = (qos->txtp.mbs - 1) * (qsb_queue_vbr_parameter_table.bit.ts - qsb_queue_parameter_table.bit.tp) / 64;
1227 if ( tmp == 0 )
1228 qsb_queue_vbr_parameter_table.bit.taus = 1;
1229 else if ( tmp > QSB_TAUS_MAX )
1230 qsb_queue_vbr_parameter_table.bit.taus = QSB_TAUS_MAX;
1231 else
1232 qsb_queue_vbr_parameter_table.bit.taus = tmp;
1233 }
1234 #endif
1235 } else {
1236 qsb_queue_vbr_parameter_table.bit.taus = 0;
1237 qsb_queue_vbr_parameter_table.bit.ts = 0;
1238 }
1239
1240 /* Queue Parameter Table (QPT) */
1241 *QSB_RTM = QSB_RTM_DM_SET(QSB_QPT_SET_MASK);
1242 *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_parameter_table.dword);
1243 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_QPT) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1244 /* Queue VBR Paramter Table (QVPT) */
1245 *QSB_RTM = QSB_RTM_DM_SET(QSB_QVPT_SET_MASK);
1246 *QSB_RTD = QSB_RTD_TTV_SET(qsb_queue_vbr_parameter_table.dword);
1247 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) | QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_VBR) | QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) | QSB_RAMAC_TESEL_SET(qsb_qid);
1248
1249 }
1250
1251 static void qsb_global_set(void)
1252 {
1253 struct clk *fpi_clk = clk_get_fpi();
1254 unsigned int qsb_clk = clk_get_rate(fpi_clk);
1255 int i;
1256 unsigned int tmp1, tmp2, tmp3;
1257
1258 *QSB_ICDV = QSB_ICDV_TAU_SET(qsb_tau);
1259 *QSB_SBL = QSB_SBL_SBL_SET(qsb_srvm);
1260 *QSB_CFG = QSB_CFG_TSTEPC_SET(qsb_tstep >> 1);
1261
1262 /*
1263 * set SCT and SPT per port
1264 */
1265 for ( i = 0; i < ATM_PORT_NUMBER; i++ ) {
1266 if ( g_atm_priv_data.port[i].tx_max_cell_rate != 0 ) {
1267 tmp1 = ((qsb_clk * qsb_tstep) >> 1) / g_atm_priv_data.port[i].tx_max_cell_rate;
1268 tmp2 = tmp1 >> 6; /* integer value of Tsb */
1269 tmp3 = (tmp1 & ((1 << 6) - 1)) + 1; /* fractional part of Tsb */
1270 /* carry over to integer part (?) */
1271 if ( tmp3 == (1 << 6) ) {
1272 tmp3 = 0;
1273 tmp2++;
1274 }
1275 if ( tmp2 == 0 )
1276 tmp2 = tmp3 = 1;
1277 /* 1. set mask */
1278 /* 2. write value to data transfer register */
1279 /* 3. start the tranfer */
1280 /* SCT (FracRate) */
1281 *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SCT_MASK);
1282 *QSB_RTD = QSB_RTD_TTV_SET(tmp3);
1283 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1284 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SCT) |
1285 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1286 QSB_RAMAC_TESEL_SET(i & 0x01);
1287 /* SPT (SBV + PN + IntRage) */
1288 *QSB_RTM = QSB_RTM_DM_SET(QSB_SET_SPT_MASK);
1289 *QSB_RTD = QSB_RTD_TTV_SET(QSB_SPT_SBV_VALID | QSB_SPT_PN_SET(i & 0x01) | QSB_SPT_INTRATE_SET(tmp2));
1290 *QSB_RAMAC = QSB_RAMAC_RW_SET(QSB_RAMAC_RW_WRITE) |
1291 QSB_RAMAC_TSEL_SET(QSB_RAMAC_TSEL_SPT) |
1292 QSB_RAMAC_LH_SET(QSB_RAMAC_LH_LOW) |
1293 QSB_RAMAC_TESEL_SET(i & 0x01);
1294 }
1295 }
1296 }
1297
1298 static inline void set_htu_entry(unsigned int vpi, unsigned int vci, unsigned int queue, int aal5, int is_retx)
1299 {
1300 struct htu_entry htu_entry = {
1301 res1: 0x00,
1302 clp: is_retx ? 0x01 : 0x00,
1303 pid: g_atm_priv_data.conn[queue].port & 0x01,
1304 vpi: vpi,
1305 vci: vci,
1306 pti: 0x00,
1307 vld: 0x01};
1308
1309 struct htu_mask htu_mask = {
1310 set: 0x01,
1311 clp: 0x01,
1312 pid_mask: 0x02,
1313 vpi_mask: 0x00,
1314 vci_mask: 0x0000,
1315 pti_mask: 0x03, // 0xx, user data
1316 clear: 0x00};
1317
1318 struct htu_result htu_result = {
1319 res1: 0x00,
1320 cellid: queue,
1321 res2: 0x00,
1322 type: aal5 ? 0x00 : 0x01,
1323 ven: 0x01,
1324 res3: 0x00,
1325 qid: queue};
1326
1327 *HTU_RESULT(queue + OAM_HTU_ENTRY_NUMBER) = htu_result;
1328 *HTU_MASK(queue + OAM_HTU_ENTRY_NUMBER) = htu_mask;
1329 *HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER) = htu_entry;
1330 }
1331
1332 static inline void clear_htu_entry(unsigned int queue)
1333 {
1334 HTU_ENTRY(queue + OAM_HTU_ENTRY_NUMBER)->vld = 0;
1335 }
1336
1337 static void validate_oam_htu_entry(void)
1338 {
1339 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 1;
1340 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 1;
1341 HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 1;
1342 }
1343
1344 static void invalidate_oam_htu_entry(void)
1345 {
1346 HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY)->vld = 0;
1347 HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY)->vld = 0;
1348 HTU_ENTRY(OAM_F5_HTU_ENTRY)->vld = 0;
1349 }
1350
1351 static inline int find_vpi(unsigned int vpi)
1352 {
1353 int i;
1354 unsigned int bit;
1355
1356 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1357 if ( (g_atm_priv_data.conn_table & bit) != 0
1358 && g_atm_priv_data.conn[i].vcc != NULL
1359 && vpi == g_atm_priv_data.conn[i].vcc->vpi )
1360 return i;
1361 }
1362
1363 return -1;
1364 }
1365
1366 static inline int find_vpivci(unsigned int vpi, unsigned int vci)
1367 {
1368 int i;
1369 unsigned int bit;
1370
1371 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1372 if ( (g_atm_priv_data.conn_table & bit) != 0
1373 && g_atm_priv_data.conn[i].vcc != NULL
1374 && vpi == g_atm_priv_data.conn[i].vcc->vpi
1375 && vci == g_atm_priv_data.conn[i].vcc->vci )
1376 return i;
1377 }
1378
1379 return -1;
1380 }
1381
1382 static inline int find_vcc(struct atm_vcc *vcc)
1383 {
1384 int i;
1385 unsigned int bit;
1386
1387 for ( i = 0, bit = 1; i < MAX_PVC_NUMBER; i++, bit <<= 1 ) {
1388 if ( (g_atm_priv_data.conn_table & bit) != 0
1389 && g_atm_priv_data.conn[i].vcc == vcc )
1390 return i;
1391 }
1392
1393 return -1;
1394 }
1395
1396 static inline int ifx_atm_version(const struct ltq_atm_ops *ops, char *buf)
1397 {
1398 int len = 0;
1399 unsigned int major, minor;
1400
1401 ops->fw_ver(&major, &minor);
1402
1403 len += sprintf(buf + len, "ATM%d.%d.%d", IFX_ATM_VER_MAJOR, IFX_ATM_VER_MID, IFX_ATM_VER_MINOR);
1404 len += sprintf(buf + len, " ATM (A1) firmware version %d.%d\n", major, minor);
1405
1406 return len;
1407 }
1408
1409 static inline void check_parameters(void)
1410 {
1411 /* Please refer to Amazon spec 15.4 for setting these values. */
1412 if ( qsb_tau < 1 )
1413 qsb_tau = 1;
1414 if ( qsb_tstep < 1 )
1415 qsb_tstep = 1;
1416 else if ( qsb_tstep > 4 )
1417 qsb_tstep = 4;
1418 else if ( qsb_tstep == 3 )
1419 qsb_tstep = 2;
1420
1421 /* There is a delay between PPE write descriptor and descriptor is */
1422 /* really stored in memory. Host also has this delay when writing */
1423 /* descriptor. So PPE will use this value to determine if the write */
1424 /* operation makes effect. */
1425 if ( write_descriptor_delay < 0 )
1426 write_descriptor_delay = 0;
1427
1428 if ( aal5_fill_pattern < 0 )
1429 aal5_fill_pattern = 0;
1430 else
1431 aal5_fill_pattern &= 0xFF;
1432
1433 /* Because of the limitation of length field in descriptors, the packet */
1434 /* size could not be larger than 64K minus overhead size. */
1435 if ( aal5r_max_packet_size < 0 )
1436 aal5r_max_packet_size = 0;
1437 else if ( aal5r_max_packet_size >= 65535 - MAX_RX_FRAME_EXTRA_BYTES )
1438 aal5r_max_packet_size = 65535 - MAX_RX_FRAME_EXTRA_BYTES;
1439 if ( aal5r_min_packet_size < 0 )
1440 aal5r_min_packet_size = 0;
1441 else if ( aal5r_min_packet_size > aal5r_max_packet_size )
1442 aal5r_min_packet_size = aal5r_max_packet_size;
1443 if ( aal5s_max_packet_size < 0 )
1444 aal5s_max_packet_size = 0;
1445 else if ( aal5s_max_packet_size >= 65535 - MAX_TX_FRAME_EXTRA_BYTES )
1446 aal5s_max_packet_size = 65535 - MAX_TX_FRAME_EXTRA_BYTES;
1447 if ( aal5s_min_packet_size < 0 )
1448 aal5s_min_packet_size = 0;
1449 else if ( aal5s_min_packet_size > aal5s_max_packet_size )
1450 aal5s_min_packet_size = aal5s_max_packet_size;
1451
1452 if ( dma_rx_descriptor_length < 2 )
1453 dma_rx_descriptor_length = 2;
1454 if ( dma_tx_descriptor_length < 2 )
1455 dma_tx_descriptor_length = 2;
1456 if ( dma_rx_clp1_descriptor_threshold < 0 )
1457 dma_rx_clp1_descriptor_threshold = 0;
1458 else if ( dma_rx_clp1_descriptor_threshold > dma_rx_descriptor_length )
1459 dma_rx_clp1_descriptor_threshold = dma_rx_descriptor_length;
1460
1461 if ( dma_tx_descriptor_length < 2 )
1462 dma_tx_descriptor_length = 2;
1463 }
1464
1465 static inline int init_priv_data(void)
1466 {
1467 void *p;
1468 int i;
1469 struct rx_descriptor rx_desc = {0};
1470 struct sk_buff *skb;
1471 volatile struct tx_descriptor *p_tx_desc;
1472 struct sk_buff **ppskb;
1473
1474 // clear atm private data structure
1475 memset(&g_atm_priv_data, 0, sizeof(g_atm_priv_data));
1476
1477 // allocate memory for RX (AAL) descriptors
1478 p = kzalloc(dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1479 if ( p == NULL )
1480 return -1;
1481 dma_cache_wback_inv((unsigned long)p, dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1482 g_atm_priv_data.aal_desc_base = p;
1483 p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1484 g_atm_priv_data.aal_desc = (volatile struct rx_descriptor *)p;
1485
1486 // allocate memory for RX (OAM) descriptors
1487 p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1488 if ( p == NULL )
1489 return -1;
1490 dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1491 g_atm_priv_data.oam_desc_base = p;
1492 p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1493 g_atm_priv_data.oam_desc = (volatile struct rx_descriptor *)p;
1494
1495 // allocate memory for RX (OAM) buffer
1496 p = kzalloc(RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT, GFP_KERNEL);
1497 if ( p == NULL )
1498 return -1;
1499 dma_cache_wback_inv((unsigned long)p, RX_DMA_CH_OAM_DESC_LEN * RX_DMA_CH_OAM_BUF_SIZE + DATA_BUFFER_ALIGNMENT);
1500 g_atm_priv_data.oam_buf_base = p;
1501 p = (void *)(((unsigned int)p + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1));
1502 g_atm_priv_data.oam_buf = p;
1503
1504 // allocate memory for TX descriptors
1505 p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1506 if ( p == NULL )
1507 return -1;
1508 dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
1509 g_atm_priv_data.tx_desc_base = p;
1510
1511 // allocate memory for TX skb pointers
1512 p = kzalloc(MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
1513 if ( p == NULL )
1514 return -1;
1515 dma_cache_wback_inv((unsigned long)p, MAX_PVC_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
1516 g_atm_priv_data.tx_skb_base = p;
1517
1518 // setup RX (AAL) descriptors
1519 rx_desc.own = 1;
1520 rx_desc.c = 0;
1521 rx_desc.sop = 1;
1522 rx_desc.eop = 1;
1523 rx_desc.byteoff = 0;
1524 rx_desc.id = 0;
1525 rx_desc.err = 0;
1526 rx_desc.datalen = RX_DMA_CH_AAL_BUF_SIZE;
1527 for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1528 skb = alloc_skb_rx();
1529 if ( skb == NULL )
1530 return -1;
1531 rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
1532 g_atm_priv_data.aal_desc[i] = rx_desc;
1533 }
1534
1535 // setup RX (OAM) descriptors
1536 p = (void *)((unsigned int)g_atm_priv_data.oam_buf | KSEG1);
1537 rx_desc.own = 1;
1538 rx_desc.c = 0;
1539 rx_desc.sop = 1;
1540 rx_desc.eop = 1;
1541 rx_desc.byteoff = 0;
1542 rx_desc.id = 0;
1543 rx_desc.err = 0;
1544 rx_desc.datalen = RX_DMA_CH_OAM_BUF_SIZE;
1545 for ( i = 0; i < RX_DMA_CH_OAM_DESC_LEN; i++ ) {
1546 rx_desc.dataptr = ((unsigned int)p >> 2) & 0x0FFFFFFF;
1547 g_atm_priv_data.oam_desc[i] = rx_desc;
1548 p = (void *)((unsigned int)p + RX_DMA_CH_OAM_BUF_SIZE);
1549 }
1550
1551 // setup TX descriptors and skb pointers
1552 p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_atm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1553 ppskb = (struct sk_buff **)(((unsigned int)g_atm_priv_data.tx_skb_base + 3) & ~3);
1554 for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1555 spin_lock_init(&g_atm_priv_data.conn[i].lock);
1556 g_atm_priv_data.conn[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
1557 g_atm_priv_data.conn[i].tx_skb = &ppskb[i * dma_tx_descriptor_length];
1558 }
1559
1560 for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1561 g_atm_priv_data.port[i].tx_max_cell_rate = DEFAULT_TX_LINK_RATE;
1562
1563 return 0;
1564 }
1565
1566 static inline void clear_priv_data(void)
1567 {
1568 int i, j;
1569 struct sk_buff *skb;
1570
1571 for ( i = 0; i < MAX_PVC_NUMBER; i++ ) {
1572 if ( g_atm_priv_data.conn[i].tx_skb != NULL ) {
1573 for ( j = 0; j < dma_tx_descriptor_length; j++ )
1574 if ( g_atm_priv_data.conn[i].tx_skb[j] != NULL )
1575 dev_kfree_skb_any(g_atm_priv_data.conn[i].tx_skb[j]);
1576 }
1577 }
1578
1579 if ( g_atm_priv_data.tx_skb_base != NULL )
1580 kfree(g_atm_priv_data.tx_skb_base);
1581
1582 if ( g_atm_priv_data.tx_desc_base != NULL )
1583 kfree(g_atm_priv_data.tx_desc_base);
1584
1585 if ( g_atm_priv_data.oam_buf_base != NULL )
1586 kfree(g_atm_priv_data.oam_buf_base);
1587
1588 if ( g_atm_priv_data.oam_desc_base != NULL )
1589 kfree(g_atm_priv_data.oam_desc_base);
1590
1591 if ( g_atm_priv_data.aal_desc_base != NULL ) {
1592 for ( i = 0; i < dma_rx_descriptor_length; i++ ) {
1593 if ( g_atm_priv_data.aal_desc[i].sop || g_atm_priv_data.aal_desc[i].eop ) { // descriptor initialized
1594 skb = get_skb_rx_pointer(g_atm_priv_data.aal_desc[i].dataptr);
1595 dev_kfree_skb_any(skb);
1596 }
1597 }
1598 kfree(g_atm_priv_data.aal_desc_base);
1599 }
1600 }
1601
1602 static inline void init_rx_tables(void)
1603 {
1604 int i;
1605 struct wrx_queue_config wrx_queue_config = {0};
1606 struct wrx_dma_channel_config wrx_dma_channel_config = {0};
1607 struct htu_entry htu_entry = {0};
1608 struct htu_result htu_result = {0};
1609 struct htu_mask htu_mask = {
1610 set: 0x01,
1611 clp: 0x01,
1612 pid_mask: 0x00,
1613 vpi_mask: 0x00,
1614 vci_mask: 0x00,
1615 pti_mask: 0x00,
1616 clear: 0x00
1617 };
1618
1619 /*
1620 * General Registers
1621 */
1622 *CFG_WRX_HTUTS = MAX_PVC_NUMBER + OAM_HTU_ENTRY_NUMBER;
1623 #ifndef CONFIG_AMAZON_SE
1624 *CFG_WRX_QNUM = MAX_QUEUE_NUMBER;
1625 #endif
1626 *CFG_WRX_DCHNUM = RX_DMA_CH_TOTAL;
1627 *WRX_DMACH_ON = (1 << RX_DMA_CH_TOTAL) - 1;
1628 *WRX_HUNT_BITTH = DEFAULT_RX_HUNT_BITTH;
1629
1630 /*
1631 * WRX Queue Configuration Table
1632 */
1633 wrx_queue_config.uumask = 0xFF;
1634 wrx_queue_config.cpimask = 0xFF;
1635 wrx_queue_config.uuexp = 0;
1636 wrx_queue_config.cpiexp = 0;
1637 wrx_queue_config.mfs = aal5r_max_packet_size;
1638 wrx_queue_config.oversize = aal5r_max_packet_size;
1639 wrx_queue_config.undersize = aal5r_min_packet_size;
1640 wrx_queue_config.errdp = aal5r_drop_error_packet;
1641 wrx_queue_config.dmach = RX_DMA_CH_AAL;
1642 for ( i = 0; i < MAX_QUEUE_NUMBER; i++ )
1643 *WRX_QUEUE_CONFIG(i) = wrx_queue_config;
1644 WRX_QUEUE_CONFIG(OAM_RX_QUEUE)->dmach = RX_DMA_CH_OAM;
1645
1646 /*
1647 * WRX DMA Channel Configuration Table
1648 */
1649 wrx_dma_channel_config.chrl = 0;
1650 wrx_dma_channel_config.clp1th = dma_rx_clp1_descriptor_threshold;
1651 wrx_dma_channel_config.mode = 0;
1652 wrx_dma_channel_config.rlcfg = 0;
1653
1654 wrx_dma_channel_config.deslen = RX_DMA_CH_OAM_DESC_LEN;
1655 wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.oam_desc >> 2) & 0x0FFFFFFF;
1656 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_OAM) = wrx_dma_channel_config;
1657
1658 wrx_dma_channel_config.deslen = dma_rx_descriptor_length;
1659 wrx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.aal_desc >> 2) & 0x0FFFFFFF;
1660 *WRX_DMA_CHANNEL_CONFIG(RX_DMA_CH_AAL) = wrx_dma_channel_config;
1661
1662 /*
1663 * HTU Tables
1664 */
1665 for (i = 0; i < MAX_PVC_NUMBER; i++) {
1666 htu_result.qid = (unsigned int)i;
1667
1668 *HTU_ENTRY(i + OAM_HTU_ENTRY_NUMBER) = htu_entry;
1669 *HTU_MASK(i + OAM_HTU_ENTRY_NUMBER) = htu_mask;
1670 *HTU_RESULT(i + OAM_HTU_ENTRY_NUMBER) = htu_result;
1671 }
1672
1673 /* OAM HTU Entry */
1674 htu_entry.vci = 0x03;
1675 htu_mask.pid_mask = 0x03;
1676 htu_mask.vpi_mask = 0xFF;
1677 htu_mask.vci_mask = 0x0000;
1678 htu_mask.pti_mask = 0x07;
1679 htu_result.cellid = OAM_RX_QUEUE;
1680 htu_result.type = 1;
1681 htu_result.ven = 1;
1682 htu_result.qid = OAM_RX_QUEUE;
1683 *HTU_RESULT(OAM_F4_SEG_HTU_ENTRY) = htu_result;
1684 *HTU_MASK(OAM_F4_SEG_HTU_ENTRY) = htu_mask;
1685 *HTU_ENTRY(OAM_F4_SEG_HTU_ENTRY) = htu_entry;
1686 htu_entry.vci = 0x04;
1687 htu_result.cellid = OAM_RX_QUEUE;
1688 htu_result.type = 1;
1689 htu_result.ven = 1;
1690 htu_result.qid = OAM_RX_QUEUE;
1691 *HTU_RESULT(OAM_F4_TOT_HTU_ENTRY) = htu_result;
1692 *HTU_MASK(OAM_F4_TOT_HTU_ENTRY) = htu_mask;
1693 *HTU_ENTRY(OAM_F4_TOT_HTU_ENTRY) = htu_entry;
1694 htu_entry.vci = 0x00;
1695 htu_entry.pti = 0x04;
1696 htu_mask.vci_mask = 0xFFFF;
1697 htu_mask.pti_mask = 0x01;
1698 htu_result.cellid = OAM_RX_QUEUE;
1699 htu_result.type = 1;
1700 htu_result.ven = 1;
1701 htu_result.qid = OAM_RX_QUEUE;
1702 *HTU_RESULT(OAM_F5_HTU_ENTRY) = htu_result;
1703 *HTU_MASK(OAM_F5_HTU_ENTRY) = htu_mask;
1704 *HTU_ENTRY(OAM_F5_HTU_ENTRY) = htu_entry;
1705 }
1706
1707 static inline void init_tx_tables(void)
1708 {
1709 int i;
1710 struct wtx_queue_config wtx_queue_config = {0};
1711 struct wtx_dma_channel_config wtx_dma_channel_config = {0};
1712 struct wtx_port_config wtx_port_config = {
1713 res1: 0,
1714 qid: 0,
1715 qsben: 1
1716 };
1717
1718 /*
1719 * General Registers
1720 */
1721 *CFG_WTX_DCHNUM = MAX_TX_DMA_CHANNEL_NUMBER;
1722 *WTX_DMACH_ON = ((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1) ^ ((1 << FIRST_QSB_QID) - 1);
1723 *CFG_WRDES_DELAY = write_descriptor_delay;
1724
1725 /*
1726 * WTX Port Configuration Table
1727 */
1728 for ( i = 0; i < ATM_PORT_NUMBER; i++ )
1729 *WTX_PORT_CONFIG(i) = wtx_port_config;
1730
1731 /*
1732 * WTX Queue Configuration Table
1733 */
1734 wtx_queue_config.qsben = 1;
1735 wtx_queue_config.sbid = 0;
1736 for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {
1737 wtx_queue_config.qsb_vcid = i;
1738 *WTX_QUEUE_CONFIG(i) = wtx_queue_config;
1739 }
1740
1741 /*
1742 * WTX DMA Channel Configuration Table
1743 */
1744 wtx_dma_channel_config.mode = 0;
1745 wtx_dma_channel_config.deslen = 0;
1746 wtx_dma_channel_config.desba = 0;
1747 for ( i = 0; i < FIRST_QSB_QID; i++ )
1748 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1749 /* normal connection */
1750 wtx_dma_channel_config.deslen = dma_tx_descriptor_length;
1751 for ( ; i < MAX_TX_DMA_CHANNEL_NUMBER ; i++ ) {
1752 wtx_dma_channel_config.desba = ((unsigned int)g_atm_priv_data.conn[i - FIRST_QSB_QID].tx_desc >> 2) & 0x0FFFFFFF;
1753 *WTX_DMA_CHANNEL_CONFIG(i) = wtx_dma_channel_config;
1754 }
1755 }
1756
1757 static int atm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
1758 {
1759 int i, j, port_num;
1760
1761 ASSERT(port_cell != NULL, "port_cell is NULL");
1762 ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
1763
1764 for ( j = 0; j < ATM_PORT_NUMBER && j < port_cell->port_num; j++ )
1765 if ( port_cell->tx_link_rate[j] > 0 )
1766 break;
1767 for ( i = 0; i < ATM_PORT_NUMBER && i < port_cell->port_num; i++ )
1768 g_atm_priv_data.port[i].tx_max_cell_rate =
1769 port_cell->tx_link_rate[i] > 0 ? port_cell->tx_link_rate[i] : port_cell->tx_link_rate[j];
1770
1771 qsb_global_set();
1772
1773 for ( i = 0; i < MAX_PVC_NUMBER; i++ )
1774 if ( g_atm_priv_data.conn[i].vcc != NULL )
1775 set_qsb(g_atm_priv_data.conn[i].vcc, &g_atm_priv_data.conn[i].vcc->qos, i);
1776
1777 // TODO: ReTX set xdata_addr
1778 g_xdata_addr = xdata_addr;
1779
1780 g_showtime = 1;
1781
1782 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1783 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_FOUND);
1784
1785 #if defined(CONFIG_VR9)
1786 IFX_REG_W32(0x0F, UTP_CFG);
1787 #endif
1788
1789 printk("enter showtime, cell rate: 0 - %d, 1 - %d, xdata addr: 0x%08x\n",
1790 g_atm_priv_data.port[0].tx_max_cell_rate,
1791 g_atm_priv_data.port[1].tx_max_cell_rate,
1792 (unsigned int)g_xdata_addr);
1793
1794 return 0;
1795 }
1796
1797 static int atm_showtime_exit(void)
1798 {
1799 int port_num;
1800
1801 if ( !g_showtime )
1802 return -1;
1803
1804 #if defined(CONFIG_VR9)
1805 IFX_REG_W32(0x00, UTP_CFG);
1806 #endif
1807
1808 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1809 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1810
1811 g_showtime = 0;
1812 g_xdata_addr = NULL;
1813 printk("leave showtime\n");
1814 return 0;
1815 }
1816
1817 extern struct ltq_atm_ops ar9_ops;
1818 extern struct ltq_atm_ops vr9_ops;
1819 extern struct ltq_atm_ops danube_ops;
1820 extern struct ltq_atm_ops ase_ops;
1821
1822 static const struct of_device_id ltq_atm_match[] = {
1823 #ifdef CONFIG_DANUBE
1824 { .compatible = "lantiq,ppe-danube", .data = &danube_ops },
1825 #elif defined CONFIG_AMAZON_SE
1826 { .compatible = "lantiq,ppe-ase", .data = &ase_ops },
1827 #elif defined CONFIG_AR9
1828 { .compatible = "lantiq,ppe-arx100", .data = &ar9_ops },
1829 #elif defined CONFIG_VR9
1830 { .compatible = "lantiq,ppe-xrx200", .data = &vr9_ops },
1831 #endif
1832 {},
1833 };
1834 MODULE_DEVICE_TABLE(of, ltq_atm_match);
1835
1836 static int ltq_atm_probe(struct platform_device *pdev)
1837 {
1838 const struct of_device_id *match;
1839 struct ltq_atm_ops *ops = NULL;
1840 int ret;
1841 int port_num;
1842 struct port_cell_info port_cell = {0};
1843 char ver_str[256];
1844
1845 match = of_match_device(ltq_atm_match, &pdev->dev);
1846 if (!match) {
1847 dev_err(&pdev->dev, "failed to find matching device\n");
1848 return -ENOENT;
1849 }
1850 ops = (struct ltq_atm_ops *) match->data;
1851
1852 check_parameters();
1853
1854 ret = init_priv_data();
1855 if ( ret != 0 ) {
1856 pr_err("INIT_PRIV_DATA_FAIL\n");
1857 goto INIT_PRIV_DATA_FAIL;
1858 }
1859
1860 ops->init();
1861 init_rx_tables();
1862 init_tx_tables();
1863
1864 /* create devices */
1865 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ ) {
1866 g_atm_priv_data.port[port_num].dev = atm_dev_register("ifxmips_atm", NULL, &g_ifx_atm_ops, -1, NULL);
1867 if ( !g_atm_priv_data.port[port_num].dev ) {
1868 pr_err("failed to register atm device %d!\n", port_num);
1869 ret = -EIO;
1870 goto ATM_DEV_REGISTER_FAIL;
1871 } else {
1872 g_atm_priv_data.port[port_num].dev->ci_range.vpi_bits = 8;
1873 g_atm_priv_data.port[port_num].dev->ci_range.vci_bits = 16;
1874 g_atm_priv_data.port[port_num].dev->link_rate = g_atm_priv_data.port[port_num].tx_max_cell_rate;
1875 g_atm_priv_data.port[port_num].dev->dev_data = (void*)port_num;
1876
1877 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
1878 atm_dev_signal_change(g_atm_priv_data.port[port_num].dev, ATM_PHY_SIG_LOST);
1879 #endif
1880 }
1881 }
1882
1883 /* register interrupt handler */
1884 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)
1885 ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "atm_mailbox_isr", &g_atm_priv_data);
1886 #else
1887 ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "atm_mailbox_isr", &g_atm_priv_data);
1888 #endif
1889 if ( ret ) {
1890 if ( ret == -EBUSY ) {
1891 pr_err("IRQ may be occupied by other driver, please reconfig to disable it.\n");
1892 } else {
1893 pr_err("request_irq fail irq:%d\n", PPE_MAILBOX_IGU1_INT);
1894 }
1895 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
1896 }
1897 disable_irq(PPE_MAILBOX_IGU1_INT);
1898
1899
1900 ret = ops->start(0);
1901 if ( ret ) {
1902 pr_err("ifx_pp32_start fail!\n");
1903 goto PP32_START_FAIL;
1904 }
1905
1906 port_cell.port_num = ATM_PORT_NUMBER;
1907 ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
1908 if ( g_showtime ) {
1909 atm_showtime_enter(&port_cell, &g_xdata_addr);
1910 } else {
1911 qsb_global_set();
1912 }
1913
1914 validate_oam_htu_entry();
1915
1916 ifx_mei_atm_showtime_enter = atm_showtime_enter;
1917 ifx_mei_atm_showtime_exit = atm_showtime_exit;
1918
1919 ifx_atm_version(ops, ver_str);
1920 printk(KERN_INFO "%s", ver_str);
1921 platform_set_drvdata(pdev, ops);
1922 printk("ifxmips_atm: ATM init succeed\n");
1923
1924 return 0;
1925
1926 PP32_START_FAIL:
1927 free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1928 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1929 ATM_DEV_REGISTER_FAIL:
1930 while ( port_num-- > 0 )
1931 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1932 INIT_PRIV_DATA_FAIL:
1933 clear_priv_data();
1934 printk("ifxmips_atm: ATM init failed\n");
1935 return ret;
1936 }
1937
1938 static int ltq_atm_remove(struct platform_device *pdev)
1939 {
1940 int port_num;
1941 struct ltq_atm_ops *ops = platform_get_drvdata(pdev);
1942
1943 ifx_mei_atm_showtime_enter = NULL;
1944 ifx_mei_atm_showtime_exit = NULL;
1945
1946 invalidate_oam_htu_entry();
1947
1948 ops->stop(0);
1949
1950 free_irq(PPE_MAILBOX_IGU1_INT, &g_atm_priv_data);
1951
1952 for ( port_num = 0; port_num < ATM_PORT_NUMBER; port_num++ )
1953 atm_dev_deregister(g_atm_priv_data.port[port_num].dev);
1954
1955 ops->shutdown();
1956
1957 clear_priv_data();
1958
1959 return 0;
1960 }
1961
1962 static struct platform_driver ltq_atm_driver = {
1963 .probe = ltq_atm_probe,
1964 .remove = ltq_atm_remove,
1965 .driver = {
1966 .name = "atm",
1967 .owner = THIS_MODULE,
1968 .of_match_table = ltq_atm_match,
1969 },
1970 };
1971
1972 module_platform_driver(ltq_atm_driver);
1973
1974 MODULE_LICENSE("Dual BSD/GPL");
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