4ce2e90ccdf87b43fd7b7bd01fd08fb7e7e7e564
[openwrt/openwrt.git] / package / kernel / lantiq / ltq-ptm / src / ifxmips_ptm_adsl.c
1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_ptm_adsl.c
4 ** PROJECT : UEIP
5 ** MODULES : PTM
6 **
7 ** DATE : 7 Jul 2009
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : PTM driver common source file (core functions for Danube/
10 ** Amazon-SE/AR9)
11 ** COPYRIGHT : Copyright (c) 2006
12 ** Infineon Technologies AG
13 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 **
15 ** This program is free software; you can redistribute it and/or modify
16 ** it under the terms of the GNU General Public License as published by
17 ** the Free Software Foundation; either version 2 of the License, or
18 ** (at your option) any later version.
19 **
20 ** HISTORY
21 ** $Date $Author $Comment
22 ** 07 JUL 2009 Xu Liang Init Version
23 *******************************************************************************/
24
25
26
27 /*
28 * ####################################
29 * Head File
30 * ####################################
31 */
32
33 /*
34 * Common Head File
35 */
36 #include <linux/version.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/errno.h>
41 #include <linux/proc_fs.h>
42 #include <linux/init.h>
43 #include <linux/ioctl.h>
44 #include <linux/etherdevice.h>
45 #include <linux/interrupt.h>
46 #include <linux/netdevice.h>
47 #include <asm/io.h>
48
49 /*
50 * Chip Specific Head File
51 */
52 #include "ifxmips_ptm_adsl.h"
53
54
55 #include <lantiq_soc.h>
56
57 /*
58 * ####################################
59 * Kernel Version Adaption
60 * ####################################
61 */
62 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
63 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
64 #define MODULE_PARM(a, b) module_param(a, int, 0)
65 #else
66 #define MODULE_PARM_ARRAY(a, b) MODULE_PARM(a, b)
67 #endif
68
69
70
71 /*
72 * ####################################
73 * Parameters to Configure PPE
74 * ####################################
75 */
76
77 static int write_desc_delay = 0x20; /* Write descriptor delay */
78
79 static int rx_max_packet_size = ETH_MAX_FRAME_LENGTH;
80 /* Max packet size for RX */
81
82 static int dma_rx_descriptor_length = 24; /* Number of descriptors per DMA RX channel */
83 static int dma_tx_descriptor_length = 24; /* Number of descriptors per DMA TX channel */
84
85 static int eth_efmtc_crc_cfg = 0x03100710; /* default: tx_eth_crc_check: 1, tx_tc_crc_check: 1, tx_tc_crc_len = 16 */
86 /* rx_eth_crc_present: 1, rx_eth_crc_check: 1, rx_tc_crc_check: 1, rx_tc_crc_len = 16 */
87
88 MODULE_PARM(write_desc_delay, "i");
89 MODULE_PARM_DESC(write_desc_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
90
91 MODULE_PARM(rx_max_packet_size, "i");
92 MODULE_PARM_DESC(rx_max_packet_size, "Max packet size in byte for downstream ethernet frames");
93
94 MODULE_PARM(dma_rx_descriptor_length, "i");
95 MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
96 MODULE_PARM(dma_tx_descriptor_length, "i");
97 MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
98
99 MODULE_PARM(eth_efmtc_crc_cfg, "i");
100 MODULE_PARM_DESC(eth_efmtc_crc_cfg, "Configuration for PTM TX/RX ethernet/efm-tc CRC");
101
102
103
104 /*
105 * ####################################
106 * Definition
107 * ####################################
108 */
109
110
111 #define DUMP_SKB_LEN ~0
112
113
114
115 /*
116 * ####################################
117 * Declaration
118 * ####################################
119 */
120
121 /*
122 * Network Operations
123 */
124 static void ptm_setup(struct net_device *, int);
125 static struct net_device_stats *ptm_get_stats(struct net_device *);
126 static int ptm_open(struct net_device *);
127 static int ptm_stop(struct net_device *);
128 static unsigned int ptm_poll(int, unsigned int);
129 static int ptm_napi_poll(struct napi_struct *, int);
130 static int ptm_hard_start_xmit(struct sk_buff *, struct net_device *);
131 static int ptm_change_mtu(struct net_device *, int);
132 static int ptm_ioctl(struct net_device *, struct ifreq *, int);
133 static void ptm_tx_timeout(struct net_device *);
134
135 /*
136 * DSL Data LED
137 */
138 static INLINE void adsl_led_flash(void);
139
140 /*
141 * buffer manage functions
142 */
143 static INLINE struct sk_buff* alloc_skb_rx(void);
144 //static INLINE struct sk_buff* alloc_skb_tx(unsigned int);
145 static INLINE struct sk_buff *get_skb_rx_pointer(unsigned int);
146 static INLINE int get_tx_desc(unsigned int, unsigned int *);
147
148 /*
149 * Mailbox handler and signal function
150 */
151 static INLINE int mailbox_rx_irq_handler(unsigned int);
152 static irqreturn_t mailbox_irq_handler(int, void *);
153 static INLINE void mailbox_signal(unsigned int, int);
154 #ifdef CONFIG_IFX_PTM_RX_TASKLET
155 static void do_ptm_tasklet(unsigned long);
156 #endif
157
158 /*
159 * Debug Functions
160 */
161 #if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
162 static void dump_skb(struct sk_buff *, u32, char *, int, int, int);
163 #else
164 #define dump_skb(skb, len, title, port, ch, is_tx) do {} while (0)
165 #endif
166 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
167 static void skb_swap(struct sk_buff *);
168 #else
169 #define skb_swap(skb) do {} while (0)
170 #endif
171
172 /*
173 * Proc File Functions
174 */
175 static INLINE void proc_file_create(void);
176 static INLINE void proc_file_delete(void);
177 static int proc_read_version(char *, char **, off_t, int, int *, void *);
178 static int proc_read_wanmib(char *, char **, off_t, int, int *, void *);
179 static int proc_write_wanmib(struct file *, const char *, unsigned long, void *);
180 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
181 static int proc_read_genconf(char *, char **, off_t, int, int *, void *);
182 #endif
183 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
184 static int proc_read_dbg(char *, char **, off_t, int, int *, void *);
185 static int proc_write_dbg(struct file *, const char *, unsigned long, void *);
186 #endif
187
188 /*
189 * Proc Help Functions
190 */
191 static INLINE int stricmp(const char *, const char *);
192 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
193 static INLINE int strincmp(const char *, const char *, int);
194 #endif
195 static INLINE int ifx_ptm_version(char *);
196
197 /*
198 * Init & clean-up functions
199 */
200 static INLINE void check_parameters(void);
201 static INLINE int init_priv_data(void);
202 static INLINE void clear_priv_data(void);
203 static INLINE void init_tables(void);
204
205 /*
206 * Exteranl Function
207 */
208 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
209 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
210 #else
211 static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
212 {
213 if ( is_showtime != NULL )
214 *is_showtime = 0;
215 return 0;
216 }
217 #endif
218
219 /*
220 * External variable
221 */
222 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
223 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
224 extern int (*ifx_mei_atm_showtime_exit)(void);
225 #else
226 int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
227 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
228 int (*ifx_mei_atm_showtime_exit)(void) = NULL;
229 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
230 #endif
231
232
233
234 /*
235 * ####################################
236 * Local Variable
237 * ####################################
238 */
239
240 static struct ptm_priv_data g_ptm_priv_data;
241
242 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
243 static struct net_device_ops g_ptm_netdev_ops = {
244 .ndo_get_stats = ptm_get_stats,
245 .ndo_open = ptm_open,
246 .ndo_stop = ptm_stop,
247 .ndo_start_xmit = ptm_hard_start_xmit,
248 .ndo_validate_addr = eth_validate_addr,
249 .ndo_set_mac_address = eth_mac_addr,
250 .ndo_change_mtu = ptm_change_mtu,
251 .ndo_do_ioctl = ptm_ioctl,
252 .ndo_tx_timeout = ptm_tx_timeout,
253 };
254 #endif
255
256 static struct net_device *g_net_dev[2] = {0};
257 static char *g_net_dev_name[2] = {"ptm0", "ptmfast0"};
258
259 #ifdef CONFIG_IFX_PTM_RX_TASKLET
260 static struct tasklet_struct g_ptm_tasklet[] = {
261 {NULL, 0, ATOMIC_INIT(0), do_ptm_tasklet, 0},
262 {NULL, 0, ATOMIC_INIT(0), do_ptm_tasklet, 1},
263 };
264 #endif
265
266 unsigned int ifx_ptm_dbg_enable = DBG_ENABLE_MASK_ERR;
267
268 static struct proc_dir_entry* g_ptm_dir = NULL;
269
270 static int g_showtime = 0;
271
272
273
274 /*
275 * ####################################
276 * Local Function
277 * ####################################
278 */
279
280 static void ptm_setup(struct net_device *dev, int ndev)
281 {
282 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
283 netif_carrier_off(dev);
284 #endif
285
286 /* hook network operations */
287 dev->netdev_ops = &g_ptm_netdev_ops;
288 netif_napi_add(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 25);
289 dev->watchdog_timeo = ETH_WATCHDOG_TIMEOUT;
290
291 dev->dev_addr[0] = 0x00;
292 dev->dev_addr[1] = 0x20;
293 dev->dev_addr[2] = 0xda;
294 dev->dev_addr[3] = 0x86;
295 dev->dev_addr[4] = 0x23;
296 dev->dev_addr[5] = 0x75 + ndev;
297 }
298
299 static struct net_device_stats *ptm_get_stats(struct net_device *dev)
300 {
301 int ndev;
302
303 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
304 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
305
306 g_ptm_priv_data.itf[ndev].stats.rx_errors = WAN_MIB_TABLE[ndev].wrx_tccrc_err_pdu + WAN_MIB_TABLE[ndev].wrx_ethcrc_err_pdu;
307 g_ptm_priv_data.itf[ndev].stats.rx_dropped = WAN_MIB_TABLE[ndev].wrx_nodesc_drop_pdu + WAN_MIB_TABLE[ndev].wrx_len_violation_drop_pdu + (WAN_MIB_TABLE[ndev].wrx_correct_pdu - g_ptm_priv_data.itf[ndev].stats.rx_packets);
308
309 return &g_ptm_priv_data.itf[ndev].stats;
310 }
311
312 static int ptm_open(struct net_device *dev)
313 {
314 int ndev;
315
316 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
317 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
318
319 napi_enable(&g_ptm_priv_data.itf[ndev].napi);
320
321 IFX_REG_W32_MASK(0, 1 << ndev, MBOX_IGU1_IER);
322
323 netif_start_queue(dev);
324
325 return 0;
326 }
327
328 static int ptm_stop(struct net_device *dev)
329 {
330 int ndev;
331
332 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
333 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
334
335 IFX_REG_W32_MASK((1 << ndev) | (1 << (ndev + 16)), 0, MBOX_IGU1_IER);
336
337 napi_disable(&g_ptm_priv_data.itf[ndev].napi);
338
339 netif_stop_queue(dev);
340
341 return 0;
342 }
343
344 static unsigned int ptm_poll(int ndev, unsigned int work_to_do)
345 {
346 unsigned int work_done = 0;
347
348 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
349
350 while ( work_done < work_to_do && WRX_DMA_CHANNEL_CONFIG(ndev)->vlddes > 0 ) {
351 if ( mailbox_rx_irq_handler(ndev) < 0 )
352 break;
353
354 work_done++;
355 }
356
357 return work_done;
358 }
359 static int ptm_napi_poll(struct napi_struct *napi, int budget)
360 {
361 int ndev;
362 unsigned int work_done;
363
364 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != napi->dev; ndev++ );
365
366 work_done = ptm_poll(ndev, budget);
367
368 // interface down
369 if ( !netif_running(napi->dev) ) {
370 napi_complete(napi);
371 return work_done;
372 }
373
374 // no more traffic
375 if ( WRX_DMA_CHANNEL_CONFIG(ndev)->vlddes == 0 ) {
376 // clear interrupt
377 IFX_REG_W32_MASK(0, 1 << ndev, MBOX_IGU1_ISRC);
378 // double check
379 if ( WRX_DMA_CHANNEL_CONFIG(ndev)->vlddes == 0 ) {
380 napi_complete(napi);
381 IFX_REG_W32_MASK(0, 1 << ndev, MBOX_IGU1_IER);
382 return work_done;
383 }
384 }
385
386 // next round
387 return work_done;
388 }
389
390 static int ptm_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
391 {
392 int ndev;
393 unsigned int f_full;
394 int desc_base;
395 register struct tx_descriptor reg_desc = {0};
396
397 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
398 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
399
400 if ( !g_showtime ) {
401 err("not in showtime");
402 goto PTM_HARD_START_XMIT_FAIL;
403 }
404
405 /* allocate descriptor */
406 desc_base = get_tx_desc(ndev, &f_full);
407 if ( f_full ) {
408 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
409 netif_trans_update(dev);
410 #else
411 dev->trans_start = jiffies;
412 #endif
413 netif_stop_queue(dev);
414
415 IFX_REG_W32_MASK(0, 1 << (ndev + 16), MBOX_IGU1_ISRC);
416 IFX_REG_W32_MASK(0, 1 << (ndev + 16), MBOX_IGU1_IER);
417 }
418 if ( desc_base < 0 )
419 goto PTM_HARD_START_XMIT_FAIL;
420
421 if ( g_ptm_priv_data.itf[ndev].tx_skb[desc_base] != NULL )
422 dev_kfree_skb_any(g_ptm_priv_data.itf[ndev].tx_skb[desc_base]);
423 g_ptm_priv_data.itf[ndev].tx_skb[desc_base] = skb;
424
425 reg_desc.dataptr = (unsigned int)skb->data >> 2;
426 reg_desc.datalen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
427 reg_desc.byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
428 reg_desc.own = 1;
429 reg_desc.c = 1;
430 reg_desc.sop = reg_desc.eop = 1;
431
432 /* write discriptor to memory and write back cache */
433 g_ptm_priv_data.itf[ndev].tx_desc[desc_base] = reg_desc;
434 dma_cache_wback((unsigned long)skb->data, skb->len);
435 wmb();
436
437 dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, ndev, ndev, 1);
438
439 if ( (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_MAC_SWAP) ) {
440 skb_swap(skb);
441 }
442
443 g_ptm_priv_data.itf[ndev].stats.tx_packets++;
444 g_ptm_priv_data.itf[ndev].stats.tx_bytes += reg_desc.datalen;
445
446 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,7,0)
447 netif_trans_update(dev);
448 #else
449 dev->trans_start = jiffies;
450 #endif
451 mailbox_signal(ndev, 1);
452
453 adsl_led_flash();
454
455 return NETDEV_TX_OK;
456
457 PTM_HARD_START_XMIT_FAIL:
458 dev_kfree_skb_any(skb);
459 g_ptm_priv_data.itf[ndev].stats.tx_dropped++;
460 return NETDEV_TX_OK;
461 }
462
463 static int ptm_change_mtu(struct net_device *dev, int mtu)
464 {
465 /* Allow up to 1508 bytes, for RFC4638 */
466 if (mtu < 68 || mtu > ETH_DATA_LEN + 8)
467 return -EINVAL;
468 dev->mtu = mtu;
469 return 0;
470 }
471
472 static int ptm_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
473 {
474 int ndev;
475
476 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
477 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
478
479 switch ( cmd )
480 {
481 case IFX_PTM_MIB_CW_GET:
482 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxNoIdleCodewords = WAN_MIB_TABLE[ndev].wrx_nonidle_cw;
483 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxIdleCodewords = WAN_MIB_TABLE[ndev].wrx_idle_cw;
484 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxCodingViolation = WAN_MIB_TABLE[ndev].wrx_err_cw;
485 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxNoIdleCodewords = 0;
486 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxIdleCodewords = 0;
487 break;
488 case IFX_PTM_MIB_FRAME_GET:
489 ((PTM_FRAME_MIB_T *)ifr->ifr_data)->RxCorrect = WAN_MIB_TABLE[ndev].wrx_correct_pdu;
490 ((PTM_FRAME_MIB_T *)ifr->ifr_data)->TC_CrcError = WAN_MIB_TABLE[ndev].wrx_tccrc_err_pdu;
491 ((PTM_FRAME_MIB_T *)ifr->ifr_data)->RxDropped = WAN_MIB_TABLE[ndev].wrx_nodesc_drop_pdu + WAN_MIB_TABLE[ndev].wrx_len_violation_drop_pdu;
492 ((PTM_FRAME_MIB_T *)ifr->ifr_data)->TxSend = WAN_MIB_TABLE[ndev].wtx_total_pdu;
493 break;
494 case IFX_PTM_CFG_GET:
495 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcPresent = CFG_ETH_EFMTC_CRC->rx_eth_crc_present;
496 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck = CFG_ETH_EFMTC_CRC->rx_eth_crc_check;
497 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck = CFG_ETH_EFMTC_CRC->rx_tc_crc_check;
498 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen = CFG_ETH_EFMTC_CRC->rx_tc_crc_len;
499 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen = CFG_ETH_EFMTC_CRC->tx_eth_crc_gen;
500 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen = CFG_ETH_EFMTC_CRC->tx_tc_crc_gen;
501 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen = CFG_ETH_EFMTC_CRC->tx_tc_crc_len;
502 break;
503 case IFX_PTM_CFG_SET:
504 CFG_ETH_EFMTC_CRC->rx_eth_crc_present = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcPresent ? 1 : 0;
505 CFG_ETH_EFMTC_CRC->rx_eth_crc_check = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck ? 1 : 0;
506 if ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck && (((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen == 16 || ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen == 32) )
507 {
508 CFG_ETH_EFMTC_CRC->rx_tc_crc_check = 1;
509 CFG_ETH_EFMTC_CRC->rx_tc_crc_len = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen;
510 }
511 else
512 {
513 CFG_ETH_EFMTC_CRC->rx_tc_crc_check = 0;
514 CFG_ETH_EFMTC_CRC->rx_tc_crc_len = 0;
515 }
516 CFG_ETH_EFMTC_CRC->tx_eth_crc_gen = ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen ? 1 : 0;
517 if ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen && (((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen == 16 || ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen == 32) )
518 {
519 CFG_ETH_EFMTC_CRC->tx_tc_crc_gen = 1;
520 CFG_ETH_EFMTC_CRC->tx_tc_crc_len = ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen;
521 }
522 else
523 {
524 CFG_ETH_EFMTC_CRC->tx_tc_crc_gen = 0;
525 CFG_ETH_EFMTC_CRC->tx_tc_crc_len = 0;
526 }
527 break;
528 default:
529 return -EOPNOTSUPP;
530 }
531
532 return 0;
533 }
534
535 static void ptm_tx_timeout(struct net_device *dev)
536 {
537 int ndev;
538
539 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
540 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
541
542 /* disable TX irq, release skb when sending new packet */
543 IFX_REG_W32_MASK(1 << (ndev + 16), 0, MBOX_IGU1_IER);
544
545 /* wake up TX queue */
546 netif_wake_queue(dev);
547
548 return;
549 }
550
551 static INLINE void adsl_led_flash(void)
552 {
553 }
554
555 static INLINE struct sk_buff* alloc_skb_rx(void)
556 {
557 struct sk_buff *skb;
558
559 /* allocate memroy including trailer and padding */
560 skb = dev_alloc_skb(rx_max_packet_size + RX_HEAD_MAC_ADDR_ALIGNMENT + DATA_BUFFER_ALIGNMENT);
561 if ( skb != NULL ) {
562 /* must be burst length alignment and reserve two more bytes for MAC address alignment */
563 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
564 skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
565 /* pub skb in reserved area "skb->data - 4" */
566 *((struct sk_buff **)skb->data - 1) = skb;
567 wmb();
568 /* write back and invalidate cache */
569 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
570 /* invalidate cache */
571 dma_cache_inv((unsigned long)skb->data, (unsigned int)skb->end - (unsigned int)skb->data);
572 }
573
574 return skb;
575 }
576
577 #if 0
578 static INLINE struct sk_buff* alloc_skb_tx(unsigned int size)
579 {
580 struct sk_buff *skb;
581
582 /* allocate memory including padding */
583 size = (size + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1);
584 skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
585 /* must be burst length alignment */
586 if ( skb != NULL )
587 skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
588 return skb;
589 }
590 #endif
591
592 static INLINE struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
593 {
594 unsigned int skb_dataptr;
595 struct sk_buff *skb;
596
597 skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
598 skb = *(struct sk_buff **)skb_dataptr;
599
600 ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
601 ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
602
603 return skb;
604 }
605
606 static INLINE int get_tx_desc(unsigned int itf, unsigned int *f_full)
607 {
608 int desc_base = -1;
609 struct ptm_itf *p_itf = &g_ptm_priv_data.itf[itf];
610
611 // assume TX is serial operation
612 // no protection provided
613
614 *f_full = 1;
615
616 if ( p_itf->tx_desc[p_itf->tx_desc_pos].own == 0 ) {
617 desc_base = p_itf->tx_desc_pos;
618 if ( ++(p_itf->tx_desc_pos) == dma_tx_descriptor_length )
619 p_itf->tx_desc_pos = 0;
620 if ( p_itf->tx_desc[p_itf->tx_desc_pos].own == 0 )
621 *f_full = 0;
622 }
623
624 return desc_base;
625 }
626
627 static INLINE int mailbox_rx_irq_handler(unsigned int ch) // return: < 0 - descriptor not available, 0 - received one packet
628 {
629 unsigned int ndev = ch;
630 struct sk_buff *skb;
631 struct sk_buff *new_skb;
632 volatile struct rx_descriptor *desc;
633 struct rx_descriptor reg_desc;
634 int netif_rx_ret;
635
636 desc = &g_ptm_priv_data.itf[ndev].rx_desc[g_ptm_priv_data.itf[ndev].rx_desc_pos];
637 if ( desc->own || !desc->c ) // if PP32 hold descriptor or descriptor not completed
638 return -EAGAIN;
639 if ( ++g_ptm_priv_data.itf[ndev].rx_desc_pos == dma_rx_descriptor_length )
640 g_ptm_priv_data.itf[ndev].rx_desc_pos = 0;
641
642 reg_desc = *desc;
643 skb = get_skb_rx_pointer(reg_desc.dataptr);
644
645 if ( !reg_desc.err ) {
646 new_skb = alloc_skb_rx();
647 if ( new_skb != NULL ) {
648 skb_reserve(skb, reg_desc.byteoff);
649 skb_put(skb, reg_desc.datalen);
650
651 dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, ndev, ndev, 0);
652
653 // parse protocol header
654 skb->dev = g_net_dev[ndev];
655 skb->protocol = eth_type_trans(skb, skb->dev);
656
657 g_net_dev[ndev]->last_rx = jiffies;
658
659 netif_rx_ret = netif_receive_skb(skb);
660
661 if ( netif_rx_ret != NET_RX_DROP ) {
662 g_ptm_priv_data.itf[ndev].stats.rx_packets++;
663 g_ptm_priv_data.itf[ndev].stats.rx_bytes += reg_desc.datalen;
664 }
665
666 reg_desc.dataptr = ((unsigned int)new_skb->data >> 2) & 0x0FFFFFFF;
667 reg_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;
668 }
669 }
670 else
671 reg_desc.err = 0;
672
673 reg_desc.datalen = rx_max_packet_size;
674 reg_desc.own = 1;
675 reg_desc.c = 0;
676
677 // update descriptor
678 *desc = reg_desc;
679 wmb();
680
681 mailbox_signal(ndev, 0);
682
683 adsl_led_flash();
684
685 return 0;
686 }
687
688 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
689 {
690 unsigned int isr;
691 int i;
692
693 isr = IFX_REG_R32(MBOX_IGU1_ISR);
694 IFX_REG_W32(isr, MBOX_IGU1_ISRC);
695 isr &= IFX_REG_R32(MBOX_IGU1_IER);
696
697 while ( (i = __fls(isr)) >= 0 ) {
698 isr ^= 1 << i;
699
700 if ( i >= 16 ) {
701 // TX
702 IFX_REG_W32_MASK(1 << i, 0, MBOX_IGU1_IER);
703 i -= 16;
704 if ( i < MAX_ITF_NUMBER )
705 netif_wake_queue(g_net_dev[i]);
706 }
707 else {
708 // RX
709 #ifdef CONFIG_IFX_PTM_RX_INTERRUPT
710 while ( WRX_DMA_CHANNEL_CONFIG(i)->vlddes > 0 )
711 mailbox_rx_irq_handler(i);
712 #else
713 IFX_REG_W32_MASK(1 << i, 0, MBOX_IGU1_IER);
714 napi_schedule(&g_ptm_priv_data.itf[i].napi);
715 #endif
716 }
717 }
718
719 return IRQ_HANDLED;
720 }
721
722 static INLINE void mailbox_signal(unsigned int itf, int is_tx)
723 {
724 int count = 1000;
725
726 if ( is_tx ) {
727 while ( MBOX_IGU3_ISR_ISR(itf + 16) && count > 0 )
728 count--;
729 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf + 16), MBOX_IGU3_ISRS);
730 }
731 else {
732 while ( MBOX_IGU3_ISR_ISR(itf) && count > 0 )
733 count--;
734 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf), MBOX_IGU3_ISRS);
735 }
736
737 ASSERT(count != 0, "MBOX_IGU3_ISR = 0x%08x", IFX_REG_R32(MBOX_IGU3_ISR));
738 }
739
740 #ifdef CONFIG_IFX_PTM_RX_TASKLET
741 static void do_ptm_tasklet(unsigned long arg)
742 {
743 unsigned int work_to_do = 25;
744 unsigned int work_done = 0;
745
746 ASSERT(arg >= 0 && arg < ARRAY_SIZE(g_net_dev), "arg = %lu (wrong value)", arg);
747
748 while ( work_done < work_to_do && WRX_DMA_CHANNEL_CONFIG(arg)->vlddes > 0 ) {
749 if ( mailbox_rx_irq_handler(arg) < 0 )
750 break;
751
752 work_done++;
753 }
754
755 // interface down
756 if ( !netif_running(g_net_dev[arg]) )
757 return;
758
759 // no more traffic
760 if ( WRX_DMA_CHANNEL_CONFIG(arg)->vlddes == 0 ) {
761 // clear interrupt
762 IFX_REG_W32_MASK(0, 1 << arg, MBOX_IGU1_ISRC);
763 // double check
764 if ( WRX_DMA_CHANNEL_CONFIG(arg)->vlddes == 0 ) {
765 IFX_REG_W32_MASK(0, 1 << arg, MBOX_IGU1_IER);
766 return;
767 }
768 }
769
770 // next round
771 tasklet_schedule(&g_ptm_tasklet[arg]);
772 }
773 #endif
774
775 #if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
776 static void dump_skb(struct sk_buff *skb, u32 len, char *title, int port, int ch, int is_tx)
777 {
778 int i;
779
780 if ( !(ifx_ptm_dbg_enable & (is_tx ? DBG_ENABLE_MASK_DUMP_SKB_TX : DBG_ENABLE_MASK_DUMP_SKB_RX)) )
781 return;
782
783 if ( skb->len < len )
784 len = skb->len;
785
786 if ( len > rx_max_packet_size ) {
787 printk("too big data length: skb = %08x, skb->data = %08x, skb->len = %d\n", (u32)skb, (u32)skb->data, skb->len);
788 return;
789 }
790
791 if ( ch >= 0 )
792 printk("%s (port %d, ch %d)\n", title, port, ch);
793 else
794 printk("%s\n", title);
795 printk(" skb->data = %08X, skb->tail = %08X, skb->len = %d\n", (u32)skb->data, (u32)skb->tail, (int)skb->len);
796 for ( i = 1; i <= len; i++ ) {
797 if ( i % 16 == 1 )
798 printk(" %4d:", i - 1);
799 printk(" %02X", (int)(*((char*)skb->data + i - 1) & 0xFF));
800 if ( i % 16 == 0 )
801 printk("\n");
802 }
803 if ( (i - 1) % 16 != 0 )
804 printk("\n");
805 }
806 #endif
807
808 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
809 static void skb_swap(struct sk_buff *skb)
810 {
811 unsigned char tmp[8];
812 unsigned char *p = skb->data;
813
814 if ( !(p[0] & 0x01) ) { // bypass broadcast/multicast
815 // swap MAC
816 memcpy(tmp, p, 6);
817 memcpy(p, p + 6, 6);
818 memcpy(p + 6, tmp, 6);
819 p += 12;
820
821 // bypass VLAN
822 while ( p[0] == 0x81 && p[1] == 0x00 )
823 p += 4;
824
825 // IP
826 if ( p[0] == 0x08 && p[1] == 0x00 ) {
827 p += 14;
828 memcpy(tmp, p, 4);
829 memcpy(p, p + 4, 4);
830 memcpy(p + 4, tmp, 4);
831 p += 8;
832 }
833
834 dma_cache_wback((unsigned long)skb->data, (unsigned long)p - (unsigned long)skb->data);
835 }
836 }
837 #endif
838
839 static INLINE void proc_file_create(void)
840 {
841 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
842 struct proc_dir_entry *res;
843
844 g_ptm_dir = proc_mkdir("driver/ifx_ptm", NULL);
845
846 create_proc_read_entry("version",
847 0,
848 g_ptm_dir,
849 proc_read_version,
850 NULL);
851
852 res = create_proc_entry("wanmib",
853 0,
854 g_ptm_dir);
855 if ( res != NULL ) {
856 res->read_proc = proc_read_wanmib;
857 res->write_proc = proc_write_wanmib;
858 }
859
860 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
861 create_proc_read_entry("genconf",
862 0,
863 g_ptm_dir,
864 proc_read_genconf,
865 NULL);
866
867 #ifdef CONFIG_AR9
868 create_proc_read_entry("regs",
869 0,
870 g_ptm_dir,
871 ifx_ptm_proc_read_regs,
872 NULL);
873 #endif
874 #endif
875
876 res = create_proc_entry("dbg",
877 0,
878 g_ptm_dir);
879 if ( res != NULL ) {
880 res->read_proc = proc_read_dbg;
881 res->write_proc = proc_write_dbg;
882 }
883 #endif
884 }
885
886 static INLINE void proc_file_delete(void)
887 {
888 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
889 remove_proc_entry("dbg", g_ptm_dir);
890 #endif
891
892 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
893 #ifdef CONFIG_AR9
894 remove_proc_entry("regs", g_ptm_dir);
895 #endif
896
897 remove_proc_entry("genconf", g_ptm_dir);
898 #endif
899
900 remove_proc_entry("wanmib", g_ptm_dir);
901
902 remove_proc_entry("version", g_ptm_dir);
903
904 remove_proc_entry("driver/ifx_ptm", NULL);
905 }
906
907 static int proc_read_version(char *buf, char **start, off_t offset, int count, int *eof, void *data)
908 {
909 int len = 0;
910
911 len += ifx_ptm_version(buf + len);
912
913 if ( offset >= len ) {
914 *start = buf;
915 *eof = 1;
916 return 0;
917 }
918 *start = buf + offset;
919 if ( (len -= offset) > count )
920 return count;
921 *eof = 1;
922 return len;
923 }
924
925 static int proc_read_wanmib(char *page, char **start, off_t off, int count, int *eof, void *data)
926 {
927 int len = 0;
928 int i;
929 char *title[] = {
930 "ptm0\n",
931 "ptmfast0\n"
932 };
933
934 for ( i = 0; i < ARRAY_SIZE(title); i++ ) {
935 len += sprintf(page + off + len, title[i]);
936 len += sprintf(page + off + len, " wrx_correct_pdu = %d\n", WAN_MIB_TABLE[i].wrx_correct_pdu);
937 len += sprintf(page + off + len, " wrx_correct_pdu_bytes = %d\n", WAN_MIB_TABLE[i].wrx_correct_pdu_bytes);
938 len += sprintf(page + off + len, " wrx_tccrc_err_pdu = %d\n", WAN_MIB_TABLE[i].wrx_tccrc_err_pdu);
939 len += sprintf(page + off + len, " wrx_tccrc_err_pdu_bytes = %d\n", WAN_MIB_TABLE[i].wrx_tccrc_err_pdu_bytes);
940 len += sprintf(page + off + len, " wrx_ethcrc_err_pdu = %d\n", WAN_MIB_TABLE[i].wrx_ethcrc_err_pdu);
941 len += sprintf(page + off + len, " wrx_ethcrc_err_pdu_bytes = %d\n", WAN_MIB_TABLE[i].wrx_ethcrc_err_pdu_bytes);
942 len += sprintf(page + off + len, " wrx_nodesc_drop_pdu = %d\n", WAN_MIB_TABLE[i].wrx_nodesc_drop_pdu);
943 len += sprintf(page + off + len, " wrx_len_violation_drop_pdu = %d\n", WAN_MIB_TABLE[i].wrx_len_violation_drop_pdu);
944 len += sprintf(page + off + len, " wrx_idle_bytes = %d\n", WAN_MIB_TABLE[i].wrx_idle_bytes);
945 len += sprintf(page + off + len, " wrx_nonidle_cw = %d\n", WAN_MIB_TABLE[i].wrx_nonidle_cw);
946 len += sprintf(page + off + len, " wrx_idle_cw = %d\n", WAN_MIB_TABLE[i].wrx_idle_cw);
947 len += sprintf(page + off + len, " wrx_err_cw = %d\n", WAN_MIB_TABLE[i].wrx_err_cw);
948 len += sprintf(page + off + len, " wtx_total_pdu = %d\n", WAN_MIB_TABLE[i].wtx_total_pdu);
949 len += sprintf(page + off + len, " wtx_total_bytes = %d\n", WAN_MIB_TABLE[i].wtx_total_bytes);
950 }
951
952 *eof = 1;
953
954 return len;
955 }
956
957 static int proc_write_wanmib(struct file *file, const char *buf, unsigned long count, void *data)
958 {
959 char str[2048];
960 char *p;
961 int len, rlen;
962
963 int i;
964
965 len = count < sizeof(str) ? count : sizeof(str) - 1;
966 rlen = len - copy_from_user(str, buf, len);
967 while ( rlen && str[rlen - 1] <= ' ' )
968 rlen--;
969 str[rlen] = 0;
970 for ( p = str; *p && *p <= ' '; p++, rlen-- );
971 if ( !*p )
972 return count;
973
974 if ( stricmp(p, "clear") == 0 || stricmp(p, "clean") == 0 ) {
975 for ( i = 0; i < 2; i++ )
976 memset((void*)&WAN_MIB_TABLE[i], 0, sizeof(WAN_MIB_TABLE[i]));
977 }
978
979 return count;
980 }
981
982 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
983
984 static int proc_read_genconf(char *page, char **start, off_t off, int count, int *eof, void *data)
985 {
986 int len = 0;
987 int len_max = off + count;
988 char *pstr;
989 char str[2048];
990 int llen = 0;
991 int i;
992 unsigned long bit;
993
994 pstr = *start = page;
995
996 __sync();
997
998 llen += sprintf(str + llen, "CFG_WAN_WRDES_DELAY (0x%08X): %d\n", (unsigned int)CFG_WAN_WRDES_DELAY, IFX_REG_R32(CFG_WAN_WRDES_DELAY));
999 llen += sprintf(str + llen, "CFG_WRX_DMACH_ON (0x%08X):", (unsigned int)CFG_WRX_DMACH_ON);
1000 for ( i = 0, bit = 1; i < MAX_RX_DMA_CHANNEL_NUMBER; i++, bit <<= 1 )
1001 llen += sprintf(str + llen, " %d - %s", i, (IFX_REG_R32(CFG_WRX_DMACH_ON) & bit) ? "on " : "off");
1002 llen += sprintf(str + llen, "\n");
1003 llen += sprintf(str + llen, "CFG_WTX_DMACH_ON (0x%08X):", (unsigned int)CFG_WTX_DMACH_ON);
1004 for ( i = 0, bit = 1; i < MAX_TX_DMA_CHANNEL_NUMBER; i++, bit <<= 1 )
1005 llen += sprintf(str + llen, " %d - %s", i, (IFX_REG_R32(CFG_WTX_DMACH_ON) & bit) ? "on " : "off");
1006 llen += sprintf(str + llen, "\n");
1007 llen += sprintf(str + llen, "CFG_WRX_LOOK_BITTH (0x%08X): %d\n", (unsigned int)CFG_WRX_LOOK_BITTH, IFX_REG_R32(CFG_WRX_LOOK_BITTH));
1008 llen += sprintf(str + llen, "CFG_ETH_EFMTC_CRC (0x%08X): rx_tc_crc_len - %2d, rx_tc_crc_check - %s\n", (unsigned int)CFG_ETH_EFMTC_CRC, CFG_ETH_EFMTC_CRC->rx_tc_crc_len, CFG_ETH_EFMTC_CRC->rx_tc_crc_check ? " on" : "off");
1009 llen += sprintf(str + llen, " rx_eth_crc_check - %s, rx_eth_crc_present - %s\n", CFG_ETH_EFMTC_CRC->rx_eth_crc_check ? " on" : "off", CFG_ETH_EFMTC_CRC->rx_eth_crc_present ? " on" : "off");
1010 llen += sprintf(str + llen, " tx_tc_crc_len - %2d, tx_tc_crc_gen - %s\n", CFG_ETH_EFMTC_CRC->tx_tc_crc_len, CFG_ETH_EFMTC_CRC->tx_tc_crc_gen ? " on" : "off");
1011 llen += sprintf(str + llen, " tx_eth_crc_gen - %s\n", CFG_ETH_EFMTC_CRC->tx_eth_crc_gen ? " on" : "off");
1012
1013 llen += sprintf(str + llen, "RX Port:\n");
1014 for ( i = 0; i < MAX_RX_DMA_CHANNEL_NUMBER; i++ )
1015 llen += sprintf(str + llen, " %d (0x%08X). mfs - %5d, dmach - %d, local_state - %d, partner_state - %d\n", i, (unsigned int)WRX_PORT_CONFIG(i), WRX_PORT_CONFIG(i)->mfs, WRX_PORT_CONFIG(i)->dmach, WRX_PORT_CONFIG(i)->local_state, WRX_PORT_CONFIG(i)->partner_state);
1016 llen += sprintf(str + llen, "RX DMA Channel:\n");
1017 for ( i = 0; i < MAX_RX_DMA_CHANNEL_NUMBER; i++ )
1018 llen += sprintf(str + llen, " %d (0x%08X). desba - 0x%08X (0x%08X), deslen - %d, vlddes - %d\n", i, (unsigned int)WRX_DMA_CHANNEL_CONFIG(i), WRX_DMA_CHANNEL_CONFIG(i)->desba, ((unsigned int)WRX_DMA_CHANNEL_CONFIG(i)->desba << 2) | KSEG1, WRX_DMA_CHANNEL_CONFIG(i)->deslen, WRX_DMA_CHANNEL_CONFIG(i)->vlddes);
1019
1020 llen += sprintf(str + llen, "TX Port:\n");
1021 for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ )
1022 llen += sprintf(str + llen, " %d (0x%08X). tx_cwth2 - %d, tx_cwth1 - %d\n", i, (unsigned int)WTX_PORT_CONFIG(i), WTX_PORT_CONFIG(i)->tx_cwth2, WTX_PORT_CONFIG(i)->tx_cwth1);
1023 llen += sprintf(str + llen, "TX DMA Channel:\n");
1024 for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ )
1025 llen += sprintf(str + llen, " %d (0x%08X). desba - 0x%08X (0x%08X), deslen - %d, vlddes - %d\n", i, (unsigned int)WTX_DMA_CHANNEL_CONFIG(i), WTX_DMA_CHANNEL_CONFIG(i)->desba, ((unsigned int)WTX_DMA_CHANNEL_CONFIG(i)->desba << 2) | KSEG1, WTX_DMA_CHANNEL_CONFIG(i)->deslen, WTX_DMA_CHANNEL_CONFIG(i)->vlddes);
1026
1027 if ( len <= off && len + llen > off )
1028 {
1029 memcpy(pstr, str + off - len, len + llen - off);
1030 pstr += len + llen - off;
1031 }
1032 else if ( len > off )
1033 {
1034 memcpy(pstr, str, llen);
1035 pstr += llen;
1036 }
1037 len += llen;
1038 if ( len >= len_max )
1039 goto PROC_READ_GENCONF_OVERRUN_END;
1040
1041 *eof = 1;
1042
1043 return len - off;
1044
1045 PROC_READ_GENCONF_OVERRUN_END:
1046 return len - llen - off;
1047 }
1048
1049 #endif // defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
1050
1051 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1052
1053 static int proc_read_dbg(char *page, char **start, off_t off, int count, int *eof, void *data)
1054 {
1055 int len = 0;
1056
1057 len += sprintf(page + off + len, "error print - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_ERR) ? "enabled" : "disabled");
1058 len += sprintf(page + off + len, "debug print - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ? "enabled" : "disabled");
1059 len += sprintf(page + off + len, "assert - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_ASSERT) ? "enabled" : "disabled");
1060 len += sprintf(page + off + len, "dump rx skb - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_RX) ? "enabled" : "disabled");
1061 len += sprintf(page + off + len, "dump tx skb - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_TX) ? "enabled" : "disabled");
1062 len += sprintf(page + off + len, "mac swap - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_MAC_SWAP) ? "enabled" : "disabled");
1063
1064 *eof = 1;
1065
1066 return len;
1067 }
1068
1069 static int proc_write_dbg(struct file *file, const char *buf, unsigned long count, void *data)
1070 {
1071 static const char *dbg_enable_mask_str[] = {
1072 " error print",
1073 " err",
1074 " debug print",
1075 " dbg",
1076 " assert",
1077 " assert",
1078 " dump rx skb",
1079 " rx",
1080 " dump tx skb",
1081 " tx",
1082 " dump init",
1083 " init",
1084 " dump qos",
1085 " qos",
1086 " mac swap",
1087 " swap",
1088 " all"
1089 };
1090 static const int dbg_enable_mask_str_len[] = {
1091 12, 4,
1092 12, 4,
1093 7, 7,
1094 12, 3,
1095 12, 3,
1096 10, 5,
1097 9, 4,
1098 9, 5,
1099 4
1100 };
1101 unsigned int dbg_enable_mask[] = {
1102 DBG_ENABLE_MASK_ERR,
1103 DBG_ENABLE_MASK_DEBUG_PRINT,
1104 DBG_ENABLE_MASK_ASSERT,
1105 DBG_ENABLE_MASK_DUMP_SKB_RX,
1106 DBG_ENABLE_MASK_DUMP_SKB_TX,
1107 DBG_ENABLE_MASK_DUMP_INIT,
1108 DBG_ENABLE_MASK_DUMP_QOS,
1109 DBG_ENABLE_MASK_MAC_SWAP,
1110 DBG_ENABLE_MASK_ALL
1111 };
1112
1113 char str[2048];
1114 char *p;
1115
1116 int len, rlen;
1117
1118 int f_enable = 0;
1119 int i;
1120
1121 len = count < sizeof(str) ? count : sizeof(str) - 1;
1122 rlen = len - copy_from_user(str, buf, len);
1123 while ( rlen && str[rlen - 1] <= ' ' )
1124 rlen--;
1125 str[rlen] = 0;
1126 for ( p = str; *p && *p <= ' '; p++, rlen-- );
1127 if ( !*p )
1128 return 0;
1129
1130 // debugging feature for enter/leave showtime
1131 if ( strincmp(p, "enter", 5) == 0 && ifx_mei_atm_showtime_enter != NULL )
1132 ifx_mei_atm_showtime_enter(NULL, NULL);
1133 else if ( strincmp(p, "leave", 5) == 0 && ifx_mei_atm_showtime_exit != NULL )
1134 ifx_mei_atm_showtime_exit();
1135
1136 if ( strincmp(p, "enable", 6) == 0 ) {
1137 p += 6;
1138 f_enable = 1;
1139 }
1140 else if ( strincmp(p, "disable", 7) == 0 ) {
1141 p += 7;
1142 f_enable = -1;
1143 }
1144 else if ( strincmp(p, "help", 4) == 0 || *p == '?' ) {
1145 printk("echo <enable/disable> [err/dbg/assert/rx/tx/init/qos/swap/all] > /proc/driver/ifx_ptm/dbg\n");
1146 }
1147
1148 if ( f_enable ) {
1149 if ( *p == 0 ) {
1150 if ( f_enable > 0 )
1151 ifx_ptm_dbg_enable |= DBG_ENABLE_MASK_ALL & ~DBG_ENABLE_MASK_MAC_SWAP;
1152 else
1153 ifx_ptm_dbg_enable &= ~DBG_ENABLE_MASK_ALL | DBG_ENABLE_MASK_MAC_SWAP;
1154 }
1155 else {
1156 do {
1157 for ( i = 0; i < ARRAY_SIZE(dbg_enable_mask_str); i++ )
1158 if ( strincmp(p, dbg_enable_mask_str[i], dbg_enable_mask_str_len[i]) == 0 ) {
1159 if ( f_enable > 0 )
1160 ifx_ptm_dbg_enable |= dbg_enable_mask[i >> 1];
1161 else
1162 ifx_ptm_dbg_enable &= ~dbg_enable_mask[i >> 1];
1163 p += dbg_enable_mask_str_len[i];
1164 break;
1165 }
1166 } while ( i < ARRAY_SIZE(dbg_enable_mask_str) );
1167 }
1168 }
1169
1170 return count;
1171 }
1172
1173 #endif // defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1174
1175 static INLINE int stricmp(const char *p1, const char *p2)
1176 {
1177 int c1, c2;
1178
1179 while ( *p1 && *p2 )
1180 {
1181 c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;
1182 c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;
1183 if ( (c1 -= c2) )
1184 return c1;
1185 p1++;
1186 p2++;
1187 }
1188
1189 return *p1 - *p2;
1190 }
1191
1192 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1193 static INLINE int strincmp(const char *p1, const char *p2, int n)
1194 {
1195 int c1 = 0, c2;
1196
1197 while ( n && *p1 && *p2 )
1198 {
1199 c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;
1200 c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;
1201 if ( (c1 -= c2) )
1202 return c1;
1203 p1++;
1204 p2++;
1205 n--;
1206 }
1207
1208 return n ? *p1 - *p2 : c1;
1209 }
1210 #endif
1211
1212 static INLINE int ifx_ptm_version(char *buf)
1213 {
1214 int len = 0;
1215 unsigned int major, minor;
1216
1217 ifx_ptm_get_fw_ver(&major, &minor);
1218
1219 len += sprintf(buf + len, "PTM %d.%d.%d", IFX_PTM_VER_MAJOR, IFX_PTM_VER_MID, IFX_PTM_VER_MINOR);
1220 len += sprintf(buf + len, " PTM (E1) firmware version %d.%d\n", major, minor);
1221
1222 return len;
1223 }
1224
1225 static INLINE void check_parameters(void)
1226 {
1227 /* There is a delay between PPE write descriptor and descriptor is */
1228 /* really stored in memory. Host also has this delay when writing */
1229 /* descriptor. So PPE will use this value to determine if the write */
1230 /* operation makes effect. */
1231 if ( write_desc_delay < 0 )
1232 write_desc_delay = 0;
1233
1234 /* Because of the limitation of length field in descriptors, the packet */
1235 /* size could not be larger than 64K minus overhead size. */
1236 if ( rx_max_packet_size < ETH_MIN_FRAME_LENGTH )
1237 rx_max_packet_size = ETH_MIN_FRAME_LENGTH;
1238 else if ( rx_max_packet_size > 65536 - 1 )
1239 rx_max_packet_size = 65536 - 1;
1240
1241 if ( dma_rx_descriptor_length < 2 )
1242 dma_rx_descriptor_length = 2;
1243 if ( dma_tx_descriptor_length < 2 )
1244 dma_tx_descriptor_length = 2;
1245 }
1246
1247 static INLINE int init_priv_data(void)
1248 {
1249 void *p;
1250 int i;
1251 struct rx_descriptor rx_desc = {0};
1252 struct sk_buff *skb;
1253 volatile struct rx_descriptor *p_rx_desc;
1254 volatile struct tx_descriptor *p_tx_desc;
1255 struct sk_buff **ppskb;
1256
1257 // clear ptm private data structure
1258 memset(&g_ptm_priv_data, 0, sizeof(g_ptm_priv_data));
1259
1260 // allocate memory for RX descriptors
1261 p = kzalloc(MAX_ITF_NUMBER * dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1262 if ( p == NULL )
1263 return -1;
1264 dma_cache_inv((unsigned long)p, MAX_ITF_NUMBER * dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1265 g_ptm_priv_data.rx_desc_base = p;
1266 //p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1267
1268 // allocate memory for TX descriptors
1269 p = kzalloc(MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1270 if ( p == NULL )
1271 return -1;
1272 dma_cache_inv((unsigned long)p, MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
1273 g_ptm_priv_data.tx_desc_base = p;
1274
1275 // allocate memroy for TX skb pointers
1276 p = kzalloc(MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
1277 if ( p == NULL )
1278 return -1;
1279 dma_cache_wback_inv((unsigned long)p, MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
1280 g_ptm_priv_data.tx_skb_base = p;
1281
1282 p_rx_desc = (volatile struct rx_descriptor *)((((unsigned int)g_ptm_priv_data.rx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1283 p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_ptm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1284 ppskb = (struct sk_buff **)(((unsigned int)g_ptm_priv_data.tx_skb_base + 3) & ~3);
1285 for ( i = 0; i < MAX_ITF_NUMBER; i++ ) {
1286 g_ptm_priv_data.itf[i].rx_desc = &p_rx_desc[i * dma_rx_descriptor_length];
1287 g_ptm_priv_data.itf[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
1288 g_ptm_priv_data.itf[i].tx_skb = &ppskb[i * dma_tx_descriptor_length];
1289 }
1290
1291 rx_desc.own = 1;
1292 rx_desc.c = 0;
1293 rx_desc.sop = 1;
1294 rx_desc.eop = 1;
1295 rx_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;
1296 rx_desc.id = 0;
1297 rx_desc.err = 0;
1298 rx_desc.datalen = rx_max_packet_size;
1299 for ( i = 0; i < MAX_ITF_NUMBER * dma_rx_descriptor_length; i++ ) {
1300 skb = alloc_skb_rx();
1301 if ( skb == NULL )
1302 return -1;
1303 rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
1304 p_rx_desc[i] = rx_desc;
1305 }
1306
1307 return 0;
1308 }
1309
1310 static INLINE void clear_priv_data(void)
1311 {
1312 int i, j;
1313 struct sk_buff *skb;
1314
1315 for ( i = 0; i < MAX_ITF_NUMBER; i++ ) {
1316 if ( g_ptm_priv_data.itf[i].tx_skb != NULL ) {
1317 for ( j = 0; j < dma_tx_descriptor_length; j++ )
1318 if ( g_ptm_priv_data.itf[i].tx_skb[j] != NULL )
1319 dev_kfree_skb_any(g_ptm_priv_data.itf[i].tx_skb[j]);
1320 }
1321 if ( g_ptm_priv_data.itf[i].rx_desc != NULL ) {
1322 for ( j = 0; j < dma_rx_descriptor_length; j++ ) {
1323 if ( g_ptm_priv_data.itf[i].rx_desc[j].sop || g_ptm_priv_data.itf[i].rx_desc[j].eop ) { // descriptor initialized
1324 skb = get_skb_rx_pointer(g_ptm_priv_data.itf[i].rx_desc[j].dataptr);
1325 dev_kfree_skb_any(skb);
1326 }
1327 }
1328 }
1329 }
1330
1331 if ( g_ptm_priv_data.rx_desc_base != NULL )
1332 kfree(g_ptm_priv_data.rx_desc_base);
1333
1334 if ( g_ptm_priv_data.tx_desc_base != NULL )
1335 kfree(g_ptm_priv_data.tx_desc_base);
1336
1337 if ( g_ptm_priv_data.tx_skb_base != NULL )
1338 kfree(g_ptm_priv_data.tx_skb_base);
1339 }
1340
1341 static INLINE void init_tables(void)
1342 {
1343 int i;
1344 volatile unsigned int *p;
1345 struct wrx_dma_channel_config rx_config = {0};
1346 struct wtx_dma_channel_config tx_config = {0};
1347 struct wrx_port_cfg_status rx_port_cfg = { 0 };
1348 struct wtx_port_cfg tx_port_cfg = { 0 };
1349
1350 /*
1351 * CDM Block 1
1352 */
1353 IFX_REG_W32(CDM_CFG_RAM1_SET(0x00) | CDM_CFG_RAM0_SET(0x00), CDM_CFG); // CDM block 1 must be data memory and mapped to 0x5000 (dword addr)
1354 p = CDM_DATA_MEMORY(0, 0); // Clear CDM block 1
1355 for ( i = 0; i < CDM_DATA_MEMORY_DWLEN; i++, p++ )
1356 IFX_REG_W32(0, p);
1357
1358 /*
1359 * General Registers
1360 */
1361 IFX_REG_W32(write_desc_delay, CFG_WAN_WRDES_DELAY);
1362 IFX_REG_W32((1 << MAX_RX_DMA_CHANNEL_NUMBER) - 1, CFG_WRX_DMACH_ON);
1363 IFX_REG_W32((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1, CFG_WTX_DMACH_ON);
1364
1365 IFX_REG_W32(8, CFG_WRX_LOOK_BITTH); // WAN RX EFM-TC Looking Threshold
1366
1367 IFX_REG_W32(eth_efmtc_crc_cfg, CFG_ETH_EFMTC_CRC);
1368
1369 /*
1370 * WRX DMA Channel Configuration Table
1371 */
1372 rx_config.deslen = dma_rx_descriptor_length;
1373 rx_port_cfg.mfs = ETH_MAX_FRAME_LENGTH;
1374 rx_port_cfg.local_state = 0; // looking for sync
1375 rx_port_cfg.partner_state = 0; // parter receiver is out of sync
1376
1377 for ( i = 0; i < MAX_RX_DMA_CHANNEL_NUMBER; i++ ) {
1378 rx_config.desba = ((unsigned int)g_ptm_priv_data.itf[i].rx_desc >> 2) & 0x0FFFFFFF;
1379 *WRX_DMA_CHANNEL_CONFIG(i) = rx_config;
1380
1381 rx_port_cfg.dmach = i;
1382 *WRX_PORT_CONFIG(i) = rx_port_cfg;
1383 }
1384
1385 /*
1386 * WTX DMA Channel Configuration Table
1387 */
1388 tx_config.deslen = dma_tx_descriptor_length;
1389 tx_port_cfg.tx_cwth1 = 5;
1390 tx_port_cfg.tx_cwth2 = 4;
1391
1392 for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {
1393 tx_config.desba = ((unsigned int)g_ptm_priv_data.itf[i].tx_desc >> 2) & 0x0FFFFFFF;
1394 *WTX_DMA_CHANNEL_CONFIG(i) = tx_config;
1395
1396 *WTX_PORT_CONFIG(i) = tx_port_cfg;
1397 }
1398 }
1399
1400
1401
1402 /*
1403 * ####################################
1404 * Global Function
1405 * ####################################
1406 */
1407
1408 static int ptm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
1409 {
1410 int i;
1411
1412 g_showtime = 1;
1413
1414 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
1415 netif_carrier_on(g_net_dev[i]);
1416
1417 printk("enter showtime\n");
1418
1419 return 0;
1420 }
1421
1422 static int ptm_showtime_exit(void)
1423 {
1424 int i;
1425
1426 if ( !g_showtime )
1427 return -1;
1428
1429 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
1430 netif_carrier_off(g_net_dev[i]);
1431
1432 g_showtime = 0;
1433
1434 printk("leave showtime\n");
1435
1436 return 0;
1437 }
1438
1439
1440
1441 /*
1442 * ####################################
1443 * Init/Cleanup API
1444 * ####################################
1445 */
1446
1447 /*
1448 * Description:
1449 * Initialize global variables, PP32, comunication structures, register IRQ
1450 * and register device.
1451 * Input:
1452 * none
1453 * Output:
1454 * 0 --- successful
1455 * else --- failure, usually it is negative value of error code
1456 */
1457 static int ifx_ptm_init(void)
1458 {
1459 int ret;
1460 struct port_cell_info port_cell = {0};
1461 void *xdata_addr = NULL;
1462 int i;
1463 char ver_str[256];
1464
1465 check_parameters();
1466
1467 ret = init_priv_data();
1468 if ( ret != 0 ) {
1469 err("INIT_PRIV_DATA_FAIL");
1470 goto INIT_PRIV_DATA_FAIL;
1471 }
1472
1473 ifx_ptm_init_chip();
1474 init_tables();
1475
1476 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
1477 g_net_dev[i] = alloc_netdev(0, g_net_dev_name[i], NET_NAME_UNKNOWN, ether_setup);
1478 if ( g_net_dev[i] == NULL )
1479 goto ALLOC_NETDEV_FAIL;
1480 ptm_setup(g_net_dev[i], i);
1481 }
1482
1483 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
1484 ret = register_netdev(g_net_dev[i]);
1485 if ( ret != 0 )
1486 goto REGISTER_NETDEV_FAIL;
1487 }
1488
1489 /* register interrupt handler */
1490 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)
1491 ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
1492 #else
1493 ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "ptm_mailbox_isr", &g_ptm_priv_data);
1494 #endif
1495 if ( ret ) {
1496 if ( ret == -EBUSY ) {
1497 err("IRQ may be occupied by other driver, please reconfig to disable it.");
1498 }
1499 else {
1500 err("request_irq fail");
1501 }
1502 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
1503 }
1504 disable_irq(PPE_MAILBOX_IGU1_INT);
1505
1506 ret = ifx_pp32_start(0);
1507 if ( ret ) {
1508 err("ifx_pp32_start fail!");
1509 goto PP32_START_FAIL;
1510 }
1511 IFX_REG_W32(0, MBOX_IGU1_IER);
1512 IFX_REG_W32(~0, MBOX_IGU1_ISRC);
1513
1514 enable_irq(PPE_MAILBOX_IGU1_INT);
1515
1516
1517 proc_file_create();
1518
1519 port_cell.port_num = 1;
1520 ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &xdata_addr);
1521 if ( g_showtime ) {
1522 ptm_showtime_enter(&port_cell, &g_xdata_addr);
1523 }
1524
1525 ifx_mei_atm_showtime_enter = ptm_showtime_enter;
1526 ifx_mei_atm_showtime_exit = ptm_showtime_exit;
1527
1528 ifx_ptm_version(ver_str);
1529 printk(KERN_INFO "%s", ver_str);
1530
1531 printk("ifxmips_ptm: PTM init succeed\n");
1532
1533 return 0;
1534
1535 PP32_START_FAIL:
1536 free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
1537 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1538 i = ARRAY_SIZE(g_net_dev);
1539 REGISTER_NETDEV_FAIL:
1540 while ( i-- )
1541 unregister_netdev(g_net_dev[i]);
1542 i = ARRAY_SIZE(g_net_dev);
1543 ALLOC_NETDEV_FAIL:
1544 while ( i-- ) {
1545 free_netdev(g_net_dev[i]);
1546 g_net_dev[i] = NULL;
1547 }
1548 INIT_PRIV_DATA_FAIL:
1549 clear_priv_data();
1550 printk("ifxmips_ptm: PTM init failed\n");
1551 return ret;
1552 }
1553
1554 /*
1555 * Description:
1556 * Release memory, free IRQ, and deregister device.
1557 * Input:
1558 * none
1559 * Output:
1560 * none
1561 */
1562 static void __exit ifx_ptm_exit(void)
1563 {
1564 int i;
1565
1566 ifx_mei_atm_showtime_enter = NULL;
1567 ifx_mei_atm_showtime_exit = NULL;
1568
1569 proc_file_delete();
1570
1571
1572 ifx_pp32_stop(0);
1573
1574 free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
1575
1576 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
1577 unregister_netdev(g_net_dev[i]);
1578
1579 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
1580 free_netdev(g_net_dev[i]);
1581 g_net_dev[i] = NULL;
1582 }
1583
1584 ifx_ptm_uninit_chip();
1585
1586 clear_priv_data();
1587 }
1588
1589 module_init(ifx_ptm_init);
1590 module_exit(ifx_ptm_exit);