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[openwrt/openwrt.git] / package / kernel / lantiq / ltq-ptm / src / ifxmips_ptm_adsl.c
1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_ptm_adsl.c
4 ** PROJECT : UEIP
5 ** MODULES : PTM
6 **
7 ** DATE : 7 Jul 2009
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : PTM driver common source file (core functions for Danube/
10 ** Amazon-SE/AR9)
11 ** COPYRIGHT : Copyright (c) 2006
12 ** Infineon Technologies AG
13 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 **
15 ** This program is free software; you can redistribute it and/or modify
16 ** it under the terms of the GNU General Public License as published by
17 ** the Free Software Foundation; either version 2 of the License, or
18 ** (at your option) any later version.
19 **
20 ** HISTORY
21 ** $Date $Author $Comment
22 ** 07 JUL 2009 Xu Liang Init Version
23 *******************************************************************************/
24
25
26
27 /*
28 * ####################################
29 * Head File
30 * ####################################
31 */
32
33 /*
34 * Common Head File
35 */
36 #include <linux/version.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/types.h>
40 #include <linux/errno.h>
41 #include <linux/proc_fs.h>
42 #include <linux/init.h>
43 #include <linux/ioctl.h>
44 #include <linux/etherdevice.h>
45 #include <linux/interrupt.h>
46 #include <linux/netdevice.h>
47 #include <asm/io.h>
48
49 /*
50 * Chip Specific Head File
51 */
52 #include "ifxmips_ptm_adsl.h"
53
54
55 #include <lantiq_soc.h>
56
57 /*
58 * ####################################
59 * Kernel Version Adaption
60 * ####################################
61 */
62 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
63 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
64 #define MODULE_PARM(a, b) module_param(a, int, 0)
65 #else
66 #define MODULE_PARM_ARRAY(a, b) MODULE_PARM(a, b)
67 #endif
68
69
70
71 /*
72 * ####################################
73 * Parameters to Configure PPE
74 * ####################################
75 */
76
77 static int write_desc_delay = 0x20; /* Write descriptor delay */
78
79 static int rx_max_packet_size = ETH_MAX_FRAME_LENGTH;
80 /* Max packet size for RX */
81
82 static int dma_rx_descriptor_length = 24; /* Number of descriptors per DMA RX channel */
83 static int dma_tx_descriptor_length = 24; /* Number of descriptors per DMA TX channel */
84
85 static int eth_efmtc_crc_cfg = 0x03100710; /* default: tx_eth_crc_check: 1, tx_tc_crc_check: 1, tx_tc_crc_len = 16 */
86 /* rx_eth_crc_present: 1, rx_eth_crc_check: 1, rx_tc_crc_check: 1, rx_tc_crc_len = 16 */
87
88 MODULE_PARM(write_desc_delay, "i");
89 MODULE_PARM_DESC(write_desc_delay, "PPE core clock cycles between descriptor write and effectiveness in external RAM");
90
91 MODULE_PARM(rx_max_packet_size, "i");
92 MODULE_PARM_DESC(rx_max_packet_size, "Max packet size in byte for downstream ethernet frames");
93
94 MODULE_PARM(dma_rx_descriptor_length, "i");
95 MODULE_PARM_DESC(dma_rx_descriptor_length, "Number of descriptor assigned to DMA RX channel (>16)");
96 MODULE_PARM(dma_tx_descriptor_length, "i");
97 MODULE_PARM_DESC(dma_tx_descriptor_length, "Number of descriptor assigned to DMA TX channel (>16)");
98
99 MODULE_PARM(eth_efmtc_crc_cfg, "i");
100 MODULE_PARM_DESC(eth_efmtc_crc_cfg, "Configuration for PTM TX/RX ethernet/efm-tc CRC");
101
102
103
104 /*
105 * ####################################
106 * Definition
107 * ####################################
108 */
109
110
111 #define DUMP_SKB_LEN ~0
112
113
114
115 /*
116 * ####################################
117 * Declaration
118 * ####################################
119 */
120
121 /*
122 * Network Operations
123 */
124 static void ptm_setup(struct net_device *, int);
125 static struct net_device_stats *ptm_get_stats(struct net_device *);
126 static int ptm_open(struct net_device *);
127 static int ptm_stop(struct net_device *);
128 static unsigned int ptm_poll(int, unsigned int);
129 static int ptm_napi_poll(struct napi_struct *, int);
130 static int ptm_hard_start_xmit(struct sk_buff *, struct net_device *);
131 static int ptm_ioctl(struct net_device *, struct ifreq *, int);
132 static void ptm_tx_timeout(struct net_device *);
133
134 /*
135 * DSL Data LED
136 */
137 static INLINE void adsl_led_flash(void);
138
139 /*
140 * buffer manage functions
141 */
142 static INLINE struct sk_buff* alloc_skb_rx(void);
143 //static INLINE struct sk_buff* alloc_skb_tx(unsigned int);
144 static INLINE struct sk_buff *get_skb_rx_pointer(unsigned int);
145 static INLINE int get_tx_desc(unsigned int, unsigned int *);
146
147 /*
148 * Mailbox handler and signal function
149 */
150 static INLINE int mailbox_rx_irq_handler(unsigned int);
151 static irqreturn_t mailbox_irq_handler(int, void *);
152 static INLINE void mailbox_signal(unsigned int, int);
153 #ifdef CONFIG_IFX_PTM_RX_TASKLET
154 static void do_ptm_tasklet(unsigned long);
155 #endif
156
157 /*
158 * Debug Functions
159 */
160 #if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
161 static void dump_skb(struct sk_buff *, u32, char *, int, int, int);
162 #else
163 #define dump_skb(skb, len, title, port, ch, is_tx) do {} while (0)
164 #endif
165 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
166 static void skb_swap(struct sk_buff *);
167 #else
168 #define skb_swap(skb) do {} while (0)
169 #endif
170
171 /*
172 * Proc File Functions
173 */
174 static INLINE void proc_file_create(void);
175 static INLINE void proc_file_delete(void);
176 static int proc_read_version(char *, char **, off_t, int, int *, void *);
177 static int proc_read_wanmib(char *, char **, off_t, int, int *, void *);
178 static int proc_write_wanmib(struct file *, const char *, unsigned long, void *);
179 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
180 static int proc_read_genconf(char *, char **, off_t, int, int *, void *);
181 #endif
182 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
183 static int proc_read_dbg(char *, char **, off_t, int, int *, void *);
184 static int proc_write_dbg(struct file *, const char *, unsigned long, void *);
185 #endif
186
187 /*
188 * Proc Help Functions
189 */
190 static INLINE int stricmp(const char *, const char *);
191 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
192 static INLINE int strincmp(const char *, const char *, int);
193 #endif
194 static INLINE int ifx_ptm_version(char *);
195
196 /*
197 * Init & clean-up functions
198 */
199 static INLINE void check_parameters(void);
200 static INLINE int init_priv_data(void);
201 static INLINE void clear_priv_data(void);
202 static INLINE void init_tables(void);
203
204 /*
205 * Exteranl Function
206 */
207 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
208 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
209 #else
210 static inline int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr)
211 {
212 if ( is_showtime != NULL )
213 *is_showtime = 0;
214 return 0;
215 }
216 #endif
217
218 /*
219 * External variable
220 */
221 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
222 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
223 extern int (*ifx_mei_atm_showtime_exit)(void);
224 #else
225 int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *) = NULL;
226 EXPORT_SYMBOL(ifx_mei_atm_showtime_enter);
227 int (*ifx_mei_atm_showtime_exit)(void) = NULL;
228 EXPORT_SYMBOL(ifx_mei_atm_showtime_exit);
229 #endif
230
231
232
233 /*
234 * ####################################
235 * Local Variable
236 * ####################################
237 */
238
239 static struct ptm_priv_data g_ptm_priv_data;
240
241 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)
242 static struct net_device_ops g_ptm_netdev_ops = {
243 .ndo_get_stats = ptm_get_stats,
244 .ndo_open = ptm_open,
245 .ndo_stop = ptm_stop,
246 .ndo_start_xmit = ptm_hard_start_xmit,
247 .ndo_validate_addr = eth_validate_addr,
248 .ndo_set_mac_address = eth_mac_addr,
249 .ndo_change_mtu = eth_change_mtu,
250 .ndo_do_ioctl = ptm_ioctl,
251 .ndo_tx_timeout = ptm_tx_timeout,
252 };
253 #endif
254
255 static struct net_device *g_net_dev[2] = {0};
256 static char *g_net_dev_name[2] = {"ptm0", "ptmfast0"};
257
258 #ifdef CONFIG_IFX_PTM_RX_TASKLET
259 static struct tasklet_struct g_ptm_tasklet[] = {
260 {NULL, 0, ATOMIC_INIT(0), do_ptm_tasklet, 0},
261 {NULL, 0, ATOMIC_INIT(0), do_ptm_tasklet, 1},
262 };
263 #endif
264
265 unsigned int ifx_ptm_dbg_enable = DBG_ENABLE_MASK_ERR;
266
267 static struct proc_dir_entry* g_ptm_dir = NULL;
268
269 static int g_showtime = 0;
270
271
272
273 /*
274 * ####################################
275 * Local Function
276 * ####################################
277 */
278
279 static void ptm_setup(struct net_device *dev, int ndev)
280 {
281 #if defined(CONFIG_IFXMIPS_DSL_CPE_MEI) || defined(CONFIG_IFXMIPS_DSL_CPE_MEI_MODULE)
282 netif_carrier_off(dev);
283 #endif
284
285 /* hook network operations */
286 dev->netdev_ops = &g_ptm_netdev_ops;
287 netif_napi_add(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 25);
288 dev->watchdog_timeo = ETH_WATCHDOG_TIMEOUT;
289
290 dev->dev_addr[0] = 0x00;
291 dev->dev_addr[1] = 0x20;
292 dev->dev_addr[2] = 0xda;
293 dev->dev_addr[3] = 0x86;
294 dev->dev_addr[4] = 0x23;
295 dev->dev_addr[5] = 0x75 + ndev;
296 }
297
298 static struct net_device_stats *ptm_get_stats(struct net_device *dev)
299 {
300 int ndev;
301
302 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
303 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
304
305 g_ptm_priv_data.itf[ndev].stats.rx_errors = WAN_MIB_TABLE[ndev].wrx_tccrc_err_pdu + WAN_MIB_TABLE[ndev].wrx_ethcrc_err_pdu;
306 g_ptm_priv_data.itf[ndev].stats.rx_dropped = WAN_MIB_TABLE[ndev].wrx_nodesc_drop_pdu + WAN_MIB_TABLE[ndev].wrx_len_violation_drop_pdu + (WAN_MIB_TABLE[ndev].wrx_correct_pdu - g_ptm_priv_data.itf[ndev].stats.rx_packets);
307
308 return &g_ptm_priv_data.itf[ndev].stats;
309 }
310
311 static int ptm_open(struct net_device *dev)
312 {
313 int ndev;
314
315 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
316 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
317
318 napi_enable(&g_ptm_priv_data.itf[ndev].napi);
319
320 IFX_REG_W32_MASK(0, 1 << ndev, MBOX_IGU1_IER);
321
322 netif_start_queue(dev);
323
324 return 0;
325 }
326
327 static int ptm_stop(struct net_device *dev)
328 {
329 int ndev;
330
331 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
332 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
333
334 IFX_REG_W32_MASK((1 << ndev) | (1 << (ndev + 16)), 0, MBOX_IGU1_IER);
335
336 napi_disable(&g_ptm_priv_data.itf[ndev].napi);
337
338 netif_stop_queue(dev);
339
340 return 0;
341 }
342
343 static unsigned int ptm_poll(int ndev, unsigned int work_to_do)
344 {
345 unsigned int work_done = 0;
346
347 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
348
349 while ( work_done < work_to_do && WRX_DMA_CHANNEL_CONFIG(ndev)->vlddes > 0 ) {
350 if ( mailbox_rx_irq_handler(ndev) < 0 )
351 break;
352
353 work_done++;
354 }
355
356 return work_done;
357 }
358 static int ptm_napi_poll(struct napi_struct *napi, int budget)
359 {
360 int ndev;
361 unsigned int work_done;
362
363 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != napi->dev; ndev++ );
364
365 work_done = ptm_poll(ndev, budget);
366
367 // interface down
368 if ( !netif_running(napi->dev) ) {
369 napi_complete(napi);
370 return work_done;
371 }
372
373 // no more traffic
374 if ( WRX_DMA_CHANNEL_CONFIG(ndev)->vlddes == 0 ) {
375 // clear interrupt
376 IFX_REG_W32_MASK(0, 1 << ndev, MBOX_IGU1_ISRC);
377 // double check
378 if ( WRX_DMA_CHANNEL_CONFIG(ndev)->vlddes == 0 ) {
379 napi_complete(napi);
380 IFX_REG_W32_MASK(0, 1 << ndev, MBOX_IGU1_IER);
381 return work_done;
382 }
383 }
384
385 // next round
386 return work_done;
387 }
388
389 static int ptm_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
390 {
391 int ndev;
392 unsigned int f_full;
393 int desc_base;
394 register struct tx_descriptor reg_desc = {0};
395
396 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
397 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
398
399 if ( !g_showtime ) {
400 err("not in showtime");
401 goto PTM_HARD_START_XMIT_FAIL;
402 }
403
404 /* allocate descriptor */
405 desc_base = get_tx_desc(ndev, &f_full);
406 if ( f_full ) {
407 dev->trans_start = jiffies;
408 netif_stop_queue(dev);
409
410 IFX_REG_W32_MASK(0, 1 << (ndev + 16), MBOX_IGU1_ISRC);
411 IFX_REG_W32_MASK(0, 1 << (ndev + 16), MBOX_IGU1_IER);
412 }
413 if ( desc_base < 0 )
414 goto PTM_HARD_START_XMIT_FAIL;
415
416 if ( g_ptm_priv_data.itf[ndev].tx_skb[desc_base] != NULL )
417 dev_kfree_skb_any(g_ptm_priv_data.itf[ndev].tx_skb[desc_base]);
418 g_ptm_priv_data.itf[ndev].tx_skb[desc_base] = skb;
419
420 reg_desc.dataptr = (unsigned int)skb->data >> 2;
421 reg_desc.datalen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
422 reg_desc.byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
423 reg_desc.own = 1;
424 reg_desc.c = 1;
425 reg_desc.sop = reg_desc.eop = 1;
426
427 /* write discriptor to memory and write back cache */
428 g_ptm_priv_data.itf[ndev].tx_desc[desc_base] = reg_desc;
429 dma_cache_wback((unsigned long)skb->data, skb->len);
430 wmb();
431
432 dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, ndev, ndev, 1);
433
434 if ( (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_MAC_SWAP) ) {
435 skb_swap(skb);
436 }
437
438 g_ptm_priv_data.itf[ndev].stats.tx_packets++;
439 g_ptm_priv_data.itf[ndev].stats.tx_bytes += reg_desc.datalen;
440
441 dev->trans_start = jiffies;
442 mailbox_signal(ndev, 1);
443
444 adsl_led_flash();
445
446 return NETDEV_TX_OK;
447
448 PTM_HARD_START_XMIT_FAIL:
449 dev_kfree_skb_any(skb);
450 g_ptm_priv_data.itf[ndev].stats.tx_dropped++;
451 return NETDEV_TX_OK;
452 }
453
454 static int ptm_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
455 {
456 int ndev;
457
458 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
459 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
460
461 switch ( cmd )
462 {
463 case IFX_PTM_MIB_CW_GET:
464 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxNoIdleCodewords = WAN_MIB_TABLE[ndev].wrx_nonidle_cw;
465 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxIdleCodewords = WAN_MIB_TABLE[ndev].wrx_idle_cw;
466 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxCodingViolation = WAN_MIB_TABLE[ndev].wrx_err_cw;
467 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxNoIdleCodewords = 0;
468 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxIdleCodewords = 0;
469 break;
470 case IFX_PTM_MIB_FRAME_GET:
471 ((PTM_FRAME_MIB_T *)ifr->ifr_data)->RxCorrect = WAN_MIB_TABLE[ndev].wrx_correct_pdu;
472 ((PTM_FRAME_MIB_T *)ifr->ifr_data)->TC_CrcError = WAN_MIB_TABLE[ndev].wrx_tccrc_err_pdu;
473 ((PTM_FRAME_MIB_T *)ifr->ifr_data)->RxDropped = WAN_MIB_TABLE[ndev].wrx_nodesc_drop_pdu + WAN_MIB_TABLE[ndev].wrx_len_violation_drop_pdu;
474 ((PTM_FRAME_MIB_T *)ifr->ifr_data)->TxSend = WAN_MIB_TABLE[ndev].wtx_total_pdu;
475 break;
476 case IFX_PTM_CFG_GET:
477 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcPresent = CFG_ETH_EFMTC_CRC->rx_eth_crc_present;
478 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck = CFG_ETH_EFMTC_CRC->rx_eth_crc_check;
479 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck = CFG_ETH_EFMTC_CRC->rx_tc_crc_check;
480 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen = CFG_ETH_EFMTC_CRC->rx_tc_crc_len;
481 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen = CFG_ETH_EFMTC_CRC->tx_eth_crc_gen;
482 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen = CFG_ETH_EFMTC_CRC->tx_tc_crc_gen;
483 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen = CFG_ETH_EFMTC_CRC->tx_tc_crc_len;
484 break;
485 case IFX_PTM_CFG_SET:
486 CFG_ETH_EFMTC_CRC->rx_eth_crc_present = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcPresent ? 1 : 0;
487 CFG_ETH_EFMTC_CRC->rx_eth_crc_check = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck ? 1 : 0;
488 if ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck && (((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen == 16 || ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen == 32) )
489 {
490 CFG_ETH_EFMTC_CRC->rx_tc_crc_check = 1;
491 CFG_ETH_EFMTC_CRC->rx_tc_crc_len = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen;
492 }
493 else
494 {
495 CFG_ETH_EFMTC_CRC->rx_tc_crc_check = 0;
496 CFG_ETH_EFMTC_CRC->rx_tc_crc_len = 0;
497 }
498 CFG_ETH_EFMTC_CRC->tx_eth_crc_gen = ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen ? 1 : 0;
499 if ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen && (((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen == 16 || ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen == 32) )
500 {
501 CFG_ETH_EFMTC_CRC->tx_tc_crc_gen = 1;
502 CFG_ETH_EFMTC_CRC->tx_tc_crc_len = ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen;
503 }
504 else
505 {
506 CFG_ETH_EFMTC_CRC->tx_tc_crc_gen = 0;
507 CFG_ETH_EFMTC_CRC->tx_tc_crc_len = 0;
508 }
509 break;
510 default:
511 return -EOPNOTSUPP;
512 }
513
514 return 0;
515 }
516
517 static void ptm_tx_timeout(struct net_device *dev)
518 {
519 int ndev;
520
521 for ( ndev = 0; ndev < ARRAY_SIZE(g_net_dev) && g_net_dev[ndev] != dev; ndev++ );
522 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
523
524 /* disable TX irq, release skb when sending new packet */
525 IFX_REG_W32_MASK(1 << (ndev + 16), 0, MBOX_IGU1_IER);
526
527 /* wake up TX queue */
528 netif_wake_queue(dev);
529
530 return;
531 }
532
533 static INLINE void adsl_led_flash(void)
534 {
535 }
536
537 static INLINE struct sk_buff* alloc_skb_rx(void)
538 {
539 struct sk_buff *skb;
540
541 /* allocate memroy including trailer and padding */
542 skb = dev_alloc_skb(rx_max_packet_size + RX_HEAD_MAC_ADDR_ALIGNMENT + DATA_BUFFER_ALIGNMENT);
543 if ( skb != NULL ) {
544 /* must be burst length alignment and reserve two more bytes for MAC address alignment */
545 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
546 skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
547 /* pub skb in reserved area "skb->data - 4" */
548 *((struct sk_buff **)skb->data - 1) = skb;
549 wmb();
550 /* write back and invalidate cache */
551 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
552 /* invalidate cache */
553 dma_cache_inv((unsigned long)skb->data, (unsigned int)skb->end - (unsigned int)skb->data);
554 }
555
556 return skb;
557 }
558
559 #if 0
560 static INLINE struct sk_buff* alloc_skb_tx(unsigned int size)
561 {
562 struct sk_buff *skb;
563
564 /* allocate memory including padding */
565 size = (size + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1);
566 skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
567 /* must be burst length alignment */
568 if ( skb != NULL )
569 skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
570 return skb;
571 }
572 #endif
573
574 static INLINE struct sk_buff *get_skb_rx_pointer(unsigned int dataptr)
575 {
576 unsigned int skb_dataptr;
577 struct sk_buff *skb;
578
579 skb_dataptr = ((dataptr - 1) << 2) | KSEG1;
580 skb = *(struct sk_buff **)skb_dataptr;
581
582 ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
583 ASSERT(((unsigned int)skb->data | KSEG1) == ((dataptr << 2) | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
584
585 return skb;
586 }
587
588 static INLINE int get_tx_desc(unsigned int itf, unsigned int *f_full)
589 {
590 int desc_base = -1;
591 struct ptm_itf *p_itf = &g_ptm_priv_data.itf[itf];
592
593 // assume TX is serial operation
594 // no protection provided
595
596 *f_full = 1;
597
598 if ( p_itf->tx_desc[p_itf->tx_desc_pos].own == 0 ) {
599 desc_base = p_itf->tx_desc_pos;
600 if ( ++(p_itf->tx_desc_pos) == dma_tx_descriptor_length )
601 p_itf->tx_desc_pos = 0;
602 if ( p_itf->tx_desc[p_itf->tx_desc_pos].own == 0 )
603 *f_full = 0;
604 }
605
606 return desc_base;
607 }
608
609 static INLINE int mailbox_rx_irq_handler(unsigned int ch) // return: < 0 - descriptor not available, 0 - received one packet
610 {
611 unsigned int ndev = ch;
612 struct sk_buff *skb;
613 struct sk_buff *new_skb;
614 volatile struct rx_descriptor *desc;
615 struct rx_descriptor reg_desc;
616 int netif_rx_ret;
617
618 desc = &g_ptm_priv_data.itf[ndev].rx_desc[g_ptm_priv_data.itf[ndev].rx_desc_pos];
619 if ( desc->own || !desc->c ) // if PP32 hold descriptor or descriptor not completed
620 return -EAGAIN;
621 if ( ++g_ptm_priv_data.itf[ndev].rx_desc_pos == dma_rx_descriptor_length )
622 g_ptm_priv_data.itf[ndev].rx_desc_pos = 0;
623
624 reg_desc = *desc;
625 skb = get_skb_rx_pointer(reg_desc.dataptr);
626
627 if ( !reg_desc.err ) {
628 new_skb = alloc_skb_rx();
629 if ( new_skb != NULL ) {
630 skb_reserve(skb, reg_desc.byteoff);
631 skb_put(skb, reg_desc.datalen);
632
633 dump_skb(skb, DUMP_SKB_LEN, (char *)__func__, ndev, ndev, 0);
634
635 // parse protocol header
636 skb->dev = g_net_dev[ndev];
637 skb->protocol = eth_type_trans(skb, skb->dev);
638
639 g_net_dev[ndev]->last_rx = jiffies;
640
641 netif_rx_ret = netif_receive_skb(skb);
642
643 if ( netif_rx_ret != NET_RX_DROP ) {
644 g_ptm_priv_data.itf[ndev].stats.rx_packets++;
645 g_ptm_priv_data.itf[ndev].stats.rx_bytes += reg_desc.datalen;
646 }
647
648 reg_desc.dataptr = ((unsigned int)new_skb->data >> 2) & 0x0FFFFFFF;
649 reg_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;
650 }
651 }
652 else
653 reg_desc.err = 0;
654
655 reg_desc.datalen = rx_max_packet_size;
656 reg_desc.own = 1;
657 reg_desc.c = 0;
658
659 // update descriptor
660 *desc = reg_desc;
661 wmb();
662
663 mailbox_signal(ndev, 0);
664
665 adsl_led_flash();
666
667 return 0;
668 }
669
670 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
671 {
672 unsigned int isr;
673 int i;
674
675 isr = IFX_REG_R32(MBOX_IGU1_ISR);
676 IFX_REG_W32(isr, MBOX_IGU1_ISRC);
677 isr &= IFX_REG_R32(MBOX_IGU1_IER);
678
679 while ( (i = __fls(isr)) >= 0 ) {
680 isr ^= 1 << i;
681
682 if ( i >= 16 ) {
683 // TX
684 IFX_REG_W32_MASK(1 << i, 0, MBOX_IGU1_IER);
685 i -= 16;
686 if ( i < MAX_ITF_NUMBER )
687 netif_wake_queue(g_net_dev[i]);
688 }
689 else {
690 // RX
691 #ifdef CONFIG_IFX_PTM_RX_INTERRUPT
692 while ( WRX_DMA_CHANNEL_CONFIG(i)->vlddes > 0 )
693 mailbox_rx_irq_handler(i);
694 #else
695 IFX_REG_W32_MASK(1 << i, 0, MBOX_IGU1_IER);
696 napi_schedule(&g_ptm_priv_data.itf[i].napi);
697 #endif
698 }
699 }
700
701 return IRQ_HANDLED;
702 }
703
704 static INLINE void mailbox_signal(unsigned int itf, int is_tx)
705 {
706 int count = 1000;
707
708 if ( is_tx ) {
709 while ( MBOX_IGU3_ISR_ISR(itf + 16) && count > 0 )
710 count--;
711 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf + 16), MBOX_IGU3_ISRS);
712 }
713 else {
714 while ( MBOX_IGU3_ISR_ISR(itf) && count > 0 )
715 count--;
716 IFX_REG_W32(MBOX_IGU3_ISRS_SET(itf), MBOX_IGU3_ISRS);
717 }
718
719 ASSERT(count != 0, "MBOX_IGU3_ISR = 0x%08x", IFX_REG_R32(MBOX_IGU3_ISR));
720 }
721
722 #ifdef CONFIG_IFX_PTM_RX_TASKLET
723 static void do_ptm_tasklet(unsigned long arg)
724 {
725 unsigned int work_to_do = 25;
726 unsigned int work_done = 0;
727
728 ASSERT(arg >= 0 && arg < ARRAY_SIZE(g_net_dev), "arg = %lu (wrong value)", arg);
729
730 while ( work_done < work_to_do && WRX_DMA_CHANNEL_CONFIG(arg)->vlddes > 0 ) {
731 if ( mailbox_rx_irq_handler(arg) < 0 )
732 break;
733
734 work_done++;
735 }
736
737 // interface down
738 if ( !netif_running(g_net_dev[arg]) )
739 return;
740
741 // no more traffic
742 if ( WRX_DMA_CHANNEL_CONFIG(arg)->vlddes == 0 ) {
743 // clear interrupt
744 IFX_REG_W32_MASK(0, 1 << arg, MBOX_IGU1_ISRC);
745 // double check
746 if ( WRX_DMA_CHANNEL_CONFIG(arg)->vlddes == 0 ) {
747 IFX_REG_W32_MASK(0, 1 << arg, MBOX_IGU1_IER);
748 return;
749 }
750 }
751
752 // next round
753 tasklet_schedule(&g_ptm_tasklet[arg]);
754 }
755 #endif
756
757 #if defined(DEBUG_DUMP_SKB) && DEBUG_DUMP_SKB
758 static void dump_skb(struct sk_buff *skb, u32 len, char *title, int port, int ch, int is_tx)
759 {
760 int i;
761
762 if ( !(ifx_ptm_dbg_enable & (is_tx ? DBG_ENABLE_MASK_DUMP_SKB_TX : DBG_ENABLE_MASK_DUMP_SKB_RX)) )
763 return;
764
765 if ( skb->len < len )
766 len = skb->len;
767
768 if ( len > rx_max_packet_size ) {
769 printk("too big data length: skb = %08x, skb->data = %08x, skb->len = %d\n", (u32)skb, (u32)skb->data, skb->len);
770 return;
771 }
772
773 if ( ch >= 0 )
774 printk("%s (port %d, ch %d)\n", title, port, ch);
775 else
776 printk("%s\n", title);
777 printk(" skb->data = %08X, skb->tail = %08X, skb->len = %d\n", (u32)skb->data, (u32)skb->tail, (int)skb->len);
778 for ( i = 1; i <= len; i++ ) {
779 if ( i % 16 == 1 )
780 printk(" %4d:", i - 1);
781 printk(" %02X", (int)(*((char*)skb->data + i - 1) & 0xFF));
782 if ( i % 16 == 0 )
783 printk("\n");
784 }
785 if ( (i - 1) % 16 != 0 )
786 printk("\n");
787 }
788 #endif
789
790 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
791 static void skb_swap(struct sk_buff *skb)
792 {
793 unsigned char tmp[8];
794 unsigned char *p = skb->data;
795
796 if ( !(p[0] & 0x01) ) { // bypass broadcast/multicast
797 // swap MAC
798 memcpy(tmp, p, 6);
799 memcpy(p, p + 6, 6);
800 memcpy(p + 6, tmp, 6);
801 p += 12;
802
803 // bypass VLAN
804 while ( p[0] == 0x81 && p[1] == 0x00 )
805 p += 4;
806
807 // IP
808 if ( p[0] == 0x08 && p[1] == 0x00 ) {
809 p += 14;
810 memcpy(tmp, p, 4);
811 memcpy(p, p + 4, 4);
812 memcpy(p + 4, tmp, 4);
813 p += 8;
814 }
815
816 dma_cache_wback((unsigned long)skb->data, (unsigned long)p - (unsigned long)skb->data);
817 }
818 }
819 #endif
820
821 static INLINE void proc_file_create(void)
822 {
823 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
824 struct proc_dir_entry *res;
825
826 g_ptm_dir = proc_mkdir("driver/ifx_ptm", NULL);
827
828 create_proc_read_entry("version",
829 0,
830 g_ptm_dir,
831 proc_read_version,
832 NULL);
833
834 res = create_proc_entry("wanmib",
835 0,
836 g_ptm_dir);
837 if ( res != NULL ) {
838 res->read_proc = proc_read_wanmib;
839 res->write_proc = proc_write_wanmib;
840 }
841
842 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
843 create_proc_read_entry("genconf",
844 0,
845 g_ptm_dir,
846 proc_read_genconf,
847 NULL);
848
849 #ifdef CONFIG_AR9
850 create_proc_read_entry("regs",
851 0,
852 g_ptm_dir,
853 ifx_ptm_proc_read_regs,
854 NULL);
855 #endif
856 #endif
857
858 res = create_proc_entry("dbg",
859 0,
860 g_ptm_dir);
861 if ( res != NULL ) {
862 res->read_proc = proc_read_dbg;
863 res->write_proc = proc_write_dbg;
864 }
865 #endif
866 }
867
868 static INLINE void proc_file_delete(void)
869 {
870 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
871 remove_proc_entry("dbg", g_ptm_dir);
872 #endif
873
874 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
875 #ifdef CONFIG_AR9
876 remove_proc_entry("regs", g_ptm_dir);
877 #endif
878
879 remove_proc_entry("genconf", g_ptm_dir);
880 #endif
881
882 remove_proc_entry("wanmib", g_ptm_dir);
883
884 remove_proc_entry("version", g_ptm_dir);
885
886 remove_proc_entry("driver/ifx_ptm", NULL);
887 }
888
889 static int proc_read_version(char *buf, char **start, off_t offset, int count, int *eof, void *data)
890 {
891 int len = 0;
892
893 len += ifx_ptm_version(buf + len);
894
895 if ( offset >= len ) {
896 *start = buf;
897 *eof = 1;
898 return 0;
899 }
900 *start = buf + offset;
901 if ( (len -= offset) > count )
902 return count;
903 *eof = 1;
904 return len;
905 }
906
907 static int proc_read_wanmib(char *page, char **start, off_t off, int count, int *eof, void *data)
908 {
909 int len = 0;
910 int i;
911 char *title[] = {
912 "ptm0\n",
913 "ptmfast0\n"
914 };
915
916 for ( i = 0; i < ARRAY_SIZE(title); i++ ) {
917 len += sprintf(page + off + len, title[i]);
918 len += sprintf(page + off + len, " wrx_correct_pdu = %d\n", WAN_MIB_TABLE[i].wrx_correct_pdu);
919 len += sprintf(page + off + len, " wrx_correct_pdu_bytes = %d\n", WAN_MIB_TABLE[i].wrx_correct_pdu_bytes);
920 len += sprintf(page + off + len, " wrx_tccrc_err_pdu = %d\n", WAN_MIB_TABLE[i].wrx_tccrc_err_pdu);
921 len += sprintf(page + off + len, " wrx_tccrc_err_pdu_bytes = %d\n", WAN_MIB_TABLE[i].wrx_tccrc_err_pdu_bytes);
922 len += sprintf(page + off + len, " wrx_ethcrc_err_pdu = %d\n", WAN_MIB_TABLE[i].wrx_ethcrc_err_pdu);
923 len += sprintf(page + off + len, " wrx_ethcrc_err_pdu_bytes = %d\n", WAN_MIB_TABLE[i].wrx_ethcrc_err_pdu_bytes);
924 len += sprintf(page + off + len, " wrx_nodesc_drop_pdu = %d\n", WAN_MIB_TABLE[i].wrx_nodesc_drop_pdu);
925 len += sprintf(page + off + len, " wrx_len_violation_drop_pdu = %d\n", WAN_MIB_TABLE[i].wrx_len_violation_drop_pdu);
926 len += sprintf(page + off + len, " wrx_idle_bytes = %d\n", WAN_MIB_TABLE[i].wrx_idle_bytes);
927 len += sprintf(page + off + len, " wrx_nonidle_cw = %d\n", WAN_MIB_TABLE[i].wrx_nonidle_cw);
928 len += sprintf(page + off + len, " wrx_idle_cw = %d\n", WAN_MIB_TABLE[i].wrx_idle_cw);
929 len += sprintf(page + off + len, " wrx_err_cw = %d\n", WAN_MIB_TABLE[i].wrx_err_cw);
930 len += sprintf(page + off + len, " wtx_total_pdu = %d\n", WAN_MIB_TABLE[i].wtx_total_pdu);
931 len += sprintf(page + off + len, " wtx_total_bytes = %d\n", WAN_MIB_TABLE[i].wtx_total_bytes);
932 }
933
934 *eof = 1;
935
936 return len;
937 }
938
939 static int proc_write_wanmib(struct file *file, const char *buf, unsigned long count, void *data)
940 {
941 char str[2048];
942 char *p;
943 int len, rlen;
944
945 int i;
946
947 len = count < sizeof(str) ? count : sizeof(str) - 1;
948 rlen = len - copy_from_user(str, buf, len);
949 while ( rlen && str[rlen - 1] <= ' ' )
950 rlen--;
951 str[rlen] = 0;
952 for ( p = str; *p && *p <= ' '; p++, rlen-- );
953 if ( !*p )
954 return count;
955
956 if ( stricmp(p, "clear") == 0 || stricmp(p, "clean") == 0 ) {
957 for ( i = 0; i < 2; i++ )
958 memset((void*)&WAN_MIB_TABLE[i], 0, sizeof(WAN_MIB_TABLE[i]));
959 }
960
961 return count;
962 }
963
964 #if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
965
966 static int proc_read_genconf(char *page, char **start, off_t off, int count, int *eof, void *data)
967 {
968 int len = 0;
969 int len_max = off + count;
970 char *pstr;
971 char str[2048];
972 int llen = 0;
973 int i;
974 unsigned long bit;
975
976 pstr = *start = page;
977
978 __sync();
979
980 llen += sprintf(str + llen, "CFG_WAN_WRDES_DELAY (0x%08X): %d\n", (unsigned int)CFG_WAN_WRDES_DELAY, IFX_REG_R32(CFG_WAN_WRDES_DELAY));
981 llen += sprintf(str + llen, "CFG_WRX_DMACH_ON (0x%08X):", (unsigned int)CFG_WRX_DMACH_ON);
982 for ( i = 0, bit = 1; i < MAX_RX_DMA_CHANNEL_NUMBER; i++, bit <<= 1 )
983 llen += sprintf(str + llen, " %d - %s", i, (IFX_REG_R32(CFG_WRX_DMACH_ON) & bit) ? "on " : "off");
984 llen += sprintf(str + llen, "\n");
985 llen += sprintf(str + llen, "CFG_WTX_DMACH_ON (0x%08X):", (unsigned int)CFG_WTX_DMACH_ON);
986 for ( i = 0, bit = 1; i < MAX_TX_DMA_CHANNEL_NUMBER; i++, bit <<= 1 )
987 llen += sprintf(str + llen, " %d - %s", i, (IFX_REG_R32(CFG_WTX_DMACH_ON) & bit) ? "on " : "off");
988 llen += sprintf(str + llen, "\n");
989 llen += sprintf(str + llen, "CFG_WRX_LOOK_BITTH (0x%08X): %d\n", (unsigned int)CFG_WRX_LOOK_BITTH, IFX_REG_R32(CFG_WRX_LOOK_BITTH));
990 llen += sprintf(str + llen, "CFG_ETH_EFMTC_CRC (0x%08X): rx_tc_crc_len - %2d, rx_tc_crc_check - %s\n", (unsigned int)CFG_ETH_EFMTC_CRC, CFG_ETH_EFMTC_CRC->rx_tc_crc_len, CFG_ETH_EFMTC_CRC->rx_tc_crc_check ? " on" : "off");
991 llen += sprintf(str + llen, " rx_eth_crc_check - %s, rx_eth_crc_present - %s\n", CFG_ETH_EFMTC_CRC->rx_eth_crc_check ? " on" : "off", CFG_ETH_EFMTC_CRC->rx_eth_crc_present ? " on" : "off");
992 llen += sprintf(str + llen, " tx_tc_crc_len - %2d, tx_tc_crc_gen - %s\n", CFG_ETH_EFMTC_CRC->tx_tc_crc_len, CFG_ETH_EFMTC_CRC->tx_tc_crc_gen ? " on" : "off");
993 llen += sprintf(str + llen, " tx_eth_crc_gen - %s\n", CFG_ETH_EFMTC_CRC->tx_eth_crc_gen ? " on" : "off");
994
995 llen += sprintf(str + llen, "RX Port:\n");
996 for ( i = 0; i < MAX_RX_DMA_CHANNEL_NUMBER; i++ )
997 llen += sprintf(str + llen, " %d (0x%08X). mfs - %5d, dmach - %d, local_state - %d, partner_state - %d\n", i, (unsigned int)WRX_PORT_CONFIG(i), WRX_PORT_CONFIG(i)->mfs, WRX_PORT_CONFIG(i)->dmach, WRX_PORT_CONFIG(i)->local_state, WRX_PORT_CONFIG(i)->partner_state);
998 llen += sprintf(str + llen, "RX DMA Channel:\n");
999 for ( i = 0; i < MAX_RX_DMA_CHANNEL_NUMBER; i++ )
1000 llen += sprintf(str + llen, " %d (0x%08X). desba - 0x%08X (0x%08X), deslen - %d, vlddes - %d\n", i, (unsigned int)WRX_DMA_CHANNEL_CONFIG(i), WRX_DMA_CHANNEL_CONFIG(i)->desba, ((unsigned int)WRX_DMA_CHANNEL_CONFIG(i)->desba << 2) | KSEG1, WRX_DMA_CHANNEL_CONFIG(i)->deslen, WRX_DMA_CHANNEL_CONFIG(i)->vlddes);
1001
1002 llen += sprintf(str + llen, "TX Port:\n");
1003 for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ )
1004 llen += sprintf(str + llen, " %d (0x%08X). tx_cwth2 - %d, tx_cwth1 - %d\n", i, (unsigned int)WTX_PORT_CONFIG(i), WTX_PORT_CONFIG(i)->tx_cwth2, WTX_PORT_CONFIG(i)->tx_cwth1);
1005 llen += sprintf(str + llen, "TX DMA Channel:\n");
1006 for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ )
1007 llen += sprintf(str + llen, " %d (0x%08X). desba - 0x%08X (0x%08X), deslen - %d, vlddes - %d\n", i, (unsigned int)WTX_DMA_CHANNEL_CONFIG(i), WTX_DMA_CHANNEL_CONFIG(i)->desba, ((unsigned int)WTX_DMA_CHANNEL_CONFIG(i)->desba << 2) | KSEG1, WTX_DMA_CHANNEL_CONFIG(i)->deslen, WTX_DMA_CHANNEL_CONFIG(i)->vlddes);
1008
1009 if ( len <= off && len + llen > off )
1010 {
1011 memcpy(pstr, str + off - len, len + llen - off);
1012 pstr += len + llen - off;
1013 }
1014 else if ( len > off )
1015 {
1016 memcpy(pstr, str, llen);
1017 pstr += llen;
1018 }
1019 len += llen;
1020 if ( len >= len_max )
1021 goto PROC_READ_GENCONF_OVERRUN_END;
1022
1023 *eof = 1;
1024
1025 return len - off;
1026
1027 PROC_READ_GENCONF_OVERRUN_END:
1028 return len - llen - off;
1029 }
1030
1031 #endif // defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
1032
1033 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1034
1035 static int proc_read_dbg(char *page, char **start, off_t off, int count, int *eof, void *data)
1036 {
1037 int len = 0;
1038
1039 len += sprintf(page + off + len, "error print - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_ERR) ? "enabled" : "disabled");
1040 len += sprintf(page + off + len, "debug print - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_DEBUG_PRINT) ? "enabled" : "disabled");
1041 len += sprintf(page + off + len, "assert - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_ASSERT) ? "enabled" : "disabled");
1042 len += sprintf(page + off + len, "dump rx skb - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_RX) ? "enabled" : "disabled");
1043 len += sprintf(page + off + len, "dump tx skb - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_DUMP_SKB_TX) ? "enabled" : "disabled");
1044 len += sprintf(page + off + len, "mac swap - %s\n", (ifx_ptm_dbg_enable & DBG_ENABLE_MASK_MAC_SWAP) ? "enabled" : "disabled");
1045
1046 *eof = 1;
1047
1048 return len;
1049 }
1050
1051 static int proc_write_dbg(struct file *file, const char *buf, unsigned long count, void *data)
1052 {
1053 static const char *dbg_enable_mask_str[] = {
1054 " error print",
1055 " err",
1056 " debug print",
1057 " dbg",
1058 " assert",
1059 " assert",
1060 " dump rx skb",
1061 " rx",
1062 " dump tx skb",
1063 " tx",
1064 " dump init",
1065 " init",
1066 " dump qos",
1067 " qos",
1068 " mac swap",
1069 " swap",
1070 " all"
1071 };
1072 static const int dbg_enable_mask_str_len[] = {
1073 12, 4,
1074 12, 4,
1075 7, 7,
1076 12, 3,
1077 12, 3,
1078 10, 5,
1079 9, 4,
1080 9, 5,
1081 4
1082 };
1083 unsigned int dbg_enable_mask[] = {
1084 DBG_ENABLE_MASK_ERR,
1085 DBG_ENABLE_MASK_DEBUG_PRINT,
1086 DBG_ENABLE_MASK_ASSERT,
1087 DBG_ENABLE_MASK_DUMP_SKB_RX,
1088 DBG_ENABLE_MASK_DUMP_SKB_TX,
1089 DBG_ENABLE_MASK_DUMP_INIT,
1090 DBG_ENABLE_MASK_DUMP_QOS,
1091 DBG_ENABLE_MASK_MAC_SWAP,
1092 DBG_ENABLE_MASK_ALL
1093 };
1094
1095 char str[2048];
1096 char *p;
1097
1098 int len, rlen;
1099
1100 int f_enable = 0;
1101 int i;
1102
1103 len = count < sizeof(str) ? count : sizeof(str) - 1;
1104 rlen = len - copy_from_user(str, buf, len);
1105 while ( rlen && str[rlen - 1] <= ' ' )
1106 rlen--;
1107 str[rlen] = 0;
1108 for ( p = str; *p && *p <= ' '; p++, rlen-- );
1109 if ( !*p )
1110 return 0;
1111
1112 // debugging feature for enter/leave showtime
1113 if ( strincmp(p, "enter", 5) == 0 && ifx_mei_atm_showtime_enter != NULL )
1114 ifx_mei_atm_showtime_enter(NULL, NULL);
1115 else if ( strincmp(p, "leave", 5) == 0 && ifx_mei_atm_showtime_exit != NULL )
1116 ifx_mei_atm_showtime_exit();
1117
1118 if ( strincmp(p, "enable", 6) == 0 ) {
1119 p += 6;
1120 f_enable = 1;
1121 }
1122 else if ( strincmp(p, "disable", 7) == 0 ) {
1123 p += 7;
1124 f_enable = -1;
1125 }
1126 else if ( strincmp(p, "help", 4) == 0 || *p == '?' ) {
1127 printk("echo <enable/disable> [err/dbg/assert/rx/tx/init/qos/swap/all] > /proc/driver/ifx_ptm/dbg\n");
1128 }
1129
1130 if ( f_enable ) {
1131 if ( *p == 0 ) {
1132 if ( f_enable > 0 )
1133 ifx_ptm_dbg_enable |= DBG_ENABLE_MASK_ALL & ~DBG_ENABLE_MASK_MAC_SWAP;
1134 else
1135 ifx_ptm_dbg_enable &= ~DBG_ENABLE_MASK_ALL | DBG_ENABLE_MASK_MAC_SWAP;
1136 }
1137 else {
1138 do {
1139 for ( i = 0; i < ARRAY_SIZE(dbg_enable_mask_str); i++ )
1140 if ( strincmp(p, dbg_enable_mask_str[i], dbg_enable_mask_str_len[i]) == 0 ) {
1141 if ( f_enable > 0 )
1142 ifx_ptm_dbg_enable |= dbg_enable_mask[i >> 1];
1143 else
1144 ifx_ptm_dbg_enable &= ~dbg_enable_mask[i >> 1];
1145 p += dbg_enable_mask_str_len[i];
1146 break;
1147 }
1148 } while ( i < ARRAY_SIZE(dbg_enable_mask_str) );
1149 }
1150 }
1151
1152 return count;
1153 }
1154
1155 #endif // defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1156
1157 static INLINE int stricmp(const char *p1, const char *p2)
1158 {
1159 int c1, c2;
1160
1161 while ( *p1 && *p2 )
1162 {
1163 c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;
1164 c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;
1165 if ( (c1 -= c2) )
1166 return c1;
1167 p1++;
1168 p2++;
1169 }
1170
1171 return *p1 - *p2;
1172 }
1173
1174 #if defined(ENABLE_DBG_PROC) && ENABLE_DBG_PROC
1175 static INLINE int strincmp(const char *p1, const char *p2, int n)
1176 {
1177 int c1 = 0, c2;
1178
1179 while ( n && *p1 && *p2 )
1180 {
1181 c1 = *p1 >= 'A' && *p1 <= 'Z' ? *p1 + 'a' - 'A' : *p1;
1182 c2 = *p2 >= 'A' && *p2 <= 'Z' ? *p2 + 'a' - 'A' : *p2;
1183 if ( (c1 -= c2) )
1184 return c1;
1185 p1++;
1186 p2++;
1187 n--;
1188 }
1189
1190 return n ? *p1 - *p2 : c1;
1191 }
1192 #endif
1193
1194 static INLINE int ifx_ptm_version(char *buf)
1195 {
1196 int len = 0;
1197 unsigned int major, minor;
1198
1199 ifx_ptm_get_fw_ver(&major, &minor);
1200
1201 len += sprintf(buf + len, "PTM %d.%d.%d", IFX_PTM_VER_MAJOR, IFX_PTM_VER_MID, IFX_PTM_VER_MINOR);
1202 len += sprintf(buf + len, " PTM (E1) firmware version %d.%d\n", major, minor);
1203
1204 return len;
1205 }
1206
1207 static INLINE void check_parameters(void)
1208 {
1209 /* There is a delay between PPE write descriptor and descriptor is */
1210 /* really stored in memory. Host also has this delay when writing */
1211 /* descriptor. So PPE will use this value to determine if the write */
1212 /* operation makes effect. */
1213 if ( write_desc_delay < 0 )
1214 write_desc_delay = 0;
1215
1216 /* Because of the limitation of length field in descriptors, the packet */
1217 /* size could not be larger than 64K minus overhead size. */
1218 if ( rx_max_packet_size < ETH_MIN_FRAME_LENGTH )
1219 rx_max_packet_size = ETH_MIN_FRAME_LENGTH;
1220 else if ( rx_max_packet_size > 65536 - 1 )
1221 rx_max_packet_size = 65536 - 1;
1222
1223 if ( dma_rx_descriptor_length < 2 )
1224 dma_rx_descriptor_length = 2;
1225 if ( dma_tx_descriptor_length < 2 )
1226 dma_tx_descriptor_length = 2;
1227 }
1228
1229 static INLINE int init_priv_data(void)
1230 {
1231 void *p;
1232 int i;
1233 struct rx_descriptor rx_desc = {0};
1234 struct sk_buff *skb;
1235 volatile struct rx_descriptor *p_rx_desc;
1236 volatile struct tx_descriptor *p_tx_desc;
1237 struct sk_buff **ppskb;
1238
1239 // clear ptm private data structure
1240 memset(&g_ptm_priv_data, 0, sizeof(g_ptm_priv_data));
1241
1242 // allocate memory for RX descriptors
1243 p = kzalloc(MAX_ITF_NUMBER * dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1244 if ( p == NULL )
1245 return -1;
1246 dma_cache_inv((unsigned long)p, MAX_ITF_NUMBER * dma_rx_descriptor_length * sizeof(struct rx_descriptor) + DESC_ALIGNMENT);
1247 g_ptm_priv_data.rx_desc_base = p;
1248 //p = (void *)((((unsigned int)p + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1249
1250 // allocate memory for TX descriptors
1251 p = kzalloc(MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT, GFP_KERNEL);
1252 if ( p == NULL )
1253 return -1;
1254 dma_cache_inv((unsigned long)p, MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct tx_descriptor) + DESC_ALIGNMENT);
1255 g_ptm_priv_data.tx_desc_base = p;
1256
1257 // allocate memroy for TX skb pointers
1258 p = kzalloc(MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4, GFP_KERNEL);
1259 if ( p == NULL )
1260 return -1;
1261 dma_cache_wback_inv((unsigned long)p, MAX_ITF_NUMBER * dma_tx_descriptor_length * sizeof(struct sk_buff *) + 4);
1262 g_ptm_priv_data.tx_skb_base = p;
1263
1264 p_rx_desc = (volatile struct rx_descriptor *)((((unsigned int)g_ptm_priv_data.rx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1265 p_tx_desc = (volatile struct tx_descriptor *)((((unsigned int)g_ptm_priv_data.tx_desc_base + DESC_ALIGNMENT - 1) & ~(DESC_ALIGNMENT - 1)) | KSEG1);
1266 ppskb = (struct sk_buff **)(((unsigned int)g_ptm_priv_data.tx_skb_base + 3) & ~3);
1267 for ( i = 0; i < MAX_ITF_NUMBER; i++ ) {
1268 g_ptm_priv_data.itf[i].rx_desc = &p_rx_desc[i * dma_rx_descriptor_length];
1269 g_ptm_priv_data.itf[i].tx_desc = &p_tx_desc[i * dma_tx_descriptor_length];
1270 g_ptm_priv_data.itf[i].tx_skb = &ppskb[i * dma_tx_descriptor_length];
1271 }
1272
1273 rx_desc.own = 1;
1274 rx_desc.c = 0;
1275 rx_desc.sop = 1;
1276 rx_desc.eop = 1;
1277 rx_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;
1278 rx_desc.id = 0;
1279 rx_desc.err = 0;
1280 rx_desc.datalen = rx_max_packet_size;
1281 for ( i = 0; i < MAX_ITF_NUMBER * dma_rx_descriptor_length; i++ ) {
1282 skb = alloc_skb_rx();
1283 if ( skb == NULL )
1284 return -1;
1285 rx_desc.dataptr = ((unsigned int)skb->data >> 2) & 0x0FFFFFFF;
1286 p_rx_desc[i] = rx_desc;
1287 }
1288
1289 return 0;
1290 }
1291
1292 static INLINE void clear_priv_data(void)
1293 {
1294 int i, j;
1295 struct sk_buff *skb;
1296
1297 for ( i = 0; i < MAX_ITF_NUMBER; i++ ) {
1298 if ( g_ptm_priv_data.itf[i].tx_skb != NULL ) {
1299 for ( j = 0; j < dma_tx_descriptor_length; j++ )
1300 if ( g_ptm_priv_data.itf[i].tx_skb[j] != NULL )
1301 dev_kfree_skb_any(g_ptm_priv_data.itf[i].tx_skb[j]);
1302 }
1303 if ( g_ptm_priv_data.itf[i].rx_desc != NULL ) {
1304 for ( j = 0; j < dma_rx_descriptor_length; j++ ) {
1305 if ( g_ptm_priv_data.itf[i].rx_desc[j].sop || g_ptm_priv_data.itf[i].rx_desc[j].eop ) { // descriptor initialized
1306 skb = get_skb_rx_pointer(g_ptm_priv_data.itf[i].rx_desc[j].dataptr);
1307 dev_kfree_skb_any(skb);
1308 }
1309 }
1310 }
1311 }
1312
1313 if ( g_ptm_priv_data.rx_desc_base != NULL )
1314 kfree(g_ptm_priv_data.rx_desc_base);
1315
1316 if ( g_ptm_priv_data.tx_desc_base != NULL )
1317 kfree(g_ptm_priv_data.tx_desc_base);
1318
1319 if ( g_ptm_priv_data.tx_skb_base != NULL )
1320 kfree(g_ptm_priv_data.tx_skb_base);
1321 }
1322
1323 static INLINE void init_tables(void)
1324 {
1325 int i;
1326 volatile unsigned int *p;
1327 struct wrx_dma_channel_config rx_config = {0};
1328 struct wtx_dma_channel_config tx_config = {0};
1329 struct wrx_port_cfg_status rx_port_cfg = { 0 };
1330 struct wtx_port_cfg tx_port_cfg = { 0 };
1331
1332 /*
1333 * CDM Block 1
1334 */
1335 IFX_REG_W32(CDM_CFG_RAM1_SET(0x00) | CDM_CFG_RAM0_SET(0x00), CDM_CFG); // CDM block 1 must be data memory and mapped to 0x5000 (dword addr)
1336 p = CDM_DATA_MEMORY(0, 0); // Clear CDM block 1
1337 for ( i = 0; i < CDM_DATA_MEMORY_DWLEN; i++, p++ )
1338 IFX_REG_W32(0, p);
1339
1340 /*
1341 * General Registers
1342 */
1343 IFX_REG_W32(write_desc_delay, CFG_WAN_WRDES_DELAY);
1344 IFX_REG_W32((1 << MAX_RX_DMA_CHANNEL_NUMBER) - 1, CFG_WRX_DMACH_ON);
1345 IFX_REG_W32((1 << MAX_TX_DMA_CHANNEL_NUMBER) - 1, CFG_WTX_DMACH_ON);
1346
1347 IFX_REG_W32(8, CFG_WRX_LOOK_BITTH); // WAN RX EFM-TC Looking Threshold
1348
1349 IFX_REG_W32(eth_efmtc_crc_cfg, CFG_ETH_EFMTC_CRC);
1350
1351 /*
1352 * WRX DMA Channel Configuration Table
1353 */
1354 rx_config.deslen = dma_rx_descriptor_length;
1355 rx_port_cfg.mfs = ETH_MAX_FRAME_LENGTH;
1356 rx_port_cfg.local_state = 0; // looking for sync
1357 rx_port_cfg.partner_state = 0; // parter receiver is out of sync
1358
1359 for ( i = 0; i < MAX_RX_DMA_CHANNEL_NUMBER; i++ ) {
1360 rx_config.desba = ((unsigned int)g_ptm_priv_data.itf[i].rx_desc >> 2) & 0x0FFFFFFF;
1361 *WRX_DMA_CHANNEL_CONFIG(i) = rx_config;
1362
1363 rx_port_cfg.dmach = i;
1364 *WRX_PORT_CONFIG(i) = rx_port_cfg;
1365 }
1366
1367 /*
1368 * WTX DMA Channel Configuration Table
1369 */
1370 tx_config.deslen = dma_tx_descriptor_length;
1371 tx_port_cfg.tx_cwth1 = 5;
1372 tx_port_cfg.tx_cwth2 = 4;
1373
1374 for ( i = 0; i < MAX_TX_DMA_CHANNEL_NUMBER; i++ ) {
1375 tx_config.desba = ((unsigned int)g_ptm_priv_data.itf[i].tx_desc >> 2) & 0x0FFFFFFF;
1376 *WTX_DMA_CHANNEL_CONFIG(i) = tx_config;
1377
1378 *WTX_PORT_CONFIG(i) = tx_port_cfg;
1379 }
1380 }
1381
1382
1383
1384 /*
1385 * ####################################
1386 * Global Function
1387 * ####################################
1388 */
1389
1390 static int ptm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
1391 {
1392 int i;
1393
1394 g_showtime = 1;
1395
1396 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
1397 netif_carrier_on(g_net_dev[i]);
1398
1399 printk("enter showtime\n");
1400
1401 return 0;
1402 }
1403
1404 static int ptm_showtime_exit(void)
1405 {
1406 int i;
1407
1408 if ( !g_showtime )
1409 return -1;
1410
1411 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
1412 netif_carrier_off(g_net_dev[i]);
1413
1414 g_showtime = 0;
1415
1416 printk("leave showtime\n");
1417
1418 return 0;
1419 }
1420
1421
1422
1423 /*
1424 * ####################################
1425 * Init/Cleanup API
1426 * ####################################
1427 */
1428
1429 /*
1430 * Description:
1431 * Initialize global variables, PP32, comunication structures, register IRQ
1432 * and register device.
1433 * Input:
1434 * none
1435 * Output:
1436 * 0 --- successful
1437 * else --- failure, usually it is negative value of error code
1438 */
1439 static int ifx_ptm_init(void)
1440 {
1441 int ret;
1442 struct port_cell_info port_cell = {0};
1443 void *xdata_addr = NULL;
1444 int i;
1445 char ver_str[256];
1446
1447 check_parameters();
1448
1449 ret = init_priv_data();
1450 if ( ret != 0 ) {
1451 err("INIT_PRIV_DATA_FAIL");
1452 goto INIT_PRIV_DATA_FAIL;
1453 }
1454
1455 ifx_ptm_init_chip();
1456 init_tables();
1457
1458 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
1459 g_net_dev[i] = alloc_netdev(0, g_net_dev_name[i], NET_NAME_UNKNOWN, ether_setup);
1460 if ( g_net_dev[i] == NULL )
1461 goto ALLOC_NETDEV_FAIL;
1462 ptm_setup(g_net_dev[i], i);
1463 }
1464
1465 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
1466 ret = register_netdev(g_net_dev[i]);
1467 if ( ret != 0 )
1468 goto REGISTER_NETDEV_FAIL;
1469 }
1470
1471 /* register interrupt handler */
1472 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,1,0)
1473 ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, 0, "ptm_mailbox_isr", &g_ptm_priv_data);
1474 #else
1475 ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "ptm_mailbox_isr", &g_ptm_priv_data);
1476 #endif
1477 if ( ret ) {
1478 if ( ret == -EBUSY ) {
1479 err("IRQ may be occupied by other driver, please reconfig to disable it.");
1480 }
1481 else {
1482 err("request_irq fail");
1483 }
1484 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
1485 }
1486 disable_irq(PPE_MAILBOX_IGU1_INT);
1487
1488 ret = ifx_pp32_start(0);
1489 if ( ret ) {
1490 err("ifx_pp32_start fail!");
1491 goto PP32_START_FAIL;
1492 }
1493 IFX_REG_W32(0, MBOX_IGU1_IER);
1494 IFX_REG_W32(~0, MBOX_IGU1_ISRC);
1495
1496 enable_irq(PPE_MAILBOX_IGU1_INT);
1497
1498
1499 proc_file_create();
1500
1501 port_cell.port_num = 1;
1502 ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &xdata_addr);
1503
1504 ifx_mei_atm_showtime_enter = ptm_showtime_enter;
1505 ifx_mei_atm_showtime_exit = ptm_showtime_exit;
1506
1507 ifx_ptm_version(ver_str);
1508 printk(KERN_INFO "%s", ver_str);
1509
1510 printk("ifxmips_ptm: PTM init succeed\n");
1511
1512 return 0;
1513
1514 PP32_START_FAIL:
1515 free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
1516 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1517 i = ARRAY_SIZE(g_net_dev);
1518 REGISTER_NETDEV_FAIL:
1519 while ( i-- )
1520 unregister_netdev(g_net_dev[i]);
1521 i = ARRAY_SIZE(g_net_dev);
1522 ALLOC_NETDEV_FAIL:
1523 while ( i-- ) {
1524 free_netdev(g_net_dev[i]);
1525 g_net_dev[i] = NULL;
1526 }
1527 INIT_PRIV_DATA_FAIL:
1528 clear_priv_data();
1529 printk("ifxmips_ptm: PTM init failed\n");
1530 return ret;
1531 }
1532
1533 /*
1534 * Description:
1535 * Release memory, free IRQ, and deregister device.
1536 * Input:
1537 * none
1538 * Output:
1539 * none
1540 */
1541 static void __exit ifx_ptm_exit(void)
1542 {
1543 int i;
1544
1545 ifx_mei_atm_showtime_enter = NULL;
1546 ifx_mei_atm_showtime_exit = NULL;
1547
1548 proc_file_delete();
1549
1550
1551 ifx_pp32_stop(0);
1552
1553 free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
1554
1555 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
1556 unregister_netdev(g_net_dev[i]);
1557
1558 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
1559 free_netdev(g_net_dev[i]);
1560 g_net_dev[i] = NULL;
1561 }
1562
1563 ifx_ptm_uninit_chip();
1564
1565 clear_priv_data();
1566 }
1567
1568 module_init(ifx_ptm_init);
1569 module_exit(ifx_ptm_exit);
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