package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ppe_ar9.h

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_ptm_ppe_ar9.h
   4 ** PROJECT      : UEIP
   5 ** MODULES      : PTM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : PTM driver header file (PPE register for AR9)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 #ifndef IFXMIPS_PTM_PPE_AR9_H
  27 #define IFXMIPS_PTM_PPE_AR9_H
  28
  29
  30
  31 /*
  32  *  FPI Configuration Bus Register and Memory Address Mapping
  33  */
  34 #define IFX_PPE                         (KSEG1 | 0x1E180000)
  35 #define PP32_DEBUG_REG_ADDR(i, x)       ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0000) << 2)))
  36 #define PPM_INT_REG_ADDR(i, x)          ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0030) << 2)))
  37 #define PP32_INTERNAL_RES_ADDR(i, x)    ((volatile unsigned int*)(IFX_PPE + (((x) + 0x0040) << 2)))
  38 #define CDM_CODE_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x1000) << 2)))
  39 #define PPE_REG_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x4000) << 2)))
  40 #define CDM_DATA_MEMORY(i, x)           ((volatile unsigned int*)(IFX_PPE + (((x) + 0x5000) << 2)))
  41 #define PPM_INT_UNIT_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6000) << 2)))
  42 #define PPM_TIMER0_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6100) << 2)))
  43 #define PPM_TASK_IND_REG_ADDR(x)        ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6200) << 2)))
  44 #define PPS_BRK_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6300) << 2)))
  45 #define PPM_TIMER1_ADDR(x)              ((volatile unsigned int*)(IFX_PPE + (((x) + 0x6400) << 2)))
  46 #define SB_RAM0_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8000) << 2)))
  47 #define SB_RAM1_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x8800) << 2)))
  48 #define SB_RAM2_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9000) << 2)))
  49 #define SB_RAM3_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0x9800) << 2)))
  50 #define SB_RAM4_ADDR(x)                 ((volatile unsigned int*)(IFX_PPE + (((x) + 0xA000) << 2)))
  51 #define QSB_CONF_REG_ADDR(x)            ((volatile unsigned int*)(IFX_PPE + (((x) + 0xC000) << 2)))
  52
  53 /*
  54  *  DWORD-Length of Memory Blocks
  55  */
  56 #define PP32_DEBUG_REG_DWLEN            0x0030
  57 #define PPM_INT_REG_DWLEN               0x0010
  58 #define PP32_INTERNAL_RES_DWLEN         0x00C0
  59 #define CDM_CODE_MEMORYn_DWLEN(n)       0x1000
  60 #define PPE_REG_DWLEN                   0x1000
  61 #define CDM_DATA_MEMORY_DWLEN           CDM_CODE_MEMORYn_DWLEN(1)
  62 #define PPM_INT_UNIT_DWLEN              0x0100
  63 #define PPM_TIMER0_DWLEN                0x0100
  64 #define PPM_TASK_IND_REG_DWLEN          0x0100
  65 #define PPS_BRK_DWLEN                   0x0100
  66 #define PPM_TIMER1_DWLEN                0x0100
  67 #define SB_RAM0_DWLEN                   0x0800
  68 #define SB_RAM1_DWLEN                   0x0800
  69 #define SB_RAM2_DWLEN                   0x0800
  70 #define SB_RAM3_DWLEN                   0x0800
  71 #define SB_RAM4_DWLEN                   0x0C00
  72 #define QSB_CONF_REG_DWLEN              0x0100
  73
  74 /*
  75  *  PP32 to FPI Address Mapping
  76  */
  77 #define SB_BUFFER(__sb_addr)            ((volatile unsigned int *)((((__sb_addr) >= 0x0000) && ((__sb_addr) <= 0x0FFF)) ? PP32_DEBUG_REG_ADDR(0, (__sb_addr)):   \
  78                                                                    (((__sb_addr) >= 0x2000) && ((__sb_addr) <= 0x27FF)) ? SB_RAM0_ADDR((__sb_addr) - 0x2000) :   \
  79                                                                    (((__sb_addr) >= 0x2800) && ((__sb_addr) <= 0x2FFF)) ? SB_RAM1_ADDR((__sb_addr) - 0x2800) :   \
  80                                                                    (((__sb_addr) >= 0x3000) && ((__sb_addr) <= 0x37FF)) ? SB_RAM2_ADDR((__sb_addr) - 0x3000) :   \
  81                                                                    (((__sb_addr) >= 0x3800) && ((__sb_addr) <= 0x3FFF)) ? SB_RAM3_ADDR((__sb_addr) - 0x3800) :   \
  82                                                                    (((__sb_addr) >= 0x4000) && ((__sb_addr) <= 0x4BFF)) ? SB_RAM4_ADDR((__sb_addr) - 0x4000) :   \
  83                                                                 0))
  84
  85 /*
  86  *  PP32 Debug Control Register
  87  */
  88 #define NUM_OF_PP32                             1
  89
  90 #define PP32_DBG_CTRL(n)                        PP32_DEBUG_REG_ADDR(n, 0x0000)
  91
  92 #define DBG_CTRL_RESTART                        0
  93 #define DBG_CTRL_STOP                           1
  94
  95 #define PP32_CTRL_CMD(n)                        PP32_DEBUG_REG_ADDR(n, 0x0B00)
  96   #define PP32_CTRL_CMD_RESTART                 (1 << 0)
  97   #define PP32_CTRL_CMD_STOP                    (1 << 1)
  98   #define PP32_CTRL_CMD_STEP                    (1 << 2)
  99   #define PP32_CTRL_CMD_BREAKOUT                (1 << 3)
 100
 101 #define PP32_CTRL_OPT(n)                        PP32_DEBUG_REG_ADDR(n, 0x0C00)
 102   #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_ON     (3 << 0)
 103   #define PP32_CTRL_OPT_BREAKOUT_ON_STOP_OFF    (2 << 0)
 104   #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_ON  (3 << 2)
 105   #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN_OFF (2 << 2)
 106   #define PP32_CTRL_OPT_STOP_ON_BREAKIN_ON      (3 << 4)
 107   #define PP32_CTRL_OPT_STOP_ON_BREAKIN_OFF     (2 << 4)
 108   #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_ON   (3 << 6)
 109   #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT_OFF  (2 << 6)
 110   #define PP32_CTRL_OPT_BREAKOUT_ON_STOP(n)     (*PP32_CTRL_OPT(n) & (1 << 0))
 111   #define PP32_CTRL_OPT_BREAKOUT_ON_BREAKIN(n)  (*PP32_CTRL_OPT(n) & (1 << 2))
 112   #define PP32_CTRL_OPT_STOP_ON_BREAKIN(n)      (*PP32_CTRL_OPT(n) & (1 << 4))
 113   #define PP32_CTRL_OPT_STOP_ON_BREAKPOINT(n)   (*PP32_CTRL_OPT(n) & (1 << 6))
 114
 115 #define PP32_BRK_PC(n, i)                       PP32_DEBUG_REG_ADDR(n, 0x0900 + (i) * 2)
 116 #define PP32_BRK_PC_MASK(n, i)                  PP32_DEBUG_REG_ADDR(n, 0x0901 + (i) * 2)
 117 #define PP32_BRK_DATA_ADDR(n, i)                PP32_DEBUG_REG_ADDR(n, 0x0904 + (i) * 2)
 118 #define PP32_BRK_DATA_ADDR_MASK(n, i)           PP32_DEBUG_REG_ADDR(n, 0x0905 + (i) * 2)
 119 #define PP32_BRK_DATA_VALUE_RD(n, i)            PP32_DEBUG_REG_ADDR(n, 0x0908 + (i) * 2)
 120 #define PP32_BRK_DATA_VALUE_RD_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x0909 + (i) * 2)
 121 #define PP32_BRK_DATA_VALUE_WR(n, i)            PP32_DEBUG_REG_ADDR(n, 0x090C + (i) * 2)
 122 #define PP32_BRK_DATA_VALUE_WR_MASK(n, i)       PP32_DEBUG_REG_ADDR(n, 0x090D + (i) * 2)
 123   #define PP32_BRK_CONTEXT_MASK(i)              (1 << (i))
 124   #define PP32_BRK_CONTEXT_MASK_EN              (1 << 4)
 125   #define PP32_BRK_COMPARE_GREATER_EQUAL        (1 << 5)    //  valid for break data value rd/wr only
 126   #define PP32_BRK_COMPARE_LOWER_EQUAL          (1 << 6)
 127   #define PP32_BRK_COMPARE_EN                   (1 << 7)
 128
 129 #define PP32_BRK_TRIG(n)                        PP32_DEBUG_REG_ADDR(n, 0x0F00)
 130   #define PP32_BRK_GRPi_PCn_ON(i, n)            ((3 << ((n) * 2)) << ((i) * 16))
 131   #define PP32_BRK_GRPi_PCn_OFF(i, n)           ((2 << ((n) * 2)) << ((i) * 16))
 132   #define PP32_BRK_GRPi_DATA_ADDRn_ON(i, n)     ((3 << ((n) * 2 + 4)) << ((i) * 16))
 133   #define PP32_BRK_GRPi_DATA_ADDRn_OFF(i, n)    ((2 << ((n) * 2 + 4)) << ((i) * 16))
 134   #define PP32_BRK_GRPi_DATA_VALUE_RDn_ON(i, n) ((3 << ((n) * 2 + 8)) << ((i) * 16))
 135   #define PP32_BRK_GRPi_DATA_VALUE_RDn_OFF(i, n)((2 << ((n) * 2 + 8)) << ((i) * 16))
 136   #define PP32_BRK_GRPi_DATA_VALUE_WRn_ON(i, n) ((3 << ((n) * 2 + 12)) << ((i) * 16))
 137   #define PP32_BRK_GRPi_DATA_VALUE_WRn_OFF(i, n)((2 << ((n) * 2 + 12)) << ((i) * 16))
 138   #define PP32_BRK_GRPi_PCn(k, i, n)            (*PP32_BRK_TRIG(k) & ((1 << ((n))) << ((i) * 8)))
 139   #define PP32_BRK_GRPi_DATA_ADDRn(k, i, n)     (*PP32_BRK_TRIG(k) & ((1 << ((n) + 2)) << ((i) * 8)))
 140   #define PP32_BRK_GRPi_DATA_VALUE_RDn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 4)) << ((i) * 8)))
 141   #define PP32_BRK_GRPi_DATA_VALUE_WRn(k, i, n) (*PP32_BRK_TRIG(k) & ((1 << ((n) + 6)) << ((i) * 8)))
 142
 143 #define PP32_CPU_STATUS(n)                      PP32_DEBUG_REG_ADDR(n, 0x0D00)
 144 #define PP32_HALT_STAT(n)                       PP32_CPU_STATUS(n)
 145 #define PP32_DBG_CUR_PC(n)                      PP32_CPU_STATUS(n)
 146   #define PP32_CPU_USER_STOPPED(n)              (*PP32_CPU_STATUS(n) & (1 << 0))
 147   #define PP32_CPU_USER_BREAKIN_RCV(n)          (*PP32_CPU_STATUS(n) & (1 << 1))
 148   #define PP32_CPU_USER_BREAKPOINT_MET(n)       (*PP32_CPU_STATUS(n) & (1 << 2))
 149   #define PP32_CPU_CUR_PC(n)                    (*PP32_CPU_STATUS(n) >> 16)
 150
 151 #define PP32_BREAKPOINT_REASONS(n)              PP32_DEBUG_REG_ADDR(n, 0x0A00)
 152   #define PP32_BRK_PC_MET(n, i)                 (*PP32_BREAKPOINT_REASONS(n) & (1 << (i)))
 153   #define PP32_BRK_DATA_ADDR_MET(n, i)          (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 2)))
 154   #define PP32_BRK_DATA_VALUE_RD_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 4)))
 155   #define PP32_BRK_DATA_VALUE_WR_MET(n, i)      (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) + 6)))
 156   #define PP32_BRK_DATA_VALUE_RD_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 8)))
 157   #define PP32_BRK_DATA_VALUE_RD_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 9)))
 158   #define PP32_BRK_DATA_VALUE_WR_LO_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 12)))
 159   #define PP32_BRK_DATA_VALUE_WR_GT_EQ(n, i)    (*PP32_BREAKPOINT_REASONS(n) & (1 << ((i) * 2 + 13)))
 160   #define PP32_BRK_CUR_CONTEXT(n)               ((*PP32_BREAKPOINT_REASONS(n) >> 16) & 0x03)
 161
 162 #define PP32_GP_REG_BASE(n)                     PP32_DEBUG_REG_ADDR(n, 0x0E00)
 163 #define PP32_GP_CONTEXTi_REGn(n, i, j)          PP32_DEBUG_REG_ADDR(n, 0x0E00 + (i) * 16 + (j))
 164
 165 /*
 166  *  Share Buffer Registers
 167  */
 168 #define SB_MST_PRI0                     PPE_REG_ADDR(0x0300)
 169 #define SB_MST_PRI1                     PPE_REG_ADDR(0x0301)
 170
 171 /*
 172  *  EMA Registers
 173  */
 174 #define EMA_CMDCFG                      PPE_REG_ADDR(0x0A00)
 175 #define EMA_DATACFG                     PPE_REG_ADDR(0x0A01)
 176 #define EMA_CMDCNT                      PPE_REG_ADDR(0x0A02)
 177 #define EMA_DATACNT                     PPE_REG_ADDR(0x0A03)
 178 #define EMA_ISR                         PPE_REG_ADDR(0x0A04)
 179 #define EMA_IER                         PPE_REG_ADDR(0x0A05)
 180 #define EMA_CFG                         PPE_REG_ADDR(0x0A06)
 181 #define EMA_SUBID                       PPE_REG_ADDR(0x0A07)
 182
 183 #define EMA_ALIGNMENT                   4
 184
 185 /*
 186  *  DPlus Registers
 187  */
 188 #define DM_RXDB                         PPE_REG_ADDR(0x0612)
 189 #define DM_RXCB                         PPE_REG_ADDR(0x0613)
 190 #define DM_RXCFG                        PPE_REG_ADDR(0x0614)
 191 #define DM_RXPGCNT                      PPE_REG_ADDR(0x0615)
 192 #define DM_RXPKTCNT                     PPE_REG_ADDR(0x0616)
 193 #define DS_RXDB                         PPE_REG_ADDR(0x0710)
 194 #define DS_RXCB                         PPE_REG_ADDR(0x0711)
 195 #define DS_RXCFG                        PPE_REG_ADDR(0x0712)
 196 #define DS_RXPGCNT                      PPE_REG_ADDR(0x0713)
 197
 198 /*
 199  *  3-Port Switch Registers (partial)
 200  */
 201 #define IFX_SW                          (KSEG1 | 0x1E108000)
 202 #define SW_REG(off)                     ((volatile unsigned int*)(IFX_SW + (off)))
 203 #define SW_P2_CTL                       SW_REG(0x00C)
 204
 205
 206 /*
 207  *  Mailbox IGU1 Interrupt
 208  */
 209 #define PPE_MAILBOX_IGU1_INT            INT_NUM_IM2_IRL24
 210
 211
 212
 213 #endif  //  IFXMIPS_PTM_PPE_AR9_H