lantiq: fix dsl drivers for 3.18
[openwrt/openwrt.git] / package / kernel / lantiq / ltq-ptm / src / ifxmips_ptm_vdsl.c
1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_ptm_vdsl.c
4 ** PROJECT : UEIP
5 ** MODULES : PTM
6 **
7 ** DATE : 7 Jul 2009
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : PTM driver common source file (core functions for VR9)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
23
24 #include <linux/version.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/ctype.h>
29 #include <linux/errno.h>
30 #include <linux/proc_fs.h>
31 #include <linux/init.h>
32 #include <linux/ioctl.h>
33 #include <linux/etherdevice.h>
34 #include <linux/interrupt.h>
35
36 #include "ifxmips_ptm_vdsl.h"
37 #include <lantiq_soc.h>
38
39 #define MODULE_PARM_ARRAY(a, b) module_param_array(a, int, NULL, 0)
40 #define MODULE_PARM(a, b) module_param(a, int, 0)
41
42 static int wanqos_en = 0;
43 static int queue_gamma_map[4] = {0xFE, 0x01, 0x00, 0x00};
44
45 MODULE_PARM(wanqos_en, "i");
46 MODULE_PARM_DESC(wanqos_en, "WAN QoS support, 1 - enabled, 0 - disabled.");
47
48 MODULE_PARM_ARRAY(queue_gamma_map, "4-4i");
49 MODULE_PARM_DESC(queue_gamma_map, "TX QoS queues mapping to 4 TX Gamma interfaces.");
50
51 extern int (*ifx_mei_atm_showtime_enter)(struct port_cell_info *, void *);
52 extern int (*ifx_mei_atm_showtime_exit)(void);
53 extern int ifx_mei_atm_showtime_check(int *is_showtime, struct port_cell_info *port_cell, void **xdata_addr);
54
55 static int g_showtime = 0;
56 static void *g_xdata_addr = NULL;
57
58
59 #define ENABLE_TMP_DBG 0
60
61 unsigned long cgu_get_pp32_clock(void)
62 {
63 struct clk *c = clk_get_ppe();
64 unsigned long rate = clk_get_rate(c);
65 clk_put(c);
66 return rate;
67 }
68
69 static void ptm_setup(struct net_device *);
70 static struct net_device_stats *ptm_get_stats(struct net_device *);
71 static int ptm_open(struct net_device *);
72 static int ptm_stop(struct net_device *);
73 static unsigned int ptm_poll(int, unsigned int);
74 static int ptm_napi_poll(struct napi_struct *, int);
75 static int ptm_hard_start_xmit(struct sk_buff *, struct net_device *);
76 static int ptm_ioctl(struct net_device *, struct ifreq *, int);
77 static void ptm_tx_timeout(struct net_device *);
78
79 static inline struct sk_buff* alloc_skb_rx(void);
80 static inline struct sk_buff* alloc_skb_tx(unsigned int);
81 static inline struct sk_buff *get_skb_pointer(unsigned int);
82 static inline int get_tx_desc(unsigned int, unsigned int *);
83
84 /*
85 * Mailbox handler and signal function
86 */
87 static irqreturn_t mailbox_irq_handler(int, void *);
88
89 /*
90 * Tasklet to Handle Swap Descriptors
91 */
92 static void do_swap_desc_tasklet(unsigned long);
93
94
95 /*
96 * Init & clean-up functions
97 */
98 static inline int init_priv_data(void);
99 static inline void clear_priv_data(void);
100 static inline int init_tables(void);
101 static inline void clear_tables(void);
102
103 static int g_wanqos_en = 0;
104
105 static int g_queue_gamma_map[4];
106
107 static struct ptm_priv_data g_ptm_priv_data;
108
109 static struct net_device_ops g_ptm_netdev_ops = {
110 .ndo_get_stats = ptm_get_stats,
111 .ndo_open = ptm_open,
112 .ndo_stop = ptm_stop,
113 .ndo_start_xmit = ptm_hard_start_xmit,
114 .ndo_validate_addr = eth_validate_addr,
115 .ndo_set_mac_address = eth_mac_addr,
116 .ndo_change_mtu = eth_change_mtu,
117 .ndo_do_ioctl = ptm_ioctl,
118 .ndo_tx_timeout = ptm_tx_timeout,
119 };
120
121 static struct net_device *g_net_dev[1] = {0};
122 static char *g_net_dev_name[1] = {"ptm0"};
123
124 static int g_ptm_prio_queue_map[8];
125
126 static DECLARE_TASKLET(g_swap_desc_tasklet, do_swap_desc_tasklet, 0);
127
128
129 unsigned int ifx_ptm_dbg_enable = DBG_ENABLE_MASK_ERR;
130
131 /*
132 * ####################################
133 * Local Function
134 * ####################################
135 */
136
137 static void ptm_setup(struct net_device *dev)
138 {
139 int ndev = 0;
140 dev->netdev_ops = &g_ptm_netdev_ops;
141 netif_napi_add(dev, &g_ptm_priv_data.itf[ndev].napi, ptm_napi_poll, 16);
142 dev->watchdog_timeo = ETH_WATCHDOG_TIMEOUT;
143
144 dev->dev_addr[0] = 0x00;
145 dev->dev_addr[1] = 0x20;
146 dev->dev_addr[2] = 0xda;
147 dev->dev_addr[3] = 0x86;
148 dev->dev_addr[4] = 0x23;
149 dev->dev_addr[5] = 0x75 + ndev;
150 }
151
152 static struct net_device_stats *ptm_get_stats(struct net_device *dev)
153 {
154 struct net_device_stats *s;
155
156 if ( dev != g_net_dev[0] )
157 return NULL;
158 s = &g_ptm_priv_data.itf[0].stats;
159
160 return s;
161 }
162
163 static int ptm_open(struct net_device *dev)
164 {
165 ASSERT(dev == g_net_dev[0], "incorrect device");
166
167 napi_enable(&g_ptm_priv_data.itf[0].napi);
168
169 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_IER);
170
171 netif_start_queue(dev);
172
173 return 0;
174 }
175
176 static int ptm_stop(struct net_device *dev)
177 {
178 ASSERT(dev == g_net_dev[0], "incorrect device");
179
180 IFX_REG_W32_MASK(1 | (1 << 17), 0, MBOX_IGU1_IER);
181
182 napi_disable(&g_ptm_priv_data.itf[0].napi);
183
184 netif_stop_queue(dev);
185
186 return 0;
187 }
188
189 static unsigned int ptm_poll(int ndev, unsigned int work_to_do)
190 {
191 unsigned int work_done = 0;
192 volatile struct rx_descriptor *desc;
193 struct rx_descriptor reg_desc;
194 struct sk_buff *skb, *new_skb;
195
196 ASSERT(ndev >= 0 && ndev < ARRAY_SIZE(g_net_dev), "ndev = %d (wrong value)", ndev);
197
198 while ( work_done < work_to_do ) {
199 desc = &WAN_RX_DESC_BASE[g_ptm_priv_data.itf[0].rx_desc_pos];
200 if ( desc->own /* || !desc->c */ ) // if PP32 hold descriptor or descriptor not completed
201 break;
202 if ( ++g_ptm_priv_data.itf[0].rx_desc_pos == WAN_RX_DESC_NUM )
203 g_ptm_priv_data.itf[0].rx_desc_pos = 0;
204
205 reg_desc = *desc;
206 skb = get_skb_pointer(reg_desc.dataptr);
207 ASSERT(skb != NULL, "invalid pointer skb == NULL");
208
209 new_skb = alloc_skb_rx();
210 if ( new_skb != NULL ) {
211 skb_reserve(skb, reg_desc.byteoff);
212 skb_put(skb, reg_desc.datalen);
213
214 // parse protocol header
215 skb->dev = g_net_dev[0];
216 skb->protocol = eth_type_trans(skb, skb->dev);
217
218 g_net_dev[0]->last_rx = jiffies;
219
220 netif_receive_skb(skb);
221
222 g_ptm_priv_data.itf[0].stats.rx_packets++;
223 g_ptm_priv_data.itf[0].stats.rx_bytes += reg_desc.datalen;
224
225 reg_desc.dataptr = (unsigned int)new_skb->data & 0x0FFFFFFF;
226 reg_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;
227 }
228
229 reg_desc.datalen = RX_MAX_BUFFER_SIZE - RX_HEAD_MAC_ADDR_ALIGNMENT;
230 reg_desc.own = 1;
231 reg_desc.c = 0;
232
233 /* write discriptor to memory */
234 *((volatile unsigned int *)desc + 1) = *((unsigned int *)&reg_desc + 1);
235 wmb();
236 *(volatile unsigned int *)desc = *(unsigned int *)&reg_desc;
237
238 work_done++;
239 }
240
241 return work_done;
242 }
243
244 static int ptm_napi_poll(struct napi_struct *napi, int budget)
245 {
246 int ndev = 0;
247 unsigned int work_done;
248
249 work_done = ptm_poll(ndev, budget);
250
251 // interface down
252 if ( !netif_running(napi->dev) ) {
253 napi_complete(napi);
254 return work_done;
255 }
256
257 // clear interrupt
258 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_ISRC);
259 // no more traffic
260 if (work_done < budget) {
261 napi_complete(napi);
262 IFX_REG_W32_MASK(0, 1, MBOX_IGU1_IER);
263 return work_done;
264 }
265
266 // next round
267 return work_done;
268 }
269
270 static int ptm_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
271 {
272 unsigned int f_full;
273 int desc_base;
274 volatile struct tx_descriptor *desc;
275 struct tx_descriptor reg_desc = {0};
276 struct sk_buff *skb_to_free;
277 unsigned int byteoff;
278
279 ASSERT(dev == g_net_dev[0], "incorrect device");
280
281 if ( !g_showtime ) {
282 err("not in showtime");
283 goto PTM_HARD_START_XMIT_FAIL;
284 }
285
286 /* allocate descriptor */
287 desc_base = get_tx_desc(0, &f_full);
288 if ( f_full ) {
289 dev->trans_start = jiffies;
290 netif_stop_queue(dev);
291
292 IFX_REG_W32_MASK(0, 1 << 17, MBOX_IGU1_ISRC);
293 IFX_REG_W32_MASK(0, 1 << 17, MBOX_IGU1_IER);
294 }
295 if ( desc_base < 0 )
296 goto PTM_HARD_START_XMIT_FAIL;
297 desc = &CPU_TO_WAN_TX_DESC_BASE[desc_base];
298
299 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
300 if ( skb_headroom(skb) < sizeof(struct sk_buff *) + byteoff || skb_cloned(skb) ) {
301 struct sk_buff *new_skb;
302
303 ASSERT(skb_headroom(skb) >= sizeof(struct sk_buff *) + byteoff, "skb_headroom(skb) < sizeof(struct sk_buff *) + byteoff");
304 ASSERT(!skb_cloned(skb), "skb is cloned");
305
306 new_skb = alloc_skb_tx(skb->len);
307 if ( new_skb == NULL ) {
308 dbg("no memory");
309 goto ALLOC_SKB_TX_FAIL;
310 }
311 skb_put(new_skb, skb->len);
312 memcpy(new_skb->data, skb->data, skb->len);
313 dev_kfree_skb_any(skb);
314 skb = new_skb;
315 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
316 /* write back to physical memory */
317 dma_cache_wback((unsigned long)skb->data, skb->len);
318 }
319
320 *(struct sk_buff **)((unsigned int)skb->data - byteoff - sizeof(struct sk_buff *)) = skb;
321 /* write back to physical memory */
322 dma_cache_wback((unsigned long)skb->data - byteoff - sizeof(struct sk_buff *), skb->len + byteoff + sizeof(struct sk_buff *));
323
324 /* free previous skb */
325 skb_to_free = get_skb_pointer(desc->dataptr);
326 if ( skb_to_free != NULL )
327 dev_kfree_skb_any(skb_to_free);
328
329 /* update descriptor */
330 reg_desc.small = 0;
331 reg_desc.dataptr = (unsigned int)skb->data & (0x0FFFFFFF ^ (DATA_BUFFER_ALIGNMENT - 1));
332 reg_desc.datalen = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
333 reg_desc.qid = g_ptm_prio_queue_map[skb->priority > 7 ? 7 : skb->priority];
334 reg_desc.byteoff = byteoff;
335 reg_desc.own = 1;
336 reg_desc.c = 1;
337 reg_desc.sop = reg_desc.eop = 1;
338
339 /* update MIB */
340 g_ptm_priv_data.itf[0].stats.tx_packets++;
341 g_ptm_priv_data.itf[0].stats.tx_bytes += reg_desc.datalen;
342
343 /* write discriptor to memory */
344 *((volatile unsigned int *)desc + 1) = *((unsigned int *)&reg_desc + 1);
345 wmb();
346 *(volatile unsigned int *)desc = *(unsigned int *)&reg_desc;
347
348 dev->trans_start = jiffies;
349
350 return 0;
351
352 ALLOC_SKB_TX_FAIL:
353 PTM_HARD_START_XMIT_FAIL:
354 dev_kfree_skb_any(skb);
355 g_ptm_priv_data.itf[0].stats.tx_dropped++;
356 return 0;
357 }
358
359 static int ptm_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
360 {
361 ASSERT(dev == g_net_dev[0], "incorrect device");
362
363 switch ( cmd )
364 {
365 case IFX_PTM_MIB_CW_GET:
366 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxNoIdleCodewords = IFX_REG_R32(DREG_AR_CELL0) + IFX_REG_R32(DREG_AR_CELL1);
367 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxIdleCodewords = IFX_REG_R32(DREG_AR_IDLE_CNT0) + IFX_REG_R32(DREG_AR_IDLE_CNT1);
368 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifRxCodingViolation = IFX_REG_R32(DREG_AR_CVN_CNT0) + IFX_REG_R32(DREG_AR_CVN_CNT1) + IFX_REG_R32(DREG_AR_CVNP_CNT0) + IFX_REG_R32(DREG_AR_CVNP_CNT1);
369 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxNoIdleCodewords = IFX_REG_R32(DREG_AT_CELL0) + IFX_REG_R32(DREG_AT_CELL1);
370 ((PTM_CW_IF_ENTRY_T *)ifr->ifr_data)->ifTxIdleCodewords = IFX_REG_R32(DREG_AT_IDLE_CNT0) + IFX_REG_R32(DREG_AT_IDLE_CNT1);
371 break;
372 case IFX_PTM_MIB_FRAME_GET:
373 {
374 PTM_FRAME_MIB_T data = {0};
375 int i;
376
377 data.RxCorrect = IFX_REG_R32(DREG_AR_HEC_CNT0) + IFX_REG_R32(DREG_AR_HEC_CNT1) + IFX_REG_R32(DREG_AR_AIIDLE_CNT0) + IFX_REG_R32(DREG_AR_AIIDLE_CNT1);
378 for ( i = 0; i < 4; i++ )
379 data.RxDropped += WAN_RX_MIB_TABLE(i)->wrx_dropdes_pdu;
380 for ( i = 0; i < 8; i++ )
381 data.TxSend += WAN_TX_MIB_TABLE(i)->wtx_total_pdu;
382
383 *((PTM_FRAME_MIB_T *)ifr->ifr_data) = data;
384 }
385 break;
386 case IFX_PTM_CFG_GET:
387 // use bear channel 0 preemption gamma interface settings
388 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcPresent = 1;
389 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck = RX_GAMMA_ITF_CFG(0)->rx_eth_fcs_ver_dis == 0 ? 1 : 0;
390 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck = RX_GAMMA_ITF_CFG(0)->rx_tc_crc_ver_dis == 0 ? 1 : 0;;
391 ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen = RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size == 0 ? 0 : (RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size * 16);
392 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen = TX_GAMMA_ITF_CFG(0)->tx_eth_fcs_gen_dis == 0 ? 1 : 0;
393 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen = TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size == 0 ? 0 : 1;
394 ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen = TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size == 0 ? 0 : (TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size * 16);
395 break;
396 case IFX_PTM_CFG_SET:
397 {
398 int i;
399
400 for ( i = 0; i < 4; i++ ) {
401 RX_GAMMA_ITF_CFG(i)->rx_eth_fcs_ver_dis = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxEthCrcCheck ? 0 : 1;
402
403 RX_GAMMA_ITF_CFG(0)->rx_tc_crc_ver_dis = ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcCheck ? 0 : 1;
404
405 switch ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->RxTcCrcLen ) {
406 case 16: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size = 1; break;
407 case 32: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size = 2; break;
408 default: RX_GAMMA_ITF_CFG(0)->rx_tc_crc_size = 0;
409 }
410
411 TX_GAMMA_ITF_CFG(0)->tx_eth_fcs_gen_dis = ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxEthCrcGen ? 0 : 1;
412
413 if ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcGen ) {
414 switch ( ((IFX_PTM_CFG_T *)ifr->ifr_data)->TxTcCrcLen ) {
415 case 16: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 1; break;
416 case 32: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 2; break;
417 default: TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 0;
418 }
419 }
420 else
421 TX_GAMMA_ITF_CFG(0)->tx_tc_crc_size = 0;
422 }
423 }
424 break;
425 case IFX_PTM_MAP_PKT_PRIO_TO_Q:
426 {
427 struct ppe_prio_q_map cmd;
428
429 if ( copy_from_user(&cmd, ifr->ifr_data, sizeof(cmd)) )
430 return -EFAULT;
431
432 if ( cmd.pkt_prio < 0 || cmd.pkt_prio >= ARRAY_SIZE(g_ptm_prio_queue_map) )
433 return -EINVAL;
434
435 if ( cmd.qid < 0 || cmd.qid >= g_wanqos_en )
436 return -EINVAL;
437
438 g_ptm_prio_queue_map[cmd.pkt_prio] = cmd.qid;
439 }
440 break;
441 default:
442 return -EOPNOTSUPP;
443 }
444
445 return 0;
446 }
447
448 static void ptm_tx_timeout(struct net_device *dev)
449 {
450 ASSERT(dev == g_net_dev[0], "incorrect device");
451
452 /* disable TX irq, release skb when sending new packet */
453 IFX_REG_W32_MASK(1 << 17, 0, MBOX_IGU1_IER);
454
455 /* wake up TX queue */
456 netif_wake_queue(dev);
457
458 return;
459 }
460
461 static inline struct sk_buff* alloc_skb_rx(void)
462 {
463 struct sk_buff *skb;
464
465 /* allocate memroy including trailer and padding */
466 skb = dev_alloc_skb(RX_MAX_BUFFER_SIZE + DATA_BUFFER_ALIGNMENT);
467 if ( skb != NULL ) {
468 /* must be burst length alignment and reserve two more bytes for MAC address alignment */
469 if ( ((unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1)) != 0 )
470 skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
471 /* pub skb in reserved area "skb->data - 4" */
472 *((struct sk_buff **)skb->data - 1) = skb;
473 wmb();
474 /* write back and invalidate cache */
475 dma_cache_wback_inv((unsigned long)skb->data - sizeof(skb), sizeof(skb));
476 /* invalidate cache */
477 dma_cache_inv((unsigned long)skb->data, (unsigned int)skb->end - (unsigned int)skb->data);
478 }
479
480 return skb;
481 }
482
483 static inline struct sk_buff* alloc_skb_tx(unsigned int size)
484 {
485 struct sk_buff *skb;
486
487 /* allocate memory including padding */
488 size = RX_MAX_BUFFER_SIZE;
489 size = (size + DATA_BUFFER_ALIGNMENT - 1) & ~(DATA_BUFFER_ALIGNMENT - 1);
490 skb = dev_alloc_skb(size + DATA_BUFFER_ALIGNMENT);
491 /* must be burst length alignment */
492 if ( skb != NULL )
493 skb_reserve(skb, ~((unsigned int)skb->data + (DATA_BUFFER_ALIGNMENT - 1)) & (DATA_BUFFER_ALIGNMENT - 1));
494 return skb;
495 }
496
497 static inline struct sk_buff *get_skb_pointer(unsigned int dataptr)
498 {
499 unsigned int skb_dataptr;
500 struct sk_buff *skb;
501
502 // usually, CPE memory is less than 256M bytes
503 // so NULL means invalid pointer
504 if ( dataptr == 0 ) {
505 dbg("dataptr is 0, it's supposed to be invalid pointer");
506 return NULL;
507 }
508
509 skb_dataptr = (dataptr - 4) | KSEG1;
510 skb = *(struct sk_buff **)skb_dataptr;
511
512 ASSERT((unsigned int)skb >= KSEG0, "invalid skb - skb = %#08x, dataptr = %#08x", (unsigned int)skb, dataptr);
513 ASSERT((((unsigned int)skb->data & (0x0FFFFFFF ^ (DATA_BUFFER_ALIGNMENT - 1))) | KSEG1) == (dataptr | KSEG1), "invalid skb - skb = %#08x, skb->data = %#08x, dataptr = %#08x", (unsigned int)skb, (unsigned int)skb->data, dataptr);
514
515 return skb;
516 }
517
518 static inline int get_tx_desc(unsigned int itf, unsigned int *f_full)
519 {
520 int desc_base = -1;
521 struct ptm_itf *p_itf = &g_ptm_priv_data.itf[0];
522
523 // assume TX is serial operation
524 // no protection provided
525
526 *f_full = 1;
527
528 if ( CPU_TO_WAN_TX_DESC_BASE[p_itf->tx_desc_pos].own == 0 ) {
529 desc_base = p_itf->tx_desc_pos;
530 if ( ++(p_itf->tx_desc_pos) == CPU_TO_WAN_TX_DESC_NUM )
531 p_itf->tx_desc_pos = 0;
532 if ( CPU_TO_WAN_TX_DESC_BASE[p_itf->tx_desc_pos].own == 0 )
533 *f_full = 0;
534 }
535
536 return desc_base;
537 }
538
539 static irqreturn_t mailbox_irq_handler(int irq, void *dev_id)
540 {
541 unsigned int isr;
542 int i;
543
544 isr = IFX_REG_R32(MBOX_IGU1_ISR);
545 IFX_REG_W32(isr, MBOX_IGU1_ISRC);
546 isr &= IFX_REG_R32(MBOX_IGU1_IER);
547
548 if (isr & BIT(0)) {
549 IFX_REG_W32_MASK(1, 0, MBOX_IGU1_IER);
550 napi_schedule(&g_ptm_priv_data.itf[0].napi);
551 #if defined(ENABLE_TMP_DBG) && ENABLE_TMP_DBG
552 {
553 volatile struct rx_descriptor *desc = &WAN_RX_DESC_BASE[g_ptm_priv_data.itf[0].rx_desc_pos];
554
555 if ( desc->own ) { // PP32 hold
556 err("invalid interrupt");
557 }
558 }
559 #endif
560 }
561 if (isr & BIT(16)) {
562 IFX_REG_W32_MASK(1 << 16, 0, MBOX_IGU1_IER);
563 tasklet_hi_schedule(&g_swap_desc_tasklet);
564 }
565 if (isr & BIT(17)) {
566 IFX_REG_W32_MASK(1 << 17, 0, MBOX_IGU1_IER);
567 netif_wake_queue(g_net_dev[0]);
568 }
569
570 return IRQ_HANDLED;
571 }
572
573 static void do_swap_desc_tasklet(unsigned long arg)
574 {
575 int budget = 32;
576 volatile struct tx_descriptor *desc;
577 struct sk_buff *skb;
578 unsigned int byteoff;
579
580 while ( budget-- > 0 ) {
581 if ( WAN_SWAP_DESC_BASE[g_ptm_priv_data.itf[0].tx_swap_desc_pos].own ) // if PP32 hold descriptor
582 break;
583
584 desc = &WAN_SWAP_DESC_BASE[g_ptm_priv_data.itf[0].tx_swap_desc_pos];
585 if ( ++g_ptm_priv_data.itf[0].tx_swap_desc_pos == WAN_SWAP_DESC_NUM )
586 g_ptm_priv_data.itf[0].tx_swap_desc_pos = 0;
587
588 skb = get_skb_pointer(desc->dataptr);
589 if ( skb != NULL )
590 dev_kfree_skb_any(skb);
591
592 skb = alloc_skb_tx(RX_MAX_BUFFER_SIZE);
593 if ( skb == NULL )
594 panic("can't allocate swap buffer for PPE firmware use\n");
595 byteoff = (unsigned int)skb->data & (DATA_BUFFER_ALIGNMENT - 1);
596 *(struct sk_buff **)((unsigned int)skb->data - byteoff - sizeof(struct sk_buff *)) = skb;
597
598 desc->dataptr = (unsigned int)skb->data & 0x0FFFFFFF;
599 desc->own = 1;
600 }
601
602 // clear interrupt
603 IFX_REG_W32_MASK(0, 16, MBOX_IGU1_ISRC);
604 // no more skb to be replaced
605 if ( WAN_SWAP_DESC_BASE[g_ptm_priv_data.itf[0].tx_swap_desc_pos].own ) { // if PP32 hold descriptor
606 IFX_REG_W32_MASK(0, 1 << 16, MBOX_IGU1_IER);
607 return;
608 }
609
610 tasklet_hi_schedule(&g_swap_desc_tasklet);
611 return;
612 }
613
614
615 static inline int ifx_ptm_version(char *buf)
616 {
617 int len = 0;
618 unsigned int major, minor;
619
620 ifx_ptm_get_fw_ver(&major, &minor);
621
622 len += sprintf(buf + len, "PTM %d.%d.%d", IFX_PTM_VER_MAJOR, IFX_PTM_VER_MID, IFX_PTM_VER_MINOR);
623 len += sprintf(buf + len, " PTM (E1) firmware version %d.%d\n", major, minor);
624
625 return len;
626 }
627
628 static inline int init_priv_data(void)
629 {
630 int i, j;
631
632 g_wanqos_en = wanqos_en ? wanqos_en : 8;
633 if ( g_wanqos_en > 8 )
634 g_wanqos_en = 8;
635
636 for ( i = 0; i < ARRAY_SIZE(g_queue_gamma_map); i++ )
637 {
638 g_queue_gamma_map[i] = queue_gamma_map[i] & ((1 << g_wanqos_en) - 1);
639 for ( j = 0; j < i; j++ )
640 g_queue_gamma_map[i] &= ~g_queue_gamma_map[j];
641 }
642
643 memset(&g_ptm_priv_data, 0, sizeof(g_ptm_priv_data));
644
645 {
646 int max_packet_priority = ARRAY_SIZE(g_ptm_prio_queue_map);
647 int tx_num_q;
648 int q_step, q_accum, p_step;
649
650 tx_num_q = __ETH_WAN_TX_QUEUE_NUM;
651 q_step = tx_num_q - 1;
652 p_step = max_packet_priority - 1;
653 for ( j = 0, q_accum = 0; j < max_packet_priority; j++, q_accum += q_step )
654 g_ptm_prio_queue_map[j] = q_step - (q_accum + (p_step >> 1)) / p_step;
655 }
656
657 return 0;
658 }
659
660 static inline void clear_priv_data(void)
661 {
662 }
663
664 static inline int init_tables(void)
665 {
666 struct sk_buff *skb_pool[WAN_RX_DESC_NUM] = {0};
667 struct cfg_std_data_len cfg_std_data_len = {0};
668 struct tx_qos_cfg tx_qos_cfg = {0};
669 struct psave_cfg psave_cfg = {0};
670 struct eg_bwctrl_cfg eg_bwctrl_cfg = {0};
671 struct test_mode test_mode = {0};
672 struct rx_bc_cfg rx_bc_cfg = {0};
673 struct tx_bc_cfg tx_bc_cfg = {0};
674 struct gpio_mode gpio_mode = {0};
675 struct gpio_wm_cfg gpio_wm_cfg = {0};
676 struct rx_gamma_itf_cfg rx_gamma_itf_cfg = {0};
677 struct tx_gamma_itf_cfg tx_gamma_itf_cfg = {0};
678 struct wtx_qos_q_desc_cfg wtx_qos_q_desc_cfg = {0};
679 struct rx_descriptor rx_desc = {0};
680 struct tx_descriptor tx_desc = {0};
681 int i;
682
683 for ( i = 0; i < WAN_RX_DESC_NUM; i++ ) {
684 skb_pool[i] = alloc_skb_rx();
685 if ( skb_pool[i] == NULL )
686 goto ALLOC_SKB_RX_FAIL;
687 }
688
689 cfg_std_data_len.byte_off = RX_HEAD_MAC_ADDR_ALIGNMENT; // this field replaces byte_off in rx descriptor of VDSL ingress
690 cfg_std_data_len.data_len = 1600;
691 *CFG_STD_DATA_LEN = cfg_std_data_len;
692
693 tx_qos_cfg.time_tick = cgu_get_pp32_clock() / 62500; // 16 * (cgu_get_pp32_clock() / 1000000)
694 tx_qos_cfg.overhd_bytes = 0;
695 tx_qos_cfg.eth1_eg_qnum = __ETH_WAN_TX_QUEUE_NUM;
696 tx_qos_cfg.eth1_burst_chk = 1;
697 tx_qos_cfg.eth1_qss = 0;
698 tx_qos_cfg.shape_en = 0; // disable
699 tx_qos_cfg.wfq_en = 0; // strict priority
700 *TX_QOS_CFG = tx_qos_cfg;
701
702 psave_cfg.start_state = 0;
703 psave_cfg.sleep_en = 1; // enable sleep mode
704 *PSAVE_CFG = psave_cfg;
705
706 eg_bwctrl_cfg.fdesc_wm = 16;
707 eg_bwctrl_cfg.class_len = 128;
708 *EG_BWCTRL_CFG = eg_bwctrl_cfg;
709
710 //*GPIO_ADDR = (unsigned int)IFX_GPIO_P0_OUT;
711 *GPIO_ADDR = (unsigned int)0x00000000; // disabled by default
712
713 gpio_mode.gpio_bit_bc1 = 2;
714 gpio_mode.gpio_bit_bc0 = 1;
715 gpio_mode.gpio_bc1_en = 0;
716 gpio_mode.gpio_bc0_en = 0;
717 *GPIO_MODE = gpio_mode;
718
719 gpio_wm_cfg.stop_wm_bc1 = 2;
720 gpio_wm_cfg.start_wm_bc1 = 4;
721 gpio_wm_cfg.stop_wm_bc0 = 2;
722 gpio_wm_cfg.start_wm_bc0 = 4;
723 *GPIO_WM_CFG = gpio_wm_cfg;
724
725 test_mode.mib_clear_mode = 0;
726 test_mode.test_mode = 0;
727 *TEST_MODE = test_mode;
728
729 rx_bc_cfg.local_state = 0;
730 rx_bc_cfg.remote_state = 0;
731 rx_bc_cfg.to_false_th = 7;
732 rx_bc_cfg.to_looking_th = 3;
733 *RX_BC_CFG(0) = rx_bc_cfg;
734 *RX_BC_CFG(1) = rx_bc_cfg;
735
736 tx_bc_cfg.fill_wm = 2;
737 tx_bc_cfg.uflw_wm = 2;
738 *TX_BC_CFG(0) = tx_bc_cfg;
739 *TX_BC_CFG(1) = tx_bc_cfg;
740
741 rx_gamma_itf_cfg.receive_state = 0;
742 rx_gamma_itf_cfg.rx_min_len = 60;
743 rx_gamma_itf_cfg.rx_pad_en = 1;
744 rx_gamma_itf_cfg.rx_eth_fcs_ver_dis = 0;
745 rx_gamma_itf_cfg.rx_rm_eth_fcs = 1;
746 rx_gamma_itf_cfg.rx_tc_crc_ver_dis = 0;
747 rx_gamma_itf_cfg.rx_tc_crc_size = 1;
748 rx_gamma_itf_cfg.rx_eth_fcs_result = 0xC704DD7B;
749 rx_gamma_itf_cfg.rx_tc_crc_result = 0x1D0F1D0F;
750 rx_gamma_itf_cfg.rx_crc_cfg = 0x2500;
751 rx_gamma_itf_cfg.rx_eth_fcs_init_value = 0xFFFFFFFF;
752 rx_gamma_itf_cfg.rx_tc_crc_init_value = 0x0000FFFF;
753 rx_gamma_itf_cfg.rx_max_len_sel = 0;
754 rx_gamma_itf_cfg.rx_edit_num2 = 0;
755 rx_gamma_itf_cfg.rx_edit_pos2 = 0;
756 rx_gamma_itf_cfg.rx_edit_type2 = 0;
757 rx_gamma_itf_cfg.rx_edit_en2 = 0;
758 rx_gamma_itf_cfg.rx_edit_num1 = 0;
759 rx_gamma_itf_cfg.rx_edit_pos1 = 0;
760 rx_gamma_itf_cfg.rx_edit_type1 = 0;
761 rx_gamma_itf_cfg.rx_edit_en1 = 0;
762 rx_gamma_itf_cfg.rx_inserted_bytes_1l = 0;
763 rx_gamma_itf_cfg.rx_inserted_bytes_1h = 0;
764 rx_gamma_itf_cfg.rx_inserted_bytes_2l = 0;
765 rx_gamma_itf_cfg.rx_inserted_bytes_2h = 0;
766 rx_gamma_itf_cfg.rx_len_adj = -6;
767 for ( i = 0; i < 4; i++ )
768 *RX_GAMMA_ITF_CFG(i) = rx_gamma_itf_cfg;
769
770 tx_gamma_itf_cfg.tx_len_adj = 6;
771 tx_gamma_itf_cfg.tx_crc_off_adj = 6;
772 tx_gamma_itf_cfg.tx_min_len = 0;
773 tx_gamma_itf_cfg.tx_eth_fcs_gen_dis = 0;
774 tx_gamma_itf_cfg.tx_tc_crc_size = 1;
775 tx_gamma_itf_cfg.tx_crc_cfg = 0x2F00;
776 tx_gamma_itf_cfg.tx_eth_fcs_init_value = 0xFFFFFFFF;
777 tx_gamma_itf_cfg.tx_tc_crc_init_value = 0x0000FFFF;
778 for ( i = 0; i < ARRAY_SIZE(g_queue_gamma_map); i++ ) {
779 tx_gamma_itf_cfg.queue_mapping = g_queue_gamma_map[i];
780 *TX_GAMMA_ITF_CFG(i) = tx_gamma_itf_cfg;
781 }
782
783 for ( i = 0; i < __ETH_WAN_TX_QUEUE_NUM; i++ ) {
784 wtx_qos_q_desc_cfg.length = WAN_TX_DESC_NUM;
785 wtx_qos_q_desc_cfg.addr = __ETH_WAN_TX_DESC_BASE(i);
786 *WTX_QOS_Q_DESC_CFG(i) = wtx_qos_q_desc_cfg;
787 }
788
789 // default TX queue QoS config is all ZERO
790
791 // TX Ctrl K Table
792 IFX_REG_W32(0x90111293, TX_CTRL_K_TABLE(0));
793 IFX_REG_W32(0x14959617, TX_CTRL_K_TABLE(1));
794 IFX_REG_W32(0x18999A1B, TX_CTRL_K_TABLE(2));
795 IFX_REG_W32(0x9C1D1E9F, TX_CTRL_K_TABLE(3));
796 IFX_REG_W32(0xA02122A3, TX_CTRL_K_TABLE(4));
797 IFX_REG_W32(0x24A5A627, TX_CTRL_K_TABLE(5));
798 IFX_REG_W32(0x28A9AA2B, TX_CTRL_K_TABLE(6));
799 IFX_REG_W32(0xAC2D2EAF, TX_CTRL_K_TABLE(7));
800 IFX_REG_W32(0x30B1B233, TX_CTRL_K_TABLE(8));
801 IFX_REG_W32(0xB43536B7, TX_CTRL_K_TABLE(9));
802 IFX_REG_W32(0xB8393ABB, TX_CTRL_K_TABLE(10));
803 IFX_REG_W32(0x3CBDBE3F, TX_CTRL_K_TABLE(11));
804 IFX_REG_W32(0xC04142C3, TX_CTRL_K_TABLE(12));
805 IFX_REG_W32(0x44C5C647, TX_CTRL_K_TABLE(13));
806 IFX_REG_W32(0x48C9CA4B, TX_CTRL_K_TABLE(14));
807 IFX_REG_W32(0xCC4D4ECF, TX_CTRL_K_TABLE(15));
808
809 // init RX descriptor
810 rx_desc.own = 1;
811 rx_desc.c = 0;
812 rx_desc.sop = 1;
813 rx_desc.eop = 1;
814 rx_desc.byteoff = RX_HEAD_MAC_ADDR_ALIGNMENT;
815 rx_desc.datalen = RX_MAX_BUFFER_SIZE - RX_HEAD_MAC_ADDR_ALIGNMENT;
816 for ( i = 0; i < WAN_RX_DESC_NUM; i++ ) {
817 rx_desc.dataptr = (unsigned int)skb_pool[i]->data & 0x0FFFFFFF;
818 WAN_RX_DESC_BASE[i] = rx_desc;
819 }
820
821 // init TX descriptor
822 tx_desc.own = 0;
823 tx_desc.c = 0;
824 tx_desc.sop = 1;
825 tx_desc.eop = 1;
826 tx_desc.byteoff = 0;
827 tx_desc.qid = 0;
828 tx_desc.datalen = 0;
829 tx_desc.small = 0;
830 tx_desc.dataptr = 0;
831 for ( i = 0; i < CPU_TO_WAN_TX_DESC_NUM; i++ )
832 CPU_TO_WAN_TX_DESC_BASE[i] = tx_desc;
833 for ( i = 0; i < WAN_TX_DESC_NUM_TOTAL; i++ )
834 WAN_TX_DESC_BASE(0)[i] = tx_desc;
835
836 // init Swap descriptor
837 for ( i = 0; i < WAN_SWAP_DESC_NUM; i++ )
838 WAN_SWAP_DESC_BASE[i] = tx_desc;
839
840 // init fastpath TX descriptor
841 tx_desc.own = 1;
842 for ( i = 0; i < FASTPATH_TO_WAN_TX_DESC_NUM; i++ )
843 FASTPATH_TO_WAN_TX_DESC_BASE[i] = tx_desc;
844
845 return 0;
846
847 ALLOC_SKB_RX_FAIL:
848 while ( i-- > 0 )
849 dev_kfree_skb_any(skb_pool[i]);
850 return -1;
851 }
852
853 static inline void clear_tables(void)
854 {
855 struct sk_buff *skb;
856 int i, j;
857
858 for ( i = 0; i < WAN_RX_DESC_NUM; i++ ) {
859 skb = get_skb_pointer(WAN_RX_DESC_BASE[i].dataptr);
860 if ( skb != NULL )
861 dev_kfree_skb_any(skb);
862 }
863
864 for ( i = 0; i < CPU_TO_WAN_TX_DESC_NUM; i++ ) {
865 skb = get_skb_pointer(CPU_TO_WAN_TX_DESC_BASE[i].dataptr);
866 if ( skb != NULL )
867 dev_kfree_skb_any(skb);
868 }
869
870 for ( j = 0; j < 8; j++ )
871 for ( i = 0; i < WAN_TX_DESC_NUM; i++ ) {
872 skb = get_skb_pointer(WAN_TX_DESC_BASE(j)[i].dataptr);
873 if ( skb != NULL )
874 dev_kfree_skb_any(skb);
875 }
876
877 for ( i = 0; i < WAN_SWAP_DESC_NUM; i++ ) {
878 skb = get_skb_pointer(WAN_SWAP_DESC_BASE[i].dataptr);
879 if ( skb != NULL )
880 dev_kfree_skb_any(skb);
881 }
882
883 for ( i = 0; i < FASTPATH_TO_WAN_TX_DESC_NUM; i++ ) {
884 skb = get_skb_pointer(FASTPATH_TO_WAN_TX_DESC_BASE[i].dataptr);
885 if ( skb != NULL )
886 dev_kfree_skb_any(skb);
887 }
888 }
889
890 static int ptm_showtime_enter(struct port_cell_info *port_cell, void *xdata_addr)
891 {
892 ASSERT(port_cell != NULL, "port_cell is NULL");
893 ASSERT(xdata_addr != NULL, "xdata_addr is NULL");
894
895 // TODO: ReTX set xdata_addr
896 g_xdata_addr = xdata_addr;
897
898 g_showtime = 1;
899
900 IFX_REG_W32(0x0F, UTP_CFG);
901
902 //#ifdef CONFIG_VR9
903 // IFX_REG_W32_MASK(1 << 17, 0, FFSM_CFG0);
904 //#endif
905
906 printk("enter showtime\n");
907
908 return 0;
909 }
910
911 static int ptm_showtime_exit(void)
912 {
913 if ( !g_showtime )
914 return -1;
915
916 //#ifdef CONFIG_VR9
917 // IFX_REG_W32_MASK(0, 1 << 17, FFSM_CFG0);
918 //#endif
919
920 IFX_REG_W32(0x00, UTP_CFG);
921
922 g_showtime = 0;
923
924 // TODO: ReTX clean state
925 g_xdata_addr = NULL;
926
927 printk("leave showtime\n");
928
929 return 0;
930 }
931
932
933
934 static int ifx_ptm_init(void)
935 {
936 int ret;
937 int i;
938 char ver_str[128];
939 struct port_cell_info port_cell = {0};
940
941 ret = init_priv_data();
942 if ( ret != 0 ) {
943 err("INIT_PRIV_DATA_FAIL");
944 goto INIT_PRIV_DATA_FAIL;
945 }
946
947 ifx_ptm_init_chip();
948 ret = init_tables();
949 if ( ret != 0 ) {
950 err("INIT_TABLES_FAIL");
951 goto INIT_TABLES_FAIL;
952 }
953
954 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
955 g_net_dev[i] = alloc_netdev(0, g_net_dev_name[i], ether_setup, ptm_setup);
956 if ( g_net_dev[i] == NULL )
957 goto ALLOC_NETDEV_FAIL;
958 }
959
960 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
961 ret = register_netdev(g_net_dev[i]);
962 if ( ret != 0 )
963 goto REGISTER_NETDEV_FAIL;
964 }
965
966 /* register interrupt handler */
967 ret = request_irq(PPE_MAILBOX_IGU1_INT, mailbox_irq_handler, IRQF_DISABLED, "ptm_mailbox_isr", &g_ptm_priv_data);
968 if ( ret ) {
969 if ( ret == -EBUSY ) {
970 err("IRQ may be occupied by other driver, please reconfig to disable it.");
971 }
972 else {
973 err("request_irq fail");
974 }
975 goto REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL;
976 }
977 disable_irq(PPE_MAILBOX_IGU1_INT);
978
979 ret = ifx_pp32_start(0);
980 if ( ret ) {
981 err("ifx_pp32_start fail!");
982 goto PP32_START_FAIL;
983 }
984 IFX_REG_W32(1 << 16, MBOX_IGU1_IER); // enable SWAP interrupt
985 IFX_REG_W32(~0, MBOX_IGU1_ISRC);
986
987 enable_irq(PPE_MAILBOX_IGU1_INT);
988
989 ifx_mei_atm_showtime_check(&g_showtime, &port_cell, &g_xdata_addr);
990
991 ifx_mei_atm_showtime_enter = ptm_showtime_enter;
992 ifx_mei_atm_showtime_exit = ptm_showtime_exit;
993
994 ifx_ptm_version(ver_str);
995 printk(KERN_INFO "%s", ver_str);
996
997 printk("ifxmips_ptm: PTM init succeed\n");
998
999 return 0;
1000
1001 PP32_START_FAIL:
1002 free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
1003 REQUEST_IRQ_PPE_MAILBOX_IGU1_INT_FAIL:
1004 i = ARRAY_SIZE(g_net_dev);
1005 REGISTER_NETDEV_FAIL:
1006 while ( i-- )
1007 unregister_netdev(g_net_dev[i]);
1008 i = ARRAY_SIZE(g_net_dev);
1009 ALLOC_NETDEV_FAIL:
1010 while ( i-- ) {
1011 free_netdev(g_net_dev[i]);
1012 g_net_dev[i] = NULL;
1013 }
1014 INIT_TABLES_FAIL:
1015 INIT_PRIV_DATA_FAIL:
1016 clear_priv_data();
1017 printk("ifxmips_ptm: PTM init failed\n");
1018 return ret;
1019 }
1020
1021 static void __exit ifx_ptm_exit(void)
1022 {
1023 int i;
1024 ifx_mei_atm_showtime_enter = NULL;
1025 ifx_mei_atm_showtime_exit = NULL;
1026
1027
1028 ifx_pp32_stop(0);
1029
1030 free_irq(PPE_MAILBOX_IGU1_INT, &g_ptm_priv_data);
1031
1032 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ )
1033 unregister_netdev(g_net_dev[i]);
1034
1035 for ( i = 0; i < ARRAY_SIZE(g_net_dev); i++ ) {
1036 free_netdev(g_net_dev[i]);
1037 g_net_dev[i] = NULL;
1038 }
1039
1040 clear_tables();
1041
1042 ifx_ptm_uninit_chip();
1043
1044 clear_priv_data();
1045 }
1046
1047 #ifndef MODULE
1048 static int __init wanqos_en_setup(char *line)
1049 {
1050 wanqos_en = simple_strtoul(line, NULL, 0);
1051
1052 if ( wanqos_en < 1 || wanqos_en > 8 )
1053 wanqos_en = 0;
1054
1055 return 0;
1056 }
1057
1058 static int __init queue_gamma_map_setup(char *line)
1059 {
1060 char *p;
1061 int i;
1062
1063 for ( i = 0, p = line; i < ARRAY_SIZE(queue_gamma_map) && isxdigit(*p); i++ )
1064 {
1065 queue_gamma_map[i] = simple_strtoul(p, &p, 0);
1066 if ( *p == ',' || *p == ';' || *p == ':' )
1067 p++;
1068 }
1069
1070 return 0;
1071 }
1072 #endif
1073 module_init(ifx_ptm_init);
1074 module_exit(ifx_ptm_exit);
1075 #ifndef MODULE
1076 __setup("wanqos_en=", wanqos_en_setup);
1077 __setup("queue_gamma_map=", queue_gamma_map_setup);
1078 #endif
1079
1080 MODULE_LICENSE("GPL");