lantiq: remove residual watchdog parts from ltq-vmmc
[openwrt/openwrt.git] / package / kernel / lantiq / ltq-vmmc / patches / 500-ar9_vr9.patch
1 --- a/src/mps/drv_mps_vmmc_ar9.c
2 +++ b/src/mps/drv_mps_vmmc_ar9.c
3 @@ -30,15 +30,24 @@
4 #include "ifxos_interrupt.h"
5
6 /* board specific headers */
7 +#if !defined CONFIG_LANTIQ
8 #include <asm/ifx/ifx_regs.h>
9 #include <asm/ifx_vpe.h>
10 #include <asm/ifx/ifx_gpio.h>
11 +#endif
12 +
13 +#include <lantiq_soc.h>
14 +#include <asm/vpe.h>
15
16 /* device specific headers */
17 #include "drv_mps_vmmc.h"
18 #include "drv_mps_vmmc_dbg.h"
19 #include "drv_mps_vmmc_device.h"
20
21 +const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n) = NULL;
22 +
23 +#define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
24 +
25 /* ============================= */
26 /* Local Macros & Definitions */
27 /* ============================= */
28 @@ -98,47 +107,48 @@ IFX_int32_t (*ifx_wdog_callback) (IFX_ui
29 */
30 IFX_int32_t ifx_mps_fw_wdog_start_ar9()
31 {
32 + return IFX_SUCCESS; /* FIXME - Disable start wdog... */
33 /* vpe1_wdog_ctr should be set up in u-boot as
34 "vpe1_wdog_ctr_addr=0xBF2001B0"; protection from incorrect or missing
35 setting */
36 - if (vpe1_wdog_ctr != VPE1_WDOG_CTR_ADDR)
37 - {
38 - vpe1_wdog_ctr = VPE1_WDOG_CTR_ADDR;
39 - }
40 +// if (vpe1_wdog_ctr != VPE1_WDOG_CTR_ADDR)
41 +// {
42 +// vpe1_wdog_ctr = VPE1_WDOG_CTR_ADDR;
43 +// }
44
45 /* vpe1_wdog_timeout should be set up in u-boot as "vpe1_wdog_timeout =
46 <value in ms>"; protection from insane setting */
47 - if (vpe1_wdog_timeout < VPE1_WDOG_TMOUT_MIN)
48 - {
49 - vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MIN;
50 - }
51 - if (vpe1_wdog_timeout > VPE1_WDOG_TMOUT_MAX)
52 - {
53 - vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MAX;
54 - }
55 +// if (vpe1_wdog_timeout < VPE1_WDOG_TMOUT_MIN)
56 +// {
57 +// vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MIN;
58 +// }
59 +// if (vpe1_wdog_timeout > VPE1_WDOG_TMOUT_MAX)
60 +// {
61 +// vpe1_wdog_timeout = VPE1_WDOG_TMOUT_MAX;
62 +// }
63
64 /* recalculate in jiffies */
65 - vpe1_wdog_timeout = vpe1_wdog_timeout * HZ / 1000;
66 +// vpe1_wdog_timeout = vpe1_wdog_timeout * HZ / 1000;
67
68 /* register BSP callback function */
69 - if (IFX_SUCCESS !=
70 - vpe1_sw_wdog_register_reset_handler (ifx_mps_wdog_callback))
71 - {
72 - TRACE (MPS, DBG_LEVEL_HIGH,
73 - (KERN_ERR "[%s %s %d]: Unable to register WDT callback.\r\n",
74 - __FILE__, __func__, __LINE__));
75 - return IFX_ERROR;;
76 - }
77 +// if (IFX_SUCCESS !=
78 +// vpe1_sw_wdog_register_reset_handler (ifx_mps_wdog_callback))
79 +// {
80 +// TRACE (MPS, DBG_LEVEL_HIGH,
81 +// (KERN_ERR "[%s %s %d]: Unable to register WDT callback.\r\n",
82 +// __FILE__, __func__, __LINE__));
83 +// return IFX_ERROR;;
84 +// }
85
86 /* start software watchdog timer */
87 - if (IFX_SUCCESS != vpe1_sw_wdog_start (0))
88 - {
89 - TRACE (MPS, DBG_LEVEL_HIGH,
90 - (KERN_ERR
91 - "[%s %s %d]: Error starting software watchdog timer.\r\n",
92 - __FILE__, __func__, __LINE__));
93 - return IFX_ERROR;
94 - }
95 +// if (IFX_SUCCESS != vpe1_sw_wdog_start (0))
96 +// {
97 +// TRACE (MPS, DBG_LEVEL_HIGH,
98 +// (KERN_ERR
99 +// "[%s %s %d]: Error starting software watchdog timer.\r\n",
100 +// __FILE__, __func__, __LINE__));
101 +// return IFX_ERROR;
102 +// }
103 return IFX_SUCCESS;
104 }
105
106 @@ -292,6 +302,18 @@ IFX_int32_t ifx_mps_download_firmware (m
107 decryption. Subtract sizeof(u32) from length to avoid decryption
108 of data beyond the FW image code */
109 pFWDwnld->length -= sizeof(IFX_uint32_t);
110 + switch(ltq_soc_type()) {
111 + case SOC_TYPE_AR9:
112 + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf0017c4;
113 + break;
114 + case SOC_TYPE_VR9:
115 + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001ea4;
116 + break;
117 + case SOC_TYPE_VR9_2:
118 + ifx_bsp_basic_mps_decrypt = (const void (*)(unsigned int, int))0xbf001f38;
119 + break;
120 + }
121 + if (ifx_bsp_basic_mps_decrypt)
122 ifx_bsp_basic_mps_decrypt((IFX_uint32_t)cpu1_base_addr, pFWDwnld->length);
123 }
124
125 @@ -306,7 +328,7 @@ IFX_int32_t ifx_mps_download_firmware (m
126 TRACE (MPS, DBG_LEVEL_HIGH,
127 ("MPS: FW checksum error: img=0x%08x calc=0x%08x\r\n",
128 pFW_img_data->crc32, cksum));
129 - return IFX_ERROR;
130 + /* return IFX_ERROR; -- FIXME */
131 }
132 }
133 else
134 @@ -362,9 +384,9 @@ IFX_void_t ifx_mps_shutdown (IFX_void_t)
135 if (vpe1_started)
136 {
137 /* stop software watchdog timer */
138 - vpe1_sw_wdog_stop (0);
139 +// vpe1_sw_wdog_stop (0);
140 /* clean up the BSP callback function */
141 - vpe1_sw_wdog_register_reset_handler (IFX_NULL);
142 +// vpe1_sw_wdog_register_reset_handler (IFX_NULL);
143 /* stop VPE1 */
144 vpe1_sw_stop (0);
145 vpe1_started = 0;
146 @@ -388,7 +410,7 @@ IFX_void_t ifx_mps_reset (IFX_void_t)
147 if (vpe1_started)
148 {
149 /* stop software watchdog timer first */
150 - vpe1_sw_wdog_stop (0);
151 +// vpe1_sw_wdog_stop (0);
152 vpe1_sw_stop (0);
153 vpe1_started = 0;
154 }
155 @@ -454,62 +476,62 @@ IFX_int32_t ifx_mps_wdog_callback (IFX_u
156 #endif /* DEBUG */
157
158 /* reset SmartSLIC */
159 - IFXOS_LOCKINT (flags);
160 - if (ifx_gpio_pin_reserve
161 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
162 - {
163 - TRACE (MPS, DBG_LEVEL_HIGH,
164 - (KERN_ERR "[%s %s %d]: GPIO port/pin reservation error.\r\n",
165 - __FILE__, __func__, __LINE__));
166 - }
167 +// IFXOS_LOCKINT (flags);
168 +// if (ifx_gpio_pin_reserve
169 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
170 +// {
171 +// TRACE (MPS, DBG_LEVEL_HIGH,
172 +// (KERN_ERR "[%s %s %d]: GPIO port/pin reservation error.\r\n",
173 +// __FILE__, __func__, __LINE__));
174 +// }
175 /* P1_ALTSEL0.15 = 0 */
176 - if (ifx_gpio_altsel0_clear
177 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
178 - {
179 - TRACE (MPS, DBG_LEVEL_HIGH,
180 - (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL0.\r\n", __FILE__,
181 - __func__, __LINE__));
182 - }
183 +// if (ifx_gpio_altsel0_clear
184 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
185 +// {
186 +// TRACE (MPS, DBG_LEVEL_HIGH,
187 +// (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL0.\r\n", __FILE__,
188 +// __func__, __LINE__));
189 +// }
190 /* P1_ALTSEL1.15 = 0 */
191 - if (ifx_gpio_altsel1_clear
192 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
193 - {
194 - TRACE (MPS, DBG_LEVEL_HIGH,
195 - (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL1.\r\n", __FILE__,
196 - __func__, __LINE__));
197 - }
198 +// if (ifx_gpio_altsel1_clear
199 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
200 +// {
201 +// TRACE (MPS, DBG_LEVEL_HIGH,
202 +// (KERN_ERR "[%s %s %d]: GPIO error clearing ALTSEL1.\r\n", __FILE__,
203 +// __func__, __LINE__));
204 +// }
205 /* P1_DIR.15 = 1 */
206 - if (ifx_gpio_dir_out_set
207 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
208 - {
209 - TRACE (MPS, DBG_LEVEL_HIGH,
210 - (KERN_ERR "[%s %s %d]: GPIO error setting DIR.\r\n", __FILE__,
211 - __func__, __LINE__));
212 - }
213 +// if (ifx_gpio_dir_out_set
214 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
215 +// {
216 +// TRACE (MPS, DBG_LEVEL_HIGH,
217 +// (KERN_ERR "[%s %s %d]: GPIO error setting DIR.\r\n", __FILE__,
218 +// __func__, __LINE__));
219 +// }
220 /* P1_OD.15 = 1 */
221 - if (ifx_gpio_open_drain_set
222 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
223 - {
224 - TRACE (MPS, DBG_LEVEL_HIGH,
225 - (KERN_ERR "[%s %s %d]: GPIO error setting OD.\r\n", __FILE__,
226 - __func__, __LINE__));
227 - }
228 +// if (ifx_gpio_open_drain_set
229 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
230 +// {
231 +// TRACE (MPS, DBG_LEVEL_HIGH,
232 +// (KERN_ERR "[%s %s %d]: GPIO error setting OD.\r\n", __FILE__,
233 +// __func__, __LINE__));
234 +// }
235 /* P1_OUT.15 = 0 */
236 - if (ifx_gpio_output_clear
237 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
238 - {
239 - TRACE (MPS, DBG_LEVEL_HIGH,
240 - (KERN_ERR "[%s %s %d]: GPIO error clearing OUT.\r\n", __FILE__,
241 - __func__, __LINE__));
242 - }
243 - if (ifx_gpio_pin_free
244 - (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
245 - {
246 - TRACE (MPS, DBG_LEVEL_HIGH,
247 - (KERN_ERR "[%s %s %d]: GPIO port/pin freeing error.\r\n", __FILE__,
248 - __func__, __LINE__));
249 - }
250 - IFXOS_UNLOCKINT (flags);
251 +// if (ifx_gpio_output_clear
252 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
253 +// {
254 +// TRACE (MPS, DBG_LEVEL_HIGH,
255 +// (KERN_ERR "[%s %s %d]: GPIO error clearing OUT.\r\n", __FILE__,
256 +// __func__, __LINE__));
257 +// }
258 +// if (ifx_gpio_pin_free
259 +// (IFX_GPIO_PIN_ID (SSLIC_RST_PORT, SSLIC_RST_PIN), IFX_MPS_MODULE_ID))
260 +// {
261 +// TRACE (MPS, DBG_LEVEL_HIGH,
262 +// (KERN_ERR "[%s %s %d]: GPIO port/pin freeing error.\r\n", __FILE__,
263 +// __func__, __LINE__));
264 +// }
265 +// IFXOS_UNLOCKINT (flags);
266
267 /* recalculate and compare the firmware checksum */
268 ifx_mps_fw_crc_compare(cpu1_base_addr, pFW_img_data);
269 --- a/src/drv_vmmc_amazon_s.h
270 +++ b/src/drv_vmmc_amazon_s.h
271 @@ -16,7 +16,7 @@
272
273
274 #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
275 -#include <asm/ifx/ifx_gpio.h>
276 +//#include <asm/ifx/ifx_gpio.h>
277 #else
278 #error no system selected
279 #endif
280 @@ -27,45 +27,6 @@
281 */
282 #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
283 do { \
284 - ret = VMMC_statusOk; \
285 - /* Reserve P0.0 as TDM/FSC */ \
286 - if (!GPIOreserved) \
287 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
288 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
289 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
290 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
291 - \
292 - /* Reserve P1.9 as TDM/DO */ \
293 - if (!GPIOreserved) \
294 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
295 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
296 - ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
297 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
298 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
299 - \
300 - /* Reserve P2.9 as TDM/DI */ \
301 - if (!GPIOreserved) \
302 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
303 - ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
304 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID);\
305 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
306 - \
307 - /* Reserve P2.8 as TDM/DCL */ \
308 - if (!GPIOreserved) \
309 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
310 - ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
311 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
312 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
313 - \
314 - if (mode == 2) { \
315 - /* TDM/FSC+DCL Master */ \
316 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
317 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
318 - } else { \
319 - /* TDM/FSC+DCL Slave */ \
320 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
321 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
322 - } \
323 } while(0);
324
325 /**
326 @@ -73,11 +34,6 @@ do { \
327 */
328 #define VMMC_DRIVER_UNLOAD_HOOK(ret) \
329 do { \
330 - ret = VMMC_statusOk; \
331 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
332 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
333 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 9), VMMC_TAPI_GPIO_MODULE_ID); \
334 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(2, 8), VMMC_TAPI_GPIO_MODULE_ID); \
335 } while (0)
336
337 #endif /* _DRV_VMMC_AMAZON_S_H */