package/kernel/mac80211/patches/308-ath9k-fix-data-bus-error-on-ar9300-and-ar9580.patch

   1 From: Miaoqing Pan <miaoqing@codeaurora.org>
   2 Date: Fri, 15 Jan 2016 18:17:21 +0800
   3 Subject: [PATCH] ath9k: fix data bus error on ar9300 and ar9580
   4
   5 One crash issue be found on ar9300: RTC_RC reg read leads crash, leading
   6 the data bus error, due to RTC_RC reg write not happen properly.
   7
   8 Warm Reset trigger in continuous beacon stuck for one of the customer for
   9 other chip, noticed the MAC was stuck in RTC reset. After analysis noticed
  10 DMA did not complete when RTC was put in reset.
  11
  12 So, before resetting the MAC need to make sure there are no pending DMA
  13 transactions because this reset does not reset all parts of the chip.
  14
  15 The 12th and 11th bit of MAC _DMA_CFG register used to do that.
  16         12 cfg_halt_ack 0x0
  17                 0 DMA has not yet halted
  18                 1 DMA has halted
  19         11 cfg_halt_req 0x0
  20                 0 DMA logic operates normally
  21                 1 Request DMA logic to stop so software can reset the MAC
  22
  23 The Bit [12] of this register indicates when the halt has taken effect or
  24 not. the DMA halt IS NOT recoverable; once software sets bit [11] to
  25 request a DMA halt, software must wait for bit [12] to be set and reset
  26 the MAC.
  27
  28 So, the same thing we implemented for ar9580 chip.
  29
  30 Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org>
  31 ---
  32
  33 --- a/drivers/net/wireless/ath/ath9k/hw.c
  34 +++ b/drivers/net/wireless/ath/ath9k/hw.c
  35 @@ -1368,6 +1368,16 @@ static bool ath9k_hw_set_reset(struct at
  36         if (ath9k_hw_mci_is_enabled(ah))
  37                 ar9003_mci_check_gpm_offset(ah);
  38
  39 +       /* DMA HALT added to resolve ar9300 and ar9580 bus error during
  40 +        * RTC_RC reg read
  41 +        */
  42 +       if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
  43 +               REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
  44 +               ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
  45 +                             20 * AH_WAIT_TIMEOUT);
  46 +               REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
  47 +       }
  48 +
  49         REG_WRITE(ah, AR_RTC_RC, rst_flags);
  50
  51         REGWRITE_BUFFER_FLUSH(ah);
  52 --- a/drivers/net/wireless/ath/ath9k/reg.h
  53 +++ b/drivers/net/wireless/ath/ath9k/reg.h
  54 @@ -34,8 +34,10 @@
  55  #define AR_CFG_SWRG          0x00000010
  56  #define AR_CFG_AP_ADHOC_INDICATION 0x00000020
  57  #define AR_CFG_PHOK          0x00000100
  58 -#define AR_CFG_CLK_GATE_DIS  0x00000400
  59  #define AR_CFG_EEBS          0x00000200
  60 +#define AR_CFG_CLK_GATE_DIS  0x00000400
  61 +#define AR_CFG_HALT_REQ             0x00000800
  62 +#define AR_CFG_HALT_ACK             0x00001000
  63  #define AR_CFG_PCI_MASTER_REQ_Q_THRESH         0x00060000
  64  #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S       17
  65