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[openwrt/openwrt.git] / package / kernel / mac80211 / patches / 650-rt2x00-add-support-for-external-PA-on-MT7620.patch
1 From 9782a7f7488443568fa4d6088b73c9aff7eb8510 Mon Sep 17 00:00:00 2001
2 From: Daniel Golle <daniel@makrotopia.org>
3 Date: Wed, 19 Apr 2017 16:14:53 +0200
4 Subject: [PATCH] rt2x00: add support for external PA on MT7620
5 To: Stanislaw Gruszka <sgruszka@redhat.com>
6 Cc: Helmut Schaa <helmut.schaa@googlemail.com>,
7 linux-wireless@vger.kernel.org,
8 Kalle Valo <kvalo@codeaurora.org>
9
10 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
11 ---
12 drivers/net/wireless/ralink/rt2x00/rt2800.h | 1 +
13 drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 70 +++++++++++++++++++++++++-
14 2 files changed, 70 insertions(+), 1 deletion(-)
15
16 diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800.h b/drivers/net/wireless/ralink/rt2x00/rt2800.h
17 index 6a8c93fb6a43..df0cefe44171 100644
18 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
19 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
20 @@ -2732,6 +2732,7 @@ enum rt2800_eeprom_word {
21 #define EEPROM_NIC_CONF2_RX_STREAM FIELD16(0x000f)
22 #define EEPROM_NIC_CONF2_TX_STREAM FIELD16(0x00f0)
23 #define EEPROM_NIC_CONF2_CRYSTAL FIELD16(0x0600)
24 +#define EEPROM_NIC_CONF2_EXTERNAL_PA FIELD16(0xc000)
25
26 /*
27 * EEPROM LNA
28 diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
29 index c06db547b0a4..db431c9544e2 100644
30 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
31 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
32 @@ -3834,6 +3834,61 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
33 rt2800_iq_calibrate(rt2x00dev, rf->channel);
34 }
35
36 + if (rt2x00_rt(rt2x00dev, RT6352)) {
37 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0,
38 + &rt2x00dev->cap_flags)) {
39 + rt2x00_warn(rt2x00dev, "Using incomplete support for " \
40 + "external PA\n");
41 + rt2800_register_read(rt2x00dev, RF_CONTROL3, &reg);
42 + reg |= 0x00000101;
43 + rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
44 +
45 + rt2800_register_read(rt2x00dev, RF_BYPASS3, &reg);
46 + reg |= 0x00000101;
47 + rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
48 +
49 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 43, 0x73);
50 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 43, 0x73);
51 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 44, 0x73);
52 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 44, 0x73);
53 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 45, 0x73);
54 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0x73);
55 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 46, 0x27);
56 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 46, 0x27);
57 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0xC8);
58 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0xC8);
59 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 48, 0xA4);
60 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 48, 0xA4);
61 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 49, 0x05);
62 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 49, 0x05);
63 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
64 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x27);
65 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 55, 0xC8);
66 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 55, 0xC8);
67 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 56, 0xA4);
68 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 56, 0xA4);
69 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 57, 0x05);
70 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 57, 0x05);
71 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 58, 0x27);
72 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 58, 0x27);
73 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 59, 0xC8);
74 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 59, 0xC8);
75 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 60, 0xA4);
76 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 60, 0xA4);
77 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 61, 0x05);
78 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 61, 0x05);
79 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 05, 0x00);
80 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 05, 0x00);
81 +
82 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
83 + 0x36303636);
84 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
85 + 0x6C6C6B6C);
86 + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
87 + 0x6C6C6B6C);
88 + }
89 + }
90 +
91 rt2800_bbp_read(rt2x00dev, 4, &bbp);
92 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
93 rt2800_bbp_write(rt2x00dev, 4, bbp);
94 @@ -8796,7 +8851,8 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
95 */
96 rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
97
98 - if (rt2x00_rt(rt2x00dev, RT3352)) {
99 + if (rt2x00_rt(rt2x00dev, RT3352) ||
100 + rt2x00_rt(rt2x00dev, RT6352)) {
101 if (rt2x00_get_field16(eeprom,
102 EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
103 __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
104 @@ -8807,6 +8863,18 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
105 &rt2x00dev->cap_flags);
106 }
107
108 + rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2, &eeprom);
109 +
110 + if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) {
111 + if (rt2x00_get_field16(eeprom,
112 + EEPROM_NIC_CONF2_EXTERNAL_PA)) {
113 + __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
114 + &rt2x00dev->cap_flags);
115 + __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
116 + &rt2x00dev->cap_flags);
117 + }
118 + }
119 +
120 return 0;
121 }
122
123 --
124 2.12.2
125
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