package/kernel/mac80211/patches/653-0036-rtl8xxxu-Add-some-8188eu-registers-and-update-CCK0_A.patch

   1 From a9f5a167be625cf0cd157aa38f3635b2b1f0cc0f Mon Sep 17 00:00:00 2001
   2 From: Jes Sorensen <Jes.Sorensen@redhat.com>
   3 Date: Fri, 29 Jul 2016 15:25:34 -0400
   4 Subject: [PATCH] rtl8xxxu: Add some 8188eu registers and update
   5  CCK0_AFE_SETTING bit defines
   6
   7 CCK0_AFE_SETTING is particular, it has the notion of primary RX antenna
   8 and optional RX antenna. When configuring RX for single antenna, setup
   9 should use the same antenna for default and optional. For AB setup,
  10 use antenna A as default and B as optional.
  11
  12 In addition add info for 8188eu IOL magic interface used to send
  13 firmware and register init files to the firmware.
  14
  15 Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com>
  16 ---
  17  .../net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h  | 30 ++++++++++++++++++++--
  18  1 file changed, 28 insertions(+), 2 deletions(-)
  19
  20 --- a/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
  21 +++ b/drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_regs.h
  22 @@ -378,6 +378,11 @@
  23  #define  PBP_PAGE_SIZE_512             0x3
  24  #define  PBP_PAGE_SIZE_1024            0x4
  25
  26 +/* 8188eu IOL magic */
  27 +#define REG_PKT_BUF_ACCESS_CTRL                0x0106
  28 +#define  PKT_BUF_ACCESS_CTRL_TX                0x69
  29 +#define  PKT_BUF_ACCESS_CTRL_RX                0xa5
  30 +
  31  #define REG_TRXDMA_CTRL                        0x010c
  32  #define  TRXDMA_CTRL_RXDMA_AGG_EN      BIT(2)
  33  #define  TRXDMA_CTRL_VOQ_SHIFT         4
  34 @@ -449,6 +454,7 @@
  35
  36  #define REG_FIFOPAGE                   0x0204
  37  #define REG_TDECTRL                    0x0208
  38 +
  39  #define REG_TXDMA_OFFSET_CHK           0x020c
  40  #define  TXDMA_OFFSET_DROP_DATA_EN     BIT(9)
  41  #define REG_TXDMA_STATUS               0x0210
  42 @@ -938,6 +944,7 @@
  43  #define REG_FPGA1_RF_MODE              0x0900
  44
  45  #define REG_FPGA1_TX_INFO              0x090c
  46 +#define REG_ANT_MAPPING1               0x0914
  47  #define REG_DPDT_CTRL                  0x092c  /* 8723BU */
  48  #define REG_RFE_CTRL_ANTA_SRC          0x0930  /* 8723BU */
  49  #define REG_RFE_PATH_SELECT            0x0940  /* 8723BU */
  50 @@ -949,9 +956,25 @@
  51
  52  #define REG_CCK0_AFE_SETTING           0x0a04
  53  #define  CCK0_AFE_RX_MASK              0x0f000000
  54 -#define  CCK0_AFE_RX_ANT_AB            BIT(24)
  55 +#define  CCK0_AFE_TX_MASK              0xf0000000
  56  #define  CCK0_AFE_RX_ANT_A             0
  57 -#define  CCK0_AFE_RX_ANT_B             (BIT(24) | BIT(26))
  58 +#define  CCK0_AFE_RX_ANT_B             BIT(26)
  59 +#define  CCK0_AFE_RX_ANT_C             BIT(27)
  60 +#define  CCK0_AFE_RX_ANT_D             (BIT(26) | BIT(27))
  61 +#define  CCK0_AFE_RX_ANT_OPTION_A      0
  62 +#define  CCK0_AFE_RX_ANT_OPTION_B      BIT(24)
  63 +#define  CCK0_AFE_RX_ANT_OPTION_C      BIT(25)
  64 +#define  CCK0_AFE_RX_ANT_OPTION_D      (BIT(24) | BIT(25))
  65 +#define  CCK0_AFE_TX_ANT_A             BIT(31)
  66 +#define  CCK0_AFE_TX_ANT_B             BIT(30)
  67 +
  68 +#define REG_CCK_ANTDIV_PARA2           0x0a04
  69 +#define REG_BB_POWER_SAVE4             0x0a74
  70 +
  71 +/* 8188eu */
  72 +#define REG_LNA_SWITCH                 0x0b2c
  73 +#define  LNA_SWITCH_DISABLE_CSCG       BIT(22)
  74 +#define  LNA_SWITCH_OUTPUT_CG          BIT(31)
  75
  76  #define REG_CONFIG_ANT_A               0x0b68
  77  #define REG_CONFIG_ANT_B               0x0b6c
  78 @@ -1004,6 +1027,9 @@
  79
  80  #define REG_OFDM0_RX_IQ_EXT_ANTA       0x0ca0
  81
  82 +/* 8188eu */
  83 +#define REG_ANTDIV_PARA1               0x0ca4
  84 +
  85  /* 8723bu */
  86  #define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4
  87