5ba558055efa3979e7edd7129e43f353b1e95c22
[openwrt/openwrt.git] / package / kernel / mac80211 / patches / 910-01-add-support-for-mt7620.patch
1 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
2 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
3 @@ -81,6 +81,7 @@
4 #define RF5372 0x5372
5 #define RF5390 0x5390
6 #define RF5392 0x5392
7 +#define RF7620 0x7620
8
9 /*
10 * Chipset revisions.
11 @@ -656,6 +657,14 @@
12 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
13
14 /*
15 + * mt7620 RF registers (reversed order)
16 + */
17 +#define RF_CSR_CFG_DATA_MT7620 FIELD32(0x0000ff00)
18 +#define RF_CSR_CFG_REGNUM_MT7620 FIELD32(0x03ff0000)
19 +#define RF_CSR_CFG_WRITE_MT7620 FIELD32(0x00000010)
20 +#define RF_CSR_CFG_BUSY_MT7620 FIELD32(0x00000001)
21 +
22 +/*
23 * EFUSE_CSR: RT30x0 EEPROM
24 */
25 #define EFUSE_CTRL 0x0580
26 @@ -1039,6 +1048,11 @@
27 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
28
29 /*
30 + * mt7620
31 + */
32 +#define MIMO_PS_CFG 0x1210
33 +
34 +/*
35 * EDCA_AC0_CFG:
36 */
37 #define EDCA_AC0_CFG 0x1300
38 @@ -1218,6 +1232,8 @@
39 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
40 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
41 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
42 +#define TX_PIN_CFG_RFRX_EN FIELD32(0x00100000) /* mt7620 */
43 +#define TX_PIN_CFG_RFRX_POL FIELD32(0x00200000) /* mt7620 */
44 #define TX_PIN_CFG_PA_PE_A2_EN FIELD32(0x01000000)
45 #define TX_PIN_CFG_PA_PE_G2_EN FIELD32(0x02000000)
46 #define TX_PIN_CFG_PA_PE_A2_POL FIELD32(0x04000000)
47 @@ -1564,6 +1580,17 @@
48 #define TX_PWR_CFG_4_EXT_STBC4_CH2 FIELD32(0x0000000f)
49 #define TX_PWR_CFG_4_EXT_STBC6_CH2 FIELD32(0x00000f00)
50
51 +/* mt7620 */
52 +#define TX0_RF_GAIN_CORRECT 0x13a0
53 +#define TX1_RF_GAIN_CORRECT 0x13a4
54 +#define TX0_RF_GAIN_ATTEN 0x13a8
55 +#define TX1_RF_GAIN_ATTEN 0x13ac
56 +#define TX_ALG_CFG_0 0x13b0
57 +#define TX_ALG_CFG_1 0x13b4
58 +#define TX0_BB_GAIN_ATTEN 0x13c0
59 +#define TX1_BB_GAIN_ATTEN 0x13c4
60 +#define TX_ALC_VGA3 0x13c8
61 +
62 /* TX_PWR_CFG_7 */
63 #define TX_PWR_CFG_7 0x13d4
64 #define TX_PWR_CFG_7_OFDM54_CH0 FIELD32(0x0000000f)
65 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
66 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
67 @@ -61,6 +61,8 @@
68 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
69 #define WAIT_FOR_RFCSR(__dev, __reg) \
70 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
71 +#define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
72 + rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, (__reg))
73 #define WAIT_FOR_RF(__dev, __reg) \
74 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
75 #define WAIT_FOR_MCU(__dev, __reg) \
76 @@ -186,19 +188,55 @@ static void rt2800_rfcsr_write(struct rt
77 * Wait until the RFCSR becomes available, afterwards we
78 * can safely write the new data into the register.
79 */
80 - if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
81 - reg = 0;
82 - rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
83 - rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
84 - rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
85 - rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
86 + switch (rt2x00dev->chip.rf) {
87 + case RF7620:
88 + if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
89 + reg = 0;
90 + rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
91 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620, word);
92 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
93 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
94 +
95 + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
96 + }
97 + break;
98 +
99 + default:
100 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
101 + reg = 0;
102 + rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
103 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
104 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
105 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
106
107 - rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
108 + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
109 + }
110 + break;
111 }
112
113 mutex_unlock(&rt2x00dev->csr_mutex);
114 }
115
116 +static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
117 + const unsigned int reg, const u8 value)
118 +{
119 + rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
120 +}
121 +
122 +static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
123 + const unsigned int reg, const u8 value)
124 +{
125 + rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
126 + rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
127 +}
128 +
129 +static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
130 + const unsigned int reg, const u8 value)
131 +{
132 + rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
133 + rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
134 +}
135 +
136 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
137 const unsigned int word, u8 *value)
138 {
139 @@ -214,22 +252,47 @@ static void rt2800_rfcsr_read(struct rt2
140 * doesn't become available in time, reg will be 0xffffffff
141 * which means we return 0xff to the caller.
142 */
143 - if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
144 - reg = 0;
145 - rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
146 - rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
147 - rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
148 + switch (rt2x00dev->chip.rf) {
149 + case RF7620:
150 + if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
151 + reg = 0;
152 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620, word);
153 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
154 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
155
156 - rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
157 + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
158
159 - WAIT_FOR_RFCSR(rt2x00dev, &reg);
160 - }
161 + WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
162 + }
163
164 - *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
165 + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
166 + break;
167 +
168 + default:
169 + if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
170 + reg = 0;
171 + rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
172 + rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
173 + rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
174 +
175 + rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
176 +
177 + WAIT_FOR_RFCSR(rt2x00dev, &reg);
178 + }
179 +
180 + *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
181 + break;
182 + }
183
184 mutex_unlock(&rt2x00dev->csr_mutex);
185 }
186
187 +static void rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
188 + const unsigned int reg, u8 *value)
189 +{
190 + rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)), value);
191 +}
192 +
193 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
194 const unsigned int word, const u32 value)
195 {
196 @@ -566,6 +629,16 @@ void rt2800_get_txwi_rxwi_size(struct rt
197 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
198 break;
199
200 + case RT5390:
201 + if ( rt2x00dev->chip.rf == RF7620 ) {
202 + *txwi_size = TXWI_DESC_SIZE_5WORDS;
203 + *rxwi_size = RXWI_DESC_SIZE_6WORDS;
204 + } else {
205 + *txwi_size = TXWI_DESC_SIZE_4WORDS;
206 + *rxwi_size = RXWI_DESC_SIZE_4WORDS;
207 + }
208 + break;
209 +
210 case RT5592:
211 *txwi_size = TXWI_DESC_SIZE_5WORDS;
212 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
213 @@ -3303,6 +3376,312 @@ static void rt2800_config_channel_rf55xx
214 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
215 }
216
217 +typedef struct mt7620_freqconfig {
218 + u8 Channel;
219 + u8 Rdiv;
220 + u16 N;
221 + u8 K;
222 + u8 D;
223 + u32 Ksd;
224 +} mt7620_freqconfig;
225 +
226 +mt7620_freqconfig mt7620_chanconfig[] =
227 +{
228 + /* 2.4 to 2.483 GHz
229 + * CH Rdiv N K D Ksd */
230 + { 0, 0, 0, 0, 0, 0 },
231 + { 1, 3, 0x50, 0, 0, 0x19999 },
232 + { 2, 3, 0x50, 0, 0, 0x24444 },
233 + { 3, 3, 0x50, 0, 0, 0x2EEEE },
234 + { 4, 3, 0x50, 0, 0, 0x39999 },
235 + { 5, 3, 0x51, 0, 0, 0x04444 },
236 + { 6, 3, 0x51, 0, 0, 0x0EEEE },
237 + { 7, 3, 0x51, 0, 0, 0x19999 },
238 + { 8, 3, 0x51, 0, 0, 0x24444 },
239 + { 9, 3, 0x51, 0, 0, 0x2EEEE },
240 + { 10, 3, 0x51, 0, 0, 0x39999 },
241 + { 11, 3, 0x52, 0, 0, 0x04444 },
242 + { 12, 3, 0x52, 0, 0, 0x0EEEE },
243 + { 13, 3, 0x52, 0, 0, 0x19999 },
244 + { 14, 3, 0x52, 0, 0, 0x33333 },
245 +};
246 +
247 +static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
248 + struct ieee80211_conf *conf,
249 + struct rf_channel *rf,
250 + struct channel_info *info)
251 +{
252 + int i;
253 + u8 bbp;
254 + u8 rfcsr;
255 + u8 txrx_agc_fc;
256 + u32 reg;
257 + u16 eeprom, target_power;
258 + u32 mac_sys_ctrl, mac_status;
259 + u32 tx_pin = 0x00150F0F;
260 + struct hw_mode_spec *spec = &rt2x00dev->spec;
261 + struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
262 +
263 + /* Frequeny plan setting */
264 + /*
265 + * Rdiv setting
266 + * R13[1:0]
267 + */
268 + rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
269 + rfcsr = rfcsr & (~0x03);
270 + if (spec->clk_is_20mhz)
271 + rfcsr |= (mt7620_chanconfig[rf->channel].Rdiv & 0x3);
272 + rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
273 +
274 + /*
275 + * N setting
276 + * R21[0], R20[7:0]
277 + */
278 + rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
279 + rfcsr = (mt7620_chanconfig[rf->channel].N & 0x00ff);
280 + rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
281 +
282 + rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
283 + rfcsr = rfcsr & (~0x01);
284 + rfcsr |= ((mt7620_chanconfig[rf->channel].N & 0x0100) >> 8);
285 + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
286 +
287 + /*
288 + * K setting
289 + * R16[3:0] (RF PLL freq selection)
290 + */
291 + rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
292 + rfcsr = rfcsr & (~0x0f);
293 + rfcsr |= (mt7620_chanconfig[rf->channel].K & 0x0f);
294 + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
295 +
296 + /*
297 + * D setting
298 + * R22[2:0] (D=15, R22[2:0]=<111>)
299 + */
300 + rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
301 + rfcsr = rfcsr & (~0x07);
302 + rfcsr |= (mt7620_chanconfig[rf->channel].D & 0x07);
303 + rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
304 +
305 + /*
306 + * Ksd setting
307 + * Ksd: R19<1:0>,R18<7:0>,R17<7:0>
308 + */
309 + rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
310 + rfcsr = (mt7620_chanconfig[rf->channel].Ksd & 0x000000ff);
311 + rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
312 +
313 + rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
314 + rfcsr = ((mt7620_chanconfig[rf->channel].Ksd & 0x0000ff00) >> 8);
315 + rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
316 +
317 + rt2800_rfcsr_read(rt2x00dev, 19, &rfcsr);
318 + rfcsr = rfcsr & (~0x03);
319 + rfcsr |= ((mt7620_chanconfig[rf->channel].Ksd & 0x00030000) >> 16);
320 + rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
321 +
322 + /* Default: XO=20MHz , SDM mode */
323 + rt2800_rfcsr_read(rt2x00dev, 16, &rfcsr);
324 + rfcsr = rfcsr & (~0xE0);
325 + rfcsr |= 0x80;
326 + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
327 +
328 + rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
329 + rfcsr |= 0x80;
330 + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
331 +
332 + rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
333 + if (rt2x00dev->default_ant.tx_chain_num == 1)
334 + rfcsr &= (~0x2);
335 + else
336 + rfcsr |= 0x2;
337 + rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
338 +
339 + rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
340 + if (rt2x00dev->default_ant.tx_chain_num == 1)
341 + rfcsr &= (~0x20);
342 + else
343 + rfcsr |= 0x20;
344 + if (rt2x00dev->default_ant.rx_chain_num == 1)
345 + rfcsr &= (~0x02);
346 + else
347 + rfcsr |= 0x02;
348 + rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
349 +
350 + rt2800_rfcsr_read(rt2x00dev, 42, &rfcsr);
351 + if (rt2x00dev->default_ant.tx_chain_num == 1)
352 + rfcsr &= (~0x40);
353 + else
354 + rfcsr |= 0x40;
355 + rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
356 +
357 + /* RF for DC Cal BW */
358 + if (conf_is_ht40(conf)) {
359 + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
360 + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
361 + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
362 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
363 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
364 + } else {
365 + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
366 + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
367 + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
368 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
369 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
370 + }
371 +
372 + if (conf_is_ht40(conf)) {
373 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
374 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
375 + } else {
376 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
377 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
378 + }
379 +
380 + rt2800_rfcsr_read(rt2x00dev, 28, &rfcsr);
381 + if (conf_is_ht40(conf) && (rf->channel == 11))
382 + rfcsr |= 0x4;
383 + else
384 + rfcsr &= (~0x4);
385 + rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
386 +
387 + /*if (bScan == FALSE)*/
388 + if (conf_is_ht40(conf)) {
389 + txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
390 + RFCSR24_TX_AGC_FC);
391 + } else {
392 + txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
393 + RFCSR24_TX_AGC_FC);
394 + }
395 + rt2800_rfcsr_read_bank(rt2x00dev, 5, 6, &rfcsr);
396 + rfcsr &= (~0x3F);
397 + rfcsr |= txrx_agc_fc;
398 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
399 + rt2800_rfcsr_read_bank(rt2x00dev, 5, 7, &rfcsr);
400 + rfcsr &= (~0x3F);
401 + rfcsr |= txrx_agc_fc;
402 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
403 + rt2800_rfcsr_read_bank(rt2x00dev, 7, 6, &rfcsr);
404 + rfcsr &= (~0x3F);
405 + rfcsr |= txrx_agc_fc;
406 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
407 + rt2800_rfcsr_read_bank(rt2x00dev, 7, 7, &rfcsr);
408 + rfcsr &= (~0x3F);
409 + rfcsr |= txrx_agc_fc;
410 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
411 +
412 + rt2800_rfcsr_read_bank(rt2x00dev, 5, 58, &rfcsr);
413 + rfcsr &= (~0x3F);
414 + rfcsr |= txrx_agc_fc;
415 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
416 + rt2800_rfcsr_read_bank(rt2x00dev, 5, 59, &rfcsr);
417 + rfcsr &= (~0x3F);
418 + rfcsr |= txrx_agc_fc;
419 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
420 + rt2800_rfcsr_read_bank(rt2x00dev, 7, 58, &rfcsr);
421 + rfcsr &= (~0x3F);
422 + rfcsr |= txrx_agc_fc;
423 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
424 + rt2800_rfcsr_read_bank(rt2x00dev, 7, 59, &rfcsr);
425 + rfcsr &= (~0x3F);
426 + rfcsr |= txrx_agc_fc;
427 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
428 +
429 + rt2800_register_read(rt2x00dev, TX_ALG_CFG_0, &reg);
430 + reg = reg & (~0x3F3F);
431 + reg |= info->default_power1;
432 + reg |= (info->default_power2 << 8);
433 + reg |= (0x2F << 16);
434 + reg |= (0x2F << 24);
435 +
436 + rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
437 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
438 + /* init base power by e2p target power */
439 + rt2800_eeprom_read(rt2x00dev, 0xD0, &target_power);
440 + target_power &= 0x3F;
441 + reg = reg & (~0x3F3F);
442 + reg |= target_power;
443 + reg |= (target_power << 8);
444 + }
445 + rt2800_register_write(rt2x00dev, TX_ALG_CFG_0, reg);
446 +
447 + rt2800_register_read(rt2x00dev, TX_ALG_CFG_1, &reg);
448 + reg = reg & (~0x3F);
449 + rt2800_register_write(rt2x00dev, TX_ALG_CFG_1, reg);
450 +
451 + /*if (bScan == FALSE)*/
452 + /* Save MAC SYS CTRL registers */
453 + rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &mac_sys_ctrl);
454 + /* Disable Tx/Rx */
455 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
456 + /* Check MAC Tx/Rx idle */
457 + for (i = 0; i < 10000; i++) {
458 + rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &mac_status);
459 + if (mac_status & 0x3)
460 + udelay(50);
461 + else
462 + break;
463 + }
464 +
465 + if (i == 10000)
466 + rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
467 +
468 + if (rf->channel > 10) {
469 + rt2800_bbp_read(rt2x00dev, 30, &bbp);
470 + bbp = 0x40;
471 + rt2800_bbp_write(rt2x00dev, 30, bbp);
472 + rt2800_rfcsr_write(rt2x00dev, 39, 0);
473 + rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
474 + } else {
475 + rt2800_bbp_read(rt2x00dev, 30, &bbp);
476 + bbp = 0x1f;
477 + rt2800_bbp_write(rt2x00dev, 30, bbp);
478 + rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
479 + rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
480 + }
481 +
482 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
483 +
484 + rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
485 + rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
486 +
487 + /* vcocal_en (initiate VCO calibration (reset after completion)) */
488 + rt2800_rfcsr_read(rt2x00dev, 4, &rfcsr);
489 + rfcsr = ((rfcsr & ~0x80) | 0x80);
490 + rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
491 + mdelay(2);
492 +
493 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
494 +
495 + if (rt2x00dev->default_ant.tx_chain_num == 1) {
496 + rt2800_bbp_write(rt2x00dev, 91, 0x07);
497 + rt2800_bbp_write(rt2x00dev, 95, 0x1A);
498 + rt2800_bbp_write(rt2x00dev, 195, 128);
499 + rt2800_bbp_write(rt2x00dev, 196, 0xA0);
500 + rt2800_bbp_write(rt2x00dev, 195, 170);
501 + rt2800_bbp_write(rt2x00dev, 196, 0x12);
502 + rt2800_bbp_write(rt2x00dev, 195, 171);
503 + rt2800_bbp_write(rt2x00dev, 196, 0x10);
504 + } else {
505 + rt2800_bbp_write(rt2x00dev, 91, 0x06);
506 + rt2800_bbp_write(rt2x00dev, 95, 0x9A);
507 + rt2800_bbp_write(rt2x00dev, 195, 128);
508 + rt2800_bbp_write(rt2x00dev, 196, 0xE0);
509 + rt2800_bbp_write(rt2x00dev, 195, 170);
510 + rt2800_bbp_write(rt2x00dev, 196, 0x30);
511 + rt2800_bbp_write(rt2x00dev, 195, 171);
512 + rt2800_bbp_write(rt2x00dev, 196, 0x30);
513 + }
514 +
515 + /* On 11A, We should delay and wait RF/BBP to be stable*/
516 + /* and the appropriate time should be 1000 micro seconds */
517 + /* 2005/06/05 - On 11G, We also need this delay time.
518 + * Otherwise it's difficult to pass the WHQL.*/
519 + udelay(1000);
520 +}
521 +
522 +
523 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
524 const unsigned int word,
525 const u8 value)
526 @@ -3459,7 +3838,7 @@ static void rt2800_config_channel(struct
527 struct channel_info *info)
528 {
529 u32 reg;
530 - unsigned int tx_pin;
531 + u32 tx_pin;
532 u8 bbp, rfcsr;
533
534 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
535 @@ -3513,6 +3892,9 @@ static void rt2800_config_channel(struct
536 case RF5592:
537 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
538 break;
539 + case RF7620:
540 + rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
541 + break;
542 default:
543 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
544 }
545 @@ -3615,7 +3997,7 @@ static void rt2800_config_channel(struct
546 else if (rt2x00_rt(rt2x00dev, RT3593) ||
547 rt2x00_rt(rt2x00dev, RT3883))
548 rt2800_bbp_write(rt2x00dev, 82, 0x82);
549 - else
550 + else if (rt2x00dev->chip.rf != RF7620)
551 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
552
553 if (rt2x00_rt(rt2x00dev, RT3593) ||
554 @@ -3637,7 +4019,7 @@ static void rt2800_config_channel(struct
555 if (rt2x00_rt(rt2x00dev, RT3572))
556 rt2800_rfcsr_write(rt2x00dev, 8, 0);
557
558 - tx_pin = 0;
559 + rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
560
561 switch (rt2x00dev->default_ant.tx_chain_num) {
562 case 3:
563 @@ -3686,6 +4068,7 @@ static void rt2800_config_channel(struct
564
565 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
566 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
567 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
568
569 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
570
571 @@ -4702,6 +5085,14 @@ void rt2800_vco_calibration(struct rt2x0
572 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
573 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
574 break;
575 + case RF7620:
576 + rt2800_rfcsr_read(rt2x00dev, 4, &rfcsr);
577 + /* vcocal_en (initiate VCO calibration (reset after completion))
578 + * It should be at the end of RF configuration. */
579 + rfcsr = ((rfcsr & ~0x80) | 0x80);
580 + rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
581 + mdelay(1);
582 + break;
583 default:
584 return;
585 }
586 @@ -5102,9 +5493,42 @@ static int rt2800_init_registers(struct
587 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
588 rt2x00_rt(rt2x00dev, RT5392) ||
589 rt2x00_rt(rt2x00dev, RT5592)) {
590 - rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
591 - rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
592 - rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
593 + if (rt2x00dev->chip.rf == RF7620) {
594 + rt2800_register_write(rt2x00dev, TX_SW_CFG0,
595 + 0x00000401);
596 + rt2800_register_write(rt2x00dev, TX_SW_CFG1,
597 + 0x000C0000);
598 + rt2800_register_write(rt2x00dev, TX_SW_CFG2,
599 + 0x00000000);
600 + rt2800_register_write(rt2x00dev, MIMO_PS_CFG,
601 + 0x00000002);
602 + rt2800_register_write(rt2x00dev, TX_PIN_CFG,
603 + 0x00150F0F);
604 + rt2800_register_write(rt2x00dev, TX_ALC_VGA3,
605 + 0x06060606);
606 + rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN,
607 + 0x0);
608 + rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN,
609 + 0x0);
610 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
611 + 0x6C6C666C);
612 + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
613 + 0x6C6C666C);
614 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
615 + 0x3630363A);
616 + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
617 + 0x3630363A);
618 + rt2800_register_read(rt2x00dev, TX_ALG_CFG_1, &reg);
619 + reg = reg & (~0x80000000);
620 + rt2800_register_write(rt2x00dev, TX_ALG_CFG_1, reg);
621 + } else {
622 + rt2800_register_write(rt2x00dev, TX_SW_CFG0,
623 + 0x00000404);
624 + rt2800_register_write(rt2x00dev, TX_SW_CFG1,
625 + 0x00080606);
626 + rt2800_register_write(rt2x00dev, TX_SW_CFG2,
627 + 0x00000000);
628 + }
629 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
630 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
631 } else {
632 @@ -6136,6 +6560,225 @@ static void rt2800_init_bbp_5592(struct
633 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
634 }
635
636 +static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
637 + const u8 reg, const u8 value)
638 +{
639 + rt2800_bbp_write(rt2x00dev, 195, reg);
640 + rt2800_bbp_write(rt2x00dev, 196, value);
641 +}
642 +
643 +static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
644 + const u8 reg, const u8 value)
645 +{
646 + rt2800_bbp_write(rt2x00dev, 158, reg);
647 + rt2800_bbp_write(rt2x00dev, 159, value);
648 +}
649 +
650 +static void rt2800_init_bbp_7620(struct rt2x00_dev *rt2x00dev)
651 +{
652 + u8 bbp;
653 +
654 + /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
655 + rt2800_bbp_read(rt2x00dev, 105, &bbp);
656 + rt2x00_set_field8(&bbp, BBP105_MLD,
657 + rt2x00dev->default_ant.rx_chain_num == 2);
658 + rt2800_bbp_write(rt2x00dev, 105, bbp);
659 +
660 + /* Avoid data loss and CRC errors */
661 + /* MAC interface control (MAC_IF_80M, 1: 80 MHz) */
662 + rt2800_bbp4_mac_if_ctrl(rt2x00dev);
663 +
664 + /* Fix I/Q swap issue */
665 + rt2800_bbp_read(rt2x00dev, 1, &bbp);
666 + bbp |= 0x04;
667 + rt2800_bbp_write(rt2x00dev, 1, bbp);
668 +
669 + /* BBP for G band */
670 + rt2800_bbp_write(rt2x00dev, 3, 0x08);
671 + rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
672 + rt2800_bbp_write(rt2x00dev, 6, 0x08);
673 + rt2800_bbp_write(rt2x00dev, 14, 0x09);
674 + rt2800_bbp_write(rt2x00dev, 15, 0xFF);
675 + rt2800_bbp_write(rt2x00dev, 16, 0x01);
676 + rt2800_bbp_write(rt2x00dev, 20, 0x06);
677 + rt2800_bbp_write(rt2x00dev, 21, 0x00);
678 + rt2800_bbp_write(rt2x00dev, 22, 0x00);
679 + rt2800_bbp_write(rt2x00dev, 27, 0x00);
680 + rt2800_bbp_write(rt2x00dev, 28, 0x00);
681 + rt2800_bbp_write(rt2x00dev, 30, 0x00);
682 + rt2800_bbp_write(rt2x00dev, 31, 0x48);
683 + rt2800_bbp_write(rt2x00dev, 47, 0x40);
684 + rt2800_bbp_write(rt2x00dev, 62, 0x00);
685 + rt2800_bbp_write(rt2x00dev, 63, 0x00);
686 + rt2800_bbp_write(rt2x00dev, 64, 0x00);
687 + rt2800_bbp_write(rt2x00dev, 65, 0x2C);
688 + rt2800_bbp_write(rt2x00dev, 66, 0x1C);
689 + rt2800_bbp_write(rt2x00dev, 67, 0x20);
690 + rt2800_bbp_write(rt2x00dev, 68, 0xDD);
691 + rt2800_bbp_write(rt2x00dev, 69, 0x10);
692 + rt2800_bbp_write(rt2x00dev, 70, 0x05);
693 + rt2800_bbp_write(rt2x00dev, 73, 0x18);
694 + rt2800_bbp_write(rt2x00dev, 74, 0x0F);
695 + rt2800_bbp_write(rt2x00dev, 75, 0x60);
696 + rt2800_bbp_write(rt2x00dev, 76, 0x44);
697 + rt2800_bbp_write(rt2x00dev, 77, 0x59);
698 + rt2800_bbp_write(rt2x00dev, 78, 0x1E);
699 + rt2800_bbp_write(rt2x00dev, 79, 0x1C);
700 + rt2800_bbp_write(rt2x00dev, 80, 0x0C);
701 + rt2800_bbp_write(rt2x00dev, 81, 0x3A);
702 + rt2800_bbp_write(rt2x00dev, 82, 0xB6);
703 + rt2800_bbp_write(rt2x00dev, 83, 0x9A);
704 + rt2800_bbp_write(rt2x00dev, 84, 0x9A);
705 + rt2800_bbp_write(rt2x00dev, 86, 0x38);
706 + rt2800_bbp_write(rt2x00dev, 88, 0x90);
707 + rt2800_bbp_write(rt2x00dev, 91, 0x04);
708 + rt2800_bbp_write(rt2x00dev, 92, 0x02);
709 + rt2800_bbp_write(rt2x00dev, 95, 0x9A);
710 + rt2800_bbp_write(rt2x00dev, 96, 0x00);
711 + rt2800_bbp_write(rt2x00dev, 103, 0xC0);
712 + rt2800_bbp_write(rt2x00dev, 104, 0x92);
713 + /* FIXME BBP105 owerwrite */
714 + rt2800_bbp_write(rt2x00dev, 105, 0x3C);
715 + rt2800_bbp_write(rt2x00dev, 106, 0x12);
716 + rt2800_bbp_write(rt2x00dev, 109, 0x00);
717 + rt2800_bbp_write(rt2x00dev, 134, 0x10);
718 + rt2800_bbp_write(rt2x00dev, 135, 0xA6);
719 + rt2800_bbp_write(rt2x00dev, 137, 0x04);
720 + rt2800_bbp_write(rt2x00dev, 142, 0x30);
721 + rt2800_bbp_write(rt2x00dev, 143, 0xF7);
722 + rt2800_bbp_write(rt2x00dev, 160, 0xEC);
723 + rt2800_bbp_write(rt2x00dev, 161, 0xC4);
724 + rt2800_bbp_write(rt2x00dev, 162, 0x77);
725 + rt2800_bbp_write(rt2x00dev, 163, 0xF9);
726 + rt2800_bbp_write(rt2x00dev, 164, 0x00);
727 + rt2800_bbp_write(rt2x00dev, 165, 0x00);
728 + rt2800_bbp_write(rt2x00dev, 186, 0x00);
729 + rt2800_bbp_write(rt2x00dev, 187, 0x00);
730 + rt2800_bbp_write(rt2x00dev, 188, 0x00);
731 + rt2800_bbp_write(rt2x00dev, 186, 0x00);
732 + rt2800_bbp_write(rt2x00dev, 187, 0x01);
733 + rt2800_bbp_write(rt2x00dev, 188, 0x00);
734 + rt2800_bbp_write(rt2x00dev, 189, 0x00);
735 +
736 + rt2800_bbp_write(rt2x00dev, 91, 0x06);
737 + rt2800_bbp_write(rt2x00dev, 92, 0x04);
738 + rt2800_bbp_write(rt2x00dev, 93, 0x54);
739 + rt2800_bbp_write(rt2x00dev, 99, 0x50);
740 + rt2800_bbp_write(rt2x00dev, 148, 0x84);
741 + rt2800_bbp_write(rt2x00dev, 167, 0x80);
742 + rt2800_bbp_write(rt2x00dev, 178, 0xFF);
743 + rt2800_bbp_write(rt2x00dev, 106, 0x13);
744 +
745 + /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
746 + rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
747 + rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14); /* ? see above */
748 + rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
749 + rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
750 + rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
751 + rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
752 + rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
753 + rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
754 + rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
755 + rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
756 + rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
757 + rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
758 + rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
759 + rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
760 + rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
761 + rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
762 + rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
763 + rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
764 + rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
765 + rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
766 + rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
767 + rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
768 + rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
769 + rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
770 + rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
771 + rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
772 + rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
773 + rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
774 + rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
775 + rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
776 + rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
777 + rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
778 + rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
779 + rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
780 + rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
781 + rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
782 + rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
783 + rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
784 + rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
785 + rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
786 + rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
787 + rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
788 + rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
789 + rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
790 + rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
791 + rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
792 + rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
793 + rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
794 + rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
795 + rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
796 + rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
797 + rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
798 + rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
799 + rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
800 + rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
801 + rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
802 + rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
803 + rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
804 + rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
805 + rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
806 + rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
807 + rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
808 + rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
809 + rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
810 + rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
811 + rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
812 + rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
813 + rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
814 + rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
815 + rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
816 + rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
817 + rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
818 + rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
819 + rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
820 + rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
821 + rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
822 + rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
823 + rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
824 + rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
825 + rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
826 + rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
827 + rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
828 + rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
829 +
830 + /* BBP for G band DCOC function */
831 + rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
832 + rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
833 + rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
834 + rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
835 + rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
836 + rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
837 + rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
838 + rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
839 + rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
840 + rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
841 + rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
842 + rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
843 + rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
844 + rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
845 + rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
846 + rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
847 + rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
848 + rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
849 + rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
850 + rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
851 +
852 + rt2800_bbp4_mac_if_ctrl(rt2x00dev);
853 +}
854 +
855 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
856 {
857 unsigned int i;
858 @@ -6178,7 +6821,10 @@ static void rt2800_init_bbp(struct rt2x0
859 return;
860 case RT5390:
861 case RT5392:
862 - rt2800_init_bbp_53xx(rt2x00dev);
863 + if (rt2x00dev->chip.rf == RF7620)
864 + rt2800_init_bbp_7620(rt2x00dev);
865 + else
866 + rt2800_init_bbp_53xx(rt2x00dev);
867 break;
868 case RT5592:
869 rt2800_init_bbp_5592(rt2x00dev);
870 @@ -7392,6 +8038,296 @@ static void rt2800_init_rfcsr_5592(struc
871 rt2800_led_open_drain_enable(rt2x00dev);
872 }
873
874 +static void rt2800_init_rfcsr_7620(struct rt2x00_dev *rt2x00dev)
875 +{
876 + u16 freq;
877 + u8 rfvalue;
878 + struct hw_mode_spec *spec = &rt2x00dev->spec;
879 +
880 + /* Initialize RF central register to default value */
881 + rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
882 + rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
883 + rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
884 + rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
885 + rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
886 + rt2800_rfcsr_write(rt2x00dev, 5, 0x40); /* Read only */
887 + rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
888 + rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
889 + rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
890 + rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
891 + rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
892 + rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
893 + /* rt2800_rfcsr_write(rt2x00dev, 12, 0x43); *//* EEPROM */
894 + rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
895 + rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
896 + rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
897 + rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
898 + rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
899 + rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
900 + rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
901 + rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
902 + rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
903 + rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
904 + rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
905 + rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
906 + rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
907 + rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
908 + rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
909 + rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
910 + rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
911 + rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
912 + rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
913 + rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
914 + rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
915 + rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
916 + rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
917 + rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
918 + rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
919 + rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
920 + rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
921 + rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
922 + rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
923 + rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
924 + rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
925 +
926 + rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
927 + if (spec->clk_is_20mhz)
928 + rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
929 + else
930 + rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
931 + rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
932 + rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
933 + rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
934 + rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
935 + rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
936 + rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
937 + rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
938 + rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
939 + rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
940 + rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
941 + rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
942 + rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
943 + rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
944 + rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
945 + rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
946 + rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
947 +
948 + rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
949 + rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
950 + rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
951 + /* RTMP_TEMPERATURE_CALIBRATION */
952 + /* rt2800_rfcsr_write(rt2x00dev, 34, 0x23); */
953 + /* rt2800_rfcsr_write(rt2x00dev, 35, 0x01); */
954 +
955 + /* use rt2800_adjust_freq_offset ? */
956 + rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &freq);
957 + rfvalue = freq & 0xff;
958 + rt2800_rfcsr_write(rt2x00dev, 12, rfvalue);
959 +
960 + /* Initialize RF channel register to default value */
961 + rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
962 + rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
963 + rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
964 + rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
965 + rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
966 + rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
967 + rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
968 + rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
969 + rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
970 + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
971 + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
972 + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
973 + rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
974 + /* rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D); */ /* fails */
975 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
976 + rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
977 + rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
978 + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
979 + rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
980 + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
981 + rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
982 + rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
983 + rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
984 + rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
985 + rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
986 + rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
987 + rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
988 + rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
989 + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
990 + rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
991 + rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
992 + rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
993 + rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
994 + rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
995 + rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
996 + rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
997 + rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
998 + rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
999 + rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
1000 + rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
1001 + rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
1002 + rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
1003 + rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
1004 + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
1005 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
1006 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
1007 + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
1008 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
1009 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
1010 + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
1011 + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
1012 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
1013 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
1014 + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
1015 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
1016 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
1017 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
1018 + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
1019 + rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
1020 + rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
1021 +
1022 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
1023 +
1024 + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
1025 + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
1026 + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
1027 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
1028 + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
1029 + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
1030 + rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
1031 + rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
1032 + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
1033 + rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
1034 + rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
1035 + rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
1036 + rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
1037 + rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
1038 + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1039 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
1040 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
1041 + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
1042 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x69);
1043 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
1044 + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x20);
1045 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1046 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
1047 + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
1048 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
1049 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1050 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
1051 + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
1052 +
1053 + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
1054 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
1055 + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
1056 + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
1057 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
1058 + rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
1059 + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
1060 + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
1061 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
1062 +
1063 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
1064 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
1065 + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
1066 + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
1067 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
1068 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
1069 +
1070 + /* Initialize RF channel register for DRQFN */
1071 + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
1072 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
1073 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
1074 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
1075 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
1076 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
1077 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
1078 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
1079 +
1080 + /* reduce power consumption */
1081 +/* rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x53);
1082 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x53);
1083 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x53);
1084 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x64);
1085 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0x4F);
1086 + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x02);
1087 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
1088 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x4F);
1089 + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x02);
1090 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
1091 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x64);
1092 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x4F);
1093 + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x02);
1094 +*/
1095 + /* Initialize RF DC calibration register to default value */
1096 + rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
1097 + rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
1098 + rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
1099 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
1100 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
1101 + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1102 + rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
1103 + rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
1104 + rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
1105 + rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
1106 + rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
1107 + rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
1108 + rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
1109 + rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
1110 + rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
1111 + rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
1112 + rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
1113 + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
1114 + rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
1115 + rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
1116 + rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
1117 + rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
1118 + rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
1119 + rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
1120 + rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
1121 + rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
1122 + rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
1123 + rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
1124 + rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
1125 + rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
1126 + rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
1127 + rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
1128 + rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
1129 + rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
1130 + rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
1131 + rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
1132 + rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
1133 + rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
1134 + rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
1135 + rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
1136 + rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
1137 + rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
1138 + rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
1139 + rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
1140 + rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
1141 + rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
1142 + rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
1143 + rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
1144 + rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
1145 + rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
1146 + rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
1147 + rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
1148 + rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
1149 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
1150 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
1151 + rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
1152 + rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
1153 + rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
1154 + rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
1155 +
1156 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
1157 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
1158 + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
1159 +
1160 + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
1161 + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
1162 +}
1163 +
1164 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1165 {
1166 if (rt2800_is_305x_soc(rt2x00dev)) {
1167 @@ -7427,7 +8363,10 @@ static void rt2800_init_rfcsr(struct rt2
1168 rt2800_init_rfcsr_5350(rt2x00dev);
1169 break;
1170 case RT5390:
1171 - rt2800_init_rfcsr_5390(rt2x00dev);
1172 + if (rt2x00dev->chip.rf == RF7620)
1173 + rt2800_init_rfcsr_7620(rt2x00dev);
1174 + else
1175 + rt2800_init_rfcsr_5390(rt2x00dev);
1176 break;
1177 case RT5392:
1178 rt2800_init_rfcsr_5392(rt2x00dev);
1179 @@ -7856,6 +8795,7 @@ static int rt2800_init_eeprom(struct rt2
1180 case RF5390:
1181 case RF5392:
1182 case RF5592:
1183 + case RF7620:
1184 break;
1185 default:
1186 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
1187 @@ -8424,6 +9364,7 @@ static int rt2800_probe_hw_mode(struct r
1188 case RF5372:
1189 case RF5390:
1190 case RF5392:
1191 + case RF7620:
1192 spec->num_channels = 14;
1193 if (spec->clk_is_20mhz)
1194 spec->channels = rf_vals_xtal20mhz_3x;
1195 @@ -8564,6 +9505,7 @@ static int rt2800_probe_hw_mode(struct r
1196 case RF5372:
1197 case RF5390:
1198 case RF5392:
1199 + case RF7620:
1200 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
1201 break;
1202 }