package/kernel/mac80211/patches/brcm/329-v5.0-0007-brcmfmac-4373-save-restore-support.patch

   1 From 2f2d389efda4caa4c1b69cb4fa2ab217f0fe6d6f Mon Sep 17 00:00:00 2001
   2 From: Chi-Hsien Lin <Chi-Hsien.Lin@cypress.com>
   3 Date: Wed, 21 Nov 2018 07:53:50 +0000
   4 Subject: [PATCH] brcmfmac: 4373 save-restore support
   5
   6 Use chipcommon sr_control0 register to check 4373 sr support.
   7
   8 Reviewed-by: Arend van Spriel <arend.vanspriel@broadcom.com>
   9 Signed-off-by: Chi-Hsien Lin <chi-hsien.lin@cypress.com>
  10 Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
  11 ---
  12  .../broadcom/brcm80211/brcmfmac/chip.c        |  5 +++++
  13  .../broadcom/brcm80211/include/chipcommon.h   | 19 +++++++++++++++++++
  14  2 files changed, 24 insertions(+)
  15
  16 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
  17 +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
  18 @@ -1365,6 +1365,11 @@ bool brcmf_chip_sr_capable(struct brcmf_
  19                 addr = CORE_CC_REG(base, sr_control1);
  20                 reg = chip->ops->read32(chip->ctx, addr);
  21                 return reg != 0;
  22 +       case CY_CC_4373_CHIP_ID:
  23 +               /* explicitly check SR engine enable bit */
  24 +               addr = CORE_CC_REG(base, sr_control0);
  25 +               reg = chip->ops->read32(chip->ctx, addr);
  26 +               return (reg & CC_SR_CTL0_ENABLE_MASK) != 0;
  27         case CY_CC_43012_CHIP_ID:
  28                 addr = CORE_CC_REG(pmu->base, retention_ctl);
  29                 reg = chip->ops->read32(chip->ctx, addr);
  30 --- a/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h
  31 +++ b/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h
  32 @@ -269,6 +269,25 @@ struct chipcregs {
  33  /* GSIO (spi/i2c) present, rev >= 37 */
  34  #define        CC_CAP2_GSIO            0x00000002
  35
  36 +/* sr_control0, rev >= 48 */
  37 +#define CC_SR_CTL0_ENABLE_MASK                 BIT(0)
  38 +#define CC_SR_CTL0_ENABLE_SHIFT                0
  39 +#define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT 1 /* sr_clk to sr_memory enable */
  40 +#define CC_SR_CTL0_RSRC_TRIGGER_SHIFT  2 /* Rising edge resource trigger 0 to
  41 +                                          * sr_engine
  42 +                                          */
  43 +#define CC_SR_CTL0_MIN_DIV_SHIFT       6 /* Min division value for fast clk
  44 +                                          * in sr_engine
  45 +                                          */
  46 +#define CC_SR_CTL0_EN_SBC_STBY_SHIFT           16
  47 +#define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT    18
  48 +#define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT          19
  49 +#define CC_SR_CTL0_ALLOW_PIC_SHIFT     20 /* Allow pic to separate power
  50 +                                           * domains
  51 +                                           */
  52 +#define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT     25
  53 +#define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP    30
  54 +
  55  /* pmucapabilities */
  56  #define PCAP_REV_MASK  0x000000ff
  57  #define PCAP_RC_MASK   0x00001f00