mac80211: Update to version 5.6.8-1
[openwrt/openwrt.git] / package / kernel / mac80211 / patches / rt2x00 / 985-rt2x00-add-rxiq-calibration.patch
1 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
2 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
3 @@ -8682,6 +8682,384 @@ static void rt2800_rxdcoc_calibration(st
4 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);
5 }
6
7 +static u32 rt2800_do_sqrt_accumulation(u32 si) {
8 + u32 root, root_pre, bit;
9 + char i;
10 + bit = 1 << 15;
11 + root = 0;
12 + for (i = 15; i >= 0; i = i - 1) {
13 + root_pre = root + bit;
14 + if ((root_pre*root_pre) <= si)
15 + root = root_pre;
16 + bit = bit >> 1;
17 + }
18 +
19 + return root;
20 +}
21 +
22 +static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev) {
23 + u8 rfb0r1, rfb0r2, rfb0r42;
24 + u8 rfb4r0, rfb4r19;
25 + u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20;
26 + u8 rfb6r0, rfb6r19;
27 + u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20;
28 +
29 + u8 bbp1, bbp4;
30 + u8 bbpr241, bbpr242;
31 + u32 i;
32 + u8 ch_idx;
33 + u8 bbpval;
34 + u8 rfval, vga_idx = 0;
35 + int mi = 0, mq = 0, si = 0, sq = 0, riq = 0;
36 + int sigma_i, sigma_q, r_iq, g_rx;
37 + int g_imb;
38 + int ph_rx;
39 + u32 savemacsysctrl = 0;
40 + u32 orig_RF_CONTROL0 = 0;
41 + u32 orig_RF_BYPASS0 = 0;
42 + u32 orig_RF_CONTROL1 = 0;
43 + u32 orig_RF_BYPASS1 = 0;
44 + u32 orig_RF_CONTROL3 = 0;
45 + u32 orig_RF_BYPASS3 = 0;
46 + u32 macstatus, bbpval1 = 0;
47 + u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};
48 +
49 + savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
50 + orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
51 + orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
52 + orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1);
53 + orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1);
54 + orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
55 + orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
56 +
57 + bbp1 = rt2800_bbp_read(rt2x00dev, 1);
58 + bbp4 = rt2800_bbp_read(rt2x00dev, 4);
59 +
60 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0);
61 +
62 + for (i = 0; i < 10000; i++) {
63 + macstatus = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
64 + if (macstatus & 0x3)
65 + udelay(50);
66 + else
67 + break;
68 + }
69 +
70 + if (i == 10000)
71 + rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
72 +
73 + bbpval = bbp4 & (~0x18);
74 + bbpval = bbp4 | 0x00;
75 + rt2800_bbp_write(rt2x00dev, 4, bbpval);
76 +
77 + bbpval = rt2800_bbp_read(rt2x00dev, 21);
78 + bbpval = bbpval | 1;
79 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
80 + bbpval = bbpval & 0xfe;
81 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
82 +
83 + rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202);
84 + rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303);
85 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
86 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101);
87 + else
88 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000);
89 +
90 + rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1);
91 +
92 + rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
93 + rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
94 + rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
95 + rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
96 + rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19);
97 + rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
98 + rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
99 + rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
100 + rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
101 + rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
102 + rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
103 +
104 + rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
105 + rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19);
106 + rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
107 + rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
108 + rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
109 + rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
110 + rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
111 + rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
112 +
113 + rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87);
114 + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27);
115 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38);
116 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38);
117 + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80);
118 + rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1);
119 + rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60);
120 + rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
121 +
122 + rt2800_bbp_write(rt2x00dev, 23, 0x0);
123 + rt2800_bbp_write(rt2x00dev, 24, 0x0);
124 +
125 + rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0);
126 +
127 + bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
128 + bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
129 +
130 + rt2800_bbp_write(rt2x00dev, 241, 0x10);
131 + rt2800_bbp_write(rt2x00dev, 242, 0x84);
132 + rt2800_bbp_write(rt2x00dev, 244, 0x31);
133 +
134 + bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3);
135 + bbpval = bbpval & (~0x7);
136 + rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval);
137 +
138 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
139 + udelay(1);
140 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
141 + usleep_range(1, 200);
142 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376);
143 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
144 + udelay(1);
145 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
146 + rt2800_bbp_write(rt2x00dev, 23, 0x06);
147 + rt2800_bbp_write(rt2x00dev, 24, 0x06);
148 + } else {
149 + rt2800_bbp_write(rt2x00dev, 23, 0x02);
150 + rt2800_bbp_write(rt2x00dev, 24, 0x02);
151 + }
152 +
153 + for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) {
154 + if (ch_idx == 0) {
155 + rfval = rfb0r1 & (~0x3);
156 + rfval = rfb0r1 | 0x1;
157 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
158 + rfval = rfb0r2 & (~0x33);
159 + rfval = rfb0r2 | 0x11;
160 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
161 + rfval = rfb0r42 & (~0x50);
162 + rfval = rfb0r42 | 0x10;
163 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
164 +
165 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
166 + udelay(1);
167 +
168 + bbpval = bbp1 & (~ 0x18);
169 + bbpval = bbpval | 0x00;
170 + rt2800_bbp_write(rt2x00dev, 1, bbpval);
171 +
172 + rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00);
173 + } else {
174 + rfval = rfb0r1 & (~0x3);
175 + rfval = rfb0r1 | 0x2;
176 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
177 + rfval = rfb0r2 & (~0x33);
178 + rfval = rfb0r2 | 0x22;
179 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
180 + rfval = rfb0r42 & (~0x50);
181 + rfval = rfb0r42 | 0x40;
182 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
183 +
184 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006);
185 + udelay(1);
186 +
187 + bbpval = bbp1 & (~ 0x18);
188 + bbpval = bbpval | 0x08;
189 + rt2800_bbp_write(rt2x00dev, 1, bbpval);
190 +
191 + rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01);
192 + }
193 + udelay(500);
194 +
195 + vga_idx = 0;
196 + while (vga_idx < 11) {
197 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]);
198 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]);
199 +
200 + rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93);
201 +
202 + for (i = 0; i < 10000; i++) {
203 + bbpval = rt2800_bbp_read(rt2x00dev, 159);
204 + if ((bbpval & 0xff) == 0x93)
205 + udelay(50);
206 + else
207 + break;
208 + }
209 +
210 + if ((bbpval & 0xff) == 0x93) {
211 + rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish");
212 + goto restore_value;
213 + }
214 +
215 + for (i = 0; i < 5; i++) {
216 + u32 bbptemp = 0;
217 + u8 value = 0;
218 + int result = 0;
219 +
220 + rt2800_bbp_write(rt2x00dev, 158, 0x1e);
221 + rt2800_bbp_write(rt2x00dev, 159, i);
222 + rt2800_bbp_write(rt2x00dev, 158, 0x22);
223 + value = rt2800_bbp_read(rt2x00dev, 159);
224 + bbptemp = bbptemp + (value << 24);
225 + rt2800_bbp_write(rt2x00dev, 158, 0x21);
226 + value = rt2800_bbp_read(rt2x00dev, 159);
227 + bbptemp = bbptemp + (value << 16);
228 + rt2800_bbp_write(rt2x00dev, 158, 0x20);
229 + value = rt2800_bbp_read(rt2x00dev, 159);
230 + bbptemp = bbptemp + (value << 8);
231 + rt2800_bbp_write(rt2x00dev, 158, 0x1f);
232 + value = rt2800_bbp_read(rt2x00dev, 159);
233 + bbptemp = bbptemp + value;
234 +
235 + if ((i < 2) && (bbptemp & 0x800000))
236 + result = (bbptemp & 0xffffff) - 0x1000000;
237 + else if (i == 4)
238 + result = bbptemp;
239 + else
240 + result = bbptemp;
241 +
242 + if (i == 0)
243 + mi = result/4096;
244 + else if (i == 1)
245 + mq = result/4096;
246 + else if (i == 2)
247 + si = bbptemp/4096;
248 + else if (i == 3)
249 + sq = bbptemp/4096;
250 + else
251 + riq = result/4096;
252 + }
253 +
254 + bbpval1 = si - mi*mi;
255 + rt2x00_dbg(rt2x00dev, "RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d", si, sq, riq, bbpval1, vga_idx);
256 +
257 + if (bbpval1 >= (100*100))
258 + break;
259 +
260 + if (bbpval1 <= 100)
261 + vga_idx = vga_idx + 9;
262 + else if (bbpval1 <= 158)
263 + vga_idx = vga_idx + 8;
264 + else if (bbpval1 <= 251)
265 + vga_idx = vga_idx + 7;
266 + else if (bbpval1 <= 398)
267 + vga_idx = vga_idx + 6;
268 + else if (bbpval1 <= 630)
269 + vga_idx = vga_idx + 5;
270 + else if (bbpval1 <= 1000)
271 + vga_idx = vga_idx + 4;
272 + else if (bbpval1 <= 1584)
273 + vga_idx = vga_idx + 3;
274 + else if (bbpval1 <= 2511)
275 + vga_idx = vga_idx + 2;
276 + else
277 + vga_idx = vga_idx + 1;
278 + }
279 +
280 + sigma_i = rt2800_do_sqrt_accumulation(100*(si - mi*mi));
281 + sigma_q = rt2800_do_sqrt_accumulation(100*(sq - mq*mq));
282 + r_iq = 10*(riq-(mi*mq));
283 +
284 + rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq);
285 +
286 + if (((sigma_i <= 1400 ) && (sigma_i >= 1000))
287 + && ((sigma_i - sigma_q) <= 112)
288 + && ((sigma_i - sigma_q) >= -112)
289 + && ((mi <= 32) && (mi >= -32))
290 + && ((mq <= 32) && (mq >= -32))) {
291 + r_iq = 10*(riq-(mi*mq));
292 + rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", sigma_i, sigma_q, r_iq);
293 +
294 + g_rx = (1000 * sigma_q) / sigma_i;
295 + g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx);
296 + ph_rx = (r_iq * 2292) / (sigma_i * sigma_q);
297 + rt2x00_info(rt2x00dev, "RXIQ G_imb=%d, Ph_rx=%d\n", g_imb, ph_rx);
298 +
299 + if ((ph_rx > 20) || (ph_rx < -20)) {
300 + ph_rx = 0;
301 + rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
302 + }
303 +
304 + if ((g_imb > 12) || (g_imb < -12)) {
305 + g_imb = 0;
306 + rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
307 + }
308 + }
309 + else {
310 + g_imb = 0;
311 + ph_rx = 0;
312 + rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", sigma_i, sigma_q, r_iq);
313 + rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
314 + }
315 +
316 + if (ch_idx == 0) {
317 + rt2800_bbp_write(rt2x00dev, 158, 0x37);
318 + rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
319 + rt2800_bbp_write(rt2x00dev, 158, 0x35);
320 + rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
321 + } else {
322 + rt2800_bbp_write(rt2x00dev, 158, 0x55);
323 + rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
324 + rt2800_bbp_write(rt2x00dev, 158, 0x53);
325 + rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
326 + }
327 + }
328 +
329 +restore_value:
330 + rt2800_bbp_write(rt2x00dev, 158, 0x3);
331 + bbpval = rt2800_bbp_read(rt2x00dev, 159);
332 + rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07));
333 +
334 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
335 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
336 + rt2800_bbp_write(rt2x00dev, 1, bbp1);
337 + rt2800_bbp_write(rt2x00dev, 4, bbp4);
338 + rt2800_bbp_write(rt2x00dev, 241, bbpr241);
339 + rt2800_bbp_write(rt2x00dev, 242, bbpr242);
340 +
341 + rt2800_bbp_write(rt2x00dev, 244, 0x00);
342 + bbpval = rt2800_bbp_read(rt2x00dev, 21);
343 + bbpval |= 0x1;
344 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
345 + usleep_range(10, 200);
346 + bbpval &= 0xfe;
347 + rt2800_bbp_write(rt2x00dev, 21, bbpval);
348 +
349 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1);
350 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2);
351 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
352 +
353 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0);
354 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19);
355 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3);
356 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4);
357 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17);
358 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18);
359 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19);
360 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20);
361 +
362 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0);
363 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19);
364 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3);
365 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4);
366 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17);
367 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18);
368 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19);
369 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20);
370 +
371 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
372 + udelay(1);
373 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
374 + udelay(1);
375 + rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0);
376 + udelay(1);
377 + rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0);
378 + rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1);
379 + rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1);
380 + rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3);
381 + rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3);
382 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
383 +}
384 +
385 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
386 bool set_bw, bool is_ht40)
387 {
388 @@ -9294,6 +9672,7 @@ static void rt2800_init_rfcsr_6352(struc
389 rt2800_rxdcoc_calibration(rt2x00dev);
390 rt2800_bw_filter_calibration(rt2x00dev, true);
391 rt2800_bw_filter_calibration(rt2x00dev, false);
392 + rt2800_rxiq_calibration(rt2x00dev);
393 }
394
395 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)