package/kernel/mac80211/patches/rt2x00/985-rt2x00-add-rxiq-calibration.patch

   1 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
   2 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
   3 @@ -8609,6 +8609,386 @@ void rt2800_rxdcoc_calibration(struct rt
   4  }
   5  EXPORT_SYMBOL_GPL(rt2800_rxdcoc_calibration);
   6
   7 +static u32 rt2800_do_sqrt_accumulation(u32 si) {
   8 +       u32 root, root_pre, bit;
   9 +       char i;
  10 +       bit = 1 << 15;
  11 +       root = 0;
  12 +       for (i = 15; i >= 0; i = i - 1) {
  13 +               root_pre = root + bit;
  14 +               if ((root_pre*root_pre) <= si)
  15 +                       root = root_pre;
  16 +               bit = bit >> 1;
  17 +       }
  18 +
  19 +       return root;
  20 +}
  21 +EXPORT_SYMBOL_GPL(rt2800_do_sqrt_accumulation);
  22 +
  23 +void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev) {
  24 +       u8 rfb0r1, rfb0r2, rfb0r42;
  25 +       u8 rfb4r0, rfb4r19;
  26 +       u8 rfb5r3, rfb5r4, rfb5r17, rfb5r18, rfb5r19, rfb5r20;
  27 +       u8 rfb6r0, rfb6r19;
  28 +       u8 rfb7r3, rfb7r4, rfb7r17, rfb7r18, rfb7r19, rfb7r20;
  29 +
  30 +       u8 bbp1, bbp4;
  31 +       u8 bbpr241, bbpr242;
  32 +       u32 i;
  33 +       u8 ch_idx;
  34 +       u8 bbpval;
  35 +       u8 rfval, vga_idx = 0;
  36 +       int mi = 0, mq = 0, si = 0, sq = 0, riq = 0;
  37 +       int sigma_i, sigma_q, r_iq, g_rx;
  38 +       int g_imb;
  39 +       int ph_rx;
  40 +       u32 savemacsysctrl = 0;
  41 +       u32 orig_RF_CONTROL0 = 0;
  42 +       u32 orig_RF_BYPASS0 = 0;
  43 +       u32 orig_RF_CONTROL1 = 0;
  44 +       u32 orig_RF_BYPASS1 = 0;
  45 +       u32 orig_RF_CONTROL3 = 0;
  46 +       u32 orig_RF_BYPASS3 = 0;
  47 +       u32 macstatus, bbpval1 = 0;
  48 +       u8 rf_vga_table[] = {0x20, 0x21, 0x22, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f};
  49 +
  50 +       savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  51 +       orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
  52 +       orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
  53 +       orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1);
  54 +       orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1);
  55 +       orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
  56 +       orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
  57 +
  58 +       bbp1 = rt2800_bbp_read(rt2x00dev, 1);
  59 +       bbp4 = rt2800_bbp_read(rt2x00dev, 4);
  60 +
  61 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0);
  62 +
  63 +       for (i = 0; i < 10000; i++) {
  64 +               macstatus = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
  65 +               if (macstatus & 0x3)
  66 +                       udelay(50);
  67 +               else
  68 +                       break;
  69 +       }
  70 +
  71 +       if (i == 10000)
  72 +               rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
  73 +
  74 +       bbpval = bbp4 & (~0x18);
  75 +       bbpval = bbp4 | 0x00;
  76 +       rt2800_bbp_write(rt2x00dev, 4, bbpval);
  77 +
  78 +       bbpval = rt2800_bbp_read(rt2x00dev, 21);
  79 +       bbpval = bbpval | 1;
  80 +       rt2800_bbp_write(rt2x00dev, 21, bbpval);
  81 +       bbpval = bbpval & 0xfe;
  82 +       rt2800_bbp_write(rt2x00dev, 21, bbpval);
  83 +
  84 +       rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202);
  85 +       rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303);
  86 +       if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
  87 +               rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101);
  88 +       } else {
  89 +               rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000);
  90 +       }
  91 +       rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1);
  92 +
  93 +       rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
  94 +       rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
  95 +       rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
  96 +       rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
  97 +       rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19);
  98 +       rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
  99 +       rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
 100 +       rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
 101 +       rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
 102 +       rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
 103 +       rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
 104 +
 105 +       rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
 106 +       rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19);
 107 +       rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
 108 +       rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
 109 +       rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
 110 +       rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
 111 +       rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
 112 +       rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
 113 +
 114 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87);
 115 +       rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27);
 116 +       rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38);
 117 +       rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38);
 118 +       rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80);
 119 +       rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1);
 120 +       rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60);
 121 +       rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
 122 +
 123 +       rt2800_bbp_write(rt2x00dev, 23, 0x0);
 124 +       rt2800_bbp_write(rt2x00dev, 24, 0x0);
 125 +
 126 +       rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0);
 127 +
 128 +       bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
 129 +       bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
 130 +
 131 +       rt2800_bbp_write(rt2x00dev, 241, 0x10);
 132 +       rt2800_bbp_write(rt2x00dev, 242, 0x84);
 133 +       rt2800_bbp_write(rt2x00dev, 244, 0x31);
 134 +
 135 +       bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3);
 136 +       bbpval = bbpval & (~0x7);
 137 +       rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval);
 138 +
 139 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
 140 +       udelay(1);
 141 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
 142 +       usleep_range(1, 200);
 143 +       rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376);
 144 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
 145 +       udelay(1);
 146 +       if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
 147 +               rt2800_bbp_write(rt2x00dev, 23, 0x06);
 148 +               rt2800_bbp_write(rt2x00dev, 24, 0x06);
 149 +       } else {
 150 +               rt2800_bbp_write(rt2x00dev, 23, 0x02);
 151 +               rt2800_bbp_write(rt2x00dev, 24, 0x02);
 152 +       }
 153 +
 154 +       for (ch_idx = 0; ch_idx < 2; ch_idx = ch_idx + 1) {
 155 +               if (ch_idx == 0) {
 156 +                       rfval = rfb0r1 & (~0x3);
 157 +                       rfval = rfb0r1 | 0x1;
 158 +                       rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
 159 +                       rfval = rfb0r2 & (~0x33);
 160 +                       rfval = rfb0r2 | 0x11;
 161 +                       rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
 162 +                       rfval = rfb0r42 & (~0x50);
 163 +                       rfval = rfb0r42 | 0x10;
 164 +                       rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
 165 +
 166 +                       rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
 167 +                       udelay(1);
 168 +
 169 +                       bbpval = bbp1 & (~ 0x18);
 170 +                       bbpval = bbpval | 0x00;
 171 +                       rt2800_bbp_write(rt2x00dev, 1, bbpval);
 172 +
 173 +                       rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00);
 174 +               } else {
 175 +                       rfval = rfb0r1 & (~0x3);
 176 +                       rfval = rfb0r1 | 0x2;
 177 +                       rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
 178 +                       rfval = rfb0r2 & (~0x33);
 179 +                       rfval = rfb0r2 | 0x22;
 180 +                       rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
 181 +                       rfval = rfb0r42 & (~0x50);
 182 +                       rfval = rfb0r42 | 0x40;
 183 +                       rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
 184 +
 185 +                       rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006);
 186 +                       udelay(1);
 187 +
 188 +                       bbpval = bbp1 & (~ 0x18);
 189 +                       bbpval = bbpval | 0x08;
 190 +                       rt2800_bbp_write(rt2x00dev, 1, bbpval);
 191 +
 192 +                       rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01);
 193 +               }
 194 +               udelay(500);
 195 +
 196 +               vga_idx = 0;
 197 +                       while (vga_idx < 11) {
 198 +                               rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]);
 199 +                               rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]);
 200 +
 201 +                               rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93);
 202 +
 203 +                               for (i = 0; i < 10000; i++) {
 204 +                                       bbpval = rt2800_bbp_read(rt2x00dev, 159);
 205 +                                       if ((bbpval & 0xff) == 0x93)
 206 +                                               udelay(50);
 207 +                                       else
 208 +                                               break;
 209 +                                       }
 210 +
 211 +                               if ((bbpval & 0xff) == 0x93) {
 212 +                                       rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish");
 213 +                                       goto restore_value;
 214 +                               }
 215 +
 216 +                               for (i = 0; i < 5; i++) {
 217 +                                       u32 bbptemp = 0;
 218 +                                       u8 value = 0;
 219 +                                       int result = 0;
 220 +
 221 +                                       rt2800_bbp_write(rt2x00dev, 158, 0x1e);
 222 +                                       rt2800_bbp_write(rt2x00dev, 159, i);
 223 +                                       rt2800_bbp_write(rt2x00dev, 158, 0x22);
 224 +                                       value = rt2800_bbp_read(rt2x00dev, 159);
 225 +                                       bbptemp = bbptemp + (value << 24);
 226 +                                       rt2800_bbp_write(rt2x00dev, 158, 0x21);
 227 +                                       value = rt2800_bbp_read(rt2x00dev, 159);
 228 +                                       bbptemp = bbptemp + (value << 16);
 229 +                                       rt2800_bbp_write(rt2x00dev, 158, 0x20);
 230 +                                       value = rt2800_bbp_read(rt2x00dev, 159);
 231 +                                       bbptemp = bbptemp + (value << 8);
 232 +                                       rt2800_bbp_write(rt2x00dev, 158, 0x1f);
 233 +                                       value = rt2800_bbp_read(rt2x00dev, 159);
 234 +                                       bbptemp = bbptemp + value;
 235 +
 236 +                                       if ((i < 2) && (bbptemp & 0x800000))
 237 +                                               result = (bbptemp & 0xffffff) - 0x1000000;
 238 +                                       else if (i == 4)
 239 +                                               result = bbptemp;
 240 +                                       else
 241 +                                               result = bbptemp;
 242 +
 243 +                                       if (i == 0)
 244 +                                               mi = result/4096;
 245 +                                       else if (i == 1)
 246 +                                               mq = result/4096;
 247 +                                       else if (i == 2)
 248 +                                               si = bbptemp/4096;
 249 +                                       else if (i == 3)
 250 +                                               sq = bbptemp/4096;
 251 +                                       else
 252 +                                               riq = result/4096;
 253 +                               }
 254 +
 255 +                               bbpval1 = si - mi*mi;
 256 +                               rt2x00_dbg(rt2x00dev, "RXIQ si=%d, sq=%d, riq=%d, bbpval %d, vga_idx %d", si, sq, riq, bbpval1, vga_idx);
 257 +
 258 +                               if (bbpval1 >= (100*100))
 259 +                                       break;
 260 +
 261 +                               if (bbpval1 <= 100)
 262 +                                       vga_idx = vga_idx + 9;
 263 +                               else if (bbpval1 <= 158)
 264 +                                       vga_idx = vga_idx + 8;
 265 +                               else if (bbpval1 <= 251)
 266 +                                       vga_idx = vga_idx + 7;
 267 +                               else if (bbpval1 <= 398)
 268 +                                       vga_idx = vga_idx + 6;
 269 +                               else if (bbpval1 <= 630)
 270 +                                       vga_idx = vga_idx + 5;
 271 +                               else if (bbpval1 <= 1000)
 272 +                                       vga_idx = vga_idx + 4;
 273 +                               else if (bbpval1 <= 1584)
 274 +                                       vga_idx = vga_idx + 3;
 275 +                               else if (bbpval1 <= 2511)
 276 +                                       vga_idx = vga_idx + 2;
 277 +                               else
 278 +                                       vga_idx = vga_idx + 1;
 279 +                       }
 280 +
 281 +               sigma_i = rt2800_do_sqrt_accumulation(100*(si - mi*mi));
 282 +               sigma_q = rt2800_do_sqrt_accumulation(100*(sq - mq*mq));
 283 +               r_iq = 10*(riq-(mi*mq));
 284 +
 285 +               rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq);
 286 +
 287 +               if (((sigma_i <= 1400 ) && (sigma_i >= 1000))
 288 +                       && ((sigma_i - sigma_q) <= 112)
 289 +                       && ((sigma_i - sigma_q) >= -112)
 290 +                       && ((mi <= 32) && (mi >= -32))
 291 +                       && ((mq <= 32) && (mq >= -32))) {
 292 +                               r_iq = 10*(riq-(mi*mq));
 293 +                               rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", sigma_i, sigma_q, r_iq);
 294 +
 295 +                               g_rx = (1000 * sigma_q) / sigma_i;
 296 +                               g_imb = ((-2) * 128 * (1000 - g_rx)) / (1000 + g_rx);
 297 +                               ph_rx = (r_iq * 2292) / (sigma_i * sigma_q);
 298 +                               rt2x00_info(rt2x00dev, "RXIQ G_imb=%d, Ph_rx=%d\n", g_imb, ph_rx);
 299 +
 300 +                               if ((ph_rx > 20) || (ph_rx < -20)) {
 301 +                                       ph_rx = 0;
 302 +                                       rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
 303 +                               }
 304 +
 305 +                               if ((g_imb > 12) || (g_imb < -12)) {
 306 +                                       g_imb = 0;
 307 +                                       rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
 308 +                               }
 309 +                       }
 310 +               else {
 311 +                       g_imb = 0;
 312 +                       ph_rx = 0;
 313 +                       rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n", sigma_i, sigma_q, r_iq);
 314 +                       rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
 315 +               }
 316 +
 317 +               if (ch_idx == 0) {
 318 +                       rt2800_bbp_write(rt2x00dev, 158, 0x37);
 319 +                       rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
 320 +                       rt2800_bbp_write(rt2x00dev, 158, 0x35);
 321 +                       rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
 322 +               } else {
 323 +                       rt2800_bbp_write(rt2x00dev, 158, 0x55);
 324 +                       rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
 325 +                       rt2800_bbp_write(rt2x00dev, 158, 0x53);
 326 +                       rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
 327 +               }
 328 +       }
 329 +
 330 +restore_value:
 331 +       rt2800_bbp_write(rt2x00dev, 158, 0x3);
 332 +       bbpval = rt2800_bbp_read(rt2x00dev, 159);
 333 +       rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07));
 334 +
 335 +       rt2800_bbp_write(rt2x00dev, 158, 0x00);
 336 +       rt2800_bbp_write(rt2x00dev, 159, 0x00);
 337 +       rt2800_bbp_write(rt2x00dev, 1, bbp1);
 338 +       rt2800_bbp_write(rt2x00dev, 4, bbp4);
 339 +       rt2800_bbp_write(rt2x00dev, 241, bbpr241);
 340 +       rt2800_bbp_write(rt2x00dev, 242, bbpr242);
 341 +
 342 +       rt2800_bbp_write(rt2x00dev, 244, 0x00);
 343 +       bbpval = rt2800_bbp_read(rt2x00dev, 21);
 344 +       bbpval = (bbpval | 0x1);
 345 +       rt2800_bbp_write(rt2x00dev, 21, bbpval);
 346 +       usleep_range(10, 200);
 347 +       bbpval = (bbpval & 0xfe);
 348 +       rt2800_bbp_write(rt2x00dev, 21, bbpval);
 349 +
 350 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1);
 351 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2);
 352 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
 353 +
 354 +       rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0);
 355 +       rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19);
 356 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3);
 357 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4);
 358 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17);
 359 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18);
 360 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19);
 361 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20);
 362 +
 363 +       rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0);
 364 +       rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19);
 365 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3);
 366 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4);
 367 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17);
 368 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18);
 369 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19);
 370 +       rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20);
 371 +
 372 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
 373 +       udelay(1);
 374 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
 375 +       udelay(1);
 376 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0);
 377 +       udelay(1);
 378 +       rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0);
 379 +       rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1);
 380 +       rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1);
 381 +       rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3);
 382 +       rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3);
 383 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
 384 +}
 385 +EXPORT_SYMBOL_GPL(rt2800_rxiq_calibration);
 386 +
 387  static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
 388                                        bool set_bw, bool is_ht40)
 389  {
 390 @@ -9221,6 +9601,7 @@ static void rt2800_init_rfcsr_6352(struc
 391         rt2800_rxdcoc_calibration(rt2x00dev);
 392         rt2800_bw_filter_calibration(rt2x00dev, true);
 393         rt2800_bw_filter_calibration(rt2x00dev, false);
 394 +       rt2800_rxiq_calibration(rt2x00dev);
 395  }
 396
 397  static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
 398 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
 399 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
 400 @@ -236,6 +236,7 @@ void rt2800_rf_self_txdc_cal(struct rt2x
 401  int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2);
 402  void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev);
 403  void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev);
 404 +void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev);
 405
 406  int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev);
 407  void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev);
 408 --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h
 409 +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
 410 @@ -565,6 +565,7 @@ struct rt2x00lib_ops {
 411         int (*calcrcalibrationcode) (struct rt2x00_dev *rt2x00dev, int d1, int d2);
 412         void (*r_calibration) (struct rt2x00_dev *rt2x00dev);
 413         void (*rxdcoc_calibration) (struct rt2x00_dev *rt2x00dev);
 414 +       void (*rxiq_calibration) (struct rt2x00_dev *rt2x00dev);
 415
 416         /*
 417          * Data queue handlers.