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d3118ebb3b81846aaeb5ba1bfda3e69cf9521e60
[openwrt/openwrt.git] / package / kernel / mac80211 / patches / rt2x00 / 986-rt2x00-add-TX-LOFT-calibration.patch
1 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
2 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
3 @@ -8989,6 +8989,954 @@ restore_value:
4 }
5 EXPORT_SYMBOL_GPL(rt2800_rxiq_calibration);
6
7 +static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev, rf_reg_pair rf_reg_record[][13], u8 chain)
8 +{
9 + u8 rfvalue = 0;
10 +
11 + if (chain == CHAIN_0) {
12 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
13 + rf_reg_record[CHAIN_0][0].bank = 0;
14 + rf_reg_record[CHAIN_0][0].reg = 1;
15 + rf_reg_record[CHAIN_0][0].value = rfvalue;
16 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
17 + rf_reg_record[CHAIN_0][1].bank = 0;
18 + rf_reg_record[CHAIN_0][1].reg = 2;
19 + rf_reg_record[CHAIN_0][1].value = rfvalue;
20 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
21 + rf_reg_record[CHAIN_0][2].bank = 0;
22 + rf_reg_record[CHAIN_0][2].reg = 35;
23 + rf_reg_record[CHAIN_0][2].value = rfvalue;
24 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
25 + rf_reg_record[CHAIN_0][3].bank = 0;
26 + rf_reg_record[CHAIN_0][3].reg = 42;
27 + rf_reg_record[CHAIN_0][3].value = rfvalue;
28 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
29 + rf_reg_record[CHAIN_0][4].bank = 4;
30 + rf_reg_record[CHAIN_0][4].reg = 0;
31 + rf_reg_record[CHAIN_0][4].value = rfvalue;
32 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);
33 + rf_reg_record[CHAIN_0][5].bank = 4;
34 + rf_reg_record[CHAIN_0][5].reg = 2;
35 + rf_reg_record[CHAIN_0][5].value = rfvalue;
36 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);
37 + rf_reg_record[CHAIN_0][6].bank = 4;
38 + rf_reg_record[CHAIN_0][6].reg = 34;
39 + rf_reg_record[CHAIN_0][6].value = rfvalue;
40 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
41 + rf_reg_record[CHAIN_0][7].bank = 5;
42 + rf_reg_record[CHAIN_0][7].reg = 3;
43 + rf_reg_record[CHAIN_0][7].value = rfvalue;
44 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
45 + rf_reg_record[CHAIN_0][8].bank = 5;
46 + rf_reg_record[CHAIN_0][8].reg = 4;
47 + rf_reg_record[CHAIN_0][8].value = rfvalue;
48 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
49 + rf_reg_record[CHAIN_0][9].bank = 5;
50 + rf_reg_record[CHAIN_0][9].reg = 17;
51 + rf_reg_record[CHAIN_0][9].value = rfvalue;
52 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
53 + rf_reg_record[CHAIN_0][10].bank = 5;
54 + rf_reg_record[CHAIN_0][10].reg = 18;
55 + rf_reg_record[CHAIN_0][10].value = rfvalue;
56 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
57 + rf_reg_record[CHAIN_0][11].bank = 5;
58 + rf_reg_record[CHAIN_0][11].reg = 19;
59 + rf_reg_record[CHAIN_0][11].value = rfvalue;
60 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
61 + rf_reg_record[CHAIN_0][12].bank = 5;
62 + rf_reg_record[CHAIN_0][12].reg = 20;
63 + rf_reg_record[CHAIN_0][12].value = rfvalue;
64 + } else if (chain == CHAIN_1) {
65 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
66 + rf_reg_record[CHAIN_1][0].bank = 0;
67 + rf_reg_record[CHAIN_1][0].reg = 1;
68 + rf_reg_record[CHAIN_1][0].value = rfvalue;
69 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
70 + rf_reg_record[CHAIN_1][1].bank = 0;
71 + rf_reg_record[CHAIN_1][1].reg = 2;
72 + rf_reg_record[CHAIN_1][1].value = rfvalue;
73 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
74 + rf_reg_record[CHAIN_1][2].bank = 0;
75 + rf_reg_record[CHAIN_1][2].reg = 35;
76 + rf_reg_record[CHAIN_1][2].value = rfvalue;
77 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
78 + rf_reg_record[CHAIN_1][3].bank = 0;
79 + rf_reg_record[CHAIN_1][3].reg = 42;
80 + rf_reg_record[CHAIN_1][3].value = rfvalue;
81 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
82 + rf_reg_record[CHAIN_1][4].bank = 6;
83 + rf_reg_record[CHAIN_1][4].reg = 0;
84 + rf_reg_record[CHAIN_1][4].value = rfvalue;
85 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);
86 + rf_reg_record[CHAIN_1][5].bank = 6;
87 + rf_reg_record[CHAIN_1][5].reg = 2;
88 + rf_reg_record[CHAIN_1][5].value = rfvalue;
89 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);
90 + rf_reg_record[CHAIN_1][6].bank = 6;
91 + rf_reg_record[CHAIN_1][6].reg = 34;
92 + rf_reg_record[CHAIN_1][6].value = rfvalue;
93 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
94 + rf_reg_record[CHAIN_1][7].bank = 7;
95 + rf_reg_record[CHAIN_1][7].reg = 3;
96 + rf_reg_record[CHAIN_1][7].value = rfvalue;
97 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
98 + rf_reg_record[CHAIN_1][8].bank = 7;
99 + rf_reg_record[CHAIN_1][8].reg = 4;
100 + rf_reg_record[CHAIN_1][8].value = rfvalue;
101 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
102 + rf_reg_record[CHAIN_1][9].bank = 7;
103 + rf_reg_record[CHAIN_1][9].reg = 17;
104 + rf_reg_record[CHAIN_1][9].value = rfvalue;
105 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
106 + rf_reg_record[CHAIN_1][10].bank = 7;
107 + rf_reg_record[CHAIN_1][10].reg = 18;
108 + rf_reg_record[CHAIN_1][10].value = rfvalue;
109 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
110 + rf_reg_record[CHAIN_1][11].bank = 7;
111 + rf_reg_record[CHAIN_1][11].reg = 19;
112 + rf_reg_record[CHAIN_1][11].value = rfvalue;
113 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
114 + rf_reg_record[CHAIN_1][12].bank = 7;
115 + rf_reg_record[CHAIN_1][12].reg = 20;
116 + rf_reg_record[CHAIN_1][12].value = rfvalue;
117 + } else {
118 + rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain);
119 + return;
120 + }
121 +
122 + return;
123 +}
124 +EXPORT_SYMBOL_GPL(rt2800_rf_configstore);
125 +
126 +static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev, rf_reg_pair rf_record[][13])
127 +{
128 + u8 chain_index = 0, record_index = 0;
129 + u8 bank = 0, rf_register = 0, value = 0;
130 +
131 + for (chain_index = 0; chain_index < 2; chain_index++) {
132 + for (record_index = 0; record_index < 13; record_index++) {
133 + bank = rf_record[chain_index][record_index].bank;
134 + rf_register = rf_record[chain_index][record_index].reg;
135 + value = rf_record[chain_index][record_index].value;
136 + rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
137 + rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n", bank, rf_register, value);
138 + }
139 + }
140 +
141 + return;
142 +}
143 +EXPORT_SYMBOL_GPL(rt2800_rf_configrecover);
144 +
145 +static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)
146 +{
147 + rt2800_bbp_write(rt2x00dev, 158, 0xAA);
148 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
149 +
150 + rt2800_bbp_write(rt2x00dev, 158, 0xAB);
151 + rt2800_bbp_write(rt2x00dev, 159, 0x0A);
152 +
153 + rt2800_bbp_write(rt2x00dev, 158, 0xAC);
154 + rt2800_bbp_write(rt2x00dev, 159, 0x3F);
155 +
156 + rt2800_bbp_write(rt2x00dev, 158, 0xAD);
157 + rt2800_bbp_write(rt2x00dev, 159, 0x3F);
158 +
159 + rt2800_bbp_write(rt2x00dev, 244, 0x40);
160 +
161 + return;
162 +}
163 +EXPORT_SYMBOL_GPL(rt2800_setbbptonegenerator);
164 +
165 +u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)
166 +{
167 + u32 macvalue = 0;
168 + int fftout_i = 0, fftout_q = 0;
169 + u32 ptmp=0, pint = 0;
170 + u8 bbp = 0;
171 + u8 tidxi;
172 +
173 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
174 + rt2800_bbp_write(rt2x00dev, 159, 0x9b);
175 +
176 + bbp = 0x9b;
177 +
178 + while (bbp == 0x9b) {
179 + udelay(10);
180 + bbp = rt2800_bbp_read(rt2x00dev, 159);
181 + bbp = bbp & 0xff;
182 + }
183 +
184 + rt2800_bbp_write(rt2x00dev, 158, 0xba);
185 + rt2800_bbp_write(rt2x00dev, 159, tidx);
186 + rt2800_bbp_write(rt2x00dev, 159, tidx);
187 + rt2800_bbp_write(rt2x00dev, 159, tidx);
188 +
189 + macvalue = rt2800_register_read(rt2x00dev, 0x057C);
190 +
191 + fftout_i = (macvalue >> 16);
192 + fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
193 + fftout_q = (macvalue & 0xffff);
194 + fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
195 + ptmp = (fftout_i * fftout_i);
196 + ptmp = ptmp + (fftout_q * fftout_q);
197 + pint = ptmp;
198 + rt2x00_dbg(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint);
199 + if (read_neg) {
200 + pint = pint >> 1;
201 + tidxi = 0x40 - tidx;
202 + tidxi = tidxi & 0x3f;
203 +
204 + rt2800_bbp_write(rt2x00dev, 158, 0xba);
205 + rt2800_bbp_write(rt2x00dev, 159, tidxi);
206 + rt2800_bbp_write(rt2x00dev, 159, tidxi);
207 + rt2800_bbp_write(rt2x00dev, 159, tidxi);
208 +
209 + macvalue = rt2800_register_read(rt2x00dev, 0x057C);
210 +
211 + fftout_i = (macvalue >> 16);
212 + fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
213 + fftout_q = (macvalue & 0xffff);
214 + fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
215 + ptmp = (fftout_i * fftout_i);
216 + ptmp = ptmp + (fftout_q * fftout_q);
217 + ptmp = ptmp >> 1;
218 + pint = pint + ptmp;
219 + }
220 +
221 + return pint;
222 +}
223 +EXPORT_SYMBOL_GPL(rt2800_do_fft_accumulation);
224 +
225 +u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx) {
226 + u32 macvalue = 0;
227 + int fftout_i = 0, fftout_q = 0;
228 + u32 ptmp=0, pint = 0;
229 +
230 + rt2800_bbp_write(rt2x00dev, 158, 0xBA);
231 + rt2800_bbp_write(rt2x00dev, 159, tidx);
232 + rt2800_bbp_write(rt2x00dev, 159, tidx);
233 + rt2800_bbp_write(rt2x00dev, 159, tidx);
234 +
235 + macvalue = rt2800_register_read(rt2x00dev, 0x057C);
236 +
237 + fftout_i = (macvalue >> 16);
238 + fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
239 + fftout_q = (macvalue & 0xffff);
240 + fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
241 + ptmp = (fftout_i * fftout_i);
242 + ptmp = ptmp + (fftout_q * fftout_q);
243 + pint = ptmp;
244 + rt2x00_info(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint);
245 +
246 + return pint;
247 +}
248 +EXPORT_SYMBOL_GPL(rt2800_read_fft_accumulation);
249 +
250 +static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)
251 +{
252 + u8 bbp = 0;
253 +
254 + rt2800_bbp_write(rt2x00dev, 158, 0xb0);
255 + bbp = alc | 0x80;
256 + rt2800_bbp_write(rt2x00dev, 159, bbp);
257 +
258 + if (ch_idx == 0)
259 + bbp = (iorq == 0) ? 0xb1: 0xb2;
260 + else
261 + bbp = (iorq == 0) ? 0xb8: 0xb9;
262 +
263 + rt2800_bbp_write(rt2x00dev, 158, bbp);
264 + bbp = dc;
265 + rt2800_bbp_write(rt2x00dev, 159, bbp);
266 +
267 + return;
268 +}
269 +EXPORT_SYMBOL_GPL(rt2800_write_dc);
270 +
271 +static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
272 +{
273 + u32 p0 = 0, p1 = 0, pf = 0;
274 + char idx0 = 0, idx1 = 0;
275 + u8 idxf[] = {0x00, 0x00};
276 + u8 ibit = 0x20;
277 + u8 iorq;
278 + char bidx;
279 +
280 + rt2800_bbp_write(rt2x00dev, 158, 0xb0);
281 + rt2800_bbp_write(rt2x00dev, 159, 0x80);
282 +
283 + for (bidx = 5; bidx >= 0; bidx--) {
284 + for (iorq = 0; iorq <= 1; iorq++) {
285 + rt2x00_dbg(rt2x00dev, "\n========================================================\n");
286 +
287 + if (idxf[iorq] == 0x20) {
288 + idx0 = 0x20;
289 + p0 = pf;
290 + } else {
291 + idx0 = idxf[iorq] - ibit;
292 + idx0 = idx0 & 0x3F;
293 + rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);
294 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
295 + }
296 +
297 + idx1 = idxf[iorq] + ((bidx == 5) ? 0 : ibit);
298 + idx1 = idx1 & 0x3F;
299 + rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
300 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
301 +
302 + rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n", alc_idx, iorq, idxf[iorq]);
303 + rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x !\n", p0, p1, pf, idx0, idx1, ibit);
304 +
305 + if ((bidx != 5) && (pf <= p0) && (pf < p1)) {
306 + pf = pf;
307 + idxf[iorq] = idxf[iorq];
308 + } else if (p0 < p1) {
309 + pf = p0;
310 + idxf[iorq] = idx0 & 0x3F;
311 + } else {
312 + pf = p1;
313 + idxf[iorq] = idx1 & 0x3F;
314 + }
315 + rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n", iorq, iorq, idxf[iorq], pf);
316 +
317 + rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);
318 +
319 + }
320 + ibit = ibit >> 1;
321 + }
322 + dc_result[ch_idx][alc_idx][0] = idxf[0];
323 + dc_result[ch_idx][alc_idx][1] = idxf[1];
324 +
325 + return;
326 +}
327 +EXPORT_SYMBOL_GPL(rt2800_loft_search);
328 +
329 +static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
330 +{
331 + u32 p0 = 0, p1 = 0, pf = 0;
332 + char perr = 0, gerr = 0, iq_err = 0;
333 + char pef = 0, gef = 0;
334 + char psta, pend;
335 + char gsta, gend;
336 +
337 + u8 ibit = 0x20;
338 + u8 first_search = 0x00, touch_neg_max = 0x00;
339 + char idx0 = 0, idx1 = 0;
340 + u8 gop;
341 + u8 bbp = 0;
342 + char bidx;
343 +
344 + rt2x00_info(rt2x00dev, "IQCalibration Start!\n");
345 + for (bidx = 5; bidx >= 1; bidx--) {
346 + for (gop = 0; gop < 2; gop++) {
347 + rt2x00_dbg(rt2x00dev, "\n========================================================\n");
348 +
349 + if ((gop == 1) || (bidx < 4)) {
350 + if (gop == 0)
351 + iq_err = gerr;
352 + else
353 + iq_err = perr;
354 +
355 + first_search = (gop == 0) ? (bidx == 3) : (bidx == 5);
356 + touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) : ((iq_err & 0x3F) == 0x20);
357 +
358 + if (touch_neg_max) {
359 + p0 = pf;
360 + idx0 = iq_err;
361 + } else {
362 + idx0 = iq_err - ibit;
363 + bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29): ((gop == 0) ? 0x46 : 0x47);
364 +
365 + rt2800_bbp_write(rt2x00dev, 158, bbp);
366 + rt2800_bbp_write(rt2x00dev, 159, idx0);
367 +
368 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
369 + }
370 +
371 + idx1 = iq_err + (first_search ? 0 : ibit);
372 + idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F);
373 +
374 + bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : (gop == 0) ? 0x46 : 0x47;
375 +
376 + rt2800_bbp_write(rt2x00dev, 158, bbp);
377 + rt2800_bbp_write(rt2x00dev, 159, idx1);
378 +
379 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
380 +
381 + rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x !\n", p0, p1, pf, idx0, idx1, iq_err, gop, ibit);
382 +
383 + if ((!first_search) && (pf <= p0) && (pf < p1)) {
384 + pf = pf;
385 + } else if (p0 < p1) {
386 + pf = p0;
387 + iq_err = idx0;
388 + } else {
389 + pf = p1;
390 + iq_err = idx1;
391 + }
392 +
393 + bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : (gop == 0) ? 0x46 : 0x47;
394 +
395 + rt2800_bbp_write(rt2x00dev, 158, bbp);
396 + rt2800_bbp_write(rt2x00dev, 159, iq_err);
397 +
398 + if (gop == 0)
399 + gerr = iq_err;
400 + else
401 + perr = iq_err;
402 +
403 + rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n", pf, gerr & 0x0F, perr & 0x3F);
404 +
405 + }
406 + }
407 +
408 + if (bidx > 0)
409 + ibit = (ibit >> 1);
410 + }
411 + gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
412 + perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
413 +
414 + gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
415 + gsta = gerr - 1;
416 + gend = gerr + 2;
417 +
418 + perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
419 + psta = perr - 1;
420 + pend = perr + 2;
421 +
422 + for (gef = gsta; gef <= gend; gef = gef + 1)
423 + for (pef = psta; pef <= pend; pef = pef + 1) {
424 + bbp = (ch_idx == 0) ? 0x28 : 0x46;
425 + rt2800_bbp_write(rt2x00dev, 158, bbp);
426 + rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
427 +
428 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
429 + rt2800_bbp_write(rt2x00dev, 158, bbp);
430 + rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
431 +
432 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
433 + if ((gef == gsta) && (pef == psta)) {
434 + pf = p1;
435 + gerr = gef;
436 + perr = pef;
437 + }
438 + else if (pf > p1){
439 + pf = p1;
440 + gerr = gef;
441 + perr = pef;
442 + }
443 + rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n", p1, pf, gef & 0x0F, pef & 0x3F);
444 + }
445 +
446 + ges[ch_idx] = gerr & 0x0F;
447 + pes[ch_idx] = perr & 0x3F;
448 +
449 + rt2x00_info(rt2x00dev, "IQCalibration Done! CH = %u, (gain=%2x, phase=%2x)\n", ch_idx, gerr & 0x0F, perr & 0x3F);
450 +
451 + return;
452 +}
453 +EXPORT_SYMBOL_GPL(rt2800_iq_search);
454 +
455 +static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)
456 +{
457 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);
458 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);
459 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
460 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);
461 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);
462 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);
463 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);
464 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);
465 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);
466 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
467 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);
468 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);
469 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
470 +}
471 +EXPORT_SYMBOL_GPL(rt2800_rf_aux_tx0_loopback);
472 +
473 +static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)
474 +{
475 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);
476 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);
477 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
478 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);
479 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);
480 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);
481 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);
482 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);
483 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);
484 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);
485 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);
486 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);
487 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);
488 +}
489 +EXPORT_SYMBOL_GPL(rt2800_rf_aux_tx1_loopback);
490 +
491 +void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
492 +{
493 + rf_reg_pair rf_store[CHAIN_NUM][13];
494 + u32 macorg1 = 0;
495 + u32 macorg2 = 0;
496 + u32 macorg3 = 0;
497 + u32 macorg4 = 0;
498 + u32 macorg5 = 0;
499 + u32 orig528 = 0;
500 + u32 orig52c = 0;
501 +
502 + u32 savemacsysctrl = 0, mtxcycle = 0;
503 + u32 macvalue = 0;
504 + u32 mac13b8 = 0;
505 + u32 p0 = 0, p1 = 0;
506 + u32 p0_idx10 = 0, p1_idx10 = 0;
507 +
508 + u8 rfvalue;
509 + u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];
510 + u8 ger[CHAIN_NUM], per[CHAIN_NUM];
511 + u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
512 + u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
513 +
514 + u8 vga_gain[] = {14, 14};
515 + u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
516 + u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
517 + u8 bbpr30, rfb0r39, rfb0r42;
518 + u8 bbpr1;
519 + u8 bbpr4;
520 + u8 bbpr241, bbpr242;
521 + u8 count_step;
522 +
523 + savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
524 + macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
525 + macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
526 + macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
527 + macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
528 + macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
529 + mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
530 + orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
531 + orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
532 +
533 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
534 + macvalue &= (~0x04);
535 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
536 +
537 + for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
538 + macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
539 + if (macvalue & 0x01)
540 + udelay(50);
541 + else
542 + break;
543 + }
544 +
545 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
546 + macvalue &= (~0x08);
547 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
548 +
549 + for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
550 + macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
551 + if (macvalue & 0x02)
552 + udelay(50);
553 + else
554 + break;
555 + }
556 +
557 + for (ch_idx = 0; ch_idx < 2; ch_idx++) {
558 + rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
559 + }
560 +
561 + bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
562 + rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
563 + rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
564 +
565 + rt2800_bbp_write(rt2x00dev, 30, 0x1F);
566 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
567 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
568 +
569 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
570 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
571 +
572 + rt2800_setbbptonegenerator(rt2x00dev);
573 +
574 + for (ch_idx = 0; ch_idx < 2; ch_idx ++) {
575 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
576 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
577 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
578 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
579 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
580 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
581 + rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
582 + udelay(1);
583 +
584 + if (ch_idx == 0) {
585 + rt2800_rf_aux_tx0_loopback(rt2x00dev);
586 + } else {
587 + rt2800_rf_aux_tx1_loopback(rt2x00dev);
588 + }
589 + udelay(1);
590 +
591 + if (ch_idx == 0) {
592 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
593 + } else {
594 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
595 + }
596 +
597 + rt2800_bbp_write(rt2x00dev, 158, 0x05);
598 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
599 +
600 + rt2800_bbp_write(rt2x00dev, 158, 0x01);
601 + if (ch_idx == 0)
602 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
603 + else
604 + rt2800_bbp_write(rt2x00dev, 159, 0x01);
605 +
606 + vga_gain[ch_idx] = 18;
607 + for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
608 + rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
609 + rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
610 +
611 + macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
612 + macvalue &= (~0x0000F1F1);
613 + macvalue |= (rf_gain[rf_alc_idx] << 4);
614 + macvalue |= (rf_gain[rf_alc_idx] << 12);
615 + rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
616 + macvalue = (0x0000F1F1);
617 + rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
618 +
619 + if (rf_alc_idx == 0) {
620 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
621 + for (;vga_gain[ch_idx] > 0;vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
622 + rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
623 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
624 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
625 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
626 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
627 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
628 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
629 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
630 + rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
631 + if ((p0 < 7000*7000) && (p1 < (7000*7000))) {
632 + break;
633 + }
634 + }
635 +
636 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
637 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
638 +
639 + rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
640 +
641 + if (vga_gain[ch_idx] < 0)
642 + vga_gain[ch_idx] = 0;
643 + }
644 +
645 + rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
646 +
647 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
648 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
649 +
650 + rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
651 + }
652 + }
653 +
654 + for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
655 + for (idx = 0; idx < 4; idx++) {
656 + rt2800_bbp_write(rt2x00dev, 158, 0xB0);
657 + bbp = (idx<<2) + rf_alc_idx;
658 + rt2800_bbp_write(rt2x00dev, 159, bbp);
659 + rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
660 +
661 + rt2800_bbp_write(rt2x00dev, 158, 0xb1);
662 + bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
663 + bbp = bbp & 0x3F;
664 + rt2800_bbp_write(rt2x00dev, 159, bbp);
665 + rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
666 +
667 + rt2800_bbp_write(rt2x00dev, 158, 0xb2);
668 + bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
669 + bbp = bbp & 0x3F;
670 + rt2800_bbp_write(rt2x00dev, 159, bbp);
671 + rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
672 +
673 + rt2800_bbp_write(rt2x00dev, 158, 0xb8);
674 + bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
675 + bbp = bbp & 0x3F;
676 + rt2800_bbp_write(rt2x00dev, 159, bbp);
677 + rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
678 +
679 + rt2800_bbp_write(rt2x00dev, 158, 0xb9);
680 + bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
681 + bbp = bbp & 0x3F;
682 + rt2800_bbp_write(rt2x00dev, 159, bbp);
683 + rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
684 + }
685 + }
686 +
687 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
688 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
689 +
690 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
691 +
692 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
693 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
694 +
695 + bbp = 0x00;
696 + rt2800_bbp_write(rt2x00dev, 244, 0x00);
697 +
698 + rt2800_bbp_write(rt2x00dev, 21, 0x01);
699 + udelay(1);
700 + rt2800_bbp_write(rt2x00dev, 21, 0x00);
701 +
702 + rt2800_rf_configrecover(rt2x00dev, rf_store);
703 +
704 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
705 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
706 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
707 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
708 + rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
709 + udelay(1);
710 + rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
711 + rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
712 + rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
713 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
714 + rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
715 + rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
716 + rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
717 +
718 + rt2x00_info(rt2x00dev, "LOFT Calibration Done!\n");
719 +
720 + savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
721 + macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
722 + macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
723 + macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
724 + macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
725 + macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
726 +
727 + bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
728 + bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
729 + bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
730 + bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
731 + mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
732 +
733 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
734 + macvalue &= (~0x04);
735 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
736 + for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
737 + macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
738 + if (macvalue & 0x01)
739 + udelay(50);
740 + else
741 + break;
742 + }
743 +
744 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
745 + macvalue &= (~0x08);
746 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
747 + for (mtxcycle = 0; mtxcycle < 10000; mtxcycle++) {
748 + macvalue = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
749 + if (macvalue & 0x02)
750 + udelay(50);
751 + else
752 + break;
753 + }
754 +
755 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
756 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
757 + rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
758 + }
759 +
760 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
761 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
762 +
763 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
764 + rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
765 + rt2800_bbp_write(rt2x00dev, 21, 0x01);
766 + udelay(1);
767 + rt2800_bbp_write(rt2x00dev, 21, 0x00);
768 +
769 + rt2800_bbp_write(rt2x00dev, 241, 0x14);
770 + rt2800_bbp_write(rt2x00dev, 242, 0x80);
771 + rt2800_bbp_write(rt2x00dev, 244, 0x31);
772 + } else {
773 + rt2800_setbbptonegenerator(rt2x00dev);
774 + }
775 +
776 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
777 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
778 + udelay(1);
779 +
780 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
781 +
782 + if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
783 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
784 + rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
785 + }
786 +
787 + rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
788 +
789 + for (ch_idx = 0; ch_idx < 2; ch_idx++) {
790 + rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
791 + }
792 +
793 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
794 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
795 +
796 + rt2800_bbp_write(rt2x00dev, 158, 0x03);
797 + rt2800_bbp_write(rt2x00dev, 159, 0x60);
798 + rt2800_bbp_write(rt2x00dev, 158, 0xB0);
799 + rt2800_bbp_write(rt2x00dev, 159, 0x80);
800 +
801 + for (ch_idx = 0; ch_idx < 2; ch_idx ++) {
802 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
803 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
804 +
805 + if (ch_idx == 0) {
806 + rt2800_bbp_write(rt2x00dev, 158, 0x01);
807 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
808 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
809 + bbp = bbpr1 & (~0x18);
810 + bbp = bbp | 0x00;
811 + rt2800_bbp_write(rt2x00dev, 1, bbp);
812 + }
813 + rt2800_rf_aux_tx0_loopback(rt2x00dev);
814 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
815 + } else {
816 + rt2800_bbp_write(rt2x00dev, 158, 0x01);
817 + rt2800_bbp_write(rt2x00dev, 159, 0x01);
818 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
819 + bbp = bbpr1 & (~0x18);
820 + bbp = bbp | 0x08;
821 + rt2800_bbp_write(rt2x00dev, 1, bbp);
822 + }
823 + rt2800_rf_aux_tx1_loopback(rt2x00dev);
824 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
825 + }
826 +
827 + rt2800_bbp_write(rt2x00dev, 158, 0x05);
828 + rt2800_bbp_write(rt2x00dev, 159, 0x04);
829 +
830 + bbp = (ch_idx == 0) ? 0x28 : 0x46;
831 + rt2800_bbp_write(rt2x00dev, 158, bbp);
832 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
833 +
834 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
835 + rt2800_bbp_write(rt2x00dev, 23, 0x06);
836 + rt2800_bbp_write(rt2x00dev, 24, 0x06);
837 + count_step = 1;
838 + } else {
839 + rt2800_bbp_write(rt2x00dev, 23, 0x1F);
840 + rt2800_bbp_write(rt2x00dev, 24, 0x1F);
841 + count_step = 2;
842 + }
843 +
844 + for (;vga_gain[ch_idx] < 19; vga_gain[ch_idx]=(vga_gain[ch_idx] + count_step)) {
845 + rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
846 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
847 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
848 +
849 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
850 + rt2800_bbp_write(rt2x00dev, 158, bbp);
851 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
852 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
853 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
854 + p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
855 + }
856 +
857 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
858 + rt2800_bbp_write(rt2x00dev, 158, bbp);
859 + rt2800_bbp_write(rt2x00dev, 159, 0x21);
860 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
861 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
862 + p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
863 + }
864 +
865 + rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
866 +
867 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
868 + rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
869 + if ((p0_idx10 > 7000*7000) || (p1_idx10 > 7000*7000)) {
870 + if (vga_gain[ch_idx]!=0)
871 + vga_gain[ch_idx] = vga_gain[ch_idx]-1;
872 + break;
873 + }
874 + }
875 +
876 + if ((p0 > 2500*2500) || (p1 > 2500*2500)) {
877 + break;
878 + }
879 + }
880 +
881 + if (vga_gain[ch_idx] > 18)
882 + vga_gain[ch_idx] = 18;
883 + rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
884 +
885 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
886 + rt2800_bbp_write(rt2x00dev, 158, bbp);
887 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
888 +
889 + rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
890 + }
891 +
892 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
893 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
894 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
895 +
896 + rt2800_bbp_write(rt2x00dev, 158, 0x28);
897 + bbp = ger[CHAIN_0] & 0x0F;
898 + rt2800_bbp_write(rt2x00dev, 159, bbp);
899 +
900 + rt2800_bbp_write(rt2x00dev, 158, 0x29);
901 + bbp = per[CHAIN_0] & 0x3F;
902 + rt2800_bbp_write(rt2x00dev, 159, bbp);
903 +
904 + rt2800_bbp_write(rt2x00dev, 158, 0x46);
905 + bbp = ger[CHAIN_1] & 0x0F;
906 + rt2800_bbp_write(rt2x00dev, 159, bbp);
907 +
908 + rt2800_bbp_write(rt2x00dev, 158, 0x47);
909 + bbp = per[CHAIN_1] & 0x3F;
910 + rt2800_bbp_write(rt2x00dev, 159, bbp);
911 +
912 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
913 + rt2800_bbp_write(rt2x00dev, 1, bbpr1);
914 + rt2800_bbp_write(rt2x00dev, 241, bbpr241);
915 + rt2800_bbp_write(rt2x00dev, 242, bbpr242);
916 + }
917 + rt2800_bbp_write(rt2x00dev, 244, 0x00);
918 +
919 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
920 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
921 + rt2800_bbp_write(rt2x00dev, 158, 0xB0);
922 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
923 +
924 + rt2800_bbp_write(rt2x00dev, 30, bbpr30);
925 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
926 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
927 +
928 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
929 + rt2800_bbp_write(rt2x00dev, 4, bbpr4);
930 + }
931 +
932 + rt2800_bbp_write(rt2x00dev, 21, 0x01);
933 + udelay(1);
934 + rt2800_bbp_write(rt2x00dev, 21, 0x00);
935 +
936 + rt2800_rf_configrecover(rt2x00dev, rf_store);
937 +
938 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
939 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
940 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
941 + rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
942 + udelay(1);
943 + rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
944 + rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
945 + rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
946 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
947 + rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
948 +
949 + rt2x00_info(rt2x00dev, "TX IQ Calibration Done!\n");
950 +
951 + return;
952 +}
953 +EXPORT_SYMBOL_GPL(rt2800_loft_iq_calibration);
954 +
955 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
956 bool set_bw, bool is_ht40)
957 {
958 @@ -9601,6 +10549,7 @@ static void rt2800_init_rfcsr_6352(struc
959 rt2800_rxdcoc_calibration(rt2x00dev);
960 rt2800_bw_filter_calibration(rt2x00dev, true);
961 rt2800_bw_filter_calibration(rt2x00dev, false);
962 + rt2800_loft_iq_calibration(rt2x00dev);
963 rt2800_rxiq_calibration(rt2x00dev);
964 }
965
966 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
967 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
968 @@ -17,6 +17,16 @@
969 #define WCID_START 33
970 #define WCID_END 222
971 #define STA_IDS_SIZE (WCID_END - WCID_START + 2)
972 +#define CHAIN_0 0x0
973 +#define CHAIN_1 0x1
974 +#define RF_ALC_NUM 6
975 +#define CHAIN_NUM 2
976 +
977 +typedef struct rf_reg_pair {
978 + u8 bank;
979 + u8 reg;
980 + u8 value;
981 +} rf_reg_pair;
982
983 /* RT2800 driver data structure */
984 struct rt2800_drv_data {
985 @@ -237,6 +247,7 @@ int rt2800_calcrcalibrationcode(struct r
986 void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev);
987 void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev);
988 void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev);
989 +void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev);
990
991 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev);
992 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev);
993 --- a/drivers/net/wireless/ralink/rt2x00/rt2x00.h
994 +++ b/drivers/net/wireless/ralink/rt2x00/rt2x00.h
995 @@ -566,6 +566,7 @@ struct rt2x00lib_ops {
996 void (*r_calibration) (struct rt2x00_dev *rt2x00dev);
997 void (*rxdcoc_calibration) (struct rt2x00_dev *rt2x00dev);
998 void (*rxiq_calibration) (struct rt2x00_dev *rt2x00dev);
999 + void (*loft_iq_calibration) (struct rt2x00_dev *rt2x00dev);
1000
1001 /*
1002 * Data queue handlers.
OpenWrt Source Repository