mac80211: refresh patches
[openwrt/openwrt.git] / package / kernel / mac80211 / patches / rt2x00 / 991-rt2x00-mt7620-differentiate-based-on-SoC-CHIP_VER.patch
1 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
2 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
3 @@ -1042,6 +1042,11 @@
4 #define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
5 #define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
6
7 +#define BB_PA_MODE_CFG0 0x1214
8 +#define BB_PA_MODE_CFG1 0x1218
9 +#define RF_PA_MODE_CFG0 0x121C
10 +#define RF_PA_MODE_CFG1 0x1220
11 +
12 /*
13 * EDCA_AC0_CFG:
14 */
15 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
16 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
17 @@ -3685,14 +3685,16 @@ static void rt2800_config_channel_rf7620
18 rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
19 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
20
21 - /* Default: XO=20MHz , SDM mode */
22 - rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
23 - rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
24 - rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
25 + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
26 + /* Default: XO=20MHz , SDM mode */
27 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
28 + rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
29 + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
30
31 - rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
32 - rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
33 - rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
34 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
35 + rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
36 + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
37 + }
38
39 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
40 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
41 @@ -3726,18 +3728,23 @@ static void rt2800_config_channel_rf7620
42 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
43 }
44
45 - if (conf_is_ht40(conf)) {
46 - rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
47 - rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
48 - } else {
49 - rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
50 - rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
51 + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
52 + if (conf_is_ht40(conf)) {
53 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
54 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
55 + } else {
56 + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
57 + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
58 + }
59 }
60
61 - rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
62 - rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
63 - conf_is_ht40(conf) && (rf->channel == 11));
64 - rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
65 + if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
66 + rt2800_hw_get_chipeco(rt2x00dev) == 2) {
67 + rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
68 + rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
69 + conf_is_ht40(conf) && (rf->channel == 11));
70 + rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
71 + }
72
73 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
74 if (conf_is_ht40(conf)) {
75 @@ -3837,25 +3844,29 @@ static void rt2800_config_alc(struct rt2
76 if (i == 10000)
77 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
78
79 - if (chan->center_freq > 2457) {
80 - bbp = rt2800_bbp_read(rt2x00dev, 30);
81 - bbp = 0x40;
82 - rt2800_bbp_write(rt2x00dev, 30, bbp);
83 - rt2800_rfcsr_write(rt2x00dev, 39, 0);
84 - if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
85 - rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
86 - else
87 - rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
88 - } else {
89 - bbp = rt2800_bbp_read(rt2x00dev, 30);
90 - bbp = 0x1f;
91 - rt2800_bbp_write(rt2x00dev, 30, bbp);
92 - rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
93 - if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
94 - rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
95 - else
96 - rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
97 + if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
98 + rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
99 + if (chan->center_freq > 2457) {
100 + bbp = rt2800_bbp_read(rt2x00dev, 30);
101 + bbp = 0x40;
102 + rt2800_bbp_write(rt2x00dev, 30, bbp);
103 + rt2800_rfcsr_write(rt2x00dev, 39, 0);
104 + if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
105 + rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
106 + else
107 + rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
108 + } else {
109 + bbp = rt2800_bbp_read(rt2x00dev, 30);
110 + bbp = 0x1f;
111 + rt2800_bbp_write(rt2x00dev, 30, bbp);
112 + rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
113 + if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
114 + rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
115 + else
116 + rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
117 + }
118 }
119 +
120 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
121
122 rt2800_vco_calibration(rt2x00dev);
123 @@ -5887,18 +5898,33 @@ static int rt2800_init_registers(struct
124 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
125 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
126 } else if (rt2x00_rt(rt2x00dev, RT6352)) {
127 - rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
128 - rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
129 - rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
130 - rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
131 - rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
132 - rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
133 - rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
134 - rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
135 - rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
136 - 0x3630363A);
137 - rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
138 - 0x3630363A);
139 + if (rt2800_hw_get_chipver(rt2x00dev) <= 1) {
140 + rt2800_register_write(rt2x00dev, TX_ALC_VGA3,
141 + 0x00000000);
142 + rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG0,
143 + 0x000055FF);
144 + rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG1,
145 + 0x00550055);
146 + rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG0,
147 + 0x000055FF);
148 + rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG1,
149 + 0x00550055);
150 + } else {
151 + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
152 + rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0000);
153 + rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
154 + rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
155 + rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
156 + rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
157 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
158 + 0x6C6C666C);
159 + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
160 + 0x6C6C666C);
161 + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
162 + 0x3630363A);
163 + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
164 + 0x3630363A);
165 + }
166 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
167 rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
168 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
169 @@ -7042,14 +7068,16 @@ static void rt2800_init_bbp_6352(struct
170 rt2800_bbp_write(rt2x00dev, 188, 0x00);
171 rt2800_bbp_write(rt2x00dev, 189, 0x00);
172
173 - rt2800_bbp_write(rt2x00dev, 91, 0x06);
174 - rt2800_bbp_write(rt2x00dev, 92, 0x04);
175 - rt2800_bbp_write(rt2x00dev, 93, 0x54);
176 - rt2800_bbp_write(rt2x00dev, 99, 0x50);
177 - rt2800_bbp_write(rt2x00dev, 148, 0x84);
178 - rt2800_bbp_write(rt2x00dev, 167, 0x80);
179 - rt2800_bbp_write(rt2x00dev, 178, 0xFF);
180 - rt2800_bbp_write(rt2x00dev, 106, 0x13);
181 + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
182 + rt2800_bbp_write(rt2x00dev, 91, 0x06);
183 + rt2800_bbp_write(rt2x00dev, 92, 0x04);
184 + rt2800_bbp_write(rt2x00dev, 93, 0x54);
185 + rt2800_bbp_write(rt2x00dev, 99, 0x50);
186 + rt2800_bbp_write(rt2x00dev, 148, 0x84);
187 + rt2800_bbp_write(rt2x00dev, 167, 0x80);
188 + rt2800_bbp_write(rt2x00dev, 178, 0xFF);
189 + rt2800_bbp_write(rt2x00dev, 106, 0x13);
190 + }
191
192 /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
193 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
194 @@ -10388,31 +10416,36 @@ static void rt2800_init_rfcsr_6352(struc
195 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
196 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
197
198 - rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
199 - if (rt2800_clk_is_20mhz(rt2x00dev))
200 - rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
201 - else
202 - rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
203 - rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
204 - rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
205 - rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
206 - rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
207 - rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
208 - rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
209 - rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
210 - rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
211 - rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
212 - rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
213 - rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
214 - rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
215 - rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
216 - rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
217 - rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
218 - rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
219 + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
220 + rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
221 + if (rt2800_clk_is_20mhz(rt2x00dev))
222 + rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
223 + else
224 + rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
225 + rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
226 + rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
227 + rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
228 + rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
229 + rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
230 + rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
231 + rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
232 + rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
233 + rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
234 + rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
235 + rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
236 + rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
237 + rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
238 + rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
239 + rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
240 + rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
241 + }
242
243 - rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
244 - rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
245 - rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
246 + if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
247 + rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
248 + rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
249 + rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
250 + rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
251 + }
252
253 /* Initialize RF channel register to default value */
254 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
255 @@ -10478,63 +10511,71 @@ static void rt2800_init_rfcsr_6352(struc
256
257 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
258
259 - rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
260 - rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
261 - rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
262 - rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
263 - rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
264 - rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
265 - rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
266 - rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
267 - rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
268 - rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
269 - rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
270 - rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
271 - rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
272 - rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
273 - rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
274 - rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
275 - rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
276 - rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
277 - rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
278 - rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
279 - rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
280 - rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
281 - rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
282 - rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
283 - rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
284 - rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
285 - rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
286 - rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
287 - rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
288 - rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
289 + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
290 + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
291 + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
292 + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
293 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
294 + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
295 + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
296 + rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
297 + rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
298 + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
299 + rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
300 + rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
301 + rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
302 + rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
303 + rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
304 + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
305 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
306 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
307 + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
308 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
309 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
310 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
311 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
312 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
313 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
314 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
315 + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
316 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
317 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
318 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
319 + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
320 + }
321
322 - rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
323 - rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
324 - rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
325 - rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
326 - rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
327 - rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
328 - rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
329 - rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
330 - rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
331 + if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
332 + rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
333 + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
334 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
335 + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
336 + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
337 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
338 + rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
339 + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
340 + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
341 + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
342
343 - rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
344 - rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
345 - rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
346 - rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
347 - rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
348 - rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
349 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
350 + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
351 + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
352 + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
353 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
354 + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
355 + }
356
357 - /* Initialize RF channel register for DRQFN */
358 - rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
359 - rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
360 - rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
361 - rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
362 - rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
363 - rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
364 - rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
365 - rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
366 + if (rt2800_hw_get_chippkg(rt2x00dev) == 0 &&
367 + rt2800_hw_get_chipver(rt2x00dev) == 1) {
368 + /* Initialize RF channel register for DRQFN */
369 + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
370 + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
371 + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
372 + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
373 + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
374 + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
375 + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
376 + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
377 + }
378
379 /* Initialize RF DC calibration register to default value */
380 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
381 @@ -10597,12 +10638,17 @@ static void rt2800_init_rfcsr_6352(struc
382 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
383 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
384
385 - rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
386 - rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
387 - rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
388 + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
389 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
390 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
391 + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
392 + }
393
394 - rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
395 - rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
396 + if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
397 + rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
398 + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
399 + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
400 + }
401
402 rt2800_r_calibration(rt2x00dev);
403 rt2800_rf_self_txdc_cal(rt2x00dev);