package/platform/lantiq/ltq-deu/src/ifxmips_deu_vr9.h

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_deu_vr9.h
   4 ** PROJECT      : IFX UEIP
   5 ** MODULES      : DEU Module for VR9
   6 **
   7 ** DATE         : September 8, 2009
   8 ** AUTHOR       : Mohammad Firdaus
   9 ** DESCRIPTION  : Data Encryption Unit Driver
  10 ** COPYRIGHT    :       Copyright (c) 2009
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author             $Comment
  21 ** 08,Sept 2009 Mohammad Firdaus    Initial UEIP release
  22 *******************************************************************************/
  23 /*!
  24   \defgroup IFX_DEU IFX_DEU_DRIVERS
  25   \ingroup API
  26   \brief deu driver module
  27 */
  28
  29 /*!
  30   \file ifxmips_deu_vr9.h
  31   \ingroup IFX_DEU
  32   \brief board specific deu driver header file for vr9
  33 */
  34
  35 /*!
  36   \defgroup IFX_DEU_DEFINITIONS IFX_DEU_DEFINITIONS
  37   \brief deu driver header file
  38 */
  39
  40
  41 #ifndef IFXMIPS_DEU_VR9_H
  42 #define IFXMIPS_DEU_VR9_H
  43
  44 /* Project Header Files */
  45 #include <linux/version.h>
  46 #include <linux/module.h>
  47 #include <linux/init.h>
  48 #include <linux/types.h>
  49 #include <linux/errno.h>
  50 #include <linux/crypto.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/delay.h>
  53 #include <asm/byteorder.h>
  54 #include <crypto/algapi.h>
  55 #include <linux/module.h>
  56 #include <linux/mm.h>
  57 #include <asm/scatterlist.h>
  58 #include <linux/skbuff.h>
  59 #include <linux/netdevice.h>
  60 #include "ifxmips_deu.h"
  61
  62
  63 #define AES_INIT 1
  64 #define DES_INIT 2
  65 #define ARC4_INIT 3
  66 #define SHA1_INIT 4
  67 #define MD5_INIT 5
  68 #define SHA1_HMAC_INIT 6
  69 #define MD5_HMAC_INIT 7
  70
  71 #define AES_START IFX_AES_CON
  72 #define DES_3DES_START  IFX_DES_CON
  73
  74 #if 0
  75 #define AES_IDLE 0
  76 #define AES_BUSY 1
  77 #define AES_STARTED 2
  78 #define AES_COMPLETED 3
  79 #define DES_IDLE 0
  80 #define DES_BUSY 1
  81 #define DES_STARTED 2
  82 #define DES_COMPLETED 3
  83 #endif
  84
  85 /* SHA1 CONSTANT */
  86 #define HASH_CON_VALUE    0x0701002C
  87
  88 #define INPUT_ENDIAN_SWAP(input)    input_swap(input)
  89 #define DEU_ENDIAN_SWAP(input)    endian_swap(input)
  90 #define FIND_DEU_CHIP_VERSION    chip_version()
  91
  92 #if defined (CONFIG_AR10)
  93 #define DELAY_PERIOD    30
  94 #else
  95 #define DELAY_PERIOD    10
  96 #endif
  97
  98 #define WAIT_AES_DMA_READY()          \
  99     do {                              \
 100         int i;                        \
 101         volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
 102         volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \
 103         for (i = 0; i < 10; i++)      \
 104             udelay(DELAY_PERIOD);     \
 105         while (dma->controlr.BSY) {}; \
 106         while (aes->controlr.BUS) {}; \
 107     } while (0)
 108
 109 #define WAIT_DES_DMA_READY()          \
 110     do {                              \
 111         int i;                        \
 112         volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON; \
 113         volatile struct des_t *des = (struct des_t *) DES_3DES_START; \
 114         for (i = 0; i < 10; i++)      \
 115             udelay(DELAY_PERIOD);     \
 116         while (dma->controlr.BSY) {}; \
 117         while (des->controlr.BUS) {}; \
 118     } while (0)
 119
 120 #define AES_DMA_MISC_CONFIG()        \
 121     do { \
 122         volatile struct aes_t *aes = (volatile struct aes_t *) AES_START; \
 123         aes->controlr.KRE = 1;        \
 124         aes->controlr.GO = 1;         \
 125     } while(0)
 126
 127 #define SHA_HASH_INIT                \
 128     do {                               \
 129         volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \
 130         hash->controlr.ENDI = 1;  \
 131         hash->controlr.SM = 1;    \
 132         hash->controlr.ALGO = 0;  \
 133         hash->controlr.INIT = 1;  \
 134     } while(0)
 135
 136 #define MD5_HASH_INIT                \
 137     do {                               \
 138         volatile struct deu_hash_t *hash = (struct deu_hash_t *) HASH_START; \
 139         hash->controlr.ENDI = 1;  \
 140         hash->controlr.SM = 1;    \
 141         hash->controlr.ALGO = 1;  \
 142         hash->controlr.INIT = 1;  \
 143     } while(0)
 144
 145 /* DEU Common Structures for AR9*/
 146
 147 struct clc_controlr_t {
 148         u32 Res:26;
 149         u32 FSOE:1;
 150         u32 SBWE:1;
 151         u32 EDIS:1;
 152         u32 SPEN:1;
 153         u32 DISS:1;
 154         u32 DISR:1;
 155
 156 };
 157
 158 struct des_t {
 159         struct des_controlr {   //10h
 160                 u32 KRE:1;
 161                 u32 reserved1:5;
 162                 u32 GO:1;
 163                 u32 STP:1;
 164                 u32 Res2:6;
 165                 u32 NDC:1;
 166                 u32 ENDI:1;
 167                 u32 Res3:2;
 168                 u32 F:3;
 169                 u32 O:3;
 170                 u32 BUS:1;
 171                 u32 DAU:1;
 172                 u32 ARS:1;
 173                 u32 SM:1;
 174                 u32 E_D:1;
 175                 u32 M:3;
 176
 177         } controlr;
 178         u32 IHR;                //14h
 179         u32 ILR;                //18h
 180         u32 K1HR;               //1c
 181         u32 K1LR;               //
 182         u32 K2HR;
 183         u32 K2LR;
 184         u32 K3HR;
 185         u32 K3LR;               //30h
 186         u32 IVHR;               //34h
 187         u32 IVLR;               //38
 188         u32 OHR;                //3c
 189         u32 OLR;                //40
 190 };
 191
 192 struct aes_t {
 193         struct aes_controlr {
 194
 195                 u32 KRE:1;
 196                 u32 reserved1:4;
 197                 u32 PNK:1;
 198                 u32 GO:1;
 199                 u32 STP:1;
 200                 u32 reserved2:6;
 201                 u32 NDC:1;
 202                 u32 ENDI:1;
 203                 u32 reserved3:2;
 204                 u32 F:3;        //fbs
 205                 u32 O:3;        //om
 206                 u32 BUS:1;      //bsy
 207                 u32 DAU:1;
 208                 u32 ARS:1;
 209                 u32 SM:1;
 210                 u32 E_D:1;
 211                 u32 KV:1;
 212                 u32 K:2;        //KL
 213
 214         } controlr;
 215         u32 ID3R;               //80h
 216         u32 ID2R;               //84h
 217         u32 ID1R;               //88h
 218         u32 ID0R;               //8Ch
 219         u32 K7R;                //90h
 220         u32 K6R;                //94h
 221         u32 K5R;                //98h
 222         u32 K4R;                //9Ch
 223         u32 K3R;                //A0h
 224         u32 K2R;                //A4h
 225         u32 K1R;                //A8h
 226         u32 K0R;                //ACh
 227         u32 IV3R;               //B0h
 228         u32 IV2R;               //B4h
 229         u32 IV1R;               //B8h
 230         u32 IV0R;               //BCh
 231         u32 OD3R;               //D4h
 232         u32 OD2R;               //D8h
 233         u32 OD1R;               //DCh
 234         u32 OD0R;               //E0h
 235 };
 236
 237 struct arc4_t {
 238         struct arc4_controlr {
 239
 240                 u32 KRE:1;
 241                 u32 KLEN:4;
 242                 u32 KSAE:1;
 243                 u32 GO:1;
 244                 u32 STP:1;
 245                 u32 reserved1:6;
 246                 u32 NDC:1;
 247                 u32 ENDI:1;
 248                 u32 reserved2:8;
 249                 u32 BUS:1;      //bsy
 250                 u32 reserved3:1;
 251                 u32 ARS:1;
 252                 u32 SM:1;
 253                 u32 reserved4:4;
 254
 255         } controlr;
 256         u32 K3R;                //104h
 257         u32 K2R;                //108h
 258         u32 K1R;                //10Ch
 259         u32 K0R;                //110h
 260
 261         u32 IDLEN;              //114h
 262
 263         u32 ID3R;               //118h
 264         u32 ID2R;               //11Ch
 265         u32 ID1R;               //120h
 266         u32 ID0R;               //124h
 267
 268         u32 OD3R;               //128h
 269         u32 OD2R;               //12Ch
 270         u32 OD1R;               //130h
 271         u32 OD0R;               //134h
 272 };
 273
 274 struct deu_hash_t {
 275         struct hash_controlr {
 276                 u32 reserved1:5;
 277                 u32 KHS:1;
 278                 u32 GO:1;
 279                 u32 INIT:1;
 280                 u32 reserved2:6;
 281                 u32 NDC:1;
 282                 u32 ENDI:1;
 283                 u32 reserved3:7;
 284                 u32 DGRY:1;
 285                 u32 BSY:1;
 286                 u32 reserved4:1;
 287                 u32 IRCL:1;
 288                 u32 SM:1;
 289                 u32 KYUE:1;
 290                 u32 HMEN:1;
 291                 u32 SSEN:1;
 292                 u32 ALGO:1;
 293
 294         } controlr;
 295         u32 MR;                 //B4h
 296         u32 D1R;                //B8h
 297         u32 D2R;                //BCh
 298         u32 D3R;                //C0h
 299         u32 D4R;                //C4h
 300         u32 D5R;                //C8h
 301
 302         u32 dummy;              //CCh
 303
 304         u32 KIDX;               //D0h
 305         u32 KEY;                //D4h
 306         u32 DBN;                //D8h
 307 };
 308
 309
 310 struct deu_dma_t {
 311         struct dma_controlr {
 312                 u32 reserved1:22;
 313                 u32 BS:2;
 314                 u32 BSY:1;
 315                 u32 reserved2:1;
 316                 u32 ALGO:2;
 317                 u32 RXCLS:2;
 318                 u32 reserved3:1;
 319                 u32 EN:1;
 320
 321         } controlr;
 322 };
 323
 324 #endif /* IFXMIPS_DEU_VR9_H */