projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
move lots of kernel related packages to the new system/ folder
[openwrt/openwrt.git] / package / system / ltq-dsl / src / ifxmips_atm_fw_regs_common.h
1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_atm_fw_regs_common.h
4 ** PROJECT : UEIP
5 ** MODULES : ATM (ADSL)
6 **
7 ** DATE : 1 AUG 2005
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : ATM Driver (Firmware Register Structures)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 4 AUG 2005 Xu Liang Initiate Version
22 ** 23 OCT 2006 Xu Liang Add GPL header.
23 ** 9 JAN 2007 Xu Liang First version got from Anand (IC designer)
24 *******************************************************************************/
25
26
27
28 #ifndef IFXMIPS_ATM_FW_REGS_COMMON_H
29 #define IFXMIPS_ATM_FW_REGS_COMMON_H
30
31
32
33 #if defined(CONFIG_DANUBE)
34 #include "ifxmips_atm_fw_regs_danube.h"
35 #elif defined(CONFIG_AMAZON_SE)
36 #include "ifxmips_atm_fw_regs_amazon_se.h"
37 #elif defined(CONFIG_AR9)
38 #include "ifxmips_atm_fw_regs_ar9.h"
39 #elif defined(CONFIG_VR9)
40 #include "ifxmips_atm_fw_regs_vr9.h"
41 #else
42 #error Platform is not specified!
43 #endif
44
45
46
47 /*
48 * PPE ATM Cell Header
49 */
50 #if defined(__BIG_ENDIAN)
51 struct uni_cell_header {
52 unsigned int gfc :4;
53 unsigned int vpi :8;
54 unsigned int vci :16;
55 unsigned int pti :3;
56 unsigned int clp :1;
57 };
58 #else
59 struct uni_cell_header {
60 unsigned int clp :1;
61 unsigned int pti :3;
62 unsigned int vci :16;
63 unsigned int vpi :8;
64 unsigned int gfc :4;
65 };
66 #endif // defined(__BIG_ENDIAN)
67
68 /*
69 * Inband Header and Trailer
70 */
71 #if defined(__BIG_ENDIAN)
72 struct rx_inband_trailer {
73 /* 0 - 3h */
74 unsigned int uu :8;
75 unsigned int cpi :8;
76 unsigned int stw_res1:4;
77 unsigned int stw_clp :1;
78 unsigned int stw_ec :1;
79 unsigned int stw_uu :1;
80 unsigned int stw_cpi :1;
81 unsigned int stw_ovz :1;
82 unsigned int stw_mfl :1;
83 unsigned int stw_usz :1;
84 unsigned int stw_crc :1;
85 unsigned int stw_il :1;
86 unsigned int stw_ra :1;
87 unsigned int stw_res2:2;
88 /* 4 - 7h */
89 unsigned int gfc :4;
90 unsigned int vpi :8;
91 unsigned int vci :16;
92 unsigned int pti :3;
93 unsigned int clp :1;
94 };
95
96 struct tx_inband_header {
97 /* 0 - 3h */
98 unsigned int gfc :4;
99 unsigned int vpi :8;
100 unsigned int vci :16;
101 unsigned int pti :3;
102 unsigned int clp :1;
103 /* 4 - 7h */
104 unsigned int uu :8;
105 unsigned int cpi :8;
106 unsigned int pad :8;
107 unsigned int res1 :8;
108 };
109 #else
110 struct rx_inband_trailer {
111 /* 0 - 3h */
112 unsigned int stw_res2:2;
113 unsigned int stw_ra :1;
114 unsigned int stw_il :1;
115 unsigned int stw_crc :1;
116 unsigned int stw_usz :1;
117 unsigned int stw_mfl :1;
118 unsigned int stw_ovz :1;
119 unsigned int stw_cpi :1;
120 unsigned int stw_uu :1;
121 unsigned int stw_ec :1;
122 unsigned int stw_clp :1;
123 unsigned int stw_res1:4;
124 unsigned int cpi :8;
125 unsigned int uu :8;
126 /* 4 - 7h */
127 unsigned int clp :1;
128 unsigned int pti :3;
129 unsigned int vci :16;
130 unsigned int vpi :8;
131 unsigned int gfc :4;
132 };
133
134 struct tx_inband_header {
135 /* 0 - 3h */
136 unsigned int clp :1;
137 unsigned int pti :3;
138 unsigned int vci :16;
139 unsigned int vpi :8;
140 unsigned int gfc :4;
141 /* 4 - 7h */
142 unsigned int res1 :8;
143 unsigned int pad :8;
144 unsigned int cpi :8;
145 unsigned int uu :8;
146 };
147 #endif // defined(__BIG_ENDIAN)
148
149 /*
150 * MIB Table Maintained by Firmware
151 */
152 struct wan_mib_table {
153 u32 res1;
154 u32 wrx_drophtu_cell;
155 u32 wrx_dropdes_pdu;
156 u32 wrx_correct_pdu;
157 u32 wrx_err_pdu;
158 u32 wrx_dropdes_cell;
159 u32 wrx_correct_cell;
160 u32 wrx_err_cell;
161 u32 wrx_total_byte;
162 u32 res2;
163 u32 wtx_total_pdu;
164 u32 wtx_total_cell;
165 u32 wtx_total_byte;
166 };
167
168 /*
169 * Host-PPE Communication Data Structure
170 */
171
172 #if defined(__BIG_ENDIAN)
173 struct fw_ver_id {
174 unsigned int family :4;
175 unsigned int fwtype :4;
176 unsigned int interface :4;
177 unsigned int fwmode :4;
178 unsigned int major :8;
179 unsigned int minor :8;
180 };
181
182 struct wrx_queue_config {
183 /* 0h */
184 unsigned int res2 :27;
185 unsigned int dmach :4;
186 unsigned int errdp :1;
187 /* 1h */
188 unsigned int oversize :16;
189 unsigned int undersize :16;
190 /* 2h */
191 unsigned int res1 :16;
192 unsigned int mfs :16;
193 /* 3h */
194 unsigned int uumask :8;
195 unsigned int cpimask :8;
196 unsigned int uuexp :8;
197 unsigned int cpiexp :8;
198 };
199
200 struct wrx_queue_context {
201 /* 0h */
202 unsigned int curr_len :16;
203 unsigned int res0 :12;
204 unsigned int mfs :1;
205 unsigned int ec :1;
206 unsigned int clp1 :1;
207 unsigned int aal5dp :1;
208
209 /* 1h */
210 unsigned int intcrc;
211
212 /* 2h, 3h */
213 unsigned int curr_des0;
214 unsigned int curr_des1;
215
216 /* 4h - 0xE */
217 unsigned int res1[11];
218
219 unsigned int last_dword;
220 };
221
222 struct wtx_port_config {
223 unsigned int res1 :27;
224 unsigned int qid :4;
225 unsigned int qsben :1;
226 };
227
228 struct wtx_queue_config {
229 unsigned int res1 :25;
230 unsigned int sbid :1;
231 unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to.
232 unsigned int res2 :1;
233 unsigned int qsben :1;
234 };
235
236 struct wrx_desc_context {
237 unsigned int dmach_wrptr : 16;
238 unsigned int dmach_rdptr : 16;
239
240 unsigned int res0 : 16;
241 unsigned int dmach_fcnt : 16;
242
243 unsigned int res1 : 11;
244 unsigned int desbuf_wrptr : 5;
245 unsigned int res2 : 11;
246 unsigned int desbuf_rdptr : 5;
247
248 unsigned int res3 : 27;
249 unsigned int desbuf_vcnt : 5;
250 };
251
252 struct wrx_dma_channel_config {
253 /* 0h */
254 unsigned int res1 :1;
255 unsigned int mode :2;
256 unsigned int rlcfg :1;
257 unsigned int desba :28;
258 /* 1h */
259 unsigned int chrl :16;
260 unsigned int clp1th :16;
261 /* 2h */
262 unsigned int deslen :16;
263 unsigned int vlddes :16;
264 };
265
266 struct wtx_dma_channel_config {
267 /* 0h */
268 unsigned int res2 :1;
269 unsigned int mode :2;
270 unsigned int res3 :1;
271 unsigned int desba :28;
272 /* 1h */
273 unsigned int res1 :32;
274 /* 2h */
275 unsigned int deslen :16;
276 unsigned int vlddes :16;
277 };
278
279 struct htu_entry {
280 unsigned int res1 :1;
281 unsigned int clp :1;
282 unsigned int pid :2;
283 unsigned int vpi :8;
284 unsigned int vci :16;
285 unsigned int pti :3;
286 unsigned int vld :1;
287 };
288
289 struct htu_mask {
290 unsigned int set :1;
291 unsigned int clp :1;
292 unsigned int pid_mask :2;
293 unsigned int vpi_mask :8;
294 unsigned int vci_mask :16;
295 unsigned int pti_mask :3;
296 unsigned int clear :1;
297 };
298
299 struct htu_result {
300 unsigned int res1 :12;
301 unsigned int cellid :4;
302 unsigned int res2 :5;
303 unsigned int type :1;
304 unsigned int ven :1;
305 unsigned int res3 :5;
306 unsigned int qid :4;
307 };
308
309 struct rx_descriptor {
310 /* 0 - 3h */
311 unsigned int own :1;
312 unsigned int c :1;
313 unsigned int sop :1;
314 unsigned int eop :1;
315 unsigned int res1 :3;
316 unsigned int byteoff :2;
317 unsigned int res2 :2;
318 unsigned int id :4;
319 unsigned int err :1;
320 unsigned int datalen :16;
321 /* 4 - 7h */
322 unsigned int res3 :4;
323 unsigned int dataptr :28;
324 };
325
326 struct tx_descriptor {
327 /* 0 - 3h */
328 unsigned int own :1;
329 unsigned int c :1;
330 unsigned int sop :1;
331 unsigned int eop :1;
332 unsigned int byteoff :5;
333 unsigned int res1 :5;
334 unsigned int iscell :1;
335 unsigned int clp :1;
336 unsigned int datalen :16;
337 /* 4 - 7h */
338 unsigned int res2 :4;
339 unsigned int dataptr :28;
340 };
341 #else
342 struct wrx_queue_config {
343 /* 0h */
344 unsigned int errdp :1;
345 unsigned int dmach :4;
346 unsigned int res2 :27;
347 /* 1h */
348 unsigned int undersize :16;
349 unsigned int oversize :16;
350 /* 2h */
351 unsigned int mfs :16;
352 unsigned int res1 :16;
353 /* 3h */
354 unsigned int cpiexp :8;
355 unsigned int uuexp :8;
356 unsigned int cpimask :8;
357 unsigned int uumask :8;
358 };
359
360 struct wtx_port_config {
361 unsigned int qsben :1;
362 unsigned int qid :4;
363 unsigned int res1 :27;
364 };
365
366 struct wtx_queue_config {
367 unsigned int qsben :1;
368 unsigned int res2 :1;
369 unsigned int qsb_vcid :4; // Which QSB queue (VCID) does this TX queue map to.
370 unsigned int sbid :1;
371 unsigned int res1 :25;
372 };
373
374 struct wrx_dma_channel_config
375 {
376 /* 0h */
377 unsigned int desba :28;
378 unsigned int rlcfg :1;
379 unsigned int mode :2;
380 unsigned int res1 :1;
381 /* 1h */
382 unsigned int clp1th :16;
383 unsigned int chrl :16;
384 /* 2h */
385 unsigned int vlddes :16;
386 unsigned int deslen :16;
387 };
388
389 struct wtx_dma_channel_config {
390 /* 0h */
391 unsigned int desba :28;
392 unsigned int res3 :1;
393 unsigned int mode :2;
394 unsigned int res2 :1;
395 /* 1h */
396 unsigned int res1 :32;
397 /* 2h */
398 unsigned int vlddes :16;
399 unsigned int deslen :16;
400 };
401
402 struct rx_descriptor {
403 /* 4 - 7h */
404 unsigned int dataptr :28;
405 unsigned int res3 :4;
406 /* 0 - 3h */
407 unsigned int datalen :16;
408 unsigned int err :1;
409 unsigned int id :4;
410 unsigned int res2 :2;
411 unsigned int byteoff :2;
412 unsigned int res1 :3;
413 unsigned int eop :1;
414 unsigned int sop :1;
415 unsigned int c :1;
416 unsigned int own :1;
417 };
418
419 struct tx_descriptor {
420 /* 4 - 7h */
421 unsigned int dataptr :28;
422 unsigned int res2 :4;
423 /* 0 - 3h */
424 unsigned int datalen :16;
425 unsigned int clp :1;
426 unsigned int iscell :1;
427 unsigned int res1 :5;
428 unsigned int byteoff :5;
429 unsigned int eop :1;
430 unsigned int sop :1;
431 unsigned int c :1;
432 unsigned int own :1;
433 };
434 #endif // defined(__BIG_ENDIAN)
435
436 #if defined(ENABLE_ATM_RETX) && ENABLE_ATM_RETX
437 #if defined(__BIG_ENDIAN)
438
439 struct Retx_adsl_ppe_intf {
440 unsigned int res0_0 : 16;
441 unsigned int dtu_sid : 8;
442 unsigned int dtu_timestamp : 8;
443
444 unsigned int res1_0 : 16;
445 unsigned int local_time : 8;
446 unsigned int res1_1 : 5;
447 unsigned int is_last_cw : 1;
448 unsigned int reinit_flag : 1;
449 unsigned int is_bad_cw : 1;
450 };
451
452 struct Retx_adsl_ppe_intf_rec {
453
454 unsigned int local_time : 8;
455 unsigned int res1_1 : 5;
456 unsigned int is_last_cw : 1;
457 unsigned int reinit_flag : 1;
458 unsigned int is_bad_cw : 1;
459
460 unsigned int dtu_sid : 8;
461 unsigned int dtu_timestamp : 8;
462
463 };
464
465 struct Retx_mode_cfg {
466 unsigned int res0 :8;
467 unsigned int invld_range :8; // used for rejecting the too late arrival of the retransmitted DTU
468 unsigned int buff_size :8; // the total number of cells in playout buffer is 32 * buff_size
469 unsigned int res1 :7;
470 unsigned int retx_en :1;
471 };
472
473 struct Retx_Tsync_cfg {
474 unsigned int fw_alpha :16; // number of consecutive HEC error cell causes that the cell delineation state machine transit from SYNC to HUNT (0 means never)
475 unsigned int sync_inp :16; // reserved
476 };
477
478 struct Retx_Td_cfg {
479 unsigned int res0 :8;
480 unsigned int td_max :8; // maximum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver
481 unsigned int res1 :8;
482 unsigned int td_min :8; // minimum delay between the time a DTU is first created at transmitter and the time the DTU is sent out of ReTX layer at receiver
483 };
484
485 struct Retx_MIB_Timer_cfg {
486 unsigned int ticks_per_sec : 16;
487 unsigned int tick_cycle : 16;
488 };
489
490 struct DTU_stat_info {
491 unsigned int complete : 1;
492 unsigned int bad : 1;
493 unsigned int res0_0 : 14;
494 unsigned int time_stamp : 8;
495 unsigned int cell_cnt : 8;
496
497 unsigned int dtu_rd_ptr : 16;
498 unsigned int dtu_wr_ptr : 16;
499 };
500
501 struct Retx_ctrl_field {
502 unsigned int res0 : 1;
503
504 unsigned int l2_drop : 1;
505 unsigned int res1 : 13;
506 unsigned int retx : 1;
507
508 unsigned int dtu_sid : 8;
509 unsigned int cell_sid : 8;
510 };
511
512 #else
513 #error Little Endian is not supported yet.
514 #endif
515
516 struct dsl_param {
517 unsigned int update_flag; // 00
518 unsigned int res0; // 04
519 unsigned int MinDelayrt; // 08
520 unsigned int MaxDelayrt; // 0C
521 unsigned int res1; // 10
522 unsigned int res2; // 14
523 unsigned int RetxEnable; // 18
524 unsigned int ServiceSpecificReTx; // 1C
525 unsigned int res3; // 20
526 unsigned int ReTxPVC; // 24
527 unsigned int res4; // 28
528 unsigned int res5; // 2C
529 unsigned int res6; // 30
530 unsigned int res7; // 34
531 unsigned int res8; // 38
532 unsigned int res9; // 3C
533 unsigned int res10; // 40
534 unsigned int res11; // 44
535 unsigned int res12; // 48
536 unsigned int res13; // 4C
537 unsigned int RxDtuCorruptedCNT; // 50
538 unsigned int RxRetxDtuUnCorrectedCNT;// 54
539 unsigned int RxLastEFB; // 58
540 unsigned int RxDtuCorrectedCNT; // 5C
541 };
542 #endif
543
544
545
546 #endif // IFXMIPS_ATM_FW_REGS_COMMON_H
OpenWrt Source Repository