eae621eafdace94b59dda86b596ad4d292ab8582
[openwrt/openwrt.git] / package / system / ltq-vmmc / patches / 100-target.patch
1 --- a/src/drv_vmmc_access.h
2 +++ b/src/drv_vmmc_access.h
3 @@ -24,6 +24,10 @@
4 #include "drv_mps_vmmc.h"
5 #endif
6
7 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
8 +# define IFX_MPS IFXMIPS_MPS_BASE_ADDR
9 +#endif
10 +
11 /* ============================= */
12 /* Global Defines */
13 /* ============================= */
14 --- a/src/drv_vmmc_danube.h
15 +++ b/src/drv_vmmc_danube.h
16 @@ -15,56 +15,18 @@
17 */
18
19 #if defined SYSTEM_DANUBE
20 -#include <asm/ifx/ifx_gpio.h>
21 +#include <lantiq_soc.h>
22 +
23 #else
24 #error no system selected
25 #endif
26
27 -#define VMMC_TAPI_GPIO_MODULE_ID IFX_GPIO_MODULE_TAPI_VMMC
28 +#define VMMC_TAPI_GPIO_MODULE_ID IFX_GPIO_MODULE_TAPI_VMMC
29 /**
30
31 */
32 #define VMMC_PCM_IF_CFG_HOOK(mode, GPIOreserved, ret) \
33 do { \
34 - ret = VMMC_statusOk; \
35 - /* Reserve P0.0 as TDM/FSC */ \
36 - if (!GPIOreserved) \
37 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
38 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
39 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
40 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID);\
41 - \
42 - /* Reserve P1.9 as TDM/DO */ \
43 - if (!GPIOreserved) \
44 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
45 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
46 - ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
47 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
48 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
49 - \
50 - /* Reserve P1.10 as TDM/DI */ \
51 - if (!GPIOreserved) \
52 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
53 - ret |= ifx_gpio_altsel0_clear(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
54 - ret |= ifx_gpio_altsel1_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID);\
55 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
56 - \
57 - /* Reserve P1.11 as TDM/DCL */ \
58 - if (!GPIOreserved) \
59 - ret |= ifx_gpio_pin_reserve(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
60 - ret |= ifx_gpio_altsel0_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
61 - ret |= ifx_gpio_altsel1_clear(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
62 - ret |= ifx_gpio_open_drain_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
63 - \
64 - if (mode == 2) { \
65 - /* TDM/FSC+DCL Master */ \
66 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
67 - ret |= ifx_gpio_dir_out_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
68 - } else { \
69 - /* TDM/FSC+DCL Slave */ \
70 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
71 - ret |= ifx_gpio_dir_in_set(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
72 - } \
73 } while(0);
74
75 /**
76 @@ -72,11 +34,6 @@
77 */
78 #define VMMC_DRIVER_UNLOAD_HOOK(ret) \
79 do { \
80 - ret = VMMC_statusOk; \
81 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(0, 0), VMMC_TAPI_GPIO_MODULE_ID); \
82 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1, 9), VMMC_TAPI_GPIO_MODULE_ID); \
83 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,10), VMMC_TAPI_GPIO_MODULE_ID); \
84 - ret |= ifx_gpio_pin_free(IFX_GPIO_PIN_ID(1,11), VMMC_TAPI_GPIO_MODULE_ID); \
85 } while (0)
86
87 #endif /* _DRV_VMMC_AMAZON_S_H */
88 --- a/src/drv_vmmc_init.c
89 +++ b/src/drv_vmmc_init.c
90 @@ -52,6 +52,14 @@
91 #include "ifx_pmu.h"
92 #endif /* PMU_SUPPORTED */
93
94 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
95 +# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
96 +# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
97 +# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
98 +# define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
99 +# define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
100 +# define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
101 +#endif
102
103 /* ============================= */
104 /* Local Macros & Definitions */
105 @@ -1591,7 +1599,7 @@
106 #ifdef VMMC_DRIVER_UNLOAD_HOOK
107 if (VDevices[0].nDevState & DS_GPIO_RESERVED)
108 {
109 - IFX_int32_t ret;
110 + IFX_int32_t ret = 0;
111 VMMC_DRIVER_UNLOAD_HOOK(ret);
112 if (!VMMC_SUCCESS(ret))
113 {
114 --- a/src/drv_vmmc_init_cap.c
115 +++ b/src/drv_vmmc_init_cap.c
116 @@ -22,6 +22,11 @@
117 #include "drv_mps_vmmc.h"
118 #include "drv_mps_vmmc_device.h"
119
120 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
121 +# define IFX_MPS_CHIPID_VERSION_GET IFXMIPS_MPS_CHIPID_VERSION_GET
122 +# define IFX_MPS_CHIPID IFXMIPS_MPS_CHIPID
123 +#endif
124 +
125 /* ============================= */
126 /* Configuration defintions */
127 /* ============================= */
128 --- a/src/mps/drv_mps_vmmc_common.c
129 +++ b/src/mps/drv_mps_vmmc_common.c
130 @@ -17,6 +17,7 @@
131 /* Includes */
132 /* ============================= */
133 #include "drv_config.h"
134 +#include "drv_vmmc_init.h"
135
136 #undef USE_PLAIN_VOICE_FIRMWARE
137 #undef PRINT_ON_ERR_INTERRUPT
138 @@ -39,8 +40,32 @@
139 #include "ifxos_interrupt.h"
140 #include "ifxos_time.h"
141
142 -#include <asm/ifx/ifx_regs.h>
143 -#include <asm/ifx/ifx_gptu.h>
144 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
145 +# include <lantiq.h>
146 +# include <irq.h>
147 +# include <lantiq_timer.h>
148 +
149 +# define ifx_gptu_timer_request lq_request_timer
150 +# define ifx_gptu_timer_start lq_start_timer
151 +# define ifx_gptu_countvalue_get lq_get_count_value
152 +# define ifx_gptu_timer_free lq_free_timer
153 +
154 +
155 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,39))
156 +# define bsp_mask_and_ack_irq ltq_mask_and_ack_irq
157 +#else
158 +extern void ltq_mask_and_ack_irq(struct irq_data *d);
159 +static void inline bsp_mask_and_ack_irq(int x)
160 +{
161 + struct irq_data d;
162 + d.irq = x;
163 + ltq_mask_and_ack_irq(&d);
164 +}
165 +#endif
166 +#else
167 +# include <asm/ifx/ifx_regs.h>
168 +# include <asm/ifx/ifx_gptu.h>
169 +#endif
170
171 #include "drv_mps_vmmc.h"
172 #include "drv_mps_vmmc_dbg.h"
173 @@ -104,6 +129,9 @@
174 extern IFX_void_t mask_and_ack_danube_irq (IFX_uint32_t irq_nr);
175
176 #endif /* */
177 +
178 +extern void sys_hw_setup (void);
179 +
180 extern IFXOS_event_t fw_ready_evt;
181 /* callback function to free all data buffers currently used by voice FW */
182 IFX_void_t (*ifx_mps_bufman_freeall)(IFX_void_t) = IFX_NULL;
183 @@ -207,7 +235,8 @@
184 */
185 IFX_void_t *ifx_mps_fastbuf_malloc (IFX_size_t size, IFX_int32_t priority)
186 {
187 - IFX_uint32_t ptr, flags;
188 + IFXOS_INTSTAT flags;
189 + IFX_uint32_t ptr;
190 IFX_int32_t index = fastbuf_index;
191
192 if (fastbuf_initialized == 0)
193 @@ -261,7 +290,7 @@
194 */
195 IFX_void_t ifx_mps_fastbuf_free (const IFX_void_t * ptr)
196 {
197 - IFX_uint32_t flags;
198 + IFXOS_INTSTAT flags;
199 IFX_int32_t index = fastbuf_index;
200
201 IFXOS_LOCKINT (flags);
202 @@ -457,7 +486,7 @@
203 */
204 static IFX_int32_t ifx_mps_bufman_inc_level (IFX_uint32_t value)
205 {
206 - IFX_uint32_t flags;
207 + IFXOS_INTSTAT flags;
208
209 if (mps_buffer.buf_level + value > MPS_BUFFER_MAX_LEVEL)
210 {
211 @@ -484,7 +513,7 @@
212 */
213 static IFX_int32_t ifx_mps_bufman_dec_level (IFX_uint32_t value)
214 {
215 - IFX_uint32_t flags;
216 + IFXOS_INTSTAT flags;
217
218 if (mps_buffer.buf_level < value)
219 {
220 @@ -636,7 +665,7 @@
221 mem_seg_ptr[i] =
222 (IFX_uint32_t *) CPHYSADDR ((IFX_uint32_t) mps_buffer.
223 malloc (segment_size, FASTBUF_FW_OWNED));
224 - if (mem_seg_ptr[i] == CPHYSADDR (IFX_NULL))
225 + if (mem_seg_ptr[i] == (IFX_uint32_t *)CPHYSADDR (IFX_NULL))
226 {
227 TRACE (MPS, DBG_LEVEL_HIGH,
228 ("%s(): cannot allocate buffer\n", __FUNCTION__));
229 @@ -952,7 +981,7 @@
230 mps_mbx_dev * pMBDev, IFX_int32_t bcommand,
231 IFX_boolean_t from_kernel)
232 {
233 - IFX_uint32_t flags;
234 + IFXOS_INTSTAT flags;
235
236 IFXOS_LOCKINT (flags);
237
238 @@ -1068,7 +1097,7 @@
239 IFX_void_t ifx_mps_release_structures (mps_comm_dev * pDev)
240 {
241 IFX_int32_t count;
242 - IFX_uint32_t flags;
243 + IFXOS_INTSTAT flags;
244
245 IFXOS_LOCKINT (flags);
246 IFXOS_BlockFree (pFW_img_data);
247 @@ -1117,7 +1146,7 @@
248
249 /* Initialize MPS main structure */
250 memset ((IFX_void_t *) pDev, 0, sizeof (mps_comm_dev));
251 - pDev->base_global = (mps_mbx_reg *) IFX_MPS_SRAM;
252 + pDev->base_global = (mps_mbx_reg *) IFXMIPS_MPS_SRAM;
253 pDev->flags = 0x00000000;
254 MBX_Memory = pDev->base_global;
255
256 @@ -1125,9 +1154,11 @@
257 for MBX communication. These are: mailbox base address, mailbox size, *
258 mailbox read index and mailbox write index. for command and voice
259 mailbox, * upstream and downstream direction. */
260 - memset ((IFX_void_t *) MBX_Memory, /* avoid to overwrite CPU boot
261 - registers */
262 - 0, sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));
263 + memset (
264 + /* avoid to overwrite CPU boot registers */
265 + (IFX_void_t *) MBX_Memory,
266 + 0,
267 + sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));
268 MBX_Memory->MBX_UPSTR_CMD_BASE =
269 (IFX_uint32_t *) CPHYSADDR ((IFX_uint32_t) MBX_UPSTRM_CMD_FIFO_BASE);
270 MBX_Memory->MBX_UPSTR_CMD_SIZE = MBX_CMD_FIFO_SIZE;
271 @@ -1564,7 +1595,7 @@
272 IFX_uint32_t * bytes)
273 {
274 IFX_int32_t i, ret;
275 - IFX_uint32_t flags;
276 + IFXOS_INTSTAT flags;
277
278 IFXOS_LOCKINT (flags);
279
280 @@ -1774,7 +1805,7 @@
281 {
282 mps_fifo *mbx;
283 IFX_uint32_t i;
284 - IFX_uint32_t flags;
285 + IFXOS_INTSTAT flags;
286 IFX_int32_t retval = -EAGAIN;
287 IFX_int32_t retries = 0;
288 IFX_uint32_t word = 0;
289 @@ -2169,6 +2200,7 @@
290 TRACE (MPS, DBG_LEVEL_HIGH,
291 ("%s(): Invalid device ID %d !\n", __FUNCTION__, pMBDev->devID));
292 }
293 +
294 return retval;
295 }
296
297 @@ -2192,7 +2224,7 @@
298 mps_mbx_dev *mbx_dev;
299 MbxMsg_s msg;
300 IFX_uint32_t bytes_read = 0;
301 - IFX_uint32_t flags;
302 + IFXOS_INTSTAT flags;
303 IFX_int32_t ret;
304
305 /* set pointer to data upstream mailbox, no matter if 0,1,2 or 3 because
306 @@ -2283,7 +2315,7 @@
307 {
308 ifx_mps_bufman_dec_level (1);
309 if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
310 - (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
311 + ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
312 {
313 IFXOS_LockRelease (pMPSDev->provide_buffer);
314 }
315 @@ -2326,7 +2358,7 @@
316 #endif /* CONFIG_PROC_FS */
317 ifx_mps_bufman_dec_level (1);
318 if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
319 - (atomic_read (&pMPSDev->provide_buffer->object.count) == 0))
320 + ((volatile unsigned int)pMPSDev->provide_buffer->object.count == 0))
321 {
322 IFXOS_LockRelease (pMPSDev->provide_buffer);
323 }
324 @@ -2356,7 +2388,7 @@
325 IFX_void_t ifx_mps_mbx_cmd_upstream (IFX_ulong_t dummy)
326 {
327 mps_fifo *mbx;
328 - IFX_uint32_t flags;
329 + IFXOS_INTSTAT flags;
330
331 /* set pointer to upstream command mailbox */
332 mbx = &(pMPSDev->cmd_upstrm_fifo);
333 @@ -2404,7 +2436,7 @@
334 mps_event_msg msg;
335 IFX_int32_t length = 0;
336 IFX_int32_t read_length = 0;
337 - IFX_uint32_t flags;
338 + IFXOS_INTSTAT flags;
339
340 /* set pointer to upstream event mailbox */
341 mbx = &(pMPSDev->event_upstrm_fifo);
342 @@ -2619,6 +2651,7 @@
343 #endif
344
345 *IFX_MPS_AD0ENR = Ad0Reg.val;
346 +
347 }
348
349 /**
350 @@ -2647,7 +2680,7 @@
351 */
352 IFX_void_t ifx_mps_dd_mbx_int_enable (IFX_void_t)
353 {
354 - IFX_uint32_t flags;
355 + IFXOS_INTSTAT flags;
356 MPS_Ad0Reg_u Ad0Reg;
357
358 IFXOS_LOCKINT (flags);
359 @@ -2673,7 +2706,7 @@
360 */
361 IFX_void_t ifx_mps_dd_mbx_int_disable (IFX_void_t)
362 {
363 - IFX_uint32_t flags;
364 + IFXOS_INTSTAT flags;
365 MPS_Ad0Reg_u Ad0Reg;
366
367 IFXOS_LOCKINT (flags);
368 @@ -2738,7 +2771,6 @@
369 #else /* */
370 mask_and_ack_danube_irq (irq);
371 #endif /* */
372 -
373 /* FW is up and ready to process commands */
374 if (MPS_Ad0StatusReg.fld.dl_end)
375 {
376 @@ -2800,6 +2832,7 @@
377 }
378 }
379
380 +
381 if (MPS_Ad0StatusReg.fld.du_mbx)
382 {
383 #ifdef CONFIG_PROC_FS
384 @@ -2944,12 +2977,12 @@
385 IFX_MPS_CVC0SR[chan] = MPS_VCStatusReg.val;
386 /* handle only enabled interrupts */
387 MPS_VCStatusReg.val &= IFX_MPS_VC0ENR[chan];
388 -
389 #ifdef LINUX_2_6
390 bsp_mask_and_ack_irq (irq);
391 #else /* */
392 mask_and_ack_danube_irq (irq);
393 #endif /* */
394 +
395 pMPSDev->event.MPS_VCStatReg[chan].val = MPS_VCStatusReg.val;
396 #ifdef PRINT_ON_ERR_INTERRUPT
397 if (MPS_VCStatusReg.fld.rcv_ov)
398 @@ -3093,7 +3126,8 @@
399 */
400 IFX_return_t ifx_mps_init_gpt ()
401 {
402 - IFX_uint32_t flags, timer_flags, timer, loops = 0;
403 + unsigned long flags;
404 + IFX_uint32_t timer_flags, timer, loops = 0;
405 IFX_ulong_t count;
406 #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
407 timer = TIMER1A;
408 @@ -3166,6 +3200,7 @@
409 #else /* Danube */
410 timer = TIMER1B;
411 #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
412 +
413 ifx_gptu_timer_free (timer);
414 }
415
416 --- a/src/mps/drv_mps_vmmc_danube.c
417 +++ b/src/mps/drv_mps_vmmc_danube.c
418 @@ -16,6 +16,7 @@
419 /* ============================= */
420 /* Includes */
421 /* ============================= */
422 +#include "linux/version.h"
423 #include "drv_config.h"
424
425 #ifdef SYSTEM_DANUBE /* defined in drv_mps_vmmc_config.h */
426 @@ -36,9 +37,22 @@
427 #include "ifxos_select.h"
428 #include "ifxos_interrupt.h"
429
430 -#include <asm/ifx/ifx_regs.h>
431 -#include <asm/ifx/ifx_gpio.h>
432 -#include <asm/ifx/common_routines.h>
433 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
434 +# include <lantiq.h>
435 +# include <irq.h>
436 +# include <lantiq_timer.h>
437 +# include <linux/dma-mapping.h>
438 +
439 +
440 +#define LQ_RCU_BASE_ADDR (KSEG1 + LTQ_RCU_BASE_ADDR)
441 +# define LQ_RCU_RST ((u32 *)(LQ_RCU_BASE_ADDR + 0x0010))
442 +#define IFX_RCU_RST_REQ_CPU1 (1 << 3)
443 +# define IFX_RCU_RST_REQ LQ_RCU_RST
444 +#else
445 +# include <asm/ifx/ifx_regs.h>
446 +# include <asm/ifx_vpe.h>
447 +# include <asm/ifx/ifx_gpio.h>
448 +#endif
449
450 #include "drv_mps_vmmc.h"
451 #include "drv_mps_vmmc_dbg.h"
452 @@ -75,6 +89,20 @@
453 /* Local function definition */
454 /* ============================= */
455
456 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
457 +IFX_uint32_t ifx_get_cp1_size(IFX_void_t)
458 +{
459 + return 1;
460 +}
461 +
462 +unsigned int *ltq_get_cp1_base(void);
463 +
464 +IFX_uint32_t *ifx_get_cp1_base(IFX_void_t)
465 +{
466 + return ltq_get_cp1_base();
467 +}
468 +#endif
469 +
470 /******************************************************************************
471 * DANUBE Specific Routines
472 ******************************************************************************/
473 @@ -134,6 +162,15 @@
474 }
475
476 /* check if FW image fits in available memory space */
477 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
478 + if (mem > ifx_get_cp1_size()<<20)
479 + {
480 + TRACE (MPS, DBG_LEVEL_HIGH,
481 + ("[%s %s %d]: error, firmware memory exceeds reserved space (%i > %i)!\n",
482 + __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()<<20));
483 + return IFX_ERROR;
484 + }
485 +#else
486 if (mem > ifx_get_cp1_size())
487 {
488 TRACE (MPS, DBG_LEVEL_HIGH,
489 @@ -141,6 +178,7 @@
490 __FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()));
491 return IFX_ERROR;
492 }
493 +#endif
494
495 /* reset the driver */
496 ifx_mps_reset ();
497 @@ -361,7 +399,7 @@
498 */
499 IFX_void_t ifx_mps_wdog_expiry()
500 {
501 - IFX_uint32_t flags;
502 + unsigned long flags;
503
504 IFXOS_LOCKINT (flags);
505 /* recalculate and compare the firmware checksum */
506 --- a/src/mps/drv_mps_vmmc_device.h
507 +++ b/src/mps/drv_mps_vmmc_device.h
508 @@ -16,8 +16,58 @@
509 declarations.
510 *******************************************************************************/
511
512 -#include <asm/ifx/ifx_regs.h>
513 -#include <asm/ifx_vpe.h>
514 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
515 +# include <lantiq.h>
516 +# include <irq.h>
517 +# include <lantiq_soc.h>
518 +# include <gpio.h>
519 +#define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000))
520 +#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
521 +#define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
522 +#define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
523 +#define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
524 +#define IFXMIPS_MPS_CVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
525 +#define IFXMIPS_MPS_CVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
526 +#define IFXMIPS_MPS_CVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
527 +#define IFXMIPS_MPS_CVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x003C))
528 +#define IFXMIPS_MPS_RAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0040))
529 +#define IFXMIPS_MPS_RAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0044))
530 +#define IFXMIPS_MPS_SAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0048))
531 +#define IFXMIPS_MPS_SAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x004C))
532 +#define IFXMIPS_MPS_CAD0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0050))
533 +#define IFXMIPS_MPS_CAD1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0054))
534 +#define IFXMIPS_MPS_AD0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
535 +#define IFXMIPS_MPS_AD1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
536 +
537 +#define IFXMIPS_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1))
538 +#define IFXMIPS_MPS_CHIPID_VERSION_SET(value) ((((1 << 4) - 1) & (value)) << 28)
539 +#define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1))
540 +#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) ((((1 << 16) - 1) & (value)) << 12)
541 +#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
542 +#define IFXMIPS_MPS_CHIPID_MANID_SET(value) ((((1 << 10) - 1) & (value)) << 1)
543 +#else
544 +# include <asm/ifx/ifx_regs.h>
545 +# include <asm/ifx_vpe.h>
546 +#endif
547 +/* MPS register */
548 +# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR
549 +# define IFX_MPS_AD1ENR IFXMIPS_MPS_AD1ENR
550 +# define IFX_MPS_RAD0SR IFXMIPS_MPS_RAD0SR
551 +# define IFX_MPS_RAD1SR IFXMIPS_MPS_RAD1SR
552 +# define IFX_MPS_VC0ENR IFXMIPS_MPS_VC0ENR
553 +# define IFX_MPS_RVC0SR IFXMIPS_MPS_RVC0SR
554 +# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
555 +# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
556 +# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
557 +# define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
558 +# define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
559 +# define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
560 +# define IFX_MPS_SAD0SR IFXMIPS_MPS_SAD0SR
561 +/* interrupt vectors */
562 +# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
563 +# define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18)
564 +# define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19)
565 +# define IFX_ICU_IM4_IER IFXMIPS_ICU_IM4_IER
566
567 /* ============================= */
568 /* MPS Common defines */
569 @@ -26,32 +76,28 @@
570 #define MPS_BASEADDRESS 0xBF107000
571 #define MPS_RAD0SR MPS_BASEADDRESS + 0x0004
572
573 -#define MPS_RAD0SR_DU (1<<0)
574 -#define MPS_RAD0SR_CU (1<<1)
575 -
576 #define MBX_BASEADDRESS 0xBF200000
577 #define VCPU_BASEADDRESS 0xBF208000 /* 0xBF108000 */
578 /*---------------------------------------------------------------------------*/
579 +#if !defined(CONFIG_LANTIQ)
580 +/* enabling interrupts is done with request_irq by the BSP
581 + The related code should not be needed anymore */
582 #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
583 /* TODO: doublecheck - IM4 or different! */
584 #define MPS_INTERRUPTS_ENABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) |= X;
585 #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) &= ~X;
586 -#define MPS_INTERRUPTS_CLEAR(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_ISR) = X;
587 -#define MPS_INTERRUPTS_SET(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IRSR) = X;/* |= ? */
588 #else /* Danube */
589 /* TODO: possibly needs to be changed to IM4 !!!!!! */
590 #ifdef LINUX_2_6
591 #define MPS_INTERRUPTS_ENABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) |= X;
592 #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) &= ~X;
593 -#define MPS_INTERRUPTS_CLEAR(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_ISR) = X;
594 -#define MPS_INTERRUPTS_SET(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IRSR) = X;/* |= ? */
595 #else /* */
596 #define MPS_INTERRUPTS_ENABLE(X) *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IER) |= X;
597 #define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IER) &= ~X;
598 -#define MPS_INTERRUPTS_CLEAR(X) *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_ISR) = X;
599 -#define MPS_INTERRUPTS_SET(X) *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IRSR) = X;/* |= ? */
600 #endif /* LINUX_2_6 */
601 #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
602 +#endif /* !defined(CONFIG_LANTIQ) */
603 +
604 /*---------------------------------------------------------------------------*/
605
606 /*---------------------------------------------------------------------------*/
607 @@ -142,53 +188,9 @@
608 #if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
609 /* ***** Amazon-S specific defines ***** */
610 #define IFX_MPS_Base AMAZON_S_MPS
611 -
612 -//#define IFX_MPS_CHIPID AMAZON_S_MPS_CHIPID
613 -//#define IFX_MPS_CHIPID_VERSION_GET AMAZON_S_MPS_CHIPID_VERSION_GET
614 -
615 -//#define IFX_MPS_AD0ENR AMAZON_S_MPS_AD0ENR
616 -//#define IFX_MPS_AD1ENR AMAZON_S_MPS_AD1ENR
617 -//#define IFX_MPS_VC0ENR AMAZON_S_MPS_VC0ENR
618 -//#define IFX_MPS_SAD0SR AMAZON_S_MPS_SAD0SR
619 -//#define IFX_MPS_RAD0SR AMAZON_S_MPS_RAD0SR
620 -//#define IFX_MPS_CAD0SR AMAZON_S_MPS_CAD0SR
621 -//#define IFX_MPS_RAD1SR AMAZON_S_MPS_RAD1SR
622 -//#define IFX_MPS_CAD1SR AMAZON_S_MPS_CAD1SR
623 -//#define IFX_MPS_RVC0SR AMAZON_S_MPS_RVC0SR
624 -//#define IFX_MPS_CVC0SR AMAZON_S_MPS_CVC0SR
625 -//#define IFX_MPS_CVC1SR AMAZON_S_MPS_CVC1SR
626 -//#define IFX_MPS_CVC2SR AMAZON_S_MPS_CVC2SR
627 -//#define IFX_MPS_CVC3SR AMAZON_S_MPS_CVC3SR
628 -
629 -//#define IFX_MPS_SRAM AMAZON_S_MPS_SRAM
630 #else /* */
631 /* ***** DANUBE specific defines ***** */
632 #define IFX_MPS_Base DANUBE_MPS
633 -
634 -//#define IFX_MPS_CHIPID DANUBE_MPS_CHIPID
635 -//#define IFX_MPS_CHIPID_VERSION_GET DANUBE_MPS_CHIPID_VERSION_GET
636 -//#define IFX_MPS_CHIPID_VERSION_SET DANUBE_MPS_CHIPID_VERSION_SET
637 -//#define IFX_MPS_CHIPID_PARTNUM_GET DANUBE_MPS_CHIPID_PARTNUM_GET
638 -//#define IFX_MPS_CHIPID_PARTNUM_SET DANUBE_MPS_CHIPID_PARTNUM_SET
639 -//#define IFX_MPS_CHIPID_MANID_GET DANUBE_MPS_CHIPID_MANID_GET
640 -//#define IFX_MPS_CHIPID_MANID_SET DANUBE_MPS_CHIPID_MANID_SET
641 -//#define IFX_MPS_SUBVER DANUBE_MPS_SUBVER
642 -
643 -//#define IFX_MPS_AD0ENR DANUBE_MPS_AD0ENR
644 -//#define IFX_MPS_AD1ENR DANUBE_MPS_AD1ENR
645 -//#define IFX_MPS_VC0ENR DANUBE_MPS_VC0ENR
646 -//#define IFX_MPS_SAD0SR DANUBE_MPS_SAD0SR
647 -//#define IFX_MPS_RAD0SR DANUBE_MPS_RAD0SR
648 -//#define IFX_MPS_CAD0SR DANUBE_MPS_CAD0SR
649 -//#define IFX_MPS_RAD1SR DANUBE_MPS_RAD1SR
650 -//#define IFX_MPS_CAD1SR DANUBE_MPS_CAD1SR
651 -//#define IFX_MPS_RVC0SR DANUBE_MPS_RVC0SR
652 -//#define IFX_MPS_CVC0SR DANUBE_MPS_CVC0SR
653 -//#define IFX_MPS_CVC1SR DANUBE_MPS_CVC1SR
654 -//#define IFX_MPS_CVC2SR DANUBE_MPS_CVC2SR
655 -//#define IFX_MPS_CVC3SR DANUBE_MPS_CVC3SR
656 -
657 -//#define IFX_MPS_SRAM DANUBE_MPS_SRAM
658 #endif /* SYSTEM_AR9 || SYSTEM_VR9 */
659 typedef enum
660 {
661 --- a/src/mps/drv_mps_vmmc_linux.c
662 +++ b/src/mps/drv_mps_vmmc_linux.c
663 @@ -57,10 +57,11 @@
664 #include <linux/moduleparam.h>
665 #endif /* */
666
667 -
668 +#if !defined CONFIG_LANTIQ
669 #include <asm/ifx/irq.h>
670 #include <asm/ifx/ifx_regs.h>
671 #include <asm/ifx_vpe.h>
672 +#endif
673
674 /* lib_ifxos headers */
675 #include "ifx_types.h"
676 @@ -959,7 +960,7 @@
677 #endif /* MPS_FIFO_BLOCKING_WRITE */
678 case FIO_MPS_GET_STATUS:
679 {
680 - IFX_uint32_t flags;
681 + unsigned long flags;
682
683 /* get the status of the channel */
684 if (!from_kernel)
685 @@ -993,7 +994,7 @@
686 #if CONFIG_MPS_HISTORY_SIZE > 0
687 case FIO_MPS_GET_CMD_HISTORY:
688 {
689 - IFX_uint32_t flags;
690 + unsigned long flags;
691
692 if (from_kernel)
693 {
694 @@ -1685,6 +1686,7 @@
695 sprintf (buf + len, " minLv: \t %8d\n",
696 ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space);
697 }
698 +
699 return len;
700 }
701
702 @@ -2291,9 +2293,11 @@
703 return result;
704 }
705
706 +#if !defined(CONFIG_LANTIQ)
707 + /** \todo This is handled already with request_irq, remove */
708 /* Enable all MPS Interrupts at ICU0 */
709 MPS_INTERRUPTS_ENABLE (0x0000FF80);
710 -
711 +#endif
712 /* enable mailbox interrupts */
713 ifx_mps_enable_mailbox_int ();
714 /* init FW ready event */
715 @@ -2421,9 +2425,11 @@
716 /* disable mailbox interrupts */
717 ifx_mps_disable_mailbox_int ();
718
719 +#if !defined(CONFIG_LANTIQ)
720 /* disable Interrupts at ICU0 */
721 - MPS_INTERRUPTS_DISABLE (DANUBE_MPS_AD0_IR4); /* Disable DFE/AFE 0 Interrupts
722 - */
723 + /* Disable DFE/AFE 0 Interrupts*/
724 + MPS_INTERRUPTS_DISABLE (DANUBE_MPS_AD0_IR4);
725 +#endif
726
727 /* disable all MPS interrupts */
728 ifx_mps_disable_all_int ();
729 --- a/src/drv_vmmc_ioctl.c
730 +++ b/src/drv_vmmc_ioctl.c
731 @@ -18,6 +18,7 @@
732 /* Includes */
733 /* ============================= */
734 #include "drv_api.h"
735 +#include "drv_vmmc_init.h"
736 #include "drv_vmmc_api.h"
737 #include "drv_vmmc_bbd.h"
738