package/uboot-lantiq/files/board/arcadyan/ddr_settings_qimonda.h

   1 /* Settings for Denali DDR SDRAM controller */
   2 /* Optimise for DDR PSC A3S12D40ETP for arv4518pw Danube Board DDR 166 Mhz - by Ngp 14th Sept. 2010 */
   3
   4 #define MC_DC0_VALUE    0x1B1B
   5 #define MC_DC1_VALUE    0xc0
   6 #define MC_DC2_VALUE    0x0
   7 #define MC_DC3_VALUE    0x100
   8 #define MC_DC4_VALUE    0xd0f
   9 #define MC_DC5_VALUE    0x204
  10 #define MC_DC6_VALUE    0x605
  11 #define MC_DC7_VALUE    0x303
  12 #define MC_DC8_VALUE    0x102
  13 #define MC_DC9_VALUE    0x70a
  14 #define MC_DC10_VALUE   0x203
  15 #define MC_DC11_VALUE   0xc02
  16 #define MC_DC12_VALUE   0x1C8
  17 #define MC_DC13_VALUE   0x1
  18 #define MC_DC14_VALUE   0x0
  19 #define MC_DC15_VALUE   0xf3c  /* WDQS tuning for clk_wr*/
  20 #define MC_DC16_VALUE   0xC800
  21 #define MC_DC17_VALUE   0xd
  22 #define MC_DC18_VALUE   0x300
  23 #define MC_DC19_VALUE   0x200
  24 #define MC_DC20_VALUE   0xA04  /* A04 for reference board, A03 for Eval board */
  25 #define MC_DC21_VALUE   0xd47
  26 #define MC_DC22_VALUE   0xd0d
  27 #define MC_DC23_VALUE   0x0
  28 #define MC_DC24_VALUE   0x62  /* WDQS Tuning for DQS */
  29 #define MC_DC25_VALUE   0x0
  30 #define MC_DC26_VALUE   0x0
  31 #define MC_DC27_VALUE   0x2040
  32 #define MC_DC28_VALUE   0x510
  33 #define MC_DC29_VALUE   0x2d89
  34 #define MC_DC30_VALUE   0x8300
  35 #define MC_DC31_VALUE   0x0
  36 #define MC_DC32_VALUE   0x0
  37 #define MC_DC33_VALUE   0x0
  38 #define MC_DC34_VALUE   0x0
  39 #define MC_DC35_VALUE   0x0
  40 #define MC_DC36_VALUE   0x0
  41 #define MC_DC37_VALUE   0x0
  42 #define MC_DC38_VALUE   0x0
  43 #define MC_DC39_VALUE   0x0
  44 #define MC_DC40_VALUE   0x0
  45 #define MC_DC41_VALUE   0x0
  46 #define MC_DC42_VALUE   0x0
  47 #define MC_DC43_VALUE   0x0
  48 #define MC_DC44_VALUE   0x0
  49 #define MC_DC45_VALUE   0x500
  50 #define MC_DC46_VALUE   0x0